1 //===-- ARMInstPrinter.cpp - Convert ARM MCInst to assembly syntax --------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This class prints an ARM MCInst to a .s file.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "asm-printer"
15 #include "ARMInstPrinter.h"
16 #include "MCTargetDesc/ARMBaseInfo.h"
17 #include "MCTargetDesc/ARMAddressingModes.h"
18 #include "llvm/MC/MCInst.h"
19 #include "llvm/MC/MCAsmInfo.h"
20 #include "llvm/MC/MCExpr.h"
21 #include "llvm/ADT/StringExtras.h"
22 #include "llvm/Support/raw_ostream.h"
25 #define GET_INSTRUCTION_NAME
26 #include "ARMGenAsmWriter.inc"
28 /// translateShiftImm - Convert shift immediate from 0-31 to 1-32 for printing.
30 /// getSORegOffset returns an integer from 0-31, but '0' should actually be printed
31 /// 32 as the immediate shouldbe within the range 1-32.
32 static unsigned translateShiftImm(unsigned imm) {
39 ARMInstPrinter::ARMInstPrinter(const MCAsmInfo &MAI,
40 const MCSubtargetInfo &STI) :
42 // Initialize the set of available features.
43 setAvailableFeatures(STI.getFeatureBits());
46 StringRef ARMInstPrinter::getOpcodeName(unsigned Opcode) const {
47 return getInstructionName(Opcode);
50 void ARMInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
51 OS << getRegisterName(RegNo);
54 void ARMInstPrinter::printInst(const MCInst *MI, raw_ostream &O) {
55 unsigned Opcode = MI->getOpcode();
57 // Check for MOVs and print canonical forms, instead.
58 if (Opcode == ARM::MOVsr) {
59 // FIXME: Thumb variants?
60 const MCOperand &Dst = MI->getOperand(0);
61 const MCOperand &MO1 = MI->getOperand(1);
62 const MCOperand &MO2 = MI->getOperand(2);
63 const MCOperand &MO3 = MI->getOperand(3);
65 O << '\t' << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO3.getImm()));
66 printSBitModifierOperand(MI, 6, O);
67 printPredicateOperand(MI, 4, O);
69 O << '\t' << getRegisterName(Dst.getReg())
70 << ", " << getRegisterName(MO1.getReg());
72 O << ", " << getRegisterName(MO2.getReg());
73 assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0);
75 if (CommentStream) printAnnotations(MI, *CommentStream);
80 if (Opcode == ARM::MOVsi) {
81 // FIXME: Thumb variants?
82 const MCOperand &Dst = MI->getOperand(0);
83 const MCOperand &MO1 = MI->getOperand(1);
84 const MCOperand &MO2 = MI->getOperand(2);
86 O << '\t' << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO2.getImm()));
87 printSBitModifierOperand(MI, 5, O);
88 printPredicateOperand(MI, 3, O);
90 O << '\t' << getRegisterName(Dst.getReg())
91 << ", " << getRegisterName(MO1.getReg());
93 if (ARM_AM::getSORegShOp(MO2.getImm()) == ARM_AM::rrx) {
94 if (CommentStream) printAnnotations(MI, *CommentStream);
98 O << ", #" << translateShiftImm(ARM_AM::getSORegOffset(MO2.getImm()));
100 if (CommentStream) printAnnotations(MI, *CommentStream);
106 if ((Opcode == ARM::STMDB_UPD || Opcode == ARM::t2STMDB_UPD) &&
107 MI->getOperand(0).getReg() == ARM::SP) {
109 printPredicateOperand(MI, 2, O);
110 if (Opcode == ARM::t2STMDB_UPD)
113 printRegisterList(MI, 4, O);
114 if (CommentStream) printAnnotations(MI, *CommentStream);
117 if (Opcode == ARM::STR_PRE_IMM && MI->getOperand(2).getReg() == ARM::SP &&
118 MI->getOperand(3).getImm() == -4) {
120 printPredicateOperand(MI, 4, O);
121 O << "\t{" << getRegisterName(MI->getOperand(1).getReg()) << "}";
122 if (CommentStream) printAnnotations(MI, *CommentStream);
127 if ((Opcode == ARM::LDMIA_UPD || Opcode == ARM::t2LDMIA_UPD) &&
128 MI->getOperand(0).getReg() == ARM::SP) {
130 printPredicateOperand(MI, 2, O);
131 if (Opcode == ARM::t2LDMIA_UPD)
134 printRegisterList(MI, 4, O);
135 if (CommentStream) printAnnotations(MI, *CommentStream);
138 if (Opcode == ARM::LDR_POST_IMM && MI->getOperand(2).getReg() == ARM::SP &&
139 MI->getOperand(4).getImm() == 4) {
141 printPredicateOperand(MI, 5, O);
142 O << "\t{" << getRegisterName(MI->getOperand(0).getReg()) << "}";
143 if (CommentStream) printAnnotations(MI, *CommentStream);
149 if ((Opcode == ARM::VSTMSDB_UPD || Opcode == ARM::VSTMDDB_UPD) &&
150 MI->getOperand(0).getReg() == ARM::SP) {
151 O << '\t' << "vpush";
152 printPredicateOperand(MI, 2, O);
154 printRegisterList(MI, 4, O);
155 if (CommentStream) printAnnotations(MI, *CommentStream);
160 if ((Opcode == ARM::VLDMSIA_UPD || Opcode == ARM::VLDMDIA_UPD) &&
161 MI->getOperand(0).getReg() == ARM::SP) {
163 printPredicateOperand(MI, 2, O);
165 printRegisterList(MI, 4, O);
166 if (CommentStream) printAnnotations(MI, *CommentStream);
170 if (Opcode == ARM::tLDMIA) {
171 bool Writeback = true;
172 unsigned BaseReg = MI->getOperand(0).getReg();
173 for (unsigned i = 3; i < MI->getNumOperands(); ++i) {
174 if (MI->getOperand(i).getReg() == BaseReg)
180 printPredicateOperand(MI, 1, O);
181 O << '\t' << getRegisterName(BaseReg);
182 if (Writeback) O << "!";
184 printRegisterList(MI, 3, O);
185 if (CommentStream) printAnnotations(MI, *CommentStream);
190 if (Opcode == ARM::tMOVr && MI->getOperand(0).getReg() == ARM::R8 &&
191 MI->getOperand(1).getReg() == ARM::R8) {
193 printPredicateOperand(MI, 2, O);
194 if (CommentStream) printAnnotations(MI, *CommentStream);
198 printInstruction(MI, O);
199 if (CommentStream) printAnnotations(MI, *CommentStream);
202 void ARMInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
204 const MCOperand &Op = MI->getOperand(OpNo);
206 unsigned Reg = Op.getReg();
207 O << getRegisterName(Reg);
208 } else if (Op.isImm()) {
209 O << '#' << Op.getImm();
211 assert(Op.isExpr() && "unknown operand kind in printOperand");
216 // so_reg is a 4-operand unit corresponding to register forms of the A5.1
217 // "Addressing Mode 1 - Data-processing operands" forms. This includes:
219 // REG REG 0,SH_OPC - e.g. R5, ROR R3
220 // REG 0 IMM,SH_OPC - e.g. R5, LSL #3
221 void ARMInstPrinter::printSORegRegOperand(const MCInst *MI, unsigned OpNum,
223 const MCOperand &MO1 = MI->getOperand(OpNum);
224 const MCOperand &MO2 = MI->getOperand(OpNum+1);
225 const MCOperand &MO3 = MI->getOperand(OpNum+2);
227 O << getRegisterName(MO1.getReg());
229 // Print the shift opc.
230 ARM_AM::ShiftOpc ShOpc = ARM_AM::getSORegShOp(MO3.getImm());
231 O << ", " << ARM_AM::getShiftOpcStr(ShOpc);
232 if (ShOpc == ARM_AM::rrx)
235 O << ' ' << getRegisterName(MO2.getReg());
236 assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0);
239 void ARMInstPrinter::printSORegImmOperand(const MCInst *MI, unsigned OpNum,
241 const MCOperand &MO1 = MI->getOperand(OpNum);
242 const MCOperand &MO2 = MI->getOperand(OpNum+1);
244 O << getRegisterName(MO1.getReg());
246 // Print the shift opc.
247 ARM_AM::ShiftOpc ShOpc = ARM_AM::getSORegShOp(MO2.getImm());
248 O << ", " << ARM_AM::getShiftOpcStr(ShOpc);
249 if (ShOpc == ARM_AM::rrx)
251 O << " #" << translateShiftImm(ARM_AM::getSORegOffset(MO2.getImm()));
255 //===--------------------------------------------------------------------===//
256 // Addressing Mode #2
257 //===--------------------------------------------------------------------===//
259 void ARMInstPrinter::printAM2PreOrOffsetIndexOp(const MCInst *MI, unsigned Op,
261 const MCOperand &MO1 = MI->getOperand(Op);
262 const MCOperand &MO2 = MI->getOperand(Op+1);
263 const MCOperand &MO3 = MI->getOperand(Op+2);
265 O << "[" << getRegisterName(MO1.getReg());
268 if (ARM_AM::getAM2Offset(MO3.getImm())) // Don't print +0.
270 << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm()))
271 << ARM_AM::getAM2Offset(MO3.getImm());
277 << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm()))
278 << getRegisterName(MO2.getReg());
280 if (unsigned ShImm = ARM_AM::getAM2Offset(MO3.getImm()))
282 << ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO3.getImm()))
287 void ARMInstPrinter::printAM2PostIndexOp(const MCInst *MI, unsigned Op,
289 const MCOperand &MO1 = MI->getOperand(Op);
290 const MCOperand &MO2 = MI->getOperand(Op+1);
291 const MCOperand &MO3 = MI->getOperand(Op+2);
293 O << "[" << getRegisterName(MO1.getReg()) << "], ";
296 unsigned ImmOffs = ARM_AM::getAM2Offset(MO3.getImm());
298 << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm()))
303 O << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm()))
304 << getRegisterName(MO2.getReg());
306 if (unsigned ShImm = ARM_AM::getAM2Offset(MO3.getImm()))
308 << ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO3.getImm()))
312 void ARMInstPrinter::printAddrMode2Operand(const MCInst *MI, unsigned Op,
314 const MCOperand &MO1 = MI->getOperand(Op);
316 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
317 printOperand(MI, Op, O);
321 const MCOperand &MO3 = MI->getOperand(Op+2);
322 unsigned IdxMode = ARM_AM::getAM2IdxMode(MO3.getImm());
324 if (IdxMode == ARMII::IndexModePost) {
325 printAM2PostIndexOp(MI, Op, O);
328 printAM2PreOrOffsetIndexOp(MI, Op, O);
331 void ARMInstPrinter::printAddrMode2OffsetOperand(const MCInst *MI,
334 const MCOperand &MO1 = MI->getOperand(OpNum);
335 const MCOperand &MO2 = MI->getOperand(OpNum+1);
338 unsigned ImmOffs = ARM_AM::getAM2Offset(MO2.getImm());
340 << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO2.getImm()))
345 O << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO2.getImm()))
346 << getRegisterName(MO1.getReg());
348 if (unsigned ShImm = ARM_AM::getAM2Offset(MO2.getImm()))
350 << ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO2.getImm()))
354 //===--------------------------------------------------------------------===//
355 // Addressing Mode #3
356 //===--------------------------------------------------------------------===//
358 void ARMInstPrinter::printAM3PostIndexOp(const MCInst *MI, unsigned Op,
360 const MCOperand &MO1 = MI->getOperand(Op);
361 const MCOperand &MO2 = MI->getOperand(Op+1);
362 const MCOperand &MO3 = MI->getOperand(Op+2);
364 O << "[" << getRegisterName(MO1.getReg()) << "], ";
367 O << (char)ARM_AM::getAM3Op(MO3.getImm())
368 << getRegisterName(MO2.getReg());
372 unsigned ImmOffs = ARM_AM::getAM3Offset(MO3.getImm());
374 << ARM_AM::getAddrOpcStr(ARM_AM::getAM3Op(MO3.getImm()))
378 void ARMInstPrinter::printAM3PreOrOffsetIndexOp(const MCInst *MI, unsigned Op,
380 const MCOperand &MO1 = MI->getOperand(Op);
381 const MCOperand &MO2 = MI->getOperand(Op+1);
382 const MCOperand &MO3 = MI->getOperand(Op+2);
384 O << '[' << getRegisterName(MO1.getReg());
387 O << ", " << getAddrOpcStr(ARM_AM::getAM3Op(MO3.getImm()))
388 << getRegisterName(MO2.getReg()) << ']';
392 if (unsigned ImmOffs = ARM_AM::getAM3Offset(MO3.getImm()))
394 << ARM_AM::getAddrOpcStr(ARM_AM::getAM3Op(MO3.getImm()))
399 void ARMInstPrinter::printAddrMode3Operand(const MCInst *MI, unsigned Op,
401 const MCOperand &MO3 = MI->getOperand(Op+2);
402 unsigned IdxMode = ARM_AM::getAM3IdxMode(MO3.getImm());
404 if (IdxMode == ARMII::IndexModePost) {
405 printAM3PostIndexOp(MI, Op, O);
408 printAM3PreOrOffsetIndexOp(MI, Op, O);
411 void ARMInstPrinter::printAddrMode3OffsetOperand(const MCInst *MI,
414 const MCOperand &MO1 = MI->getOperand(OpNum);
415 const MCOperand &MO2 = MI->getOperand(OpNum+1);
418 O << getAddrOpcStr(ARM_AM::getAM3Op(MO2.getImm()))
419 << getRegisterName(MO1.getReg());
423 unsigned ImmOffs = ARM_AM::getAM3Offset(MO2.getImm());
425 << ARM_AM::getAddrOpcStr(ARM_AM::getAM3Op(MO2.getImm()))
429 void ARMInstPrinter::printPostIdxImm8Operand(const MCInst *MI,
432 const MCOperand &MO = MI->getOperand(OpNum);
433 unsigned Imm = MO.getImm();
434 O << '#' << ((Imm & 256) ? "" : "-") << (Imm & 0xff);
437 void ARMInstPrinter::printPostIdxRegOperand(const MCInst *MI, unsigned OpNum,
439 const MCOperand &MO1 = MI->getOperand(OpNum);
440 const MCOperand &MO2 = MI->getOperand(OpNum+1);
442 O << (MO2.getImm() ? "" : "-") << getRegisterName(MO1.getReg());
445 void ARMInstPrinter::printPostIdxImm8s4Operand(const MCInst *MI,
448 const MCOperand &MO = MI->getOperand(OpNum);
449 unsigned Imm = MO.getImm();
450 O << '#' << ((Imm & 256) ? "" : "-") << ((Imm & 0xff) << 2);
454 void ARMInstPrinter::printLdStmModeOperand(const MCInst *MI, unsigned OpNum,
456 ARM_AM::AMSubMode Mode = ARM_AM::getAM4SubMode(MI->getOperand(OpNum)
458 O << ARM_AM::getAMSubModeStr(Mode);
461 void ARMInstPrinter::printAddrMode5Operand(const MCInst *MI, unsigned OpNum,
463 const MCOperand &MO1 = MI->getOperand(OpNum);
464 const MCOperand &MO2 = MI->getOperand(OpNum+1);
466 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
467 printOperand(MI, OpNum, O);
471 O << "[" << getRegisterName(MO1.getReg());
473 unsigned ImmOffs = ARM_AM::getAM5Offset(MO2.getImm());
474 unsigned Op = ARM_AM::getAM5Op(MO2.getImm());
475 if (ImmOffs || Op == ARM_AM::sub) {
477 << ARM_AM::getAddrOpcStr(ARM_AM::getAM5Op(MO2.getImm()))
483 void ARMInstPrinter::printAddrMode6Operand(const MCInst *MI, unsigned OpNum,
485 const MCOperand &MO1 = MI->getOperand(OpNum);
486 const MCOperand &MO2 = MI->getOperand(OpNum+1);
488 O << "[" << getRegisterName(MO1.getReg());
490 // FIXME: Both darwin as and GNU as violate ARM docs here.
491 O << ", :" << (MO2.getImm() << 3);
496 void ARMInstPrinter::printAddrMode7Operand(const MCInst *MI, unsigned OpNum,
498 const MCOperand &MO1 = MI->getOperand(OpNum);
499 O << "[" << getRegisterName(MO1.getReg()) << "]";
502 void ARMInstPrinter::printAddrMode6OffsetOperand(const MCInst *MI,
505 const MCOperand &MO = MI->getOperand(OpNum);
506 if (MO.getReg() == 0)
509 O << ", " << getRegisterName(MO.getReg());
512 void ARMInstPrinter::printBitfieldInvMaskImmOperand(const MCInst *MI,
515 const MCOperand &MO = MI->getOperand(OpNum);
516 uint32_t v = ~MO.getImm();
517 int32_t lsb = CountTrailingZeros_32(v);
518 int32_t width = (32 - CountLeadingZeros_32 (v)) - lsb;
519 assert(MO.isImm() && "Not a valid bf_inv_mask_imm value!");
520 O << '#' << lsb << ", #" << width;
523 void ARMInstPrinter::printMemBOption(const MCInst *MI, unsigned OpNum,
525 unsigned val = MI->getOperand(OpNum).getImm();
526 O << ARM_MB::MemBOptToString(val);
529 void ARMInstPrinter::printShiftImmOperand(const MCInst *MI, unsigned OpNum,
531 unsigned ShiftOp = MI->getOperand(OpNum).getImm();
532 bool isASR = (ShiftOp & (1 << 5)) != 0;
533 unsigned Amt = ShiftOp & 0x1f;
535 O << ", asr #" << (Amt == 0 ? 32 : Amt);
537 O << ", lsl #" << Amt;
540 void ARMInstPrinter::printPKHLSLShiftImm(const MCInst *MI, unsigned OpNum,
542 unsigned Imm = MI->getOperand(OpNum).getImm();
545 assert(Imm > 0 && Imm < 32 && "Invalid PKH shift immediate value!");
546 O << ", lsl #" << Imm;
549 void ARMInstPrinter::printPKHASRShiftImm(const MCInst *MI, unsigned OpNum,
551 unsigned Imm = MI->getOperand(OpNum).getImm();
552 // A shift amount of 32 is encoded as 0.
555 assert(Imm > 0 && Imm <= 32 && "Invalid PKH shift immediate value!");
556 O << ", asr #" << Imm;
559 void ARMInstPrinter::printRegisterList(const MCInst *MI, unsigned OpNum,
562 for (unsigned i = OpNum, e = MI->getNumOperands(); i != e; ++i) {
563 if (i != OpNum) O << ", ";
564 O << getRegisterName(MI->getOperand(i).getReg());
569 void ARMInstPrinter::printSetendOperand(const MCInst *MI, unsigned OpNum,
571 const MCOperand &Op = MI->getOperand(OpNum);
578 void ARMInstPrinter::printCPSIMod(const MCInst *MI, unsigned OpNum,
580 const MCOperand &Op = MI->getOperand(OpNum);
581 O << ARM_PROC::IModToString(Op.getImm());
584 void ARMInstPrinter::printCPSIFlag(const MCInst *MI, unsigned OpNum,
586 const MCOperand &Op = MI->getOperand(OpNum);
587 unsigned IFlags = Op.getImm();
588 for (int i=2; i >= 0; --i)
589 if (IFlags & (1 << i))
590 O << ARM_PROC::IFlagsToString(1 << i);
593 void ARMInstPrinter::printMSRMaskOperand(const MCInst *MI, unsigned OpNum,
595 const MCOperand &Op = MI->getOperand(OpNum);
596 unsigned SpecRegRBit = Op.getImm() >> 4;
597 unsigned Mask = Op.getImm() & 0xf;
599 // As special cases, CPSR_f, CPSR_s and CPSR_fs prefer printing as
600 // APSR_nzcvq, APSR_g and APSRnzcvqg, respectively.
601 if (!SpecRegRBit && (Mask == 8 || Mask == 4 || Mask == 12)) {
605 case 4: O << "g"; return;
606 case 8: O << "nzcvq"; return;
607 case 12: O << "nzcvqg"; return;
609 llvm_unreachable("Unexpected mask value!");
619 if (Mask & 8) O << 'f';
620 if (Mask & 4) O << 's';
621 if (Mask & 2) O << 'x';
622 if (Mask & 1) O << 'c';
626 void ARMInstPrinter::printPredicateOperand(const MCInst *MI, unsigned OpNum,
628 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
630 O << ARMCondCodeToString(CC);
633 void ARMInstPrinter::printMandatoryPredicateOperand(const MCInst *MI,
636 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
637 O << ARMCondCodeToString(CC);
640 void ARMInstPrinter::printSBitModifierOperand(const MCInst *MI, unsigned OpNum,
642 if (MI->getOperand(OpNum).getReg()) {
643 assert(MI->getOperand(OpNum).getReg() == ARM::CPSR &&
644 "Expect ARM CPSR register!");
649 void ARMInstPrinter::printNoHashImmediate(const MCInst *MI, unsigned OpNum,
651 O << MI->getOperand(OpNum).getImm();
654 void ARMInstPrinter::printPImmediate(const MCInst *MI, unsigned OpNum,
656 O << "p" << MI->getOperand(OpNum).getImm();
659 void ARMInstPrinter::printCImmediate(const MCInst *MI, unsigned OpNum,
661 O << "c" << MI->getOperand(OpNum).getImm();
664 void ARMInstPrinter::printPCLabel(const MCInst *MI, unsigned OpNum,
666 llvm_unreachable("Unhandled PC-relative pseudo-instruction!");
669 void ARMInstPrinter::printThumbS4ImmOperand(const MCInst *MI, unsigned OpNum,
671 O << "#" << MI->getOperand(OpNum).getImm() * 4;
674 void ARMInstPrinter::printThumbSRImm(const MCInst *MI, unsigned OpNum,
676 unsigned Imm = MI->getOperand(OpNum).getImm();
677 O << "#" << (Imm == 0 ? 32 : Imm);
680 void ARMInstPrinter::printThumbITMask(const MCInst *MI, unsigned OpNum,
682 // (3 - the number of trailing zeros) is the number of then / else.
683 unsigned Mask = MI->getOperand(OpNum).getImm();
684 unsigned CondBit0 = Mask >> 4 & 1;
685 unsigned NumTZ = CountTrailingZeros_32(Mask);
686 assert(NumTZ <= 3 && "Invalid IT mask!");
687 for (unsigned Pos = 3, e = NumTZ; Pos > e; --Pos) {
688 bool T = ((Mask >> Pos) & 1) == CondBit0;
696 void ARMInstPrinter::printThumbAddrModeRROperand(const MCInst *MI, unsigned Op,
698 const MCOperand &MO1 = MI->getOperand(Op);
699 const MCOperand &MO2 = MI->getOperand(Op + 1);
701 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
702 printOperand(MI, Op, O);
706 O << "[" << getRegisterName(MO1.getReg());
707 if (unsigned RegNum = MO2.getReg())
708 O << ", " << getRegisterName(RegNum);
712 void ARMInstPrinter::printThumbAddrModeImm5SOperand(const MCInst *MI,
716 const MCOperand &MO1 = MI->getOperand(Op);
717 const MCOperand &MO2 = MI->getOperand(Op + 1);
719 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
720 printOperand(MI, Op, O);
724 O << "[" << getRegisterName(MO1.getReg());
725 if (unsigned ImmOffs = MO2.getImm())
726 O << ", #" << ImmOffs * Scale;
730 void ARMInstPrinter::printThumbAddrModeImm5S1Operand(const MCInst *MI,
733 printThumbAddrModeImm5SOperand(MI, Op, O, 1);
736 void ARMInstPrinter::printThumbAddrModeImm5S2Operand(const MCInst *MI,
739 printThumbAddrModeImm5SOperand(MI, Op, O, 2);
742 void ARMInstPrinter::printThumbAddrModeImm5S4Operand(const MCInst *MI,
745 printThumbAddrModeImm5SOperand(MI, Op, O, 4);
748 void ARMInstPrinter::printThumbAddrModeSPOperand(const MCInst *MI, unsigned Op,
750 printThumbAddrModeImm5SOperand(MI, Op, O, 4);
753 // Constant shifts t2_so_reg is a 2-operand unit corresponding to the Thumb2
754 // register with shift forms.
756 // REG IMM, SH_OPC - e.g. R5, LSL #3
757 void ARMInstPrinter::printT2SOOperand(const MCInst *MI, unsigned OpNum,
759 const MCOperand &MO1 = MI->getOperand(OpNum);
760 const MCOperand &MO2 = MI->getOperand(OpNum+1);
762 unsigned Reg = MO1.getReg();
763 O << getRegisterName(Reg);
765 // Print the shift opc.
766 assert(MO2.isImm() && "Not a valid t2_so_reg value!");
767 ARM_AM::ShiftOpc ShOpc = ARM_AM::getSORegShOp(MO2.getImm());
768 O << ", " << ARM_AM::getShiftOpcStr(ShOpc);
769 if (ShOpc != ARM_AM::rrx)
770 O << " #" << translateShiftImm(ARM_AM::getSORegOffset(MO2.getImm()));
773 void ARMInstPrinter::printAddrModeImm12Operand(const MCInst *MI, unsigned OpNum,
775 const MCOperand &MO1 = MI->getOperand(OpNum);
776 const MCOperand &MO2 = MI->getOperand(OpNum+1);
778 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
779 printOperand(MI, OpNum, O);
783 O << "[" << getRegisterName(MO1.getReg());
785 int32_t OffImm = (int32_t)MO2.getImm();
786 bool isSub = OffImm < 0;
787 // Special value for #-0. All others are normal.
788 if (OffImm == INT32_MIN)
791 O << ", #-" << -OffImm;
793 O << ", #" << OffImm;
797 void ARMInstPrinter::printT2AddrModeImm8Operand(const MCInst *MI,
800 const MCOperand &MO1 = MI->getOperand(OpNum);
801 const MCOperand &MO2 = MI->getOperand(OpNum+1);
803 O << "[" << getRegisterName(MO1.getReg());
805 int32_t OffImm = (int32_t)MO2.getImm();
808 O << ", #-" << -OffImm;
810 O << ", #" << OffImm;
814 void ARMInstPrinter::printT2AddrModeImm8s4Operand(const MCInst *MI,
817 const MCOperand &MO1 = MI->getOperand(OpNum);
818 const MCOperand &MO2 = MI->getOperand(OpNum+1);
820 O << "[" << getRegisterName(MO1.getReg());
822 int32_t OffImm = (int32_t)MO2.getImm() / 4;
825 O << ", #-" << -OffImm * 4;
827 O << ", #" << OffImm * 4;
831 void ARMInstPrinter::printT2AddrModeImm0_1020s4Operand(const MCInst *MI,
834 const MCOperand &MO1 = MI->getOperand(OpNum);
835 const MCOperand &MO2 = MI->getOperand(OpNum+1);
837 O << "[" << getRegisterName(MO1.getReg());
839 O << ", #" << MO2.getImm() * 4;
843 void ARMInstPrinter::printT2AddrModeImm8OffsetOperand(const MCInst *MI,
846 const MCOperand &MO1 = MI->getOperand(OpNum);
847 int32_t OffImm = (int32_t)MO1.getImm();
850 O << "#-" << -OffImm;
855 void ARMInstPrinter::printT2AddrModeImm8s4OffsetOperand(const MCInst *MI,
858 const MCOperand &MO1 = MI->getOperand(OpNum);
859 int32_t OffImm = (int32_t)MO1.getImm() / 4;
864 O << "#-" << -OffImm * 4;
866 O << "#" << OffImm * 4;
870 void ARMInstPrinter::printT2AddrModeSoRegOperand(const MCInst *MI,
873 const MCOperand &MO1 = MI->getOperand(OpNum);
874 const MCOperand &MO2 = MI->getOperand(OpNum+1);
875 const MCOperand &MO3 = MI->getOperand(OpNum+2);
877 O << "[" << getRegisterName(MO1.getReg());
879 assert(MO2.getReg() && "Invalid so_reg load / store address!");
880 O << ", " << getRegisterName(MO2.getReg());
882 unsigned ShAmt = MO3.getImm();
884 assert(ShAmt <= 3 && "Not a valid Thumb2 addressing mode!");
885 O << ", lsl #" << ShAmt;
890 void ARMInstPrinter::printVFPf32ImmOperand(const MCInst *MI, unsigned OpNum,
892 const MCOperand &MO = MI->getOperand(OpNum);
895 O << (float)MO.getFPImm();
902 FPUnion.I = MO.getImm();
907 void ARMInstPrinter::printVFPf64ImmOperand(const MCInst *MI, unsigned OpNum,
909 const MCOperand &MO = MI->getOperand(OpNum);
914 // We expect the binary encoding of a floating point number here.
920 FPUnion.I = MO.getImm();
925 void ARMInstPrinter::printNEONModImmOperand(const MCInst *MI, unsigned OpNum,
927 unsigned EncodedImm = MI->getOperand(OpNum).getImm();
929 uint64_t Val = ARM_AM::decodeNEONModImm(EncodedImm, EltBits);
930 O << "#0x" << utohexstr(Val);
933 void ARMInstPrinter::printImmPlusOneOperand(const MCInst *MI, unsigned OpNum,
935 unsigned Imm = MI->getOperand(OpNum).getImm();
939 void ARMInstPrinter::printRotImmOperand(const MCInst *MI, unsigned OpNum,
941 unsigned Imm = MI->getOperand(OpNum).getImm();
946 default: assert (0 && "illegal ror immediate!");
947 case 1: O << "8"; break;
948 case 2: O << "16"; break;
949 case 3: O << "24"; break;