1 //===-- ARMInstPrinter.cpp - Convert ARM MCInst to assembly syntax --------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This class prints an ARM MCInst to a .s file.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "asm-printer"
15 #include "ARMInstPrinter.h"
16 #include "MCTargetDesc/ARMAddressingModes.h"
17 #include "MCTargetDesc/ARMBaseInfo.h"
18 #include "llvm/MC/MCAsmInfo.h"
19 #include "llvm/MC/MCExpr.h"
20 #include "llvm/MC/MCInst.h"
21 #include "llvm/MC/MCInstrInfo.h"
22 #include "llvm/MC/MCRegisterInfo.h"
23 #include "llvm/Support/raw_ostream.h"
26 #include "ARMGenAsmWriter.inc"
28 /// translateShiftImm - Convert shift immediate from 0-31 to 1-32 for printing.
30 /// getSORegOffset returns an integer from 0-31, representing '32' as 0.
31 static unsigned translateShiftImm(unsigned imm) {
32 // lsr #32 and asr #32 exist, but should be encoded as a 0.
33 assert((imm & ~0x1f) == 0 && "Invalid shift encoding");
40 /// Prints the shift value with an immediate value.
41 static void printRegImmShift(raw_ostream &O, ARM_AM::ShiftOpc ShOpc,
42 unsigned ShImm, bool UseMarkup) {
43 if (ShOpc == ARM_AM::no_shift || (ShOpc == ARM_AM::lsl && !ShImm))
47 assert (!(ShOpc == ARM_AM::ror && !ShImm) && "Cannot have ror #0");
48 O << getShiftOpcStr(ShOpc);
50 if (ShOpc != ARM_AM::rrx) {
54 O << "#" << translateShiftImm(ShImm);
60 ARMInstPrinter::ARMInstPrinter(const MCAsmInfo &MAI,
61 const MCInstrInfo &MII,
62 const MCRegisterInfo &MRI,
63 const MCSubtargetInfo &STI) :
64 MCInstPrinter(MAI, MII, MRI) {
65 // Initialize the set of available features.
66 setAvailableFeatures(STI.getFeatureBits());
69 void ARMInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
71 << getRegisterName(RegNo)
75 void ARMInstPrinter::printInst(const MCInst *MI, raw_ostream &O,
77 unsigned Opcode = MI->getOpcode();
79 // Check for HINT instructions w/ canonical names.
80 if (Opcode == ARM::HINT || Opcode == ARM::t2HINT) {
81 switch (MI->getOperand(0).getImm()) {
82 case 0: O << "\tnop"; break;
83 case 1: O << "\tyield"; break;
84 case 2: O << "\twfe"; break;
85 case 3: O << "\twfi"; break;
86 case 4: O << "\tsev"; break;
88 // Anything else should just print normally.
89 printInstruction(MI, O);
90 printAnnotation(O, Annot);
93 printPredicateOperand(MI, 1, O);
94 if (Opcode == ARM::t2HINT)
96 printAnnotation(O, Annot);
100 // Check for MOVs and print canonical forms, instead.
101 if (Opcode == ARM::MOVsr) {
102 // FIXME: Thumb variants?
103 const MCOperand &Dst = MI->getOperand(0);
104 const MCOperand &MO1 = MI->getOperand(1);
105 const MCOperand &MO2 = MI->getOperand(2);
106 const MCOperand &MO3 = MI->getOperand(3);
108 O << '\t' << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO3.getImm()));
109 printSBitModifierOperand(MI, 6, O);
110 printPredicateOperand(MI, 4, O);
113 printRegName(O, Dst.getReg());
115 printRegName(O, MO1.getReg());
118 printRegName(O, MO2.getReg());
119 assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0);
120 printAnnotation(O, Annot);
124 if (Opcode == ARM::MOVsi) {
125 // FIXME: Thumb variants?
126 const MCOperand &Dst = MI->getOperand(0);
127 const MCOperand &MO1 = MI->getOperand(1);
128 const MCOperand &MO2 = MI->getOperand(2);
130 O << '\t' << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO2.getImm()));
131 printSBitModifierOperand(MI, 5, O);
132 printPredicateOperand(MI, 3, O);
135 printRegName(O, Dst.getReg());
137 printRegName(O, MO1.getReg());
139 if (ARM_AM::getSORegShOp(MO2.getImm()) == ARM_AM::rrx) {
140 printAnnotation(O, Annot);
146 << "#" << translateShiftImm(ARM_AM::getSORegOffset(MO2.getImm()))
148 printAnnotation(O, Annot);
154 if ((Opcode == ARM::STMDB_UPD || Opcode == ARM::t2STMDB_UPD) &&
155 MI->getOperand(0).getReg() == ARM::SP &&
156 MI->getNumOperands() > 5) {
157 // Should only print PUSH if there are at least two registers in the list.
159 printPredicateOperand(MI, 2, O);
160 if (Opcode == ARM::t2STMDB_UPD)
163 printRegisterList(MI, 4, O);
164 printAnnotation(O, Annot);
167 if (Opcode == ARM::STR_PRE_IMM && MI->getOperand(2).getReg() == ARM::SP &&
168 MI->getOperand(3).getImm() == -4) {
170 printPredicateOperand(MI, 4, O);
172 printRegName(O, MI->getOperand(1).getReg());
174 printAnnotation(O, Annot);
179 if ((Opcode == ARM::LDMIA_UPD || Opcode == ARM::t2LDMIA_UPD) &&
180 MI->getOperand(0).getReg() == ARM::SP &&
181 MI->getNumOperands() > 5) {
182 // Should only print POP if there are at least two registers in the list.
184 printPredicateOperand(MI, 2, O);
185 if (Opcode == ARM::t2LDMIA_UPD)
188 printRegisterList(MI, 4, O);
189 printAnnotation(O, Annot);
192 if (Opcode == ARM::LDR_POST_IMM && MI->getOperand(2).getReg() == ARM::SP &&
193 MI->getOperand(4).getImm() == 4) {
195 printPredicateOperand(MI, 5, O);
197 printRegName(O, MI->getOperand(0).getReg());
199 printAnnotation(O, Annot);
205 if ((Opcode == ARM::VSTMSDB_UPD || Opcode == ARM::VSTMDDB_UPD) &&
206 MI->getOperand(0).getReg() == ARM::SP) {
207 O << '\t' << "vpush";
208 printPredicateOperand(MI, 2, O);
210 printRegisterList(MI, 4, O);
211 printAnnotation(O, Annot);
216 if ((Opcode == ARM::VLDMSIA_UPD || Opcode == ARM::VLDMDIA_UPD) &&
217 MI->getOperand(0).getReg() == ARM::SP) {
219 printPredicateOperand(MI, 2, O);
221 printRegisterList(MI, 4, O);
222 printAnnotation(O, Annot);
226 if (Opcode == ARM::tLDMIA) {
227 bool Writeback = true;
228 unsigned BaseReg = MI->getOperand(0).getReg();
229 for (unsigned i = 3; i < MI->getNumOperands(); ++i) {
230 if (MI->getOperand(i).getReg() == BaseReg)
236 printPredicateOperand(MI, 1, O);
238 printRegName(O, BaseReg);
239 if (Writeback) O << "!";
241 printRegisterList(MI, 3, O);
242 printAnnotation(O, Annot);
246 // Combine 2 GPRs from disassember into a GPRPair to match with instr def.
247 // ldrexd/strexd require even/odd GPR pair. To enforce this constraint,
248 // a single GPRPair reg operand is used in the .td file to replace the two
249 // GPRs. However, when decoding them, the two GRPs cannot be automatically
250 // expressed as a GPRPair, so we have to manually merge them.
251 // FIXME: We would really like to be able to tablegen'erate this.
252 if (Opcode == ARM::LDREXD || Opcode == ARM::STREXD) {
253 const MCRegisterClass& MRC = MRI.getRegClass(ARM::GPRRegClassID);
254 bool isStore = Opcode == ARM::STREXD;
255 unsigned Reg = MI->getOperand(isStore ? 1 : 0).getReg();
256 if (MRC.contains(Reg)) {
259 NewMI.setOpcode(Opcode);
262 NewMI.addOperand(MI->getOperand(0));
263 NewReg = MCOperand::CreateReg(MRI.getMatchingSuperReg(Reg, ARM::gsub_0,
264 &MRI.getRegClass(ARM::GPRPairRegClassID)));
265 NewMI.addOperand(NewReg);
267 // Copy the rest operands into NewMI.
268 for(unsigned i= isStore ? 3 : 2; i < MI->getNumOperands(); ++i)
269 NewMI.addOperand(MI->getOperand(i));
270 printInstruction(&NewMI, O);
275 printInstruction(MI, O);
276 printAnnotation(O, Annot);
279 void ARMInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
281 const MCOperand &Op = MI->getOperand(OpNo);
283 unsigned Reg = Op.getReg();
284 printRegName(O, Reg);
285 } else if (Op.isImm()) {
287 << '#' << formatImm(Op.getImm())
290 assert(Op.isExpr() && "unknown operand kind in printOperand");
291 // If a symbolic branch target was added as a constant expression then print
292 // that address in hex. And only print 32 unsigned bits for the address.
293 const MCConstantExpr *BranchTarget = dyn_cast<MCConstantExpr>(Op.getExpr());
295 if (BranchTarget && BranchTarget->EvaluateAsAbsolute(Address)) {
297 O.write_hex((uint32_t)Address);
300 // Otherwise, just print the expression.
306 void ARMInstPrinter::printThumbLdrLabelOperand(const MCInst *MI, unsigned OpNum,
308 const MCOperand &MO1 = MI->getOperand(OpNum);
314 O << markup("<mem:") << "[pc, ";
316 int32_t OffImm = (int32_t)MO1.getImm();
317 bool isSub = OffImm < 0;
319 // Special value for #-0. All others are normal.
320 if (OffImm == INT32_MIN)
324 << "#-" << formatImm(-OffImm)
328 << "#" << formatImm(OffImm)
331 O << "]" << markup(">");
334 // so_reg is a 4-operand unit corresponding to register forms of the A5.1
335 // "Addressing Mode 1 - Data-processing operands" forms. This includes:
337 // REG REG 0,SH_OPC - e.g. R5, ROR R3
338 // REG 0 IMM,SH_OPC - e.g. R5, LSL #3
339 void ARMInstPrinter::printSORegRegOperand(const MCInst *MI, unsigned OpNum,
341 const MCOperand &MO1 = MI->getOperand(OpNum);
342 const MCOperand &MO2 = MI->getOperand(OpNum+1);
343 const MCOperand &MO3 = MI->getOperand(OpNum+2);
345 printRegName(O, MO1.getReg());
347 // Print the shift opc.
348 ARM_AM::ShiftOpc ShOpc = ARM_AM::getSORegShOp(MO3.getImm());
349 O << ", " << ARM_AM::getShiftOpcStr(ShOpc);
350 if (ShOpc == ARM_AM::rrx)
354 printRegName(O, MO2.getReg());
355 assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0);
358 void ARMInstPrinter::printSORegImmOperand(const MCInst *MI, unsigned OpNum,
360 const MCOperand &MO1 = MI->getOperand(OpNum);
361 const MCOperand &MO2 = MI->getOperand(OpNum+1);
363 printRegName(O, MO1.getReg());
365 // Print the shift opc.
366 printRegImmShift(O, ARM_AM::getSORegShOp(MO2.getImm()),
367 ARM_AM::getSORegOffset(MO2.getImm()), UseMarkup);
371 //===--------------------------------------------------------------------===//
372 // Addressing Mode #2
373 //===--------------------------------------------------------------------===//
375 void ARMInstPrinter::printAM2PreOrOffsetIndexOp(const MCInst *MI, unsigned Op,
377 const MCOperand &MO1 = MI->getOperand(Op);
378 const MCOperand &MO2 = MI->getOperand(Op+1);
379 const MCOperand &MO3 = MI->getOperand(Op+2);
381 O << markup("<mem:") << "[";
382 printRegName(O, MO1.getReg());
385 if (ARM_AM::getAM2Offset(MO3.getImm())) { // Don't print +0.
389 << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm()))
390 << ARM_AM::getAM2Offset(MO3.getImm())
393 O << "]" << markup(">");
398 O << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm()));
399 printRegName(O, MO2.getReg());
401 printRegImmShift(O, ARM_AM::getAM2ShiftOpc(MO3.getImm()),
402 ARM_AM::getAM2Offset(MO3.getImm()), UseMarkup);
403 O << "]" << markup(">");
406 void ARMInstPrinter::printAddrModeTBB(const MCInst *MI, unsigned Op,
408 const MCOperand &MO1 = MI->getOperand(Op);
409 const MCOperand &MO2 = MI->getOperand(Op+1);
410 O << markup("<mem:") << "[";
411 printRegName(O, MO1.getReg());
413 printRegName(O, MO2.getReg());
414 O << "]" << markup(">");
417 void ARMInstPrinter::printAddrModeTBH(const MCInst *MI, unsigned Op,
419 const MCOperand &MO1 = MI->getOperand(Op);
420 const MCOperand &MO2 = MI->getOperand(Op+1);
421 O << markup("<mem:") << "[";
422 printRegName(O, MO1.getReg());
424 printRegName(O, MO2.getReg());
425 O << ", lsl " << markup("<imm:") << "#1" << markup(">") << "]" << markup(">");
428 void ARMInstPrinter::printAddrMode2Operand(const MCInst *MI, unsigned Op,
430 const MCOperand &MO1 = MI->getOperand(Op);
432 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
433 printOperand(MI, Op, O);
438 const MCOperand &MO3 = MI->getOperand(Op+2);
439 unsigned IdxMode = ARM_AM::getAM2IdxMode(MO3.getImm());
440 assert(IdxMode != ARMII::IndexModePost &&
441 "Should be pre or offset index op");
444 printAM2PreOrOffsetIndexOp(MI, Op, O);
447 void ARMInstPrinter::printAddrMode2OffsetOperand(const MCInst *MI,
450 const MCOperand &MO1 = MI->getOperand(OpNum);
451 const MCOperand &MO2 = MI->getOperand(OpNum+1);
454 unsigned ImmOffs = ARM_AM::getAM2Offset(MO2.getImm());
456 << '#' << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO2.getImm()))
462 O << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO2.getImm()));
463 printRegName(O, MO1.getReg());
465 printRegImmShift(O, ARM_AM::getAM2ShiftOpc(MO2.getImm()),
466 ARM_AM::getAM2Offset(MO2.getImm()), UseMarkup);
469 //===--------------------------------------------------------------------===//
470 // Addressing Mode #3
471 //===--------------------------------------------------------------------===//
473 void ARMInstPrinter::printAM3PostIndexOp(const MCInst *MI, unsigned Op,
475 const MCOperand &MO1 = MI->getOperand(Op);
476 const MCOperand &MO2 = MI->getOperand(Op+1);
477 const MCOperand &MO3 = MI->getOperand(Op+2);
479 O << markup("<mem:") << "[";
480 printRegName(O, MO1.getReg());
481 O << "], " << markup(">");
484 O << (char)ARM_AM::getAM3Op(MO3.getImm());
485 printRegName(O, MO2.getReg());
489 unsigned ImmOffs = ARM_AM::getAM3Offset(MO3.getImm());
492 << ARM_AM::getAddrOpcStr(ARM_AM::getAM3Op(MO3.getImm()))
497 void ARMInstPrinter::printAM3PreOrOffsetIndexOp(const MCInst *MI, unsigned Op,
499 bool AlwaysPrintImm0) {
500 const MCOperand &MO1 = MI->getOperand(Op);
501 const MCOperand &MO2 = MI->getOperand(Op+1);
502 const MCOperand &MO3 = MI->getOperand(Op+2);
504 O << markup("<mem:") << '[';
505 printRegName(O, MO1.getReg());
508 O << ", " << getAddrOpcStr(ARM_AM::getAM3Op(MO3.getImm()));
509 printRegName(O, MO2.getReg());
510 O << ']' << markup(">");
514 //If the op is sub we have to print the immediate even if it is 0
515 unsigned ImmOffs = ARM_AM::getAM3Offset(MO3.getImm());
516 ARM_AM::AddrOpc op = ARM_AM::getAM3Op(MO3.getImm());
518 if (AlwaysPrintImm0 || ImmOffs || (op == ARM_AM::sub)) {
522 << ARM_AM::getAddrOpcStr(op)
526 O << ']' << markup(">");
529 template <bool AlwaysPrintImm0>
530 void ARMInstPrinter::printAddrMode3Operand(const MCInst *MI, unsigned Op,
532 const MCOperand &MO1 = MI->getOperand(Op);
533 if (!MO1.isReg()) { // For label symbolic references.
534 printOperand(MI, Op, O);
538 const MCOperand &MO3 = MI->getOperand(Op+2);
539 unsigned IdxMode = ARM_AM::getAM3IdxMode(MO3.getImm());
541 if (IdxMode == ARMII::IndexModePost) {
542 printAM3PostIndexOp(MI, Op, O);
545 printAM3PreOrOffsetIndexOp(MI, Op, O, AlwaysPrintImm0);
548 void ARMInstPrinter::printAddrMode3OffsetOperand(const MCInst *MI,
551 const MCOperand &MO1 = MI->getOperand(OpNum);
552 const MCOperand &MO2 = MI->getOperand(OpNum+1);
555 O << getAddrOpcStr(ARM_AM::getAM3Op(MO2.getImm()));
556 printRegName(O, MO1.getReg());
560 unsigned ImmOffs = ARM_AM::getAM3Offset(MO2.getImm());
562 << '#' << ARM_AM::getAddrOpcStr(ARM_AM::getAM3Op(MO2.getImm())) << ImmOffs
566 void ARMInstPrinter::printPostIdxImm8Operand(const MCInst *MI,
569 const MCOperand &MO = MI->getOperand(OpNum);
570 unsigned Imm = MO.getImm();
572 << '#' << ((Imm & 256) ? "" : "-") << (Imm & 0xff)
576 void ARMInstPrinter::printPostIdxRegOperand(const MCInst *MI, unsigned OpNum,
578 const MCOperand &MO1 = MI->getOperand(OpNum);
579 const MCOperand &MO2 = MI->getOperand(OpNum+1);
581 O << (MO2.getImm() ? "" : "-");
582 printRegName(O, MO1.getReg());
585 void ARMInstPrinter::printPostIdxImm8s4Operand(const MCInst *MI,
588 const MCOperand &MO = MI->getOperand(OpNum);
589 unsigned Imm = MO.getImm();
591 << '#' << ((Imm & 256) ? "" : "-") << ((Imm & 0xff) << 2)
596 void ARMInstPrinter::printLdStmModeOperand(const MCInst *MI, unsigned OpNum,
598 ARM_AM::AMSubMode Mode = ARM_AM::getAM4SubMode(MI->getOperand(OpNum)
600 O << ARM_AM::getAMSubModeStr(Mode);
603 template <bool AlwaysPrintImm0>
604 void ARMInstPrinter::printAddrMode5Operand(const MCInst *MI, unsigned OpNum,
606 const MCOperand &MO1 = MI->getOperand(OpNum);
607 const MCOperand &MO2 = MI->getOperand(OpNum+1);
609 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
610 printOperand(MI, OpNum, O);
614 O << markup("<mem:") << "[";
615 printRegName(O, MO1.getReg());
617 unsigned ImmOffs = ARM_AM::getAM5Offset(MO2.getImm());
618 unsigned Op = ARM_AM::getAM5Op(MO2.getImm());
619 if (AlwaysPrintImm0 || ImmOffs || Op == ARM_AM::sub) {
623 << ARM_AM::getAddrOpcStr(ARM_AM::getAM5Op(MO2.getImm()))
627 O << "]" << markup(">");
630 void ARMInstPrinter::printAddrMode6Operand(const MCInst *MI, unsigned OpNum,
632 const MCOperand &MO1 = MI->getOperand(OpNum);
633 const MCOperand &MO2 = MI->getOperand(OpNum+1);
635 O << markup("<mem:") << "[";
636 printRegName(O, MO1.getReg());
638 O << ":" << (MO2.getImm() << 3);
640 O << "]" << markup(">");
643 void ARMInstPrinter::printAddrMode7Operand(const MCInst *MI, unsigned OpNum,
645 const MCOperand &MO1 = MI->getOperand(OpNum);
646 O << markup("<mem:") << "[";
647 printRegName(O, MO1.getReg());
648 O << "]" << markup(">");
651 void ARMInstPrinter::printAddrMode6OffsetOperand(const MCInst *MI,
654 const MCOperand &MO = MI->getOperand(OpNum);
655 if (MO.getReg() == 0)
659 printRegName(O, MO.getReg());
663 void ARMInstPrinter::printBitfieldInvMaskImmOperand(const MCInst *MI,
666 const MCOperand &MO = MI->getOperand(OpNum);
667 uint32_t v = ~MO.getImm();
668 int32_t lsb = countTrailingZeros(v);
669 int32_t width = (32 - countLeadingZeros (v)) - lsb;
670 assert(MO.isImm() && "Not a valid bf_inv_mask_imm value!");
671 O << markup("<imm:") << '#' << lsb << markup(">")
673 << markup("<imm:") << '#' << width << markup(">");
676 void ARMInstPrinter::printMemBOption(const MCInst *MI, unsigned OpNum,
678 unsigned val = MI->getOperand(OpNum).getImm();
679 O << ARM_MB::MemBOptToString(val);
682 void ARMInstPrinter::printInstSyncBOption(const MCInst *MI, unsigned OpNum,
684 unsigned val = MI->getOperand(OpNum).getImm();
685 O << ARM_ISB::InstSyncBOptToString(val);
688 void ARMInstPrinter::printShiftImmOperand(const MCInst *MI, unsigned OpNum,
690 unsigned ShiftOp = MI->getOperand(OpNum).getImm();
691 bool isASR = (ShiftOp & (1 << 5)) != 0;
692 unsigned Amt = ShiftOp & 0x1f;
696 << "#" << (Amt == 0 ? 32 : Amt)
707 void ARMInstPrinter::printPKHLSLShiftImm(const MCInst *MI, unsigned OpNum,
709 unsigned Imm = MI->getOperand(OpNum).getImm();
712 assert(Imm > 0 && Imm < 32 && "Invalid PKH shift immediate value!");
713 O << ", lsl " << markup("<imm:") << "#" << Imm << markup(">");
716 void ARMInstPrinter::printPKHASRShiftImm(const MCInst *MI, unsigned OpNum,
718 unsigned Imm = MI->getOperand(OpNum).getImm();
719 // A shift amount of 32 is encoded as 0.
722 assert(Imm > 0 && Imm <= 32 && "Invalid PKH shift immediate value!");
723 O << ", asr " << markup("<imm:") << "#" << Imm << markup(">");
726 void ARMInstPrinter::printRegisterList(const MCInst *MI, unsigned OpNum,
729 for (unsigned i = OpNum, e = MI->getNumOperands(); i != e; ++i) {
730 if (i != OpNum) O << ", ";
731 printRegName(O, MI->getOperand(i).getReg());
736 void ARMInstPrinter::printGPRPairOperand(const MCInst *MI, unsigned OpNum,
738 unsigned Reg = MI->getOperand(OpNum).getReg();
739 printRegName(O, MRI.getSubReg(Reg, ARM::gsub_0));
741 printRegName(O, MRI.getSubReg(Reg, ARM::gsub_1));
745 void ARMInstPrinter::printSetendOperand(const MCInst *MI, unsigned OpNum,
747 const MCOperand &Op = MI->getOperand(OpNum);
754 void ARMInstPrinter::printCPSIMod(const MCInst *MI, unsigned OpNum,
756 const MCOperand &Op = MI->getOperand(OpNum);
757 O << ARM_PROC::IModToString(Op.getImm());
760 void ARMInstPrinter::printCPSIFlag(const MCInst *MI, unsigned OpNum,
762 const MCOperand &Op = MI->getOperand(OpNum);
763 unsigned IFlags = Op.getImm();
764 for (int i=2; i >= 0; --i)
765 if (IFlags & (1 << i))
766 O << ARM_PROC::IFlagsToString(1 << i);
772 void ARMInstPrinter::printMSRMaskOperand(const MCInst *MI, unsigned OpNum,
774 const MCOperand &Op = MI->getOperand(OpNum);
775 unsigned SpecRegRBit = Op.getImm() >> 4;
776 unsigned Mask = Op.getImm() & 0xf;
778 if (getAvailableFeatures() & ARM::FeatureMClass) {
779 unsigned SYSm = Op.getImm();
780 unsigned Opcode = MI->getOpcode();
781 // For reads of the special registers ignore the "mask encoding" bits
782 // which are only for writes.
783 if (Opcode == ARM::t2MRS_M)
786 default: llvm_unreachable("Unexpected mask value!");
788 case 0x800: O << "apsr"; return; // with _nzcvq bits is an alias for aspr
789 case 0x400: O << "apsr_g"; return;
790 case 0xc00: O << "apsr_nzcvqg"; return;
792 case 0x801: O << "iapsr"; return; // with _nzcvq bits is an alias for iapsr
793 case 0x401: O << "iapsr_g"; return;
794 case 0xc01: O << "iapsr_nzcvqg"; return;
796 case 0x802: O << "eapsr"; return; // with _nzcvq bits is an alias for eapsr
797 case 0x402: O << "eapsr_g"; return;
798 case 0xc02: O << "eapsr_nzcvqg"; return;
800 case 0x803: O << "xpsr"; return; // with _nzcvq bits is an alias for xpsr
801 case 0x403: O << "xpsr_g"; return;
802 case 0xc03: O << "xpsr_nzcvqg"; return;
804 case 0x805: O << "ipsr"; return;
806 case 0x806: O << "epsr"; return;
808 case 0x807: O << "iepsr"; return;
810 case 0x808: O << "msp"; return;
812 case 0x809: O << "psp"; return;
814 case 0x810: O << "primask"; return;
816 case 0x811: O << "basepri"; return;
818 case 0x812: O << "basepri_max"; return;
820 case 0x813: O << "faultmask"; return;
822 case 0x814: O << "control"; return;
826 // As special cases, CPSR_f, CPSR_s and CPSR_fs prefer printing as
827 // APSR_nzcvq, APSR_g and APSRnzcvqg, respectively.
828 if (!SpecRegRBit && (Mask == 8 || Mask == 4 || Mask == 12)) {
831 default: llvm_unreachable("Unexpected mask value!");
832 case 4: O << "g"; return;
833 case 8: O << "nzcvq"; return;
834 case 12: O << "nzcvqg"; return;
845 if (Mask & 8) O << 'f';
846 if (Mask & 4) O << 's';
847 if (Mask & 2) O << 'x';
848 if (Mask & 1) O << 'c';
852 void ARMInstPrinter::printPredicateOperand(const MCInst *MI, unsigned OpNum,
854 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
855 // Handle the undefined 15 CC value here for printing so we don't abort().
856 if ((unsigned)CC == 15)
858 else if (CC != ARMCC::AL)
859 O << ARMCondCodeToString(CC);
862 void ARMInstPrinter::printMandatoryPredicateOperand(const MCInst *MI,
865 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
866 O << ARMCondCodeToString(CC);
869 void ARMInstPrinter::printSBitModifierOperand(const MCInst *MI, unsigned OpNum,
871 if (MI->getOperand(OpNum).getReg()) {
872 assert(MI->getOperand(OpNum).getReg() == ARM::CPSR &&
873 "Expect ARM CPSR register!");
878 void ARMInstPrinter::printNoHashImmediate(const MCInst *MI, unsigned OpNum,
880 O << MI->getOperand(OpNum).getImm();
883 void ARMInstPrinter::printPImmediate(const MCInst *MI, unsigned OpNum,
885 O << "p" << MI->getOperand(OpNum).getImm();
888 void ARMInstPrinter::printCImmediate(const MCInst *MI, unsigned OpNum,
890 O << "c" << MI->getOperand(OpNum).getImm();
893 void ARMInstPrinter::printCoprocOptionImm(const MCInst *MI, unsigned OpNum,
895 O << "{" << MI->getOperand(OpNum).getImm() << "}";
898 void ARMInstPrinter::printPCLabel(const MCInst *MI, unsigned OpNum,
900 llvm_unreachable("Unhandled PC-relative pseudo-instruction!");
903 void ARMInstPrinter::printAdrLabelOperand(const MCInst *MI, unsigned OpNum,
905 const MCOperand &MO = MI->getOperand(OpNum);
912 int32_t OffImm = (int32_t)MO.getImm();
914 O << markup("<imm:");
915 if (OffImm == INT32_MIN)
918 O << "#-" << -OffImm;
924 void ARMInstPrinter::printThumbS4ImmOperand(const MCInst *MI, unsigned OpNum,
927 << "#" << formatImm(MI->getOperand(OpNum).getImm() * 4)
931 void ARMInstPrinter::printThumbSRImm(const MCInst *MI, unsigned OpNum,
933 unsigned Imm = MI->getOperand(OpNum).getImm();
935 << "#" << formatImm((Imm == 0 ? 32 : Imm))
939 void ARMInstPrinter::printThumbITMask(const MCInst *MI, unsigned OpNum,
941 // (3 - the number of trailing zeros) is the number of then / else.
942 unsigned Mask = MI->getOperand(OpNum).getImm();
943 unsigned Firstcond = MI->getOperand(OpNum-1).getImm();
944 unsigned CondBit0 = Firstcond & 1;
945 unsigned NumTZ = countTrailingZeros(Mask);
946 assert(NumTZ <= 3 && "Invalid IT mask!");
947 for (unsigned Pos = 3, e = NumTZ; Pos > e; --Pos) {
948 bool T = ((Mask >> Pos) & 1) == CondBit0;
956 void ARMInstPrinter::printThumbAddrModeRROperand(const MCInst *MI, unsigned Op,
958 const MCOperand &MO1 = MI->getOperand(Op);
959 const MCOperand &MO2 = MI->getOperand(Op + 1);
961 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
962 printOperand(MI, Op, O);
966 O << markup("<mem:") << "[";
967 printRegName(O, MO1.getReg());
968 if (unsigned RegNum = MO2.getReg()) {
970 printRegName(O, RegNum);
972 O << "]" << markup(">");
975 void ARMInstPrinter::printThumbAddrModeImm5SOperand(const MCInst *MI,
979 const MCOperand &MO1 = MI->getOperand(Op);
980 const MCOperand &MO2 = MI->getOperand(Op + 1);
982 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
983 printOperand(MI, Op, O);
987 O << markup("<mem:") << "[";
988 printRegName(O, MO1.getReg());
989 if (unsigned ImmOffs = MO2.getImm()) {
992 << "#" << formatImm(ImmOffs * Scale)
995 O << "]" << markup(">");
998 void ARMInstPrinter::printThumbAddrModeImm5S1Operand(const MCInst *MI,
1001 printThumbAddrModeImm5SOperand(MI, Op, O, 1);
1004 void ARMInstPrinter::printThumbAddrModeImm5S2Operand(const MCInst *MI,
1007 printThumbAddrModeImm5SOperand(MI, Op, O, 2);
1010 void ARMInstPrinter::printThumbAddrModeImm5S4Operand(const MCInst *MI,
1013 printThumbAddrModeImm5SOperand(MI, Op, O, 4);
1016 void ARMInstPrinter::printThumbAddrModeSPOperand(const MCInst *MI, unsigned Op,
1018 printThumbAddrModeImm5SOperand(MI, Op, O, 4);
1021 // Constant shifts t2_so_reg is a 2-operand unit corresponding to the Thumb2
1022 // register with shift forms.
1023 // REG 0 0 - e.g. R5
1024 // REG IMM, SH_OPC - e.g. R5, LSL #3
1025 void ARMInstPrinter::printT2SOOperand(const MCInst *MI, unsigned OpNum,
1027 const MCOperand &MO1 = MI->getOperand(OpNum);
1028 const MCOperand &MO2 = MI->getOperand(OpNum+1);
1030 unsigned Reg = MO1.getReg();
1031 printRegName(O, Reg);
1033 // Print the shift opc.
1034 assert(MO2.isImm() && "Not a valid t2_so_reg value!");
1035 printRegImmShift(O, ARM_AM::getSORegShOp(MO2.getImm()),
1036 ARM_AM::getSORegOffset(MO2.getImm()), UseMarkup);
1039 template <bool AlwaysPrintImm0>
1040 void ARMInstPrinter::printAddrModeImm12Operand(const MCInst *MI, unsigned OpNum,
1042 const MCOperand &MO1 = MI->getOperand(OpNum);
1043 const MCOperand &MO2 = MI->getOperand(OpNum+1);
1045 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
1046 printOperand(MI, OpNum, O);
1050 O << markup("<mem:") << "[";
1051 printRegName(O, MO1.getReg());
1053 int32_t OffImm = (int32_t)MO2.getImm();
1054 bool isSub = OffImm < 0;
1055 // Special value for #-0. All others are normal.
1056 if (OffImm == INT32_MIN)
1064 else if (AlwaysPrintImm0 || OffImm > 0) {
1070 O << "]" << markup(">");
1073 template<bool AlwaysPrintImm0>
1074 void ARMInstPrinter::printT2AddrModeImm8Operand(const MCInst *MI,
1077 const MCOperand &MO1 = MI->getOperand(OpNum);
1078 const MCOperand &MO2 = MI->getOperand(OpNum+1);
1080 O << markup("<mem:") << "[";
1081 printRegName(O, MO1.getReg());
1083 int32_t OffImm = (int32_t)MO2.getImm();
1084 bool isSub = OffImm < 0;
1086 if (OffImm == INT32_MIN)
1093 } else if (AlwaysPrintImm0 || OffImm > 0) {
1099 O << "]" << markup(">");
1102 template<bool AlwaysPrintImm0>
1103 void ARMInstPrinter::printT2AddrModeImm8s4Operand(const MCInst *MI,
1106 const MCOperand &MO1 = MI->getOperand(OpNum);
1107 const MCOperand &MO2 = MI->getOperand(OpNum+1);
1109 if (!MO1.isReg()) { // For label symbolic references.
1110 printOperand(MI, OpNum, O);
1114 O << markup("<mem:") << "[";
1115 printRegName(O, MO1.getReg());
1117 int32_t OffImm = (int32_t)MO2.getImm();
1118 bool isSub = OffImm < 0;
1120 assert(((OffImm & 0x3) == 0) && "Not a valid immediate!");
1123 if (OffImm == INT32_MIN)
1130 } else if (AlwaysPrintImm0 || OffImm > 0) {
1136 O << "]" << markup(">");
1139 void ARMInstPrinter::printT2AddrModeImm0_1020s4Operand(const MCInst *MI,
1142 const MCOperand &MO1 = MI->getOperand(OpNum);
1143 const MCOperand &MO2 = MI->getOperand(OpNum+1);
1145 O << markup("<mem:") << "[";
1146 printRegName(O, MO1.getReg());
1150 << "#" << formatImm(MO2.getImm() * 4)
1153 O << "]" << markup(">");
1156 void ARMInstPrinter::printT2AddrModeImm8OffsetOperand(const MCInst *MI,
1159 const MCOperand &MO1 = MI->getOperand(OpNum);
1160 int32_t OffImm = (int32_t)MO1.getImm();
1161 O << ", " << markup("<imm:");
1162 if (OffImm == INT32_MIN)
1164 else if (OffImm < 0)
1165 O << "#-" << -OffImm;
1171 void ARMInstPrinter::printT2AddrModeImm8s4OffsetOperand(const MCInst *MI,
1174 const MCOperand &MO1 = MI->getOperand(OpNum);
1175 int32_t OffImm = (int32_t)MO1.getImm();
1177 assert(((OffImm & 0x3) == 0) && "Not a valid immediate!");
1179 O << ", " << markup("<imm:");
1180 if (OffImm == INT32_MIN)
1182 else if (OffImm < 0)
1183 O << "#-" << -OffImm;
1189 void ARMInstPrinter::printT2AddrModeSoRegOperand(const MCInst *MI,
1192 const MCOperand &MO1 = MI->getOperand(OpNum);
1193 const MCOperand &MO2 = MI->getOperand(OpNum+1);
1194 const MCOperand &MO3 = MI->getOperand(OpNum+2);
1196 O << markup("<mem:") << "[";
1197 printRegName(O, MO1.getReg());
1199 assert(MO2.getReg() && "Invalid so_reg load / store address!");
1201 printRegName(O, MO2.getReg());
1203 unsigned ShAmt = MO3.getImm();
1205 assert(ShAmt <= 3 && "Not a valid Thumb2 addressing mode!");
1211 O << "]" << markup(">");
1214 void ARMInstPrinter::printFPImmOperand(const MCInst *MI, unsigned OpNum,
1216 const MCOperand &MO = MI->getOperand(OpNum);
1217 O << markup("<imm:")
1218 << '#' << ARM_AM::getFPImmFloat(MO.getImm())
1222 void ARMInstPrinter::printNEONModImmOperand(const MCInst *MI, unsigned OpNum,
1224 unsigned EncodedImm = MI->getOperand(OpNum).getImm();
1226 uint64_t Val = ARM_AM::decodeNEONModImm(EncodedImm, EltBits);
1227 O << markup("<imm:")
1233 void ARMInstPrinter::printImmPlusOneOperand(const MCInst *MI, unsigned OpNum,
1235 unsigned Imm = MI->getOperand(OpNum).getImm();
1236 O << markup("<imm:")
1237 << "#" << formatImm(Imm + 1)
1241 void ARMInstPrinter::printRotImmOperand(const MCInst *MI, unsigned OpNum,
1243 unsigned Imm = MI->getOperand(OpNum).getImm();
1250 default: assert (0 && "illegal ror immediate!");
1251 case 1: O << "8"; break;
1252 case 2: O << "16"; break;
1253 case 3: O << "24"; break;
1258 void ARMInstPrinter::printFBits16(const MCInst *MI, unsigned OpNum,
1260 O << markup("<imm:")
1261 << "#" << 16 - MI->getOperand(OpNum).getImm()
1265 void ARMInstPrinter::printFBits32(const MCInst *MI, unsigned OpNum,
1267 O << markup("<imm:")
1268 << "#" << 32 - MI->getOperand(OpNum).getImm()
1272 void ARMInstPrinter::printVectorIndex(const MCInst *MI, unsigned OpNum,
1274 O << "[" << MI->getOperand(OpNum).getImm() << "]";
1277 void ARMInstPrinter::printVectorListOne(const MCInst *MI, unsigned OpNum,
1280 printRegName(O, MI->getOperand(OpNum).getReg());
1284 void ARMInstPrinter::printVectorListTwo(const MCInst *MI, unsigned OpNum,
1286 unsigned Reg = MI->getOperand(OpNum).getReg();
1287 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0);
1288 unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_1);
1290 printRegName(O, Reg0);
1292 printRegName(O, Reg1);
1296 void ARMInstPrinter::printVectorListTwoSpaced(const MCInst *MI,
1299 unsigned Reg = MI->getOperand(OpNum).getReg();
1300 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0);
1301 unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_2);
1303 printRegName(O, Reg0);
1305 printRegName(O, Reg1);
1309 void ARMInstPrinter::printVectorListThree(const MCInst *MI, unsigned OpNum,
1311 // Normally, it's not safe to use register enum values directly with
1312 // addition to get the next register, but for VFP registers, the
1313 // sort order is guaranteed because they're all of the form D<n>.
1315 printRegName(O, MI->getOperand(OpNum).getReg());
1317 printRegName(O, MI->getOperand(OpNum).getReg() + 1);
1319 printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1323 void ARMInstPrinter::printVectorListFour(const MCInst *MI, unsigned OpNum,
1325 // Normally, it's not safe to use register enum values directly with
1326 // addition to get the next register, but for VFP registers, the
1327 // sort order is guaranteed because they're all of the form D<n>.
1329 printRegName(O, MI->getOperand(OpNum).getReg());
1331 printRegName(O, MI->getOperand(OpNum).getReg() + 1);
1333 printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1335 printRegName(O, MI->getOperand(OpNum).getReg() + 3);
1339 void ARMInstPrinter::printVectorListOneAllLanes(const MCInst *MI,
1343 printRegName(O, MI->getOperand(OpNum).getReg());
1347 void ARMInstPrinter::printVectorListTwoAllLanes(const MCInst *MI,
1350 unsigned Reg = MI->getOperand(OpNum).getReg();
1351 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0);
1352 unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_1);
1354 printRegName(O, Reg0);
1356 printRegName(O, Reg1);
1360 void ARMInstPrinter::printVectorListThreeAllLanes(const MCInst *MI,
1363 // Normally, it's not safe to use register enum values directly with
1364 // addition to get the next register, but for VFP registers, the
1365 // sort order is guaranteed because they're all of the form D<n>.
1367 printRegName(O, MI->getOperand(OpNum).getReg());
1369 printRegName(O, MI->getOperand(OpNum).getReg() + 1);
1371 printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1375 void ARMInstPrinter::printVectorListFourAllLanes(const MCInst *MI,
1378 // Normally, it's not safe to use register enum values directly with
1379 // addition to get the next register, but for VFP registers, the
1380 // sort order is guaranteed because they're all of the form D<n>.
1382 printRegName(O, MI->getOperand(OpNum).getReg());
1384 printRegName(O, MI->getOperand(OpNum).getReg() + 1);
1386 printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1388 printRegName(O, MI->getOperand(OpNum).getReg() + 3);
1392 void ARMInstPrinter::printVectorListTwoSpacedAllLanes(const MCInst *MI,
1395 unsigned Reg = MI->getOperand(OpNum).getReg();
1396 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0);
1397 unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_2);
1399 printRegName(O, Reg0);
1401 printRegName(O, Reg1);
1405 void ARMInstPrinter::printVectorListThreeSpacedAllLanes(const MCInst *MI,
1408 // Normally, it's not safe to use register enum values directly with
1409 // addition to get the next register, but for VFP registers, the
1410 // sort order is guaranteed because they're all of the form D<n>.
1412 printRegName(O, MI->getOperand(OpNum).getReg());
1414 printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1416 printRegName(O, MI->getOperand(OpNum).getReg() + 4);
1420 void ARMInstPrinter::printVectorListFourSpacedAllLanes(const MCInst *MI,
1423 // Normally, it's not safe to use register enum values directly with
1424 // addition to get the next register, but for VFP registers, the
1425 // sort order is guaranteed because they're all of the form D<n>.
1427 printRegName(O, MI->getOperand(OpNum).getReg());
1429 printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1431 printRegName(O, MI->getOperand(OpNum).getReg() + 4);
1433 printRegName(O, MI->getOperand(OpNum).getReg() + 6);
1437 void ARMInstPrinter::printVectorListThreeSpaced(const MCInst *MI,
1440 // Normally, it's not safe to use register enum values directly with
1441 // addition to get the next register, but for VFP registers, the
1442 // sort order is guaranteed because they're all of the form D<n>.
1444 printRegName(O, MI->getOperand(OpNum).getReg());
1446 printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1448 printRegName(O, MI->getOperand(OpNum).getReg() + 4);
1452 void ARMInstPrinter::printVectorListFourSpaced(const MCInst *MI,
1455 // Normally, it's not safe to use register enum values directly with
1456 // addition to get the next register, but for VFP registers, the
1457 // sort order is guaranteed because they're all of the form D<n>.
1459 printRegName(O, MI->getOperand(OpNum).getReg());
1461 printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1463 printRegName(O, MI->getOperand(OpNum).getReg() + 4);
1465 printRegName(O, MI->getOperand(OpNum).getReg() + 6);