1 //===-- ARMInstPrinter.cpp - Convert ARM MCInst to assembly syntax --------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This class prints an ARM MCInst to a .s file.
12 //===----------------------------------------------------------------------===//
14 #include "ARMInstPrinter.h"
15 #include "MCTargetDesc/ARMAddressingModes.h"
16 #include "MCTargetDesc/ARMBaseInfo.h"
17 #include "llvm/MC/MCAsmInfo.h"
18 #include "llvm/MC/MCExpr.h"
19 #include "llvm/MC/MCInst.h"
20 #include "llvm/MC/MCInstrInfo.h"
21 #include "llvm/MC/MCRegisterInfo.h"
22 #include "llvm/Support/raw_ostream.h"
25 #define DEBUG_TYPE "asm-printer"
27 #include "ARMGenAsmWriter.inc"
29 /// translateShiftImm - Convert shift immediate from 0-31 to 1-32 for printing.
31 /// getSORegOffset returns an integer from 0-31, representing '32' as 0.
32 static unsigned translateShiftImm(unsigned imm) {
33 // lsr #32 and asr #32 exist, but should be encoded as a 0.
34 assert((imm & ~0x1f) == 0 && "Invalid shift encoding");
41 /// Prints the shift value with an immediate value.
42 static void printRegImmShift(raw_ostream &O, ARM_AM::ShiftOpc ShOpc,
43 unsigned ShImm, bool UseMarkup) {
44 if (ShOpc == ARM_AM::no_shift || (ShOpc == ARM_AM::lsl && !ShImm))
48 assert(!(ShOpc == ARM_AM::ror && !ShImm) && "Cannot have ror #0");
49 O << getShiftOpcStr(ShOpc);
51 if (ShOpc != ARM_AM::rrx) {
55 O << "#" << translateShiftImm(ShImm);
61 ARMInstPrinter::ARMInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII,
62 const MCRegisterInfo &MRI)
63 : MCInstPrinter(MAI, MII, MRI) {}
65 void ARMInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
66 OS << markup("<reg:") << getRegisterName(RegNo) << markup(">");
69 void ARMInstPrinter::printInst(const MCInst *MI, raw_ostream &O,
70 StringRef Annot, const MCSubtargetInfo &STI) {
71 unsigned Opcode = MI->getOpcode();
75 // Check for HINT instructions w/ canonical names.
79 switch (MI->getOperand(0).getImm()) {
96 if (STI.getFeatureBits()[ARM::HasV8Ops]) {
99 } // Fallthrough for non-v8
101 // Anything else should just print normally.
102 printInstruction(MI, STI, O);
103 printAnnotation(O, Annot);
106 printPredicateOperand(MI, 1, STI, O);
107 if (Opcode == ARM::t2HINT)
109 printAnnotation(O, Annot);
112 // Check for MOVs and print canonical forms, instead.
114 // FIXME: Thumb variants?
115 const MCOperand &Dst = MI->getOperand(0);
116 const MCOperand &MO1 = MI->getOperand(1);
117 const MCOperand &MO2 = MI->getOperand(2);
118 const MCOperand &MO3 = MI->getOperand(3);
120 O << '\t' << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO3.getImm()));
121 printSBitModifierOperand(MI, 6, STI, O);
122 printPredicateOperand(MI, 4, STI, O);
125 printRegName(O, Dst.getReg());
127 printRegName(O, MO1.getReg());
130 printRegName(O, MO2.getReg());
131 assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0);
132 printAnnotation(O, Annot);
137 // FIXME: Thumb variants?
138 const MCOperand &Dst = MI->getOperand(0);
139 const MCOperand &MO1 = MI->getOperand(1);
140 const MCOperand &MO2 = MI->getOperand(2);
142 O << '\t' << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO2.getImm()));
143 printSBitModifierOperand(MI, 5, STI, O);
144 printPredicateOperand(MI, 3, STI, O);
147 printRegName(O, Dst.getReg());
149 printRegName(O, MO1.getReg());
151 if (ARM_AM::getSORegShOp(MO2.getImm()) == ARM_AM::rrx) {
152 printAnnotation(O, Annot);
156 O << ", " << markup("<imm:") << "#"
157 << translateShiftImm(ARM_AM::getSORegOffset(MO2.getImm())) << markup(">");
158 printAnnotation(O, Annot);
164 case ARM::t2STMDB_UPD:
165 if (MI->getOperand(0).getReg() == ARM::SP && MI->getNumOperands() > 5) {
166 // Should only print PUSH if there are at least two registers in the list.
168 printPredicateOperand(MI, 2, STI, O);
169 if (Opcode == ARM::t2STMDB_UPD)
172 printRegisterList(MI, 4, STI, O);
173 printAnnotation(O, Annot);
178 case ARM::STR_PRE_IMM:
179 if (MI->getOperand(2).getReg() == ARM::SP &&
180 MI->getOperand(3).getImm() == -4) {
182 printPredicateOperand(MI, 4, STI, O);
184 printRegName(O, MI->getOperand(1).getReg());
186 printAnnotation(O, Annot);
193 case ARM::t2LDMIA_UPD:
194 if (MI->getOperand(0).getReg() == ARM::SP && MI->getNumOperands() > 5) {
195 // Should only print POP if there are at least two registers in the list.
197 printPredicateOperand(MI, 2, STI, O);
198 if (Opcode == ARM::t2LDMIA_UPD)
201 printRegisterList(MI, 4, STI, O);
202 printAnnotation(O, Annot);
207 case ARM::LDR_POST_IMM:
208 if (MI->getOperand(2).getReg() == ARM::SP &&
209 MI->getOperand(4).getImm() == 4) {
211 printPredicateOperand(MI, 5, STI, O);
213 printRegName(O, MI->getOperand(0).getReg());
215 printAnnotation(O, Annot);
221 case ARM::VSTMSDB_UPD:
222 case ARM::VSTMDDB_UPD:
223 if (MI->getOperand(0).getReg() == ARM::SP) {
224 O << '\t' << "vpush";
225 printPredicateOperand(MI, 2, STI, O);
227 printRegisterList(MI, 4, STI, O);
228 printAnnotation(O, Annot);
234 case ARM::VLDMSIA_UPD:
235 case ARM::VLDMDIA_UPD:
236 if (MI->getOperand(0).getReg() == ARM::SP) {
238 printPredicateOperand(MI, 2, STI, O);
240 printRegisterList(MI, 4, STI, O);
241 printAnnotation(O, Annot);
247 bool Writeback = true;
248 unsigned BaseReg = MI->getOperand(0).getReg();
249 for (unsigned i = 3; i < MI->getNumOperands(); ++i) {
250 if (MI->getOperand(i).getReg() == BaseReg)
256 printPredicateOperand(MI, 1, STI, O);
258 printRegName(O, BaseReg);
262 printRegisterList(MI, 3, STI, O);
263 printAnnotation(O, Annot);
267 // Combine 2 GPRs from disassember into a GPRPair to match with instr def.
268 // ldrexd/strexd require even/odd GPR pair. To enforce this constraint,
269 // a single GPRPair reg operand is used in the .td file to replace the two
270 // GPRs. However, when decoding them, the two GRPs cannot be automatically
271 // expressed as a GPRPair, so we have to manually merge them.
272 // FIXME: We would really like to be able to tablegen'erate this.
277 const MCRegisterClass &MRC = MRI.getRegClass(ARM::GPRRegClassID);
278 bool isStore = Opcode == ARM::STREXD || Opcode == ARM::STLEXD;
279 unsigned Reg = MI->getOperand(isStore ? 1 : 0).getReg();
280 if (MRC.contains(Reg)) {
283 NewMI.setOpcode(Opcode);
286 NewMI.addOperand(MI->getOperand(0));
287 NewReg = MCOperand::createReg(MRI.getMatchingSuperReg(
288 Reg, ARM::gsub_0, &MRI.getRegClass(ARM::GPRPairRegClassID)));
289 NewMI.addOperand(NewReg);
291 // Copy the rest operands into NewMI.
292 for (unsigned i = isStore ? 3 : 2; i < MI->getNumOperands(); ++i)
293 NewMI.addOperand(MI->getOperand(i));
294 printInstruction(&NewMI, STI, O);
299 // B9.3.3 ERET (Thumb)
300 // For a target that has Virtualization Extensions, ERET is the preferred
301 // disassembly of SUBS PC, LR, #0
302 case ARM::t2SUBS_PC_LR: {
303 if (MI->getNumOperands() == 3 && MI->getOperand(0).isImm() &&
304 MI->getOperand(0).getImm() == 0 &&
305 STI.getFeatureBits()[ARM::FeatureVirtualization]) {
307 printPredicateOperand(MI, 1, STI, O);
308 printAnnotation(O, Annot);
315 printInstruction(MI, STI, O);
316 printAnnotation(O, Annot);
319 void ARMInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
320 const MCSubtargetInfo &STI, raw_ostream &O) {
321 const MCOperand &Op = MI->getOperand(OpNo);
323 unsigned Reg = Op.getReg();
324 printRegName(O, Reg);
325 } else if (Op.isImm()) {
326 O << markup("<imm:") << '#' << formatImm(Op.getImm()) << markup(">");
328 assert(Op.isExpr() && "unknown operand kind in printOperand");
329 const MCExpr *Expr = Op.getExpr();
330 switch (Expr->getKind()) {
333 Expr->print(O, &MAI);
335 case MCExpr::Constant: {
336 // If a symbolic branch target was added as a constant expression then
337 // print that address in hex. And only print 32 unsigned bits for the
339 const MCConstantExpr *Constant = cast<MCConstantExpr>(Expr);
340 int64_t TargetAddress;
341 if (!Constant->evaluateAsAbsolute(TargetAddress)) {
343 Expr->print(O, &MAI);
346 O.write_hex(static_cast<uint32_t>(TargetAddress));
351 // FIXME: Should we always treat this as if it is a constant literal and
352 // prefix it with '#'?
353 Expr->print(O, &MAI);
359 void ARMInstPrinter::printThumbLdrLabelOperand(const MCInst *MI, unsigned OpNum,
360 const MCSubtargetInfo &STI,
362 const MCOperand &MO1 = MI->getOperand(OpNum);
364 MO1.getExpr()->print(O, &MAI);
368 O << markup("<mem:") << "[pc, ";
370 int32_t OffImm = (int32_t)MO1.getImm();
371 bool isSub = OffImm < 0;
373 // Special value for #-0. All others are normal.
374 if (OffImm == INT32_MIN)
377 O << markup("<imm:") << "#-" << formatImm(-OffImm) << markup(">");
379 O << markup("<imm:") << "#" << formatImm(OffImm) << markup(">");
381 O << "]" << markup(">");
384 // so_reg is a 4-operand unit corresponding to register forms of the A5.1
385 // "Addressing Mode 1 - Data-processing operands" forms. This includes:
387 // REG REG 0,SH_OPC - e.g. R5, ROR R3
388 // REG 0 IMM,SH_OPC - e.g. R5, LSL #3
389 void ARMInstPrinter::printSORegRegOperand(const MCInst *MI, unsigned OpNum,
390 const MCSubtargetInfo &STI,
392 const MCOperand &MO1 = MI->getOperand(OpNum);
393 const MCOperand &MO2 = MI->getOperand(OpNum + 1);
394 const MCOperand &MO3 = MI->getOperand(OpNum + 2);
396 printRegName(O, MO1.getReg());
398 // Print the shift opc.
399 ARM_AM::ShiftOpc ShOpc = ARM_AM::getSORegShOp(MO3.getImm());
400 O << ", " << ARM_AM::getShiftOpcStr(ShOpc);
401 if (ShOpc == ARM_AM::rrx)
405 printRegName(O, MO2.getReg());
406 assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0);
409 void ARMInstPrinter::printSORegImmOperand(const MCInst *MI, unsigned OpNum,
410 const MCSubtargetInfo &STI,
412 const MCOperand &MO1 = MI->getOperand(OpNum);
413 const MCOperand &MO2 = MI->getOperand(OpNum + 1);
415 printRegName(O, MO1.getReg());
417 // Print the shift opc.
418 printRegImmShift(O, ARM_AM::getSORegShOp(MO2.getImm()),
419 ARM_AM::getSORegOffset(MO2.getImm()), UseMarkup);
422 //===--------------------------------------------------------------------===//
423 // Addressing Mode #2
424 //===--------------------------------------------------------------------===//
426 void ARMInstPrinter::printAM2PreOrOffsetIndexOp(const MCInst *MI, unsigned Op,
427 const MCSubtargetInfo &STI,
429 const MCOperand &MO1 = MI->getOperand(Op);
430 const MCOperand &MO2 = MI->getOperand(Op + 1);
431 const MCOperand &MO3 = MI->getOperand(Op + 2);
433 O << markup("<mem:") << "[";
434 printRegName(O, MO1.getReg());
437 if (ARM_AM::getAM2Offset(MO3.getImm())) { // Don't print +0.
438 O << ", " << markup("<imm:") << "#"
439 << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm()))
440 << ARM_AM::getAM2Offset(MO3.getImm()) << markup(">");
442 O << "]" << markup(">");
447 O << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm()));
448 printRegName(O, MO2.getReg());
450 printRegImmShift(O, ARM_AM::getAM2ShiftOpc(MO3.getImm()),
451 ARM_AM::getAM2Offset(MO3.getImm()), UseMarkup);
452 O << "]" << markup(">");
455 void ARMInstPrinter::printAddrModeTBB(const MCInst *MI, unsigned Op,
456 const MCSubtargetInfo &STI,
458 const MCOperand &MO1 = MI->getOperand(Op);
459 const MCOperand &MO2 = MI->getOperand(Op + 1);
460 O << markup("<mem:") << "[";
461 printRegName(O, MO1.getReg());
463 printRegName(O, MO2.getReg());
464 O << "]" << markup(">");
467 void ARMInstPrinter::printAddrModeTBH(const MCInst *MI, unsigned Op,
468 const MCSubtargetInfo &STI,
470 const MCOperand &MO1 = MI->getOperand(Op);
471 const MCOperand &MO2 = MI->getOperand(Op + 1);
472 O << markup("<mem:") << "[";
473 printRegName(O, MO1.getReg());
475 printRegName(O, MO2.getReg());
476 O << ", lsl " << markup("<imm:") << "#1" << markup(">") << "]" << markup(">");
479 void ARMInstPrinter::printAddrMode2Operand(const MCInst *MI, unsigned Op,
480 const MCSubtargetInfo &STI,
482 const MCOperand &MO1 = MI->getOperand(Op);
484 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
485 printOperand(MI, Op, STI, O);
490 const MCOperand &MO3 = MI->getOperand(Op + 2);
491 unsigned IdxMode = ARM_AM::getAM2IdxMode(MO3.getImm());
492 assert(IdxMode != ARMII::IndexModePost && "Should be pre or offset index op");
495 printAM2PreOrOffsetIndexOp(MI, Op, STI, O);
498 void ARMInstPrinter::printAddrMode2OffsetOperand(const MCInst *MI,
500 const MCSubtargetInfo &STI,
502 const MCOperand &MO1 = MI->getOperand(OpNum);
503 const MCOperand &MO2 = MI->getOperand(OpNum + 1);
506 unsigned ImmOffs = ARM_AM::getAM2Offset(MO2.getImm());
507 O << markup("<imm:") << '#'
508 << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO2.getImm())) << ImmOffs
513 O << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO2.getImm()));
514 printRegName(O, MO1.getReg());
516 printRegImmShift(O, ARM_AM::getAM2ShiftOpc(MO2.getImm()),
517 ARM_AM::getAM2Offset(MO2.getImm()), UseMarkup);
520 //===--------------------------------------------------------------------===//
521 // Addressing Mode #3
522 //===--------------------------------------------------------------------===//
524 void ARMInstPrinter::printAM3PreOrOffsetIndexOp(const MCInst *MI, unsigned Op,
526 bool AlwaysPrintImm0) {
527 const MCOperand &MO1 = MI->getOperand(Op);
528 const MCOperand &MO2 = MI->getOperand(Op + 1);
529 const MCOperand &MO3 = MI->getOperand(Op + 2);
531 O << markup("<mem:") << '[';
532 printRegName(O, MO1.getReg());
535 O << ", " << getAddrOpcStr(ARM_AM::getAM3Op(MO3.getImm()));
536 printRegName(O, MO2.getReg());
537 O << ']' << markup(">");
541 // If the op is sub we have to print the immediate even if it is 0
542 unsigned ImmOffs = ARM_AM::getAM3Offset(MO3.getImm());
543 ARM_AM::AddrOpc op = ARM_AM::getAM3Op(MO3.getImm());
545 if (AlwaysPrintImm0 || ImmOffs || (op == ARM_AM::sub)) {
546 O << ", " << markup("<imm:") << "#" << ARM_AM::getAddrOpcStr(op) << ImmOffs
549 O << ']' << markup(">");
552 template <bool AlwaysPrintImm0>
553 void ARMInstPrinter::printAddrMode3Operand(const MCInst *MI, unsigned Op,
554 const MCSubtargetInfo &STI,
556 const MCOperand &MO1 = MI->getOperand(Op);
557 if (!MO1.isReg()) { // For label symbolic references.
558 printOperand(MI, Op, STI, O);
562 assert(ARM_AM::getAM3IdxMode(MI->getOperand(Op + 2).getImm()) !=
563 ARMII::IndexModePost &&
564 "unexpected idxmode");
565 printAM3PreOrOffsetIndexOp(MI, Op, O, AlwaysPrintImm0);
568 void ARMInstPrinter::printAddrMode3OffsetOperand(const MCInst *MI,
570 const MCSubtargetInfo &STI,
572 const MCOperand &MO1 = MI->getOperand(OpNum);
573 const MCOperand &MO2 = MI->getOperand(OpNum + 1);
576 O << getAddrOpcStr(ARM_AM::getAM3Op(MO2.getImm()));
577 printRegName(O, MO1.getReg());
581 unsigned ImmOffs = ARM_AM::getAM3Offset(MO2.getImm());
582 O << markup("<imm:") << '#'
583 << ARM_AM::getAddrOpcStr(ARM_AM::getAM3Op(MO2.getImm())) << ImmOffs
587 void ARMInstPrinter::printPostIdxImm8Operand(const MCInst *MI, unsigned OpNum,
588 const MCSubtargetInfo &STI,
590 const MCOperand &MO = MI->getOperand(OpNum);
591 unsigned Imm = MO.getImm();
592 O << markup("<imm:") << '#' << ((Imm & 256) ? "" : "-") << (Imm & 0xff)
596 void ARMInstPrinter::printPostIdxRegOperand(const MCInst *MI, unsigned OpNum,
597 const MCSubtargetInfo &STI,
599 const MCOperand &MO1 = MI->getOperand(OpNum);
600 const MCOperand &MO2 = MI->getOperand(OpNum + 1);
602 O << (MO2.getImm() ? "" : "-");
603 printRegName(O, MO1.getReg());
606 void ARMInstPrinter::printPostIdxImm8s4Operand(const MCInst *MI, unsigned OpNum,
607 const MCSubtargetInfo &STI,
609 const MCOperand &MO = MI->getOperand(OpNum);
610 unsigned Imm = MO.getImm();
611 O << markup("<imm:") << '#' << ((Imm & 256) ? "" : "-") << ((Imm & 0xff) << 2)
615 void ARMInstPrinter::printLdStmModeOperand(const MCInst *MI, unsigned OpNum,
616 const MCSubtargetInfo &STI,
618 ARM_AM::AMSubMode Mode =
619 ARM_AM::getAM4SubMode(MI->getOperand(OpNum).getImm());
620 O << ARM_AM::getAMSubModeStr(Mode);
623 template <bool AlwaysPrintImm0>
624 void ARMInstPrinter::printAddrMode5Operand(const MCInst *MI, unsigned OpNum,
625 const MCSubtargetInfo &STI,
627 const MCOperand &MO1 = MI->getOperand(OpNum);
628 const MCOperand &MO2 = MI->getOperand(OpNum + 1);
630 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
631 printOperand(MI, OpNum, STI, O);
635 O << markup("<mem:") << "[";
636 printRegName(O, MO1.getReg());
638 unsigned ImmOffs = ARM_AM::getAM5Offset(MO2.getImm());
639 ARM_AM::AddrOpc Op = ARM_AM::getAM5Op(MO2.getImm());
640 if (AlwaysPrintImm0 || ImmOffs || Op == ARM_AM::sub) {
641 O << ", " << markup("<imm:") << "#" << ARM_AM::getAddrOpcStr(Op)
642 << ImmOffs * 4 << markup(">");
644 O << "]" << markup(">");
647 void ARMInstPrinter::printAddrMode6Operand(const MCInst *MI, unsigned OpNum,
648 const MCSubtargetInfo &STI,
650 const MCOperand &MO1 = MI->getOperand(OpNum);
651 const MCOperand &MO2 = MI->getOperand(OpNum + 1);
653 O << markup("<mem:") << "[";
654 printRegName(O, MO1.getReg());
656 O << ":" << (MO2.getImm() << 3);
658 O << "]" << markup(">");
661 void ARMInstPrinter::printAddrMode7Operand(const MCInst *MI, unsigned OpNum,
662 const MCSubtargetInfo &STI,
664 const MCOperand &MO1 = MI->getOperand(OpNum);
665 O << markup("<mem:") << "[";
666 printRegName(O, MO1.getReg());
667 O << "]" << markup(">");
670 void ARMInstPrinter::printAddrMode6OffsetOperand(const MCInst *MI,
672 const MCSubtargetInfo &STI,
674 const MCOperand &MO = MI->getOperand(OpNum);
675 if (MO.getReg() == 0)
679 printRegName(O, MO.getReg());
683 void ARMInstPrinter::printBitfieldInvMaskImmOperand(const MCInst *MI,
685 const MCSubtargetInfo &STI,
687 const MCOperand &MO = MI->getOperand(OpNum);
688 uint32_t v = ~MO.getImm();
689 int32_t lsb = countTrailingZeros(v);
690 int32_t width = (32 - countLeadingZeros(v)) - lsb;
691 assert(MO.isImm() && "Not a valid bf_inv_mask_imm value!");
692 O << markup("<imm:") << '#' << lsb << markup(">") << ", " << markup("<imm:")
693 << '#' << width << markup(">");
696 void ARMInstPrinter::printMemBOption(const MCInst *MI, unsigned OpNum,
697 const MCSubtargetInfo &STI,
699 unsigned val = MI->getOperand(OpNum).getImm();
700 O << ARM_MB::MemBOptToString(val, STI.getFeatureBits()[ARM::HasV8Ops]);
703 void ARMInstPrinter::printInstSyncBOption(const MCInst *MI, unsigned OpNum,
704 const MCSubtargetInfo &STI,
706 unsigned val = MI->getOperand(OpNum).getImm();
707 O << ARM_ISB::InstSyncBOptToString(val);
710 void ARMInstPrinter::printShiftImmOperand(const MCInst *MI, unsigned OpNum,
711 const MCSubtargetInfo &STI,
713 unsigned ShiftOp = MI->getOperand(OpNum).getImm();
714 bool isASR = (ShiftOp & (1 << 5)) != 0;
715 unsigned Amt = ShiftOp & 0x1f;
717 O << ", asr " << markup("<imm:") << "#" << (Amt == 0 ? 32 : Amt)
720 O << ", lsl " << markup("<imm:") << "#" << Amt << markup(">");
724 void ARMInstPrinter::printPKHLSLShiftImm(const MCInst *MI, unsigned OpNum,
725 const MCSubtargetInfo &STI,
727 unsigned Imm = MI->getOperand(OpNum).getImm();
730 assert(Imm > 0 && Imm < 32 && "Invalid PKH shift immediate value!");
731 O << ", lsl " << markup("<imm:") << "#" << Imm << markup(">");
734 void ARMInstPrinter::printPKHASRShiftImm(const MCInst *MI, unsigned OpNum,
735 const MCSubtargetInfo &STI,
737 unsigned Imm = MI->getOperand(OpNum).getImm();
738 // A shift amount of 32 is encoded as 0.
741 assert(Imm > 0 && Imm <= 32 && "Invalid PKH shift immediate value!");
742 O << ", asr " << markup("<imm:") << "#" << Imm << markup(">");
745 void ARMInstPrinter::printRegisterList(const MCInst *MI, unsigned OpNum,
746 const MCSubtargetInfo &STI,
749 for (unsigned i = OpNum, e = MI->getNumOperands(); i != e; ++i) {
752 printRegName(O, MI->getOperand(i).getReg());
757 void ARMInstPrinter::printGPRPairOperand(const MCInst *MI, unsigned OpNum,
758 const MCSubtargetInfo &STI,
760 unsigned Reg = MI->getOperand(OpNum).getReg();
761 printRegName(O, MRI.getSubReg(Reg, ARM::gsub_0));
763 printRegName(O, MRI.getSubReg(Reg, ARM::gsub_1));
766 void ARMInstPrinter::printSetendOperand(const MCInst *MI, unsigned OpNum,
767 const MCSubtargetInfo &STI,
769 const MCOperand &Op = MI->getOperand(OpNum);
776 void ARMInstPrinter::printCPSIMod(const MCInst *MI, unsigned OpNum,
777 const MCSubtargetInfo &STI, raw_ostream &O) {
778 const MCOperand &Op = MI->getOperand(OpNum);
779 O << ARM_PROC::IModToString(Op.getImm());
782 void ARMInstPrinter::printCPSIFlag(const MCInst *MI, unsigned OpNum,
783 const MCSubtargetInfo &STI, raw_ostream &O) {
784 const MCOperand &Op = MI->getOperand(OpNum);
785 unsigned IFlags = Op.getImm();
786 for (int i = 2; i >= 0; --i)
787 if (IFlags & (1 << i))
788 O << ARM_PROC::IFlagsToString(1 << i);
794 void ARMInstPrinter::printMSRMaskOperand(const MCInst *MI, unsigned OpNum,
795 const MCSubtargetInfo &STI,
797 const MCOperand &Op = MI->getOperand(OpNum);
798 unsigned SpecRegRBit = Op.getImm() >> 4;
799 unsigned Mask = Op.getImm() & 0xf;
800 const FeatureBitset &FeatureBits = STI.getFeatureBits();
802 if (FeatureBits[ARM::FeatureMClass]) {
803 unsigned SYSm = Op.getImm();
804 unsigned Opcode = MI->getOpcode();
806 // For writes, handle extended mask bits if the DSP extension is present.
807 if (Opcode == ARM::t2MSR_M && FeatureBits[ARM::FeatureDSPThumb2]) {
836 // Handle the basic 8-bit mask.
839 if (Opcode == ARM::t2MSR_M && FeatureBits [ARM::HasV7Ops]) {
840 // ARMv7-M deprecates using MSR APSR without a _<bits> qualifier as an
841 // alias for MSR APSR_nzcvq.
860 llvm_unreachable("Unexpected mask value!");
906 // As special cases, CPSR_f, CPSR_s and CPSR_fs prefer printing as
907 // APSR_nzcvq, APSR_g and APSRnzcvqg, respectively.
908 if (!SpecRegRBit && (Mask == 8 || Mask == 4 || Mask == 12)) {
912 llvm_unreachable("Unexpected mask value!");
943 void ARMInstPrinter::printBankedRegOperand(const MCInst *MI, unsigned OpNum,
944 const MCSubtargetInfo &STI,
946 uint32_t Banked = MI->getOperand(OpNum).getImm();
947 uint32_t R = (Banked & 0x20) >> 5;
948 uint32_t SysM = Banked & 0x1f;
950 // Nothing much we can do about this, the encodings are specified in B9.2.3 of
951 // the ARM ARM v7C, and are all over the shop.
978 llvm_unreachable("Invalid banked SPSR register");
982 assert(!R && "should have dealt with SPSR regs");
983 const char *RegNames[] = {
984 "r8_usr", "r9_usr", "r10_usr", "r11_usr", "r12_usr", "sp_usr", "lr_usr",
985 "", "r8_fiq", "r9_fiq", "r10_fiq", "r11_fiq", "r12_fiq", "sp_fiq",
986 "lr_fiq", "", "lr_irq", "sp_irq", "lr_svc", "sp_svc", "lr_abt",
987 "sp_abt", "lr_und", "sp_und", "", "", "", "",
988 "lr_mon", "sp_mon", "elr_hyp", "sp_hyp"};
989 const char *Name = RegNames[SysM];
990 assert(Name[0] && "invalid banked register operand");
995 void ARMInstPrinter::printPredicateOperand(const MCInst *MI, unsigned OpNum,
996 const MCSubtargetInfo &STI,
998 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
999 // Handle the undefined 15 CC value here for printing so we don't abort().
1000 if ((unsigned)CC == 15)
1002 else if (CC != ARMCC::AL)
1003 O << ARMCondCodeToString(CC);
1006 void ARMInstPrinter::printMandatoryPredicateOperand(const MCInst *MI,
1008 const MCSubtargetInfo &STI,
1010 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
1011 O << ARMCondCodeToString(CC);
1014 void ARMInstPrinter::printSBitModifierOperand(const MCInst *MI, unsigned OpNum,
1015 const MCSubtargetInfo &STI,
1017 if (MI->getOperand(OpNum).getReg()) {
1018 assert(MI->getOperand(OpNum).getReg() == ARM::CPSR &&
1019 "Expect ARM CPSR register!");
1024 void ARMInstPrinter::printNoHashImmediate(const MCInst *MI, unsigned OpNum,
1025 const MCSubtargetInfo &STI,
1027 O << MI->getOperand(OpNum).getImm();
1030 void ARMInstPrinter::printPImmediate(const MCInst *MI, unsigned OpNum,
1031 const MCSubtargetInfo &STI,
1033 O << "p" << MI->getOperand(OpNum).getImm();
1036 void ARMInstPrinter::printCImmediate(const MCInst *MI, unsigned OpNum,
1037 const MCSubtargetInfo &STI,
1039 O << "c" << MI->getOperand(OpNum).getImm();
1042 void ARMInstPrinter::printCoprocOptionImm(const MCInst *MI, unsigned OpNum,
1043 const MCSubtargetInfo &STI,
1045 O << "{" << MI->getOperand(OpNum).getImm() << "}";
1048 void ARMInstPrinter::printPCLabel(const MCInst *MI, unsigned OpNum,
1049 const MCSubtargetInfo &STI, raw_ostream &O) {
1050 llvm_unreachable("Unhandled PC-relative pseudo-instruction!");
1053 template <unsigned scale>
1054 void ARMInstPrinter::printAdrLabelOperand(const MCInst *MI, unsigned OpNum,
1055 const MCSubtargetInfo &STI,
1057 const MCOperand &MO = MI->getOperand(OpNum);
1060 MO.getExpr()->print(O, &MAI);
1064 int32_t OffImm = (int32_t)MO.getImm() << scale;
1066 O << markup("<imm:");
1067 if (OffImm == INT32_MIN)
1069 else if (OffImm < 0)
1070 O << "#-" << -OffImm;
1076 void ARMInstPrinter::printThumbS4ImmOperand(const MCInst *MI, unsigned OpNum,
1077 const MCSubtargetInfo &STI,
1079 O << markup("<imm:") << "#" << formatImm(MI->getOperand(OpNum).getImm() * 4)
1083 void ARMInstPrinter::printThumbSRImm(const MCInst *MI, unsigned OpNum,
1084 const MCSubtargetInfo &STI,
1086 unsigned Imm = MI->getOperand(OpNum).getImm();
1087 O << markup("<imm:") << "#" << formatImm((Imm == 0 ? 32 : Imm))
1091 void ARMInstPrinter::printThumbITMask(const MCInst *MI, unsigned OpNum,
1092 const MCSubtargetInfo &STI,
1094 // (3 - the number of trailing zeros) is the number of then / else.
1095 unsigned Mask = MI->getOperand(OpNum).getImm();
1096 unsigned Firstcond = MI->getOperand(OpNum - 1).getImm();
1097 unsigned CondBit0 = Firstcond & 1;
1098 unsigned NumTZ = countTrailingZeros(Mask);
1099 assert(NumTZ <= 3 && "Invalid IT mask!");
1100 for (unsigned Pos = 3, e = NumTZ; Pos > e; --Pos) {
1101 bool T = ((Mask >> Pos) & 1) == CondBit0;
1109 void ARMInstPrinter::printThumbAddrModeRROperand(const MCInst *MI, unsigned Op,
1110 const MCSubtargetInfo &STI,
1112 const MCOperand &MO1 = MI->getOperand(Op);
1113 const MCOperand &MO2 = MI->getOperand(Op + 1);
1115 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
1116 printOperand(MI, Op, STI, O);
1120 O << markup("<mem:") << "[";
1121 printRegName(O, MO1.getReg());
1122 if (unsigned RegNum = MO2.getReg()) {
1124 printRegName(O, RegNum);
1126 O << "]" << markup(">");
1129 void ARMInstPrinter::printThumbAddrModeImm5SOperand(const MCInst *MI,
1131 const MCSubtargetInfo &STI,
1134 const MCOperand &MO1 = MI->getOperand(Op);
1135 const MCOperand &MO2 = MI->getOperand(Op + 1);
1137 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
1138 printOperand(MI, Op, STI, O);
1142 O << markup("<mem:") << "[";
1143 printRegName(O, MO1.getReg());
1144 if (unsigned ImmOffs = MO2.getImm()) {
1145 O << ", " << markup("<imm:") << "#" << formatImm(ImmOffs * Scale)
1148 O << "]" << markup(">");
1151 void ARMInstPrinter::printThumbAddrModeImm5S1Operand(const MCInst *MI,
1153 const MCSubtargetInfo &STI,
1155 printThumbAddrModeImm5SOperand(MI, Op, STI, O, 1);
1158 void ARMInstPrinter::printThumbAddrModeImm5S2Operand(const MCInst *MI,
1160 const MCSubtargetInfo &STI,
1162 printThumbAddrModeImm5SOperand(MI, Op, STI, O, 2);
1165 void ARMInstPrinter::printThumbAddrModeImm5S4Operand(const MCInst *MI,
1167 const MCSubtargetInfo &STI,
1169 printThumbAddrModeImm5SOperand(MI, Op, STI, O, 4);
1172 void ARMInstPrinter::printThumbAddrModeSPOperand(const MCInst *MI, unsigned Op,
1173 const MCSubtargetInfo &STI,
1175 printThumbAddrModeImm5SOperand(MI, Op, STI, O, 4);
1178 // Constant shifts t2_so_reg is a 2-operand unit corresponding to the Thumb2
1179 // register with shift forms.
1180 // REG 0 0 - e.g. R5
1181 // REG IMM, SH_OPC - e.g. R5, LSL #3
1182 void ARMInstPrinter::printT2SOOperand(const MCInst *MI, unsigned OpNum,
1183 const MCSubtargetInfo &STI,
1185 const MCOperand &MO1 = MI->getOperand(OpNum);
1186 const MCOperand &MO2 = MI->getOperand(OpNum + 1);
1188 unsigned Reg = MO1.getReg();
1189 printRegName(O, Reg);
1191 // Print the shift opc.
1192 assert(MO2.isImm() && "Not a valid t2_so_reg value!");
1193 printRegImmShift(O, ARM_AM::getSORegShOp(MO2.getImm()),
1194 ARM_AM::getSORegOffset(MO2.getImm()), UseMarkup);
1197 template <bool AlwaysPrintImm0>
1198 void ARMInstPrinter::printAddrModeImm12Operand(const MCInst *MI, unsigned OpNum,
1199 const MCSubtargetInfo &STI,
1201 const MCOperand &MO1 = MI->getOperand(OpNum);
1202 const MCOperand &MO2 = MI->getOperand(OpNum + 1);
1204 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
1205 printOperand(MI, OpNum, STI, O);
1209 O << markup("<mem:") << "[";
1210 printRegName(O, MO1.getReg());
1212 int32_t OffImm = (int32_t)MO2.getImm();
1213 bool isSub = OffImm < 0;
1214 // Special value for #-0. All others are normal.
1215 if (OffImm == INT32_MIN)
1218 O << ", " << markup("<imm:") << "#-" << formatImm(-OffImm) << markup(">");
1219 } else if (AlwaysPrintImm0 || OffImm > 0) {
1220 O << ", " << markup("<imm:") << "#" << formatImm(OffImm) << markup(">");
1222 O << "]" << markup(">");
1225 template <bool AlwaysPrintImm0>
1226 void ARMInstPrinter::printT2AddrModeImm8Operand(const MCInst *MI,
1228 const MCSubtargetInfo &STI,
1230 const MCOperand &MO1 = MI->getOperand(OpNum);
1231 const MCOperand &MO2 = MI->getOperand(OpNum + 1);
1233 O << markup("<mem:") << "[";
1234 printRegName(O, MO1.getReg());
1236 int32_t OffImm = (int32_t)MO2.getImm();
1237 bool isSub = OffImm < 0;
1239 if (OffImm == INT32_MIN)
1242 O << ", " << markup("<imm:") << "#-" << -OffImm << markup(">");
1243 } else if (AlwaysPrintImm0 || OffImm > 0) {
1244 O << ", " << markup("<imm:") << "#" << OffImm << markup(">");
1246 O << "]" << markup(">");
1249 template <bool AlwaysPrintImm0>
1250 void ARMInstPrinter::printT2AddrModeImm8s4Operand(const MCInst *MI,
1252 const MCSubtargetInfo &STI,
1254 const MCOperand &MO1 = MI->getOperand(OpNum);
1255 const MCOperand &MO2 = MI->getOperand(OpNum + 1);
1257 if (!MO1.isReg()) { // For label symbolic references.
1258 printOperand(MI, OpNum, STI, O);
1262 O << markup("<mem:") << "[";
1263 printRegName(O, MO1.getReg());
1265 int32_t OffImm = (int32_t)MO2.getImm();
1266 bool isSub = OffImm < 0;
1268 assert(((OffImm & 0x3) == 0) && "Not a valid immediate!");
1271 if (OffImm == INT32_MIN)
1274 O << ", " << markup("<imm:") << "#-" << -OffImm << markup(">");
1275 } else if (AlwaysPrintImm0 || OffImm > 0) {
1276 O << ", " << markup("<imm:") << "#" << OffImm << markup(">");
1278 O << "]" << markup(">");
1281 void ARMInstPrinter::printT2AddrModeImm0_1020s4Operand(
1282 const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI,
1284 const MCOperand &MO1 = MI->getOperand(OpNum);
1285 const MCOperand &MO2 = MI->getOperand(OpNum + 1);
1287 O << markup("<mem:") << "[";
1288 printRegName(O, MO1.getReg());
1290 O << ", " << markup("<imm:") << "#" << formatImm(MO2.getImm() * 4)
1293 O << "]" << markup(">");
1296 void ARMInstPrinter::printT2AddrModeImm8OffsetOperand(
1297 const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI,
1299 const MCOperand &MO1 = MI->getOperand(OpNum);
1300 int32_t OffImm = (int32_t)MO1.getImm();
1301 O << ", " << markup("<imm:");
1302 if (OffImm == INT32_MIN)
1304 else if (OffImm < 0)
1305 O << "#-" << -OffImm;
1311 void ARMInstPrinter::printT2AddrModeImm8s4OffsetOperand(
1312 const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI,
1314 const MCOperand &MO1 = MI->getOperand(OpNum);
1315 int32_t OffImm = (int32_t)MO1.getImm();
1317 assert(((OffImm & 0x3) == 0) && "Not a valid immediate!");
1319 O << ", " << markup("<imm:");
1320 if (OffImm == INT32_MIN)
1322 else if (OffImm < 0)
1323 O << "#-" << -OffImm;
1329 void ARMInstPrinter::printT2AddrModeSoRegOperand(const MCInst *MI,
1331 const MCSubtargetInfo &STI,
1333 const MCOperand &MO1 = MI->getOperand(OpNum);
1334 const MCOperand &MO2 = MI->getOperand(OpNum + 1);
1335 const MCOperand &MO3 = MI->getOperand(OpNum + 2);
1337 O << markup("<mem:") << "[";
1338 printRegName(O, MO1.getReg());
1340 assert(MO2.getReg() && "Invalid so_reg load / store address!");
1342 printRegName(O, MO2.getReg());
1344 unsigned ShAmt = MO3.getImm();
1346 assert(ShAmt <= 3 && "Not a valid Thumb2 addressing mode!");
1347 O << ", lsl " << markup("<imm:") << "#" << ShAmt << markup(">");
1349 O << "]" << markup(">");
1352 void ARMInstPrinter::printFPImmOperand(const MCInst *MI, unsigned OpNum,
1353 const MCSubtargetInfo &STI,
1355 const MCOperand &MO = MI->getOperand(OpNum);
1356 O << markup("<imm:") << '#' << ARM_AM::getFPImmFloat(MO.getImm())
1360 void ARMInstPrinter::printNEONModImmOperand(const MCInst *MI, unsigned OpNum,
1361 const MCSubtargetInfo &STI,
1363 unsigned EncodedImm = MI->getOperand(OpNum).getImm();
1365 uint64_t Val = ARM_AM::decodeNEONModImm(EncodedImm, EltBits);
1366 O << markup("<imm:") << "#0x";
1371 void ARMInstPrinter::printImmPlusOneOperand(const MCInst *MI, unsigned OpNum,
1372 const MCSubtargetInfo &STI,
1374 unsigned Imm = MI->getOperand(OpNum).getImm();
1375 O << markup("<imm:") << "#" << formatImm(Imm + 1) << markup(">");
1378 void ARMInstPrinter::printRotImmOperand(const MCInst *MI, unsigned OpNum,
1379 const MCSubtargetInfo &STI,
1381 unsigned Imm = MI->getOperand(OpNum).getImm();
1384 assert(Imm <= 3 && "illegal ror immediate!");
1385 O << ", ror " << markup("<imm:") << "#" << 8 * Imm << markup(">");
1388 void ARMInstPrinter::printModImmOperand(const MCInst *MI, unsigned OpNum,
1389 const MCSubtargetInfo &STI,
1391 MCOperand Op = MI->getOperand(OpNum);
1393 // Support for fixups (MCFixup)
1395 return printOperand(MI, OpNum, STI, O);
1397 unsigned Bits = Op.getImm() & 0xFF;
1398 unsigned Rot = (Op.getImm() & 0xF00) >> 7;
1400 bool PrintUnsigned = false;
1401 switch (MI->getOpcode()) {
1403 // Movs to PC should be treated unsigned
1404 PrintUnsigned = (MI->getOperand(OpNum - 1).getReg() == ARM::PC);
1407 // Movs to special registers should be treated unsigned
1408 PrintUnsigned = true;
1412 int32_t Rotated = ARM_AM::rotr32(Bits, Rot);
1413 if (ARM_AM::getSOImmVal(Rotated) == Op.getImm()) {
1414 // #rot has the least possible value
1415 O << "#" << markup("<imm:");
1417 O << static_cast<uint32_t>(Rotated);
1424 // Explicit #bits, #rot implied
1425 O << "#" << markup("<imm:") << Bits << markup(">") << ", #" << markup("<imm:")
1426 << Rot << markup(">");
1429 void ARMInstPrinter::printFBits16(const MCInst *MI, unsigned OpNum,
1430 const MCSubtargetInfo &STI, raw_ostream &O) {
1431 O << markup("<imm:") << "#" << 16 - MI->getOperand(OpNum).getImm()
1435 void ARMInstPrinter::printFBits32(const MCInst *MI, unsigned OpNum,
1436 const MCSubtargetInfo &STI, raw_ostream &O) {
1437 O << markup("<imm:") << "#" << 32 - MI->getOperand(OpNum).getImm()
1441 void ARMInstPrinter::printVectorIndex(const MCInst *MI, unsigned OpNum,
1442 const MCSubtargetInfo &STI,
1444 O << "[" << MI->getOperand(OpNum).getImm() << "]";
1447 void ARMInstPrinter::printVectorListOne(const MCInst *MI, unsigned OpNum,
1448 const MCSubtargetInfo &STI,
1451 printRegName(O, MI->getOperand(OpNum).getReg());
1455 void ARMInstPrinter::printVectorListTwo(const MCInst *MI, unsigned OpNum,
1456 const MCSubtargetInfo &STI,
1458 unsigned Reg = MI->getOperand(OpNum).getReg();
1459 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0);
1460 unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_1);
1462 printRegName(O, Reg0);
1464 printRegName(O, Reg1);
1468 void ARMInstPrinter::printVectorListTwoSpaced(const MCInst *MI, unsigned OpNum,
1469 const MCSubtargetInfo &STI,
1471 unsigned Reg = MI->getOperand(OpNum).getReg();
1472 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0);
1473 unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_2);
1475 printRegName(O, Reg0);
1477 printRegName(O, Reg1);
1481 void ARMInstPrinter::printVectorListThree(const MCInst *MI, unsigned OpNum,
1482 const MCSubtargetInfo &STI,
1484 // Normally, it's not safe to use register enum values directly with
1485 // addition to get the next register, but for VFP registers, the
1486 // sort order is guaranteed because they're all of the form D<n>.
1488 printRegName(O, MI->getOperand(OpNum).getReg());
1490 printRegName(O, MI->getOperand(OpNum).getReg() + 1);
1492 printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1496 void ARMInstPrinter::printVectorListFour(const MCInst *MI, unsigned OpNum,
1497 const MCSubtargetInfo &STI,
1499 // Normally, it's not safe to use register enum values directly with
1500 // addition to get the next register, but for VFP registers, the
1501 // sort order is guaranteed because they're all of the form D<n>.
1503 printRegName(O, MI->getOperand(OpNum).getReg());
1505 printRegName(O, MI->getOperand(OpNum).getReg() + 1);
1507 printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1509 printRegName(O, MI->getOperand(OpNum).getReg() + 3);
1513 void ARMInstPrinter::printVectorListOneAllLanes(const MCInst *MI,
1515 const MCSubtargetInfo &STI,
1518 printRegName(O, MI->getOperand(OpNum).getReg());
1522 void ARMInstPrinter::printVectorListTwoAllLanes(const MCInst *MI,
1524 const MCSubtargetInfo &STI,
1526 unsigned Reg = MI->getOperand(OpNum).getReg();
1527 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0);
1528 unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_1);
1530 printRegName(O, Reg0);
1532 printRegName(O, Reg1);
1536 void ARMInstPrinter::printVectorListThreeAllLanes(const MCInst *MI,
1538 const MCSubtargetInfo &STI,
1540 // Normally, it's not safe to use register enum values directly with
1541 // addition to get the next register, but for VFP registers, the
1542 // sort order is guaranteed because they're all of the form D<n>.
1544 printRegName(O, MI->getOperand(OpNum).getReg());
1546 printRegName(O, MI->getOperand(OpNum).getReg() + 1);
1548 printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1552 void ARMInstPrinter::printVectorListFourAllLanes(const MCInst *MI,
1554 const MCSubtargetInfo &STI,
1556 // Normally, it's not safe to use register enum values directly with
1557 // addition to get the next register, but for VFP registers, the
1558 // sort order is guaranteed because they're all of the form D<n>.
1560 printRegName(O, MI->getOperand(OpNum).getReg());
1562 printRegName(O, MI->getOperand(OpNum).getReg() + 1);
1564 printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1566 printRegName(O, MI->getOperand(OpNum).getReg() + 3);
1570 void ARMInstPrinter::printVectorListTwoSpacedAllLanes(
1571 const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI,
1573 unsigned Reg = MI->getOperand(OpNum).getReg();
1574 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0);
1575 unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_2);
1577 printRegName(O, Reg0);
1579 printRegName(O, Reg1);
1583 void ARMInstPrinter::printVectorListThreeSpacedAllLanes(
1584 const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI,
1586 // Normally, it's not safe to use register enum values directly with
1587 // addition to get the next register, but for VFP registers, the
1588 // sort order is guaranteed because they're all of the form D<n>.
1590 printRegName(O, MI->getOperand(OpNum).getReg());
1592 printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1594 printRegName(O, MI->getOperand(OpNum).getReg() + 4);
1598 void ARMInstPrinter::printVectorListFourSpacedAllLanes(
1599 const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI,
1601 // Normally, it's not safe to use register enum values directly with
1602 // addition to get the next register, but for VFP registers, the
1603 // sort order is guaranteed because they're all of the form D<n>.
1605 printRegName(O, MI->getOperand(OpNum).getReg());
1607 printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1609 printRegName(O, MI->getOperand(OpNum).getReg() + 4);
1611 printRegName(O, MI->getOperand(OpNum).getReg() + 6);
1615 void ARMInstPrinter::printVectorListThreeSpaced(const MCInst *MI,
1617 const MCSubtargetInfo &STI,
1619 // Normally, it's not safe to use register enum values directly with
1620 // addition to get the next register, but for VFP registers, the
1621 // sort order is guaranteed because they're all of the form D<n>.
1623 printRegName(O, MI->getOperand(OpNum).getReg());
1625 printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1627 printRegName(O, MI->getOperand(OpNum).getReg() + 4);
1631 void ARMInstPrinter::printVectorListFourSpaced(const MCInst *MI, unsigned OpNum,
1632 const MCSubtargetInfo &STI,
1634 // Normally, it's not safe to use register enum values directly with
1635 // addition to get the next register, but for VFP registers, the
1636 // sort order is guaranteed because they're all of the form D<n>.
1638 printRegName(O, MI->getOperand(OpNum).getReg());
1640 printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1642 printRegName(O, MI->getOperand(OpNum).getReg() + 4);
1644 printRegName(O, MI->getOperand(OpNum).getReg() + 6);