1 //===-- ARMInstPrinter.cpp - Convert ARM MCInst to assembly syntax --------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This class prints an ARM MCInst to a .s file.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "asm-printer"
15 #include "ARMBaseInfo.h"
16 #include "ARMInstPrinter.h"
17 #include "ARMAddressingModes.h"
18 #include "llvm/MC/MCInst.h"
19 #include "llvm/MC/MCAsmInfo.h"
20 #include "llvm/MC/MCExpr.h"
21 #include "llvm/ADT/StringExtras.h"
22 #include "llvm/Support/raw_ostream.h"
25 #define GET_INSTRUCTION_NAME
26 #include "ARMGenAsmWriter.inc"
28 StringRef ARMInstPrinter::getOpcodeName(unsigned Opcode) const {
29 return getInstructionName(Opcode);
33 void ARMInstPrinter::printInst(const MCInst *MI, raw_ostream &O) {
34 unsigned Opcode = MI->getOpcode();
36 // Check for MOVs and print canonical forms, instead.
37 if (Opcode == ARM::MOVs) {
38 // FIXME: Thumb variants?
39 const MCOperand &Dst = MI->getOperand(0);
40 const MCOperand &MO1 = MI->getOperand(1);
41 const MCOperand &MO2 = MI->getOperand(2);
42 const MCOperand &MO3 = MI->getOperand(3);
44 O << '\t' << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO3.getImm()));
45 printSBitModifierOperand(MI, 6, O);
46 printPredicateOperand(MI, 4, O);
48 O << '\t' << getRegisterName(Dst.getReg())
49 << ", " << getRegisterName(MO1.getReg());
51 if (ARM_AM::getSORegShOp(MO3.getImm()) == ARM_AM::rrx)
57 O << getRegisterName(MO2.getReg());
58 assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0);
60 O << "#" << ARM_AM::getSORegOffset(MO3.getImm());
66 if ((Opcode == ARM::STMDB_UPD || Opcode == ARM::t2STMDB_UPD) &&
67 MI->getOperand(0).getReg() == ARM::SP) {
69 printPredicateOperand(MI, 2, O);
70 if (Opcode == ARM::t2STMDB_UPD)
73 printRegisterList(MI, 4, O);
78 if ((Opcode == ARM::LDMIA_UPD || Opcode == ARM::t2LDMIA_UPD) &&
79 MI->getOperand(0).getReg() == ARM::SP) {
81 printPredicateOperand(MI, 2, O);
82 if (Opcode == ARM::t2LDMIA_UPD)
85 printRegisterList(MI, 4, O);
90 if ((Opcode == ARM::VSTMSDB_UPD || Opcode == ARM::VSTMDDB_UPD) &&
91 MI->getOperand(0).getReg() == ARM::SP) {
93 printPredicateOperand(MI, 2, O);
95 printRegisterList(MI, 4, O);
100 if ((Opcode == ARM::VLDMSIA_UPD || Opcode == ARM::VLDMDIA_UPD) &&
101 MI->getOperand(0).getReg() == ARM::SP) {
103 printPredicateOperand(MI, 2, O);
105 printRegisterList(MI, 4, O);
109 printInstruction(MI, O);
112 void ARMInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
114 const MCOperand &Op = MI->getOperand(OpNo);
116 unsigned Reg = Op.getReg();
117 O << getRegisterName(Reg);
118 } else if (Op.isImm()) {
119 O << '#' << Op.getImm();
121 assert(Op.isExpr() && "unknown operand kind in printOperand");
126 static void printSOImm(raw_ostream &O, int64_t V, raw_ostream *CommentStream,
127 const MCAsmInfo *MAI) {
128 // Break it up into two parts that make up a shifter immediate.
129 V = ARM_AM::getSOImmVal(V);
130 assert(V != -1 && "Not a valid so_imm value!");
132 unsigned Imm = ARM_AM::getSOImmValImm(V);
133 unsigned Rot = ARM_AM::getSOImmValRot(V);
135 // Print low-level immediate formation info, per
136 // A5.1.3: "Data-processing operands - Immediate".
138 O << "#" << Imm << ", " << Rot;
139 // Pretty printed version.
141 *CommentStream << (int)ARM_AM::rotr32(Imm, Rot) << "\n";
148 /// printSOImmOperand - SOImm is 4-bit rotate amount in bits 8-11 with 8-bit
149 /// immediate in bits 0-7.
150 void ARMInstPrinter::printSOImmOperand(const MCInst *MI, unsigned OpNum,
152 const MCOperand &MO = MI->getOperand(OpNum);
153 assert(MO.isImm() && "Not a valid so_imm value!");
154 printSOImm(O, MO.getImm(), CommentStream, &MAI);
157 // so_reg is a 4-operand unit corresponding to register forms of the A5.1
158 // "Addressing Mode 1 - Data-processing operands" forms. This includes:
160 // REG REG 0,SH_OPC - e.g. R5, ROR R3
161 // REG 0 IMM,SH_OPC - e.g. R5, LSL #3
162 void ARMInstPrinter::printSORegOperand(const MCInst *MI, unsigned OpNum,
164 const MCOperand &MO1 = MI->getOperand(OpNum);
165 const MCOperand &MO2 = MI->getOperand(OpNum+1);
166 const MCOperand &MO3 = MI->getOperand(OpNum+2);
168 O << getRegisterName(MO1.getReg());
170 // Print the shift opc.
171 ARM_AM::ShiftOpc ShOpc = ARM_AM::getSORegShOp(MO3.getImm());
172 O << ", " << ARM_AM::getShiftOpcStr(ShOpc);
174 O << ' ' << getRegisterName(MO2.getReg());
175 assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0);
176 } else if (ShOpc != ARM_AM::rrx) {
177 O << " #" << ARM_AM::getSORegOffset(MO3.getImm());
182 void ARMInstPrinter::printAddrMode2Operand(const MCInst *MI, unsigned Op,
184 const MCOperand &MO1 = MI->getOperand(Op);
185 const MCOperand &MO2 = MI->getOperand(Op+1);
186 const MCOperand &MO3 = MI->getOperand(Op+2);
188 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
189 printOperand(MI, Op, O);
193 O << "[" << getRegisterName(MO1.getReg());
196 if (ARM_AM::getAM2Offset(MO3.getImm())) // Don't print +0.
198 << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm()))
199 << ARM_AM::getAM2Offset(MO3.getImm());
205 << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm()))
206 << getRegisterName(MO2.getReg());
208 if (unsigned ShImm = ARM_AM::getAM2Offset(MO3.getImm()))
210 << ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO3.getImm()))
215 void ARMInstPrinter::printAddrMode2OffsetOperand(const MCInst *MI,
218 const MCOperand &MO1 = MI->getOperand(OpNum);
219 const MCOperand &MO2 = MI->getOperand(OpNum+1);
222 unsigned ImmOffs = ARM_AM::getAM2Offset(MO2.getImm());
224 << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO2.getImm()))
229 O << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO2.getImm()))
230 << getRegisterName(MO1.getReg());
232 if (unsigned ShImm = ARM_AM::getAM2Offset(MO2.getImm()))
234 << ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO2.getImm()))
238 void ARMInstPrinter::printAddrMode3Operand(const MCInst *MI, unsigned OpNum,
240 const MCOperand &MO1 = MI->getOperand(OpNum);
241 const MCOperand &MO2 = MI->getOperand(OpNum+1);
242 const MCOperand &MO3 = MI->getOperand(OpNum+2);
244 O << '[' << getRegisterName(MO1.getReg());
247 O << ", " << (char)ARM_AM::getAM3Op(MO3.getImm())
248 << getRegisterName(MO2.getReg()) << ']';
252 if (unsigned ImmOffs = ARM_AM::getAM3Offset(MO3.getImm()))
254 << ARM_AM::getAddrOpcStr(ARM_AM::getAM3Op(MO3.getImm()))
259 void ARMInstPrinter::printAddrMode3OffsetOperand(const MCInst *MI,
262 const MCOperand &MO1 = MI->getOperand(OpNum);
263 const MCOperand &MO2 = MI->getOperand(OpNum+1);
266 O << (char)ARM_AM::getAM3Op(MO2.getImm())
267 << getRegisterName(MO1.getReg());
271 unsigned ImmOffs = ARM_AM::getAM3Offset(MO2.getImm());
273 << ARM_AM::getAddrOpcStr(ARM_AM::getAM3Op(MO2.getImm()))
277 void ARMInstPrinter::printLdStmModeOperand(const MCInst *MI, unsigned OpNum,
279 ARM_AM::AMSubMode Mode = ARM_AM::getAM4SubMode(MI->getOperand(OpNum)
281 O << ARM_AM::getAMSubModeStr(Mode);
284 void ARMInstPrinter::printAddrMode5Operand(const MCInst *MI, unsigned OpNum,
286 const MCOperand &MO1 = MI->getOperand(OpNum);
287 const MCOperand &MO2 = MI->getOperand(OpNum+1);
289 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
290 printOperand(MI, OpNum, O);
294 O << "[" << getRegisterName(MO1.getReg());
296 if (unsigned ImmOffs = ARM_AM::getAM5Offset(MO2.getImm())) {
298 << ARM_AM::getAddrOpcStr(ARM_AM::getAM5Op(MO2.getImm()))
304 void ARMInstPrinter::printAddrMode6Operand(const MCInst *MI, unsigned OpNum,
306 const MCOperand &MO1 = MI->getOperand(OpNum);
307 const MCOperand &MO2 = MI->getOperand(OpNum+1);
309 O << "[" << getRegisterName(MO1.getReg());
311 // FIXME: Both darwin as and GNU as violate ARM docs here.
312 O << ", :" << (MO2.getImm() << 3);
317 void ARMInstPrinter::printAddrMode6OffsetOperand(const MCInst *MI,
320 const MCOperand &MO = MI->getOperand(OpNum);
321 if (MO.getReg() == 0)
324 O << ", " << getRegisterName(MO.getReg());
327 void ARMInstPrinter::printBitfieldInvMaskImmOperand(const MCInst *MI,
330 const MCOperand &MO = MI->getOperand(OpNum);
331 uint32_t v = ~MO.getImm();
332 int32_t lsb = CountTrailingZeros_32(v);
333 int32_t width = (32 - CountLeadingZeros_32 (v)) - lsb;
334 assert(MO.isImm() && "Not a valid bf_inv_mask_imm value!");
335 O << '#' << lsb << ", #" << width;
338 void ARMInstPrinter::printMemBOption(const MCInst *MI, unsigned OpNum,
340 unsigned val = MI->getOperand(OpNum).getImm();
341 O << ARM_MB::MemBOptToString(val);
344 void ARMInstPrinter::printShiftImmOperand(const MCInst *MI, unsigned OpNum,
346 unsigned ShiftOp = MI->getOperand(OpNum).getImm();
347 ARM_AM::ShiftOpc Opc = ARM_AM::getSORegShOp(ShiftOp);
349 case ARM_AM::no_shift:
358 assert(0 && "unexpected shift opcode for shift immediate operand");
360 O << ARM_AM::getSORegOffset(ShiftOp);
363 void ARMInstPrinter::printRegisterList(const MCInst *MI, unsigned OpNum,
366 for (unsigned i = OpNum, e = MI->getNumOperands(); i != e; ++i) {
367 if (i != OpNum) O << ", ";
368 O << getRegisterName(MI->getOperand(i).getReg());
373 void ARMInstPrinter::printSetendOperand(const MCInst *MI, unsigned OpNum,
375 const MCOperand &Op = MI->getOperand(OpNum);
382 void ARMInstPrinter::printCPSOptionOperand(const MCInst *MI, unsigned OpNum,
384 const MCOperand &Op = MI->getOperand(OpNum);
385 unsigned option = Op.getImm();
386 unsigned mode = option & 31;
387 bool changemode = option >> 5 & 1;
388 unsigned AIF = option >> 6 & 7;
389 unsigned imod = option >> 9 & 3;
396 if (AIF & 4) O << 'a';
397 if (AIF & 2) O << 'i';
398 if (AIF & 1) O << 'f';
399 if (AIF > 0 && changemode) O << ", ";
405 void ARMInstPrinter::printMSRMaskOperand(const MCInst *MI, unsigned OpNum,
407 const MCOperand &Op = MI->getOperand(OpNum);
408 unsigned Mask = Op.getImm();
411 if (Mask & 8) O << 'f';
412 if (Mask & 4) O << 's';
413 if (Mask & 2) O << 'x';
414 if (Mask & 1) O << 'c';
418 void ARMInstPrinter::printNegZeroOperand(const MCInst *MI, unsigned OpNum,
420 const MCOperand &Op = MI->getOperand(OpNum);
423 O << '-' << (-Op.getImm() - 1);
428 void ARMInstPrinter::printPredicateOperand(const MCInst *MI, unsigned OpNum,
430 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
432 O << ARMCondCodeToString(CC);
435 void ARMInstPrinter::printMandatoryPredicateOperand(const MCInst *MI,
438 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
439 O << ARMCondCodeToString(CC);
442 void ARMInstPrinter::printSBitModifierOperand(const MCInst *MI, unsigned OpNum,
444 if (MI->getOperand(OpNum).getReg()) {
445 assert(MI->getOperand(OpNum).getReg() == ARM::CPSR &&
446 "Expect ARM CPSR register!");
451 void ARMInstPrinter::printNoHashImmediate(const MCInst *MI, unsigned OpNum,
453 O << MI->getOperand(OpNum).getImm();
456 void ARMInstPrinter::printPCLabel(const MCInst *MI, unsigned OpNum,
458 llvm_unreachable("Unhandled PC-relative pseudo-instruction!");
461 void ARMInstPrinter::printThumbS4ImmOperand(const MCInst *MI, unsigned OpNum,
463 O << "#" << MI->getOperand(OpNum).getImm() * 4;
466 void ARMInstPrinter::printThumbITMask(const MCInst *MI, unsigned OpNum,
468 // (3 - the number of trailing zeros) is the number of then / else.
469 unsigned Mask = MI->getOperand(OpNum).getImm();
470 unsigned CondBit0 = Mask >> 4 & 1;
471 unsigned NumTZ = CountTrailingZeros_32(Mask);
472 assert(NumTZ <= 3 && "Invalid IT mask!");
473 for (unsigned Pos = 3, e = NumTZ; Pos > e; --Pos) {
474 bool T = ((Mask >> Pos) & 1) == CondBit0;
482 void ARMInstPrinter::printThumbAddrModeRROperand(const MCInst *MI, unsigned Op,
484 const MCOperand &MO1 = MI->getOperand(Op);
485 const MCOperand &MO2 = MI->getOperand(Op + 1);
487 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
488 printOperand(MI, Op, O);
492 O << "[" << getRegisterName(MO1.getReg());
493 if (unsigned RegNum = MO2.getReg())
494 O << ", " << getRegisterName(RegNum);
498 void ARMInstPrinter::printThumbAddrModeImm5SOperand(const MCInst *MI,
502 const MCOperand &MO1 = MI->getOperand(Op);
503 const MCOperand &MO2 = MI->getOperand(Op + 1);
505 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
506 printOperand(MI, Op, O);
510 O << "[" << getRegisterName(MO1.getReg());
511 if (unsigned ImmOffs = MO2.getImm())
512 O << ", #" << ImmOffs * Scale;
516 void ARMInstPrinter::printThumbAddrModeImm5S1Operand(const MCInst *MI,
519 printThumbAddrModeImm5SOperand(MI, Op, O, 1);
522 void ARMInstPrinter::printThumbAddrModeImm5S2Operand(const MCInst *MI,
525 printThumbAddrModeImm5SOperand(MI, Op, O, 2);
528 void ARMInstPrinter::printThumbAddrModeImm5S4Operand(const MCInst *MI,
531 printThumbAddrModeImm5SOperand(MI, Op, O, 4);
534 void ARMInstPrinter::printThumbAddrModeSPOperand(const MCInst *MI, unsigned Op,
536 printThumbAddrModeImm5SOperand(MI, Op, O, 4);
539 // Constant shifts t2_so_reg is a 2-operand unit corresponding to the Thumb2
540 // register with shift forms.
542 // REG IMM, SH_OPC - e.g. R5, LSL #3
543 void ARMInstPrinter::printT2SOOperand(const MCInst *MI, unsigned OpNum,
545 const MCOperand &MO1 = MI->getOperand(OpNum);
546 const MCOperand &MO2 = MI->getOperand(OpNum+1);
548 unsigned Reg = MO1.getReg();
549 O << getRegisterName(Reg);
551 // Print the shift opc.
552 assert(MO2.isImm() && "Not a valid t2_so_reg value!");
553 ARM_AM::ShiftOpc ShOpc = ARM_AM::getSORegShOp(MO2.getImm());
554 O << ", " << ARM_AM::getShiftOpcStr(ShOpc);
555 if (ShOpc != ARM_AM::rrx)
556 O << " #" << ARM_AM::getSORegOffset(MO2.getImm());
559 void ARMInstPrinter::printAddrModeImm12Operand(const MCInst *MI, unsigned OpNum,
561 const MCOperand &MO1 = MI->getOperand(OpNum);
562 const MCOperand &MO2 = MI->getOperand(OpNum+1);
564 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
565 printOperand(MI, OpNum, O);
567 } else if (MO1.getReg() == ARM::PC && MO2.isExpr()) {
568 printOperand(MI, OpNum+1, O);
572 O << "[" << getRegisterName(MO1.getReg());
574 int32_t OffImm = (int32_t)MO2.getImm();
575 bool isSub = OffImm < 0;
576 // Special value for #-0. All others are normal.
577 if (OffImm == INT32_MIN)
580 O << ", #-" << -OffImm;
582 O << ", #" << OffImm;
586 void ARMInstPrinter::printT2AddrModeImm8Operand(const MCInst *MI,
589 const MCOperand &MO1 = MI->getOperand(OpNum);
590 const MCOperand &MO2 = MI->getOperand(OpNum+1);
592 O << "[" << getRegisterName(MO1.getReg());
594 int32_t OffImm = (int32_t)MO2.getImm();
597 O << ", #-" << -OffImm;
599 O << ", #" << OffImm;
603 void ARMInstPrinter::printT2AddrModeImm8s4Operand(const MCInst *MI,
606 const MCOperand &MO1 = MI->getOperand(OpNum);
607 const MCOperand &MO2 = MI->getOperand(OpNum+1);
609 O << "[" << getRegisterName(MO1.getReg());
611 int32_t OffImm = (int32_t)MO2.getImm() / 4;
614 O << ", #-" << -OffImm * 4;
616 O << ", #" << OffImm * 4;
620 void ARMInstPrinter::printT2AddrModeImm8OffsetOperand(const MCInst *MI,
623 const MCOperand &MO1 = MI->getOperand(OpNum);
624 int32_t OffImm = (int32_t)MO1.getImm();
627 O << "#-" << -OffImm;
632 void ARMInstPrinter::printT2AddrModeImm8s4OffsetOperand(const MCInst *MI,
635 const MCOperand &MO1 = MI->getOperand(OpNum);
636 int32_t OffImm = (int32_t)MO1.getImm() / 4;
639 O << "#-" << -OffImm * 4;
641 O << "#" << OffImm * 4;
644 void ARMInstPrinter::printT2AddrModeSoRegOperand(const MCInst *MI,
647 const MCOperand &MO1 = MI->getOperand(OpNum);
648 const MCOperand &MO2 = MI->getOperand(OpNum+1);
649 const MCOperand &MO3 = MI->getOperand(OpNum+2);
651 O << "[" << getRegisterName(MO1.getReg());
653 assert(MO2.getReg() && "Invalid so_reg load / store address!");
654 O << ", " << getRegisterName(MO2.getReg());
656 unsigned ShAmt = MO3.getImm();
658 assert(ShAmt <= 3 && "Not a valid Thumb2 addressing mode!");
659 O << ", lsl #" << ShAmt;
664 void ARMInstPrinter::printVFPf32ImmOperand(const MCInst *MI, unsigned OpNum,
666 O << '#' << (float)MI->getOperand(OpNum).getFPImm();
669 void ARMInstPrinter::printVFPf64ImmOperand(const MCInst *MI, unsigned OpNum,
671 O << '#' << MI->getOperand(OpNum).getFPImm();
674 void ARMInstPrinter::printNEONModImmOperand(const MCInst *MI, unsigned OpNum,
676 unsigned EncodedImm = MI->getOperand(OpNum).getImm();
678 uint64_t Val = ARM_AM::decodeNEONModImm(EncodedImm, EltBits);
679 O << "#0x" << utohexstr(Val);