1 //===- ARMDisassemblerCore.cpp - ARM disassembler helpers -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file is part of the ARM Disassembler.
11 // It contains code to represent the core concepts of Builder and DisassembleFP
12 // to solve the problem of disassembling an ARM instr.
14 //===----------------------------------------------------------------------===//
16 #define DEBUG_TYPE "arm-disassembler"
18 #include "ARMDisassemblerCore.h"
19 #include "ARMAddressingModes.h"
20 #include "llvm/Support/Debug.h"
21 #include "llvm/Support/raw_ostream.h"
23 //#define DEBUG(X) do { X; } while (0)
25 /// ARMGenInstrInfo.inc - ARMGenInstrInfo.inc contains the static const
26 /// TargetInstrDesc ARMInsts[] definition and the TargetOperandInfo[]'s
27 /// describing the operand info for each ARMInsts[i].
29 /// Together with an instruction's encoding format, we can take advantage of the
30 /// NumOperands and the OpInfo fields of the target instruction description in
31 /// the quest to build out the MCOperand list for an MCInst.
33 /// The general guideline is that with a known format, the number of dst and src
34 /// operands are well-known. The dst is built first, followed by the src
35 /// operand(s). The operands not yet used at this point are for the Implicit
36 /// Uses and Defs by this instr. For the Uses part, the pred:$p operand is
37 /// defined with two components:
39 /// def pred { // Operand PredicateOperand
40 /// ValueType Type = OtherVT;
41 /// string PrintMethod = "printPredicateOperand";
42 /// string AsmOperandLowerMethod = ?;
43 /// dag MIOperandInfo = (ops i32imm, CCR);
44 /// AsmOperandClass ParserMatchClass = ImmAsmOperand;
45 /// dag DefaultOps = (ops (i32 14), (i32 zero_reg));
48 /// which is manifested by the TargetOperandInfo[] of:
50 /// { 0, 0|(1<<TOI::Predicate), 0 },
51 /// { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }
53 /// So the first predicate MCOperand corresponds to the immediate part of the
54 /// ARM condition field (Inst{31-28}), and the second predicate MCOperand
55 /// corresponds to a register kind of ARM::CPSR.
57 /// For the Defs part, in the simple case of only cc_out:$s, we have:
59 /// def cc_out { // Operand OptionalDefOperand
60 /// ValueType Type = OtherVT;
61 /// string PrintMethod = "printSBitModifierOperand";
62 /// string AsmOperandLowerMethod = ?;
63 /// dag MIOperandInfo = (ops CCR);
64 /// AsmOperandClass ParserMatchClass = ImmAsmOperand;
65 /// dag DefaultOps = (ops (i32 zero_reg));
68 /// which is manifested by the one TargetOperandInfo of:
70 /// { ARM::CCRRegClassID, 0|(1<<TOI::OptionalDef), 0 }
72 /// And this maps to one MCOperand with the regsiter kind of ARM::CPSR.
73 #include "ARMGenInstrInfo.inc"
77 const char *ARMUtils::OpcodeName(unsigned Opcode) {
78 return ARMInsts[Opcode].Name;
81 // Return the register enum Based on RegClass and the raw register number.
84 getRegisterEnum(BO B, unsigned RegClassID, unsigned RawRegister) {
85 // For this purpose, we can treat rGPR as if it were GPR.
86 if (RegClassID == ARM::rGPRRegClassID) RegClassID = ARM::GPRRegClassID;
88 // See also decodeNEONRd(), decodeNEONRn(), decodeNEONRm().
90 RegClassID == ARM::QPRRegClassID ? RawRegister >> 1 : RawRegister;
97 case ARM::GPRRegClassID: case ARM::tGPRRegClassID: return ARM::R0;
98 case ARM::DPRRegClassID: case ARM::DPR_8RegClassID:
99 case ARM::DPR_VFP2RegClassID:
101 case ARM::QPRRegClassID: case ARM::QPR_8RegClassID:
102 case ARM::QPR_VFP2RegClassID:
104 case ARM::SPRRegClassID: case ARM::SPR_8RegClassID: return ARM::S0;
108 switch (RegClassID) {
109 case ARM::GPRRegClassID: case ARM::tGPRRegClassID: return ARM::R1;
110 case ARM::DPRRegClassID: case ARM::DPR_8RegClassID:
111 case ARM::DPR_VFP2RegClassID:
113 case ARM::QPRRegClassID: case ARM::QPR_8RegClassID:
114 case ARM::QPR_VFP2RegClassID:
116 case ARM::SPRRegClassID: case ARM::SPR_8RegClassID: return ARM::S1;
120 switch (RegClassID) {
121 case ARM::GPRRegClassID: case ARM::tGPRRegClassID: return ARM::R2;
122 case ARM::DPRRegClassID: case ARM::DPR_8RegClassID:
123 case ARM::DPR_VFP2RegClassID:
125 case ARM::QPRRegClassID: case ARM::QPR_8RegClassID:
126 case ARM::QPR_VFP2RegClassID:
128 case ARM::SPRRegClassID: case ARM::SPR_8RegClassID: return ARM::S2;
132 switch (RegClassID) {
133 case ARM::GPRRegClassID: case ARM::tGPRRegClassID: return ARM::R3;
134 case ARM::DPRRegClassID: case ARM::DPR_8RegClassID:
135 case ARM::DPR_VFP2RegClassID:
137 case ARM::QPRRegClassID: case ARM::QPR_8RegClassID:
138 case ARM::QPR_VFP2RegClassID:
140 case ARM::SPRRegClassID: case ARM::SPR_8RegClassID: return ARM::S3;
144 switch (RegClassID) {
145 case ARM::GPRRegClassID: case ARM::tGPRRegClassID: return ARM::R4;
146 case ARM::DPRRegClassID: case ARM::DPR_8RegClassID:
147 case ARM::DPR_VFP2RegClassID:
149 case ARM::QPRRegClassID: case ARM::QPR_VFP2RegClassID: return ARM::Q4;
150 case ARM::SPRRegClassID: case ARM::SPR_8RegClassID: return ARM::S4;
154 switch (RegClassID) {
155 case ARM::GPRRegClassID: case ARM::tGPRRegClassID: return ARM::R5;
156 case ARM::DPRRegClassID: case ARM::DPR_8RegClassID:
157 case ARM::DPR_VFP2RegClassID:
159 case ARM::QPRRegClassID: case ARM::QPR_VFP2RegClassID: return ARM::Q5;
160 case ARM::SPRRegClassID: case ARM::SPR_8RegClassID: return ARM::S5;
164 switch (RegClassID) {
165 case ARM::GPRRegClassID: case ARM::tGPRRegClassID: return ARM::R6;
166 case ARM::DPRRegClassID: case ARM::DPR_8RegClassID:
167 case ARM::DPR_VFP2RegClassID:
169 case ARM::QPRRegClassID: case ARM::QPR_VFP2RegClassID: return ARM::Q6;
170 case ARM::SPRRegClassID: case ARM::SPR_8RegClassID: return ARM::S6;
174 switch (RegClassID) {
175 case ARM::GPRRegClassID: case ARM::tGPRRegClassID: return ARM::R7;
176 case ARM::DPRRegClassID: case ARM::DPR_8RegClassID:
177 case ARM::DPR_VFP2RegClassID:
179 case ARM::QPRRegClassID: case ARM::QPR_VFP2RegClassID: return ARM::Q7;
180 case ARM::SPRRegClassID: case ARM::SPR_8RegClassID: return ARM::S7;
184 switch (RegClassID) {
185 case ARM::GPRRegClassID: return ARM::R8;
186 case ARM::DPRRegClassID: case ARM::DPR_VFP2RegClassID: return ARM::D8;
187 case ARM::QPRRegClassID: return ARM::Q8;
188 case ARM::SPRRegClassID: case ARM::SPR_8RegClassID: return ARM::S8;
192 switch (RegClassID) {
193 case ARM::GPRRegClassID: return ARM::R9;
194 case ARM::DPRRegClassID: case ARM::DPR_VFP2RegClassID: return ARM::D9;
195 case ARM::QPRRegClassID: return ARM::Q9;
196 case ARM::SPRRegClassID: case ARM::SPR_8RegClassID: return ARM::S9;
200 switch (RegClassID) {
201 case ARM::GPRRegClassID: return ARM::R10;
202 case ARM::DPRRegClassID: case ARM::DPR_VFP2RegClassID: return ARM::D10;
203 case ARM::QPRRegClassID: return ARM::Q10;
204 case ARM::SPRRegClassID: case ARM::SPR_8RegClassID: return ARM::S10;
208 switch (RegClassID) {
209 case ARM::GPRRegClassID: return ARM::R11;
210 case ARM::DPRRegClassID: case ARM::DPR_VFP2RegClassID: return ARM::D11;
211 case ARM::QPRRegClassID: return ARM::Q11;
212 case ARM::SPRRegClassID: case ARM::SPR_8RegClassID: return ARM::S11;
216 switch (RegClassID) {
217 case ARM::GPRRegClassID: return ARM::R12;
218 case ARM::DPRRegClassID: case ARM::DPR_VFP2RegClassID: return ARM::D12;
219 case ARM::QPRRegClassID: return ARM::Q12;
220 case ARM::SPRRegClassID: case ARM::SPR_8RegClassID: return ARM::S12;
224 switch (RegClassID) {
225 case ARM::GPRRegClassID: return ARM::SP;
226 case ARM::DPRRegClassID: case ARM::DPR_VFP2RegClassID: return ARM::D13;
227 case ARM::QPRRegClassID: return ARM::Q13;
228 case ARM::SPRRegClassID: case ARM::SPR_8RegClassID: return ARM::S13;
232 switch (RegClassID) {
233 case ARM::GPRRegClassID: return ARM::LR;
234 case ARM::DPRRegClassID: case ARM::DPR_VFP2RegClassID: return ARM::D14;
235 case ARM::QPRRegClassID: return ARM::Q14;
236 case ARM::SPRRegClassID: case ARM::SPR_8RegClassID: return ARM::S14;
240 switch (RegClassID) {
241 case ARM::GPRRegClassID: return ARM::PC;
242 case ARM::DPRRegClassID: case ARM::DPR_VFP2RegClassID: return ARM::D15;
243 case ARM::QPRRegClassID: return ARM::Q15;
244 case ARM::SPRRegClassID: case ARM::SPR_8RegClassID: return ARM::S15;
248 switch (RegClassID) {
249 case ARM::DPRRegClassID: return ARM::D16;
250 case ARM::SPRRegClassID: return ARM::S16;
254 switch (RegClassID) {
255 case ARM::DPRRegClassID: return ARM::D17;
256 case ARM::SPRRegClassID: return ARM::S17;
260 switch (RegClassID) {
261 case ARM::DPRRegClassID: return ARM::D18;
262 case ARM::SPRRegClassID: return ARM::S18;
266 switch (RegClassID) {
267 case ARM::DPRRegClassID: return ARM::D19;
268 case ARM::SPRRegClassID: return ARM::S19;
272 switch (RegClassID) {
273 case ARM::DPRRegClassID: return ARM::D20;
274 case ARM::SPRRegClassID: return ARM::S20;
278 switch (RegClassID) {
279 case ARM::DPRRegClassID: return ARM::D21;
280 case ARM::SPRRegClassID: return ARM::S21;
284 switch (RegClassID) {
285 case ARM::DPRRegClassID: return ARM::D22;
286 case ARM::SPRRegClassID: return ARM::S22;
290 switch (RegClassID) {
291 case ARM::DPRRegClassID: return ARM::D23;
292 case ARM::SPRRegClassID: return ARM::S23;
296 switch (RegClassID) {
297 case ARM::DPRRegClassID: return ARM::D24;
298 case ARM::SPRRegClassID: return ARM::S24;
302 switch (RegClassID) {
303 case ARM::DPRRegClassID: return ARM::D25;
304 case ARM::SPRRegClassID: return ARM::S25;
308 switch (RegClassID) {
309 case ARM::DPRRegClassID: return ARM::D26;
310 case ARM::SPRRegClassID: return ARM::S26;
314 switch (RegClassID) {
315 case ARM::DPRRegClassID: return ARM::D27;
316 case ARM::SPRRegClassID: return ARM::S27;
320 switch (RegClassID) {
321 case ARM::DPRRegClassID: return ARM::D28;
322 case ARM::SPRRegClassID: return ARM::S28;
326 switch (RegClassID) {
327 case ARM::DPRRegClassID: return ARM::D29;
328 case ARM::SPRRegClassID: return ARM::S29;
332 switch (RegClassID) {
333 case ARM::DPRRegClassID: return ARM::D30;
334 case ARM::SPRRegClassID: return ARM::S30;
338 switch (RegClassID) {
339 case ARM::DPRRegClassID: return ARM::D31;
340 case ARM::SPRRegClassID: return ARM::S31;
344 DEBUG(errs() << "Invalid (RegClassID, RawRegister) combination\n");
345 // Encoding error. Mark the builder with error code != 0.
350 ///////////////////////////////
352 // Utility Functions //
354 ///////////////////////////////
356 // Extract/Decode Rd: Inst{15-12}.
357 static inline unsigned decodeRd(uint32_t insn) {
358 return (insn >> ARMII::RegRdShift) & ARMII::GPRRegMask;
361 // Extract/Decode Rn: Inst{19-16}.
362 static inline unsigned decodeRn(uint32_t insn) {
363 return (insn >> ARMII::RegRnShift) & ARMII::GPRRegMask;
366 // Extract/Decode Rm: Inst{3-0}.
367 static inline unsigned decodeRm(uint32_t insn) {
368 return (insn & ARMII::GPRRegMask);
371 // Extract/Decode Rs: Inst{11-8}.
372 static inline unsigned decodeRs(uint32_t insn) {
373 return (insn >> ARMII::RegRsShift) & ARMII::GPRRegMask;
376 static inline unsigned getCondField(uint32_t insn) {
377 return (insn >> ARMII::CondShift);
380 static inline unsigned getIBit(uint32_t insn) {
381 return (insn >> ARMII::I_BitShift) & 1;
384 static inline unsigned getAM3IBit(uint32_t insn) {
385 return (insn >> ARMII::AM3_I_BitShift) & 1;
388 static inline unsigned getPBit(uint32_t insn) {
389 return (insn >> ARMII::P_BitShift) & 1;
392 static inline unsigned getUBit(uint32_t insn) {
393 return (insn >> ARMII::U_BitShift) & 1;
396 static inline unsigned getPUBits(uint32_t insn) {
397 return (insn >> ARMII::U_BitShift) & 3;
400 static inline unsigned getSBit(uint32_t insn) {
401 return (insn >> ARMII::S_BitShift) & 1;
404 static inline unsigned getWBit(uint32_t insn) {
405 return (insn >> ARMII::W_BitShift) & 1;
408 static inline unsigned getDBit(uint32_t insn) {
409 return (insn >> ARMII::D_BitShift) & 1;
412 static inline unsigned getNBit(uint32_t insn) {
413 return (insn >> ARMII::N_BitShift) & 1;
416 static inline unsigned getMBit(uint32_t insn) {
417 return (insn >> ARMII::M_BitShift) & 1;
420 // See A8.4 Shifts applied to a register.
421 // A8.4.2 Register controlled shifts.
423 // getShiftOpcForBits - getShiftOpcForBits translates from the ARM encoding bits
424 // into llvm enums for shift opcode. The API clients should pass in the value
425 // encoded with two bits, so the assert stays to signal a wrong API usage.
427 // A8-12: DecodeRegShift()
428 static inline ARM_AM::ShiftOpc getShiftOpcForBits(unsigned bits) {
430 default: assert(0 && "No such value"); return ARM_AM::no_shift;
431 case 0: return ARM_AM::lsl;
432 case 1: return ARM_AM::lsr;
433 case 2: return ARM_AM::asr;
434 case 3: return ARM_AM::ror;
438 // See A8.4 Shifts applied to a register.
439 // A8.4.1 Constant shifts.
441 // getImmShiftSE - getImmShiftSE translates from the raw ShiftOpc and raw Imm5
442 // encodings into the intended ShiftOpc and shift amount.
444 // A8-11: DecodeImmShift()
445 static inline void getImmShiftSE(ARM_AM::ShiftOpc &ShOp, unsigned &ShImm) {
449 case ARM_AM::no_shift:
453 ShOp = ARM_AM::no_shift;
465 // getAMSubModeForBits - getAMSubModeForBits translates from the ARM encoding
466 // bits Inst{24-23} (P(24) and U(23)) into llvm enums for AMSubMode. The API
467 // clients should pass in the value encoded with two bits, so the assert stays
468 // to signal a wrong API usage.
469 static inline ARM_AM::AMSubMode getAMSubModeForBits(unsigned bits) {
471 default: assert(0 && "No such value"); return ARM_AM::bad_am_submode;
472 case 1: return ARM_AM::ia; // P=0 U=1
473 case 3: return ARM_AM::ib; // P=1 U=1
474 case 0: return ARM_AM::da; // P=0 U=0
475 case 2: return ARM_AM::db; // P=1 U=0
479 ////////////////////////////////////////////
481 // Disassemble function definitions //
483 ////////////////////////////////////////////
485 /// There is a separate Disassemble*Frm function entry for disassembly of an ARM
486 /// instr into a list of MCOperands in the appropriate order, with possible dst,
487 /// followed by possible src(s).
489 /// The processing of the predicate, and the 'S' modifier bit, if MI modifies
490 /// the CPSR, is factored into ARMBasicMCBuilder's method named
491 /// TryPredicateAndSBitModifier.
493 static bool DisassemblePseudo(MCInst &MI, unsigned Opcode, uint32_t insn,
494 unsigned short NumOps, unsigned &NumOpsAdded, BO) {
496 assert(0 && "Unexpected pseudo instruction!");
500 // Multiply Instructions.
501 // MLA, MLS, SMLABB, SMLABT, SMLATB, SMLATT, SMLAWB, SMLAWT, SMMLA, SMMLS:
502 // Rd{19-16} Rn{3-0} Rm{11-8} Ra{15-12}
504 // MUL, SMMUL, SMULBB, SMULBT, SMULTB, SMULTT, SMULWB, SMULWT:
505 // Rd{19-16} Rn{3-0} Rm{11-8}
507 // SMLAL, SMULL, UMAAL, UMLAL, UMULL, SMLALBB, SMLALBT, SMLALTB, SMLALTT:
508 // RdLo{15-12} RdHi{19-16} Rn{3-0} Rm{11-8}
510 // The mapping of the multiply registers to the "regular" ARM registers, where
511 // there are convenience decoder functions, is:
517 static bool DisassembleMulFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
518 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
520 const TargetInstrDesc &TID = ARMInsts[Opcode];
521 unsigned short NumDefs = TID.getNumDefs();
522 const TargetOperandInfo *OpInfo = TID.OpInfo;
523 unsigned &OpIdx = NumOpsAdded;
527 assert(NumDefs > 0 && "NumDefs should be greater than 0 for MulFrm");
529 && OpInfo[0].RegClass == ARM::GPRRegClassID
530 && OpInfo[1].RegClass == ARM::GPRRegClassID
531 && OpInfo[2].RegClass == ARM::GPRRegClassID
532 && "Expect three register operands");
534 // Instructions with two destination registers have RdLo{15-12} first.
536 assert(NumOps >= 4 && OpInfo[3].RegClass == ARM::GPRRegClassID &&
537 "Expect 4th register operand");
538 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
543 // The destination register: RdHi{19-16} or Rd{19-16}.
544 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
547 // The two src regsiters: Rn{3-0}, then Rm{11-8}.
548 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
550 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
554 // Many multiply instructions (e.g., MLA) have three src registers.
555 // The third register operand is Ra{15-12}.
556 if (OpIdx < NumOps && OpInfo[OpIdx].RegClass == ARM::GPRRegClassID) {
557 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
565 // Helper routines for disassembly of coprocessor instructions.
567 static bool LdStCopOpcode(unsigned Opcode) {
568 if ((Opcode >= ARM::LDC2L_OFFSET && Opcode <= ARM::LDC_PRE) ||
569 (Opcode >= ARM::STC2L_OFFSET && Opcode <= ARM::STC_PRE))
573 static bool CoprocessorOpcode(unsigned Opcode) {
574 if (LdStCopOpcode(Opcode))
580 case ARM::CDP: case ARM::CDP2:
581 case ARM::MCR: case ARM::MCR2: case ARM::MRC: case ARM::MRC2:
582 case ARM::MCRR: case ARM::MCRR2: case ARM::MRRC: case ARM::MRRC2:
586 static inline unsigned GetCoprocessor(uint32_t insn) {
587 return slice(insn, 11, 8);
589 static inline unsigned GetCopOpc1(uint32_t insn, bool CDP) {
590 return CDP ? slice(insn, 23, 20) : slice(insn, 23, 21);
592 static inline unsigned GetCopOpc2(uint32_t insn) {
593 return slice(insn, 7, 5);
595 static inline unsigned GetCopOpc(uint32_t insn) {
596 return slice(insn, 7, 4);
598 // Most of the operands are in immediate forms, except Rd and Rn, which are ARM
601 // CDP, CDP2: cop opc1 CRd CRn CRm opc2
603 // MCR, MCR2, MRC, MRC2: cop opc1 Rd CRn CRm opc2
605 // MCRR, MCRR2, MRRC, MRRc2: cop opc Rd Rn CRm
607 // LDC_OFFSET, LDC_PRE, LDC_POST: cop CRd Rn R0 [+/-]imm8:00
609 // STC_OFFSET, STC_PRE, STC_POST: cop CRd Rn R0 [+/-]imm8:00
613 // LDC_OPTION: cop CRd Rn imm8
615 // STC_OPTION: cop CRd Rn imm8
618 static bool DisassembleCoprocessor(MCInst &MI, unsigned Opcode, uint32_t insn,
619 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
621 assert(NumOps >= 5 && "Num of operands >= 5 for coprocessor instr");
623 unsigned &OpIdx = NumOpsAdded;
624 bool OneCopOpc = (Opcode == ARM::MCRR || Opcode == ARM::MCRR2 ||
625 Opcode == ARM::MRRC || Opcode == ARM::MRRC2);
626 // CDP/CDP2 has no GPR operand; the opc1 operand is also wider (Inst{23-20}).
627 bool NoGPR = (Opcode == ARM::CDP || Opcode == ARM::CDP2);
628 bool LdStCop = LdStCopOpcode(Opcode);
632 MI.addOperand(MCOperand::CreateImm(GetCoprocessor(insn)));
635 // Unindex if P:W = 0b00 --> _OPTION variant
636 unsigned PW = getPBit(insn) << 1 | getWBit(insn);
638 MI.addOperand(MCOperand::CreateImm(decodeRd(insn)));
640 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
644 MI.addOperand(MCOperand::CreateReg(0));
645 ARM_AM::AddrOpc AddrOpcode = getUBit(insn) ? ARM_AM::add : ARM_AM::sub;
646 unsigned Offset = ARM_AM::getAM2Opc(AddrOpcode, slice(insn, 7, 0) << 2,
648 MI.addOperand(MCOperand::CreateImm(Offset));
651 MI.addOperand(MCOperand::CreateImm(slice(insn, 7, 0)));
655 MI.addOperand(MCOperand::CreateImm(OneCopOpc ? GetCopOpc(insn)
656 : GetCopOpc1(insn, NoGPR)));
658 MI.addOperand(NoGPR ? MCOperand::CreateImm(decodeRd(insn))
659 : MCOperand::CreateReg(
660 getRegisterEnum(B, ARM::GPRRegClassID,
663 MI.addOperand(OneCopOpc ? MCOperand::CreateReg(
664 getRegisterEnum(B, ARM::GPRRegClassID,
666 : MCOperand::CreateImm(decodeRn(insn)));
668 MI.addOperand(MCOperand::CreateImm(decodeRm(insn)));
673 MI.addOperand(MCOperand::CreateImm(GetCopOpc2(insn)));
681 // Branch Instructions.
682 // BLr9: SignExtend(Imm24:'00', 32)
683 // Bcc, BLr9_pred: SignExtend(Imm24:'00', 32) Pred0 Pred1
684 // SMC: ZeroExtend(imm4, 32)
685 // SVC: ZeroExtend(Imm24, 32)
687 // Various coprocessor instructions are assigned BrFrm arbitrarily.
688 // Delegates to DisassembleCoprocessor() helper function.
691 // MSR/MSRsys: Rm mask=Inst{19-16}
693 // MSRi/MSRsysi: so_imm
694 // SRSW/SRS: ldstm_mode:$amode mode_imm
695 // RFEW/RFE: ldstm_mode:$amode Rn
696 static bool DisassembleBrFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
697 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
699 if (CoprocessorOpcode(Opcode))
700 return DisassembleCoprocessor(MI, Opcode, insn, NumOps, NumOpsAdded, B);
702 const TargetOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo;
703 if (!OpInfo) return false;
705 // MRS and MRSsys take one GPR reg Rd.
706 if (Opcode == ARM::MRS || Opcode == ARM::MRSsys) {
707 assert(NumOps >= 1 && OpInfo[0].RegClass == ARM::GPRRegClassID &&
708 "Reg operand expected");
709 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
714 // BXJ takes one GPR reg Rm.
715 if (Opcode == ARM::BXJ) {
716 assert(NumOps >= 1 && OpInfo[0].RegClass == ARM::GPRRegClassID &&
717 "Reg operand expected");
718 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
723 // MSR and MSRsys take one GPR reg Rm, followed by the mask.
724 if (Opcode == ARM::MSR || Opcode == ARM::MSRsys) {
725 assert(NumOps >= 1 && OpInfo[0].RegClass == ARM::GPRRegClassID &&
726 "Reg operand expected");
727 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
729 MI.addOperand(MCOperand::CreateImm(slice(insn, 19, 16)));
733 // MSRi and MSRsysi take one so_imm operand, followed by the mask.
734 if (Opcode == ARM::MSRi || Opcode == ARM::MSRsysi) {
735 // SOImm is 4-bit rotate amount in bits 11-8 with 8-bit imm in bits 7-0.
736 // A5.2.4 Rotate amount is twice the numeric value of Inst{11-8}.
737 // See also ARMAddressingModes.h: getSOImmValImm() and getSOImmValRot().
738 unsigned Rot = (insn >> ARMII::SoRotImmShift) & 0xF;
739 unsigned Imm = insn & 0xFF;
740 MI.addOperand(MCOperand::CreateImm(ARM_AM::rotr32(Imm, 2*Rot)));
741 MI.addOperand(MCOperand::CreateImm(slice(insn, 19, 16)));
745 if (Opcode == ARM::SRSW || Opcode == ARM::SRS ||
746 Opcode == ARM::RFEW || Opcode == ARM::RFE) {
747 ARM_AM::AMSubMode SubMode = getAMSubModeForBits(getPUBits(insn));
748 MI.addOperand(MCOperand::CreateImm(ARM_AM::getAM4ModeImm(SubMode)));
750 if (Opcode == ARM::SRSW || Opcode == ARM::SRS)
751 MI.addOperand(MCOperand::CreateImm(slice(insn, 4, 0)));
753 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
759 assert((Opcode == ARM::Bcc || Opcode == ARM::BLr9 || Opcode == ARM::BLr9_pred
760 || Opcode == ARM::SMC || Opcode == ARM::SVC) &&
761 "Unexpected Opcode");
763 assert(NumOps >= 1 && OpInfo[0].RegClass < 0 && "Reg operand expected");
766 if (Opcode == ARM::SMC) {
767 // ZeroExtend(imm4, 32) where imm24 = Inst{3-0}.
768 Imm32 = slice(insn, 3, 0);
769 } else if (Opcode == ARM::SVC) {
770 // ZeroExtend(imm24, 32) where imm24 = Inst{23-0}.
771 Imm32 = slice(insn, 23, 0);
773 // SignExtend(imm24:'00', 32) where imm24 = Inst{23-0}.
774 unsigned Imm26 = slice(insn, 23, 0) << 2;
775 //Imm32 = signextend<signed int, 26>(Imm26);
776 Imm32 = SignExtend32<26>(Imm26);
778 // When executing an ARM instruction, PC reads as the address of the current
779 // instruction plus 8. The assembler subtracts 8 from the difference
780 // between the branch instruction and the target address, disassembler has
781 // to add 8 to compensate.
785 MI.addOperand(MCOperand::CreateImm(Imm32));
791 // Misc. Branch Instructions.
794 static bool DisassembleBrMiscFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
795 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
797 const TargetOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo;
798 if (!OpInfo) return false;
800 unsigned &OpIdx = NumOpsAdded;
804 // BX_RET has only two predicate operands, do an early return.
805 if (Opcode == ARM::BX_RET)
808 // BLXr9 and BRIND take one GPR reg.
809 if (Opcode == ARM::BLXr9 || Opcode == ARM::BRIND) {
810 assert(NumOps >= 1 && OpInfo[OpIdx].RegClass == ARM::GPRRegClassID &&
811 "Reg operand expected");
812 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
821 static inline bool getBFCInvMask(uint32_t insn, uint32_t &mask) {
822 uint32_t lsb = slice(insn, 11, 7);
823 uint32_t msb = slice(insn, 20, 16);
826 DEBUG(errs() << "Encoding error: msb < lsb\n");
830 for (uint32_t i = lsb; i <= msb; ++i)
836 // A major complication is the fact that some of the saturating add/subtract
837 // operations have Rd Rm Rn, instead of the "normal" Rd Rn Rm.
838 // They are QADD, QDADD, QDSUB, and QSUB.
839 static bool DisassembleDPFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
840 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
842 const TargetInstrDesc &TID = ARMInsts[Opcode];
843 unsigned short NumDefs = TID.getNumDefs();
844 bool isUnary = isUnaryDP(TID.TSFlags);
845 const TargetOperandInfo *OpInfo = TID.OpInfo;
846 unsigned &OpIdx = NumOpsAdded;
850 // Disassemble register def if there is one.
851 if (NumDefs && (OpInfo[OpIdx].RegClass == ARM::GPRRegClassID)) {
852 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
857 // Now disassemble the src operands.
861 // Special-case handling of BFC/BFI/SBFX/UBFX.
862 if (Opcode == ARM::BFC || Opcode == ARM::BFI) {
863 MI.addOperand(MCOperand::CreateReg(0));
864 if (Opcode == ARM::BFI) {
865 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
870 if (!getBFCInvMask(insn, mask))
873 MI.addOperand(MCOperand::CreateImm(mask));
877 if (Opcode == ARM::SBFX || Opcode == ARM::UBFX) {
878 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
880 MI.addOperand(MCOperand::CreateImm(slice(insn, 11, 7)));
881 MI.addOperand(MCOperand::CreateImm(slice(insn, 20, 16) + 1));
886 bool RmRn = (Opcode == ARM::QADD || Opcode == ARM::QDADD ||
887 Opcode == ARM::QDSUB || Opcode == ARM::QSUB);
889 // BinaryDP has an Rn operand.
891 assert(OpInfo[OpIdx].RegClass == ARM::GPRRegClassID &&
892 "Reg operand expected");
893 MI.addOperand(MCOperand::CreateReg(
894 getRegisterEnum(B, ARM::GPRRegClassID,
895 RmRn ? decodeRm(insn) : decodeRn(insn))));
899 // If this is a two-address operand, skip it, e.g., MOVCCr operand 1.
900 if (isUnary && (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)) {
901 MI.addOperand(MCOperand::CreateReg(0));
905 // Now disassemble operand 2.
909 if (OpInfo[OpIdx].RegClass == ARM::GPRRegClassID) {
910 // We have a reg/reg form.
911 // Assert disabled because saturating operations, e.g., A8.6.127 QASX, are
912 // routed here as well.
913 // assert(getIBit(insn) == 0 && "I_Bit != '0' reg/reg form");
914 MI.addOperand(MCOperand::CreateReg(
915 getRegisterEnum(B, ARM::GPRRegClassID,
916 RmRn? decodeRn(insn) : decodeRm(insn))));
918 } else if (Opcode == ARM::MOVi16 || Opcode == ARM::MOVTi16) {
919 // We have an imm16 = imm4:imm12 (imm4=Inst{19:16}, imm12 = Inst{11:0}).
920 assert(getIBit(insn) == 1 && "I_Bit != '1' reg/imm form");
921 unsigned Imm16 = slice(insn, 19, 16) << 12 | slice(insn, 11, 0);
922 MI.addOperand(MCOperand::CreateImm(Imm16));
925 // We have a reg/imm form.
926 // SOImm is 4-bit rotate amount in bits 11-8 with 8-bit imm in bits 7-0.
927 // A5.2.4 Rotate amount is twice the numeric value of Inst{11-8}.
928 // See also ARMAddressingModes.h: getSOImmValImm() and getSOImmValRot().
929 assert(getIBit(insn) == 1 && "I_Bit != '1' reg/imm form");
930 unsigned Rot = (insn >> ARMII::SoRotImmShift) & 0xF;
931 unsigned Imm = insn & 0xFF;
932 MI.addOperand(MCOperand::CreateImm(ARM_AM::rotr32(Imm, 2*Rot)));
939 static bool DisassembleDPSoRegFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
940 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
942 const TargetInstrDesc &TID = ARMInsts[Opcode];
943 unsigned short NumDefs = TID.getNumDefs();
944 bool isUnary = isUnaryDP(TID.TSFlags);
945 const TargetOperandInfo *OpInfo = TID.OpInfo;
946 unsigned &OpIdx = NumOpsAdded;
950 // Disassemble register def if there is one.
951 if (NumDefs && (OpInfo[OpIdx].RegClass == ARM::GPRRegClassID)) {
952 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
957 // Disassemble the src operands.
961 // BinaryDP has an Rn operand.
963 assert(OpInfo[OpIdx].RegClass == ARM::GPRRegClassID &&
964 "Reg operand expected");
965 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
970 // If this is a two-address operand, skip it, e.g., MOVCCs operand 1.
971 if (isUnary && (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)) {
972 MI.addOperand(MCOperand::CreateReg(0));
976 // Disassemble operand 2, which consists of three components.
977 if (OpIdx + 2 >= NumOps)
980 assert((OpInfo[OpIdx].RegClass == ARM::GPRRegClassID) &&
981 (OpInfo[OpIdx+1].RegClass == ARM::GPRRegClassID) &&
982 (OpInfo[OpIdx+2].RegClass < 0) &&
983 "Expect 3 reg operands");
985 // Register-controlled shifts have Inst{7} = 0 and Inst{4} = 1.
986 unsigned Rs = slice(insn, 4, 4);
988 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
991 // Register-controlled shifts: [Rm, Rs, shift].
992 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
994 // Inst{6-5} encodes the shift opcode.
995 ARM_AM::ShiftOpc ShOp = getShiftOpcForBits(slice(insn, 6, 5));
996 MI.addOperand(MCOperand::CreateImm(ARM_AM::getSORegOpc(ShOp, 0)));
998 // Constant shifts: [Rm, reg0, shift_imm].
999 MI.addOperand(MCOperand::CreateReg(0)); // NoRegister
1000 // Inst{6-5} encodes the shift opcode.
1001 ARM_AM::ShiftOpc ShOp = getShiftOpcForBits(slice(insn, 6, 5));
1002 // Inst{11-7} encodes the imm5 shift amount.
1003 unsigned ShImm = slice(insn, 11, 7);
1005 // A8.4.1. Possible rrx or shift amount of 32...
1006 getImmShiftSE(ShOp, ShImm);
1007 MI.addOperand(MCOperand::CreateImm(ARM_AM::getSORegOpc(ShOp, ShImm)));
1014 static bool DisassembleLdStFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
1015 unsigned short NumOps, unsigned &NumOpsAdded, bool isStore, BO B) {
1017 const TargetInstrDesc &TID = ARMInsts[Opcode];
1018 bool isPrePost = isPrePostLdSt(TID.TSFlags);
1019 const TargetOperandInfo *OpInfo = TID.OpInfo;
1020 if (!OpInfo) return false;
1022 unsigned &OpIdx = NumOpsAdded;
1026 assert(((!isStore && TID.getNumDefs() > 0) ||
1027 (isStore && (TID.getNumDefs() == 0 || isPrePost)))
1028 && "Invalid arguments");
1030 // Operand 0 of a pre- and post-indexed store is the address base writeback.
1031 if (isPrePost && isStore) {
1032 assert(OpInfo[OpIdx].RegClass == ARM::GPRRegClassID &&
1033 "Reg operand expected");
1034 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1039 // Disassemble the dst/src operand.
1040 if (OpIdx >= NumOps)
1043 assert(OpInfo[OpIdx].RegClass == ARM::GPRRegClassID &&
1044 "Reg operand expected");
1045 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1049 // After dst of a pre- and post-indexed load is the address base writeback.
1050 if (isPrePost && !isStore) {
1051 assert(OpInfo[OpIdx].RegClass == ARM::GPRRegClassID &&
1052 "Reg operand expected");
1053 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1058 // Disassemble the base operand.
1059 if (OpIdx >= NumOps)
1062 assert(OpInfo[OpIdx].RegClass == ARM::GPRRegClassID &&
1063 "Reg operand expected");
1064 assert((!isPrePost || (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1))
1065 && "Index mode or tied_to operand expected");
1066 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1070 // For reg/reg form, base reg is followed by +/- reg shop imm.
1071 // For immediate form, it is followed by +/- imm12.
1072 // See also ARMAddressingModes.h (Addressing Mode #2).
1073 if (OpIdx + 1 >= NumOps)
1076 assert((OpInfo[OpIdx].RegClass == ARM::GPRRegClassID) &&
1077 (OpInfo[OpIdx+1].RegClass < 0) &&
1078 "Expect 1 reg operand followed by 1 imm operand");
1080 ARM_AM::AddrOpc AddrOpcode = getUBit(insn) ? ARM_AM::add : ARM_AM::sub;
1081 if (getIBit(insn) == 0) {
1082 MI.addOperand(MCOperand::CreateReg(0));
1084 // Disassemble the 12-bit immediate offset.
1085 unsigned Imm12 = slice(insn, 11, 0);
1086 unsigned Offset = ARM_AM::getAM2Opc(AddrOpcode, Imm12, ARM_AM::no_shift);
1087 MI.addOperand(MCOperand::CreateImm(Offset));
1089 // Disassemble the offset reg (Rm), shift type, and immediate shift length.
1090 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1092 // Inst{6-5} encodes the shift opcode.
1093 ARM_AM::ShiftOpc ShOp = getShiftOpcForBits(slice(insn, 6, 5));
1094 // Inst{11-7} encodes the imm5 shift amount.
1095 unsigned ShImm = slice(insn, 11, 7);
1097 // A8.4.1. Possible rrx or shift amount of 32...
1098 getImmShiftSE(ShOp, ShImm);
1099 MI.addOperand(MCOperand::CreateImm(
1100 ARM_AM::getAM2Opc(AddrOpcode, ShImm, ShOp)));
1107 static bool DisassembleLdFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
1108 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
1109 return DisassembleLdStFrm(MI, Opcode, insn, NumOps, NumOpsAdded, false, B);
1112 static bool DisassembleStFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
1113 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
1114 return DisassembleLdStFrm(MI, Opcode, insn, NumOps, NumOpsAdded, true, B);
1117 static bool HasDualReg(unsigned Opcode) {
1121 case ARM::LDRD: case ARM::LDRD_PRE: case ARM::LDRD_POST:
1122 case ARM::STRD: case ARM::STRD_PRE: case ARM::STRD_POST:
1127 static bool DisassembleLdStMiscFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
1128 unsigned short NumOps, unsigned &NumOpsAdded, bool isStore, BO B) {
1130 const TargetInstrDesc &TID = ARMInsts[Opcode];
1131 bool isPrePost = isPrePostLdSt(TID.TSFlags);
1132 const TargetOperandInfo *OpInfo = TID.OpInfo;
1133 if (!OpInfo) return false;
1135 unsigned &OpIdx = NumOpsAdded;
1139 assert(((!isStore && TID.getNumDefs() > 0) ||
1140 (isStore && (TID.getNumDefs() == 0 || isPrePost)))
1141 && "Invalid arguments");
1143 // Operand 0 of a pre- and post-indexed store is the address base writeback.
1144 if (isPrePost && isStore) {
1145 assert(OpInfo[OpIdx].RegClass == ARM::GPRRegClassID &&
1146 "Reg operand expected");
1147 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1152 bool DualReg = HasDualReg(Opcode);
1154 // Disassemble the dst/src operand.
1155 if (OpIdx >= NumOps)
1158 assert(OpInfo[OpIdx].RegClass == ARM::GPRRegClassID &&
1159 "Reg operand expected");
1160 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1164 // Fill in LDRD and STRD's second operand.
1166 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1167 decodeRd(insn) + 1)));
1171 // After dst of a pre- and post-indexed load is the address base writeback.
1172 if (isPrePost && !isStore) {
1173 assert(OpInfo[OpIdx].RegClass == ARM::GPRRegClassID &&
1174 "Reg operand expected");
1175 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1180 // Disassemble the base operand.
1181 if (OpIdx >= NumOps)
1184 assert(OpInfo[OpIdx].RegClass == ARM::GPRRegClassID &&
1185 "Reg operand expected");
1186 assert((!isPrePost || (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1))
1187 && "Index mode or tied_to operand expected");
1188 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1192 // For reg/reg form, base reg is followed by +/- reg.
1193 // For immediate form, it is followed by +/- imm8.
1194 // See also ARMAddressingModes.h (Addressing Mode #3).
1195 if (OpIdx + 1 >= NumOps)
1198 assert((OpInfo[OpIdx].RegClass == ARM::GPRRegClassID) &&
1199 (OpInfo[OpIdx+1].RegClass < 0) &&
1200 "Expect 1 reg operand followed by 1 imm operand");
1202 ARM_AM::AddrOpc AddrOpcode = getUBit(insn) ? ARM_AM::add : ARM_AM::sub;
1203 if (getAM3IBit(insn) == 1) {
1204 MI.addOperand(MCOperand::CreateReg(0));
1206 // Disassemble the 8-bit immediate offset.
1207 unsigned Imm4H = (insn >> ARMII::ImmHiShift) & 0xF;
1208 unsigned Imm4L = insn & 0xF;
1209 unsigned Offset = ARM_AM::getAM3Opc(AddrOpcode, (Imm4H << 4) | Imm4L);
1210 MI.addOperand(MCOperand::CreateImm(Offset));
1212 // Disassemble the offset reg (Rm).
1213 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1215 unsigned Offset = ARM_AM::getAM3Opc(AddrOpcode, 0);
1216 MI.addOperand(MCOperand::CreateImm(Offset));
1223 static bool DisassembleLdMiscFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
1224 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
1225 return DisassembleLdStMiscFrm(MI, Opcode, insn, NumOps, NumOpsAdded, false,
1229 static bool DisassembleStMiscFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
1230 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
1231 return DisassembleLdStMiscFrm(MI, Opcode, insn, NumOps, NumOpsAdded, true, B);
1234 // The algorithm for disassembly of LdStMulFrm is different from others because
1235 // it explicitly populates the two predicate operands after operand 0 (the base)
1236 // and operand 1 (the AM4 mode imm). After operand 3, we need to populate the
1237 // reglist with each affected register encoded as an MCOperand.
1238 static bool DisassembleLdStMulFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
1239 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
1241 assert(NumOps >= 5 && "LdStMulFrm expects NumOps >= 5");
1244 unsigned Base = getRegisterEnum(B, ARM::GPRRegClassID, decodeRn(insn));
1246 // Writeback to base, if necessary.
1247 if (Opcode == ARM::LDMIA_UPD || Opcode == ARM::STMIA_UPD ||
1248 Opcode == ARM::LDMDA_UPD || Opcode == ARM::STMDA_UPD ||
1249 Opcode == ARM::LDMDB_UPD || Opcode == ARM::STMDB_UPD ||
1250 Opcode == ARM::LDMIB_UPD || Opcode == ARM::STMIB_UPD) {
1251 MI.addOperand(MCOperand::CreateReg(Base));
1255 // Add the base register operand.
1256 MI.addOperand(MCOperand::CreateReg(Base));
1258 // Handling the two predicate operands before the reglist.
1259 int64_t CondVal = insn >> ARMII::CondShift;
1260 MI.addOperand(MCOperand::CreateImm(CondVal == 0xF ? 0xE : CondVal));
1261 MI.addOperand(MCOperand::CreateReg(ARM::CPSR));
1265 // Fill the variadic part of reglist.
1266 unsigned RegListBits = insn & ((1 << 16) - 1);
1267 for (unsigned i = 0; i < 16; ++i) {
1268 if ((RegListBits >> i) & 1) {
1269 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1278 // LDREX, LDREXB, LDREXH: Rd Rn
1279 // LDREXD: Rd Rd+1 Rn
1280 // STREX, STREXB, STREXH: Rd Rm Rn
1281 // STREXD: Rd Rm Rm+1 Rn
1283 // SWP, SWPB: Rd Rm Rn
1284 static bool DisassembleLdStExFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
1285 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
1287 const TargetOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo;
1288 if (!OpInfo) return false;
1290 unsigned &OpIdx = NumOpsAdded;
1295 && OpInfo[0].RegClass == ARM::GPRRegClassID
1296 && OpInfo[1].RegClass == ARM::GPRRegClassID
1297 && "Expect 2 reg operands");
1299 bool isStore = slice(insn, 20, 20) == 0;
1300 bool isDW = (Opcode == ARM::LDREXD || Opcode == ARM::STREXD);
1302 // Add the destination operand.
1303 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1307 // Store register Exclusive needs a source operand.
1309 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1314 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1315 decodeRm(insn)+1)));
1319 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1320 decodeRd(insn)+1)));
1324 // Finally add the pointer operand.
1325 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1332 // Misc. Arithmetic Instructions.
1334 // PKHBT, PKHTB: Rd Rn Rm , LSL/ASR #imm5
1335 // RBIT, REV, REV16, REVSH: Rd Rm
1336 static bool DisassembleArithMiscFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
1337 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
1339 const TargetOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo;
1340 unsigned &OpIdx = NumOpsAdded;
1345 && OpInfo[0].RegClass == ARM::GPRRegClassID
1346 && OpInfo[1].RegClass == ARM::GPRRegClassID
1347 && "Expect 2 reg operands");
1349 bool ThreeReg = NumOps > 2 && OpInfo[2].RegClass == ARM::GPRRegClassID;
1351 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1356 assert(NumOps >= 4 && "Expect >= 4 operands");
1357 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1362 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1366 // If there is still an operand info left which is an immediate operand, add
1367 // an additional imm5 LSL/ASR operand.
1368 if (ThreeReg && OpInfo[OpIdx].RegClass < 0
1369 && !OpInfo[OpIdx].isPredicate() && !OpInfo[OpIdx].isOptionalDef()) {
1370 // Extract the 5-bit immediate field Inst{11-7}.
1371 unsigned ShiftAmt = (insn >> ARMII::ShiftShift) & 0x1F;
1372 ARM_AM::ShiftOpc Opc = ARM_AM::no_shift;
1373 if (Opcode == ARM::PKHBT)
1375 else if (Opcode == ARM::PKHBT)
1377 getImmShiftSE(Opc, ShiftAmt);
1378 MI.addOperand(MCOperand::CreateImm(ARM_AM::getSORegOpc(Opc, ShiftAmt)));
1385 /// DisassembleSatFrm - Disassemble saturate instructions:
1386 /// SSAT, SSAT16, USAT, and USAT16.
1387 static bool DisassembleSatFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
1388 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
1390 const TargetInstrDesc &TID = ARMInsts[Opcode];
1391 NumOpsAdded = TID.getNumOperands() - 2; // ignore predicate operands
1393 // Disassemble register def.
1394 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1397 unsigned Pos = slice(insn, 20, 16);
1398 if (Opcode == ARM::SSAT || Opcode == ARM::SSAT16)
1400 MI.addOperand(MCOperand::CreateImm(Pos));
1402 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1405 if (NumOpsAdded == 4) {
1406 ARM_AM::ShiftOpc Opc = (slice(insn, 6, 6) != 0 ? ARM_AM::asr : ARM_AM::lsl);
1407 // Inst{11-7} encodes the imm5 shift amount.
1408 unsigned ShAmt = slice(insn, 11, 7);
1410 // A8.6.183. Possible ASR shift amount of 32...
1411 if (Opc == ARM_AM::asr)
1414 Opc = ARM_AM::no_shift;
1416 MI.addOperand(MCOperand::CreateImm(ARM_AM::getSORegOpc(Opc, ShAmt)));
1421 // Extend instructions.
1422 // SXT* and UXT*: Rd [Rn] Rm [rot_imm].
1423 // The 2nd operand register is Rn and the 3rd operand regsiter is Rm for the
1424 // three register operand form. Otherwise, Rn=0b1111 and only Rm is used.
1425 static bool DisassembleExtFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
1426 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
1428 const TargetOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo;
1429 unsigned &OpIdx = NumOpsAdded;
1434 && OpInfo[0].RegClass == ARM::GPRRegClassID
1435 && OpInfo[1].RegClass == ARM::GPRRegClassID
1436 && "Expect 2 reg operands");
1438 bool ThreeReg = NumOps > 2 && OpInfo[2].RegClass == ARM::GPRRegClassID;
1440 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1445 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1450 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1454 // If there is still an operand info left which is an immediate operand, add
1455 // an additional rotate immediate operand.
1456 if (OpIdx < NumOps && OpInfo[OpIdx].RegClass < 0
1457 && !OpInfo[OpIdx].isPredicate() && !OpInfo[OpIdx].isOptionalDef()) {
1458 // Extract the 2-bit rotate field Inst{11-10}.
1459 unsigned rot = (insn >> ARMII::ExtRotImmShift) & 3;
1460 // Rotation by 8, 16, or 24 bits.
1461 MI.addOperand(MCOperand::CreateImm(rot << 3));
1468 /////////////////////////////////////
1470 // Utility Functions For VFP //
1472 /////////////////////////////////////
1474 // Extract/Decode Dd/Sd:
1476 // SP => d = UInt(Vd:D)
1477 // DP => d = UInt(D:Vd)
1478 static unsigned decodeVFPRd(uint32_t insn, bool isSPVFP) {
1479 return isSPVFP ? (decodeRd(insn) << 1 | getDBit(insn))
1480 : (decodeRd(insn) | getDBit(insn) << 4);
1483 // Extract/Decode Dn/Sn:
1485 // SP => n = UInt(Vn:N)
1486 // DP => n = UInt(N:Vn)
1487 static unsigned decodeVFPRn(uint32_t insn, bool isSPVFP) {
1488 return isSPVFP ? (decodeRn(insn) << 1 | getNBit(insn))
1489 : (decodeRn(insn) | getNBit(insn) << 4);
1492 // Extract/Decode Dm/Sm:
1494 // SP => m = UInt(Vm:M)
1495 // DP => m = UInt(M:Vm)
1496 static unsigned decodeVFPRm(uint32_t insn, bool isSPVFP) {
1497 return isSPVFP ? (decodeRm(insn) << 1 | getMBit(insn))
1498 : (decodeRm(insn) | getMBit(insn) << 4);
1502 static APInt VFPExpandImm(unsigned char byte, unsigned N) {
1503 assert(N == 32 || N == 64);
1506 unsigned bit6 = slice(byte, 6, 6);
1508 Result = slice(byte, 7, 7) << 31 | slice(byte, 5, 0) << 19;
1510 Result |= 0x1f << 25;
1512 Result |= 0x1 << 30;
1514 Result = (uint64_t)slice(byte, 7, 7) << 63 |
1515 (uint64_t)slice(byte, 5, 0) << 48;
1517 Result |= 0xffULL << 54;
1519 Result |= 0x1ULL << 62;
1521 return APInt(N, Result);
1524 // VFP Unary Format Instructions:
1526 // VCMP[E]ZD, VCMP[E]ZS: compares one floating-point register with zero
1527 // VCVTDS, VCVTSD: converts between double-precision and single-precision
1528 // The rest of the instructions have homogeneous [VFP]Rd and [VFP]Rm registers.
1529 static bool DisassembleVFPUnaryFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
1530 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
1532 assert(NumOps >= 1 && "VFPUnaryFrm expects NumOps >= 1");
1534 const TargetOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo;
1535 unsigned &OpIdx = NumOpsAdded;
1539 unsigned RegClass = OpInfo[OpIdx].RegClass;
1540 assert((RegClass == ARM::SPRRegClassID || RegClass == ARM::DPRRegClassID) &&
1541 "Reg operand expected");
1542 bool isSP = (RegClass == ARM::SPRRegClassID);
1544 MI.addOperand(MCOperand::CreateReg(
1545 getRegisterEnum(B, RegClass, decodeVFPRd(insn, isSP))));
1548 // Early return for compare with zero instructions.
1549 if (Opcode == ARM::VCMPEZD || Opcode == ARM::VCMPEZS
1550 || Opcode == ARM::VCMPZD || Opcode == ARM::VCMPZS)
1553 RegClass = OpInfo[OpIdx].RegClass;
1554 assert((RegClass == ARM::SPRRegClassID || RegClass == ARM::DPRRegClassID) &&
1555 "Reg operand expected");
1556 isSP = (RegClass == ARM::SPRRegClassID);
1558 MI.addOperand(MCOperand::CreateReg(
1559 getRegisterEnum(B, RegClass, decodeVFPRm(insn, isSP))));
1565 // All the instructions have homogeneous [VFP]Rd, [VFP]Rn, and [VFP]Rm regs.
1566 // Some of them have operand constraints which tie the first operand in the
1567 // InOperandList to that of the dst. As far as asm printing is concerned, this
1568 // tied_to operand is simply skipped.
1569 static bool DisassembleVFPBinaryFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
1570 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
1572 assert(NumOps >= 3 && "VFPBinaryFrm expects NumOps >= 3");
1574 const TargetInstrDesc &TID = ARMInsts[Opcode];
1575 const TargetOperandInfo *OpInfo = TID.OpInfo;
1576 unsigned &OpIdx = NumOpsAdded;
1580 unsigned RegClass = OpInfo[OpIdx].RegClass;
1581 assert((RegClass == ARM::SPRRegClassID || RegClass == ARM::DPRRegClassID) &&
1582 "Reg operand expected");
1583 bool isSP = (RegClass == ARM::SPRRegClassID);
1585 MI.addOperand(MCOperand::CreateReg(
1586 getRegisterEnum(B, RegClass, decodeVFPRd(insn, isSP))));
1589 // Skip tied_to operand constraint.
1590 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1) {
1591 assert(NumOps >= 4 && "Expect >=4 operands");
1592 MI.addOperand(MCOperand::CreateReg(0));
1596 MI.addOperand(MCOperand::CreateReg(
1597 getRegisterEnum(B, RegClass, decodeVFPRn(insn, isSP))));
1600 MI.addOperand(MCOperand::CreateReg(
1601 getRegisterEnum(B, RegClass, decodeVFPRm(insn, isSP))));
1607 // A8.6.295 vcvt (floating-point <-> integer)
1608 // Int to FP: VSITOD, VSITOS, VUITOD, VUITOS
1609 // FP to Int: VTOSI[Z|R]D, VTOSI[Z|R]S, VTOUI[Z|R]D, VTOUI[Z|R]S
1611 // A8.6.297 vcvt (floating-point and fixed-point)
1612 // Dd|Sd Dd|Sd(TIED_TO) #fbits(= 16|32 - UInt(imm4:i))
1613 static bool DisassembleVFPConv1Frm(MCInst &MI, unsigned Opcode, uint32_t insn,
1614 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
1616 assert(NumOps >= 2 && "VFPConv1Frm expects NumOps >= 2");
1618 const TargetInstrDesc &TID = ARMInsts[Opcode];
1619 const TargetOperandInfo *OpInfo = TID.OpInfo;
1620 if (!OpInfo) return false;
1622 bool SP = slice(insn, 8, 8) == 0; // A8.6.295 & A8.6.297
1623 bool fixed_point = slice(insn, 17, 17) == 1; // A8.6.297
1624 unsigned RegClassID = SP ? ARM::SPRRegClassID : ARM::DPRRegClassID;
1628 assert(NumOps >= 3 && "Expect >= 3 operands");
1629 int size = slice(insn, 7, 7) == 0 ? 16 : 32;
1630 int fbits = size - (slice(insn,3,0) << 1 | slice(insn,5,5));
1631 MI.addOperand(MCOperand::CreateReg(
1632 getRegisterEnum(B, RegClassID,
1633 decodeVFPRd(insn, SP))));
1635 assert(TID.getOperandConstraint(1, TOI::TIED_TO) != -1 &&
1636 "Tied to operand expected");
1637 MI.addOperand(MI.getOperand(0));
1639 assert(OpInfo[2].RegClass < 0 && !OpInfo[2].isPredicate() &&
1640 !OpInfo[2].isOptionalDef() && "Imm operand expected");
1641 MI.addOperand(MCOperand::CreateImm(fbits));
1646 // The Rd (destination) and Rm (source) bits have different interpretations
1647 // depending on their single-precisonness.
1649 if (slice(insn, 18, 18) == 1) { // to_integer operation
1650 d = decodeVFPRd(insn, true /* Is Single Precision */);
1651 MI.addOperand(MCOperand::CreateReg(
1652 getRegisterEnum(B, ARM::SPRRegClassID, d)));
1653 m = decodeVFPRm(insn, SP);
1654 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, RegClassID, m)));
1656 d = decodeVFPRd(insn, SP);
1657 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, RegClassID, d)));
1658 m = decodeVFPRm(insn, true /* Is Single Precision */);
1659 MI.addOperand(MCOperand::CreateReg(
1660 getRegisterEnum(B, ARM::SPRRegClassID, m)));
1668 // VMOVRS - A8.6.330
1669 // Rt => Rd; Sn => UInt(Vn:N)
1670 static bool DisassembleVFPConv2Frm(MCInst &MI, unsigned Opcode, uint32_t insn,
1671 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
1673 assert(NumOps >= 2 && "VFPConv2Frm expects NumOps >= 2");
1675 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1677 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::SPRRegClassID,
1678 decodeVFPRn(insn, true))));
1683 // VMOVRRD - A8.6.332
1684 // Rt => Rd; Rt2 => Rn; Dm => UInt(M:Vm)
1686 // VMOVRRS - A8.6.331
1687 // Rt => Rd; Rt2 => Rn; Sm => UInt(Vm:M); Sm1 = Sm+1
1688 static bool DisassembleVFPConv3Frm(MCInst &MI, unsigned Opcode, uint32_t insn,
1689 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
1691 assert(NumOps >= 3 && "VFPConv3Frm expects NumOps >= 3");
1693 const TargetOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo;
1694 unsigned &OpIdx = NumOpsAdded;
1696 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1698 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1702 if (OpInfo[OpIdx].RegClass == ARM::SPRRegClassID) {
1703 unsigned Sm = decodeVFPRm(insn, true);
1704 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::SPRRegClassID,
1706 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::SPRRegClassID,
1710 MI.addOperand(MCOperand::CreateReg(
1711 getRegisterEnum(B, ARM::DPRRegClassID,
1712 decodeVFPRm(insn, false))));
1718 // VMOVSR - A8.6.330
1719 // Rt => Rd; Sn => UInt(Vn:N)
1720 static bool DisassembleVFPConv4Frm(MCInst &MI, unsigned Opcode, uint32_t insn,
1721 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
1723 assert(NumOps >= 2 && "VFPConv4Frm expects NumOps >= 2");
1725 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::SPRRegClassID,
1726 decodeVFPRn(insn, true))));
1727 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1733 // VMOVDRR - A8.6.332
1734 // Rt => Rd; Rt2 => Rn; Dm => UInt(M:Vm)
1736 // VMOVRRS - A8.6.331
1737 // Rt => Rd; Rt2 => Rn; Sm => UInt(Vm:M); Sm1 = Sm+1
1738 static bool DisassembleVFPConv5Frm(MCInst &MI, unsigned Opcode, uint32_t insn,
1739 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
1741 assert(NumOps >= 3 && "VFPConv5Frm expects NumOps >= 3");
1743 const TargetOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo;
1744 unsigned &OpIdx = NumOpsAdded;
1748 if (OpInfo[OpIdx].RegClass == ARM::SPRRegClassID) {
1749 unsigned Sm = decodeVFPRm(insn, true);
1750 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::SPRRegClassID,
1752 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::SPRRegClassID,
1756 MI.addOperand(MCOperand::CreateReg(
1757 getRegisterEnum(B, ARM::DPRRegClassID,
1758 decodeVFPRm(insn, false))));
1762 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1764 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1770 // VFP Load/Store Instructions.
1771 // VLDRD, VLDRS, VSTRD, VSTRS
1772 static bool DisassembleVFPLdStFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
1773 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
1775 assert(NumOps >= 3 && "VFPLdStFrm expects NumOps >= 3");
1777 bool isSPVFP = (Opcode == ARM::VLDRS || Opcode == ARM::VSTRS);
1778 unsigned RegClassID = isSPVFP ? ARM::SPRRegClassID : ARM::DPRRegClassID;
1780 // Extract Dd/Sd for operand 0.
1781 unsigned RegD = decodeVFPRd(insn, isSPVFP);
1783 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, RegClassID, RegD)));
1785 unsigned Base = getRegisterEnum(B, ARM::GPRRegClassID, decodeRn(insn));
1786 MI.addOperand(MCOperand::CreateReg(Base));
1788 // Next comes the AM5 Opcode.
1789 ARM_AM::AddrOpc AddrOpcode = getUBit(insn) ? ARM_AM::add : ARM_AM::sub;
1790 unsigned char Imm8 = insn & 0xFF;
1791 MI.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(AddrOpcode, Imm8)));
1798 // VFP Load/Store Multiple Instructions.
1799 // This is similar to the algorithm for LDM/STM in that operand 0 (the base) and
1800 // operand 1 (the AM4 mode imm) is followed by two predicate operands. It is
1801 // followed by a reglist of either DPR(s) or SPR(s).
1803 // VLDMD[_UPD], VLDMS[_UPD], VSTMD[_UPD], VSTMS[_UPD]
1804 static bool DisassembleVFPLdStMulFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
1805 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
1807 assert(NumOps >= 5 && "VFPLdStMulFrm expects NumOps >= 5");
1809 unsigned &OpIdx = NumOpsAdded;
1813 unsigned Base = getRegisterEnum(B, ARM::GPRRegClassID, decodeRn(insn));
1815 // Writeback to base, if necessary.
1816 if (Opcode == ARM::VLDMDIA_UPD || Opcode == ARM::VLDMSIA_UPD ||
1817 Opcode == ARM::VLDMDDB_UPD || Opcode == ARM::VLDMSDB_UPD ||
1818 Opcode == ARM::VSTMDIA_UPD || Opcode == ARM::VSTMSIA_UPD ||
1819 Opcode == ARM::VSTMDDB_UPD || Opcode == ARM::VSTMSDB_UPD) {
1820 MI.addOperand(MCOperand::CreateReg(Base));
1824 MI.addOperand(MCOperand::CreateReg(Base));
1826 // Next comes the AM4 Opcode.
1827 ARM_AM::AMSubMode SubMode = getAMSubModeForBits(getPUBits(insn));
1828 // Must be either "ia" or "db" submode.
1829 if (SubMode != ARM_AM::ia && SubMode != ARM_AM::db) {
1830 DEBUG(errs() << "Illegal addressing mode 4 sub-mode!\n");
1833 MI.addOperand(MCOperand::CreateImm(ARM_AM::getAM4ModeImm(SubMode)));
1835 // Handling the two predicate operands before the reglist.
1836 int64_t CondVal = insn >> ARMII::CondShift;
1837 MI.addOperand(MCOperand::CreateImm(CondVal == 0xF ? 0xE : CondVal));
1838 MI.addOperand(MCOperand::CreateReg(ARM::CPSR));
1842 bool isSPVFP = (Opcode == ARM::VLDMSIA || Opcode == ARM::VLDMSDB ||
1843 Opcode == ARM::VLDMSIA_UPD || Opcode == ARM::VLDMSDB_UPD ||
1844 Opcode == ARM::VSTMSIA || Opcode == ARM::VSTMSDB ||
1845 Opcode == ARM::VSTMSIA_UPD || Opcode == ARM::VSTMSDB_UPD);
1846 unsigned RegClassID = isSPVFP ? ARM::SPRRegClassID : ARM::DPRRegClassID;
1849 unsigned RegD = decodeVFPRd(insn, isSPVFP);
1851 // Fill the variadic part of reglist.
1852 unsigned char Imm8 = insn & 0xFF;
1853 unsigned Regs = isSPVFP ? Imm8 : Imm8/2;
1854 for (unsigned i = 0; i < Regs; ++i) {
1855 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, RegClassID,
1863 // Misc. VFP Instructions.
1864 // FMSTAT (vmrs with Rt=0b1111, i.e., to apsr_nzcv and no register operand)
1865 // FCONSTD (DPR and a VFPf64Imm operand)
1866 // FCONSTS (SPR and a VFPf32Imm operand)
1867 // VMRS/VMSR (GPR operand)
1868 static bool DisassembleVFPMiscFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
1869 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
1871 const TargetOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo;
1872 unsigned &OpIdx = NumOpsAdded;
1876 if (Opcode == ARM::FMSTAT)
1879 assert(NumOps >= 2 && "VFPMiscFrm expects >=2 operands");
1881 unsigned RegEnum = 0;
1882 switch (OpInfo[0].RegClass) {
1883 case ARM::DPRRegClassID:
1884 RegEnum = getRegisterEnum(B, ARM::DPRRegClassID, decodeVFPRd(insn, false));
1886 case ARM::SPRRegClassID:
1887 RegEnum = getRegisterEnum(B, ARM::SPRRegClassID, decodeVFPRd(insn, true));
1889 case ARM::GPRRegClassID:
1890 RegEnum = getRegisterEnum(B, ARM::GPRRegClassID, decodeRd(insn));
1893 assert(0 && "Invalid reg class id");
1897 MI.addOperand(MCOperand::CreateReg(RegEnum));
1900 // Extract/decode the f64/f32 immediate.
1901 if (OpIdx < NumOps && OpInfo[OpIdx].RegClass < 0
1902 && !OpInfo[OpIdx].isPredicate() && !OpInfo[OpIdx].isOptionalDef()) {
1903 // The asm syntax specifies the floating point value, not the 8-bit literal.
1904 APInt immRaw = VFPExpandImm(slice(insn,19,16) << 4 | slice(insn, 3, 0),
1905 Opcode == ARM::FCONSTD ? 64 : 32);
1906 APFloat immFP = APFloat(immRaw, true);
1907 double imm = Opcode == ARM::FCONSTD ? immFP.convertToDouble() :
1908 immFP.convertToFloat();
1909 MI.addOperand(MCOperand::CreateFPImm(imm));
1917 // DisassembleThumbFrm() is defined in ThumbDisassemblerCore.h file.
1918 #include "ThumbDisassemblerCore.h"
1920 /////////////////////////////////////////////////////
1922 // Utility Functions For ARM Advanced SIMD //
1924 /////////////////////////////////////////////////////
1926 // The following NEON namings are based on A8.6.266 VABA, VABAL. Notice that
1927 // A8.6.303 VDUP (ARM core register)'s D/Vd pair is the N/Vn pair of VABA/VABAL.
1929 // A7.3 Register encoding
1931 // Extract/Decode NEON D/Vd:
1933 // Note that for quadword, Qd = UInt(D:Vd<3:1>) = Inst{22:15-13}, whereas for
1934 // doubleword, Dd = UInt(D:Vd). We compensate for this difference by
1935 // handling it in the getRegisterEnum() utility function.
1936 // D = Inst{22}, Vd = Inst{15-12}
1937 static unsigned decodeNEONRd(uint32_t insn) {
1938 return ((insn >> ARMII::NEON_D_BitShift) & 1) << 4
1939 | ((insn >> ARMII::NEON_RegRdShift) & ARMII::NEONRegMask);
1942 // Extract/Decode NEON N/Vn:
1944 // Note that for quadword, Qn = UInt(N:Vn<3:1>) = Inst{7:19-17}, whereas for
1945 // doubleword, Dn = UInt(N:Vn). We compensate for this difference by
1946 // handling it in the getRegisterEnum() utility function.
1947 // N = Inst{7}, Vn = Inst{19-16}
1948 static unsigned decodeNEONRn(uint32_t insn) {
1949 return ((insn >> ARMII::NEON_N_BitShift) & 1) << 4
1950 | ((insn >> ARMII::NEON_RegRnShift) & ARMII::NEONRegMask);
1953 // Extract/Decode NEON M/Vm:
1955 // Note that for quadword, Qm = UInt(M:Vm<3:1>) = Inst{5:3-1}, whereas for
1956 // doubleword, Dm = UInt(M:Vm). We compensate for this difference by
1957 // handling it in the getRegisterEnum() utility function.
1958 // M = Inst{5}, Vm = Inst{3-0}
1959 static unsigned decodeNEONRm(uint32_t insn) {
1960 return ((insn >> ARMII::NEON_M_BitShift) & 1) << 4
1961 | ((insn >> ARMII::NEON_RegRmShift) & ARMII::NEONRegMask);
1972 } // End of unnamed namespace
1974 // size field -> Inst{11-10}
1975 // index_align field -> Inst{7-4}
1977 // The Lane Index interpretation depends on the Data Size:
1978 // 8 (encoded as size = 0b00) -> Index = index_align[3:1]
1979 // 16 (encoded as size = 0b01) -> Index = index_align[3:2]
1980 // 32 (encoded as size = 0b10) -> Index = index_align[3]
1982 // Ref: A8.6.317 VLD4 (single 4-element structure to one lane).
1983 static unsigned decodeLaneIndex(uint32_t insn) {
1984 unsigned size = insn >> 10 & 3;
1985 assert((size == 0 || size == 1 || size == 2) &&
1986 "Encoding error: size should be either 0, 1, or 2");
1988 unsigned index_align = insn >> 4 & 0xF;
1989 return (index_align >> 1) >> size;
1992 // imm64 = AdvSIMDExpandImm(op, cmode, i:imm3:imm4)
1993 // op = Inst{5}, cmode = Inst{11-8}
1994 // i = Inst{24} (ARM architecture)
1995 // imm3 = Inst{18-16}, imm4 = Inst{3-0}
1996 // Ref: Table A7-15 Modified immediate values for Advanced SIMD instructions.
1997 static uint64_t decodeN1VImm(uint32_t insn, ElemSize esize) {
1998 unsigned char op = (insn >> 5) & 1;
1999 unsigned char cmode = (insn >> 8) & 0xF;
2000 unsigned char Imm8 = ((insn >> 24) & 1) << 7 |
2001 ((insn >> 16) & 7) << 4 |
2003 return (op << 12) | (cmode << 8) | Imm8;
2006 // A8.6.339 VMUL, VMULL (by scalar)
2007 // ESize16 => m = Inst{2-0} (Vm<2:0>) D0-D7
2008 // ESize32 => m = Inst{3-0} (Vm<3:0>) D0-D15
2009 static unsigned decodeRestrictedDm(uint32_t insn, ElemSize esize) {
2016 assert(0 && "Unreachable code!");
2021 // A8.6.339 VMUL, VMULL (by scalar)
2022 // ESize16 => index = Inst{5:3} (M:Vm<3>) D0-D7
2023 // ESize32 => index = Inst{5} (M) D0-D15
2024 static unsigned decodeRestrictedDmIndex(uint32_t insn, ElemSize esize) {
2027 return (((insn >> 5) & 1) << 1) | ((insn >> 3) & 1);
2029 return (insn >> 5) & 1;
2031 assert(0 && "Unreachable code!");
2036 // A8.6.296 VCVT (between floating-point and fixed-point, Advanced SIMD)
2037 // (64 - <fbits>) is encoded as imm6, i.e., Inst{21-16}.
2038 static unsigned decodeVCVTFractionBits(uint32_t insn) {
2039 return 64 - ((insn >> 16) & 0x3F);
2042 // A8.6.302 VDUP (scalar)
2043 // ESize8 => index = Inst{19-17}
2044 // ESize16 => index = Inst{19-18}
2045 // ESize32 => index = Inst{19}
2046 static unsigned decodeNVLaneDupIndex(uint32_t insn, ElemSize esize) {
2049 return (insn >> 17) & 7;
2051 return (insn >> 18) & 3;
2053 return (insn >> 19) & 1;
2055 assert(0 && "Unspecified element size!");
2060 // A8.6.328 VMOV (ARM core register to scalar)
2061 // A8.6.329 VMOV (scalar to ARM core register)
2062 // ESize8 => index = Inst{21:6-5}
2063 // ESize16 => index = Inst{21:6}
2064 // ESize32 => index = Inst{21}
2065 static unsigned decodeNVLaneOpIndex(uint32_t insn, ElemSize esize) {
2068 return ((insn >> 21) & 1) << 2 | ((insn >> 5) & 3);
2070 return ((insn >> 21) & 1) << 1 | ((insn >> 6) & 1);
2072 return ((insn >> 21) & 1);
2074 assert(0 && "Unspecified element size!");
2079 // Imm6 = Inst{21-16}, L = Inst{7}
2081 // LeftShift == true (A8.6.367 VQSHL, A8.6.387 VSLI):
2083 // '0001xxx' => esize = 8; shift_amount = imm6 - 8
2084 // '001xxxx' => esize = 16; shift_amount = imm6 - 16
2085 // '01xxxxx' => esize = 32; shift_amount = imm6 - 32
2086 // '1xxxxxx' => esize = 64; shift_amount = imm6
2088 // LeftShift == false (A8.6.376 VRSHR, A8.6.368 VQSHRN):
2090 // '0001xxx' => esize = 8; shift_amount = 16 - imm6
2091 // '001xxxx' => esize = 16; shift_amount = 32 - imm6
2092 // '01xxxxx' => esize = 32; shift_amount = 64 - imm6
2093 // '1xxxxxx' => esize = 64; shift_amount = 64 - imm6
2095 static unsigned decodeNVSAmt(uint32_t insn, bool LeftShift) {
2096 ElemSize esize = ESizeNA;
2097 unsigned L = (insn >> 7) & 1;
2098 unsigned imm6 = (insn >> 16) & 0x3F;
2102 else if (imm6 >> 4 == 1)
2104 else if (imm6 >> 5 == 1)
2107 assert(0 && "Wrong encoding of Inst{7:21-16}!");
2112 return esize == ESize64 ? imm6 : (imm6 - esize);
2114 return esize == ESize64 ? (esize - imm6) : (2*esize - imm6);
2118 // Imm4 = Inst{11-8}
2119 static unsigned decodeN3VImm(uint32_t insn) {
2120 return (insn >> 8) & 0xF;
2124 // D[d] D[d2] ... Rn [TIED_TO Rn] align [Rm]
2126 // D[d] D[d2] ... Rn [TIED_TO Rn] align [Rm] TIED_TO ... imm(idx)
2128 // Rn [TIED_TO Rn] align [Rm] D[d] D[d2] ...
2130 // Rn [TIED_TO Rn] align [Rm] D[d] D[d2] ... [imm(idx)]
2132 // Correctly set VLD*/VST*'s TIED_TO GPR, as the asm printer needs it.
2133 static bool DisassembleNLdSt0(MCInst &MI, unsigned Opcode, uint32_t insn,
2134 unsigned short NumOps, unsigned &NumOpsAdded, bool Store, bool DblSpaced,
2137 const TargetInstrDesc &TID = ARMInsts[Opcode];
2138 const TargetOperandInfo *OpInfo = TID.OpInfo;
2140 // At least one DPR register plus addressing mode #6.
2141 assert(NumOps >= 3 && "Expect >= 3 operands");
2143 unsigned &OpIdx = NumOpsAdded;
2147 // We have homogeneous NEON registers for Load/Store.
2148 unsigned RegClass = 0;
2150 // Double-spaced registers have increments of 2.
2151 unsigned Inc = DblSpaced ? 2 : 1;
2153 unsigned Rn = decodeRn(insn);
2154 unsigned Rm = decodeRm(insn);
2155 unsigned Rd = decodeNEONRd(insn);
2157 // A7.7.1 Advanced SIMD addressing mode.
2160 // LLVM Addressing Mode #6.
2161 unsigned RmEnum = 0;
2163 RmEnum = getRegisterEnum(B, ARM::GPRRegClassID, Rm);
2166 // Consume possible WB, AddrMode6, possible increment reg, the DPR/QPR's,
2167 // then possible lane index.
2168 assert(OpIdx < NumOps && OpInfo[0].RegClass == ARM::GPRRegClassID &&
2169 "Reg operand expected");
2172 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
2177 assert((OpIdx+1) < NumOps && OpInfo[OpIdx].RegClass == ARM::GPRRegClassID &&
2178 OpInfo[OpIdx + 1].RegClass < 0 && "Addrmode #6 Operands expected");
2179 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
2181 MI.addOperand(MCOperand::CreateImm(0)); // Alignment ignored?
2185 MI.addOperand(MCOperand::CreateReg(RmEnum));
2189 assert(OpIdx < NumOps &&
2190 (OpInfo[OpIdx].RegClass == ARM::DPRRegClassID ||
2191 OpInfo[OpIdx].RegClass == ARM::QPRRegClassID) &&
2192 "Reg operand expected");
2194 RegClass = OpInfo[OpIdx].RegClass;
2195 while (OpIdx < NumOps && (unsigned)OpInfo[OpIdx].RegClass == RegClass) {
2196 MI.addOperand(MCOperand::CreateReg(
2197 getRegisterEnum(B, RegClass, Rd)));
2202 // Handle possible lane index.
2203 if (OpIdx < NumOps && OpInfo[OpIdx].RegClass < 0
2204 && !OpInfo[OpIdx].isPredicate() && !OpInfo[OpIdx].isOptionalDef()) {
2205 MI.addOperand(MCOperand::CreateImm(decodeLaneIndex(insn)));
2210 // Consume the DPR/QPR's, possible WB, AddrMode6, possible incrment reg,
2211 // possible TIED_TO DPR/QPR's (ignored), then possible lane index.
2212 RegClass = OpInfo[0].RegClass;
2214 while (OpIdx < NumOps && (unsigned)OpInfo[OpIdx].RegClass == RegClass) {
2215 MI.addOperand(MCOperand::CreateReg(
2216 getRegisterEnum(B, RegClass, Rd)));
2222 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
2227 assert((OpIdx+1) < NumOps && OpInfo[OpIdx].RegClass == ARM::GPRRegClassID &&
2228 OpInfo[OpIdx + 1].RegClass < 0 && "Addrmode #6 Operands expected");
2229 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
2231 MI.addOperand(MCOperand::CreateImm(0)); // Alignment ignored?
2235 MI.addOperand(MCOperand::CreateReg(RmEnum));
2239 while (OpIdx < NumOps && (unsigned)OpInfo[OpIdx].RegClass == RegClass) {
2240 assert(TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1 &&
2241 "Tied to operand expected");
2242 MI.addOperand(MCOperand::CreateReg(0));
2246 // Handle possible lane index.
2247 if (OpIdx < NumOps && OpInfo[OpIdx].RegClass < 0
2248 && !OpInfo[OpIdx].isPredicate() && !OpInfo[OpIdx].isOptionalDef()) {
2249 MI.addOperand(MCOperand::CreateImm(decodeLaneIndex(insn)));
2254 // Accessing registers past the end of the NEON register file is not
2263 // If L (Inst{21}) == 0, store instructions.
2264 // Find out about double-spaced-ness of the Opcode and pass it on to
2265 // DisassembleNLdSt0().
2266 static bool DisassembleNLdSt(MCInst &MI, unsigned Opcode, uint32_t insn,
2267 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
2269 const StringRef Name = ARMInsts[Opcode].Name;
2270 bool DblSpaced = false;
2272 if (Name.find("LN") != std::string::npos) {
2273 // To one lane instructions.
2274 // See, for example, 8.6.317 VLD4 (single 4-element structure to one lane).
2276 // <size> == 16 && Inst{5} == 1 --> DblSpaced = true
2277 if (Name.endswith("16") || Name.endswith("16_UPD"))
2278 DblSpaced = slice(insn, 5, 5) == 1;
2280 // <size> == 32 && Inst{6} == 1 --> DblSpaced = true
2281 if (Name.endswith("32") || Name.endswith("32_UPD"))
2282 DblSpaced = slice(insn, 6, 6) == 1;
2285 // Multiple n-element structures with type encoded as Inst{11-8}.
2286 // See, for example, A8.6.316 VLD4 (multiple 4-element structures).
2288 // n == 2 && type == 0b1001 -> DblSpaced = true
2289 if (Name.startswith("VST2") || Name.startswith("VLD2"))
2290 DblSpaced = slice(insn, 11, 8) == 9;
2292 // n == 3 && type == 0b0101 -> DblSpaced = true
2293 if (Name.startswith("VST3") || Name.startswith("VLD3"))
2294 DblSpaced = slice(insn, 11, 8) == 5;
2296 // n == 4 && type == 0b0001 -> DblSpaced = true
2297 if (Name.startswith("VST4") || Name.startswith("VLD4"))
2298 DblSpaced = slice(insn, 11, 8) == 1;
2301 return DisassembleNLdSt0(MI, Opcode, insn, NumOps, NumOpsAdded,
2302 slice(insn, 21, 21) == 0, DblSpaced, B);
2307 static bool DisassembleN1RegModImmFrm(MCInst &MI, unsigned Opcode,
2308 uint32_t insn, unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
2310 const TargetInstrDesc &TID = ARMInsts[Opcode];
2311 const TargetOperandInfo *OpInfo = TID.OpInfo;
2313 assert(NumOps >= 2 &&
2314 (OpInfo[0].RegClass == ARM::DPRRegClassID ||
2315 OpInfo[0].RegClass == ARM::QPRRegClassID) &&
2316 (OpInfo[1].RegClass < 0) &&
2317 "Expect 1 reg operand followed by 1 imm operand");
2319 // Qd/Dd = Inst{22:15-12} => NEON Rd
2320 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, OpInfo[0].RegClass,
2321 decodeNEONRd(insn))));
2323 ElemSize esize = ESizeNA;
2326 case ARM::VMOVv16i8:
2329 case ARM::VMOVv4i16:
2330 case ARM::VMOVv8i16:
2331 case ARM::VMVNv4i16:
2332 case ARM::VMVNv8i16:
2335 case ARM::VMOVv2i32:
2336 case ARM::VMOVv4i32:
2337 case ARM::VMVNv2i32:
2338 case ARM::VMVNv4i32:
2341 case ARM::VMOVv1i64:
2342 case ARM::VMOVv2i64:
2346 assert(0 && "Unreachable code!");
2350 // One register and a modified immediate value.
2351 // Add the imm operand.
2352 MI.addOperand(MCOperand::CreateImm(decodeN1VImm(insn, esize)));
2362 N2V_VectorConvert_Between_Float_Fixed
2364 } // End of unnamed namespace
2366 // Vector Convert [between floating-point and fixed-point]
2367 // Qd/Dd Qm/Dm [fbits]
2369 // Vector Duplicate Lane (from scalar to all elements) Instructions.
2370 // VDUPLN16d, VDUPLN16q, VDUPLN32d, VDUPLN32q, VDUPLN8d, VDUPLN8q:
2373 // Vector Move Long:
2376 // Vector Move Narrow:
2380 static bool DisassembleNVdVmOptImm(MCInst &MI, unsigned Opc, uint32_t insn,
2381 unsigned short NumOps, unsigned &NumOpsAdded, N2VFlag Flag, BO B) {
2383 const TargetInstrDesc &TID = ARMInsts[Opc];
2384 const TargetOperandInfo *OpInfo = TID.OpInfo;
2386 assert(NumOps >= 2 &&
2387 (OpInfo[0].RegClass == ARM::DPRRegClassID ||
2388 OpInfo[0].RegClass == ARM::QPRRegClassID) &&
2389 (OpInfo[1].RegClass == ARM::DPRRegClassID ||
2390 OpInfo[1].RegClass == ARM::QPRRegClassID) &&
2391 "Expect >= 2 operands and first 2 as reg operands");
2393 unsigned &OpIdx = NumOpsAdded;
2397 ElemSize esize = ESizeNA;
2398 if (Flag == N2V_VectorDupLane) {
2399 // VDUPLN has its index embedded. Its size can be inferred from the Opcode.
2400 assert(Opc >= ARM::VDUPLN16d && Opc <= ARM::VDUPLN8q &&
2401 "Unexpected Opcode");
2402 esize = (Opc == ARM::VDUPLN8d || Opc == ARM::VDUPLN8q) ? ESize8
2403 : ((Opc == ARM::VDUPLN16d || Opc == ARM::VDUPLN16q) ? ESize16
2407 // Qd/Dd = Inst{22:15-12} => NEON Rd
2408 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, OpInfo[OpIdx].RegClass,
2409 decodeNEONRd(insn))));
2413 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1) {
2415 MI.addOperand(MCOperand::CreateReg(0));
2419 // Dm = Inst{5:3-0} => NEON Rm
2420 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, OpInfo[OpIdx].RegClass,
2421 decodeNEONRm(insn))));
2424 // VZIP and others have two TIED_TO reg operands.
2426 while (OpIdx < NumOps &&
2427 (Idx = TID.getOperandConstraint(OpIdx, TOI::TIED_TO)) != -1) {
2428 // Add TIED_TO operand.
2429 MI.addOperand(MI.getOperand(Idx));
2433 // Add the imm operand, if required.
2434 if (OpIdx < NumOps && OpInfo[OpIdx].RegClass < 0
2435 && !OpInfo[OpIdx].isPredicate() && !OpInfo[OpIdx].isOptionalDef()) {
2437 unsigned imm = 0xFFFFFFFF;
2439 if (Flag == N2V_VectorDupLane)
2440 imm = decodeNVLaneDupIndex(insn, esize);
2441 if (Flag == N2V_VectorConvert_Between_Float_Fixed)
2442 imm = decodeVCVTFractionBits(insn);
2444 assert(imm != 0xFFFFFFFF && "Internal error");
2445 MI.addOperand(MCOperand::CreateImm(imm));
2452 static bool DisassembleN2RegFrm(MCInst &MI, unsigned Opc, uint32_t insn,
2453 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
2455 return DisassembleNVdVmOptImm(MI, Opc, insn, NumOps, NumOpsAdded,
2458 static bool DisassembleNVCVTFrm(MCInst &MI, unsigned Opc, uint32_t insn,
2459 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
2461 return DisassembleNVdVmOptImm(MI, Opc, insn, NumOps, NumOpsAdded,
2462 N2V_VectorConvert_Between_Float_Fixed, B);
2464 static bool DisassembleNVecDupLnFrm(MCInst &MI, unsigned Opc, uint32_t insn,
2465 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
2467 return DisassembleNVdVmOptImm(MI, Opc, insn, NumOps, NumOpsAdded,
2468 N2V_VectorDupLane, B);
2471 // Vector Shift [Accumulate] Instructions.
2472 // Qd/Dd [Qd/Dd (TIED_TO)] Qm/Dm ShiftAmt
2474 // Vector Shift Left Long (with maximum shift count) Instructions.
2475 // VSHLLi16, VSHLLi32, VSHLLi8: Qd Dm imm (== size)
2477 static bool DisassembleNVectorShift(MCInst &MI, unsigned Opcode, uint32_t insn,
2478 unsigned short NumOps, unsigned &NumOpsAdded, bool LeftShift, BO B) {
2480 const TargetInstrDesc &TID = ARMInsts[Opcode];
2481 const TargetOperandInfo *OpInfo = TID.OpInfo;
2483 assert(NumOps >= 3 &&
2484 (OpInfo[0].RegClass == ARM::DPRRegClassID ||
2485 OpInfo[0].RegClass == ARM::QPRRegClassID) &&
2486 (OpInfo[1].RegClass == ARM::DPRRegClassID ||
2487 OpInfo[1].RegClass == ARM::QPRRegClassID) &&
2488 "Expect >= 3 operands and first 2 as reg operands");
2490 unsigned &OpIdx = NumOpsAdded;
2494 // Qd/Dd = Inst{22:15-12} => NEON Rd
2495 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, OpInfo[OpIdx].RegClass,
2496 decodeNEONRd(insn))));
2499 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1) {
2501 MI.addOperand(MCOperand::CreateReg(0));
2505 assert((OpInfo[OpIdx].RegClass == ARM::DPRRegClassID ||
2506 OpInfo[OpIdx].RegClass == ARM::QPRRegClassID) &&
2507 "Reg operand expected");
2509 // Qm/Dm = Inst{5:3-0} => NEON Rm
2510 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, OpInfo[OpIdx].RegClass,
2511 decodeNEONRm(insn))));
2514 assert(OpInfo[OpIdx].RegClass < 0 && "Imm operand expected");
2516 // Add the imm operand.
2518 // VSHLL has maximum shift count as the imm, inferred from its size.
2522 Imm = decodeNVSAmt(insn, LeftShift);
2534 MI.addOperand(MCOperand::CreateImm(Imm));
2540 // Left shift instructions.
2541 static bool DisassembleN2RegVecShLFrm(MCInst &MI, unsigned Opcode,
2542 uint32_t insn, unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
2544 return DisassembleNVectorShift(MI, Opcode, insn, NumOps, NumOpsAdded, true,
2547 // Right shift instructions have different shift amount interpretation.
2548 static bool DisassembleN2RegVecShRFrm(MCInst &MI, unsigned Opcode,
2549 uint32_t insn, unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
2551 return DisassembleNVectorShift(MI, Opcode, insn, NumOps, NumOpsAdded, false,
2560 N3V_Multiply_By_Scalar
2562 } // End of unnamed namespace
2564 // NEON Three Register Instructions with Optional Immediate Operand
2566 // Vector Extract Instructions.
2567 // Qd/Dd Qn/Dn Qm/Dm imm4
2569 // Vector Shift (Register) Instructions.
2570 // Qd/Dd Qm/Dm Qn/Dn (notice the order of m, n)
2572 // Vector Multiply [Accumulate/Subtract] [Long] By Scalar Instructions.
2573 // Qd/Dd Qn/Dn RestrictedDm index
2576 static bool DisassembleNVdVnVmOptImm(MCInst &MI, unsigned Opcode, uint32_t insn,
2577 unsigned short NumOps, unsigned &NumOpsAdded, N3VFlag Flag, BO B) {
2579 const TargetInstrDesc &TID = ARMInsts[Opcode];
2580 const TargetOperandInfo *OpInfo = TID.OpInfo;
2582 // No checking for OpInfo[2] because of MOVDneon/MOVQ with only two regs.
2583 assert(NumOps >= 3 &&
2584 (OpInfo[0].RegClass == ARM::DPRRegClassID ||
2585 OpInfo[0].RegClass == ARM::QPRRegClassID) &&
2586 (OpInfo[1].RegClass == ARM::DPRRegClassID ||
2587 OpInfo[1].RegClass == ARM::QPRRegClassID) &&
2588 "Expect >= 3 operands and first 2 as reg operands");
2590 unsigned &OpIdx = NumOpsAdded;
2594 bool VdVnVm = Flag == N3V_VectorShift ? false : true;
2595 bool IsImm4 = Flag == N3V_VectorExtract ? true : false;
2596 bool IsDmRestricted = Flag == N3V_Multiply_By_Scalar ? true : false;
2597 ElemSize esize = ESizeNA;
2598 if (Flag == N3V_Multiply_By_Scalar) {
2599 unsigned size = (insn >> 20) & 3;
2600 if (size == 1) esize = ESize16;
2601 if (size == 2) esize = ESize32;
2602 assert (esize == ESize16 || esize == ESize32);
2605 // Qd/Dd = Inst{22:15-12} => NEON Rd
2606 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, OpInfo[OpIdx].RegClass,
2607 decodeNEONRd(insn))));
2610 // VABA, VABAL, VBSLd, VBSLq, ...
2611 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1) {
2613 MI.addOperand(MCOperand::CreateReg(0));
2617 // Dn = Inst{7:19-16} => NEON Rn
2619 // Dm = Inst{5:3-0} => NEON Rm
2620 MI.addOperand(MCOperand::CreateReg(
2621 getRegisterEnum(B, OpInfo[OpIdx].RegClass,
2622 VdVnVm ? decodeNEONRn(insn)
2623 : decodeNEONRm(insn))));
2626 // Special case handling for VMOVDneon and VMOVQ because they are marked as
2628 if (Opcode == ARM::VMOVDneon || Opcode == ARM::VMOVQ)
2631 // Dm = Inst{5:3-0} => NEON Rm
2633 // Dm is restricted to D0-D7 if size is 16, D0-D15 otherwise
2635 // Dn = Inst{7:19-16} => NEON Rn
2636 unsigned m = VdVnVm ? (IsDmRestricted ? decodeRestrictedDm(insn, esize)
2637 : decodeNEONRm(insn))
2638 : decodeNEONRn(insn);
2640 MI.addOperand(MCOperand::CreateReg(
2641 getRegisterEnum(B, OpInfo[OpIdx].RegClass, m)));
2644 if (OpIdx < NumOps && OpInfo[OpIdx].RegClass < 0
2645 && !OpInfo[OpIdx].isPredicate() && !OpInfo[OpIdx].isOptionalDef()) {
2646 // Add the imm operand.
2649 Imm = decodeN3VImm(insn);
2650 else if (IsDmRestricted)
2651 Imm = decodeRestrictedDmIndex(insn, esize);
2653 assert(0 && "Internal error: unreachable code!");
2657 MI.addOperand(MCOperand::CreateImm(Imm));
2664 static bool DisassembleN3RegFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
2665 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
2667 return DisassembleNVdVnVmOptImm(MI, Opcode, insn, NumOps, NumOpsAdded,
2670 static bool DisassembleN3RegVecShFrm(MCInst &MI, unsigned Opcode,
2671 uint32_t insn, unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
2673 return DisassembleNVdVnVmOptImm(MI, Opcode, insn, NumOps, NumOpsAdded,
2674 N3V_VectorShift, B);
2676 static bool DisassembleNVecExtractFrm(MCInst &MI, unsigned Opcode,
2677 uint32_t insn, unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
2679 return DisassembleNVdVnVmOptImm(MI, Opcode, insn, NumOps, NumOpsAdded,
2680 N3V_VectorExtract, B);
2682 static bool DisassembleNVecMulScalarFrm(MCInst &MI, unsigned Opcode,
2683 uint32_t insn, unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
2685 return DisassembleNVdVnVmOptImm(MI, Opcode, insn, NumOps, NumOpsAdded,
2686 N3V_Multiply_By_Scalar, B);
2689 // Vector Table Lookup
2691 // VTBL1, VTBX1: Dd [Dd(TIED_TO)] Dn Dm
2692 // VTBL2, VTBX2: Dd [Dd(TIED_TO)] Dn Dn+1 Dm
2693 // VTBL3, VTBX3: Dd [Dd(TIED_TO)] Dn Dn+1 Dn+2 Dm
2694 // VTBL4, VTBX4: Dd [Dd(TIED_TO)] Dn Dn+1 Dn+2 Dn+3 Dm
2695 static bool DisassembleNVTBLFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
2696 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
2698 const TargetInstrDesc &TID = ARMInsts[Opcode];
2699 const TargetOperandInfo *OpInfo = TID.OpInfo;
2700 if (!OpInfo) return false;
2702 assert(NumOps >= 3 &&
2703 OpInfo[0].RegClass == ARM::DPRRegClassID &&
2704 OpInfo[1].RegClass == ARM::DPRRegClassID &&
2705 OpInfo[2].RegClass == ARM::DPRRegClassID &&
2706 "Expect >= 3 operands and first 3 as reg operands");
2708 unsigned &OpIdx = NumOpsAdded;
2712 unsigned Rn = decodeNEONRn(insn);
2714 // {Dn} encoded as len = 0b00
2715 // {Dn Dn+1} encoded as len = 0b01
2716 // {Dn Dn+1 Dn+2 } encoded as len = 0b10
2717 // {Dn Dn+1 Dn+2 Dn+3} encoded as len = 0b11
2718 unsigned Len = slice(insn, 9, 8) + 1;
2720 // Dd (the destination vector)
2721 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::DPRRegClassID,
2722 decodeNEONRd(insn))));
2725 // Process tied_to operand constraint.
2727 if ((Idx = TID.getOperandConstraint(OpIdx, TOI::TIED_TO)) != -1) {
2728 MI.addOperand(MI.getOperand(Idx));
2732 // Do the <list> now.
2733 for (unsigned i = 0; i < Len; ++i) {
2734 assert(OpIdx < NumOps && OpInfo[OpIdx].RegClass == ARM::DPRRegClassID &&
2735 "Reg operand expected");
2736 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::DPRRegClassID,
2741 // Dm (the index vector)
2742 assert(OpIdx < NumOps && OpInfo[OpIdx].RegClass == ARM::DPRRegClassID &&
2743 "Reg operand (index vector) expected");
2744 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::DPRRegClassID,
2745 decodeNEONRm(insn))));
2751 // Vector Get Lane (move scalar to ARM core register) Instructions.
2752 // VGETLNi32, VGETLNs16, VGETLNs8, VGETLNu16, VGETLNu8: Rt Dn index
2753 static bool DisassembleNGetLnFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
2754 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
2756 const TargetInstrDesc &TID = ARMInsts[Opcode];
2757 const TargetOperandInfo *OpInfo = TID.OpInfo;
2758 if (!OpInfo) return false;
2760 assert(TID.getNumDefs() == 1 && NumOps >= 3 &&
2761 OpInfo[0].RegClass == ARM::GPRRegClassID &&
2762 OpInfo[1].RegClass == ARM::DPRRegClassID &&
2763 OpInfo[2].RegClass < 0 &&
2764 "Expect >= 3 operands with one dst operand");
2767 Opcode == ARM::VGETLNi32 ? ESize32
2768 : ((Opcode == ARM::VGETLNs16 || Opcode == ARM::VGETLNu16) ? ESize16
2771 // Rt = Inst{15-12} => ARM Rd
2772 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
2775 // Dn = Inst{7:19-16} => NEON Rn
2776 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::DPRRegClassID,
2777 decodeNEONRn(insn))));
2779 MI.addOperand(MCOperand::CreateImm(decodeNVLaneOpIndex(insn, esize)));
2785 // Vector Set Lane (move ARM core register to scalar) Instructions.
2786 // VSETLNi16, VSETLNi32, VSETLNi8: Dd Dd (TIED_TO) Rt index
2787 static bool DisassembleNSetLnFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
2788 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
2790 const TargetInstrDesc &TID = ARMInsts[Opcode];
2791 const TargetOperandInfo *OpInfo = TID.OpInfo;
2792 if (!OpInfo) return false;
2794 assert(TID.getNumDefs() == 1 && NumOps >= 3 &&
2795 OpInfo[0].RegClass == ARM::DPRRegClassID &&
2796 OpInfo[1].RegClass == ARM::DPRRegClassID &&
2797 TID.getOperandConstraint(1, TOI::TIED_TO) != -1 &&
2798 OpInfo[2].RegClass == ARM::GPRRegClassID &&
2799 OpInfo[3].RegClass < 0 &&
2800 "Expect >= 3 operands with one dst operand");
2803 Opcode == ARM::VSETLNi8 ? ESize8
2804 : (Opcode == ARM::VSETLNi16 ? ESize16
2807 // Dd = Inst{7:19-16} => NEON Rn
2808 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::DPRRegClassID,
2809 decodeNEONRn(insn))));
2812 MI.addOperand(MCOperand::CreateReg(0));
2814 // Rt = Inst{15-12} => ARM Rd
2815 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
2818 MI.addOperand(MCOperand::CreateImm(decodeNVLaneOpIndex(insn, esize)));
2824 // Vector Duplicate Instructions (from ARM core register to all elements).
2825 // VDUP8d, VDUP16d, VDUP32d, VDUP8q, VDUP16q, VDUP32q: Qd/Dd Rt
2826 static bool DisassembleNDupFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
2827 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
2829 const TargetOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo;
2831 assert(NumOps >= 2 &&
2832 (OpInfo[0].RegClass == ARM::DPRRegClassID ||
2833 OpInfo[0].RegClass == ARM::QPRRegClassID) &&
2834 OpInfo[1].RegClass == ARM::GPRRegClassID &&
2835 "Expect >= 2 operands and first 2 as reg operand");
2837 unsigned RegClass = OpInfo[0].RegClass;
2839 // Qd/Dd = Inst{7:19-16} => NEON Rn
2840 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, RegClass,
2841 decodeNEONRn(insn))));
2843 // Rt = Inst{15-12} => ARM Rd
2844 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
2854 static inline bool MemBarrierInstr(uint32_t insn) {
2855 unsigned op7_4 = slice(insn, 7, 4);
2856 if (slice(insn, 31, 8) == 0xf57ff0 && (op7_4 >= 4 && op7_4 <= 6))
2862 static inline bool PreLoadOpcode(unsigned Opcode) {
2864 case ARM::PLDi12: case ARM::PLDrs:
2865 case ARM::PLDWi12: case ARM::PLDWrs:
2866 case ARM::PLIi12: case ARM::PLIrs:
2873 static bool DisassemblePreLoadFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
2874 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
2876 // Preload Data/Instruction requires either 2 or 3 operands.
2877 // PLDi, PLDWi, PLIi: addrmode_imm12
2878 // PLDr[a|m], PLDWr[a|m], PLIr[a|m]: ldst_so_reg
2880 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
2883 if (Opcode == ARM::PLDi12 || Opcode == ARM::PLDWi12
2884 || Opcode == ARM::PLIi12) {
2885 unsigned Imm12 = slice(insn, 11, 0);
2886 bool Negative = getUBit(insn) == 0;
2887 // -0 is represented specially. All other values are as normal.
2888 if (Imm12 == 0 && Negative)
2890 MI.addOperand(MCOperand::CreateImm(Imm12));
2893 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
2896 ARM_AM::AddrOpc AddrOpcode = getUBit(insn) ? ARM_AM::add : ARM_AM::sub;
2898 // Inst{6-5} encodes the shift opcode.
2899 ARM_AM::ShiftOpc ShOp = getShiftOpcForBits(slice(insn, 6, 5));
2900 // Inst{11-7} encodes the imm5 shift amount.
2901 unsigned ShImm = slice(insn, 11, 7);
2903 // A8.4.1. Possible rrx or shift amount of 32...
2904 getImmShiftSE(ShOp, ShImm);
2905 MI.addOperand(MCOperand::CreateImm(
2906 ARM_AM::getAM2Opc(AddrOpcode, ShImm, ShOp)));
2913 static bool DisassembleMiscFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
2914 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
2916 if (MemBarrierInstr(insn)) {
2917 // DMBsy, DSBsy, and ISBsy instructions have zero operand and are taken care
2918 // of within the generic ARMBasicMCBuilder::BuildIt() method.
2920 // Inst{3-0} encodes the memory barrier option for the variants.
2921 MI.addOperand(MCOperand::CreateImm(slice(insn, 3, 0)));
2939 if (Opcode == ARM::SETEND) {
2941 MI.addOperand(MCOperand::CreateImm(slice(insn, 9, 9)));
2945 // CPS has a singleton $opt operand that contains the following information:
2946 // opt{4-0} = mode from Inst{4-0}
2947 // opt{5} = changemode from Inst{17}
2948 // opt{8-6} = AIF from Inst{8-6}
2949 // opt{10-9} = imod from Inst{19-18} with 0b10 as enable and 0b11 as disable
2950 if (Opcode == ARM::CPS) {
2951 unsigned Option = slice(insn, 4, 0) | slice(insn, 17, 17) << 5 |
2952 slice(insn, 8, 6) << 6 | slice(insn, 19, 18) << 9;
2953 MI.addOperand(MCOperand::CreateImm(Option));
2958 // DBG has its option specified in Inst{3-0}.
2959 if (Opcode == ARM::DBG) {
2960 MI.addOperand(MCOperand::CreateImm(slice(insn, 3, 0)));
2965 // BKPT takes an imm32 val equal to ZeroExtend(Inst{19-8:3-0}).
2966 if (Opcode == ARM::BKPT) {
2967 MI.addOperand(MCOperand::CreateImm(slice(insn, 19, 8) << 4 |
2968 slice(insn, 3, 0)));
2973 if (PreLoadOpcode(Opcode))
2974 return DisassemblePreLoadFrm(MI, Opcode, insn, NumOps, NumOpsAdded, B);
2976 assert(0 && "Unexpected misc instruction!");
2980 /// FuncPtrs - FuncPtrs maps ARMFormat to its corresponding DisassembleFP.
2981 /// We divide the disassembly task into different categories, with each one
2982 /// corresponding to a specific instruction encoding format. There could be
2983 /// exceptions when handling a specific format, and that is why the Opcode is
2984 /// also present in the function prototype.
2985 static const DisassembleFP FuncPtrs[] = {
2989 &DisassembleBrMiscFrm,
2991 &DisassembleDPSoRegFrm,
2994 &DisassembleLdMiscFrm,
2995 &DisassembleStMiscFrm,
2996 &DisassembleLdStMulFrm,
2997 &DisassembleLdStExFrm,
2998 &DisassembleArithMiscFrm,
3001 &DisassembleVFPUnaryFrm,
3002 &DisassembleVFPBinaryFrm,
3003 &DisassembleVFPConv1Frm,
3004 &DisassembleVFPConv2Frm,
3005 &DisassembleVFPConv3Frm,
3006 &DisassembleVFPConv4Frm,
3007 &DisassembleVFPConv5Frm,
3008 &DisassembleVFPLdStFrm,
3009 &DisassembleVFPLdStMulFrm,
3010 &DisassembleVFPMiscFrm,
3011 &DisassembleThumbFrm,
3012 &DisassembleMiscFrm,
3013 &DisassembleNGetLnFrm,
3014 &DisassembleNSetLnFrm,
3015 &DisassembleNDupFrm,
3017 // VLD and VST (including one lane) Instructions.
3020 // A7.4.6 One register and a modified immediate value
3021 // 1-Register Instructions with imm.
3022 // LLVM only defines VMOVv instructions.
3023 &DisassembleN1RegModImmFrm,
3025 // 2-Register Instructions with no imm.
3026 &DisassembleN2RegFrm,
3028 // 2-Register Instructions with imm (vector convert float/fixed point).
3029 &DisassembleNVCVTFrm,
3031 // 2-Register Instructions with imm (vector dup lane).
3032 &DisassembleNVecDupLnFrm,
3034 // Vector Shift Left Instructions.
3035 &DisassembleN2RegVecShLFrm,
3037 // Vector Shift Righ Instructions, which has different interpretation of the
3038 // shift amount from the imm6 field.
3039 &DisassembleN2RegVecShRFrm,
3041 // 3-Register Data-Processing Instructions.
3042 &DisassembleN3RegFrm,
3044 // Vector Shift (Register) Instructions.
3045 // D:Vd M:Vm N:Vn (notice that M:Vm is the first operand)
3046 &DisassembleN3RegVecShFrm,
3048 // Vector Extract Instructions.
3049 &DisassembleNVecExtractFrm,
3051 // Vector [Saturating Rounding Doubling] Multiply [Accumulate/Subtract] [Long]
3052 // By Scalar Instructions.
3053 &DisassembleNVecMulScalarFrm,
3055 // Vector Table Lookup uses byte indexes in a control vector to look up byte
3056 // values in a table and generate a new vector.
3057 &DisassembleNVTBLFrm,
3062 /// BuildIt - BuildIt performs the build step for this ARM Basic MC Builder.
3063 /// The general idea is to set the Opcode for the MCInst, followed by adding
3064 /// the appropriate MCOperands to the MCInst. ARM Basic MC Builder delegates
3065 /// to the Format-specific disassemble function for disassembly, followed by
3066 /// TryPredicateAndSBitModifier() to do PredicateOperand and OptionalDefOperand
3067 /// which follow the Dst/Src Operands.
3068 bool ARMBasicMCBuilder::BuildIt(MCInst &MI, uint32_t insn) {
3069 // Stage 1 sets the Opcode.
3070 MI.setOpcode(Opcode);
3071 // If the number of operands is zero, we're done!
3075 // Stage 2 calls the format-specific disassemble function to build the operand
3079 unsigned NumOpsAdded = 0;
3080 bool OK = (*Disasm)(MI, Opcode, insn, NumOps, NumOpsAdded, this);
3082 if (!OK || this->Err != 0) return false;
3083 if (NumOpsAdded >= NumOps)
3086 // Stage 3 deals with operands unaccounted for after stage 2 is finished.
3087 // FIXME: Should this be done selectively?
3088 return TryPredicateAndSBitModifier(MI, Opcode, insn, NumOps - NumOpsAdded);
3091 // A8.3 Conditional execution
3092 // A8.3.1 Pseudocode details of conditional execution
3093 // Condition bits '111x' indicate the instruction is always executed.
3094 static uint32_t CondCode(uint32_t CondField) {
3095 if (CondField == 0xF)
3100 /// DoPredicateOperands - DoPredicateOperands process the predicate operands
3101 /// of some Thumb instructions which come before the reglist operands. It
3102 /// returns true if the two predicate operands have been processed.
3103 bool ARMBasicMCBuilder::DoPredicateOperands(MCInst& MI, unsigned Opcode,
3104 uint32_t /* insn */, unsigned short NumOpsRemaining) {
3106 assert(NumOpsRemaining > 0 && "Invalid argument");
3108 const TargetOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo;
3109 unsigned Idx = MI.getNumOperands();
3111 // First, we check whether this instr specifies the PredicateOperand through
3112 // a pair of TargetOperandInfos with isPredicate() property.
3113 if (NumOpsRemaining >= 2 &&
3114 OpInfo[Idx].isPredicate() && OpInfo[Idx+1].isPredicate() &&
3115 OpInfo[Idx].RegClass < 0 &&
3116 OpInfo[Idx+1].RegClass == ARM::CCRRegClassID)
3118 // If we are inside an IT block, get the IT condition bits maintained via
3119 // ARMBasicMCBuilder::ITState[7:0], through ARMBasicMCBuilder::GetITCond().
3122 MI.addOperand(MCOperand::CreateImm(GetITCond()));
3124 MI.addOperand(MCOperand::CreateImm(ARMCC::AL));
3125 MI.addOperand(MCOperand::CreateReg(ARM::CPSR));
3132 /// TryPredicateAndSBitModifier - TryPredicateAndSBitModifier tries to process
3133 /// the possible Predicate and SBitModifier, to build the remaining MCOperand
3135 bool ARMBasicMCBuilder::TryPredicateAndSBitModifier(MCInst& MI, unsigned Opcode,
3136 uint32_t insn, unsigned short NumOpsRemaining) {
3138 assert(NumOpsRemaining > 0 && "Invalid argument");
3140 const TargetOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo;
3141 const std::string &Name = ARMInsts[Opcode].Name;
3142 unsigned Idx = MI.getNumOperands();
3144 // First, we check whether this instr specifies the PredicateOperand through
3145 // a pair of TargetOperandInfos with isPredicate() property.
3146 if (NumOpsRemaining >= 2 &&
3147 OpInfo[Idx].isPredicate() && OpInfo[Idx+1].isPredicate() &&
3148 OpInfo[Idx].RegClass < 0 &&
3149 OpInfo[Idx+1].RegClass == ARM::CCRRegClassID)
3151 // If we are inside an IT block, get the IT condition bits maintained via
3152 // ARMBasicMCBuilder::ITState[7:0], through ARMBasicMCBuilder::GetITCond().
3155 MI.addOperand(MCOperand::CreateImm(GetITCond()));
3157 if (Name.length() > 1 && Name[0] == 't') {
3158 // Thumb conditional branch instructions have their cond field embedded,
3162 if (Name == "t2Bcc")
3163 MI.addOperand(MCOperand::CreateImm(CondCode(slice(insn, 25, 22))));
3164 else if (Name == "tBcc")
3165 MI.addOperand(MCOperand::CreateImm(CondCode(slice(insn, 11, 8))));
3167 MI.addOperand(MCOperand::CreateImm(ARMCC::AL));
3169 // ARM instructions get their condition field from Inst{31-28}.
3170 MI.addOperand(MCOperand::CreateImm(CondCode(getCondField(insn))));
3173 MI.addOperand(MCOperand::CreateReg(ARM::CPSR));
3175 NumOpsRemaining -= 2;
3178 if (NumOpsRemaining == 0)
3181 // Next, if OptionalDefOperand exists, we check whether the 'S' bit is set.
3182 if (OpInfo[Idx].isOptionalDef() && OpInfo[Idx].RegClass==ARM::CCRRegClassID) {
3183 MI.addOperand(MCOperand::CreateReg(getSBit(insn) == 1 ? ARM::CPSR : 0));
3187 if (NumOpsRemaining == 0)
3193 /// RunBuildAfterHook - RunBuildAfterHook performs operations deemed necessary
3194 /// after BuildIt is finished.
3195 bool ARMBasicMCBuilder::RunBuildAfterHook(bool Status, MCInst &MI,
3198 if (!SP) return Status;
3200 if (Opcode == ARM::t2IT)
3201 Status = SP->InitIT(slice(insn, 7, 0)) ? Status : false;
3202 else if (InITBlock())
3208 /// Opcode, Format, and NumOperands make up an ARM Basic MCBuilder.
3209 ARMBasicMCBuilder::ARMBasicMCBuilder(unsigned opc, ARMFormat format,
3211 : Opcode(opc), Format(format), NumOps(num), SP(0), Err(0) {
3212 unsigned Idx = (unsigned)format;
3213 assert(Idx < (array_lengthof(FuncPtrs) - 1) && "Unknown format");
3214 Disasm = FuncPtrs[Idx];
3217 /// CreateMCBuilder - Return an ARMBasicMCBuilder that can build up the MC
3218 /// infrastructure of an MCInst given the Opcode and Format of the instr.
3219 /// Return NULL if it fails to create/return a proper builder. API clients
3220 /// are responsible for freeing up of the allocated memory. Cacheing can be
3221 /// performed by the API clients to improve performance.
3222 ARMBasicMCBuilder *llvm::CreateMCBuilder(unsigned Opcode, ARMFormat Format) {
3223 // For "Unknown format", fail by returning a NULL pointer.
3224 if ((unsigned)Format >= (array_lengthof(FuncPtrs) - 1)) {
3225 DEBUG(errs() << "Unknown format\n");
3229 return new ARMBasicMCBuilder(Opcode, Format,
3230 ARMInsts[Opcode].getNumOperands());