1 //===-- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA --------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "llvm/MC/MCDisassembler.h"
11 #include "MCTargetDesc/ARMAddressingModes.h"
12 #include "MCTargetDesc/ARMBaseInfo.h"
13 #include "MCTargetDesc/ARMMCExpr.h"
14 #include "llvm/MC/MCContext.h"
15 #include "llvm/MC/MCExpr.h"
16 #include "llvm/MC/MCFixedLenDisassembler.h"
17 #include "llvm/MC/MCInst.h"
18 #include "llvm/MC/MCInstrDesc.h"
19 #include "llvm/MC/MCSubtargetInfo.h"
20 #include "llvm/Support/Debug.h"
21 #include "llvm/Support/ErrorHandling.h"
22 #include "llvm/Support/LEB128.h"
23 #include "llvm/Support/MemoryObject.h"
24 #include "llvm/Support/TargetRegistry.h"
25 #include "llvm/Support/raw_ostream.h"
30 #define DEBUG_TYPE "arm-disassembler"
32 typedef MCDisassembler::DecodeStatus DecodeStatus;
35 // Handles the condition code status of instructions in IT blocks
39 // Returns the condition code for instruction in IT block
41 unsigned CC = ARMCC::AL;
47 // Advances the IT block state to the next T or E
48 void advanceITState() {
52 // Returns true if the current instruction is in an IT block
53 bool instrInITBlock() {
54 return !ITStates.empty();
57 // Returns true if current instruction is the last instruction in an IT block
58 bool instrLastInITBlock() {
59 return ITStates.size() == 1;
62 // Called when decoding an IT instruction. Sets the IT state for the following
63 // instructions that for the IT block. Firstcond and Mask correspond to the
64 // fields in the IT instruction encoding.
65 void setITState(char Firstcond, char Mask) {
66 // (3 - the number of trailing zeros) is the number of then / else.
67 unsigned CondBit0 = Firstcond & 1;
68 unsigned NumTZ = countTrailingZeros<uint8_t>(Mask);
69 unsigned char CCBits = static_cast<unsigned char>(Firstcond & 0xf);
70 assert(NumTZ <= 3 && "Invalid IT mask!");
71 // push condition codes onto the stack the correct order for the pops
72 for (unsigned Pos = NumTZ+1; Pos <= 3; ++Pos) {
73 bool T = ((Mask >> Pos) & 1) == CondBit0;
75 ITStates.push_back(CCBits);
77 ITStates.push_back(CCBits ^ 1);
79 ITStates.push_back(CCBits);
83 std::vector<unsigned char> ITStates;
88 /// ARM disassembler for all ARM platforms.
89 class ARMDisassembler : public MCDisassembler {
91 ARMDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) :
92 MCDisassembler(STI, Ctx) {
97 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
98 const MemoryObject &Region, uint64_t Address,
100 raw_ostream &CStream) const override;
103 /// Thumb disassembler for all Thumb platforms.
104 class ThumbDisassembler : public MCDisassembler {
106 ThumbDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) :
107 MCDisassembler(STI, Ctx) {
110 ~ThumbDisassembler() {}
112 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
113 const MemoryObject &Region, uint64_t Address,
114 raw_ostream &VStream,
115 raw_ostream &CStream) const override;
118 mutable ITStatus ITBlock;
119 DecodeStatus AddThumbPredicate(MCInst&) const;
120 void UpdateThumbVFPPredicate(MCInst&) const;
124 static bool Check(DecodeStatus &Out, DecodeStatus In) {
126 case MCDisassembler::Success:
127 // Out stays the same.
129 case MCDisassembler::SoftFail:
132 case MCDisassembler::Fail:
136 llvm_unreachable("Invalid DecodeStatus!");
140 // Forward declare these because the autogenerated code will reference them.
141 // Definitions are further down.
142 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo,
143 uint64_t Address, const void *Decoder);
144 static DecodeStatus DecodeGPRnopcRegisterClass(MCInst &Inst,
145 unsigned RegNo, uint64_t Address,
146 const void *Decoder);
147 static DecodeStatus DecodeGPRwithAPSRRegisterClass(MCInst &Inst,
148 unsigned RegNo, uint64_t Address,
149 const void *Decoder);
150 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo,
151 uint64_t Address, const void *Decoder);
152 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo,
153 uint64_t Address, const void *Decoder);
154 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo,
155 uint64_t Address, const void *Decoder);
156 static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo,
157 uint64_t Address, const void *Decoder);
158 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo,
159 uint64_t Address, const void *Decoder);
160 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo,
161 uint64_t Address, const void *Decoder);
162 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo,
163 uint64_t Address, const void *Decoder);
164 static DecodeStatus DecodeDPR_VFP2RegisterClass(MCInst &Inst,
167 const void *Decoder);
168 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo,
169 uint64_t Address, const void *Decoder);
170 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo,
171 uint64_t Address, const void *Decoder);
172 static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst,
173 unsigned RegNo, uint64_t Address,
174 const void *Decoder);
176 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val,
177 uint64_t Address, const void *Decoder);
178 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val,
179 uint64_t Address, const void *Decoder);
180 static DecodeStatus DecodeSOImmOperand(MCInst &Inst, unsigned Val,
181 uint64_t Address, const void *Decoder);
182 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val,
183 uint64_t Address, const void *Decoder);
184 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val,
185 uint64_t Address, const void *Decoder);
186 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val,
187 uint64_t Address, const void *Decoder);
189 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Insn,
190 uint64_t Address, const void *Decoder);
191 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn,
192 uint64_t Address, const void *Decoder);
193 static DecodeStatus DecodeAddrMode2IdxInstruction(MCInst &Inst,
196 const void *Decoder);
197 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Insn,
198 uint64_t Address, const void *Decoder);
199 static DecodeStatus DecodeAddrMode3Instruction(MCInst &Inst,unsigned Insn,
200 uint64_t Address, const void *Decoder);
201 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Insn,
202 uint64_t Address, const void *Decoder);
203 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Insn,
204 uint64_t Address, const void *Decoder);
206 static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst & Inst,
209 const void *Decoder);
210 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn,
211 uint64_t Address, const void *Decoder);
212 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn,
213 uint64_t Address, const void *Decoder);
214 static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn,
215 uint64_t Address, const void *Decoder);
216 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn,
217 uint64_t Address, const void *Decoder);
218 static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn,
219 uint64_t Address, const void *Decoder);
220 static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val,
221 uint64_t Address, const void *Decoder);
222 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val,
223 uint64_t Address, const void *Decoder);
224 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val,
225 uint64_t Address, const void *Decoder);
226 static DecodeStatus DecodeT2BInstruction(MCInst &Inst, unsigned Insn,
227 uint64_t Address, const void *Decoder);
228 static DecodeStatus DecodeBranchImmInstruction(MCInst &Inst,unsigned Insn,
229 uint64_t Address, const void *Decoder);
230 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val,
231 uint64_t Address, const void *Decoder);
232 static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Val,
233 uint64_t Address, const void *Decoder);
234 static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Val,
235 uint64_t Address, const void *Decoder);
236 static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Val,
237 uint64_t Address, const void *Decoder);
238 static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Val,
239 uint64_t Address, const void *Decoder);
240 static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Val,
241 uint64_t Address, const void *Decoder);
242 static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Val,
243 uint64_t Address, const void *Decoder);
244 static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Val,
245 uint64_t Address, const void *Decoder);
246 static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Val,
247 uint64_t Address, const void *Decoder);
248 static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Val,
249 uint64_t Address, const void *Decoder);
250 static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Val,
251 uint64_t Address, const void *Decoder);
252 static DecodeStatus DecodeNEONModImmInstruction(MCInst &Inst,unsigned Val,
253 uint64_t Address, const void *Decoder);
254 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Val,
255 uint64_t Address, const void *Decoder);
256 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val,
257 uint64_t Address, const void *Decoder);
258 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val,
259 uint64_t Address, const void *Decoder);
260 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val,
261 uint64_t Address, const void *Decoder);
262 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val,
263 uint64_t Address, const void *Decoder);
264 static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn,
265 uint64_t Address, const void *Decoder);
266 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn,
267 uint64_t Address, const void *Decoder);
268 static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Insn,
269 uint64_t Address, const void *Decoder);
270 static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Insn,
271 uint64_t Address, const void *Decoder);
272 static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Insn,
273 uint64_t Address, const void *Decoder);
274 static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Insn,
275 uint64_t Address, const void *Decoder);
276 static DecodeStatus DecodeBankedReg(MCInst &Inst, unsigned Insn,
277 uint64_t Address, const void *Decoder);
278 static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn,
279 uint64_t Address, const void *Decoder);
280 static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn,
281 uint64_t Address, const void *Decoder);
282 static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn,
283 uint64_t Address, const void *Decoder);
284 static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn,
285 uint64_t Address, const void *Decoder);
286 static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn,
287 uint64_t Address, const void *Decoder);
288 static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn,
289 uint64_t Address, const void *Decoder);
290 static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn,
291 uint64_t Address, const void *Decoder);
292 static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn,
293 uint64_t Address, const void *Decoder);
294 static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn,
295 uint64_t Address, const void *Decoder);
296 static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn,
297 uint64_t Address, const void *Decoder);
298 static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn,
299 uint64_t Address, const void *Decoder);
300 static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn,
301 uint64_t Address, const void *Decoder);
302 static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn,
303 uint64_t Address, const void *Decoder);
304 static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn,
305 uint64_t Address, const void *Decoder);
306 static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn,
307 uint64_t Address, const void *Decoder);
308 static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn,
309 uint64_t Address, const void *Decoder);
310 static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn,
311 uint64_t Address, const void *Decoder);
312 static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn,
313 uint64_t Address, const void *Decoder);
314 static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn,
315 uint64_t Address, const void *Decoder);
318 static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn,
319 uint64_t Address, const void *Decoder);
320 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val,
321 uint64_t Address, const void *Decoder);
322 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val,
323 uint64_t Address, const void *Decoder);
324 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val,
325 uint64_t Address, const void *Decoder);
326 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val,
327 uint64_t Address, const void *Decoder);
328 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val,
329 uint64_t Address, const void *Decoder);
330 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val,
331 uint64_t Address, const void *Decoder);
332 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val,
333 uint64_t Address, const void *Decoder);
334 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val,
335 uint64_t Address, const void *Decoder);
336 static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Val,
337 uint64_t Address, const void *Decoder);
338 static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn,
339 uint64_t Address, const void* Decoder);
340 static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn,
341 uint64_t Address, const void* Decoder);
342 static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn,
343 uint64_t Address, const void* Decoder);
344 static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn,
345 uint64_t Address, const void* Decoder);
346 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val,
347 uint64_t Address, const void *Decoder);
348 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val,
349 uint64_t Address, const void *Decoder);
350 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val,
351 uint64_t Address, const void *Decoder);
352 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val,
353 uint64_t Address, const void *Decoder);
354 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val,
355 uint64_t Address, const void *Decoder);
356 static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Val,
357 uint64_t Address, const void *Decoder);
358 static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn,
359 uint64_t Address, const void *Decoder);
360 static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn,
361 uint64_t Address, const void *Decoder);
362 static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn,
363 uint64_t Address, const void *Decoder);
364 static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Insn,
365 uint64_t Address, const void *Decoder);
366 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val,
367 uint64_t Address, const void *Decoder);
368 static DecodeStatus DecodeThumbTableBranch(MCInst &Inst, unsigned Val,
369 uint64_t Address, const void *Decoder);
370 static DecodeStatus DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Val,
371 uint64_t Address, const void *Decoder);
372 static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val,
373 uint64_t Address, const void *Decoder);
374 static DecodeStatus DecodeThumbBCCTargetOperand(MCInst &Inst,unsigned Val,
375 uint64_t Address, const void *Decoder);
376 static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val,
377 uint64_t Address, const void *Decoder);
378 static DecodeStatus DecodeIT(MCInst &Inst, unsigned Val,
379 uint64_t Address, const void *Decoder);
380 static DecodeStatus DecodeT2LDRDPreInstruction(MCInst &Inst,unsigned Insn,
381 uint64_t Address, const void *Decoder);
382 static DecodeStatus DecodeT2STRDPreInstruction(MCInst &Inst,unsigned Insn,
383 uint64_t Address, const void *Decoder);
384 static DecodeStatus DecodeT2Adr(MCInst &Inst, unsigned Val,
385 uint64_t Address, const void *Decoder);
386 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Val,
387 uint64_t Address, const void *Decoder);
388 static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, unsigned Val,
389 uint64_t Address, const void *Decoder);
391 static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val,
392 uint64_t Address, const void *Decoder);
393 static DecodeStatus DecodeMRRC2(llvm::MCInst &Inst, unsigned Val,
394 uint64_t Address, const void *Decoder);
395 #include "ARMGenDisassemblerTables.inc"
397 static MCDisassembler *createARMDisassembler(const Target &T,
398 const MCSubtargetInfo &STI,
400 return new ARMDisassembler(STI, Ctx);
403 static MCDisassembler *createThumbDisassembler(const Target &T,
404 const MCSubtargetInfo &STI,
406 return new ThumbDisassembler(STI, Ctx);
409 DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
410 const MemoryObject &Region,
411 uint64_t Address, raw_ostream &OS,
412 raw_ostream &CS) const {
417 assert(!(STI.getFeatureBits() & ARM::ModeThumb) &&
418 "Asked to disassemble an ARM instruction but Subtarget is in Thumb "
421 // We want to read exactly 4 bytes of data.
422 if (Region.readBytes(Address, 4, Bytes) == -1) {
424 return MCDisassembler::Fail;
427 // Encoded as a small-endian 32-bit word in the stream.
429 (Bytes[3] << 24) | (Bytes[2] << 16) | (Bytes[1] << 8) | (Bytes[0] << 0);
431 // Calling the auto-generated decoder function.
432 DecodeStatus Result =
433 decodeInstruction(DecoderTableARM32, MI, Insn, Address, this, STI);
434 if (Result != MCDisassembler::Fail) {
439 // VFP and NEON instructions, similarly, are shared between ARM
442 Result = decodeInstruction(DecoderTableVFP32, MI, Insn, Address, this, STI);
443 if (Result != MCDisassembler::Fail) {
449 Result = decodeInstruction(DecoderTableVFPV832, MI, Insn, Address, this, STI);
450 if (Result != MCDisassembler::Fail) {
457 decodeInstruction(DecoderTableNEONData32, MI, Insn, Address, this, STI);
458 if (Result != MCDisassembler::Fail) {
460 // Add a fake predicate operand, because we share these instruction
461 // definitions with Thumb2 where these instructions are predicable.
462 if (!DecodePredicateOperand(MI, 0xE, Address, this))
463 return MCDisassembler::Fail;
468 Result = decodeInstruction(DecoderTableNEONLoadStore32, MI, Insn, Address,
470 if (Result != MCDisassembler::Fail) {
472 // Add a fake predicate operand, because we share these instruction
473 // definitions with Thumb2 where these instructions are predicable.
474 if (!DecodePredicateOperand(MI, 0xE, Address, this))
475 return MCDisassembler::Fail;
481 decodeInstruction(DecoderTableNEONDup32, MI, Insn, Address, this, STI);
482 if (Result != MCDisassembler::Fail) {
484 // Add a fake predicate operand, because we share these instruction
485 // definitions with Thumb2 where these instructions are predicable.
486 if (!DecodePredicateOperand(MI, 0xE, Address, this))
487 return MCDisassembler::Fail;
493 decodeInstruction(DecoderTablev8NEON32, MI, Insn, Address, this, STI);
494 if (Result != MCDisassembler::Fail) {
501 decodeInstruction(DecoderTablev8Crypto32, MI, Insn, Address, this, STI);
502 if (Result != MCDisassembler::Fail) {
509 return MCDisassembler::Fail;
513 extern const MCInstrDesc ARMInsts[];
516 /// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the
517 /// immediate Value in the MCInst. The immediate Value has had any PC
518 /// adjustment made by the caller. If the instruction is a branch instruction
519 /// then isBranch is true, else false. If the getOpInfo() function was set as
520 /// part of the setupForSymbolicDisassembly() call then that function is called
521 /// to get any symbolic information at the Address for this instruction. If
522 /// that returns non-zero then the symbolic information it returns is used to
523 /// create an MCExpr and that is added as an operand to the MCInst. If
524 /// getOpInfo() returns zero and isBranch is true then a symbol look up for
525 /// Value is done and if a symbol is found an MCExpr is created with that, else
526 /// an MCExpr with Value is created. This function returns true if it adds an
527 /// operand to the MCInst and false otherwise.
528 static bool tryAddingSymbolicOperand(uint64_t Address, int32_t Value,
529 bool isBranch, uint64_t InstSize,
530 MCInst &MI, const void *Decoder) {
531 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
532 // FIXME: Does it make sense for value to be negative?
533 return Dis->tryAddingSymbolicOperand(MI, (uint32_t)Value, Address, isBranch,
534 /* Offset */ 0, InstSize);
537 /// tryAddingPcLoadReferenceComment - trys to add a comment as to what is being
538 /// referenced by a load instruction with the base register that is the Pc.
539 /// These can often be values in a literal pool near the Address of the
540 /// instruction. The Address of the instruction and its immediate Value are
541 /// used as a possible literal pool entry. The SymbolLookUp call back will
542 /// return the name of a symbol referenced by the literal pool's entry if
543 /// the referenced address is that of a symbol. Or it will return a pointer to
544 /// a literal 'C' string if the referenced address of the literal pool's entry
545 /// is an address into a section with 'C' string literals.
546 static void tryAddingPcLoadReferenceComment(uint64_t Address, int Value,
547 const void *Decoder) {
548 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
549 Dis->tryAddingPcLoadReferenceComment(Value, Address);
552 // Thumb1 instructions don't have explicit S bits. Rather, they
553 // implicitly set CPSR. Since it's not represented in the encoding, the
554 // auto-generated decoder won't inject the CPSR operand. We need to fix
555 // that as a post-pass.
556 static void AddThumb1SBit(MCInst &MI, bool InITBlock) {
557 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
558 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
559 MCInst::iterator I = MI.begin();
560 for (unsigned i = 0; i < NumOps; ++i, ++I) {
561 if (I == MI.end()) break;
562 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) {
563 if (i > 0 && OpInfo[i-1].isPredicate()) continue;
564 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR));
569 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR));
572 // Most Thumb instructions don't have explicit predicates in the
573 // encoding, but rather get their predicates from IT context. We need
574 // to fix up the predicate operands using this context information as a
576 MCDisassembler::DecodeStatus
577 ThumbDisassembler::AddThumbPredicate(MCInst &MI) const {
578 MCDisassembler::DecodeStatus S = Success;
580 // A few instructions actually have predicates encoded in them. Don't
581 // try to overwrite it if we're seeing one of those.
582 switch (MI.getOpcode()) {
593 // Some instructions (mostly conditional branches) are not
594 // allowed in IT blocks.
595 if (ITBlock.instrInITBlock())
604 // Some instructions (mostly unconditional branches) can
605 // only appears at the end of, or outside of, an IT.
606 if (ITBlock.instrInITBlock() && !ITBlock.instrLastInITBlock())
613 // If we're in an IT block, base the predicate on that. Otherwise,
614 // assume a predicate of AL.
616 CC = ITBlock.getITCC();
619 if (ITBlock.instrInITBlock())
620 ITBlock.advanceITState();
622 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
623 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
624 MCInst::iterator I = MI.begin();
625 for (unsigned i = 0; i < NumOps; ++i, ++I) {
626 if (I == MI.end()) break;
627 if (OpInfo[i].isPredicate()) {
628 I = MI.insert(I, MCOperand::CreateImm(CC));
631 MI.insert(I, MCOperand::CreateReg(0));
633 MI.insert(I, MCOperand::CreateReg(ARM::CPSR));
638 I = MI.insert(I, MCOperand::CreateImm(CC));
641 MI.insert(I, MCOperand::CreateReg(0));
643 MI.insert(I, MCOperand::CreateReg(ARM::CPSR));
648 // Thumb VFP instructions are a special case. Because we share their
649 // encodings between ARM and Thumb modes, and they are predicable in ARM
650 // mode, the auto-generated decoder will give them an (incorrect)
651 // predicate operand. We need to rewrite these operands based on the IT
652 // context as a post-pass.
653 void ThumbDisassembler::UpdateThumbVFPPredicate(MCInst &MI) const {
655 CC = ITBlock.getITCC();
656 if (ITBlock.instrInITBlock())
657 ITBlock.advanceITState();
659 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
660 MCInst::iterator I = MI.begin();
661 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
662 for (unsigned i = 0; i < NumOps; ++i, ++I) {
663 if (OpInfo[i].isPredicate() ) {
669 I->setReg(ARM::CPSR);
675 DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
676 const MemoryObject &Region,
679 raw_ostream &CS) const {
684 assert((STI.getFeatureBits() & ARM::ModeThumb) &&
685 "Asked to disassemble in Thumb mode but Subtarget is in ARM mode!");
687 // We want to read exactly 2 bytes of data.
688 if (Region.readBytes(Address, 2, Bytes) == -1) {
690 return MCDisassembler::Fail;
693 uint16_t Insn16 = (Bytes[1] << 8) | Bytes[0];
694 DecodeStatus Result =
695 decodeInstruction(DecoderTableThumb16, MI, Insn16, Address, this, STI);
696 if (Result != MCDisassembler::Fail) {
698 Check(Result, AddThumbPredicate(MI));
703 Result = decodeInstruction(DecoderTableThumbSBit16, MI, Insn16, Address, this,
707 bool InITBlock = ITBlock.instrInITBlock();
708 Check(Result, AddThumbPredicate(MI));
709 AddThumb1SBit(MI, InITBlock);
715 decodeInstruction(DecoderTableThumb216, MI, Insn16, Address, this, STI);
716 if (Result != MCDisassembler::Fail) {
719 // Nested IT blocks are UNPREDICTABLE. Must be checked before we add
720 // the Thumb predicate.
721 if (MI.getOpcode() == ARM::t2IT && ITBlock.instrInITBlock())
722 Result = MCDisassembler::SoftFail;
724 Check(Result, AddThumbPredicate(MI));
726 // If we find an IT instruction, we need to parse its condition
727 // code and mask operands so that we can apply them correctly
728 // to the subsequent instructions.
729 if (MI.getOpcode() == ARM::t2IT) {
731 unsigned Firstcond = MI.getOperand(0).getImm();
732 unsigned Mask = MI.getOperand(1).getImm();
733 ITBlock.setITState(Firstcond, Mask);
739 // We want to read exactly 4 bytes of data.
740 if (Region.readBytes(Address, 4, Bytes) == -1) {
742 return MCDisassembler::Fail;
746 (Bytes[3] << 8) | (Bytes[2] << 0) | (Bytes[1] << 24) | (Bytes[0] << 16);
749 decodeInstruction(DecoderTableThumb32, MI, Insn32, Address, this, STI);
750 if (Result != MCDisassembler::Fail) {
752 bool InITBlock = ITBlock.instrInITBlock();
753 Check(Result, AddThumbPredicate(MI));
754 AddThumb1SBit(MI, InITBlock);
760 decodeInstruction(DecoderTableThumb232, MI, Insn32, Address, this, STI);
761 if (Result != MCDisassembler::Fail) {
763 Check(Result, AddThumbPredicate(MI));
767 if (fieldFromInstruction(Insn32, 28, 4) == 0xE) {
770 decodeInstruction(DecoderTableVFP32, MI, Insn32, Address, this, STI);
771 if (Result != MCDisassembler::Fail) {
773 UpdateThumbVFPPredicate(MI);
780 decodeInstruction(DecoderTableVFPV832, MI, Insn32, Address, this, STI);
781 if (Result != MCDisassembler::Fail) {
786 if (fieldFromInstruction(Insn32, 28, 4) == 0xE) {
788 Result = decodeInstruction(DecoderTableNEONDup32, MI, Insn32, Address, this,
790 if (Result != MCDisassembler::Fail) {
792 Check(Result, AddThumbPredicate(MI));
797 if (fieldFromInstruction(Insn32, 24, 8) == 0xF9) {
799 uint32_t NEONLdStInsn = Insn32;
800 NEONLdStInsn &= 0xF0FFFFFF;
801 NEONLdStInsn |= 0x04000000;
802 Result = decodeInstruction(DecoderTableNEONLoadStore32, MI, NEONLdStInsn,
804 if (Result != MCDisassembler::Fail) {
806 Check(Result, AddThumbPredicate(MI));
811 if (fieldFromInstruction(Insn32, 24, 4) == 0xF) {
813 uint32_t NEONDataInsn = Insn32;
814 NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24
815 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24
816 NEONDataInsn |= 0x12000000; // Set bits 28 and 25
817 Result = decodeInstruction(DecoderTableNEONData32, MI, NEONDataInsn,
819 if (Result != MCDisassembler::Fail) {
821 Check(Result, AddThumbPredicate(MI));
826 uint32_t NEONCryptoInsn = Insn32;
827 NEONCryptoInsn &= 0xF0FFFFFF; // Clear bits 27-24
828 NEONCryptoInsn |= (NEONCryptoInsn & 0x10000000) >> 4; // Move bit 28 to bit 24
829 NEONCryptoInsn |= 0x12000000; // Set bits 28 and 25
830 Result = decodeInstruction(DecoderTablev8Crypto32, MI, NEONCryptoInsn,
832 if (Result != MCDisassembler::Fail) {
838 uint32_t NEONv8Insn = Insn32;
839 NEONv8Insn &= 0xF3FFFFFF; // Clear bits 27-26
840 Result = decodeInstruction(DecoderTablev8NEON32, MI, NEONv8Insn, Address,
842 if (Result != MCDisassembler::Fail) {
850 return MCDisassembler::Fail;
854 extern "C" void LLVMInitializeARMDisassembler() {
855 TargetRegistry::RegisterMCDisassembler(TheARMLETarget,
856 createARMDisassembler);
857 TargetRegistry::RegisterMCDisassembler(TheARMBETarget,
858 createARMDisassembler);
859 TargetRegistry::RegisterMCDisassembler(TheThumbLETarget,
860 createThumbDisassembler);
861 TargetRegistry::RegisterMCDisassembler(TheThumbBETarget,
862 createThumbDisassembler);
865 static const uint16_t GPRDecoderTable[] = {
866 ARM::R0, ARM::R1, ARM::R2, ARM::R3,
867 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
868 ARM::R8, ARM::R9, ARM::R10, ARM::R11,
869 ARM::R12, ARM::SP, ARM::LR, ARM::PC
872 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo,
873 uint64_t Address, const void *Decoder) {
875 return MCDisassembler::Fail;
877 unsigned Register = GPRDecoderTable[RegNo];
878 Inst.addOperand(MCOperand::CreateReg(Register));
879 return MCDisassembler::Success;
883 DecodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo,
884 uint64_t Address, const void *Decoder) {
885 DecodeStatus S = MCDisassembler::Success;
888 S = MCDisassembler::SoftFail;
890 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
896 DecodeGPRwithAPSRRegisterClass(MCInst &Inst, unsigned RegNo,
897 uint64_t Address, const void *Decoder) {
898 DecodeStatus S = MCDisassembler::Success;
902 Inst.addOperand(MCOperand::CreateReg(ARM::APSR_NZCV));
903 return MCDisassembler::Success;
906 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
910 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo,
911 uint64_t Address, const void *Decoder) {
913 return MCDisassembler::Fail;
914 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
917 static const uint16_t GPRPairDecoderTable[] = {
918 ARM::R0_R1, ARM::R2_R3, ARM::R4_R5, ARM::R6_R7,
919 ARM::R8_R9, ARM::R10_R11, ARM::R12_SP
922 static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo,
923 uint64_t Address, const void *Decoder) {
924 DecodeStatus S = MCDisassembler::Success;
927 return MCDisassembler::Fail;
929 if ((RegNo & 1) || RegNo == 0xe)
930 S = MCDisassembler::SoftFail;
932 unsigned RegisterPair = GPRPairDecoderTable[RegNo/2];
933 Inst.addOperand(MCOperand::CreateReg(RegisterPair));
937 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo,
938 uint64_t Address, const void *Decoder) {
939 unsigned Register = 0;
960 return MCDisassembler::Fail;
963 Inst.addOperand(MCOperand::CreateReg(Register));
964 return MCDisassembler::Success;
967 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo,
968 uint64_t Address, const void *Decoder) {
969 DecodeStatus S = MCDisassembler::Success;
970 if (RegNo == 13 || RegNo == 15)
971 S = MCDisassembler::SoftFail;
972 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
976 static const uint16_t SPRDecoderTable[] = {
977 ARM::S0, ARM::S1, ARM::S2, ARM::S3,
978 ARM::S4, ARM::S5, ARM::S6, ARM::S7,
979 ARM::S8, ARM::S9, ARM::S10, ARM::S11,
980 ARM::S12, ARM::S13, ARM::S14, ARM::S15,
981 ARM::S16, ARM::S17, ARM::S18, ARM::S19,
982 ARM::S20, ARM::S21, ARM::S22, ARM::S23,
983 ARM::S24, ARM::S25, ARM::S26, ARM::S27,
984 ARM::S28, ARM::S29, ARM::S30, ARM::S31
987 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo,
988 uint64_t Address, const void *Decoder) {
990 return MCDisassembler::Fail;
992 unsigned Register = SPRDecoderTable[RegNo];
993 Inst.addOperand(MCOperand::CreateReg(Register));
994 return MCDisassembler::Success;
997 static const uint16_t DPRDecoderTable[] = {
998 ARM::D0, ARM::D1, ARM::D2, ARM::D3,
999 ARM::D4, ARM::D5, ARM::D6, ARM::D7,
1000 ARM::D8, ARM::D9, ARM::D10, ARM::D11,
1001 ARM::D12, ARM::D13, ARM::D14, ARM::D15,
1002 ARM::D16, ARM::D17, ARM::D18, ARM::D19,
1003 ARM::D20, ARM::D21, ARM::D22, ARM::D23,
1004 ARM::D24, ARM::D25, ARM::D26, ARM::D27,
1005 ARM::D28, ARM::D29, ARM::D30, ARM::D31
1008 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo,
1009 uint64_t Address, const void *Decoder) {
1010 uint64_t featureBits = ((const MCDisassembler*)Decoder)->getSubtargetInfo()
1012 bool hasD16 = featureBits & ARM::FeatureD16;
1014 if (RegNo > 31 || (hasD16 && RegNo > 15))
1015 return MCDisassembler::Fail;
1017 unsigned Register = DPRDecoderTable[RegNo];
1018 Inst.addOperand(MCOperand::CreateReg(Register));
1019 return MCDisassembler::Success;
1022 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo,
1023 uint64_t Address, const void *Decoder) {
1025 return MCDisassembler::Fail;
1026 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
1030 DecodeDPR_VFP2RegisterClass(MCInst &Inst, unsigned RegNo,
1031 uint64_t Address, const void *Decoder) {
1033 return MCDisassembler::Fail;
1034 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
1037 static const uint16_t QPRDecoderTable[] = {
1038 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3,
1039 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7,
1040 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11,
1041 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15
1045 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo,
1046 uint64_t Address, const void *Decoder) {
1047 if (RegNo > 31 || (RegNo & 1) != 0)
1048 return MCDisassembler::Fail;
1051 unsigned Register = QPRDecoderTable[RegNo];
1052 Inst.addOperand(MCOperand::CreateReg(Register));
1053 return MCDisassembler::Success;
1056 static const uint16_t DPairDecoderTable[] = {
1057 ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6,
1058 ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12,
1059 ARM::Q6, ARM::D13_D14, ARM::Q7, ARM::D15_D16, ARM::Q8, ARM::D17_D18,
1060 ARM::Q9, ARM::D19_D20, ARM::Q10, ARM::D21_D22, ARM::Q11, ARM::D23_D24,
1061 ARM::Q12, ARM::D25_D26, ARM::Q13, ARM::D27_D28, ARM::Q14, ARM::D29_D30,
1065 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo,
1066 uint64_t Address, const void *Decoder) {
1068 return MCDisassembler::Fail;
1070 unsigned Register = DPairDecoderTable[RegNo];
1071 Inst.addOperand(MCOperand::CreateReg(Register));
1072 return MCDisassembler::Success;
1075 static const uint16_t DPairSpacedDecoderTable[] = {
1076 ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5,
1077 ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9,
1078 ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13,
1079 ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17,
1080 ARM::D16_D18, ARM::D17_D19, ARM::D18_D20, ARM::D19_D21,
1081 ARM::D20_D22, ARM::D21_D23, ARM::D22_D24, ARM::D23_D25,
1082 ARM::D24_D26, ARM::D25_D27, ARM::D26_D28, ARM::D27_D29,
1083 ARM::D28_D30, ARM::D29_D31
1086 static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst,
1089 const void *Decoder) {
1091 return MCDisassembler::Fail;
1093 unsigned Register = DPairSpacedDecoderTable[RegNo];
1094 Inst.addOperand(MCOperand::CreateReg(Register));
1095 return MCDisassembler::Success;
1098 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val,
1099 uint64_t Address, const void *Decoder) {
1100 if (Val == 0xF) return MCDisassembler::Fail;
1101 // AL predicate is not allowed on Thumb1 branches.
1102 if (Inst.getOpcode() == ARM::tBcc && Val == 0xE)
1103 return MCDisassembler::Fail;
1104 Inst.addOperand(MCOperand::CreateImm(Val));
1105 if (Val == ARMCC::AL) {
1106 Inst.addOperand(MCOperand::CreateReg(0));
1108 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1109 return MCDisassembler::Success;
1112 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val,
1113 uint64_t Address, const void *Decoder) {
1115 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1117 Inst.addOperand(MCOperand::CreateReg(0));
1118 return MCDisassembler::Success;
1121 static DecodeStatus DecodeSOImmOperand(MCInst &Inst, unsigned Val,
1122 uint64_t Address, const void *Decoder) {
1123 uint32_t imm = Val & 0xFF;
1124 uint32_t rot = (Val & 0xF00) >> 7;
1125 uint32_t rot_imm = (imm >> rot) | (imm << ((32-rot) & 0x1F));
1126 Inst.addOperand(MCOperand::CreateImm(rot_imm));
1127 return MCDisassembler::Success;
1130 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Val,
1131 uint64_t Address, const void *Decoder) {
1132 DecodeStatus S = MCDisassembler::Success;
1134 unsigned Rm = fieldFromInstruction(Val, 0, 4);
1135 unsigned type = fieldFromInstruction(Val, 5, 2);
1136 unsigned imm = fieldFromInstruction(Val, 7, 5);
1138 // Register-immediate
1139 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1140 return MCDisassembler::Fail;
1142 ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
1145 Shift = ARM_AM::lsl;
1148 Shift = ARM_AM::lsr;
1151 Shift = ARM_AM::asr;
1154 Shift = ARM_AM::ror;
1158 if (Shift == ARM_AM::ror && imm == 0)
1159 Shift = ARM_AM::rrx;
1161 unsigned Op = Shift | (imm << 3);
1162 Inst.addOperand(MCOperand::CreateImm(Op));
1167 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Val,
1168 uint64_t Address, const void *Decoder) {
1169 DecodeStatus S = MCDisassembler::Success;
1171 unsigned Rm = fieldFromInstruction(Val, 0, 4);
1172 unsigned type = fieldFromInstruction(Val, 5, 2);
1173 unsigned Rs = fieldFromInstruction(Val, 8, 4);
1175 // Register-register
1176 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1177 return MCDisassembler::Fail;
1178 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder)))
1179 return MCDisassembler::Fail;
1181 ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
1184 Shift = ARM_AM::lsl;
1187 Shift = ARM_AM::lsr;
1190 Shift = ARM_AM::asr;
1193 Shift = ARM_AM::ror;
1197 Inst.addOperand(MCOperand::CreateImm(Shift));
1202 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val,
1203 uint64_t Address, const void *Decoder) {
1204 DecodeStatus S = MCDisassembler::Success;
1206 bool NeedDisjointWriteback = false;
1207 unsigned WritebackReg = 0;
1208 switch (Inst.getOpcode()) {
1211 case ARM::LDMIA_UPD:
1212 case ARM::LDMDB_UPD:
1213 case ARM::LDMIB_UPD:
1214 case ARM::LDMDA_UPD:
1215 case ARM::t2LDMIA_UPD:
1216 case ARM::t2LDMDB_UPD:
1217 case ARM::t2STMIA_UPD:
1218 case ARM::t2STMDB_UPD:
1219 NeedDisjointWriteback = true;
1220 WritebackReg = Inst.getOperand(0).getReg();
1224 // Empty register lists are not allowed.
1225 if (Val == 0) return MCDisassembler::Fail;
1226 for (unsigned i = 0; i < 16; ++i) {
1227 if (Val & (1 << i)) {
1228 if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder)))
1229 return MCDisassembler::Fail;
1230 // Writeback not allowed if Rn is in the target list.
1231 if (NeedDisjointWriteback && WritebackReg == Inst.end()[-1].getReg())
1232 Check(S, MCDisassembler::SoftFail);
1239 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val,
1240 uint64_t Address, const void *Decoder) {
1241 DecodeStatus S = MCDisassembler::Success;
1243 unsigned Vd = fieldFromInstruction(Val, 8, 5);
1244 unsigned regs = fieldFromInstruction(Val, 0, 8);
1246 // In case of unpredictable encoding, tweak the operands.
1247 if (regs == 0 || (Vd + regs) > 32) {
1248 regs = Vd + regs > 32 ? 32 - Vd : regs;
1249 regs = std::max( 1u, regs);
1250 S = MCDisassembler::SoftFail;
1253 if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder)))
1254 return MCDisassembler::Fail;
1255 for (unsigned i = 0; i < (regs - 1); ++i) {
1256 if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder)))
1257 return MCDisassembler::Fail;
1263 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val,
1264 uint64_t Address, const void *Decoder) {
1265 DecodeStatus S = MCDisassembler::Success;
1267 unsigned Vd = fieldFromInstruction(Val, 8, 5);
1268 unsigned regs = fieldFromInstruction(Val, 1, 7);
1270 // In case of unpredictable encoding, tweak the operands.
1271 if (regs == 0 || regs > 16 || (Vd + regs) > 32) {
1272 regs = Vd + regs > 32 ? 32 - Vd : regs;
1273 regs = std::max( 1u, regs);
1274 regs = std::min(16u, regs);
1275 S = MCDisassembler::SoftFail;
1278 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
1279 return MCDisassembler::Fail;
1280 for (unsigned i = 0; i < (regs - 1); ++i) {
1281 if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder)))
1282 return MCDisassembler::Fail;
1288 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Val,
1289 uint64_t Address, const void *Decoder) {
1290 // This operand encodes a mask of contiguous zeros between a specified MSB
1291 // and LSB. To decode it, we create the mask of all bits MSB-and-lower,
1292 // the mask of all bits LSB-and-lower, and then xor them to create
1293 // the mask of that's all ones on [msb, lsb]. Finally we not it to
1294 // create the final mask.
1295 unsigned msb = fieldFromInstruction(Val, 5, 5);
1296 unsigned lsb = fieldFromInstruction(Val, 0, 5);
1298 DecodeStatus S = MCDisassembler::Success;
1300 Check(S, MCDisassembler::SoftFail);
1301 // The check above will cause the warning for the "potentially undefined
1302 // instruction encoding" but we can't build a bad MCOperand value here
1303 // with a lsb > msb or else printing the MCInst will cause a crash.
1307 uint32_t msb_mask = 0xFFFFFFFF;
1308 if (msb != 31) msb_mask = (1U << (msb+1)) - 1;
1309 uint32_t lsb_mask = (1U << lsb) - 1;
1311 Inst.addOperand(MCOperand::CreateImm(~(msb_mask ^ lsb_mask)));
1315 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn,
1316 uint64_t Address, const void *Decoder) {
1317 DecodeStatus S = MCDisassembler::Success;
1319 unsigned pred = fieldFromInstruction(Insn, 28, 4);
1320 unsigned CRd = fieldFromInstruction(Insn, 12, 4);
1321 unsigned coproc = fieldFromInstruction(Insn, 8, 4);
1322 unsigned imm = fieldFromInstruction(Insn, 0, 8);
1323 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1324 unsigned U = fieldFromInstruction(Insn, 23, 1);
1326 switch (Inst.getOpcode()) {
1327 case ARM::LDC_OFFSET:
1330 case ARM::LDC_OPTION:
1331 case ARM::LDCL_OFFSET:
1333 case ARM::LDCL_POST:
1334 case ARM::LDCL_OPTION:
1335 case ARM::STC_OFFSET:
1338 case ARM::STC_OPTION:
1339 case ARM::STCL_OFFSET:
1341 case ARM::STCL_POST:
1342 case ARM::STCL_OPTION:
1343 case ARM::t2LDC_OFFSET:
1344 case ARM::t2LDC_PRE:
1345 case ARM::t2LDC_POST:
1346 case ARM::t2LDC_OPTION:
1347 case ARM::t2LDCL_OFFSET:
1348 case ARM::t2LDCL_PRE:
1349 case ARM::t2LDCL_POST:
1350 case ARM::t2LDCL_OPTION:
1351 case ARM::t2STC_OFFSET:
1352 case ARM::t2STC_PRE:
1353 case ARM::t2STC_POST:
1354 case ARM::t2STC_OPTION:
1355 case ARM::t2STCL_OFFSET:
1356 case ARM::t2STCL_PRE:
1357 case ARM::t2STCL_POST:
1358 case ARM::t2STCL_OPTION:
1359 if (coproc == 0xA || coproc == 0xB)
1360 return MCDisassembler::Fail;
1366 uint64_t featureBits = ((const MCDisassembler*)Decoder)->getSubtargetInfo()
1368 if ((featureBits & ARM::HasV8Ops) && (coproc != 14))
1369 return MCDisassembler::Fail;
1371 Inst.addOperand(MCOperand::CreateImm(coproc));
1372 Inst.addOperand(MCOperand::CreateImm(CRd));
1373 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1374 return MCDisassembler::Fail;
1376 switch (Inst.getOpcode()) {
1377 case ARM::t2LDC2_OFFSET:
1378 case ARM::t2LDC2L_OFFSET:
1379 case ARM::t2LDC2_PRE:
1380 case ARM::t2LDC2L_PRE:
1381 case ARM::t2STC2_OFFSET:
1382 case ARM::t2STC2L_OFFSET:
1383 case ARM::t2STC2_PRE:
1384 case ARM::t2STC2L_PRE:
1385 case ARM::LDC2_OFFSET:
1386 case ARM::LDC2L_OFFSET:
1388 case ARM::LDC2L_PRE:
1389 case ARM::STC2_OFFSET:
1390 case ARM::STC2L_OFFSET:
1392 case ARM::STC2L_PRE:
1393 case ARM::t2LDC_OFFSET:
1394 case ARM::t2LDCL_OFFSET:
1395 case ARM::t2LDC_PRE:
1396 case ARM::t2LDCL_PRE:
1397 case ARM::t2STC_OFFSET:
1398 case ARM::t2STCL_OFFSET:
1399 case ARM::t2STC_PRE:
1400 case ARM::t2STCL_PRE:
1401 case ARM::LDC_OFFSET:
1402 case ARM::LDCL_OFFSET:
1405 case ARM::STC_OFFSET:
1406 case ARM::STCL_OFFSET:
1409 imm = ARM_AM::getAM5Opc(U ? ARM_AM::add : ARM_AM::sub, imm);
1410 Inst.addOperand(MCOperand::CreateImm(imm));
1412 case ARM::t2LDC2_POST:
1413 case ARM::t2LDC2L_POST:
1414 case ARM::t2STC2_POST:
1415 case ARM::t2STC2L_POST:
1416 case ARM::LDC2_POST:
1417 case ARM::LDC2L_POST:
1418 case ARM::STC2_POST:
1419 case ARM::STC2L_POST:
1420 case ARM::t2LDC_POST:
1421 case ARM::t2LDCL_POST:
1422 case ARM::t2STC_POST:
1423 case ARM::t2STCL_POST:
1425 case ARM::LDCL_POST:
1427 case ARM::STCL_POST:
1431 // The 'option' variant doesn't encode 'U' in the immediate since
1432 // the immediate is unsigned [0,255].
1433 Inst.addOperand(MCOperand::CreateImm(imm));
1437 switch (Inst.getOpcode()) {
1438 case ARM::LDC_OFFSET:
1441 case ARM::LDC_OPTION:
1442 case ARM::LDCL_OFFSET:
1444 case ARM::LDCL_POST:
1445 case ARM::LDCL_OPTION:
1446 case ARM::STC_OFFSET:
1449 case ARM::STC_OPTION:
1450 case ARM::STCL_OFFSET:
1452 case ARM::STCL_POST:
1453 case ARM::STCL_OPTION:
1454 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1455 return MCDisassembler::Fail;
1465 DecodeAddrMode2IdxInstruction(MCInst &Inst, unsigned Insn,
1466 uint64_t Address, const void *Decoder) {
1467 DecodeStatus S = MCDisassembler::Success;
1469 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1470 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
1471 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
1472 unsigned imm = fieldFromInstruction(Insn, 0, 12);
1473 unsigned pred = fieldFromInstruction(Insn, 28, 4);
1474 unsigned reg = fieldFromInstruction(Insn, 25, 1);
1475 unsigned P = fieldFromInstruction(Insn, 24, 1);
1476 unsigned W = fieldFromInstruction(Insn, 21, 1);
1478 // On stores, the writeback operand precedes Rt.
1479 switch (Inst.getOpcode()) {
1480 case ARM::STR_POST_IMM:
1481 case ARM::STR_POST_REG:
1482 case ARM::STRB_POST_IMM:
1483 case ARM::STRB_POST_REG:
1484 case ARM::STRT_POST_REG:
1485 case ARM::STRT_POST_IMM:
1486 case ARM::STRBT_POST_REG:
1487 case ARM::STRBT_POST_IMM:
1488 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1489 return MCDisassembler::Fail;
1495 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
1496 return MCDisassembler::Fail;
1498 // On loads, the writeback operand comes after Rt.
1499 switch (Inst.getOpcode()) {
1500 case ARM::LDR_POST_IMM:
1501 case ARM::LDR_POST_REG:
1502 case ARM::LDRB_POST_IMM:
1503 case ARM::LDRB_POST_REG:
1504 case ARM::LDRBT_POST_REG:
1505 case ARM::LDRBT_POST_IMM:
1506 case ARM::LDRT_POST_REG:
1507 case ARM::LDRT_POST_IMM:
1508 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1509 return MCDisassembler::Fail;
1515 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1516 return MCDisassembler::Fail;
1518 ARM_AM::AddrOpc Op = ARM_AM::add;
1519 if (!fieldFromInstruction(Insn, 23, 1))
1522 bool writeback = (P == 0) || (W == 1);
1523 unsigned idx_mode = 0;
1525 idx_mode = ARMII::IndexModePre;
1526 else if (!P && writeback)
1527 idx_mode = ARMII::IndexModePost;
1529 if (writeback && (Rn == 15 || Rn == Rt))
1530 S = MCDisassembler::SoftFail; // UNPREDICTABLE
1533 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1534 return MCDisassembler::Fail;
1535 ARM_AM::ShiftOpc Opc = ARM_AM::lsl;
1536 switch( fieldFromInstruction(Insn, 5, 2)) {
1550 return MCDisassembler::Fail;
1552 unsigned amt = fieldFromInstruction(Insn, 7, 5);
1553 if (Opc == ARM_AM::ror && amt == 0)
1555 unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode);
1557 Inst.addOperand(MCOperand::CreateImm(imm));
1559 Inst.addOperand(MCOperand::CreateReg(0));
1560 unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode);
1561 Inst.addOperand(MCOperand::CreateImm(tmp));
1564 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1565 return MCDisassembler::Fail;
1570 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Val,
1571 uint64_t Address, const void *Decoder) {
1572 DecodeStatus S = MCDisassembler::Success;
1574 unsigned Rn = fieldFromInstruction(Val, 13, 4);
1575 unsigned Rm = fieldFromInstruction(Val, 0, 4);
1576 unsigned type = fieldFromInstruction(Val, 5, 2);
1577 unsigned imm = fieldFromInstruction(Val, 7, 5);
1578 unsigned U = fieldFromInstruction(Val, 12, 1);
1580 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl;
1596 if (ShOp == ARM_AM::ror && imm == 0)
1599 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1600 return MCDisassembler::Fail;
1601 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1602 return MCDisassembler::Fail;
1605 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp);
1607 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp);
1608 Inst.addOperand(MCOperand::CreateImm(shift));
1614 DecodeAddrMode3Instruction(MCInst &Inst, unsigned Insn,
1615 uint64_t Address, const void *Decoder) {
1616 DecodeStatus S = MCDisassembler::Success;
1618 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
1619 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1620 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
1621 unsigned type = fieldFromInstruction(Insn, 22, 1);
1622 unsigned imm = fieldFromInstruction(Insn, 8, 4);
1623 unsigned U = ((~fieldFromInstruction(Insn, 23, 1)) & 1) << 8;
1624 unsigned pred = fieldFromInstruction(Insn, 28, 4);
1625 unsigned W = fieldFromInstruction(Insn, 21, 1);
1626 unsigned P = fieldFromInstruction(Insn, 24, 1);
1627 unsigned Rt2 = Rt + 1;
1629 bool writeback = (W == 1) | (P == 0);
1631 // For {LD,ST}RD, Rt must be even, else undefined.
1632 switch (Inst.getOpcode()) {
1635 case ARM::STRD_POST:
1638 case ARM::LDRD_POST:
1639 if (Rt & 0x1) S = MCDisassembler::SoftFail;
1644 switch (Inst.getOpcode()) {
1647 case ARM::STRD_POST:
1648 if (P == 0 && W == 1)
1649 S = MCDisassembler::SoftFail;
1651 if (writeback && (Rn == 15 || Rn == Rt || Rn == Rt2))
1652 S = MCDisassembler::SoftFail;
1653 if (type && Rm == 15)
1654 S = MCDisassembler::SoftFail;
1656 S = MCDisassembler::SoftFail;
1657 if (!type && fieldFromInstruction(Insn, 8, 4))
1658 S = MCDisassembler::SoftFail;
1662 case ARM::STRH_POST:
1664 S = MCDisassembler::SoftFail;
1665 if (writeback && (Rn == 15 || Rn == Rt))
1666 S = MCDisassembler::SoftFail;
1667 if (!type && Rm == 15)
1668 S = MCDisassembler::SoftFail;
1672 case ARM::LDRD_POST:
1673 if (type && Rn == 15){
1675 S = MCDisassembler::SoftFail;
1678 if (P == 0 && W == 1)
1679 S = MCDisassembler::SoftFail;
1680 if (!type && (Rt2 == 15 || Rm == 15 || Rm == Rt || Rm == Rt2))
1681 S = MCDisassembler::SoftFail;
1682 if (!type && writeback && Rn == 15)
1683 S = MCDisassembler::SoftFail;
1684 if (writeback && (Rn == Rt || Rn == Rt2))
1685 S = MCDisassembler::SoftFail;
1689 case ARM::LDRH_POST:
1690 if (type && Rn == 15){
1692 S = MCDisassembler::SoftFail;
1696 S = MCDisassembler::SoftFail;
1697 if (!type && Rm == 15)
1698 S = MCDisassembler::SoftFail;
1699 if (!type && writeback && (Rn == 15 || Rn == Rt))
1700 S = MCDisassembler::SoftFail;
1703 case ARM::LDRSH_PRE:
1704 case ARM::LDRSH_POST:
1706 case ARM::LDRSB_PRE:
1707 case ARM::LDRSB_POST:
1708 if (type && Rn == 15){
1710 S = MCDisassembler::SoftFail;
1713 if (type && (Rt == 15 || (writeback && Rn == Rt)))
1714 S = MCDisassembler::SoftFail;
1715 if (!type && (Rt == 15 || Rm == 15))
1716 S = MCDisassembler::SoftFail;
1717 if (!type && writeback && (Rn == 15 || Rn == Rt))
1718 S = MCDisassembler::SoftFail;
1724 if (writeback) { // Writeback
1726 U |= ARMII::IndexModePre << 9;
1728 U |= ARMII::IndexModePost << 9;
1730 // On stores, the writeback operand precedes Rt.
1731 switch (Inst.getOpcode()) {
1734 case ARM::STRD_POST:
1737 case ARM::STRH_POST:
1738 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1739 return MCDisassembler::Fail;
1746 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
1747 return MCDisassembler::Fail;
1748 switch (Inst.getOpcode()) {
1751 case ARM::STRD_POST:
1754 case ARM::LDRD_POST:
1755 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
1756 return MCDisassembler::Fail;
1763 // On loads, the writeback operand comes after Rt.
1764 switch (Inst.getOpcode()) {
1767 case ARM::LDRD_POST:
1770 case ARM::LDRH_POST:
1772 case ARM::LDRSH_PRE:
1773 case ARM::LDRSH_POST:
1775 case ARM::LDRSB_PRE:
1776 case ARM::LDRSB_POST:
1779 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1780 return MCDisassembler::Fail;
1787 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1788 return MCDisassembler::Fail;
1791 Inst.addOperand(MCOperand::CreateReg(0));
1792 Inst.addOperand(MCOperand::CreateImm(U | (imm << 4) | Rm));
1794 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1795 return MCDisassembler::Fail;
1796 Inst.addOperand(MCOperand::CreateImm(U));
1799 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1800 return MCDisassembler::Fail;
1805 static DecodeStatus DecodeRFEInstruction(MCInst &Inst, unsigned Insn,
1806 uint64_t Address, const void *Decoder) {
1807 DecodeStatus S = MCDisassembler::Success;
1809 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1810 unsigned mode = fieldFromInstruction(Insn, 23, 2);
1827 Inst.addOperand(MCOperand::CreateImm(mode));
1828 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1829 return MCDisassembler::Fail;
1834 static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn,
1835 uint64_t Address, const void *Decoder) {
1836 DecodeStatus S = MCDisassembler::Success;
1838 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
1839 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
1840 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1841 unsigned pred = fieldFromInstruction(Insn, 28, 4);
1844 return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
1846 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
1847 return MCDisassembler::Fail;
1848 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1849 return MCDisassembler::Fail;
1850 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
1851 return MCDisassembler::Fail;
1852 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1853 return MCDisassembler::Fail;
1857 static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst &Inst,
1859 uint64_t Address, const void *Decoder) {
1860 DecodeStatus S = MCDisassembler::Success;
1862 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1863 unsigned pred = fieldFromInstruction(Insn, 28, 4);
1864 unsigned reglist = fieldFromInstruction(Insn, 0, 16);
1867 // Ambiguous with RFE and SRS
1868 switch (Inst.getOpcode()) {
1870 Inst.setOpcode(ARM::RFEDA);
1872 case ARM::LDMDA_UPD:
1873 Inst.setOpcode(ARM::RFEDA_UPD);
1876 Inst.setOpcode(ARM::RFEDB);
1878 case ARM::LDMDB_UPD:
1879 Inst.setOpcode(ARM::RFEDB_UPD);
1882 Inst.setOpcode(ARM::RFEIA);
1884 case ARM::LDMIA_UPD:
1885 Inst.setOpcode(ARM::RFEIA_UPD);
1888 Inst.setOpcode(ARM::RFEIB);
1890 case ARM::LDMIB_UPD:
1891 Inst.setOpcode(ARM::RFEIB_UPD);
1894 Inst.setOpcode(ARM::SRSDA);
1896 case ARM::STMDA_UPD:
1897 Inst.setOpcode(ARM::SRSDA_UPD);
1900 Inst.setOpcode(ARM::SRSDB);
1902 case ARM::STMDB_UPD:
1903 Inst.setOpcode(ARM::SRSDB_UPD);
1906 Inst.setOpcode(ARM::SRSIA);
1908 case ARM::STMIA_UPD:
1909 Inst.setOpcode(ARM::SRSIA_UPD);
1912 Inst.setOpcode(ARM::SRSIB);
1914 case ARM::STMIB_UPD:
1915 Inst.setOpcode(ARM::SRSIB_UPD);
1918 return MCDisassembler::Fail;
1921 // For stores (which become SRS's, the only operand is the mode.
1922 if (fieldFromInstruction(Insn, 20, 1) == 0) {
1923 // Check SRS encoding constraints
1924 if (!(fieldFromInstruction(Insn, 22, 1) == 1 &&
1925 fieldFromInstruction(Insn, 20, 1) == 0))
1926 return MCDisassembler::Fail;
1929 MCOperand::CreateImm(fieldFromInstruction(Insn, 0, 4)));
1933 return DecodeRFEInstruction(Inst, Insn, Address, Decoder);
1936 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1937 return MCDisassembler::Fail;
1938 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1939 return MCDisassembler::Fail; // Tied
1940 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1941 return MCDisassembler::Fail;
1942 if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder)))
1943 return MCDisassembler::Fail;
1948 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn,
1949 uint64_t Address, const void *Decoder) {
1950 unsigned imod = fieldFromInstruction(Insn, 18, 2);
1951 unsigned M = fieldFromInstruction(Insn, 17, 1);
1952 unsigned iflags = fieldFromInstruction(Insn, 6, 3);
1953 unsigned mode = fieldFromInstruction(Insn, 0, 5);
1955 DecodeStatus S = MCDisassembler::Success;
1957 // This decoder is called from multiple location that do not check
1958 // the full encoding is valid before they do.
1959 if (fieldFromInstruction(Insn, 5, 1) != 0 ||
1960 fieldFromInstruction(Insn, 16, 1) != 0 ||
1961 fieldFromInstruction(Insn, 20, 8) != 0x10)
1962 return MCDisassembler::Fail;
1964 // imod == '01' --> UNPREDICTABLE
1965 // NOTE: Even though this is technically UNPREDICTABLE, we choose to
1966 // return failure here. The '01' imod value is unprintable, so there's
1967 // nothing useful we could do even if we returned UNPREDICTABLE.
1969 if (imod == 1) return MCDisassembler::Fail;
1972 Inst.setOpcode(ARM::CPS3p);
1973 Inst.addOperand(MCOperand::CreateImm(imod));
1974 Inst.addOperand(MCOperand::CreateImm(iflags));
1975 Inst.addOperand(MCOperand::CreateImm(mode));
1976 } else if (imod && !M) {
1977 Inst.setOpcode(ARM::CPS2p);
1978 Inst.addOperand(MCOperand::CreateImm(imod));
1979 Inst.addOperand(MCOperand::CreateImm(iflags));
1980 if (mode) S = MCDisassembler::SoftFail;
1981 } else if (!imod && M) {
1982 Inst.setOpcode(ARM::CPS1p);
1983 Inst.addOperand(MCOperand::CreateImm(mode));
1984 if (iflags) S = MCDisassembler::SoftFail;
1986 // imod == '00' && M == '0' --> UNPREDICTABLE
1987 Inst.setOpcode(ARM::CPS1p);
1988 Inst.addOperand(MCOperand::CreateImm(mode));
1989 S = MCDisassembler::SoftFail;
1995 static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn,
1996 uint64_t Address, const void *Decoder) {
1997 unsigned imod = fieldFromInstruction(Insn, 9, 2);
1998 unsigned M = fieldFromInstruction(Insn, 8, 1);
1999 unsigned iflags = fieldFromInstruction(Insn, 5, 3);
2000 unsigned mode = fieldFromInstruction(Insn, 0, 5);
2002 DecodeStatus S = MCDisassembler::Success;
2004 // imod == '01' --> UNPREDICTABLE
2005 // NOTE: Even though this is technically UNPREDICTABLE, we choose to
2006 // return failure here. The '01' imod value is unprintable, so there's
2007 // nothing useful we could do even if we returned UNPREDICTABLE.
2009 if (imod == 1) return MCDisassembler::Fail;
2012 Inst.setOpcode(ARM::t2CPS3p);
2013 Inst.addOperand(MCOperand::CreateImm(imod));
2014 Inst.addOperand(MCOperand::CreateImm(iflags));
2015 Inst.addOperand(MCOperand::CreateImm(mode));
2016 } else if (imod && !M) {
2017 Inst.setOpcode(ARM::t2CPS2p);
2018 Inst.addOperand(MCOperand::CreateImm(imod));
2019 Inst.addOperand(MCOperand::CreateImm(iflags));
2020 if (mode) S = MCDisassembler::SoftFail;
2021 } else if (!imod && M) {
2022 Inst.setOpcode(ARM::t2CPS1p);
2023 Inst.addOperand(MCOperand::CreateImm(mode));
2024 if (iflags) S = MCDisassembler::SoftFail;
2026 // imod == '00' && M == '0' --> this is a HINT instruction
2027 int imm = fieldFromInstruction(Insn, 0, 8);
2028 // HINT are defined only for immediate in [0..4]
2029 if(imm > 4) return MCDisassembler::Fail;
2030 Inst.setOpcode(ARM::t2HINT);
2031 Inst.addOperand(MCOperand::CreateImm(imm));
2037 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn,
2038 uint64_t Address, const void *Decoder) {
2039 DecodeStatus S = MCDisassembler::Success;
2041 unsigned Rd = fieldFromInstruction(Insn, 8, 4);
2044 imm |= (fieldFromInstruction(Insn, 0, 8) << 0);
2045 imm |= (fieldFromInstruction(Insn, 12, 3) << 8);
2046 imm |= (fieldFromInstruction(Insn, 16, 4) << 12);
2047 imm |= (fieldFromInstruction(Insn, 26, 1) << 11);
2049 if (Inst.getOpcode() == ARM::t2MOVTi16)
2050 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
2051 return MCDisassembler::Fail;
2052 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
2053 return MCDisassembler::Fail;
2055 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder))
2056 Inst.addOperand(MCOperand::CreateImm(imm));
2061 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn,
2062 uint64_t Address, const void *Decoder) {
2063 DecodeStatus S = MCDisassembler::Success;
2065 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2066 unsigned pred = fieldFromInstruction(Insn, 28, 4);
2069 imm |= (fieldFromInstruction(Insn, 0, 12) << 0);
2070 imm |= (fieldFromInstruction(Insn, 16, 4) << 12);
2072 if (Inst.getOpcode() == ARM::MOVTi16)
2073 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
2074 return MCDisassembler::Fail;
2076 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
2077 return MCDisassembler::Fail;
2079 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder))
2080 Inst.addOperand(MCOperand::CreateImm(imm));
2082 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2083 return MCDisassembler::Fail;
2088 static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn,
2089 uint64_t Address, const void *Decoder) {
2090 DecodeStatus S = MCDisassembler::Success;
2092 unsigned Rd = fieldFromInstruction(Insn, 16, 4);
2093 unsigned Rn = fieldFromInstruction(Insn, 0, 4);
2094 unsigned Rm = fieldFromInstruction(Insn, 8, 4);
2095 unsigned Ra = fieldFromInstruction(Insn, 12, 4);
2096 unsigned pred = fieldFromInstruction(Insn, 28, 4);
2099 return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
2101 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
2102 return MCDisassembler::Fail;
2103 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
2104 return MCDisassembler::Fail;
2105 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
2106 return MCDisassembler::Fail;
2107 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder)))
2108 return MCDisassembler::Fail;
2110 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2111 return MCDisassembler::Fail;
2116 static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val,
2117 uint64_t Address, const void *Decoder) {
2118 DecodeStatus S = MCDisassembler::Success;
2120 unsigned add = fieldFromInstruction(Val, 12, 1);
2121 unsigned imm = fieldFromInstruction(Val, 0, 12);
2122 unsigned Rn = fieldFromInstruction(Val, 13, 4);
2124 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2125 return MCDisassembler::Fail;
2127 if (!add) imm *= -1;
2128 if (imm == 0 && !add) imm = INT32_MIN;
2129 Inst.addOperand(MCOperand::CreateImm(imm));
2131 tryAddingPcLoadReferenceComment(Address, Address + imm + 8, Decoder);
2136 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val,
2137 uint64_t Address, const void *Decoder) {
2138 DecodeStatus S = MCDisassembler::Success;
2140 unsigned Rn = fieldFromInstruction(Val, 9, 4);
2141 unsigned U = fieldFromInstruction(Val, 8, 1);
2142 unsigned imm = fieldFromInstruction(Val, 0, 8);
2144 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2145 return MCDisassembler::Fail;
2148 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::add, imm)));
2150 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm)));
2155 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val,
2156 uint64_t Address, const void *Decoder) {
2157 return DecodeGPRRegisterClass(Inst, Val, Address, Decoder);
2161 DecodeT2BInstruction(MCInst &Inst, unsigned Insn,
2162 uint64_t Address, const void *Decoder) {
2163 DecodeStatus Status = MCDisassembler::Success;
2165 // Note the J1 and J2 values are from the encoded instruction. So here
2166 // change them to I1 and I2 values via as documented:
2167 // I1 = NOT(J1 EOR S);
2168 // I2 = NOT(J2 EOR S);
2169 // and build the imm32 with one trailing zero as documented:
2170 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32);
2171 unsigned S = fieldFromInstruction(Insn, 26, 1);
2172 unsigned J1 = fieldFromInstruction(Insn, 13, 1);
2173 unsigned J2 = fieldFromInstruction(Insn, 11, 1);
2174 unsigned I1 = !(J1 ^ S);
2175 unsigned I2 = !(J2 ^ S);
2176 unsigned imm10 = fieldFromInstruction(Insn, 16, 10);
2177 unsigned imm11 = fieldFromInstruction(Insn, 0, 11);
2178 unsigned tmp = (S << 23) | (I1 << 22) | (I2 << 21) | (imm10 << 11) | imm11;
2179 int imm32 = SignExtend32<25>(tmp << 1);
2180 if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4,
2181 true, 4, Inst, Decoder))
2182 Inst.addOperand(MCOperand::CreateImm(imm32));
2188 DecodeBranchImmInstruction(MCInst &Inst, unsigned Insn,
2189 uint64_t Address, const void *Decoder) {
2190 DecodeStatus S = MCDisassembler::Success;
2192 unsigned pred = fieldFromInstruction(Insn, 28, 4);
2193 unsigned imm = fieldFromInstruction(Insn, 0, 24) << 2;
2196 Inst.setOpcode(ARM::BLXi);
2197 imm |= fieldFromInstruction(Insn, 24, 1) << 1;
2198 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8,
2199 true, 4, Inst, Decoder))
2200 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm)));
2204 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8,
2205 true, 4, Inst, Decoder))
2206 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm)));
2207 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2208 return MCDisassembler::Fail;
2214 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val,
2215 uint64_t Address, const void *Decoder) {
2216 DecodeStatus S = MCDisassembler::Success;
2218 unsigned Rm = fieldFromInstruction(Val, 0, 4);
2219 unsigned align = fieldFromInstruction(Val, 4, 2);
2221 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2222 return MCDisassembler::Fail;
2224 Inst.addOperand(MCOperand::CreateImm(0));
2226 Inst.addOperand(MCOperand::CreateImm(4 << align));
2231 static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Insn,
2232 uint64_t Address, const void *Decoder) {
2233 DecodeStatus S = MCDisassembler::Success;
2235 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2236 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2237 unsigned wb = fieldFromInstruction(Insn, 16, 4);
2238 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2239 Rn |= fieldFromInstruction(Insn, 4, 2) << 4;
2240 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2242 // First output register
2243 switch (Inst.getOpcode()) {
2244 case ARM::VLD1q16: case ARM::VLD1q32: case ARM::VLD1q64: case ARM::VLD1q8:
2245 case ARM::VLD1q16wb_fixed: case ARM::VLD1q16wb_register:
2246 case ARM::VLD1q32wb_fixed: case ARM::VLD1q32wb_register:
2247 case ARM::VLD1q64wb_fixed: case ARM::VLD1q64wb_register:
2248 case ARM::VLD1q8wb_fixed: case ARM::VLD1q8wb_register:
2249 case ARM::VLD2d16: case ARM::VLD2d32: case ARM::VLD2d8:
2250 case ARM::VLD2d16wb_fixed: case ARM::VLD2d16wb_register:
2251 case ARM::VLD2d32wb_fixed: case ARM::VLD2d32wb_register:
2252 case ARM::VLD2d8wb_fixed: case ARM::VLD2d8wb_register:
2253 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2254 return MCDisassembler::Fail;
2259 case ARM::VLD2b16wb_fixed:
2260 case ARM::VLD2b16wb_register:
2261 case ARM::VLD2b32wb_fixed:
2262 case ARM::VLD2b32wb_register:
2263 case ARM::VLD2b8wb_fixed:
2264 case ARM::VLD2b8wb_register:
2265 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
2266 return MCDisassembler::Fail;
2269 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2270 return MCDisassembler::Fail;
2273 // Second output register
2274 switch (Inst.getOpcode()) {
2278 case ARM::VLD3d8_UPD:
2279 case ARM::VLD3d16_UPD:
2280 case ARM::VLD3d32_UPD:
2284 case ARM::VLD4d8_UPD:
2285 case ARM::VLD4d16_UPD:
2286 case ARM::VLD4d32_UPD:
2287 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
2288 return MCDisassembler::Fail;
2293 case ARM::VLD3q8_UPD:
2294 case ARM::VLD3q16_UPD:
2295 case ARM::VLD3q32_UPD:
2299 case ARM::VLD4q8_UPD:
2300 case ARM::VLD4q16_UPD:
2301 case ARM::VLD4q32_UPD:
2302 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2303 return MCDisassembler::Fail;
2308 // Third output register
2309 switch(Inst.getOpcode()) {
2313 case ARM::VLD3d8_UPD:
2314 case ARM::VLD3d16_UPD:
2315 case ARM::VLD3d32_UPD:
2319 case ARM::VLD4d8_UPD:
2320 case ARM::VLD4d16_UPD:
2321 case ARM::VLD4d32_UPD:
2322 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2323 return MCDisassembler::Fail;
2328 case ARM::VLD3q8_UPD:
2329 case ARM::VLD3q16_UPD:
2330 case ARM::VLD3q32_UPD:
2334 case ARM::VLD4q8_UPD:
2335 case ARM::VLD4q16_UPD:
2336 case ARM::VLD4q32_UPD:
2337 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
2338 return MCDisassembler::Fail;
2344 // Fourth output register
2345 switch (Inst.getOpcode()) {
2349 case ARM::VLD4d8_UPD:
2350 case ARM::VLD4d16_UPD:
2351 case ARM::VLD4d32_UPD:
2352 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
2353 return MCDisassembler::Fail;
2358 case ARM::VLD4q8_UPD:
2359 case ARM::VLD4q16_UPD:
2360 case ARM::VLD4q32_UPD:
2361 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
2362 return MCDisassembler::Fail;
2368 // Writeback operand
2369 switch (Inst.getOpcode()) {
2370 case ARM::VLD1d8wb_fixed:
2371 case ARM::VLD1d16wb_fixed:
2372 case ARM::VLD1d32wb_fixed:
2373 case ARM::VLD1d64wb_fixed:
2374 case ARM::VLD1d8wb_register:
2375 case ARM::VLD1d16wb_register:
2376 case ARM::VLD1d32wb_register:
2377 case ARM::VLD1d64wb_register:
2378 case ARM::VLD1q8wb_fixed:
2379 case ARM::VLD1q16wb_fixed:
2380 case ARM::VLD1q32wb_fixed:
2381 case ARM::VLD1q64wb_fixed:
2382 case ARM::VLD1q8wb_register:
2383 case ARM::VLD1q16wb_register:
2384 case ARM::VLD1q32wb_register:
2385 case ARM::VLD1q64wb_register:
2386 case ARM::VLD1d8Twb_fixed:
2387 case ARM::VLD1d8Twb_register:
2388 case ARM::VLD1d16Twb_fixed:
2389 case ARM::VLD1d16Twb_register:
2390 case ARM::VLD1d32Twb_fixed:
2391 case ARM::VLD1d32Twb_register:
2392 case ARM::VLD1d64Twb_fixed:
2393 case ARM::VLD1d64Twb_register:
2394 case ARM::VLD1d8Qwb_fixed:
2395 case ARM::VLD1d8Qwb_register:
2396 case ARM::VLD1d16Qwb_fixed:
2397 case ARM::VLD1d16Qwb_register:
2398 case ARM::VLD1d32Qwb_fixed:
2399 case ARM::VLD1d32Qwb_register:
2400 case ARM::VLD1d64Qwb_fixed:
2401 case ARM::VLD1d64Qwb_register:
2402 case ARM::VLD2d8wb_fixed:
2403 case ARM::VLD2d16wb_fixed:
2404 case ARM::VLD2d32wb_fixed:
2405 case ARM::VLD2q8wb_fixed:
2406 case ARM::VLD2q16wb_fixed:
2407 case ARM::VLD2q32wb_fixed:
2408 case ARM::VLD2d8wb_register:
2409 case ARM::VLD2d16wb_register:
2410 case ARM::VLD2d32wb_register:
2411 case ARM::VLD2q8wb_register:
2412 case ARM::VLD2q16wb_register:
2413 case ARM::VLD2q32wb_register:
2414 case ARM::VLD2b8wb_fixed:
2415 case ARM::VLD2b16wb_fixed:
2416 case ARM::VLD2b32wb_fixed:
2417 case ARM::VLD2b8wb_register:
2418 case ARM::VLD2b16wb_register:
2419 case ARM::VLD2b32wb_register:
2420 Inst.addOperand(MCOperand::CreateImm(0));
2422 case ARM::VLD3d8_UPD:
2423 case ARM::VLD3d16_UPD:
2424 case ARM::VLD3d32_UPD:
2425 case ARM::VLD3q8_UPD:
2426 case ARM::VLD3q16_UPD:
2427 case ARM::VLD3q32_UPD:
2428 case ARM::VLD4d8_UPD:
2429 case ARM::VLD4d16_UPD:
2430 case ARM::VLD4d32_UPD:
2431 case ARM::VLD4q8_UPD:
2432 case ARM::VLD4q16_UPD:
2433 case ARM::VLD4q32_UPD:
2434 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
2435 return MCDisassembler::Fail;
2441 // AddrMode6 Base (register+alignment)
2442 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
2443 return MCDisassembler::Fail;
2445 // AddrMode6 Offset (register)
2446 switch (Inst.getOpcode()) {
2448 // The below have been updated to have explicit am6offset split
2449 // between fixed and register offset. For those instructions not
2450 // yet updated, we need to add an additional reg0 operand for the
2453 // The fixed offset encodes as Rm == 0xd, so we check for that.
2455 Inst.addOperand(MCOperand::CreateReg(0));
2458 // Fall through to handle the register offset variant.
2459 case ARM::VLD1d8wb_fixed:
2460 case ARM::VLD1d16wb_fixed:
2461 case ARM::VLD1d32wb_fixed:
2462 case ARM::VLD1d64wb_fixed:
2463 case ARM::VLD1d8Twb_fixed:
2464 case ARM::VLD1d16Twb_fixed:
2465 case ARM::VLD1d32Twb_fixed:
2466 case ARM::VLD1d64Twb_fixed:
2467 case ARM::VLD1d8Qwb_fixed:
2468 case ARM::VLD1d16Qwb_fixed:
2469 case ARM::VLD1d32Qwb_fixed:
2470 case ARM::VLD1d64Qwb_fixed:
2471 case ARM::VLD1d8wb_register:
2472 case ARM::VLD1d16wb_register:
2473 case ARM::VLD1d32wb_register:
2474 case ARM::VLD1d64wb_register:
2475 case ARM::VLD1q8wb_fixed:
2476 case ARM::VLD1q16wb_fixed:
2477 case ARM::VLD1q32wb_fixed:
2478 case ARM::VLD1q64wb_fixed:
2479 case ARM::VLD1q8wb_register:
2480 case ARM::VLD1q16wb_register:
2481 case ARM::VLD1q32wb_register:
2482 case ARM::VLD1q64wb_register:
2483 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback
2484 // variant encodes Rm == 0xf. Anything else is a register offset post-
2485 // increment and we need to add the register operand to the instruction.
2486 if (Rm != 0xD && Rm != 0xF &&
2487 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2488 return MCDisassembler::Fail;
2490 case ARM::VLD2d8wb_fixed:
2491 case ARM::VLD2d16wb_fixed:
2492 case ARM::VLD2d32wb_fixed:
2493 case ARM::VLD2b8wb_fixed:
2494 case ARM::VLD2b16wb_fixed:
2495 case ARM::VLD2b32wb_fixed:
2496 case ARM::VLD2q8wb_fixed:
2497 case ARM::VLD2q16wb_fixed:
2498 case ARM::VLD2q32wb_fixed:
2505 static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Insn,
2506 uint64_t Address, const void *Decoder) {
2507 unsigned type = fieldFromInstruction(Insn, 8, 4);
2508 unsigned align = fieldFromInstruction(Insn, 4, 2);
2509 if (type == 6 && (align & 2)) return MCDisassembler::Fail;
2510 if (type == 7 && (align & 2)) return MCDisassembler::Fail;
2511 if (type == 10 && align == 3) return MCDisassembler::Fail;
2513 unsigned load = fieldFromInstruction(Insn, 21, 1);
2514 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
2515 : DecodeVSTInstruction(Inst, Insn, Address, Decoder);
2518 static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Insn,
2519 uint64_t Address, const void *Decoder) {
2520 unsigned size = fieldFromInstruction(Insn, 6, 2);
2521 if (size == 3) return MCDisassembler::Fail;
2523 unsigned type = fieldFromInstruction(Insn, 8, 4);
2524 unsigned align = fieldFromInstruction(Insn, 4, 2);
2525 if (type == 8 && align == 3) return MCDisassembler::Fail;
2526 if (type == 9 && align == 3) return MCDisassembler::Fail;
2528 unsigned load = fieldFromInstruction(Insn, 21, 1);
2529 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
2530 : DecodeVSTInstruction(Inst, Insn, Address, Decoder);
2533 static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Insn,
2534 uint64_t Address, const void *Decoder) {
2535 unsigned size = fieldFromInstruction(Insn, 6, 2);
2536 if (size == 3) return MCDisassembler::Fail;
2538 unsigned align = fieldFromInstruction(Insn, 4, 2);
2539 if (align & 2) return MCDisassembler::Fail;
2541 unsigned load = fieldFromInstruction(Insn, 21, 1);
2542 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
2543 : DecodeVSTInstruction(Inst, Insn, Address, Decoder);
2546 static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Insn,
2547 uint64_t Address, const void *Decoder) {
2548 unsigned size = fieldFromInstruction(Insn, 6, 2);
2549 if (size == 3) return MCDisassembler::Fail;
2551 unsigned load = fieldFromInstruction(Insn, 21, 1);
2552 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
2553 : DecodeVSTInstruction(Inst, Insn, Address, Decoder);
2556 static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Insn,
2557 uint64_t Address, const void *Decoder) {
2558 DecodeStatus S = MCDisassembler::Success;
2560 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2561 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2562 unsigned wb = fieldFromInstruction(Insn, 16, 4);
2563 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2564 Rn |= fieldFromInstruction(Insn, 4, 2) << 4;
2565 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2567 // Writeback Operand
2568 switch (Inst.getOpcode()) {
2569 case ARM::VST1d8wb_fixed:
2570 case ARM::VST1d16wb_fixed:
2571 case ARM::VST1d32wb_fixed:
2572 case ARM::VST1d64wb_fixed:
2573 case ARM::VST1d8wb_register:
2574 case ARM::VST1d16wb_register:
2575 case ARM::VST1d32wb_register:
2576 case ARM::VST1d64wb_register:
2577 case ARM::VST1q8wb_fixed:
2578 case ARM::VST1q16wb_fixed:
2579 case ARM::VST1q32wb_fixed:
2580 case ARM::VST1q64wb_fixed:
2581 case ARM::VST1q8wb_register:
2582 case ARM::VST1q16wb_register:
2583 case ARM::VST1q32wb_register:
2584 case ARM::VST1q64wb_register:
2585 case ARM::VST1d8Twb_fixed:
2586 case ARM::VST1d16Twb_fixed:
2587 case ARM::VST1d32Twb_fixed:
2588 case ARM::VST1d64Twb_fixed:
2589 case ARM::VST1d8Twb_register:
2590 case ARM::VST1d16Twb_register:
2591 case ARM::VST1d32Twb_register:
2592 case ARM::VST1d64Twb_register:
2593 case ARM::VST1d8Qwb_fixed:
2594 case ARM::VST1d16Qwb_fixed:
2595 case ARM::VST1d32Qwb_fixed:
2596 case ARM::VST1d64Qwb_fixed:
2597 case ARM::VST1d8Qwb_register:
2598 case ARM::VST1d16Qwb_register:
2599 case ARM::VST1d32Qwb_register:
2600 case ARM::VST1d64Qwb_register:
2601 case ARM::VST2d8wb_fixed:
2602 case ARM::VST2d16wb_fixed:
2603 case ARM::VST2d32wb_fixed:
2604 case ARM::VST2d8wb_register:
2605 case ARM::VST2d16wb_register:
2606 case ARM::VST2d32wb_register:
2607 case ARM::VST2q8wb_fixed:
2608 case ARM::VST2q16wb_fixed:
2609 case ARM::VST2q32wb_fixed:
2610 case ARM::VST2q8wb_register:
2611 case ARM::VST2q16wb_register:
2612 case ARM::VST2q32wb_register:
2613 case ARM::VST2b8wb_fixed:
2614 case ARM::VST2b16wb_fixed:
2615 case ARM::VST2b32wb_fixed:
2616 case ARM::VST2b8wb_register:
2617 case ARM::VST2b16wb_register:
2618 case ARM::VST2b32wb_register:
2620 return MCDisassembler::Fail;
2621 Inst.addOperand(MCOperand::CreateImm(0));
2623 case ARM::VST3d8_UPD:
2624 case ARM::VST3d16_UPD:
2625 case ARM::VST3d32_UPD:
2626 case ARM::VST3q8_UPD:
2627 case ARM::VST3q16_UPD:
2628 case ARM::VST3q32_UPD:
2629 case ARM::VST4d8_UPD:
2630 case ARM::VST4d16_UPD:
2631 case ARM::VST4d32_UPD:
2632 case ARM::VST4q8_UPD:
2633 case ARM::VST4q16_UPD:
2634 case ARM::VST4q32_UPD:
2635 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
2636 return MCDisassembler::Fail;
2642 // AddrMode6 Base (register+alignment)
2643 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
2644 return MCDisassembler::Fail;
2646 // AddrMode6 Offset (register)
2647 switch (Inst.getOpcode()) {
2650 Inst.addOperand(MCOperand::CreateReg(0));
2651 else if (Rm != 0xF) {
2652 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2653 return MCDisassembler::Fail;
2656 case ARM::VST1d8wb_fixed:
2657 case ARM::VST1d16wb_fixed:
2658 case ARM::VST1d32wb_fixed:
2659 case ARM::VST1d64wb_fixed:
2660 case ARM::VST1q8wb_fixed:
2661 case ARM::VST1q16wb_fixed:
2662 case ARM::VST1q32wb_fixed:
2663 case ARM::VST1q64wb_fixed:
2664 case ARM::VST1d8Twb_fixed:
2665 case ARM::VST1d16Twb_fixed:
2666 case ARM::VST1d32Twb_fixed:
2667 case ARM::VST1d64Twb_fixed:
2668 case ARM::VST1d8Qwb_fixed:
2669 case ARM::VST1d16Qwb_fixed:
2670 case ARM::VST1d32Qwb_fixed:
2671 case ARM::VST1d64Qwb_fixed:
2672 case ARM::VST2d8wb_fixed:
2673 case ARM::VST2d16wb_fixed:
2674 case ARM::VST2d32wb_fixed:
2675 case ARM::VST2q8wb_fixed:
2676 case ARM::VST2q16wb_fixed:
2677 case ARM::VST2q32wb_fixed:
2678 case ARM::VST2b8wb_fixed:
2679 case ARM::VST2b16wb_fixed:
2680 case ARM::VST2b32wb_fixed:
2685 // First input register
2686 switch (Inst.getOpcode()) {
2691 case ARM::VST1q16wb_fixed:
2692 case ARM::VST1q16wb_register:
2693 case ARM::VST1q32wb_fixed:
2694 case ARM::VST1q32wb_register:
2695 case ARM::VST1q64wb_fixed:
2696 case ARM::VST1q64wb_register:
2697 case ARM::VST1q8wb_fixed:
2698 case ARM::VST1q8wb_register:
2702 case ARM::VST2d16wb_fixed:
2703 case ARM::VST2d16wb_register:
2704 case ARM::VST2d32wb_fixed:
2705 case ARM::VST2d32wb_register:
2706 case ARM::VST2d8wb_fixed:
2707 case ARM::VST2d8wb_register:
2708 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2709 return MCDisassembler::Fail;
2714 case ARM::VST2b16wb_fixed:
2715 case ARM::VST2b16wb_register:
2716 case ARM::VST2b32wb_fixed:
2717 case ARM::VST2b32wb_register:
2718 case ARM::VST2b8wb_fixed:
2719 case ARM::VST2b8wb_register:
2720 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
2721 return MCDisassembler::Fail;
2724 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2725 return MCDisassembler::Fail;
2728 // Second input register
2729 switch (Inst.getOpcode()) {
2733 case ARM::VST3d8_UPD:
2734 case ARM::VST3d16_UPD:
2735 case ARM::VST3d32_UPD:
2739 case ARM::VST4d8_UPD:
2740 case ARM::VST4d16_UPD:
2741 case ARM::VST4d32_UPD:
2742 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
2743 return MCDisassembler::Fail;
2748 case ARM::VST3q8_UPD:
2749 case ARM::VST3q16_UPD:
2750 case ARM::VST3q32_UPD:
2754 case ARM::VST4q8_UPD:
2755 case ARM::VST4q16_UPD:
2756 case ARM::VST4q32_UPD:
2757 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2758 return MCDisassembler::Fail;
2764 // Third input register
2765 switch (Inst.getOpcode()) {
2769 case ARM::VST3d8_UPD:
2770 case ARM::VST3d16_UPD:
2771 case ARM::VST3d32_UPD:
2775 case ARM::VST4d8_UPD:
2776 case ARM::VST4d16_UPD:
2777 case ARM::VST4d32_UPD:
2778 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2779 return MCDisassembler::Fail;
2784 case ARM::VST3q8_UPD:
2785 case ARM::VST3q16_UPD:
2786 case ARM::VST3q32_UPD:
2790 case ARM::VST4q8_UPD:
2791 case ARM::VST4q16_UPD:
2792 case ARM::VST4q32_UPD:
2793 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
2794 return MCDisassembler::Fail;
2800 // Fourth input register
2801 switch (Inst.getOpcode()) {
2805 case ARM::VST4d8_UPD:
2806 case ARM::VST4d16_UPD:
2807 case ARM::VST4d32_UPD:
2808 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
2809 return MCDisassembler::Fail;
2814 case ARM::VST4q8_UPD:
2815 case ARM::VST4q16_UPD:
2816 case ARM::VST4q32_UPD:
2817 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
2818 return MCDisassembler::Fail;
2827 static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Insn,
2828 uint64_t Address, const void *Decoder) {
2829 DecodeStatus S = MCDisassembler::Success;
2831 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2832 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2833 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2834 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2835 unsigned align = fieldFromInstruction(Insn, 4, 1);
2836 unsigned size = fieldFromInstruction(Insn, 6, 2);
2838 if (size == 0 && align == 1)
2839 return MCDisassembler::Fail;
2840 align *= (1 << size);
2842 switch (Inst.getOpcode()) {
2843 case ARM::VLD1DUPq16: case ARM::VLD1DUPq32: case ARM::VLD1DUPq8:
2844 case ARM::VLD1DUPq16wb_fixed: case ARM::VLD1DUPq16wb_register:
2845 case ARM::VLD1DUPq32wb_fixed: case ARM::VLD1DUPq32wb_register:
2846 case ARM::VLD1DUPq8wb_fixed: case ARM::VLD1DUPq8wb_register:
2847 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2848 return MCDisassembler::Fail;
2851 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2852 return MCDisassembler::Fail;
2856 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2857 return MCDisassembler::Fail;
2860 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2861 return MCDisassembler::Fail;
2862 Inst.addOperand(MCOperand::CreateImm(align));
2864 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback
2865 // variant encodes Rm == 0xf. Anything else is a register offset post-
2866 // increment and we need to add the register operand to the instruction.
2867 if (Rm != 0xD && Rm != 0xF &&
2868 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2869 return MCDisassembler::Fail;
2874 static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Insn,
2875 uint64_t Address, const void *Decoder) {
2876 DecodeStatus S = MCDisassembler::Success;
2878 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2879 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2880 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2881 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2882 unsigned align = fieldFromInstruction(Insn, 4, 1);
2883 unsigned size = 1 << fieldFromInstruction(Insn, 6, 2);
2886 switch (Inst.getOpcode()) {
2887 case ARM::VLD2DUPd16: case ARM::VLD2DUPd32: case ARM::VLD2DUPd8:
2888 case ARM::VLD2DUPd16wb_fixed: case ARM::VLD2DUPd16wb_register:
2889 case ARM::VLD2DUPd32wb_fixed: case ARM::VLD2DUPd32wb_register:
2890 case ARM::VLD2DUPd8wb_fixed: case ARM::VLD2DUPd8wb_register:
2891 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2892 return MCDisassembler::Fail;
2894 case ARM::VLD2DUPd16x2: case ARM::VLD2DUPd32x2: case ARM::VLD2DUPd8x2:
2895 case ARM::VLD2DUPd16x2wb_fixed: case ARM::VLD2DUPd16x2wb_register:
2896 case ARM::VLD2DUPd32x2wb_fixed: case ARM::VLD2DUPd32x2wb_register:
2897 case ARM::VLD2DUPd8x2wb_fixed: case ARM::VLD2DUPd8x2wb_register:
2898 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
2899 return MCDisassembler::Fail;
2902 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2903 return MCDisassembler::Fail;
2908 Inst.addOperand(MCOperand::CreateImm(0));
2910 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2911 return MCDisassembler::Fail;
2912 Inst.addOperand(MCOperand::CreateImm(align));
2914 if (Rm != 0xD && Rm != 0xF) {
2915 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2916 return MCDisassembler::Fail;
2922 static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Insn,
2923 uint64_t Address, const void *Decoder) {
2924 DecodeStatus S = MCDisassembler::Success;
2926 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2927 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2928 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2929 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2930 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1;
2932 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2933 return MCDisassembler::Fail;
2934 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
2935 return MCDisassembler::Fail;
2936 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
2937 return MCDisassembler::Fail;
2939 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2940 return MCDisassembler::Fail;
2943 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2944 return MCDisassembler::Fail;
2945 Inst.addOperand(MCOperand::CreateImm(0));
2948 Inst.addOperand(MCOperand::CreateReg(0));
2949 else if (Rm != 0xF) {
2950 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2951 return MCDisassembler::Fail;
2957 static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Insn,
2958 uint64_t Address, const void *Decoder) {
2959 DecodeStatus S = MCDisassembler::Success;
2961 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2962 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2963 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2964 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2965 unsigned size = fieldFromInstruction(Insn, 6, 2);
2966 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1;
2967 unsigned align = fieldFromInstruction(Insn, 4, 1);
2971 return MCDisassembler::Fail;
2982 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2983 return MCDisassembler::Fail;
2984 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
2985 return MCDisassembler::Fail;
2986 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
2987 return MCDisassembler::Fail;
2988 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder)))
2989 return MCDisassembler::Fail;
2991 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2992 return MCDisassembler::Fail;
2995 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2996 return MCDisassembler::Fail;
2997 Inst.addOperand(MCOperand::CreateImm(align));
3000 Inst.addOperand(MCOperand::CreateReg(0));
3001 else if (Rm != 0xF) {
3002 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3003 return MCDisassembler::Fail;
3010 DecodeNEONModImmInstruction(MCInst &Inst, unsigned Insn,
3011 uint64_t Address, const void *Decoder) {
3012 DecodeStatus S = MCDisassembler::Success;
3014 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3015 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3016 unsigned imm = fieldFromInstruction(Insn, 0, 4);
3017 imm |= fieldFromInstruction(Insn, 16, 3) << 4;
3018 imm |= fieldFromInstruction(Insn, 24, 1) << 7;
3019 imm |= fieldFromInstruction(Insn, 8, 4) << 8;
3020 imm |= fieldFromInstruction(Insn, 5, 1) << 12;
3021 unsigned Q = fieldFromInstruction(Insn, 6, 1);
3024 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
3025 return MCDisassembler::Fail;
3027 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3028 return MCDisassembler::Fail;
3031 Inst.addOperand(MCOperand::CreateImm(imm));
3033 switch (Inst.getOpcode()) {
3034 case ARM::VORRiv4i16:
3035 case ARM::VORRiv2i32:
3036 case ARM::VBICiv4i16:
3037 case ARM::VBICiv2i32:
3038 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3039 return MCDisassembler::Fail;
3041 case ARM::VORRiv8i16:
3042 case ARM::VORRiv4i32:
3043 case ARM::VBICiv8i16:
3044 case ARM::VBICiv4i32:
3045 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
3046 return MCDisassembler::Fail;
3055 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Insn,
3056 uint64_t Address, const void *Decoder) {
3057 DecodeStatus S = MCDisassembler::Success;
3059 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3060 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3061 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3062 Rm |= fieldFromInstruction(Insn, 5, 1) << 4;
3063 unsigned size = fieldFromInstruction(Insn, 18, 2);
3065 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
3066 return MCDisassembler::Fail;
3067 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
3068 return MCDisassembler::Fail;
3069 Inst.addOperand(MCOperand::CreateImm(8 << size));
3074 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val,
3075 uint64_t Address, const void *Decoder) {
3076 Inst.addOperand(MCOperand::CreateImm(8 - Val));
3077 return MCDisassembler::Success;
3080 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val,
3081 uint64_t Address, const void *Decoder) {
3082 Inst.addOperand(MCOperand::CreateImm(16 - Val));
3083 return MCDisassembler::Success;
3086 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val,
3087 uint64_t Address, const void *Decoder) {
3088 Inst.addOperand(MCOperand::CreateImm(32 - Val));
3089 return MCDisassembler::Success;
3092 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val,
3093 uint64_t Address, const void *Decoder) {
3094 Inst.addOperand(MCOperand::CreateImm(64 - Val));
3095 return MCDisassembler::Success;
3098 static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn,
3099 uint64_t Address, const void *Decoder) {
3100 DecodeStatus S = MCDisassembler::Success;
3102 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3103 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3104 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3105 Rn |= fieldFromInstruction(Insn, 7, 1) << 4;
3106 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3107 Rm |= fieldFromInstruction(Insn, 5, 1) << 4;
3108 unsigned op = fieldFromInstruction(Insn, 6, 1);
3110 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3111 return MCDisassembler::Fail;
3113 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3114 return MCDisassembler::Fail; // Writeback
3117 switch (Inst.getOpcode()) {
3120 if (!Check(S, DecodeDPairRegisterClass(Inst, Rn, Address, Decoder)))
3121 return MCDisassembler::Fail;
3124 if (!Check(S, DecodeDPRRegisterClass(Inst, Rn, Address, Decoder)))
3125 return MCDisassembler::Fail;
3128 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
3129 return MCDisassembler::Fail;
3134 static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn,
3135 uint64_t Address, const void *Decoder) {
3136 DecodeStatus S = MCDisassembler::Success;
3138 unsigned dst = fieldFromInstruction(Insn, 8, 3);
3139 unsigned imm = fieldFromInstruction(Insn, 0, 8);
3141 if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder)))
3142 return MCDisassembler::Fail;
3144 switch(Inst.getOpcode()) {
3146 return MCDisassembler::Fail;
3148 break; // tADR does not explicitly represent the PC as an operand.
3150 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3154 Inst.addOperand(MCOperand::CreateImm(imm));
3158 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val,
3159 uint64_t Address, const void *Decoder) {
3160 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<12>(Val<<1) + 4,
3161 true, 2, Inst, Decoder))
3162 Inst.addOperand(MCOperand::CreateImm(SignExtend32<12>(Val << 1)));
3163 return MCDisassembler::Success;
3166 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val,
3167 uint64_t Address, const void *Decoder) {
3168 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<21>(Val) + 4,
3169 true, 4, Inst, Decoder))
3170 Inst.addOperand(MCOperand::CreateImm(SignExtend32<21>(Val)));
3171 return MCDisassembler::Success;
3174 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val,
3175 uint64_t Address, const void *Decoder) {
3176 if (!tryAddingSymbolicOperand(Address, Address + (Val<<1) + 4,
3177 true, 2, Inst, Decoder))
3178 Inst.addOperand(MCOperand::CreateImm(Val << 1));
3179 return MCDisassembler::Success;
3182 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val,
3183 uint64_t Address, const void *Decoder) {
3184 DecodeStatus S = MCDisassembler::Success;
3186 unsigned Rn = fieldFromInstruction(Val, 0, 3);
3187 unsigned Rm = fieldFromInstruction(Val, 3, 3);
3189 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
3190 return MCDisassembler::Fail;
3191 if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder)))
3192 return MCDisassembler::Fail;
3197 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val,
3198 uint64_t Address, const void *Decoder) {
3199 DecodeStatus S = MCDisassembler::Success;
3201 unsigned Rn = fieldFromInstruction(Val, 0, 3);
3202 unsigned imm = fieldFromInstruction(Val, 3, 5);
3204 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
3205 return MCDisassembler::Fail;
3206 Inst.addOperand(MCOperand::CreateImm(imm));
3211 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val,
3212 uint64_t Address, const void *Decoder) {
3213 unsigned imm = Val << 2;
3215 Inst.addOperand(MCOperand::CreateImm(imm));
3216 tryAddingPcLoadReferenceComment(Address, (Address & ~2u) + imm + 4, Decoder);
3218 return MCDisassembler::Success;
3221 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val,
3222 uint64_t Address, const void *Decoder) {
3223 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3224 Inst.addOperand(MCOperand::CreateImm(Val));
3226 return MCDisassembler::Success;
3229 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val,
3230 uint64_t Address, const void *Decoder) {
3231 DecodeStatus S = MCDisassembler::Success;
3233 unsigned Rn = fieldFromInstruction(Val, 6, 4);
3234 unsigned Rm = fieldFromInstruction(Val, 2, 4);
3235 unsigned imm = fieldFromInstruction(Val, 0, 2);
3237 // Thumb stores cannot use PC as dest register.
3238 switch (Inst.getOpcode()) {
3243 return MCDisassembler::Fail;
3248 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3249 return MCDisassembler::Fail;
3250 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
3251 return MCDisassembler::Fail;
3252 Inst.addOperand(MCOperand::CreateImm(imm));
3257 static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Insn,
3258 uint64_t Address, const void *Decoder) {
3259 DecodeStatus S = MCDisassembler::Success;
3261 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3262 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3264 uint64_t featureBits = ((const MCDisassembler*)Decoder)->getSubtargetInfo()
3266 bool hasMP = featureBits & ARM::FeatureMP;
3267 bool hasV7Ops = featureBits & ARM::HasV7Ops;
3270 switch (Inst.getOpcode()) {
3272 Inst.setOpcode(ARM::t2LDRBpci);
3275 Inst.setOpcode(ARM::t2LDRHpci);
3278 Inst.setOpcode(ARM::t2LDRSHpci);
3281 Inst.setOpcode(ARM::t2LDRSBpci);
3284 Inst.setOpcode(ARM::t2LDRpci);
3287 Inst.setOpcode(ARM::t2PLDpci);
3290 Inst.setOpcode(ARM::t2PLIpci);
3293 return MCDisassembler::Fail;
3296 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
3300 switch (Inst.getOpcode()) {
3302 return MCDisassembler::Fail;
3304 Inst.setOpcode(ARM::t2PLDWs);
3307 Inst.setOpcode(ARM::t2PLIs);
3313 switch (Inst.getOpcode()) {
3318 return MCDisassembler::Fail;
3321 if (!hasV7Ops || !hasMP)
3322 return MCDisassembler::Fail;
3325 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3326 return MCDisassembler::Fail;
3329 unsigned addrmode = fieldFromInstruction(Insn, 4, 2);
3330 addrmode |= fieldFromInstruction(Insn, 0, 4) << 2;
3331 addrmode |= fieldFromInstruction(Insn, 16, 4) << 6;
3332 if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder)))
3333 return MCDisassembler::Fail;
3338 static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn,
3339 uint64_t Address, const void* Decoder) {
3340 DecodeStatus S = MCDisassembler::Success;
3342 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3343 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3344 unsigned U = fieldFromInstruction(Insn, 9, 1);
3345 unsigned imm = fieldFromInstruction(Insn, 0, 8);
3348 unsigned add = fieldFromInstruction(Insn, 9, 1);
3350 uint64_t featureBits = ((const MCDisassembler*)Decoder)->getSubtargetInfo()
3352 bool hasMP = featureBits & ARM::FeatureMP;
3353 bool hasV7Ops = featureBits & ARM::HasV7Ops;
3356 switch (Inst.getOpcode()) {
3358 Inst.setOpcode(ARM::t2LDRpci);
3361 Inst.setOpcode(ARM::t2LDRBpci);
3363 case ARM::t2LDRSBi8:
3364 Inst.setOpcode(ARM::t2LDRSBpci);
3367 Inst.setOpcode(ARM::t2LDRHpci);
3369 case ARM::t2LDRSHi8:
3370 Inst.setOpcode(ARM::t2LDRSHpci);
3373 Inst.setOpcode(ARM::t2PLDpci);
3376 Inst.setOpcode(ARM::t2PLIpci);
3379 return MCDisassembler::Fail;
3381 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
3385 switch (Inst.getOpcode()) {
3386 case ARM::t2LDRSHi8:
3387 return MCDisassembler::Fail;
3390 Inst.setOpcode(ARM::t2PLDWi8);
3392 case ARM::t2LDRSBi8:
3393 Inst.setOpcode(ARM::t2PLIi8);
3400 switch (Inst.getOpcode()) {
3405 return MCDisassembler::Fail;
3408 if (!hasV7Ops || !hasMP)
3409 return MCDisassembler::Fail;
3412 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3413 return MCDisassembler::Fail;
3416 if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder)))
3417 return MCDisassembler::Fail;
3421 static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn,
3422 uint64_t Address, const void* Decoder) {
3423 DecodeStatus S = MCDisassembler::Success;
3425 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3426 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3427 unsigned imm = fieldFromInstruction(Insn, 0, 12);
3430 uint64_t featureBits = ((const MCDisassembler*)Decoder)->getSubtargetInfo()
3432 bool hasMP = (featureBits & ARM::FeatureMP);
3433 bool hasV7Ops = (featureBits & ARM::HasV7Ops);
3436 switch (Inst.getOpcode()) {
3438 Inst.setOpcode(ARM::t2LDRpci);
3440 case ARM::t2LDRHi12:
3441 Inst.setOpcode(ARM::t2LDRHpci);
3443 case ARM::t2LDRSHi12:
3444 Inst.setOpcode(ARM::t2LDRSHpci);
3446 case ARM::t2LDRBi12:
3447 Inst.setOpcode(ARM::t2LDRBpci);
3449 case ARM::t2LDRSBi12:
3450 Inst.setOpcode(ARM::t2LDRSBpci);
3453 Inst.setOpcode(ARM::t2PLDpci);
3456 Inst.setOpcode(ARM::t2PLIpci);
3459 return MCDisassembler::Fail;
3461 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
3465 switch (Inst.getOpcode()) {
3466 case ARM::t2LDRSHi12:
3467 return MCDisassembler::Fail;
3468 case ARM::t2LDRHi12:
3469 Inst.setOpcode(ARM::t2PLDWi12);
3471 case ARM::t2LDRSBi12:
3472 Inst.setOpcode(ARM::t2PLIi12);
3479 switch (Inst.getOpcode()) {
3484 return MCDisassembler::Fail;
3486 case ARM::t2PLDWi12:
3487 if (!hasV7Ops || !hasMP)
3488 return MCDisassembler::Fail;
3491 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3492 return MCDisassembler::Fail;
3495 if (!Check(S, DecodeT2AddrModeImm12(Inst, imm, Address, Decoder)))
3496 return MCDisassembler::Fail;
3500 static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn,
3501 uint64_t Address, const void* Decoder) {
3502 DecodeStatus S = MCDisassembler::Success;
3504 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3505 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3506 unsigned imm = fieldFromInstruction(Insn, 0, 8);
3510 switch (Inst.getOpcode()) {
3512 Inst.setOpcode(ARM::t2LDRpci);
3515 Inst.setOpcode(ARM::t2LDRBpci);
3518 Inst.setOpcode(ARM::t2LDRHpci);
3521 Inst.setOpcode(ARM::t2LDRSBpci);
3524 Inst.setOpcode(ARM::t2LDRSHpci);
3527 return MCDisassembler::Fail;
3529 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
3532 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
3533 return MCDisassembler::Fail;
3534 if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder)))
3535 return MCDisassembler::Fail;
3539 static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn,
3540 uint64_t Address, const void* Decoder) {
3541 DecodeStatus S = MCDisassembler::Success;
3543 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3544 unsigned U = fieldFromInstruction(Insn, 23, 1);
3545 int imm = fieldFromInstruction(Insn, 0, 12);
3547 uint64_t featureBits = ((const MCDisassembler*)Decoder)->getSubtargetInfo()
3549 bool hasV7Ops = (featureBits & ARM::HasV7Ops);
3552 switch (Inst.getOpcode()) {
3553 case ARM::t2LDRBpci:
3554 case ARM::t2LDRHpci:
3555 Inst.setOpcode(ARM::t2PLDpci);
3557 case ARM::t2LDRSBpci:
3558 Inst.setOpcode(ARM::t2PLIpci);
3560 case ARM::t2LDRSHpci:
3561 return MCDisassembler::Fail;
3567 switch(Inst.getOpcode()) {
3572 return MCDisassembler::Fail;
3575 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3576 return MCDisassembler::Fail;
3580 // Special case for #-0.
3586 Inst.addOperand(MCOperand::CreateImm(imm));
3591 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val,
3592 uint64_t Address, const void *Decoder) {
3594 Inst.addOperand(MCOperand::CreateImm(INT32_MIN));
3596 int imm = Val & 0xFF;
3598 if (!(Val & 0x100)) imm *= -1;
3599 Inst.addOperand(MCOperand::CreateImm(imm * 4));
3602 return MCDisassembler::Success;
3605 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val,
3606 uint64_t Address, const void *Decoder) {
3607 DecodeStatus S = MCDisassembler::Success;
3609 unsigned Rn = fieldFromInstruction(Val, 9, 4);
3610 unsigned imm = fieldFromInstruction(Val, 0, 9);
3612 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3613 return MCDisassembler::Fail;
3614 if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder)))
3615 return MCDisassembler::Fail;
3620 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val,
3621 uint64_t Address, const void *Decoder) {
3622 DecodeStatus S = MCDisassembler::Success;
3624 unsigned Rn = fieldFromInstruction(Val, 8, 4);
3625 unsigned imm = fieldFromInstruction(Val, 0, 8);
3627 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
3628 return MCDisassembler::Fail;
3630 Inst.addOperand(MCOperand::CreateImm(imm));
3635 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val,
3636 uint64_t Address, const void *Decoder) {
3637 int imm = Val & 0xFF;
3640 else if (!(Val & 0x100))
3642 Inst.addOperand(MCOperand::CreateImm(imm));
3644 return MCDisassembler::Success;
3648 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val,
3649 uint64_t Address, const void *Decoder) {
3650 DecodeStatus S = MCDisassembler::Success;
3652 unsigned Rn = fieldFromInstruction(Val, 9, 4);
3653 unsigned imm = fieldFromInstruction(Val, 0, 9);
3655 // Thumb stores cannot use PC as dest register.
3656 switch (Inst.getOpcode()) {
3664 return MCDisassembler::Fail;
3670 // Some instructions always use an additive offset.
3671 switch (Inst.getOpcode()) {
3686 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3687 return MCDisassembler::Fail;
3688 if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder)))
3689 return MCDisassembler::Fail;
3694 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Insn,
3695 uint64_t Address, const void *Decoder) {
3696 DecodeStatus S = MCDisassembler::Success;
3698 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3699 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3700 unsigned addr = fieldFromInstruction(Insn, 0, 8);
3701 addr |= fieldFromInstruction(Insn, 9, 1) << 8;
3703 unsigned load = fieldFromInstruction(Insn, 20, 1);
3706 switch (Inst.getOpcode()) {
3707 case ARM::t2LDR_PRE:
3708 case ARM::t2LDR_POST:
3709 Inst.setOpcode(ARM::t2LDRpci);
3711 case ARM::t2LDRB_PRE:
3712 case ARM::t2LDRB_POST:
3713 Inst.setOpcode(ARM::t2LDRBpci);
3715 case ARM::t2LDRH_PRE:
3716 case ARM::t2LDRH_POST:
3717 Inst.setOpcode(ARM::t2LDRHpci);
3719 case ARM::t2LDRSB_PRE:
3720 case ARM::t2LDRSB_POST:
3722 Inst.setOpcode(ARM::t2PLIpci);
3724 Inst.setOpcode(ARM::t2LDRSBpci);
3726 case ARM::t2LDRSH_PRE:
3727 case ARM::t2LDRSH_POST:
3728 Inst.setOpcode(ARM::t2LDRSHpci);
3731 return MCDisassembler::Fail;
3733 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
3737 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3738 return MCDisassembler::Fail;
3741 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3742 return MCDisassembler::Fail;
3745 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3746 return MCDisassembler::Fail;
3749 if (!Check(S, DecodeT2AddrModeImm8(Inst, addr, Address, Decoder)))
3750 return MCDisassembler::Fail;
3755 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val,
3756 uint64_t Address, const void *Decoder) {
3757 DecodeStatus S = MCDisassembler::Success;
3759 unsigned Rn = fieldFromInstruction(Val, 13, 4);
3760 unsigned imm = fieldFromInstruction(Val, 0, 12);
3762 // Thumb stores cannot use PC as dest register.
3763 switch (Inst.getOpcode()) {
3765 case ARM::t2STRBi12:
3766 case ARM::t2STRHi12:
3768 return MCDisassembler::Fail;
3773 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3774 return MCDisassembler::Fail;
3775 Inst.addOperand(MCOperand::CreateImm(imm));
3781 static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Insn,
3782 uint64_t Address, const void *Decoder) {
3783 unsigned imm = fieldFromInstruction(Insn, 0, 7);
3785 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3786 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3787 Inst.addOperand(MCOperand::CreateImm(imm));
3789 return MCDisassembler::Success;
3792 static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn,
3793 uint64_t Address, const void *Decoder) {
3794 DecodeStatus S = MCDisassembler::Success;
3796 if (Inst.getOpcode() == ARM::tADDrSP) {
3797 unsigned Rdm = fieldFromInstruction(Insn, 0, 3);
3798 Rdm |= fieldFromInstruction(Insn, 7, 1) << 3;
3800 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
3801 return MCDisassembler::Fail;
3802 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3803 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
3804 return MCDisassembler::Fail;
3805 } else if (Inst.getOpcode() == ARM::tADDspr) {
3806 unsigned Rm = fieldFromInstruction(Insn, 3, 4);
3808 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3809 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3810 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3811 return MCDisassembler::Fail;
3817 static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn,
3818 uint64_t Address, const void *Decoder) {
3819 unsigned imod = fieldFromInstruction(Insn, 4, 1) | 0x2;
3820 unsigned flags = fieldFromInstruction(Insn, 0, 3);
3822 Inst.addOperand(MCOperand::CreateImm(imod));
3823 Inst.addOperand(MCOperand::CreateImm(flags));
3825 return MCDisassembler::Success;
3828 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn,
3829 uint64_t Address, const void *Decoder) {
3830 DecodeStatus S = MCDisassembler::Success;
3831 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3832 unsigned add = fieldFromInstruction(Insn, 4, 1);
3834 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
3835 return MCDisassembler::Fail;
3836 Inst.addOperand(MCOperand::CreateImm(add));
3841 static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Val,
3842 uint64_t Address, const void *Decoder) {
3843 // Val is passed in as S:J1:J2:imm10H:imm10L:'0'
3844 // Note only one trailing zero not two. Also the J1 and J2 values are from
3845 // the encoded instruction. So here change to I1 and I2 values via:
3846 // I1 = NOT(J1 EOR S);
3847 // I2 = NOT(J2 EOR S);
3848 // and build the imm32 with two trailing zeros as documented:
3849 // imm32 = SignExtend(S:I1:I2:imm10H:imm10L:'00', 32);
3850 unsigned S = (Val >> 23) & 1;
3851 unsigned J1 = (Val >> 22) & 1;
3852 unsigned J2 = (Val >> 21) & 1;
3853 unsigned I1 = !(J1 ^ S);
3854 unsigned I2 = !(J2 ^ S);
3855 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21);
3856 int imm32 = SignExtend32<25>(tmp << 1);
3858 if (!tryAddingSymbolicOperand(Address,
3859 (Address & ~2u) + imm32 + 4,
3860 true, 4, Inst, Decoder))
3861 Inst.addOperand(MCOperand::CreateImm(imm32));
3862 return MCDisassembler::Success;
3865 static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Val,
3866 uint64_t Address, const void *Decoder) {
3867 if (Val == 0xA || Val == 0xB)
3868 return MCDisassembler::Fail;
3870 uint64_t featureBits = ((const MCDisassembler*)Decoder)->getSubtargetInfo()
3872 if ((featureBits & ARM::HasV8Ops) && !(Val == 14 || Val == 15))
3873 return MCDisassembler::Fail;
3875 Inst.addOperand(MCOperand::CreateImm(Val));
3876 return MCDisassembler::Success;
3880 DecodeThumbTableBranch(MCInst &Inst, unsigned Insn,
3881 uint64_t Address, const void *Decoder) {
3882 DecodeStatus S = MCDisassembler::Success;
3884 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3885 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3887 if (Rn == ARM::SP) S = MCDisassembler::SoftFail;
3888 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3889 return MCDisassembler::Fail;
3890 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
3891 return MCDisassembler::Fail;
3896 DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Insn,
3897 uint64_t Address, const void *Decoder) {
3898 DecodeStatus S = MCDisassembler::Success;
3900 unsigned pred = fieldFromInstruction(Insn, 22, 4);
3901 if (pred == 0xE || pred == 0xF) {
3902 unsigned opc = fieldFromInstruction(Insn, 4, 28);
3905 return MCDisassembler::Fail;
3907 Inst.setOpcode(ARM::t2DSB);
3910 Inst.setOpcode(ARM::t2DMB);
3913 Inst.setOpcode(ARM::t2ISB);
3917 unsigned imm = fieldFromInstruction(Insn, 0, 4);
3918 return DecodeMemBarrierOption(Inst, imm, Address, Decoder);
3921 unsigned brtarget = fieldFromInstruction(Insn, 0, 11) << 1;
3922 brtarget |= fieldFromInstruction(Insn, 11, 1) << 19;
3923 brtarget |= fieldFromInstruction(Insn, 13, 1) << 18;
3924 brtarget |= fieldFromInstruction(Insn, 16, 6) << 12;
3925 brtarget |= fieldFromInstruction(Insn, 26, 1) << 20;
3927 if (!Check(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder)))
3928 return MCDisassembler::Fail;
3929 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3930 return MCDisassembler::Fail;
3935 // Decode a shifted immediate operand. These basically consist
3936 // of an 8-bit value, and a 4-bit directive that specifies either
3937 // a splat operation or a rotation.
3938 static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val,
3939 uint64_t Address, const void *Decoder) {
3940 unsigned ctrl = fieldFromInstruction(Val, 10, 2);
3942 unsigned byte = fieldFromInstruction(Val, 8, 2);
3943 unsigned imm = fieldFromInstruction(Val, 0, 8);
3946 Inst.addOperand(MCOperand::CreateImm(imm));
3949 Inst.addOperand(MCOperand::CreateImm((imm << 16) | imm));
3952 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 8)));
3955 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 16) |
3960 unsigned unrot = fieldFromInstruction(Val, 0, 7) | 0x80;
3961 unsigned rot = fieldFromInstruction(Val, 7, 5);
3962 unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31));
3963 Inst.addOperand(MCOperand::CreateImm(imm));
3966 return MCDisassembler::Success;
3970 DecodeThumbBCCTargetOperand(MCInst &Inst, unsigned Val,
3971 uint64_t Address, const void *Decoder){
3972 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<9>(Val<<1) + 4,
3973 true, 2, Inst, Decoder))
3974 Inst.addOperand(MCOperand::CreateImm(SignExtend32<9>(Val << 1)));
3975 return MCDisassembler::Success;
3978 static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val,
3979 uint64_t Address, const void *Decoder){
3980 // Val is passed in as S:J1:J2:imm10:imm11
3981 // Note no trailing zero after imm11. Also the J1 and J2 values are from
3982 // the encoded instruction. So here change to I1 and I2 values via:
3983 // I1 = NOT(J1 EOR S);
3984 // I2 = NOT(J2 EOR S);
3985 // and build the imm32 with one trailing zero as documented:
3986 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32);
3987 unsigned S = (Val >> 23) & 1;
3988 unsigned J1 = (Val >> 22) & 1;
3989 unsigned J2 = (Val >> 21) & 1;
3990 unsigned I1 = !(J1 ^ S);
3991 unsigned I2 = !(J2 ^ S);
3992 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21);
3993 int imm32 = SignExtend32<25>(tmp << 1);
3995 if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4,
3996 true, 4, Inst, Decoder))
3997 Inst.addOperand(MCOperand::CreateImm(imm32));
3998 return MCDisassembler::Success;
4001 static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Val,
4002 uint64_t Address, const void *Decoder) {
4004 return MCDisassembler::Fail;
4006 Inst.addOperand(MCOperand::CreateImm(Val));
4007 return MCDisassembler::Success;
4010 static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Val,
4011 uint64_t Address, const void *Decoder) {
4013 return MCDisassembler::Fail;
4015 Inst.addOperand(MCOperand::CreateImm(Val));
4016 return MCDisassembler::Success;
4019 static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Val,
4020 uint64_t Address, const void *Decoder) {
4021 DecodeStatus S = MCDisassembler::Success;
4022 uint64_t FeatureBits = ((const MCDisassembler*)Decoder)->getSubtargetInfo()
4024 if (FeatureBits & ARM::FeatureMClass) {
4025 unsigned ValLow = Val & 0xff;
4027 // Validate the SYSm value first.
4042 case 18: // basepri_max
4043 case 19: // faultmask
4044 if (!(FeatureBits & ARM::HasV7Ops))
4045 // Values basepri, basepri_max and faultmask are only valid for v7m.
4046 return MCDisassembler::Fail;
4049 return MCDisassembler::Fail;
4052 if (Inst.getOpcode() == ARM::t2MSR_M) {
4053 unsigned Mask = fieldFromInstruction(Val, 10, 2);
4054 if (!(FeatureBits & ARM::HasV7Ops)) {
4055 // The ARMv6-M MSR bits {11-10} can be only 0b10, other values are
4058 S = MCDisassembler::SoftFail;
4061 // The ARMv7-M architecture stores an additional 2-bit mask value in
4062 // MSR bits {11-10}. The mask is used only with apsr, iapsr, eapsr and
4063 // xpsr, it has to be 0b10 in other cases. Bit mask{1} indicates if
4064 // the NZCVQ bits should be moved by the instruction. Bit mask{0}
4065 // indicates the move for the GE{3:0} bits, the mask{0} bit can be set
4066 // only if the processor includes the DSP extension.
4067 if (Mask == 0 || (Mask != 2 && ValLow > 3) ||
4068 (!(FeatureBits & ARM::FeatureDSPThumb2) && (Mask & 1)))
4069 S = MCDisassembler::SoftFail;
4075 return MCDisassembler::Fail;
4077 Inst.addOperand(MCOperand::CreateImm(Val));
4081 static DecodeStatus DecodeBankedReg(MCInst &Inst, unsigned Val,
4082 uint64_t Address, const void *Decoder) {
4084 unsigned R = fieldFromInstruction(Val, 5, 1);
4085 unsigned SysM = fieldFromInstruction(Val, 0, 5);
4087 // The table of encodings for these banked registers comes from B9.2.3 of the
4088 // ARM ARM. There are patterns, but nothing regular enough to make this logic
4089 // neater. So by fiat, these values are UNPREDICTABLE:
4091 if (SysM == 0x7 || SysM == 0xf || SysM == 0x18 || SysM == 0x19 ||
4092 SysM == 0x1a || SysM == 0x1b)
4093 return MCDisassembler::SoftFail;
4095 if (SysM != 0xe && SysM != 0x10 && SysM != 0x12 && SysM != 0x14 &&
4096 SysM != 0x16 && SysM != 0x1c && SysM != 0x1e)
4097 return MCDisassembler::SoftFail;
4100 Inst.addOperand(MCOperand::CreateImm(Val));
4101 return MCDisassembler::Success;
4104 static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn,
4105 uint64_t Address, const void *Decoder) {
4106 DecodeStatus S = MCDisassembler::Success;
4108 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4109 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4110 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4113 S = MCDisassembler::SoftFail;
4115 if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder)))
4116 return MCDisassembler::Fail;
4117 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4118 return MCDisassembler::Fail;
4119 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4120 return MCDisassembler::Fail;
4125 static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn,
4126 uint64_t Address, const void *Decoder){
4127 DecodeStatus S = MCDisassembler::Success;
4129 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4130 unsigned Rt = fieldFromInstruction(Insn, 0, 4);
4131 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4132 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4134 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
4135 return MCDisassembler::Fail;
4137 if (Rn == 0xF || Rd == Rn || Rd == Rt || Rd == Rt+1)
4138 S = MCDisassembler::SoftFail;
4140 if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder)))
4141 return MCDisassembler::Fail;
4142 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4143 return MCDisassembler::Fail;
4144 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4145 return MCDisassembler::Fail;
4150 static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn,
4151 uint64_t Address, const void *Decoder) {
4152 DecodeStatus S = MCDisassembler::Success;
4154 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4155 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4156 unsigned imm = fieldFromInstruction(Insn, 0, 12);
4157 imm |= fieldFromInstruction(Insn, 16, 4) << 13;
4158 imm |= fieldFromInstruction(Insn, 23, 1) << 12;
4159 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4161 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
4163 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
4164 return MCDisassembler::Fail;
4165 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4166 return MCDisassembler::Fail;
4167 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
4168 return MCDisassembler::Fail;
4169 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4170 return MCDisassembler::Fail;
4175 static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn,
4176 uint64_t Address, const void *Decoder) {
4177 DecodeStatus S = MCDisassembler::Success;
4179 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4180 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4181 unsigned imm = fieldFromInstruction(Insn, 0, 12);
4182 imm |= fieldFromInstruction(Insn, 16, 4) << 13;
4183 imm |= fieldFromInstruction(Insn, 23, 1) << 12;
4184 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4185 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4187 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
4188 if (Rm == 0xF) S = MCDisassembler::SoftFail;
4190 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
4191 return MCDisassembler::Fail;
4192 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4193 return MCDisassembler::Fail;
4194 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
4195 return MCDisassembler::Fail;
4196 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4197 return MCDisassembler::Fail;
4203 static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn,
4204 uint64_t Address, const void *Decoder) {
4205 DecodeStatus S = MCDisassembler::Success;
4207 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4208 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4209 unsigned imm = fieldFromInstruction(Insn, 0, 12);
4210 imm |= fieldFromInstruction(Insn, 16, 4) << 13;
4211 imm |= fieldFromInstruction(Insn, 23, 1) << 12;
4212 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4214 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
4216 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4217 return MCDisassembler::Fail;
4218 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
4219 return MCDisassembler::Fail;
4220 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
4221 return MCDisassembler::Fail;
4222 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4223 return MCDisassembler::Fail;
4228 static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn,
4229 uint64_t Address, const void *Decoder) {
4230 DecodeStatus S = MCDisassembler::Success;
4232 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4233 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4234 unsigned imm = fieldFromInstruction(Insn, 0, 12);
4235 imm |= fieldFromInstruction(Insn, 16, 4) << 13;
4236 imm |= fieldFromInstruction(Insn, 23, 1) << 12;
4237 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4239 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
4241 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4242 return MCDisassembler::Fail;
4243 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
4244 return MCDisassembler::Fail;
4245 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
4246 return MCDisassembler::Fail;
4247 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4248 return MCDisassembler::Fail;
4253 static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn,
4254 uint64_t Address, const void *Decoder) {
4255 DecodeStatus S = MCDisassembler::Success;
4257 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4258 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4259 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4260 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4261 unsigned size = fieldFromInstruction(Insn, 10, 2);
4267 return MCDisassembler::Fail;
4269 if (fieldFromInstruction(Insn, 4, 1))
4270 return MCDisassembler::Fail; // UNDEFINED
4271 index = fieldFromInstruction(Insn, 5, 3);
4274 if (fieldFromInstruction(Insn, 5, 1))
4275 return MCDisassembler::Fail; // UNDEFINED
4276 index = fieldFromInstruction(Insn, 6, 2);
4277 if (fieldFromInstruction(Insn, 4, 1))
4281 if (fieldFromInstruction(Insn, 6, 1))
4282 return MCDisassembler::Fail; // UNDEFINED
4283 index = fieldFromInstruction(Insn, 7, 1);
4285 switch (fieldFromInstruction(Insn, 4, 2)) {
4291 return MCDisassembler::Fail;
4296 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4297 return MCDisassembler::Fail;
4298 if (Rm != 0xF) { // Writeback
4299 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4300 return MCDisassembler::Fail;
4302 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4303 return MCDisassembler::Fail;
4304 Inst.addOperand(MCOperand::CreateImm(align));
4307 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4308 return MCDisassembler::Fail;
4310 Inst.addOperand(MCOperand::CreateReg(0));
4313 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4314 return MCDisassembler::Fail;
4315 Inst.addOperand(MCOperand::CreateImm(index));
4320 static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn,
4321 uint64_t Address, const void *Decoder) {
4322 DecodeStatus S = MCDisassembler::Success;
4324 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4325 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4326 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4327 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4328 unsigned size = fieldFromInstruction(Insn, 10, 2);
4334 return MCDisassembler::Fail;
4336 if (fieldFromInstruction(Insn, 4, 1))
4337 return MCDisassembler::Fail; // UNDEFINED
4338 index = fieldFromInstruction(Insn, 5, 3);
4341 if (fieldFromInstruction(Insn, 5, 1))
4342 return MCDisassembler::Fail; // UNDEFINED
4343 index = fieldFromInstruction(Insn, 6, 2);
4344 if (fieldFromInstruction(Insn, 4, 1))
4348 if (fieldFromInstruction(Insn, 6, 1))
4349 return MCDisassembler::Fail; // UNDEFINED
4350 index = fieldFromInstruction(Insn, 7, 1);
4352 switch (fieldFromInstruction(Insn, 4, 2)) {
4358 return MCDisassembler::Fail;
4363 if (Rm != 0xF) { // Writeback
4364 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4365 return MCDisassembler::Fail;
4367 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4368 return MCDisassembler::Fail;
4369 Inst.addOperand(MCOperand::CreateImm(align));
4372 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4373 return MCDisassembler::Fail;
4375 Inst.addOperand(MCOperand::CreateReg(0));
4378 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4379 return MCDisassembler::Fail;
4380 Inst.addOperand(MCOperand::CreateImm(index));
4386 static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn,
4387 uint64_t Address, const void *Decoder) {
4388 DecodeStatus S = MCDisassembler::Success;
4390 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4391 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4392 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4393 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4394 unsigned size = fieldFromInstruction(Insn, 10, 2);
4401 return MCDisassembler::Fail;
4403 index = fieldFromInstruction(Insn, 5, 3);
4404 if (fieldFromInstruction(Insn, 4, 1))
4408 index = fieldFromInstruction(Insn, 6, 2);
4409 if (fieldFromInstruction(Insn, 4, 1))
4411 if (fieldFromInstruction(Insn, 5, 1))
4415 if (fieldFromInstruction(Insn, 5, 1))
4416 return MCDisassembler::Fail; // UNDEFINED
4417 index = fieldFromInstruction(Insn, 7, 1);
4418 if (fieldFromInstruction(Insn, 4, 1) != 0)
4420 if (fieldFromInstruction(Insn, 6, 1))
4425 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4426 return MCDisassembler::Fail;
4427 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4428 return MCDisassembler::Fail;
4429 if (Rm != 0xF) { // Writeback
4430 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4431 return MCDisassembler::Fail;
4433 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4434 return MCDisassembler::Fail;
4435 Inst.addOperand(MCOperand::CreateImm(align));
4438 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4439 return MCDisassembler::Fail;
4441 Inst.addOperand(MCOperand::CreateReg(0));
4444 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4445 return MCDisassembler::Fail;
4446 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4447 return MCDisassembler::Fail;
4448 Inst.addOperand(MCOperand::CreateImm(index));
4453 static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn,
4454 uint64_t Address, const void *Decoder) {
4455 DecodeStatus S = MCDisassembler::Success;
4457 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4458 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4459 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4460 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4461 unsigned size = fieldFromInstruction(Insn, 10, 2);
4468 return MCDisassembler::Fail;
4470 index = fieldFromInstruction(Insn, 5, 3);
4471 if (fieldFromInstruction(Insn, 4, 1))
4475 index = fieldFromInstruction(Insn, 6, 2);
4476 if (fieldFromInstruction(Insn, 4, 1))
4478 if (fieldFromInstruction(Insn, 5, 1))
4482 if (fieldFromInstruction(Insn, 5, 1))
4483 return MCDisassembler::Fail; // UNDEFINED
4484 index = fieldFromInstruction(Insn, 7, 1);
4485 if (fieldFromInstruction(Insn, 4, 1) != 0)
4487 if (fieldFromInstruction(Insn, 6, 1))
4492 if (Rm != 0xF) { // Writeback
4493 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4494 return MCDisassembler::Fail;
4496 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4497 return MCDisassembler::Fail;
4498 Inst.addOperand(MCOperand::CreateImm(align));
4501 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4502 return MCDisassembler::Fail;
4504 Inst.addOperand(MCOperand::CreateReg(0));
4507 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4508 return MCDisassembler::Fail;
4509 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4510 return MCDisassembler::Fail;
4511 Inst.addOperand(MCOperand::CreateImm(index));
4517 static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn,
4518 uint64_t Address, const void *Decoder) {
4519 DecodeStatus S = MCDisassembler::Success;
4521 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4522 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4523 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4524 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4525 unsigned size = fieldFromInstruction(Insn, 10, 2);
4532 return MCDisassembler::Fail;
4534 if (fieldFromInstruction(Insn, 4, 1))
4535 return MCDisassembler::Fail; // UNDEFINED
4536 index = fieldFromInstruction(Insn, 5, 3);
4539 if (fieldFromInstruction(Insn, 4, 1))
4540 return MCDisassembler::Fail; // UNDEFINED
4541 index = fieldFromInstruction(Insn, 6, 2);
4542 if (fieldFromInstruction(Insn, 5, 1))
4546 if (fieldFromInstruction(Insn, 4, 2))
4547 return MCDisassembler::Fail; // UNDEFINED
4548 index = fieldFromInstruction(Insn, 7, 1);
4549 if (fieldFromInstruction(Insn, 6, 1))
4554 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4555 return MCDisassembler::Fail;
4556 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4557 return MCDisassembler::Fail;
4558 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4559 return MCDisassembler::Fail;
4561 if (Rm != 0xF) { // Writeback
4562 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4563 return MCDisassembler::Fail;
4565 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4566 return MCDisassembler::Fail;
4567 Inst.addOperand(MCOperand::CreateImm(align));
4570 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4571 return MCDisassembler::Fail;
4573 Inst.addOperand(MCOperand::CreateReg(0));
4576 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4577 return MCDisassembler::Fail;
4578 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4579 return MCDisassembler::Fail;
4580 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4581 return MCDisassembler::Fail;
4582 Inst.addOperand(MCOperand::CreateImm(index));
4587 static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn,
4588 uint64_t Address, const void *Decoder) {
4589 DecodeStatus S = MCDisassembler::Success;
4591 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4592 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4593 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4594 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4595 unsigned size = fieldFromInstruction(Insn, 10, 2);
4602 return MCDisassembler::Fail;
4604 if (fieldFromInstruction(Insn, 4, 1))
4605 return MCDisassembler::Fail; // UNDEFINED
4606 index = fieldFromInstruction(Insn, 5, 3);
4609 if (fieldFromInstruction(Insn, 4, 1))
4610 return MCDisassembler::Fail; // UNDEFINED
4611 index = fieldFromInstruction(Insn, 6, 2);
4612 if (fieldFromInstruction(Insn, 5, 1))
4616 if (fieldFromInstruction(Insn, 4, 2))
4617 return MCDisassembler::Fail; // UNDEFINED
4618 index = fieldFromInstruction(Insn, 7, 1);
4619 if (fieldFromInstruction(Insn, 6, 1))
4624 if (Rm != 0xF) { // Writeback
4625 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4626 return MCDisassembler::Fail;
4628 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4629 return MCDisassembler::Fail;
4630 Inst.addOperand(MCOperand::CreateImm(align));
4633 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4634 return MCDisassembler::Fail;
4636 Inst.addOperand(MCOperand::CreateReg(0));
4639 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4640 return MCDisassembler::Fail;
4641 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4642 return MCDisassembler::Fail;
4643 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4644 return MCDisassembler::Fail;
4645 Inst.addOperand(MCOperand::CreateImm(index));
4651 static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn,
4652 uint64_t Address, const void *Decoder) {
4653 DecodeStatus S = MCDisassembler::Success;
4655 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4656 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4657 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4658 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4659 unsigned size = fieldFromInstruction(Insn, 10, 2);
4666 return MCDisassembler::Fail;
4668 if (fieldFromInstruction(Insn, 4, 1))
4670 index = fieldFromInstruction(Insn, 5, 3);
4673 if (fieldFromInstruction(Insn, 4, 1))
4675 index = fieldFromInstruction(Insn, 6, 2);
4676 if (fieldFromInstruction(Insn, 5, 1))
4680 switch (fieldFromInstruction(Insn, 4, 2)) {
4684 return MCDisassembler::Fail;
4686 align = 4 << fieldFromInstruction(Insn, 4, 2); break;
4689 index = fieldFromInstruction(Insn, 7, 1);
4690 if (fieldFromInstruction(Insn, 6, 1))
4695 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4696 return MCDisassembler::Fail;
4697 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4698 return MCDisassembler::Fail;
4699 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4700 return MCDisassembler::Fail;
4701 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
4702 return MCDisassembler::Fail;
4704 if (Rm != 0xF) { // Writeback
4705 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4706 return MCDisassembler::Fail;
4708 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4709 return MCDisassembler::Fail;
4710 Inst.addOperand(MCOperand::CreateImm(align));
4713 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4714 return MCDisassembler::Fail;
4716 Inst.addOperand(MCOperand::CreateReg(0));
4719 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4720 return MCDisassembler::Fail;
4721 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4722 return MCDisassembler::Fail;
4723 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4724 return MCDisassembler::Fail;
4725 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
4726 return MCDisassembler::Fail;
4727 Inst.addOperand(MCOperand::CreateImm(index));
4732 static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn,
4733 uint64_t Address, const void *Decoder) {
4734 DecodeStatus S = MCDisassembler::Success;
4736 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4737 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4738 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4739 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4740 unsigned size = fieldFromInstruction(Insn, 10, 2);
4747 return MCDisassembler::Fail;
4749 if (fieldFromInstruction(Insn, 4, 1))
4751 index = fieldFromInstruction(Insn, 5, 3);
4754 if (fieldFromInstruction(Insn, 4, 1))
4756 index = fieldFromInstruction(Insn, 6, 2);
4757 if (fieldFromInstruction(Insn, 5, 1))
4761 switch (fieldFromInstruction(Insn, 4, 2)) {
4765 return MCDisassembler::Fail;
4767 align = 4 << fieldFromInstruction(Insn, 4, 2); break;
4770 index = fieldFromInstruction(Insn, 7, 1);
4771 if (fieldFromInstruction(Insn, 6, 1))
4776 if (Rm != 0xF) { // Writeback
4777 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4778 return MCDisassembler::Fail;
4780 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4781 return MCDisassembler::Fail;
4782 Inst.addOperand(MCOperand::CreateImm(align));
4785 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4786 return MCDisassembler::Fail;
4788 Inst.addOperand(MCOperand::CreateReg(0));
4791 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4792 return MCDisassembler::Fail;
4793 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4794 return MCDisassembler::Fail;
4795 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4796 return MCDisassembler::Fail;
4797 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
4798 return MCDisassembler::Fail;
4799 Inst.addOperand(MCOperand::CreateImm(index));
4804 static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn,
4805 uint64_t Address, const void *Decoder) {
4806 DecodeStatus S = MCDisassembler::Success;
4807 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4808 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4);
4809 unsigned Rm = fieldFromInstruction(Insn, 5, 1);
4810 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4811 Rm |= fieldFromInstruction(Insn, 0, 4) << 1;
4813 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
4814 S = MCDisassembler::SoftFail;
4816 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)))
4817 return MCDisassembler::Fail;
4818 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
4819 return MCDisassembler::Fail;
4820 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder)))
4821 return MCDisassembler::Fail;
4822 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
4823 return MCDisassembler::Fail;
4824 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4825 return MCDisassembler::Fail;
4830 static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn,
4831 uint64_t Address, const void *Decoder) {
4832 DecodeStatus S = MCDisassembler::Success;
4833 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4834 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4);
4835 unsigned Rm = fieldFromInstruction(Insn, 5, 1);
4836 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4837 Rm |= fieldFromInstruction(Insn, 0, 4) << 1;
4839 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
4840 S = MCDisassembler::SoftFail;
4842 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder)))
4843 return MCDisassembler::Fail;
4844 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
4845 return MCDisassembler::Fail;
4846 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)))
4847 return MCDisassembler::Fail;
4848 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
4849 return MCDisassembler::Fail;
4850 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4851 return MCDisassembler::Fail;
4856 static DecodeStatus DecodeIT(MCInst &Inst, unsigned Insn,
4857 uint64_t Address, const void *Decoder) {
4858 DecodeStatus S = MCDisassembler::Success;
4859 unsigned pred = fieldFromInstruction(Insn, 4, 4);
4860 unsigned mask = fieldFromInstruction(Insn, 0, 4);
4864 S = MCDisassembler::SoftFail;
4868 return MCDisassembler::Fail;
4870 Inst.addOperand(MCOperand::CreateImm(pred));
4871 Inst.addOperand(MCOperand::CreateImm(mask));
4876 DecodeT2LDRDPreInstruction(MCInst &Inst, unsigned Insn,
4877 uint64_t Address, const void *Decoder) {
4878 DecodeStatus S = MCDisassembler::Success;
4880 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4881 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4);
4882 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4883 unsigned addr = fieldFromInstruction(Insn, 0, 8);
4884 unsigned W = fieldFromInstruction(Insn, 21, 1);
4885 unsigned U = fieldFromInstruction(Insn, 23, 1);
4886 unsigned P = fieldFromInstruction(Insn, 24, 1);
4887 bool writeback = (W == 1) | (P == 0);
4889 addr |= (U << 8) | (Rn << 9);
4891 if (writeback && (Rn == Rt || Rn == Rt2))
4892 Check(S, MCDisassembler::SoftFail);
4894 Check(S, MCDisassembler::SoftFail);
4897 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
4898 return MCDisassembler::Fail;
4900 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
4901 return MCDisassembler::Fail;
4902 // Writeback operand
4903 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
4904 return MCDisassembler::Fail;
4906 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
4907 return MCDisassembler::Fail;
4913 DecodeT2STRDPreInstruction(MCInst &Inst, unsigned Insn,
4914 uint64_t Address, const void *Decoder) {
4915 DecodeStatus S = MCDisassembler::Success;
4917 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4918 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4);
4919 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4920 unsigned addr = fieldFromInstruction(Insn, 0, 8);
4921 unsigned W = fieldFromInstruction(Insn, 21, 1);
4922 unsigned U = fieldFromInstruction(Insn, 23, 1);
4923 unsigned P = fieldFromInstruction(Insn, 24, 1);
4924 bool writeback = (W == 1) | (P == 0);
4926 addr |= (U << 8) | (Rn << 9);
4928 if (writeback && (Rn == Rt || Rn == Rt2))
4929 Check(S, MCDisassembler::SoftFail);
4931 // Writeback operand
4932 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
4933 return MCDisassembler::Fail;
4935 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
4936 return MCDisassembler::Fail;
4938 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
4939 return MCDisassembler::Fail;
4941 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
4942 return MCDisassembler::Fail;
4947 static DecodeStatus DecodeT2Adr(MCInst &Inst, uint32_t Insn,
4948 uint64_t Address, const void *Decoder) {
4949 unsigned sign1 = fieldFromInstruction(Insn, 21, 1);
4950 unsigned sign2 = fieldFromInstruction(Insn, 23, 1);
4951 if (sign1 != sign2) return MCDisassembler::Fail;
4953 unsigned Val = fieldFromInstruction(Insn, 0, 8);
4954 Val |= fieldFromInstruction(Insn, 12, 3) << 8;
4955 Val |= fieldFromInstruction(Insn, 26, 1) << 11;
4957 Inst.addOperand(MCOperand::CreateImm(SignExtend32<13>(Val)));
4959 return MCDisassembler::Success;
4962 static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, uint32_t Val,
4964 const void *Decoder) {
4965 DecodeStatus S = MCDisassembler::Success;
4967 // Shift of "asr #32" is not allowed in Thumb2 mode.
4968 if (Val == 0x20) S = MCDisassembler::SoftFail;
4969 Inst.addOperand(MCOperand::CreateImm(Val));
4973 static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn,
4974 uint64_t Address, const void *Decoder) {
4975 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4976 unsigned Rt2 = fieldFromInstruction(Insn, 0, 4);
4977 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4978 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4981 return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
4983 DecodeStatus S = MCDisassembler::Success;
4985 if (Rt == Rn || Rn == Rt2)
4986 S = MCDisassembler::SoftFail;
4988 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
4989 return MCDisassembler::Fail;
4990 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder)))
4991 return MCDisassembler::Fail;
4992 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
4993 return MCDisassembler::Fail;
4994 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4995 return MCDisassembler::Fail;
5000 static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn,
5001 uint64_t Address, const void *Decoder) {
5002 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0);
5003 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4);
5004 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0);
5005 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4);
5006 unsigned imm = fieldFromInstruction(Insn, 16, 6);
5007 unsigned cmode = fieldFromInstruction(Insn, 8, 4);
5008 unsigned op = fieldFromInstruction(Insn, 5, 1);
5010 DecodeStatus S = MCDisassembler::Success;
5012 // VMOVv2f32 is ambiguous with these decodings.
5013 if (!(imm & 0x38) && cmode == 0xF) {
5014 if (op == 1) return MCDisassembler::Fail;
5015 Inst.setOpcode(ARM::VMOVv2f32);
5016 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder);
5019 if (!(imm & 0x20)) return MCDisassembler::Fail;
5021 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
5022 return MCDisassembler::Fail;
5023 if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder)))
5024 return MCDisassembler::Fail;
5025 Inst.addOperand(MCOperand::CreateImm(64 - imm));
5030 static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn,
5031 uint64_t Address, const void *Decoder) {
5032 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0);
5033 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4);
5034 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0);
5035 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4);
5036 unsigned imm = fieldFromInstruction(Insn, 16, 6);
5037 unsigned cmode = fieldFromInstruction(Insn, 8, 4);
5038 unsigned op = fieldFromInstruction(Insn, 5, 1);
5040 DecodeStatus S = MCDisassembler::Success;
5042 // VMOVv4f32 is ambiguous with these decodings.
5043 if (!(imm & 0x38) && cmode == 0xF) {
5044 if (op == 1) return MCDisassembler::Fail;
5045 Inst.setOpcode(ARM::VMOVv4f32);
5046 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder);
5049 if (!(imm & 0x20)) return MCDisassembler::Fail;
5051 if (!Check(S, DecodeQPRRegisterClass(Inst, Vd, Address, Decoder)))
5052 return MCDisassembler::Fail;
5053 if (!Check(S, DecodeQPRRegisterClass(Inst, Vm, Address, Decoder)))
5054 return MCDisassembler::Fail;
5055 Inst.addOperand(MCOperand::CreateImm(64 - imm));
5060 static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val,
5061 uint64_t Address, const void *Decoder) {
5062 DecodeStatus S = MCDisassembler::Success;
5064 unsigned Rn = fieldFromInstruction(Val, 16, 4);
5065 unsigned Rt = fieldFromInstruction(Val, 12, 4);
5066 unsigned Rm = fieldFromInstruction(Val, 0, 4);
5067 Rm |= (fieldFromInstruction(Val, 23, 1) << 4);
5068 unsigned Cond = fieldFromInstruction(Val, 28, 4);
5070 if (fieldFromInstruction(Val, 8, 4) != 0 || Rn == Rt)
5071 S = MCDisassembler::SoftFail;
5073 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
5074 return MCDisassembler::Fail;
5075 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
5076 return MCDisassembler::Fail;
5077 if (!Check(S, DecodeAddrMode7Operand(Inst, Rn, Address, Decoder)))
5078 return MCDisassembler::Fail;
5079 if (!Check(S, DecodePostIdxReg(Inst, Rm, Address, Decoder)))
5080 return MCDisassembler::Fail;
5081 if (!Check(S, DecodePredicateOperand(Inst, Cond, Address, Decoder)))
5082 return MCDisassembler::Fail;
5087 static DecodeStatus DecodeMRRC2(llvm::MCInst &Inst, unsigned Val,
5088 uint64_t Address, const void *Decoder) {
5090 DecodeStatus S = MCDisassembler::Success;
5092 unsigned CRm = fieldFromInstruction(Val, 0, 4);
5093 unsigned opc1 = fieldFromInstruction(Val, 4, 4);
5094 unsigned cop = fieldFromInstruction(Val, 8, 4);
5095 unsigned Rt = fieldFromInstruction(Val, 12, 4);
5096 unsigned Rt2 = fieldFromInstruction(Val, 16, 4);
5098 if ((cop & ~0x1) == 0xa)
5099 return MCDisassembler::Fail;
5102 S = MCDisassembler::SoftFail;
5104 Inst.addOperand(MCOperand::CreateImm(cop));
5105 Inst.addOperand(MCOperand::CreateImm(opc1));
5106 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
5107 return MCDisassembler::Fail;
5108 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder)))
5109 return MCDisassembler::Fail;
5110 Inst.addOperand(MCOperand::CreateImm(CRm));