1 //===-- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA --------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #define DEBUG_TYPE "arm-disassembler"
13 #include "ARMSubtarget.h"
14 #include "MCTargetDesc/ARMAddressingModes.h"
15 #include "MCTargetDesc/ARMMCExpr.h"
16 #include "MCTargetDesc/ARMBaseInfo.h"
17 #include "llvm/MC/EDInstInfo.h"
18 #include "llvm/MC/MCInst.h"
19 #include "llvm/MC/MCInstrDesc.h"
20 #include "llvm/MC/MCExpr.h"
21 #include "llvm/MC/MCContext.h"
22 #include "llvm/MC/MCDisassembler.h"
23 #include "llvm/Support/Debug.h"
24 #include "llvm/Support/MemoryObject.h"
25 #include "llvm/Support/ErrorHandling.h"
26 #include "llvm/Support/TargetRegistry.h"
27 #include "llvm/Support/raw_ostream.h"
31 typedef MCDisassembler::DecodeStatus DecodeStatus;
34 /// ARMDisassembler - ARM disassembler for all ARM platforms.
35 class ARMDisassembler : public MCDisassembler {
37 /// Constructor - Initializes the disassembler.
39 ARMDisassembler(const MCSubtargetInfo &STI) :
46 /// getInstruction - See MCDisassembler.
47 DecodeStatus getInstruction(MCInst &instr,
49 const MemoryObject ®ion,
52 raw_ostream &cStream) const;
54 /// getEDInfo - See MCDisassembler.
55 const EDInstInfo *getEDInfo() const;
59 /// ThumbDisassembler - Thumb disassembler for all Thumb platforms.
60 class ThumbDisassembler : public MCDisassembler {
62 /// Constructor - Initializes the disassembler.
64 ThumbDisassembler(const MCSubtargetInfo &STI) :
68 ~ThumbDisassembler() {
71 /// getInstruction - See MCDisassembler.
72 DecodeStatus getInstruction(MCInst &instr,
74 const MemoryObject ®ion,
77 raw_ostream &cStream) const;
79 /// getEDInfo - See MCDisassembler.
80 const EDInstInfo *getEDInfo() const;
82 mutable std::vector<unsigned> ITBlock;
83 DecodeStatus AddThumbPredicate(MCInst&) const;
84 void UpdateThumbVFPPredicate(MCInst&) const;
88 static bool Check(DecodeStatus &Out, DecodeStatus In) {
90 case MCDisassembler::Success:
91 // Out stays the same.
93 case MCDisassembler::SoftFail:
96 case MCDisassembler::Fail:
100 llvm_unreachable("Invalid DecodeStatus!");
104 // Forward declare these because the autogenerated code will reference them.
105 // Definitions are further down.
106 static DecodeStatus DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
107 uint64_t Address, const void *Decoder);
108 static DecodeStatus DecodeGPRnopcRegisterClass(llvm::MCInst &Inst,
109 unsigned RegNo, uint64_t Address,
110 const void *Decoder);
111 static DecodeStatus DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
112 uint64_t Address, const void *Decoder);
113 static DecodeStatus DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
114 uint64_t Address, const void *Decoder);
115 static DecodeStatus DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
116 uint64_t Address, const void *Decoder);
117 static DecodeStatus DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
118 uint64_t Address, const void *Decoder);
119 static DecodeStatus DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
120 uint64_t Address, const void *Decoder);
121 static DecodeStatus DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
122 uint64_t Address, const void *Decoder);
123 static DecodeStatus DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst,
126 const void *Decoder);
127 static DecodeStatus DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
128 uint64_t Address, const void *Decoder);
129 static DecodeStatus DecodeDPairRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
130 uint64_t Address, const void *Decoder);
131 static DecodeStatus DecodeDPairSpacedRegisterClass(llvm::MCInst &Inst,
132 unsigned RegNo, uint64_t Address,
133 const void *Decoder);
135 static DecodeStatus DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val,
136 uint64_t Address, const void *Decoder);
137 static DecodeStatus DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val,
138 uint64_t Address, const void *Decoder);
139 static DecodeStatus DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val,
140 uint64_t Address, const void *Decoder);
141 static DecodeStatus DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val,
142 uint64_t Address, const void *Decoder);
143 static DecodeStatus DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned Val,
144 uint64_t Address, const void *Decoder);
145 static DecodeStatus DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned Val,
146 uint64_t Address, const void *Decoder);
148 static DecodeStatus DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Insn,
149 uint64_t Address, const void *Decoder);
150 static DecodeStatus DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn,
151 uint64_t Address, const void *Decoder);
152 static DecodeStatus DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst,
155 const void *Decoder);
156 static DecodeStatus DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Insn,
157 uint64_t Address, const void *Decoder);
158 static DecodeStatus DecodeAddrMode3Instruction(llvm::MCInst &Inst,unsigned Insn,
159 uint64_t Address, const void *Decoder);
160 static DecodeStatus DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Insn,
161 uint64_t Address, const void *Decoder);
162 static DecodeStatus DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Insn,
163 uint64_t Address, const void *Decoder);
165 static DecodeStatus DecodeMemMultipleWritebackInstruction(llvm::MCInst & Inst,
168 const void *Decoder);
169 static DecodeStatus DecodeT2MOVTWInstruction(llvm::MCInst &Inst, unsigned Insn,
170 uint64_t Address, const void *Decoder);
171 static DecodeStatus DecodeArmMOVTWInstruction(llvm::MCInst &Inst, unsigned Insn,
172 uint64_t Address, const void *Decoder);
173 static DecodeStatus DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn,
174 uint64_t Address, const void *Decoder);
175 static DecodeStatus DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn,
176 uint64_t Address, const void *Decoder);
177 static DecodeStatus DecodeT2CPSInstruction(llvm::MCInst &Inst, unsigned Insn,
178 uint64_t Address, const void *Decoder);
179 static DecodeStatus DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val,
180 uint64_t Address, const void *Decoder);
181 static DecodeStatus DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val,
182 uint64_t Address, const void *Decoder);
183 static DecodeStatus DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val,
184 uint64_t Address, const void *Decoder);
185 static DecodeStatus DecodeBranchImmInstruction(llvm::MCInst &Inst,unsigned Insn,
186 uint64_t Address, const void *Decoder);
187 static DecodeStatus DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val,
188 uint64_t Address, const void *Decoder);
189 static DecodeStatus DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Val,
190 uint64_t Address, const void *Decoder);
191 static DecodeStatus DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Val,
192 uint64_t Address, const void *Decoder);
193 static DecodeStatus DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Val,
194 uint64_t Address, const void *Decoder);
195 static DecodeStatus DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Val,
196 uint64_t Address, const void *Decoder);
197 static DecodeStatus DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Val,
198 uint64_t Address, const void *Decoder);
199 static DecodeStatus DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Val,
200 uint64_t Address, const void *Decoder);
201 static DecodeStatus DecodeNEONModImmInstruction(llvm::MCInst &Inst,unsigned Val,
202 uint64_t Address, const void *Decoder);
203 static DecodeStatus DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned Val,
204 uint64_t Address, const void *Decoder);
205 static DecodeStatus DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned Val,
206 uint64_t Address, const void *Decoder);
207 static DecodeStatus DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned Val,
208 uint64_t Address, const void *Decoder);
209 static DecodeStatus DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned Val,
210 uint64_t Address, const void *Decoder);
211 static DecodeStatus DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned Val,
212 uint64_t Address, const void *Decoder);
213 static DecodeStatus DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn,
214 uint64_t Address, const void *Decoder);
215 static DecodeStatus DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn,
216 uint64_t Address, const void *Decoder);
217 static DecodeStatus DecodeCoprocessor(llvm::MCInst &Inst, unsigned Insn,
218 uint64_t Address, const void *Decoder);
219 static DecodeStatus DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Insn,
220 uint64_t Address, const void *Decoder);
221 static DecodeStatus DecodeMSRMask(llvm::MCInst &Inst, unsigned Insn,
222 uint64_t Address, const void *Decoder);
223 static DecodeStatus DecodeDoubleRegLoad(llvm::MCInst &Inst, unsigned Insn,
224 uint64_t Address, const void *Decoder);
225 static DecodeStatus DecodeDoubleRegStore(llvm::MCInst &Inst, unsigned Insn,
226 uint64_t Address, const void *Decoder);
227 static DecodeStatus DecodeLDRPreImm(llvm::MCInst &Inst, unsigned Insn,
228 uint64_t Address, const void *Decoder);
229 static DecodeStatus DecodeLDRPreReg(llvm::MCInst &Inst, unsigned Insn,
230 uint64_t Address, const void *Decoder);
231 static DecodeStatus DecodeSTRPreImm(llvm::MCInst &Inst, unsigned Insn,
232 uint64_t Address, const void *Decoder);
233 static DecodeStatus DecodeSTRPreReg(llvm::MCInst &Inst, unsigned Insn,
234 uint64_t Address, const void *Decoder);
235 static DecodeStatus DecodeVLD1LN(llvm::MCInst &Inst, unsigned Insn,
236 uint64_t Address, const void *Decoder);
237 static DecodeStatus DecodeVLD2LN(llvm::MCInst &Inst, unsigned Insn,
238 uint64_t Address, const void *Decoder);
239 static DecodeStatus DecodeVLD3LN(llvm::MCInst &Inst, unsigned Insn,
240 uint64_t Address, const void *Decoder);
241 static DecodeStatus DecodeVLD4LN(llvm::MCInst &Inst, unsigned Insn,
242 uint64_t Address, const void *Decoder);
243 static DecodeStatus DecodeVST1LN(llvm::MCInst &Inst, unsigned Insn,
244 uint64_t Address, const void *Decoder);
245 static DecodeStatus DecodeVST2LN(llvm::MCInst &Inst, unsigned Insn,
246 uint64_t Address, const void *Decoder);
247 static DecodeStatus DecodeVST3LN(llvm::MCInst &Inst, unsigned Insn,
248 uint64_t Address, const void *Decoder);
249 static DecodeStatus DecodeVST4LN(llvm::MCInst &Inst, unsigned Insn,
250 uint64_t Address, const void *Decoder);
251 static DecodeStatus DecodeVMOVSRR(llvm::MCInst &Inst, unsigned Insn,
252 uint64_t Address, const void *Decoder);
253 static DecodeStatus DecodeVMOVRRS(llvm::MCInst &Inst, unsigned Insn,
254 uint64_t Address, const void *Decoder);
255 static DecodeStatus DecodeSwap(llvm::MCInst &Inst, unsigned Insn,
256 uint64_t Address, const void *Decoder);
257 static DecodeStatus DecodeVCVTD(llvm::MCInst &Inst, unsigned Insn,
258 uint64_t Address, const void *Decoder);
259 static DecodeStatus DecodeVCVTQ(llvm::MCInst &Inst, unsigned Insn,
260 uint64_t Address, const void *Decoder);
263 static DecodeStatus DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn,
264 uint64_t Address, const void *Decoder);
265 static DecodeStatus DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val,
266 uint64_t Address, const void *Decoder);
267 static DecodeStatus DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val,
268 uint64_t Address, const void *Decoder);
269 static DecodeStatus DecodeThumbCmpBROperand(llvm::MCInst &Inst, unsigned Val,
270 uint64_t Address, const void *Decoder);
271 static DecodeStatus DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned Val,
272 uint64_t Address, const void *Decoder);
273 static DecodeStatus DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned Val,
274 uint64_t Address, const void *Decoder);
275 static DecodeStatus DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned Val,
276 uint64_t Address, const void *Decoder);
277 static DecodeStatus DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val,
278 uint64_t Address, const void *Decoder);
279 static DecodeStatus DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned Val,
280 uint64_t Address, const void *Decoder);
281 static DecodeStatus DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Val,
282 uint64_t Address, const void *Decoder);
283 static DecodeStatus DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val,
284 uint64_t Address, const void *Decoder);
285 static DecodeStatus DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned Val,
286 uint64_t Address, const void *Decoder);
287 static DecodeStatus DecodeT2AddrModeImm0_1020s4(llvm::MCInst &Inst,unsigned Val,
288 uint64_t Address, const void *Decoder);
289 static DecodeStatus DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val,
290 uint64_t Address, const void *Decoder);
291 static DecodeStatus DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val,
292 uint64_t Address, const void *Decoder);
293 static DecodeStatus DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Val,
294 uint64_t Address, const void *Decoder);
295 static DecodeStatus DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn,
296 uint64_t Address, const void *Decoder);
297 static DecodeStatus DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn,
298 uint64_t Address, const void *Decoder);
299 static DecodeStatus DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Insn,
300 uint64_t Address, const void *Decoder);
301 static DecodeStatus DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val,
302 uint64_t Address, const void *Decoder);
303 static DecodeStatus DecodeThumbTableBranch(llvm::MCInst &Inst, unsigned Val,
304 uint64_t Address, const void *Decoder);
305 static DecodeStatus DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Val,
306 uint64_t Address, const void *Decoder);
307 static DecodeStatus DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val,
308 uint64_t Address, const void *Decoder);
309 static DecodeStatus DecodeThumbBCCTargetOperand(llvm::MCInst &Inst,unsigned Val,
310 uint64_t Address, const void *Decoder);
311 static DecodeStatus DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val,
312 uint64_t Address, const void *Decoder);
313 static DecodeStatus DecodeIT(llvm::MCInst &Inst, unsigned Val,
314 uint64_t Address, const void *Decoder);
315 static DecodeStatus DecodeT2LDRDPreInstruction(llvm::MCInst &Inst,unsigned Insn,
316 uint64_t Address, const void *Decoder);
317 static DecodeStatus DecodeT2STRDPreInstruction(llvm::MCInst &Inst,unsigned Insn,
318 uint64_t Address, const void *Decoder);
319 static DecodeStatus DecodeT2Adr(llvm::MCInst &Inst, unsigned Val,
320 uint64_t Address, const void *Decoder);
321 static DecodeStatus DecodeT2LdStPre(llvm::MCInst &Inst, unsigned Val,
322 uint64_t Address, const void *Decoder);
323 static DecodeStatus DecodeT2ShifterImmOperand(llvm::MCInst &Inst, unsigned Val,
324 uint64_t Address, const void *Decoder);
328 #include "ARMGenDisassemblerTables.inc"
329 #include "ARMGenInstrInfo.inc"
330 #include "ARMGenEDInfo.inc"
332 static MCDisassembler *createARMDisassembler(const Target &T, const MCSubtargetInfo &STI) {
333 return new ARMDisassembler(STI);
336 static MCDisassembler *createThumbDisassembler(const Target &T, const MCSubtargetInfo &STI) {
337 return new ThumbDisassembler(STI);
340 const EDInstInfo *ARMDisassembler::getEDInfo() const {
344 const EDInstInfo *ThumbDisassembler::getEDInfo() const {
348 DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
349 const MemoryObject &Region,
352 raw_ostream &cs) const {
357 assert(!(STI.getFeatureBits() & ARM::ModeThumb) &&
358 "Asked to disassemble an ARM instruction but Subtarget is in Thumb mode!");
360 // We want to read exactly 4 bytes of data.
361 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) {
363 return MCDisassembler::Fail;
366 // Encoded as a small-endian 32-bit word in the stream.
367 uint32_t insn = (bytes[3] << 24) |
372 // Calling the auto-generated decoder function.
373 DecodeStatus result = decodeARMInstruction32(MI, insn, Address, this, STI);
374 if (result != MCDisassembler::Fail) {
379 // VFP and NEON instructions, similarly, are shared between ARM
382 result = decodeVFPInstruction32(MI, insn, Address, this, STI);
383 if (result != MCDisassembler::Fail) {
389 result = decodeNEONDataInstruction32(MI, insn, Address, this, STI);
390 if (result != MCDisassembler::Fail) {
392 // Add a fake predicate operand, because we share these instruction
393 // definitions with Thumb2 where these instructions are predicable.
394 if (!DecodePredicateOperand(MI, 0xE, Address, this))
395 return MCDisassembler::Fail;
400 result = decodeNEONLoadStoreInstruction32(MI, insn, Address, this, STI);
401 if (result != MCDisassembler::Fail) {
403 // Add a fake predicate operand, because we share these instruction
404 // definitions with Thumb2 where these instructions are predicable.
405 if (!DecodePredicateOperand(MI, 0xE, Address, this))
406 return MCDisassembler::Fail;
411 result = decodeNEONDupInstruction32(MI, insn, Address, this, STI);
412 if (result != MCDisassembler::Fail) {
414 // Add a fake predicate operand, because we share these instruction
415 // definitions with Thumb2 where these instructions are predicable.
416 if (!DecodePredicateOperand(MI, 0xE, Address, this))
417 return MCDisassembler::Fail;
424 return MCDisassembler::Fail;
428 extern const MCInstrDesc ARMInsts[];
431 /// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the
432 /// immediate Value in the MCInst. The immediate Value has had any PC
433 /// adjustment made by the caller. If the instruction is a branch instruction
434 /// then isBranch is true, else false. If the getOpInfo() function was set as
435 /// part of the setupForSymbolicDisassembly() call then that function is called
436 /// to get any symbolic information at the Address for this instruction. If
437 /// that returns non-zero then the symbolic information it returns is used to
438 /// create an MCExpr and that is added as an operand to the MCInst. If
439 /// getOpInfo() returns zero and isBranch is true then a symbol look up for
440 /// Value is done and if a symbol is found an MCExpr is created with that, else
441 /// an MCExpr with Value is created. This function returns true if it adds an
442 /// operand to the MCInst and false otherwise.
443 static bool tryAddingSymbolicOperand(uint64_t Address, int32_t Value,
444 bool isBranch, uint64_t InstSize,
445 MCInst &MI, const void *Decoder) {
446 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
447 LLVMOpInfoCallback getOpInfo = Dis->getLLVMOpInfoCallback();
448 struct LLVMOpInfo1 SymbolicOp;
449 memset(&SymbolicOp, '\0', sizeof(struct LLVMOpInfo1));
450 SymbolicOp.Value = Value;
451 void *DisInfo = Dis->getDisInfoBlock();
454 !getOpInfo(DisInfo, Address, 0 /* Offset */, InstSize, 1, &SymbolicOp)) {
455 // Clear SymbolicOp.Value from above and also all other fields.
456 memset(&SymbolicOp, '\0', sizeof(struct LLVMOpInfo1));
457 LLVMSymbolLookupCallback SymbolLookUp = Dis->getLLVMSymbolLookupCallback();
460 uint64_t ReferenceType;
462 ReferenceType = LLVMDisassembler_ReferenceType_In_Branch;
464 ReferenceType = LLVMDisassembler_ReferenceType_InOut_None;
465 const char *ReferenceName;
466 const char *Name = SymbolLookUp(DisInfo, Value, &ReferenceType, Address,
469 SymbolicOp.AddSymbol.Name = Name;
470 SymbolicOp.AddSymbol.Present = true;
472 // For branches always create an MCExpr so it gets printed as hex address.
474 SymbolicOp.Value = Value;
476 if(ReferenceType == LLVMDisassembler_ReferenceType_Out_SymbolStub)
477 (*Dis->CommentStream) << "symbol stub for: " << ReferenceName;
478 if (!Name && !isBranch)
482 MCContext *Ctx = Dis->getMCContext();
483 const MCExpr *Add = NULL;
484 if (SymbolicOp.AddSymbol.Present) {
485 if (SymbolicOp.AddSymbol.Name) {
486 StringRef Name(SymbolicOp.AddSymbol.Name);
487 MCSymbol *Sym = Ctx->GetOrCreateSymbol(Name);
488 Add = MCSymbolRefExpr::Create(Sym, *Ctx);
490 Add = MCConstantExpr::Create(SymbolicOp.AddSymbol.Value, *Ctx);
494 const MCExpr *Sub = NULL;
495 if (SymbolicOp.SubtractSymbol.Present) {
496 if (SymbolicOp.SubtractSymbol.Name) {
497 StringRef Name(SymbolicOp.SubtractSymbol.Name);
498 MCSymbol *Sym = Ctx->GetOrCreateSymbol(Name);
499 Sub = MCSymbolRefExpr::Create(Sym, *Ctx);
501 Sub = MCConstantExpr::Create(SymbolicOp.SubtractSymbol.Value, *Ctx);
505 const MCExpr *Off = NULL;
506 if (SymbolicOp.Value != 0)
507 Off = MCConstantExpr::Create(SymbolicOp.Value, *Ctx);
513 LHS = MCBinaryExpr::CreateSub(Add, Sub, *Ctx);
515 LHS = MCUnaryExpr::CreateMinus(Sub, *Ctx);
517 Expr = MCBinaryExpr::CreateAdd(LHS, Off, *Ctx);
522 Expr = MCBinaryExpr::CreateAdd(Add, Off, *Ctx);
529 Expr = MCConstantExpr::Create(0, *Ctx);
532 if (SymbolicOp.VariantKind == LLVMDisassembler_VariantKind_ARM_HI16)
533 MI.addOperand(MCOperand::CreateExpr(ARMMCExpr::CreateUpper16(Expr, *Ctx)));
534 else if (SymbolicOp.VariantKind == LLVMDisassembler_VariantKind_ARM_LO16)
535 MI.addOperand(MCOperand::CreateExpr(ARMMCExpr::CreateLower16(Expr, *Ctx)));
536 else if (SymbolicOp.VariantKind == LLVMDisassembler_VariantKind_None)
537 MI.addOperand(MCOperand::CreateExpr(Expr));
539 llvm_unreachable("bad SymbolicOp.VariantKind");
544 /// tryAddingPcLoadReferenceComment - trys to add a comment as to what is being
545 /// referenced by a load instruction with the base register that is the Pc.
546 /// These can often be values in a literal pool near the Address of the
547 /// instruction. The Address of the instruction and its immediate Value are
548 /// used as a possible literal pool entry. The SymbolLookUp call back will
549 /// return the name of a symbol referenced by the the literal pool's entry if
550 /// the referenced address is that of a symbol. Or it will return a pointer to
551 /// a literal 'C' string if the referenced address of the literal pool's entry
552 /// is an address into a section with 'C' string literals.
553 static void tryAddingPcLoadReferenceComment(uint64_t Address, int Value,
554 const void *Decoder) {
555 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
556 LLVMSymbolLookupCallback SymbolLookUp = Dis->getLLVMSymbolLookupCallback();
558 void *DisInfo = Dis->getDisInfoBlock();
559 uint64_t ReferenceType;
560 ReferenceType = LLVMDisassembler_ReferenceType_In_PCrel_Load;
561 const char *ReferenceName;
562 (void)SymbolLookUp(DisInfo, Value, &ReferenceType, Address, &ReferenceName);
563 if(ReferenceType == LLVMDisassembler_ReferenceType_Out_LitPool_SymAddr ||
564 ReferenceType == LLVMDisassembler_ReferenceType_Out_LitPool_CstrAddr)
565 (*Dis->CommentStream) << "literal pool for: " << ReferenceName;
569 // Thumb1 instructions don't have explicit S bits. Rather, they
570 // implicitly set CPSR. Since it's not represented in the encoding, the
571 // auto-generated decoder won't inject the CPSR operand. We need to fix
572 // that as a post-pass.
573 static void AddThumb1SBit(MCInst &MI, bool InITBlock) {
574 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
575 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
576 MCInst::iterator I = MI.begin();
577 for (unsigned i = 0; i < NumOps; ++i, ++I) {
578 if (I == MI.end()) break;
579 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) {
580 if (i > 0 && OpInfo[i-1].isPredicate()) continue;
581 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR));
586 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR));
589 // Most Thumb instructions don't have explicit predicates in the
590 // encoding, but rather get their predicates from IT context. We need
591 // to fix up the predicate operands using this context information as a
593 MCDisassembler::DecodeStatus
594 ThumbDisassembler::AddThumbPredicate(MCInst &MI) const {
595 MCDisassembler::DecodeStatus S = Success;
597 // A few instructions actually have predicates encoded in them. Don't
598 // try to overwrite it if we're seeing one of those.
599 switch (MI.getOpcode()) {
610 // Some instructions (mostly conditional branches) are not
611 // allowed in IT blocks.
612 if (!ITBlock.empty())
621 // Some instructions (mostly unconditional branches) can
622 // only appears at the end of, or outside of, an IT.
623 if (ITBlock.size() > 1)
630 // If we're in an IT block, base the predicate on that. Otherwise,
631 // assume a predicate of AL.
633 if (!ITBlock.empty()) {
641 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
642 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
643 MCInst::iterator I = MI.begin();
644 for (unsigned i = 0; i < NumOps; ++i, ++I) {
645 if (I == MI.end()) break;
646 if (OpInfo[i].isPredicate()) {
647 I = MI.insert(I, MCOperand::CreateImm(CC));
650 MI.insert(I, MCOperand::CreateReg(0));
652 MI.insert(I, MCOperand::CreateReg(ARM::CPSR));
657 I = MI.insert(I, MCOperand::CreateImm(CC));
660 MI.insert(I, MCOperand::CreateReg(0));
662 MI.insert(I, MCOperand::CreateReg(ARM::CPSR));
667 // Thumb VFP instructions are a special case. Because we share their
668 // encodings between ARM and Thumb modes, and they are predicable in ARM
669 // mode, the auto-generated decoder will give them an (incorrect)
670 // predicate operand. We need to rewrite these operands based on the IT
671 // context as a post-pass.
672 void ThumbDisassembler::UpdateThumbVFPPredicate(MCInst &MI) const {
674 if (!ITBlock.empty()) {
680 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
681 MCInst::iterator I = MI.begin();
682 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
683 for (unsigned i = 0; i < NumOps; ++i, ++I) {
684 if (OpInfo[i].isPredicate() ) {
690 I->setReg(ARM::CPSR);
696 DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
697 const MemoryObject &Region,
700 raw_ostream &cs) const {
705 assert((STI.getFeatureBits() & ARM::ModeThumb) &&
706 "Asked to disassemble in Thumb mode but Subtarget is in ARM mode!");
708 // We want to read exactly 2 bytes of data.
709 if (Region.readBytes(Address, 2, (uint8_t*)bytes, NULL) == -1) {
711 return MCDisassembler::Fail;
714 uint16_t insn16 = (bytes[1] << 8) | bytes[0];
715 DecodeStatus result = decodeThumbInstruction16(MI, insn16, Address, this, STI);
716 if (result != MCDisassembler::Fail) {
718 Check(result, AddThumbPredicate(MI));
723 result = decodeThumbSBitInstruction16(MI, insn16, Address, this, STI);
726 bool InITBlock = !ITBlock.empty();
727 Check(result, AddThumbPredicate(MI));
728 AddThumb1SBit(MI, InITBlock);
733 result = decodeThumb2Instruction16(MI, insn16, Address, this, STI);
734 if (result != MCDisassembler::Fail) {
737 // Nested IT blocks are UNPREDICTABLE. Must be checked before we add
738 // the Thumb predicate.
739 if (MI.getOpcode() == ARM::t2IT && !ITBlock.empty())
740 result = MCDisassembler::SoftFail;
742 Check(result, AddThumbPredicate(MI));
744 // If we find an IT instruction, we need to parse its condition
745 // code and mask operands so that we can apply them correctly
746 // to the subsequent instructions.
747 if (MI.getOpcode() == ARM::t2IT) {
749 // (3 - the number of trailing zeros) is the number of then / else.
750 unsigned firstcond = MI.getOperand(0).getImm();
751 unsigned Mask = MI.getOperand(1).getImm();
752 unsigned CondBit0 = Mask >> 4 & 1;
753 unsigned NumTZ = CountTrailingZeros_32(Mask);
754 assert(NumTZ <= 3 && "Invalid IT mask!");
755 for (unsigned Pos = 3, e = NumTZ; Pos > e; --Pos) {
756 bool T = ((Mask >> Pos) & 1) == CondBit0;
758 ITBlock.insert(ITBlock.begin(), firstcond);
760 ITBlock.insert(ITBlock.begin(), firstcond ^ 1);
763 ITBlock.push_back(firstcond);
769 // We want to read exactly 4 bytes of data.
770 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) {
772 return MCDisassembler::Fail;
775 uint32_t insn32 = (bytes[3] << 8) |
780 result = decodeThumbInstruction32(MI, insn32, Address, this, STI);
781 if (result != MCDisassembler::Fail) {
783 bool InITBlock = ITBlock.size();
784 Check(result, AddThumbPredicate(MI));
785 AddThumb1SBit(MI, InITBlock);
790 result = decodeThumb2Instruction32(MI, insn32, Address, this, STI);
791 if (result != MCDisassembler::Fail) {
793 Check(result, AddThumbPredicate(MI));
798 result = decodeVFPInstruction32(MI, insn32, Address, this, STI);
799 if (result != MCDisassembler::Fail) {
801 UpdateThumbVFPPredicate(MI);
806 result = decodeNEONDupInstruction32(MI, insn32, Address, this, STI);
807 if (result != MCDisassembler::Fail) {
809 Check(result, AddThumbPredicate(MI));
813 if (fieldFromInstruction32(insn32, 24, 8) == 0xF9) {
815 uint32_t NEONLdStInsn = insn32;
816 NEONLdStInsn &= 0xF0FFFFFF;
817 NEONLdStInsn |= 0x04000000;
818 result = decodeNEONLoadStoreInstruction32(MI, NEONLdStInsn, Address, this, STI);
819 if (result != MCDisassembler::Fail) {
821 Check(result, AddThumbPredicate(MI));
826 if (fieldFromInstruction32(insn32, 24, 4) == 0xF) {
828 uint32_t NEONDataInsn = insn32;
829 NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24
830 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24
831 NEONDataInsn |= 0x12000000; // Set bits 28 and 25
832 result = decodeNEONDataInstruction32(MI, NEONDataInsn, Address, this, STI);
833 if (result != MCDisassembler::Fail) {
835 Check(result, AddThumbPredicate(MI));
841 return MCDisassembler::Fail;
845 extern "C" void LLVMInitializeARMDisassembler() {
846 TargetRegistry::RegisterMCDisassembler(TheARMTarget,
847 createARMDisassembler);
848 TargetRegistry::RegisterMCDisassembler(TheThumbTarget,
849 createThumbDisassembler);
852 static const uint16_t GPRDecoderTable[] = {
853 ARM::R0, ARM::R1, ARM::R2, ARM::R3,
854 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
855 ARM::R8, ARM::R9, ARM::R10, ARM::R11,
856 ARM::R12, ARM::SP, ARM::LR, ARM::PC
859 static DecodeStatus DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
860 uint64_t Address, const void *Decoder) {
862 return MCDisassembler::Fail;
864 unsigned Register = GPRDecoderTable[RegNo];
865 Inst.addOperand(MCOperand::CreateReg(Register));
866 return MCDisassembler::Success;
870 DecodeGPRnopcRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
871 uint64_t Address, const void *Decoder) {
872 DecodeStatus S = MCDisassembler::Success;
875 S = MCDisassembler::SoftFail;
877 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
882 static DecodeStatus DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
883 uint64_t Address, const void *Decoder) {
885 return MCDisassembler::Fail;
886 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
889 static DecodeStatus DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
890 uint64_t Address, const void *Decoder) {
891 unsigned Register = 0;
912 return MCDisassembler::Fail;
915 Inst.addOperand(MCOperand::CreateReg(Register));
916 return MCDisassembler::Success;
919 static DecodeStatus DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
920 uint64_t Address, const void *Decoder) {
921 if (RegNo == 13 || RegNo == 15) return MCDisassembler::Fail;
922 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
925 static const uint16_t SPRDecoderTable[] = {
926 ARM::S0, ARM::S1, ARM::S2, ARM::S3,
927 ARM::S4, ARM::S5, ARM::S6, ARM::S7,
928 ARM::S8, ARM::S9, ARM::S10, ARM::S11,
929 ARM::S12, ARM::S13, ARM::S14, ARM::S15,
930 ARM::S16, ARM::S17, ARM::S18, ARM::S19,
931 ARM::S20, ARM::S21, ARM::S22, ARM::S23,
932 ARM::S24, ARM::S25, ARM::S26, ARM::S27,
933 ARM::S28, ARM::S29, ARM::S30, ARM::S31
936 static DecodeStatus DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
937 uint64_t Address, const void *Decoder) {
939 return MCDisassembler::Fail;
941 unsigned Register = SPRDecoderTable[RegNo];
942 Inst.addOperand(MCOperand::CreateReg(Register));
943 return MCDisassembler::Success;
946 static const uint16_t DPRDecoderTable[] = {
947 ARM::D0, ARM::D1, ARM::D2, ARM::D3,
948 ARM::D4, ARM::D5, ARM::D6, ARM::D7,
949 ARM::D8, ARM::D9, ARM::D10, ARM::D11,
950 ARM::D12, ARM::D13, ARM::D14, ARM::D15,
951 ARM::D16, ARM::D17, ARM::D18, ARM::D19,
952 ARM::D20, ARM::D21, ARM::D22, ARM::D23,
953 ARM::D24, ARM::D25, ARM::D26, ARM::D27,
954 ARM::D28, ARM::D29, ARM::D30, ARM::D31
957 static DecodeStatus DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
958 uint64_t Address, const void *Decoder) {
960 return MCDisassembler::Fail;
962 unsigned Register = DPRDecoderTable[RegNo];
963 Inst.addOperand(MCOperand::CreateReg(Register));
964 return MCDisassembler::Success;
967 static DecodeStatus DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
968 uint64_t Address, const void *Decoder) {
970 return MCDisassembler::Fail;
971 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
975 DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
976 uint64_t Address, const void *Decoder) {
978 return MCDisassembler::Fail;
979 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
982 static const uint16_t QPRDecoderTable[] = {
983 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3,
984 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7,
985 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11,
986 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15
990 static DecodeStatus DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
991 uint64_t Address, const void *Decoder) {
993 return MCDisassembler::Fail;
996 unsigned Register = QPRDecoderTable[RegNo];
997 Inst.addOperand(MCOperand::CreateReg(Register));
998 return MCDisassembler::Success;
1001 static const uint16_t DPairDecoderTable[] = {
1002 ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6,
1003 ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12,
1004 ARM::Q6, ARM::D13_D14, ARM::Q7, ARM::D15_D16, ARM::Q8, ARM::D17_D18,
1005 ARM::Q9, ARM::D19_D20, ARM::Q10, ARM::D21_D22, ARM::Q11, ARM::D23_D24,
1006 ARM::Q12, ARM::D25_D26, ARM::Q13, ARM::D27_D28, ARM::Q14, ARM::D29_D30,
1010 static DecodeStatus DecodeDPairRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
1011 uint64_t Address, const void *Decoder) {
1013 return MCDisassembler::Fail;
1015 unsigned Register = DPairDecoderTable[RegNo];
1016 Inst.addOperand(MCOperand::CreateReg(Register));
1017 return MCDisassembler::Success;
1020 static const uint16_t DPairSpacedDecoderTable[] = {
1021 ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5,
1022 ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9,
1023 ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13,
1024 ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17,
1025 ARM::D16_D18, ARM::D17_D19, ARM::D18_D20, ARM::D19_D21,
1026 ARM::D20_D22, ARM::D21_D23, ARM::D22_D24, ARM::D23_D25,
1027 ARM::D24_D26, ARM::D25_D27, ARM::D26_D28, ARM::D27_D29,
1028 ARM::D28_D30, ARM::D29_D31
1031 static DecodeStatus DecodeDPairSpacedRegisterClass(llvm::MCInst &Inst,
1034 const void *Decoder) {
1036 return MCDisassembler::Fail;
1038 unsigned Register = DPairSpacedDecoderTable[RegNo];
1039 Inst.addOperand(MCOperand::CreateReg(Register));
1040 return MCDisassembler::Success;
1043 static DecodeStatus DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val,
1044 uint64_t Address, const void *Decoder) {
1045 if (Val == 0xF) return MCDisassembler::Fail;
1046 // AL predicate is not allowed on Thumb1 branches.
1047 if (Inst.getOpcode() == ARM::tBcc && Val == 0xE)
1048 return MCDisassembler::Fail;
1049 Inst.addOperand(MCOperand::CreateImm(Val));
1050 if (Val == ARMCC::AL) {
1051 Inst.addOperand(MCOperand::CreateReg(0));
1053 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1054 return MCDisassembler::Success;
1057 static DecodeStatus DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val,
1058 uint64_t Address, const void *Decoder) {
1060 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1062 Inst.addOperand(MCOperand::CreateReg(0));
1063 return MCDisassembler::Success;
1066 static DecodeStatus DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val,
1067 uint64_t Address, const void *Decoder) {
1068 uint32_t imm = Val & 0xFF;
1069 uint32_t rot = (Val & 0xF00) >> 7;
1070 uint32_t rot_imm = (imm >> rot) | (imm << ((32-rot) & 0x1F));
1071 Inst.addOperand(MCOperand::CreateImm(rot_imm));
1072 return MCDisassembler::Success;
1075 static DecodeStatus DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Val,
1076 uint64_t Address, const void *Decoder) {
1077 DecodeStatus S = MCDisassembler::Success;
1079 unsigned Rm = fieldFromInstruction32(Val, 0, 4);
1080 unsigned type = fieldFromInstruction32(Val, 5, 2);
1081 unsigned imm = fieldFromInstruction32(Val, 7, 5);
1083 // Register-immediate
1084 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1085 return MCDisassembler::Fail;
1087 ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
1090 Shift = ARM_AM::lsl;
1093 Shift = ARM_AM::lsr;
1096 Shift = ARM_AM::asr;
1099 Shift = ARM_AM::ror;
1103 if (Shift == ARM_AM::ror && imm == 0)
1104 Shift = ARM_AM::rrx;
1106 unsigned Op = Shift | (imm << 3);
1107 Inst.addOperand(MCOperand::CreateImm(Op));
1112 static DecodeStatus DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Val,
1113 uint64_t Address, const void *Decoder) {
1114 DecodeStatus S = MCDisassembler::Success;
1116 unsigned Rm = fieldFromInstruction32(Val, 0, 4);
1117 unsigned type = fieldFromInstruction32(Val, 5, 2);
1118 unsigned Rs = fieldFromInstruction32(Val, 8, 4);
1120 // Register-register
1121 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1122 return MCDisassembler::Fail;
1123 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder)))
1124 return MCDisassembler::Fail;
1126 ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
1129 Shift = ARM_AM::lsl;
1132 Shift = ARM_AM::lsr;
1135 Shift = ARM_AM::asr;
1138 Shift = ARM_AM::ror;
1142 Inst.addOperand(MCOperand::CreateImm(Shift));
1147 static DecodeStatus DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val,
1148 uint64_t Address, const void *Decoder) {
1149 DecodeStatus S = MCDisassembler::Success;
1151 bool writebackLoad = false;
1152 unsigned writebackReg = 0;
1153 switch (Inst.getOpcode()) {
1156 case ARM::LDMIA_UPD:
1157 case ARM::LDMDB_UPD:
1158 case ARM::LDMIB_UPD:
1159 case ARM::LDMDA_UPD:
1160 case ARM::t2LDMIA_UPD:
1161 case ARM::t2LDMDB_UPD:
1162 writebackLoad = true;
1163 writebackReg = Inst.getOperand(0).getReg();
1167 // Empty register lists are not allowed.
1168 if (CountPopulation_32(Val) == 0) return MCDisassembler::Fail;
1169 for (unsigned i = 0; i < 16; ++i) {
1170 if (Val & (1 << i)) {
1171 if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder)))
1172 return MCDisassembler::Fail;
1173 // Writeback not allowed if Rn is in the target list.
1174 if (writebackLoad && writebackReg == Inst.end()[-1].getReg())
1175 Check(S, MCDisassembler::SoftFail);
1182 static DecodeStatus DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned Val,
1183 uint64_t Address, const void *Decoder) {
1184 DecodeStatus S = MCDisassembler::Success;
1186 unsigned Vd = fieldFromInstruction32(Val, 8, 4);
1187 unsigned regs = Val & 0xFF;
1189 if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder)))
1190 return MCDisassembler::Fail;
1191 for (unsigned i = 0; i < (regs - 1); ++i) {
1192 if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder)))
1193 return MCDisassembler::Fail;
1199 static DecodeStatus DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned Val,
1200 uint64_t Address, const void *Decoder) {
1201 DecodeStatus S = MCDisassembler::Success;
1203 unsigned Vd = fieldFromInstruction32(Val, 8, 4);
1204 unsigned regs = (Val & 0xFF) / 2;
1206 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
1207 return MCDisassembler::Fail;
1208 for (unsigned i = 0; i < (regs - 1); ++i) {
1209 if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder)))
1210 return MCDisassembler::Fail;
1216 static DecodeStatus DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Val,
1217 uint64_t Address, const void *Decoder) {
1218 // This operand encodes a mask of contiguous zeros between a specified MSB
1219 // and LSB. To decode it, we create the mask of all bits MSB-and-lower,
1220 // the mask of all bits LSB-and-lower, and then xor them to create
1221 // the mask of that's all ones on [msb, lsb]. Finally we not it to
1222 // create the final mask.
1223 unsigned msb = fieldFromInstruction32(Val, 5, 5);
1224 unsigned lsb = fieldFromInstruction32(Val, 0, 5);
1226 DecodeStatus S = MCDisassembler::Success;
1227 if (lsb > msb) Check(S, MCDisassembler::SoftFail);
1229 uint32_t msb_mask = 0xFFFFFFFF;
1230 if (msb != 31) msb_mask = (1U << (msb+1)) - 1;
1231 uint32_t lsb_mask = (1U << lsb) - 1;
1233 Inst.addOperand(MCOperand::CreateImm(~(msb_mask ^ lsb_mask)));
1237 static DecodeStatus DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn,
1238 uint64_t Address, const void *Decoder) {
1239 DecodeStatus S = MCDisassembler::Success;
1241 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1242 unsigned CRd = fieldFromInstruction32(Insn, 12, 4);
1243 unsigned coproc = fieldFromInstruction32(Insn, 8, 4);
1244 unsigned imm = fieldFromInstruction32(Insn, 0, 8);
1245 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1246 unsigned U = fieldFromInstruction32(Insn, 23, 1);
1248 switch (Inst.getOpcode()) {
1249 case ARM::LDC_OFFSET:
1252 case ARM::LDC_OPTION:
1253 case ARM::LDCL_OFFSET:
1255 case ARM::LDCL_POST:
1256 case ARM::LDCL_OPTION:
1257 case ARM::STC_OFFSET:
1260 case ARM::STC_OPTION:
1261 case ARM::STCL_OFFSET:
1263 case ARM::STCL_POST:
1264 case ARM::STCL_OPTION:
1265 case ARM::t2LDC_OFFSET:
1266 case ARM::t2LDC_PRE:
1267 case ARM::t2LDC_POST:
1268 case ARM::t2LDC_OPTION:
1269 case ARM::t2LDCL_OFFSET:
1270 case ARM::t2LDCL_PRE:
1271 case ARM::t2LDCL_POST:
1272 case ARM::t2LDCL_OPTION:
1273 case ARM::t2STC_OFFSET:
1274 case ARM::t2STC_PRE:
1275 case ARM::t2STC_POST:
1276 case ARM::t2STC_OPTION:
1277 case ARM::t2STCL_OFFSET:
1278 case ARM::t2STCL_PRE:
1279 case ARM::t2STCL_POST:
1280 case ARM::t2STCL_OPTION:
1281 if (coproc == 0xA || coproc == 0xB)
1282 return MCDisassembler::Fail;
1288 Inst.addOperand(MCOperand::CreateImm(coproc));
1289 Inst.addOperand(MCOperand::CreateImm(CRd));
1290 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1291 return MCDisassembler::Fail;
1293 switch (Inst.getOpcode()) {
1294 case ARM::t2LDC2_OFFSET:
1295 case ARM::t2LDC2L_OFFSET:
1296 case ARM::t2LDC2_PRE:
1297 case ARM::t2LDC2L_PRE:
1298 case ARM::t2STC2_OFFSET:
1299 case ARM::t2STC2L_OFFSET:
1300 case ARM::t2STC2_PRE:
1301 case ARM::t2STC2L_PRE:
1302 case ARM::LDC2_OFFSET:
1303 case ARM::LDC2L_OFFSET:
1305 case ARM::LDC2L_PRE:
1306 case ARM::STC2_OFFSET:
1307 case ARM::STC2L_OFFSET:
1309 case ARM::STC2L_PRE:
1310 case ARM::t2LDC_OFFSET:
1311 case ARM::t2LDCL_OFFSET:
1312 case ARM::t2LDC_PRE:
1313 case ARM::t2LDCL_PRE:
1314 case ARM::t2STC_OFFSET:
1315 case ARM::t2STCL_OFFSET:
1316 case ARM::t2STC_PRE:
1317 case ARM::t2STCL_PRE:
1318 case ARM::LDC_OFFSET:
1319 case ARM::LDCL_OFFSET:
1322 case ARM::STC_OFFSET:
1323 case ARM::STCL_OFFSET:
1326 imm = ARM_AM::getAM5Opc(U ? ARM_AM::add : ARM_AM::sub, imm);
1327 Inst.addOperand(MCOperand::CreateImm(imm));
1329 case ARM::t2LDC2_POST:
1330 case ARM::t2LDC2L_POST:
1331 case ARM::t2STC2_POST:
1332 case ARM::t2STC2L_POST:
1333 case ARM::LDC2_POST:
1334 case ARM::LDC2L_POST:
1335 case ARM::STC2_POST:
1336 case ARM::STC2L_POST:
1337 case ARM::t2LDC_POST:
1338 case ARM::t2LDCL_POST:
1339 case ARM::t2STC_POST:
1340 case ARM::t2STCL_POST:
1342 case ARM::LDCL_POST:
1344 case ARM::STCL_POST:
1348 // The 'option' variant doesn't encode 'U' in the immediate since
1349 // the immediate is unsigned [0,255].
1350 Inst.addOperand(MCOperand::CreateImm(imm));
1354 switch (Inst.getOpcode()) {
1355 case ARM::LDC_OFFSET:
1358 case ARM::LDC_OPTION:
1359 case ARM::LDCL_OFFSET:
1361 case ARM::LDCL_POST:
1362 case ARM::LDCL_OPTION:
1363 case ARM::STC_OFFSET:
1366 case ARM::STC_OPTION:
1367 case ARM::STCL_OFFSET:
1369 case ARM::STCL_POST:
1370 case ARM::STCL_OPTION:
1371 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1372 return MCDisassembler::Fail;
1382 DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, unsigned Insn,
1383 uint64_t Address, const void *Decoder) {
1384 DecodeStatus S = MCDisassembler::Success;
1386 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1387 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
1388 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
1389 unsigned imm = fieldFromInstruction32(Insn, 0, 12);
1390 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1391 unsigned reg = fieldFromInstruction32(Insn, 25, 1);
1392 unsigned P = fieldFromInstruction32(Insn, 24, 1);
1393 unsigned W = fieldFromInstruction32(Insn, 21, 1);
1395 // On stores, the writeback operand precedes Rt.
1396 switch (Inst.getOpcode()) {
1397 case ARM::STR_POST_IMM:
1398 case ARM::STR_POST_REG:
1399 case ARM::STRB_POST_IMM:
1400 case ARM::STRB_POST_REG:
1401 case ARM::STRT_POST_REG:
1402 case ARM::STRT_POST_IMM:
1403 case ARM::STRBT_POST_REG:
1404 case ARM::STRBT_POST_IMM:
1405 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1406 return MCDisassembler::Fail;
1412 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
1413 return MCDisassembler::Fail;
1415 // On loads, the writeback operand comes after Rt.
1416 switch (Inst.getOpcode()) {
1417 case ARM::LDR_POST_IMM:
1418 case ARM::LDR_POST_REG:
1419 case ARM::LDRB_POST_IMM:
1420 case ARM::LDRB_POST_REG:
1421 case ARM::LDRBT_POST_REG:
1422 case ARM::LDRBT_POST_IMM:
1423 case ARM::LDRT_POST_REG:
1424 case ARM::LDRT_POST_IMM:
1425 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1426 return MCDisassembler::Fail;
1432 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1433 return MCDisassembler::Fail;
1435 ARM_AM::AddrOpc Op = ARM_AM::add;
1436 if (!fieldFromInstruction32(Insn, 23, 1))
1439 bool writeback = (P == 0) || (W == 1);
1440 unsigned idx_mode = 0;
1442 idx_mode = ARMII::IndexModePre;
1443 else if (!P && writeback)
1444 idx_mode = ARMII::IndexModePost;
1446 if (writeback && (Rn == 15 || Rn == Rt))
1447 S = MCDisassembler::SoftFail; // UNPREDICTABLE
1450 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1451 return MCDisassembler::Fail;
1452 ARM_AM::ShiftOpc Opc = ARM_AM::lsl;
1453 switch( fieldFromInstruction32(Insn, 5, 2)) {
1467 return MCDisassembler::Fail;
1469 unsigned amt = fieldFromInstruction32(Insn, 7, 5);
1470 unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode);
1472 Inst.addOperand(MCOperand::CreateImm(imm));
1474 Inst.addOperand(MCOperand::CreateReg(0));
1475 unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode);
1476 Inst.addOperand(MCOperand::CreateImm(tmp));
1479 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1480 return MCDisassembler::Fail;
1485 static DecodeStatus DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Val,
1486 uint64_t Address, const void *Decoder) {
1487 DecodeStatus S = MCDisassembler::Success;
1489 unsigned Rn = fieldFromInstruction32(Val, 13, 4);
1490 unsigned Rm = fieldFromInstruction32(Val, 0, 4);
1491 unsigned type = fieldFromInstruction32(Val, 5, 2);
1492 unsigned imm = fieldFromInstruction32(Val, 7, 5);
1493 unsigned U = fieldFromInstruction32(Val, 12, 1);
1495 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl;
1511 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1512 return MCDisassembler::Fail;
1513 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1514 return MCDisassembler::Fail;
1517 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp);
1519 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp);
1520 Inst.addOperand(MCOperand::CreateImm(shift));
1526 DecodeAddrMode3Instruction(llvm::MCInst &Inst, unsigned Insn,
1527 uint64_t Address, const void *Decoder) {
1528 DecodeStatus S = MCDisassembler::Success;
1530 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
1531 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1532 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
1533 unsigned type = fieldFromInstruction32(Insn, 22, 1);
1534 unsigned imm = fieldFromInstruction32(Insn, 8, 4);
1535 unsigned U = ((~fieldFromInstruction32(Insn, 23, 1)) & 1) << 8;
1536 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1537 unsigned W = fieldFromInstruction32(Insn, 21, 1);
1538 unsigned P = fieldFromInstruction32(Insn, 24, 1);
1540 bool writeback = (W == 1) | (P == 0);
1542 // For {LD,ST}RD, Rt must be even, else undefined.
1543 switch (Inst.getOpcode()) {
1546 case ARM::STRD_POST:
1549 case ARM::LDRD_POST:
1550 if (Rt & 0x1) return MCDisassembler::Fail;
1556 if (writeback) { // Writeback
1558 U |= ARMII::IndexModePre << 9;
1560 U |= ARMII::IndexModePost << 9;
1562 // On stores, the writeback operand precedes Rt.
1563 switch (Inst.getOpcode()) {
1566 case ARM::STRD_POST:
1569 case ARM::STRH_POST:
1570 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1571 return MCDisassembler::Fail;
1578 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
1579 return MCDisassembler::Fail;
1580 switch (Inst.getOpcode()) {
1583 case ARM::STRD_POST:
1586 case ARM::LDRD_POST:
1587 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
1588 return MCDisassembler::Fail;
1595 // On loads, the writeback operand comes after Rt.
1596 switch (Inst.getOpcode()) {
1599 case ARM::LDRD_POST:
1602 case ARM::LDRH_POST:
1604 case ARM::LDRSH_PRE:
1605 case ARM::LDRSH_POST:
1607 case ARM::LDRSB_PRE:
1608 case ARM::LDRSB_POST:
1611 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1612 return MCDisassembler::Fail;
1619 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1620 return MCDisassembler::Fail;
1623 Inst.addOperand(MCOperand::CreateReg(0));
1624 Inst.addOperand(MCOperand::CreateImm(U | (imm << 4) | Rm));
1626 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1627 return MCDisassembler::Fail;
1628 Inst.addOperand(MCOperand::CreateImm(U));
1631 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1632 return MCDisassembler::Fail;
1637 static DecodeStatus DecodeRFEInstruction(llvm::MCInst &Inst, unsigned Insn,
1638 uint64_t Address, const void *Decoder) {
1639 DecodeStatus S = MCDisassembler::Success;
1641 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1642 unsigned mode = fieldFromInstruction32(Insn, 23, 2);
1659 Inst.addOperand(MCOperand::CreateImm(mode));
1660 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1661 return MCDisassembler::Fail;
1666 static DecodeStatus DecodeMemMultipleWritebackInstruction(llvm::MCInst &Inst,
1668 uint64_t Address, const void *Decoder) {
1669 DecodeStatus S = MCDisassembler::Success;
1671 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1672 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1673 unsigned reglist = fieldFromInstruction32(Insn, 0, 16);
1676 switch (Inst.getOpcode()) {
1678 Inst.setOpcode(ARM::RFEDA);
1680 case ARM::LDMDA_UPD:
1681 Inst.setOpcode(ARM::RFEDA_UPD);
1684 Inst.setOpcode(ARM::RFEDB);
1686 case ARM::LDMDB_UPD:
1687 Inst.setOpcode(ARM::RFEDB_UPD);
1690 Inst.setOpcode(ARM::RFEIA);
1692 case ARM::LDMIA_UPD:
1693 Inst.setOpcode(ARM::RFEIA_UPD);
1696 Inst.setOpcode(ARM::RFEIB);
1698 case ARM::LDMIB_UPD:
1699 Inst.setOpcode(ARM::RFEIB_UPD);
1702 Inst.setOpcode(ARM::SRSDA);
1704 case ARM::STMDA_UPD:
1705 Inst.setOpcode(ARM::SRSDA_UPD);
1708 Inst.setOpcode(ARM::SRSDB);
1710 case ARM::STMDB_UPD:
1711 Inst.setOpcode(ARM::SRSDB_UPD);
1714 Inst.setOpcode(ARM::SRSIA);
1716 case ARM::STMIA_UPD:
1717 Inst.setOpcode(ARM::SRSIA_UPD);
1720 Inst.setOpcode(ARM::SRSIB);
1722 case ARM::STMIB_UPD:
1723 Inst.setOpcode(ARM::SRSIB_UPD);
1726 if (!Check(S, MCDisassembler::Fail)) return MCDisassembler::Fail;
1729 // For stores (which become SRS's, the only operand is the mode.
1730 if (fieldFromInstruction32(Insn, 20, 1) == 0) {
1732 MCOperand::CreateImm(fieldFromInstruction32(Insn, 0, 4)));
1736 return DecodeRFEInstruction(Inst, Insn, Address, Decoder);
1739 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1740 return MCDisassembler::Fail;
1741 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1742 return MCDisassembler::Fail; // Tied
1743 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1744 return MCDisassembler::Fail;
1745 if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder)))
1746 return MCDisassembler::Fail;
1751 static DecodeStatus DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn,
1752 uint64_t Address, const void *Decoder) {
1753 unsigned imod = fieldFromInstruction32(Insn, 18, 2);
1754 unsigned M = fieldFromInstruction32(Insn, 17, 1);
1755 unsigned iflags = fieldFromInstruction32(Insn, 6, 3);
1756 unsigned mode = fieldFromInstruction32(Insn, 0, 5);
1758 DecodeStatus S = MCDisassembler::Success;
1760 // imod == '01' --> UNPREDICTABLE
1761 // NOTE: Even though this is technically UNPREDICTABLE, we choose to
1762 // return failure here. The '01' imod value is unprintable, so there's
1763 // nothing useful we could do even if we returned UNPREDICTABLE.
1765 if (imod == 1) return MCDisassembler::Fail;
1768 Inst.setOpcode(ARM::CPS3p);
1769 Inst.addOperand(MCOperand::CreateImm(imod));
1770 Inst.addOperand(MCOperand::CreateImm(iflags));
1771 Inst.addOperand(MCOperand::CreateImm(mode));
1772 } else if (imod && !M) {
1773 Inst.setOpcode(ARM::CPS2p);
1774 Inst.addOperand(MCOperand::CreateImm(imod));
1775 Inst.addOperand(MCOperand::CreateImm(iflags));
1776 if (mode) S = MCDisassembler::SoftFail;
1777 } else if (!imod && M) {
1778 Inst.setOpcode(ARM::CPS1p);
1779 Inst.addOperand(MCOperand::CreateImm(mode));
1780 if (iflags) S = MCDisassembler::SoftFail;
1782 // imod == '00' && M == '0' --> UNPREDICTABLE
1783 Inst.setOpcode(ARM::CPS1p);
1784 Inst.addOperand(MCOperand::CreateImm(mode));
1785 S = MCDisassembler::SoftFail;
1791 static DecodeStatus DecodeT2CPSInstruction(llvm::MCInst &Inst, unsigned Insn,
1792 uint64_t Address, const void *Decoder) {
1793 unsigned imod = fieldFromInstruction32(Insn, 9, 2);
1794 unsigned M = fieldFromInstruction32(Insn, 8, 1);
1795 unsigned iflags = fieldFromInstruction32(Insn, 5, 3);
1796 unsigned mode = fieldFromInstruction32(Insn, 0, 5);
1798 DecodeStatus S = MCDisassembler::Success;
1800 // imod == '01' --> UNPREDICTABLE
1801 // NOTE: Even though this is technically UNPREDICTABLE, we choose to
1802 // return failure here. The '01' imod value is unprintable, so there's
1803 // nothing useful we could do even if we returned UNPREDICTABLE.
1805 if (imod == 1) return MCDisassembler::Fail;
1808 Inst.setOpcode(ARM::t2CPS3p);
1809 Inst.addOperand(MCOperand::CreateImm(imod));
1810 Inst.addOperand(MCOperand::CreateImm(iflags));
1811 Inst.addOperand(MCOperand::CreateImm(mode));
1812 } else if (imod && !M) {
1813 Inst.setOpcode(ARM::t2CPS2p);
1814 Inst.addOperand(MCOperand::CreateImm(imod));
1815 Inst.addOperand(MCOperand::CreateImm(iflags));
1816 if (mode) S = MCDisassembler::SoftFail;
1817 } else if (!imod && M) {
1818 Inst.setOpcode(ARM::t2CPS1p);
1819 Inst.addOperand(MCOperand::CreateImm(mode));
1820 if (iflags) S = MCDisassembler::SoftFail;
1822 // imod == '00' && M == '0' --> UNPREDICTABLE
1823 Inst.setOpcode(ARM::t2CPS1p);
1824 Inst.addOperand(MCOperand::CreateImm(mode));
1825 S = MCDisassembler::SoftFail;
1831 static DecodeStatus DecodeT2MOVTWInstruction(llvm::MCInst &Inst, unsigned Insn,
1832 uint64_t Address, const void *Decoder) {
1833 DecodeStatus S = MCDisassembler::Success;
1835 unsigned Rd = fieldFromInstruction32(Insn, 8, 4);
1838 imm |= (fieldFromInstruction32(Insn, 0, 8) << 0);
1839 imm |= (fieldFromInstruction32(Insn, 12, 3) << 8);
1840 imm |= (fieldFromInstruction32(Insn, 16, 4) << 12);
1841 imm |= (fieldFromInstruction32(Insn, 26, 1) << 11);
1843 if (Inst.getOpcode() == ARM::t2MOVTi16)
1844 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
1845 return MCDisassembler::Fail;
1846 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
1847 return MCDisassembler::Fail;
1849 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder))
1850 Inst.addOperand(MCOperand::CreateImm(imm));
1855 static DecodeStatus DecodeArmMOVTWInstruction(llvm::MCInst &Inst, unsigned Insn,
1856 uint64_t Address, const void *Decoder) {
1857 DecodeStatus S = MCDisassembler::Success;
1859 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
1860 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1863 imm |= (fieldFromInstruction32(Insn, 0, 12) << 0);
1864 imm |= (fieldFromInstruction32(Insn, 16, 4) << 12);
1866 if (Inst.getOpcode() == ARM::MOVTi16)
1867 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
1868 return MCDisassembler::Fail;
1869 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
1870 return MCDisassembler::Fail;
1872 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder))
1873 Inst.addOperand(MCOperand::CreateImm(imm));
1875 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1876 return MCDisassembler::Fail;
1881 static DecodeStatus DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn,
1882 uint64_t Address, const void *Decoder) {
1883 DecodeStatus S = MCDisassembler::Success;
1885 unsigned Rd = fieldFromInstruction32(Insn, 16, 4);
1886 unsigned Rn = fieldFromInstruction32(Insn, 0, 4);
1887 unsigned Rm = fieldFromInstruction32(Insn, 8, 4);
1888 unsigned Ra = fieldFromInstruction32(Insn, 12, 4);
1889 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1892 return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
1894 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
1895 return MCDisassembler::Fail;
1896 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
1897 return MCDisassembler::Fail;
1898 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1899 return MCDisassembler::Fail;
1900 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder)))
1901 return MCDisassembler::Fail;
1903 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1904 return MCDisassembler::Fail;
1909 static DecodeStatus DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val,
1910 uint64_t Address, const void *Decoder) {
1911 DecodeStatus S = MCDisassembler::Success;
1913 unsigned add = fieldFromInstruction32(Val, 12, 1);
1914 unsigned imm = fieldFromInstruction32(Val, 0, 12);
1915 unsigned Rn = fieldFromInstruction32(Val, 13, 4);
1917 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1918 return MCDisassembler::Fail;
1920 if (!add) imm *= -1;
1921 if (imm == 0 && !add) imm = INT32_MIN;
1922 Inst.addOperand(MCOperand::CreateImm(imm));
1924 tryAddingPcLoadReferenceComment(Address, Address + imm + 8, Decoder);
1929 static DecodeStatus DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val,
1930 uint64_t Address, const void *Decoder) {
1931 DecodeStatus S = MCDisassembler::Success;
1933 unsigned Rn = fieldFromInstruction32(Val, 9, 4);
1934 unsigned U = fieldFromInstruction32(Val, 8, 1);
1935 unsigned imm = fieldFromInstruction32(Val, 0, 8);
1937 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1938 return MCDisassembler::Fail;
1941 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::add, imm)));
1943 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm)));
1948 static DecodeStatus DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val,
1949 uint64_t Address, const void *Decoder) {
1950 return DecodeGPRRegisterClass(Inst, Val, Address, Decoder);
1954 DecodeBranchImmInstruction(llvm::MCInst &Inst, unsigned Insn,
1955 uint64_t Address, const void *Decoder) {
1956 DecodeStatus S = MCDisassembler::Success;
1958 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1959 unsigned imm = fieldFromInstruction32(Insn, 0, 24) << 2;
1962 Inst.setOpcode(ARM::BLXi);
1963 imm |= fieldFromInstruction32(Insn, 24, 1) << 1;
1964 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8,
1965 true, 4, Inst, Decoder))
1966 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm)));
1970 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8,
1971 true, 4, Inst, Decoder))
1972 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm)));
1973 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1974 return MCDisassembler::Fail;
1980 static DecodeStatus DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val,
1981 uint64_t Address, const void *Decoder) {
1982 DecodeStatus S = MCDisassembler::Success;
1984 unsigned Rm = fieldFromInstruction32(Val, 0, 4);
1985 unsigned align = fieldFromInstruction32(Val, 4, 2);
1987 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1988 return MCDisassembler::Fail;
1990 Inst.addOperand(MCOperand::CreateImm(0));
1992 Inst.addOperand(MCOperand::CreateImm(4 << align));
1997 static DecodeStatus DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Insn,
1998 uint64_t Address, const void *Decoder) {
1999 DecodeStatus S = MCDisassembler::Success;
2001 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2002 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2003 unsigned wb = fieldFromInstruction32(Insn, 16, 4);
2004 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2005 Rn |= fieldFromInstruction32(Insn, 4, 2) << 4;
2006 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2008 // First output register
2009 switch (Inst.getOpcode()) {
2010 case ARM::VLD1q16: case ARM::VLD1q32: case ARM::VLD1q64: case ARM::VLD1q8:
2011 case ARM::VLD1q16wb_fixed: case ARM::VLD1q16wb_register:
2012 case ARM::VLD1q32wb_fixed: case ARM::VLD1q32wb_register:
2013 case ARM::VLD1q64wb_fixed: case ARM::VLD1q64wb_register:
2014 case ARM::VLD1q8wb_fixed: case ARM::VLD1q8wb_register:
2015 case ARM::VLD2d16: case ARM::VLD2d32: case ARM::VLD2d8:
2016 case ARM::VLD2d16wb_fixed: case ARM::VLD2d16wb_register:
2017 case ARM::VLD2d32wb_fixed: case ARM::VLD2d32wb_register:
2018 case ARM::VLD2d8wb_fixed: case ARM::VLD2d8wb_register:
2019 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2020 return MCDisassembler::Fail;
2025 case ARM::VLD2b16wb_fixed:
2026 case ARM::VLD2b16wb_register:
2027 case ARM::VLD2b32wb_fixed:
2028 case ARM::VLD2b32wb_register:
2029 case ARM::VLD2b8wb_fixed:
2030 case ARM::VLD2b8wb_register:
2031 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
2032 return MCDisassembler::Fail;
2035 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2036 return MCDisassembler::Fail;
2039 // Second output register
2040 switch (Inst.getOpcode()) {
2044 case ARM::VLD3d8_UPD:
2045 case ARM::VLD3d16_UPD:
2046 case ARM::VLD3d32_UPD:
2050 case ARM::VLD4d8_UPD:
2051 case ARM::VLD4d16_UPD:
2052 case ARM::VLD4d32_UPD:
2053 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
2054 return MCDisassembler::Fail;
2059 case ARM::VLD3q8_UPD:
2060 case ARM::VLD3q16_UPD:
2061 case ARM::VLD3q32_UPD:
2065 case ARM::VLD4q8_UPD:
2066 case ARM::VLD4q16_UPD:
2067 case ARM::VLD4q32_UPD:
2068 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2069 return MCDisassembler::Fail;
2074 // Third output register
2075 switch(Inst.getOpcode()) {
2079 case ARM::VLD3d8_UPD:
2080 case ARM::VLD3d16_UPD:
2081 case ARM::VLD3d32_UPD:
2085 case ARM::VLD4d8_UPD:
2086 case ARM::VLD4d16_UPD:
2087 case ARM::VLD4d32_UPD:
2088 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2089 return MCDisassembler::Fail;
2094 case ARM::VLD3q8_UPD:
2095 case ARM::VLD3q16_UPD:
2096 case ARM::VLD3q32_UPD:
2100 case ARM::VLD4q8_UPD:
2101 case ARM::VLD4q16_UPD:
2102 case ARM::VLD4q32_UPD:
2103 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
2104 return MCDisassembler::Fail;
2110 // Fourth output register
2111 switch (Inst.getOpcode()) {
2115 case ARM::VLD4d8_UPD:
2116 case ARM::VLD4d16_UPD:
2117 case ARM::VLD4d32_UPD:
2118 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
2119 return MCDisassembler::Fail;
2124 case ARM::VLD4q8_UPD:
2125 case ARM::VLD4q16_UPD:
2126 case ARM::VLD4q32_UPD:
2127 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
2128 return MCDisassembler::Fail;
2134 // Writeback operand
2135 switch (Inst.getOpcode()) {
2136 case ARM::VLD1d8wb_fixed:
2137 case ARM::VLD1d16wb_fixed:
2138 case ARM::VLD1d32wb_fixed:
2139 case ARM::VLD1d64wb_fixed:
2140 case ARM::VLD1d8wb_register:
2141 case ARM::VLD1d16wb_register:
2142 case ARM::VLD1d32wb_register:
2143 case ARM::VLD1d64wb_register:
2144 case ARM::VLD1q8wb_fixed:
2145 case ARM::VLD1q16wb_fixed:
2146 case ARM::VLD1q32wb_fixed:
2147 case ARM::VLD1q64wb_fixed:
2148 case ARM::VLD1q8wb_register:
2149 case ARM::VLD1q16wb_register:
2150 case ARM::VLD1q32wb_register:
2151 case ARM::VLD1q64wb_register:
2152 case ARM::VLD1d8Twb_fixed:
2153 case ARM::VLD1d8Twb_register:
2154 case ARM::VLD1d16Twb_fixed:
2155 case ARM::VLD1d16Twb_register:
2156 case ARM::VLD1d32Twb_fixed:
2157 case ARM::VLD1d32Twb_register:
2158 case ARM::VLD1d64Twb_fixed:
2159 case ARM::VLD1d64Twb_register:
2160 case ARM::VLD1d8Qwb_fixed:
2161 case ARM::VLD1d8Qwb_register:
2162 case ARM::VLD1d16Qwb_fixed:
2163 case ARM::VLD1d16Qwb_register:
2164 case ARM::VLD1d32Qwb_fixed:
2165 case ARM::VLD1d32Qwb_register:
2166 case ARM::VLD1d64Qwb_fixed:
2167 case ARM::VLD1d64Qwb_register:
2168 case ARM::VLD2d8wb_fixed:
2169 case ARM::VLD2d16wb_fixed:
2170 case ARM::VLD2d32wb_fixed:
2171 case ARM::VLD2q8wb_fixed:
2172 case ARM::VLD2q16wb_fixed:
2173 case ARM::VLD2q32wb_fixed:
2174 case ARM::VLD2d8wb_register:
2175 case ARM::VLD2d16wb_register:
2176 case ARM::VLD2d32wb_register:
2177 case ARM::VLD2q8wb_register:
2178 case ARM::VLD2q16wb_register:
2179 case ARM::VLD2q32wb_register:
2180 case ARM::VLD2b8wb_fixed:
2181 case ARM::VLD2b16wb_fixed:
2182 case ARM::VLD2b32wb_fixed:
2183 case ARM::VLD2b8wb_register:
2184 case ARM::VLD2b16wb_register:
2185 case ARM::VLD2b32wb_register:
2186 case ARM::VLD3d8_UPD:
2187 case ARM::VLD3d16_UPD:
2188 case ARM::VLD3d32_UPD:
2189 case ARM::VLD3q8_UPD:
2190 case ARM::VLD3q16_UPD:
2191 case ARM::VLD3q32_UPD:
2192 case ARM::VLD4d8_UPD:
2193 case ARM::VLD4d16_UPD:
2194 case ARM::VLD4d32_UPD:
2195 case ARM::VLD4q8_UPD:
2196 case ARM::VLD4q16_UPD:
2197 case ARM::VLD4q32_UPD:
2198 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
2199 return MCDisassembler::Fail;
2205 // AddrMode6 Base (register+alignment)
2206 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
2207 return MCDisassembler::Fail;
2209 // AddrMode6 Offset (register)
2210 switch (Inst.getOpcode()) {
2212 // The below have been updated to have explicit am6offset split
2213 // between fixed and register offset. For those instructions not
2214 // yet updated, we need to add an additional reg0 operand for the
2217 // The fixed offset encodes as Rm == 0xd, so we check for that.
2219 Inst.addOperand(MCOperand::CreateReg(0));
2222 // Fall through to handle the register offset variant.
2223 case ARM::VLD1d8wb_fixed:
2224 case ARM::VLD1d16wb_fixed:
2225 case ARM::VLD1d32wb_fixed:
2226 case ARM::VLD1d64wb_fixed:
2227 case ARM::VLD1d8Twb_fixed:
2228 case ARM::VLD1d16Twb_fixed:
2229 case ARM::VLD1d32Twb_fixed:
2230 case ARM::VLD1d64Twb_fixed:
2231 case ARM::VLD1d8Qwb_fixed:
2232 case ARM::VLD1d16Qwb_fixed:
2233 case ARM::VLD1d32Qwb_fixed:
2234 case ARM::VLD1d64Qwb_fixed:
2235 case ARM::VLD1d8wb_register:
2236 case ARM::VLD1d16wb_register:
2237 case ARM::VLD1d32wb_register:
2238 case ARM::VLD1d64wb_register:
2239 case ARM::VLD1q8wb_fixed:
2240 case ARM::VLD1q16wb_fixed:
2241 case ARM::VLD1q32wb_fixed:
2242 case ARM::VLD1q64wb_fixed:
2243 case ARM::VLD1q8wb_register:
2244 case ARM::VLD1q16wb_register:
2245 case ARM::VLD1q32wb_register:
2246 case ARM::VLD1q64wb_register:
2247 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback
2248 // variant encodes Rm == 0xf. Anything else is a register offset post-
2249 // increment and we need to add the register operand to the instruction.
2250 if (Rm != 0xD && Rm != 0xF &&
2251 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2252 return MCDisassembler::Fail;
2259 static DecodeStatus DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Insn,
2260 uint64_t Address, const void *Decoder) {
2261 DecodeStatus S = MCDisassembler::Success;
2263 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2264 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2265 unsigned wb = fieldFromInstruction32(Insn, 16, 4);
2266 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2267 Rn |= fieldFromInstruction32(Insn, 4, 2) << 4;
2268 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2270 // Writeback Operand
2271 switch (Inst.getOpcode()) {
2272 case ARM::VST1d8wb_fixed:
2273 case ARM::VST1d16wb_fixed:
2274 case ARM::VST1d32wb_fixed:
2275 case ARM::VST1d64wb_fixed:
2276 case ARM::VST1d8wb_register:
2277 case ARM::VST1d16wb_register:
2278 case ARM::VST1d32wb_register:
2279 case ARM::VST1d64wb_register:
2280 case ARM::VST1q8wb_fixed:
2281 case ARM::VST1q16wb_fixed:
2282 case ARM::VST1q32wb_fixed:
2283 case ARM::VST1q64wb_fixed:
2284 case ARM::VST1q8wb_register:
2285 case ARM::VST1q16wb_register:
2286 case ARM::VST1q32wb_register:
2287 case ARM::VST1q64wb_register:
2288 case ARM::VST1d8Twb_fixed:
2289 case ARM::VST1d16Twb_fixed:
2290 case ARM::VST1d32Twb_fixed:
2291 case ARM::VST1d64Twb_fixed:
2292 case ARM::VST1d8Twb_register:
2293 case ARM::VST1d16Twb_register:
2294 case ARM::VST1d32Twb_register:
2295 case ARM::VST1d64Twb_register:
2296 case ARM::VST1d8Qwb_fixed:
2297 case ARM::VST1d16Qwb_fixed:
2298 case ARM::VST1d32Qwb_fixed:
2299 case ARM::VST1d64Qwb_fixed:
2300 case ARM::VST1d8Qwb_register:
2301 case ARM::VST1d16Qwb_register:
2302 case ARM::VST1d32Qwb_register:
2303 case ARM::VST1d64Qwb_register:
2304 case ARM::VST2d8wb_fixed:
2305 case ARM::VST2d16wb_fixed:
2306 case ARM::VST2d32wb_fixed:
2307 case ARM::VST2d8wb_register:
2308 case ARM::VST2d16wb_register:
2309 case ARM::VST2d32wb_register:
2310 case ARM::VST2q8wb_fixed:
2311 case ARM::VST2q16wb_fixed:
2312 case ARM::VST2q32wb_fixed:
2313 case ARM::VST2q8wb_register:
2314 case ARM::VST2q16wb_register:
2315 case ARM::VST2q32wb_register:
2316 case ARM::VST2b8wb_fixed:
2317 case ARM::VST2b16wb_fixed:
2318 case ARM::VST2b32wb_fixed:
2319 case ARM::VST2b8wb_register:
2320 case ARM::VST2b16wb_register:
2321 case ARM::VST2b32wb_register:
2322 case ARM::VST3d8_UPD:
2323 case ARM::VST3d16_UPD:
2324 case ARM::VST3d32_UPD:
2325 case ARM::VST3q8_UPD:
2326 case ARM::VST3q16_UPD:
2327 case ARM::VST3q32_UPD:
2328 case ARM::VST4d8_UPD:
2329 case ARM::VST4d16_UPD:
2330 case ARM::VST4d32_UPD:
2331 case ARM::VST4q8_UPD:
2332 case ARM::VST4q16_UPD:
2333 case ARM::VST4q32_UPD:
2334 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
2335 return MCDisassembler::Fail;
2341 // AddrMode6 Base (register+alignment)
2342 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
2343 return MCDisassembler::Fail;
2345 // AddrMode6 Offset (register)
2346 switch (Inst.getOpcode()) {
2349 Inst.addOperand(MCOperand::CreateReg(0));
2350 else if (Rm != 0xF) {
2351 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2352 return MCDisassembler::Fail;
2355 case ARM::VST1d8wb_fixed:
2356 case ARM::VST1d16wb_fixed:
2357 case ARM::VST1d32wb_fixed:
2358 case ARM::VST1d64wb_fixed:
2359 case ARM::VST1q8wb_fixed:
2360 case ARM::VST1q16wb_fixed:
2361 case ARM::VST1q32wb_fixed:
2362 case ARM::VST1q64wb_fixed:
2367 // First input register
2368 switch (Inst.getOpcode()) {
2373 case ARM::VST1q16wb_fixed:
2374 case ARM::VST1q16wb_register:
2375 case ARM::VST1q32wb_fixed:
2376 case ARM::VST1q32wb_register:
2377 case ARM::VST1q64wb_fixed:
2378 case ARM::VST1q64wb_register:
2379 case ARM::VST1q8wb_fixed:
2380 case ARM::VST1q8wb_register:
2384 case ARM::VST2d16wb_fixed:
2385 case ARM::VST2d16wb_register:
2386 case ARM::VST2d32wb_fixed:
2387 case ARM::VST2d32wb_register:
2388 case ARM::VST2d8wb_fixed:
2389 case ARM::VST2d8wb_register:
2390 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2391 return MCDisassembler::Fail;
2396 case ARM::VST2b16wb_fixed:
2397 case ARM::VST2b16wb_register:
2398 case ARM::VST2b32wb_fixed:
2399 case ARM::VST2b32wb_register:
2400 case ARM::VST2b8wb_fixed:
2401 case ARM::VST2b8wb_register:
2402 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
2403 return MCDisassembler::Fail;
2406 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2407 return MCDisassembler::Fail;
2410 // Second input register
2411 switch (Inst.getOpcode()) {
2415 case ARM::VST3d8_UPD:
2416 case ARM::VST3d16_UPD:
2417 case ARM::VST3d32_UPD:
2421 case ARM::VST4d8_UPD:
2422 case ARM::VST4d16_UPD:
2423 case ARM::VST4d32_UPD:
2424 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
2425 return MCDisassembler::Fail;
2430 case ARM::VST3q8_UPD:
2431 case ARM::VST3q16_UPD:
2432 case ARM::VST3q32_UPD:
2436 case ARM::VST4q8_UPD:
2437 case ARM::VST4q16_UPD:
2438 case ARM::VST4q32_UPD:
2439 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2440 return MCDisassembler::Fail;
2446 // Third input register
2447 switch (Inst.getOpcode()) {
2451 case ARM::VST3d8_UPD:
2452 case ARM::VST3d16_UPD:
2453 case ARM::VST3d32_UPD:
2457 case ARM::VST4d8_UPD:
2458 case ARM::VST4d16_UPD:
2459 case ARM::VST4d32_UPD:
2460 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2461 return MCDisassembler::Fail;
2466 case ARM::VST3q8_UPD:
2467 case ARM::VST3q16_UPD:
2468 case ARM::VST3q32_UPD:
2472 case ARM::VST4q8_UPD:
2473 case ARM::VST4q16_UPD:
2474 case ARM::VST4q32_UPD:
2475 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
2476 return MCDisassembler::Fail;
2482 // Fourth input register
2483 switch (Inst.getOpcode()) {
2487 case ARM::VST4d8_UPD:
2488 case ARM::VST4d16_UPD:
2489 case ARM::VST4d32_UPD:
2490 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
2491 return MCDisassembler::Fail;
2496 case ARM::VST4q8_UPD:
2497 case ARM::VST4q16_UPD:
2498 case ARM::VST4q32_UPD:
2499 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
2500 return MCDisassembler::Fail;
2509 static DecodeStatus DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Insn,
2510 uint64_t Address, const void *Decoder) {
2511 DecodeStatus S = MCDisassembler::Success;
2513 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2514 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2515 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2516 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2517 unsigned align = fieldFromInstruction32(Insn, 4, 1);
2518 unsigned size = fieldFromInstruction32(Insn, 6, 2);
2520 align *= (1 << size);
2522 switch (Inst.getOpcode()) {
2523 case ARM::VLD1DUPq16: case ARM::VLD1DUPq32: case ARM::VLD1DUPq8:
2524 case ARM::VLD1DUPq16wb_fixed: case ARM::VLD1DUPq16wb_register:
2525 case ARM::VLD1DUPq32wb_fixed: case ARM::VLD1DUPq32wb_register:
2526 case ARM::VLD1DUPq8wb_fixed: case ARM::VLD1DUPq8wb_register:
2527 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2528 return MCDisassembler::Fail;
2531 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2532 return MCDisassembler::Fail;
2536 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2537 return MCDisassembler::Fail;
2540 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2541 return MCDisassembler::Fail;
2542 Inst.addOperand(MCOperand::CreateImm(align));
2544 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback
2545 // variant encodes Rm == 0xf. Anything else is a register offset post-
2546 // increment and we need to add the register operand to the instruction.
2547 if (Rm != 0xD && Rm != 0xF &&
2548 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2549 return MCDisassembler::Fail;
2554 static DecodeStatus DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Insn,
2555 uint64_t Address, const void *Decoder) {
2556 DecodeStatus S = MCDisassembler::Success;
2558 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2559 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2560 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2561 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2562 unsigned align = fieldFromInstruction32(Insn, 4, 1);
2563 unsigned size = 1 << fieldFromInstruction32(Insn, 6, 2);
2564 unsigned pred = fieldFromInstruction32(Insn, 22, 4);
2567 switch (Inst.getOpcode()) {
2568 case ARM::VLD2DUPd16: case ARM::VLD2DUPd32: case ARM::VLD2DUPd8:
2569 case ARM::VLD2DUPd16wb_fixed: case ARM::VLD2DUPd16wb_register:
2570 case ARM::VLD2DUPd32wb_fixed: case ARM::VLD2DUPd32wb_register:
2571 case ARM::VLD2DUPd8wb_fixed: case ARM::VLD2DUPd8wb_register:
2572 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2573 return MCDisassembler::Fail;
2575 case ARM::VLD2DUPd16x2: case ARM::VLD2DUPd32x2: case ARM::VLD2DUPd8x2:
2576 case ARM::VLD2DUPd16x2wb_fixed: case ARM::VLD2DUPd16x2wb_register:
2577 case ARM::VLD2DUPd32x2wb_fixed: case ARM::VLD2DUPd32x2wb_register:
2578 case ARM::VLD2DUPd8x2wb_fixed: case ARM::VLD2DUPd8x2wb_register:
2579 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
2580 return MCDisassembler::Fail;
2583 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2584 return MCDisassembler::Fail;
2589 Inst.addOperand(MCOperand::CreateImm(0));
2591 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2592 return MCDisassembler::Fail;
2593 Inst.addOperand(MCOperand::CreateImm(align));
2596 Inst.addOperand(MCOperand::CreateReg(0));
2597 else if (Rm != 0xF) {
2598 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2599 return MCDisassembler::Fail;
2602 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2603 return MCDisassembler::Fail;
2608 static DecodeStatus DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Insn,
2609 uint64_t Address, const void *Decoder) {
2610 DecodeStatus S = MCDisassembler::Success;
2612 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2613 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2614 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2615 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2616 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1;
2618 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2619 return MCDisassembler::Fail;
2620 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
2621 return MCDisassembler::Fail;
2622 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
2623 return MCDisassembler::Fail;
2625 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2626 return MCDisassembler::Fail;
2629 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2630 return MCDisassembler::Fail;
2631 Inst.addOperand(MCOperand::CreateImm(0));
2634 Inst.addOperand(MCOperand::CreateReg(0));
2635 else if (Rm != 0xF) {
2636 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2637 return MCDisassembler::Fail;
2643 static DecodeStatus DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Insn,
2644 uint64_t Address, const void *Decoder) {
2645 DecodeStatus S = MCDisassembler::Success;
2647 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2648 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2649 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2650 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2651 unsigned size = fieldFromInstruction32(Insn, 6, 2);
2652 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1;
2653 unsigned align = fieldFromInstruction32(Insn, 4, 1);
2668 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2669 return MCDisassembler::Fail;
2670 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
2671 return MCDisassembler::Fail;
2672 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
2673 return MCDisassembler::Fail;
2674 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder)))
2675 return MCDisassembler::Fail;
2677 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2678 return MCDisassembler::Fail;
2681 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2682 return MCDisassembler::Fail;
2683 Inst.addOperand(MCOperand::CreateImm(align));
2686 Inst.addOperand(MCOperand::CreateReg(0));
2687 else if (Rm != 0xF) {
2688 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2689 return MCDisassembler::Fail;
2696 DecodeNEONModImmInstruction(llvm::MCInst &Inst, unsigned Insn,
2697 uint64_t Address, const void *Decoder) {
2698 DecodeStatus S = MCDisassembler::Success;
2700 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2701 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2702 unsigned imm = fieldFromInstruction32(Insn, 0, 4);
2703 imm |= fieldFromInstruction32(Insn, 16, 3) << 4;
2704 imm |= fieldFromInstruction32(Insn, 24, 1) << 7;
2705 imm |= fieldFromInstruction32(Insn, 8, 4) << 8;
2706 imm |= fieldFromInstruction32(Insn, 5, 1) << 12;
2707 unsigned Q = fieldFromInstruction32(Insn, 6, 1);
2710 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
2711 return MCDisassembler::Fail;
2713 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2714 return MCDisassembler::Fail;
2717 Inst.addOperand(MCOperand::CreateImm(imm));
2719 switch (Inst.getOpcode()) {
2720 case ARM::VORRiv4i16:
2721 case ARM::VORRiv2i32:
2722 case ARM::VBICiv4i16:
2723 case ARM::VBICiv2i32:
2724 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2725 return MCDisassembler::Fail;
2727 case ARM::VORRiv8i16:
2728 case ARM::VORRiv4i32:
2729 case ARM::VBICiv8i16:
2730 case ARM::VBICiv4i32:
2731 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
2732 return MCDisassembler::Fail;
2741 static DecodeStatus DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned Insn,
2742 uint64_t Address, const void *Decoder) {
2743 DecodeStatus S = MCDisassembler::Success;
2745 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2746 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2747 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2748 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4;
2749 unsigned size = fieldFromInstruction32(Insn, 18, 2);
2751 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
2752 return MCDisassembler::Fail;
2753 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
2754 return MCDisassembler::Fail;
2755 Inst.addOperand(MCOperand::CreateImm(8 << size));
2760 static DecodeStatus DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned Val,
2761 uint64_t Address, const void *Decoder) {
2762 Inst.addOperand(MCOperand::CreateImm(8 - Val));
2763 return MCDisassembler::Success;
2766 static DecodeStatus DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned Val,
2767 uint64_t Address, const void *Decoder) {
2768 Inst.addOperand(MCOperand::CreateImm(16 - Val));
2769 return MCDisassembler::Success;
2772 static DecodeStatus DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned Val,
2773 uint64_t Address, const void *Decoder) {
2774 Inst.addOperand(MCOperand::CreateImm(32 - Val));
2775 return MCDisassembler::Success;
2778 static DecodeStatus DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned Val,
2779 uint64_t Address, const void *Decoder) {
2780 Inst.addOperand(MCOperand::CreateImm(64 - Val));
2781 return MCDisassembler::Success;
2784 static DecodeStatus DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn,
2785 uint64_t Address, const void *Decoder) {
2786 DecodeStatus S = MCDisassembler::Success;
2788 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2789 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2790 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2791 Rn |= fieldFromInstruction32(Insn, 7, 1) << 4;
2792 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2793 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4;
2794 unsigned op = fieldFromInstruction32(Insn, 6, 1);
2796 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2797 return MCDisassembler::Fail;
2799 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2800 return MCDisassembler::Fail; // Writeback
2803 switch (Inst.getOpcode()) {
2806 if (!Check(S, DecodeDPairRegisterClass(Inst, Rn, Address, Decoder)))
2807 return MCDisassembler::Fail;
2810 if (!Check(S, DecodeDPRRegisterClass(Inst, Rn, Address, Decoder)))
2811 return MCDisassembler::Fail;
2814 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
2815 return MCDisassembler::Fail;
2820 static DecodeStatus DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn,
2821 uint64_t Address, const void *Decoder) {
2822 DecodeStatus S = MCDisassembler::Success;
2824 unsigned dst = fieldFromInstruction16(Insn, 8, 3);
2825 unsigned imm = fieldFromInstruction16(Insn, 0, 8);
2827 if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder)))
2828 return MCDisassembler::Fail;
2830 switch(Inst.getOpcode()) {
2832 return MCDisassembler::Fail;
2834 break; // tADR does not explicitly represent the PC as an operand.
2836 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
2840 Inst.addOperand(MCOperand::CreateImm(imm));
2844 static DecodeStatus DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val,
2845 uint64_t Address, const void *Decoder) {
2846 Inst.addOperand(MCOperand::CreateImm(SignExtend32<12>(Val << 1)));
2847 return MCDisassembler::Success;
2850 static DecodeStatus DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val,
2851 uint64_t Address, const void *Decoder) {
2852 Inst.addOperand(MCOperand::CreateImm(SignExtend32<21>(Val)));
2853 return MCDisassembler::Success;
2856 static DecodeStatus DecodeThumbCmpBROperand(llvm::MCInst &Inst, unsigned Val,
2857 uint64_t Address, const void *Decoder) {
2858 Inst.addOperand(MCOperand::CreateImm(SignExtend32<7>(Val << 1)));
2859 return MCDisassembler::Success;
2862 static DecodeStatus DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned Val,
2863 uint64_t Address, const void *Decoder) {
2864 DecodeStatus S = MCDisassembler::Success;
2866 unsigned Rn = fieldFromInstruction32(Val, 0, 3);
2867 unsigned Rm = fieldFromInstruction32(Val, 3, 3);
2869 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
2870 return MCDisassembler::Fail;
2871 if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder)))
2872 return MCDisassembler::Fail;
2877 static DecodeStatus DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned Val,
2878 uint64_t Address, const void *Decoder) {
2879 DecodeStatus S = MCDisassembler::Success;
2881 unsigned Rn = fieldFromInstruction32(Val, 0, 3);
2882 unsigned imm = fieldFromInstruction32(Val, 3, 5);
2884 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
2885 return MCDisassembler::Fail;
2886 Inst.addOperand(MCOperand::CreateImm(imm));
2891 static DecodeStatus DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned Val,
2892 uint64_t Address, const void *Decoder) {
2893 unsigned imm = Val << 2;
2895 Inst.addOperand(MCOperand::CreateImm(imm));
2896 tryAddingPcLoadReferenceComment(Address, (Address & ~2u) + imm + 4, Decoder);
2898 return MCDisassembler::Success;
2901 static DecodeStatus DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val,
2902 uint64_t Address, const void *Decoder) {
2903 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
2904 Inst.addOperand(MCOperand::CreateImm(Val));
2906 return MCDisassembler::Success;
2909 static DecodeStatus DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned Val,
2910 uint64_t Address, const void *Decoder) {
2911 DecodeStatus S = MCDisassembler::Success;
2913 unsigned Rn = fieldFromInstruction32(Val, 6, 4);
2914 unsigned Rm = fieldFromInstruction32(Val, 2, 4);
2915 unsigned imm = fieldFromInstruction32(Val, 0, 2);
2917 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2918 return MCDisassembler::Fail;
2919 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
2920 return MCDisassembler::Fail;
2921 Inst.addOperand(MCOperand::CreateImm(imm));
2926 static DecodeStatus DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Insn,
2927 uint64_t Address, const void *Decoder) {
2928 DecodeStatus S = MCDisassembler::Success;
2930 switch (Inst.getOpcode()) {
2936 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
2937 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
2938 return MCDisassembler::Fail;
2942 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2944 switch (Inst.getOpcode()) {
2946 Inst.setOpcode(ARM::t2LDRBpci);
2949 Inst.setOpcode(ARM::t2LDRHpci);
2952 Inst.setOpcode(ARM::t2LDRSHpci);
2955 Inst.setOpcode(ARM::t2LDRSBpci);
2958 Inst.setOpcode(ARM::t2PLDi12);
2959 Inst.addOperand(MCOperand::CreateReg(ARM::PC));
2962 return MCDisassembler::Fail;
2965 int imm = fieldFromInstruction32(Insn, 0, 12);
2966 if (!fieldFromInstruction32(Insn, 23, 1)) imm *= -1;
2967 Inst.addOperand(MCOperand::CreateImm(imm));
2972 unsigned addrmode = fieldFromInstruction32(Insn, 4, 2);
2973 addrmode |= fieldFromInstruction32(Insn, 0, 4) << 2;
2974 addrmode |= fieldFromInstruction32(Insn, 16, 4) << 6;
2975 if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder)))
2976 return MCDisassembler::Fail;
2981 static DecodeStatus DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val,
2982 uint64_t Address, const void *Decoder) {
2983 int imm = Val & 0xFF;
2984 if (!(Val & 0x100)) imm *= -1;
2985 Inst.addOperand(MCOperand::CreateImm(imm << 2));
2987 return MCDisassembler::Success;
2990 static DecodeStatus DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned Val,
2991 uint64_t Address, const void *Decoder) {
2992 DecodeStatus S = MCDisassembler::Success;
2994 unsigned Rn = fieldFromInstruction32(Val, 9, 4);
2995 unsigned imm = fieldFromInstruction32(Val, 0, 9);
2997 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2998 return MCDisassembler::Fail;
2999 if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder)))
3000 return MCDisassembler::Fail;
3005 static DecodeStatus DecodeT2AddrModeImm0_1020s4(llvm::MCInst &Inst,unsigned Val,
3006 uint64_t Address, const void *Decoder) {
3007 DecodeStatus S = MCDisassembler::Success;
3009 unsigned Rn = fieldFromInstruction32(Val, 8, 4);
3010 unsigned imm = fieldFromInstruction32(Val, 0, 8);
3012 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
3013 return MCDisassembler::Fail;
3015 Inst.addOperand(MCOperand::CreateImm(imm));
3020 static DecodeStatus DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val,
3021 uint64_t Address, const void *Decoder) {
3022 int imm = Val & 0xFF;
3025 else if (!(Val & 0x100))
3027 Inst.addOperand(MCOperand::CreateImm(imm));
3029 return MCDisassembler::Success;
3033 static DecodeStatus DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val,
3034 uint64_t Address, const void *Decoder) {
3035 DecodeStatus S = MCDisassembler::Success;
3037 unsigned Rn = fieldFromInstruction32(Val, 9, 4);
3038 unsigned imm = fieldFromInstruction32(Val, 0, 9);
3040 // Some instructions always use an additive offset.
3041 switch (Inst.getOpcode()) {
3056 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3057 return MCDisassembler::Fail;
3058 if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder)))
3059 return MCDisassembler::Fail;
3064 static DecodeStatus DecodeT2LdStPre(llvm::MCInst &Inst, unsigned Insn,
3065 uint64_t Address, const void *Decoder) {
3066 DecodeStatus S = MCDisassembler::Success;
3068 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3069 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3070 unsigned addr = fieldFromInstruction32(Insn, 0, 8);
3071 addr |= fieldFromInstruction32(Insn, 9, 1) << 8;
3073 unsigned load = fieldFromInstruction32(Insn, 20, 1);
3076 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3077 return MCDisassembler::Fail;
3080 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
3081 return MCDisassembler::Fail;
3084 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3085 return MCDisassembler::Fail;
3088 if (!Check(S, DecodeT2AddrModeImm8(Inst, addr, Address, Decoder)))
3089 return MCDisassembler::Fail;
3094 static DecodeStatus DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val,
3095 uint64_t Address, const void *Decoder) {
3096 DecodeStatus S = MCDisassembler::Success;
3098 unsigned Rn = fieldFromInstruction32(Val, 13, 4);
3099 unsigned imm = fieldFromInstruction32(Val, 0, 12);
3101 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3102 return MCDisassembler::Fail;
3103 Inst.addOperand(MCOperand::CreateImm(imm));
3109 static DecodeStatus DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Insn,
3110 uint64_t Address, const void *Decoder) {
3111 unsigned imm = fieldFromInstruction16(Insn, 0, 7);
3113 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3114 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3115 Inst.addOperand(MCOperand::CreateImm(imm));
3117 return MCDisassembler::Success;
3120 static DecodeStatus DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn,
3121 uint64_t Address, const void *Decoder) {
3122 DecodeStatus S = MCDisassembler::Success;
3124 if (Inst.getOpcode() == ARM::tADDrSP) {
3125 unsigned Rdm = fieldFromInstruction16(Insn, 0, 3);
3126 Rdm |= fieldFromInstruction16(Insn, 7, 1) << 3;
3128 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
3129 return MCDisassembler::Fail;
3130 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
3131 return MCDisassembler::Fail;
3132 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3133 } else if (Inst.getOpcode() == ARM::tADDspr) {
3134 unsigned Rm = fieldFromInstruction16(Insn, 3, 4);
3136 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3137 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3138 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3139 return MCDisassembler::Fail;
3145 static DecodeStatus DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn,
3146 uint64_t Address, const void *Decoder) {
3147 unsigned imod = fieldFromInstruction16(Insn, 4, 1) | 0x2;
3148 unsigned flags = fieldFromInstruction16(Insn, 0, 3);
3150 Inst.addOperand(MCOperand::CreateImm(imod));
3151 Inst.addOperand(MCOperand::CreateImm(flags));
3153 return MCDisassembler::Success;
3156 static DecodeStatus DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn,
3157 uint64_t Address, const void *Decoder) {
3158 DecodeStatus S = MCDisassembler::Success;
3159 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3160 unsigned add = fieldFromInstruction32(Insn, 4, 1);
3162 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3163 return MCDisassembler::Fail;
3164 Inst.addOperand(MCOperand::CreateImm(add));
3169 static DecodeStatus DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Val,
3170 uint64_t Address, const void *Decoder) {
3171 if (!tryAddingSymbolicOperand(Address,
3172 (Address & ~2u) + SignExtend32<22>(Val << 1) + 4,
3173 true, 4, Inst, Decoder))
3174 Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1)));
3175 return MCDisassembler::Success;
3178 static DecodeStatus DecodeCoprocessor(llvm::MCInst &Inst, unsigned Val,
3179 uint64_t Address, const void *Decoder) {
3180 if (Val == 0xA || Val == 0xB)
3181 return MCDisassembler::Fail;
3183 Inst.addOperand(MCOperand::CreateImm(Val));
3184 return MCDisassembler::Success;
3188 DecodeThumbTableBranch(llvm::MCInst &Inst, unsigned Insn,
3189 uint64_t Address, const void *Decoder) {
3190 DecodeStatus S = MCDisassembler::Success;
3192 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3193 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3195 if (Rn == ARM::SP) S = MCDisassembler::SoftFail;
3196 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3197 return MCDisassembler::Fail;
3198 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
3199 return MCDisassembler::Fail;
3204 DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Insn,
3205 uint64_t Address, const void *Decoder) {
3206 DecodeStatus S = MCDisassembler::Success;
3208 unsigned pred = fieldFromInstruction32(Insn, 22, 4);
3209 if (pred == 0xE || pred == 0xF) {
3210 unsigned opc = fieldFromInstruction32(Insn, 4, 28);
3213 return MCDisassembler::Fail;
3215 Inst.setOpcode(ARM::t2DSB);
3218 Inst.setOpcode(ARM::t2DMB);
3221 Inst.setOpcode(ARM::t2ISB);
3225 unsigned imm = fieldFromInstruction32(Insn, 0, 4);
3226 return DecodeMemBarrierOption(Inst, imm, Address, Decoder);
3229 unsigned brtarget = fieldFromInstruction32(Insn, 0, 11) << 1;
3230 brtarget |= fieldFromInstruction32(Insn, 11, 1) << 19;
3231 brtarget |= fieldFromInstruction32(Insn, 13, 1) << 18;
3232 brtarget |= fieldFromInstruction32(Insn, 16, 6) << 12;
3233 brtarget |= fieldFromInstruction32(Insn, 26, 1) << 20;
3235 if (!Check(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder)))
3236 return MCDisassembler::Fail;
3237 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3238 return MCDisassembler::Fail;
3243 // Decode a shifted immediate operand. These basically consist
3244 // of an 8-bit value, and a 4-bit directive that specifies either
3245 // a splat operation or a rotation.
3246 static DecodeStatus DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val,
3247 uint64_t Address, const void *Decoder) {
3248 unsigned ctrl = fieldFromInstruction32(Val, 10, 2);
3250 unsigned byte = fieldFromInstruction32(Val, 8, 2);
3251 unsigned imm = fieldFromInstruction32(Val, 0, 8);
3254 Inst.addOperand(MCOperand::CreateImm(imm));
3257 Inst.addOperand(MCOperand::CreateImm((imm << 16) | imm));
3260 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 8)));
3263 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 16) |
3268 unsigned unrot = fieldFromInstruction32(Val, 0, 7) | 0x80;
3269 unsigned rot = fieldFromInstruction32(Val, 7, 5);
3270 unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31));
3271 Inst.addOperand(MCOperand::CreateImm(imm));
3274 return MCDisassembler::Success;
3278 DecodeThumbBCCTargetOperand(llvm::MCInst &Inst, unsigned Val,
3279 uint64_t Address, const void *Decoder){
3280 Inst.addOperand(MCOperand::CreateImm(Val << 1));
3281 return MCDisassembler::Success;
3284 static DecodeStatus DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val,
3285 uint64_t Address, const void *Decoder){
3286 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<22>(Val<<1) + 4,
3287 true, 4, Inst, Decoder))
3288 Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1)));
3289 return MCDisassembler::Success;
3292 static DecodeStatus DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Val,
3293 uint64_t Address, const void *Decoder) {
3296 return MCDisassembler::Fail;
3308 Inst.addOperand(MCOperand::CreateImm(Val));
3309 return MCDisassembler::Success;
3312 static DecodeStatus DecodeMSRMask(llvm::MCInst &Inst, unsigned Val,
3313 uint64_t Address, const void *Decoder) {
3314 if (!Val) return MCDisassembler::Fail;
3315 Inst.addOperand(MCOperand::CreateImm(Val));
3316 return MCDisassembler::Success;
3319 static DecodeStatus DecodeDoubleRegLoad(llvm::MCInst &Inst, unsigned Insn,
3320 uint64_t Address, const void *Decoder) {
3321 DecodeStatus S = MCDisassembler::Success;
3323 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3324 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3325 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3327 if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return MCDisassembler::Fail;
3329 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3330 return MCDisassembler::Fail;
3331 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
3332 return MCDisassembler::Fail;
3333 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3334 return MCDisassembler::Fail;
3335 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3336 return MCDisassembler::Fail;
3342 static DecodeStatus DecodeDoubleRegStore(llvm::MCInst &Inst, unsigned Insn,
3343 uint64_t Address, const void *Decoder){
3344 DecodeStatus S = MCDisassembler::Success;
3346 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3347 unsigned Rt = fieldFromInstruction32(Insn, 0, 4);
3348 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3349 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3351 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
3352 return MCDisassembler::Fail;
3354 if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return MCDisassembler::Fail;
3355 if (Rd == Rn || Rd == Rt || Rd == Rt+1) return MCDisassembler::Fail;
3357 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3358 return MCDisassembler::Fail;
3359 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
3360 return MCDisassembler::Fail;
3361 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3362 return MCDisassembler::Fail;
3363 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3364 return MCDisassembler::Fail;
3369 static DecodeStatus DecodeLDRPreImm(llvm::MCInst &Inst, unsigned Insn,
3370 uint64_t Address, const void *Decoder) {
3371 DecodeStatus S = MCDisassembler::Success;
3373 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3374 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3375 unsigned imm = fieldFromInstruction32(Insn, 0, 12);
3376 imm |= fieldFromInstruction32(Insn, 16, 4) << 13;
3377 imm |= fieldFromInstruction32(Insn, 23, 1) << 12;
3378 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3380 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
3382 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3383 return MCDisassembler::Fail;
3384 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3385 return MCDisassembler::Fail;
3386 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
3387 return MCDisassembler::Fail;
3388 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3389 return MCDisassembler::Fail;
3394 static DecodeStatus DecodeLDRPreReg(llvm::MCInst &Inst, unsigned Insn,
3395 uint64_t Address, const void *Decoder) {
3396 DecodeStatus S = MCDisassembler::Success;
3398 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3399 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3400 unsigned imm = fieldFromInstruction32(Insn, 0, 12);
3401 imm |= fieldFromInstruction32(Insn, 16, 4) << 13;
3402 imm |= fieldFromInstruction32(Insn, 23, 1) << 12;
3403 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3404 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3406 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
3407 if (Rm == 0xF) S = MCDisassembler::SoftFail;
3409 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3410 return MCDisassembler::Fail;
3411 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3412 return MCDisassembler::Fail;
3413 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
3414 return MCDisassembler::Fail;
3415 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3416 return MCDisassembler::Fail;
3422 static DecodeStatus DecodeSTRPreImm(llvm::MCInst &Inst, unsigned Insn,
3423 uint64_t Address, const void *Decoder) {
3424 DecodeStatus S = MCDisassembler::Success;
3426 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3427 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3428 unsigned imm = fieldFromInstruction32(Insn, 0, 12);
3429 imm |= fieldFromInstruction32(Insn, 16, 4) << 13;
3430 imm |= fieldFromInstruction32(Insn, 23, 1) << 12;
3431 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3433 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
3435 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3436 return MCDisassembler::Fail;
3437 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3438 return MCDisassembler::Fail;
3439 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
3440 return MCDisassembler::Fail;
3441 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3442 return MCDisassembler::Fail;
3447 static DecodeStatus DecodeSTRPreReg(llvm::MCInst &Inst, unsigned Insn,
3448 uint64_t Address, const void *Decoder) {
3449 DecodeStatus S = MCDisassembler::Success;
3451 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3452 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3453 unsigned imm = fieldFromInstruction32(Insn, 0, 12);
3454 imm |= fieldFromInstruction32(Insn, 16, 4) << 13;
3455 imm |= fieldFromInstruction32(Insn, 23, 1) << 12;
3456 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3458 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
3460 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3461 return MCDisassembler::Fail;
3462 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3463 return MCDisassembler::Fail;
3464 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
3465 return MCDisassembler::Fail;
3466 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3467 return MCDisassembler::Fail;
3472 static DecodeStatus DecodeVLD1LN(llvm::MCInst &Inst, unsigned Insn,
3473 uint64_t Address, const void *Decoder) {
3474 DecodeStatus S = MCDisassembler::Success;
3476 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3477 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3478 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3479 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3480 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3486 return MCDisassembler::Fail;
3488 if (fieldFromInstruction32(Insn, 4, 1))
3489 return MCDisassembler::Fail; // UNDEFINED
3490 index = fieldFromInstruction32(Insn, 5, 3);
3493 if (fieldFromInstruction32(Insn, 5, 1))
3494 return MCDisassembler::Fail; // UNDEFINED
3495 index = fieldFromInstruction32(Insn, 6, 2);
3496 if (fieldFromInstruction32(Insn, 4, 1))
3500 if (fieldFromInstruction32(Insn, 6, 1))
3501 return MCDisassembler::Fail; // UNDEFINED
3502 index = fieldFromInstruction32(Insn, 7, 1);
3503 if (fieldFromInstruction32(Insn, 4, 2) != 0)
3507 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3508 return MCDisassembler::Fail;
3509 if (Rm != 0xF) { // Writeback
3510 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3511 return MCDisassembler::Fail;
3513 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3514 return MCDisassembler::Fail;
3515 Inst.addOperand(MCOperand::CreateImm(align));
3518 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3519 return MCDisassembler::Fail;
3521 Inst.addOperand(MCOperand::CreateReg(0));
3524 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3525 return MCDisassembler::Fail;
3526 Inst.addOperand(MCOperand::CreateImm(index));
3531 static DecodeStatus DecodeVST1LN(llvm::MCInst &Inst, unsigned Insn,
3532 uint64_t Address, const void *Decoder) {
3533 DecodeStatus S = MCDisassembler::Success;
3535 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3536 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3537 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3538 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3539 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3545 return MCDisassembler::Fail;
3547 if (fieldFromInstruction32(Insn, 4, 1))
3548 return MCDisassembler::Fail; // UNDEFINED
3549 index = fieldFromInstruction32(Insn, 5, 3);
3552 if (fieldFromInstruction32(Insn, 5, 1))
3553 return MCDisassembler::Fail; // UNDEFINED
3554 index = fieldFromInstruction32(Insn, 6, 2);
3555 if (fieldFromInstruction32(Insn, 4, 1))
3559 if (fieldFromInstruction32(Insn, 6, 1))
3560 return MCDisassembler::Fail; // UNDEFINED
3561 index = fieldFromInstruction32(Insn, 7, 1);
3562 if (fieldFromInstruction32(Insn, 4, 2) != 0)
3566 if (Rm != 0xF) { // Writeback
3567 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3568 return MCDisassembler::Fail;
3570 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3571 return MCDisassembler::Fail;
3572 Inst.addOperand(MCOperand::CreateImm(align));
3575 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3576 return MCDisassembler::Fail;
3578 Inst.addOperand(MCOperand::CreateReg(0));
3581 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3582 return MCDisassembler::Fail;
3583 Inst.addOperand(MCOperand::CreateImm(index));
3589 static DecodeStatus DecodeVLD2LN(llvm::MCInst &Inst, unsigned Insn,
3590 uint64_t Address, const void *Decoder) {
3591 DecodeStatus S = MCDisassembler::Success;
3593 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3594 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3595 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3596 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3597 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3604 return MCDisassembler::Fail;
3606 index = fieldFromInstruction32(Insn, 5, 3);
3607 if (fieldFromInstruction32(Insn, 4, 1))
3611 index = fieldFromInstruction32(Insn, 6, 2);
3612 if (fieldFromInstruction32(Insn, 4, 1))
3614 if (fieldFromInstruction32(Insn, 5, 1))
3618 if (fieldFromInstruction32(Insn, 5, 1))
3619 return MCDisassembler::Fail; // UNDEFINED
3620 index = fieldFromInstruction32(Insn, 7, 1);
3621 if (fieldFromInstruction32(Insn, 4, 1) != 0)
3623 if (fieldFromInstruction32(Insn, 6, 1))
3628 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3629 return MCDisassembler::Fail;
3630 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3631 return MCDisassembler::Fail;
3632 if (Rm != 0xF) { // Writeback
3633 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3634 return MCDisassembler::Fail;
3636 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3637 return MCDisassembler::Fail;
3638 Inst.addOperand(MCOperand::CreateImm(align));
3641 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3642 return MCDisassembler::Fail;
3644 Inst.addOperand(MCOperand::CreateReg(0));
3647 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3648 return MCDisassembler::Fail;
3649 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3650 return MCDisassembler::Fail;
3651 Inst.addOperand(MCOperand::CreateImm(index));
3656 static DecodeStatus DecodeVST2LN(llvm::MCInst &Inst, unsigned Insn,
3657 uint64_t Address, const void *Decoder) {
3658 DecodeStatus S = MCDisassembler::Success;
3660 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3661 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3662 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3663 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3664 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3671 return MCDisassembler::Fail;
3673 index = fieldFromInstruction32(Insn, 5, 3);
3674 if (fieldFromInstruction32(Insn, 4, 1))
3678 index = fieldFromInstruction32(Insn, 6, 2);
3679 if (fieldFromInstruction32(Insn, 4, 1))
3681 if (fieldFromInstruction32(Insn, 5, 1))
3685 if (fieldFromInstruction32(Insn, 5, 1))
3686 return MCDisassembler::Fail; // UNDEFINED
3687 index = fieldFromInstruction32(Insn, 7, 1);
3688 if (fieldFromInstruction32(Insn, 4, 1) != 0)
3690 if (fieldFromInstruction32(Insn, 6, 1))
3695 if (Rm != 0xF) { // Writeback
3696 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3697 return MCDisassembler::Fail;
3699 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3700 return MCDisassembler::Fail;
3701 Inst.addOperand(MCOperand::CreateImm(align));
3704 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3705 return MCDisassembler::Fail;
3707 Inst.addOperand(MCOperand::CreateReg(0));
3710 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3711 return MCDisassembler::Fail;
3712 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3713 return MCDisassembler::Fail;
3714 Inst.addOperand(MCOperand::CreateImm(index));
3720 static DecodeStatus DecodeVLD3LN(llvm::MCInst &Inst, unsigned Insn,
3721 uint64_t Address, const void *Decoder) {
3722 DecodeStatus S = MCDisassembler::Success;
3724 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3725 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3726 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3727 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3728 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3735 return MCDisassembler::Fail;
3737 if (fieldFromInstruction32(Insn, 4, 1))
3738 return MCDisassembler::Fail; // UNDEFINED
3739 index = fieldFromInstruction32(Insn, 5, 3);
3742 if (fieldFromInstruction32(Insn, 4, 1))
3743 return MCDisassembler::Fail; // UNDEFINED
3744 index = fieldFromInstruction32(Insn, 6, 2);
3745 if (fieldFromInstruction32(Insn, 5, 1))
3749 if (fieldFromInstruction32(Insn, 4, 2))
3750 return MCDisassembler::Fail; // UNDEFINED
3751 index = fieldFromInstruction32(Insn, 7, 1);
3752 if (fieldFromInstruction32(Insn, 6, 1))
3757 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3758 return MCDisassembler::Fail;
3759 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3760 return MCDisassembler::Fail;
3761 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
3762 return MCDisassembler::Fail;
3764 if (Rm != 0xF) { // Writeback
3765 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3766 return MCDisassembler::Fail;
3768 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3769 return MCDisassembler::Fail;
3770 Inst.addOperand(MCOperand::CreateImm(align));
3773 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3774 return MCDisassembler::Fail;
3776 Inst.addOperand(MCOperand::CreateReg(0));
3779 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3780 return MCDisassembler::Fail;
3781 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3782 return MCDisassembler::Fail;
3783 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
3784 return MCDisassembler::Fail;
3785 Inst.addOperand(MCOperand::CreateImm(index));
3790 static DecodeStatus DecodeVST3LN(llvm::MCInst &Inst, unsigned Insn,
3791 uint64_t Address, const void *Decoder) {
3792 DecodeStatus S = MCDisassembler::Success;
3794 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3795 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3796 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3797 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3798 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3805 return MCDisassembler::Fail;
3807 if (fieldFromInstruction32(Insn, 4, 1))
3808 return MCDisassembler::Fail; // UNDEFINED
3809 index = fieldFromInstruction32(Insn, 5, 3);
3812 if (fieldFromInstruction32(Insn, 4, 1))
3813 return MCDisassembler::Fail; // UNDEFINED
3814 index = fieldFromInstruction32(Insn, 6, 2);
3815 if (fieldFromInstruction32(Insn, 5, 1))
3819 if (fieldFromInstruction32(Insn, 4, 2))
3820 return MCDisassembler::Fail; // UNDEFINED
3821 index = fieldFromInstruction32(Insn, 7, 1);
3822 if (fieldFromInstruction32(Insn, 6, 1))
3827 if (Rm != 0xF) { // Writeback
3828 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3829 return MCDisassembler::Fail;
3831 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3832 return MCDisassembler::Fail;
3833 Inst.addOperand(MCOperand::CreateImm(align));
3836 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3837 return MCDisassembler::Fail;
3839 Inst.addOperand(MCOperand::CreateReg(0));
3842 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3843 return MCDisassembler::Fail;
3844 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3845 return MCDisassembler::Fail;
3846 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
3847 return MCDisassembler::Fail;
3848 Inst.addOperand(MCOperand::CreateImm(index));
3854 static DecodeStatus DecodeVLD4LN(llvm::MCInst &Inst, unsigned Insn,
3855 uint64_t Address, const void *Decoder) {
3856 DecodeStatus S = MCDisassembler::Success;
3858 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3859 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3860 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3861 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3862 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3869 return MCDisassembler::Fail;
3871 if (fieldFromInstruction32(Insn, 4, 1))
3873 index = fieldFromInstruction32(Insn, 5, 3);
3876 if (fieldFromInstruction32(Insn, 4, 1))
3878 index = fieldFromInstruction32(Insn, 6, 2);
3879 if (fieldFromInstruction32(Insn, 5, 1))
3883 if (fieldFromInstruction32(Insn, 4, 2))
3884 align = 4 << fieldFromInstruction32(Insn, 4, 2);
3885 index = fieldFromInstruction32(Insn, 7, 1);
3886 if (fieldFromInstruction32(Insn, 6, 1))
3891 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3892 return MCDisassembler::Fail;
3893 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3894 return MCDisassembler::Fail;
3895 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
3896 return MCDisassembler::Fail;
3897 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
3898 return MCDisassembler::Fail;
3900 if (Rm != 0xF) { // Writeback
3901 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3902 return MCDisassembler::Fail;
3904 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3905 return MCDisassembler::Fail;
3906 Inst.addOperand(MCOperand::CreateImm(align));
3909 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3910 return MCDisassembler::Fail;
3912 Inst.addOperand(MCOperand::CreateReg(0));
3915 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3916 return MCDisassembler::Fail;
3917 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3918 return MCDisassembler::Fail;
3919 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
3920 return MCDisassembler::Fail;
3921 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
3922 return MCDisassembler::Fail;
3923 Inst.addOperand(MCOperand::CreateImm(index));
3928 static DecodeStatus DecodeVST4LN(llvm::MCInst &Inst, unsigned Insn,
3929 uint64_t Address, const void *Decoder) {
3930 DecodeStatus S = MCDisassembler::Success;
3932 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3933 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3934 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3935 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3936 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3943 return MCDisassembler::Fail;
3945 if (fieldFromInstruction32(Insn, 4, 1))
3947 index = fieldFromInstruction32(Insn, 5, 3);
3950 if (fieldFromInstruction32(Insn, 4, 1))
3952 index = fieldFromInstruction32(Insn, 6, 2);
3953 if (fieldFromInstruction32(Insn, 5, 1))
3957 if (fieldFromInstruction32(Insn, 4, 2))
3958 align = 4 << fieldFromInstruction32(Insn, 4, 2);
3959 index = fieldFromInstruction32(Insn, 7, 1);
3960 if (fieldFromInstruction32(Insn, 6, 1))
3965 if (Rm != 0xF) { // Writeback
3966 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3967 return MCDisassembler::Fail;
3969 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3970 return MCDisassembler::Fail;
3971 Inst.addOperand(MCOperand::CreateImm(align));
3974 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3975 return MCDisassembler::Fail;
3977 Inst.addOperand(MCOperand::CreateReg(0));
3980 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3981 return MCDisassembler::Fail;
3982 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3983 return MCDisassembler::Fail;
3984 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
3985 return MCDisassembler::Fail;
3986 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
3987 return MCDisassembler::Fail;
3988 Inst.addOperand(MCOperand::CreateImm(index));
3993 static DecodeStatus DecodeVMOVSRR(llvm::MCInst &Inst, unsigned Insn,
3994 uint64_t Address, const void *Decoder) {
3995 DecodeStatus S = MCDisassembler::Success;
3996 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3997 unsigned Rt2 = fieldFromInstruction32(Insn, 16, 4);
3998 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3999 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
4000 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4;
4002 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
4003 S = MCDisassembler::SoftFail;
4005 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)))
4006 return MCDisassembler::Fail;
4007 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
4008 return MCDisassembler::Fail;
4009 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder)))
4010 return MCDisassembler::Fail;
4011 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
4012 return MCDisassembler::Fail;
4013 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4014 return MCDisassembler::Fail;
4019 static DecodeStatus DecodeVMOVRRS(llvm::MCInst &Inst, unsigned Insn,
4020 uint64_t Address, const void *Decoder) {
4021 DecodeStatus S = MCDisassembler::Success;
4022 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
4023 unsigned Rt2 = fieldFromInstruction32(Insn, 16, 4);
4024 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
4025 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
4026 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4;
4028 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
4029 S = MCDisassembler::SoftFail;
4031 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder)))
4032 return MCDisassembler::Fail;
4033 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
4034 return MCDisassembler::Fail;
4035 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)))
4036 return MCDisassembler::Fail;
4037 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
4038 return MCDisassembler::Fail;
4039 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4040 return MCDisassembler::Fail;
4045 static DecodeStatus DecodeIT(llvm::MCInst &Inst, unsigned Insn,
4046 uint64_t Address, const void *Decoder) {
4047 DecodeStatus S = MCDisassembler::Success;
4048 unsigned pred = fieldFromInstruction16(Insn, 4, 4);
4049 // The InstPrinter needs to have the low bit of the predicate in
4050 // the mask operand to be able to print it properly.
4051 unsigned mask = fieldFromInstruction16(Insn, 0, 5);
4055 S = MCDisassembler::SoftFail;
4058 if ((mask & 0xF) == 0) {
4059 // Preserve the high bit of the mask, which is the low bit of
4063 S = MCDisassembler::SoftFail;
4066 Inst.addOperand(MCOperand::CreateImm(pred));
4067 Inst.addOperand(MCOperand::CreateImm(mask));
4072 DecodeT2LDRDPreInstruction(llvm::MCInst &Inst, unsigned Insn,
4073 uint64_t Address, const void *Decoder) {
4074 DecodeStatus S = MCDisassembler::Success;
4076 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
4077 unsigned Rt2 = fieldFromInstruction32(Insn, 8, 4);
4078 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
4079 unsigned addr = fieldFromInstruction32(Insn, 0, 8);
4080 unsigned W = fieldFromInstruction32(Insn, 21, 1);
4081 unsigned U = fieldFromInstruction32(Insn, 23, 1);
4082 unsigned P = fieldFromInstruction32(Insn, 24, 1);
4083 bool writeback = (W == 1) | (P == 0);
4085 addr |= (U << 8) | (Rn << 9);
4087 if (writeback && (Rn == Rt || Rn == Rt2))
4088 Check(S, MCDisassembler::SoftFail);
4090 Check(S, MCDisassembler::SoftFail);
4093 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
4094 return MCDisassembler::Fail;
4096 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
4097 return MCDisassembler::Fail;
4098 // Writeback operand
4099 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
4100 return MCDisassembler::Fail;
4102 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
4103 return MCDisassembler::Fail;
4109 DecodeT2STRDPreInstruction(llvm::MCInst &Inst, unsigned Insn,
4110 uint64_t Address, const void *Decoder) {
4111 DecodeStatus S = MCDisassembler::Success;
4113 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
4114 unsigned Rt2 = fieldFromInstruction32(Insn, 8, 4);
4115 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
4116 unsigned addr = fieldFromInstruction32(Insn, 0, 8);
4117 unsigned W = fieldFromInstruction32(Insn, 21, 1);
4118 unsigned U = fieldFromInstruction32(Insn, 23, 1);
4119 unsigned P = fieldFromInstruction32(Insn, 24, 1);
4120 bool writeback = (W == 1) | (P == 0);
4122 addr |= (U << 8) | (Rn << 9);
4124 if (writeback && (Rn == Rt || Rn == Rt2))
4125 Check(S, MCDisassembler::SoftFail);
4127 // Writeback operand
4128 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
4129 return MCDisassembler::Fail;
4131 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
4132 return MCDisassembler::Fail;
4134 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
4135 return MCDisassembler::Fail;
4137 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
4138 return MCDisassembler::Fail;
4143 static DecodeStatus DecodeT2Adr(llvm::MCInst &Inst, uint32_t Insn,
4144 uint64_t Address, const void *Decoder) {
4145 unsigned sign1 = fieldFromInstruction32(Insn, 21, 1);
4146 unsigned sign2 = fieldFromInstruction32(Insn, 23, 1);
4147 if (sign1 != sign2) return MCDisassembler::Fail;
4149 unsigned Val = fieldFromInstruction32(Insn, 0, 8);
4150 Val |= fieldFromInstruction32(Insn, 12, 3) << 8;
4151 Val |= fieldFromInstruction32(Insn, 26, 1) << 11;
4153 Inst.addOperand(MCOperand::CreateImm(SignExtend32<13>(Val)));
4155 return MCDisassembler::Success;
4158 static DecodeStatus DecodeT2ShifterImmOperand(llvm::MCInst &Inst, uint32_t Val,
4160 const void *Decoder) {
4161 DecodeStatus S = MCDisassembler::Success;
4163 // Shift of "asr #32" is not allowed in Thumb2 mode.
4164 if (Val == 0x20) S = MCDisassembler::SoftFail;
4165 Inst.addOperand(MCOperand::CreateImm(Val));
4169 static DecodeStatus DecodeSwap(llvm::MCInst &Inst, unsigned Insn,
4170 uint64_t Address, const void *Decoder) {
4171 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
4172 unsigned Rt2 = fieldFromInstruction32(Insn, 0, 4);
4173 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
4174 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
4177 return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
4179 DecodeStatus S = MCDisassembler::Success;
4180 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
4181 return MCDisassembler::Fail;
4182 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder)))
4183 return MCDisassembler::Fail;
4184 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
4185 return MCDisassembler::Fail;
4186 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4187 return MCDisassembler::Fail;
4192 static DecodeStatus DecodeVCVTD(llvm::MCInst &Inst, unsigned Insn,
4193 uint64_t Address, const void *Decoder) {
4194 unsigned Vd = (fieldFromInstruction32(Insn, 12, 4) << 0);
4195 Vd |= (fieldFromInstruction32(Insn, 22, 1) << 4);
4196 unsigned Vm = (fieldFromInstruction32(Insn, 0, 4) << 0);
4197 Vm |= (fieldFromInstruction32(Insn, 5, 1) << 4);
4198 unsigned imm = fieldFromInstruction32(Insn, 16, 6);
4199 unsigned cmode = fieldFromInstruction32(Insn, 8, 4);
4201 DecodeStatus S = MCDisassembler::Success;
4203 // VMOVv2f32 is ambiguous with these decodings.
4204 if (!(imm & 0x38) && cmode == 0xF) {
4205 Inst.setOpcode(ARM::VMOVv2f32);
4206 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder);
4209 if (!(imm & 0x20)) Check(S, MCDisassembler::SoftFail);
4211 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
4212 return MCDisassembler::Fail;
4213 if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder)))
4214 return MCDisassembler::Fail;
4215 Inst.addOperand(MCOperand::CreateImm(64 - imm));
4220 static DecodeStatus DecodeVCVTQ(llvm::MCInst &Inst, unsigned Insn,
4221 uint64_t Address, const void *Decoder) {
4222 unsigned Vd = (fieldFromInstruction32(Insn, 12, 4) << 0);
4223 Vd |= (fieldFromInstruction32(Insn, 22, 1) << 4);
4224 unsigned Vm = (fieldFromInstruction32(Insn, 0, 4) << 0);
4225 Vm |= (fieldFromInstruction32(Insn, 5, 1) << 4);
4226 unsigned imm = fieldFromInstruction32(Insn, 16, 6);
4227 unsigned cmode = fieldFromInstruction32(Insn, 8, 4);
4229 DecodeStatus S = MCDisassembler::Success;
4231 // VMOVv4f32 is ambiguous with these decodings.
4232 if (!(imm & 0x38) && cmode == 0xF) {
4233 Inst.setOpcode(ARM::VMOVv4f32);
4234 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder);
4237 if (!(imm & 0x20)) Check(S, MCDisassembler::SoftFail);
4239 if (!Check(S, DecodeQPRRegisterClass(Inst, Vd, Address, Decoder)))
4240 return MCDisassembler::Fail;
4241 if (!Check(S, DecodeQPRRegisterClass(Inst, Vm, Address, Decoder)))
4242 return MCDisassembler::Fail;
4243 Inst.addOperand(MCOperand::CreateImm(64 - imm));