1 //===-- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA --------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "llvm/MC/MCDisassembler.h"
11 #include "MCTargetDesc/ARMAddressingModes.h"
12 #include "MCTargetDesc/ARMBaseInfo.h"
13 #include "MCTargetDesc/ARMMCExpr.h"
14 #include "llvm/MC/MCContext.h"
15 #include "llvm/MC/MCExpr.h"
16 #include "llvm/MC/MCFixedLenDisassembler.h"
17 #include "llvm/MC/MCInst.h"
18 #include "llvm/MC/MCInstrDesc.h"
19 #include "llvm/MC/MCSubtargetInfo.h"
20 #include "llvm/Support/Debug.h"
21 #include "llvm/Support/ErrorHandling.h"
22 #include "llvm/Support/LEB128.h"
23 #include "llvm/Support/TargetRegistry.h"
24 #include "llvm/Support/raw_ostream.h"
29 #define DEBUG_TYPE "arm-disassembler"
31 typedef MCDisassembler::DecodeStatus DecodeStatus;
34 // Handles the condition code status of instructions in IT blocks
38 // Returns the condition code for instruction in IT block
40 unsigned CC = ARMCC::AL;
46 // Advances the IT block state to the next T or E
47 void advanceITState() {
51 // Returns true if the current instruction is in an IT block
52 bool instrInITBlock() {
53 return !ITStates.empty();
56 // Returns true if current instruction is the last instruction in an IT block
57 bool instrLastInITBlock() {
58 return ITStates.size() == 1;
61 // Called when decoding an IT instruction. Sets the IT state for the following
62 // instructions that for the IT block. Firstcond and Mask correspond to the
63 // fields in the IT instruction encoding.
64 void setITState(char Firstcond, char Mask) {
65 // (3 - the number of trailing zeros) is the number of then / else.
66 unsigned CondBit0 = Firstcond & 1;
67 unsigned NumTZ = countTrailingZeros<uint8_t>(Mask);
68 unsigned char CCBits = static_cast<unsigned char>(Firstcond & 0xf);
69 assert(NumTZ <= 3 && "Invalid IT mask!");
70 // push condition codes onto the stack the correct order for the pops
71 for (unsigned Pos = NumTZ+1; Pos <= 3; ++Pos) {
72 bool T = ((Mask >> Pos) & 1) == CondBit0;
74 ITStates.push_back(CCBits);
76 ITStates.push_back(CCBits ^ 1);
78 ITStates.push_back(CCBits);
82 std::vector<unsigned char> ITStates;
87 /// ARM disassembler for all ARM platforms.
88 class ARMDisassembler : public MCDisassembler {
90 ARMDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) :
91 MCDisassembler(STI, Ctx) {
96 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
97 ArrayRef<uint8_t> Bytes, uint64_t Address,
99 raw_ostream &CStream) const override;
102 /// Thumb disassembler for all Thumb platforms.
103 class ThumbDisassembler : public MCDisassembler {
105 ThumbDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) :
106 MCDisassembler(STI, Ctx) {
109 ~ThumbDisassembler() {}
111 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
112 ArrayRef<uint8_t> Bytes, uint64_t Address,
113 raw_ostream &VStream,
114 raw_ostream &CStream) const override;
117 mutable ITStatus ITBlock;
118 DecodeStatus AddThumbPredicate(MCInst&) const;
119 void UpdateThumbVFPPredicate(MCInst&) const;
123 static bool Check(DecodeStatus &Out, DecodeStatus In) {
125 case MCDisassembler::Success:
126 // Out stays the same.
128 case MCDisassembler::SoftFail:
131 case MCDisassembler::Fail:
135 llvm_unreachable("Invalid DecodeStatus!");
139 // Forward declare these because the autogenerated code will reference them.
140 // Definitions are further down.
141 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo,
142 uint64_t Address, const void *Decoder);
143 static DecodeStatus DecodeGPRnopcRegisterClass(MCInst &Inst,
144 unsigned RegNo, uint64_t Address,
145 const void *Decoder);
146 static DecodeStatus DecodeGPRwithAPSRRegisterClass(MCInst &Inst,
147 unsigned RegNo, uint64_t Address,
148 const void *Decoder);
149 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo,
150 uint64_t Address, const void *Decoder);
151 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo,
152 uint64_t Address, const void *Decoder);
153 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo,
154 uint64_t Address, const void *Decoder);
155 static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo,
156 uint64_t Address, const void *Decoder);
157 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo,
158 uint64_t Address, const void *Decoder);
159 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo,
160 uint64_t Address, const void *Decoder);
161 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo,
162 uint64_t Address, const void *Decoder);
163 static DecodeStatus DecodeDPR_VFP2RegisterClass(MCInst &Inst,
166 const void *Decoder);
167 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo,
168 uint64_t Address, const void *Decoder);
169 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo,
170 uint64_t Address, const void *Decoder);
171 static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst,
172 unsigned RegNo, uint64_t Address,
173 const void *Decoder);
175 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val,
176 uint64_t Address, const void *Decoder);
177 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val,
178 uint64_t Address, const void *Decoder);
179 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val,
180 uint64_t Address, const void *Decoder);
181 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val,
182 uint64_t Address, const void *Decoder);
183 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val,
184 uint64_t Address, const void *Decoder);
186 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Insn,
187 uint64_t Address, const void *Decoder);
188 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn,
189 uint64_t Address, const void *Decoder);
190 static DecodeStatus DecodeAddrMode2IdxInstruction(MCInst &Inst,
193 const void *Decoder);
194 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Insn,
195 uint64_t Address, const void *Decoder);
196 static DecodeStatus DecodeAddrMode3Instruction(MCInst &Inst,unsigned Insn,
197 uint64_t Address, const void *Decoder);
198 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Insn,
199 uint64_t Address, const void *Decoder);
200 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Insn,
201 uint64_t Address, const void *Decoder);
203 static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst & Inst,
206 const void *Decoder);
207 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn,
208 uint64_t Address, const void *Decoder);
209 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn,
210 uint64_t Address, const void *Decoder);
211 static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn,
212 uint64_t Address, const void *Decoder);
213 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn,
214 uint64_t Address, const void *Decoder);
215 static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn,
216 uint64_t Address, const void *Decoder);
217 static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val,
218 uint64_t Address, const void *Decoder);
219 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val,
220 uint64_t Address, const void *Decoder);
221 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val,
222 uint64_t Address, const void *Decoder);
223 static DecodeStatus DecodeT2BInstruction(MCInst &Inst, unsigned Insn,
224 uint64_t Address, const void *Decoder);
225 static DecodeStatus DecodeBranchImmInstruction(MCInst &Inst,unsigned Insn,
226 uint64_t Address, const void *Decoder);
227 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val,
228 uint64_t Address, const void *Decoder);
229 static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Val,
230 uint64_t Address, const void *Decoder);
231 static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Val,
232 uint64_t Address, const void *Decoder);
233 static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Val,
234 uint64_t Address, const void *Decoder);
235 static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Val,
236 uint64_t Address, const void *Decoder);
237 static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Val,
238 uint64_t Address, const void *Decoder);
239 static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Val,
240 uint64_t Address, const void *Decoder);
241 static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Val,
242 uint64_t Address, const void *Decoder);
243 static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Val,
244 uint64_t Address, const void *Decoder);
245 static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Val,
246 uint64_t Address, const void *Decoder);
247 static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Val,
248 uint64_t Address, const void *Decoder);
249 static DecodeStatus DecodeNEONModImmInstruction(MCInst &Inst,unsigned Val,
250 uint64_t Address, const void *Decoder);
251 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Val,
252 uint64_t Address, const void *Decoder);
253 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val,
254 uint64_t Address, const void *Decoder);
255 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val,
256 uint64_t Address, const void *Decoder);
257 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val,
258 uint64_t Address, const void *Decoder);
259 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val,
260 uint64_t Address, const void *Decoder);
261 static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn,
262 uint64_t Address, const void *Decoder);
263 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn,
264 uint64_t Address, const void *Decoder);
265 static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Insn,
266 uint64_t Address, const void *Decoder);
267 static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Insn,
268 uint64_t Address, const void *Decoder);
269 static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Insn,
270 uint64_t Address, const void *Decoder);
271 static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Insn,
272 uint64_t Address, const void *Decoder);
273 static DecodeStatus DecodeBankedReg(MCInst &Inst, unsigned Insn,
274 uint64_t Address, const void *Decoder);
275 static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn,
276 uint64_t Address, const void *Decoder);
277 static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn,
278 uint64_t Address, const void *Decoder);
279 static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn,
280 uint64_t Address, const void *Decoder);
281 static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn,
282 uint64_t Address, const void *Decoder);
283 static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn,
284 uint64_t Address, const void *Decoder);
285 static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn,
286 uint64_t Address, const void *Decoder);
287 static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn,
288 uint64_t Address, const void *Decoder);
289 static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn,
290 uint64_t Address, const void *Decoder);
291 static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn,
292 uint64_t Address, const void *Decoder);
293 static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn,
294 uint64_t Address, const void *Decoder);
295 static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn,
296 uint64_t Address, const void *Decoder);
297 static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn,
298 uint64_t Address, const void *Decoder);
299 static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn,
300 uint64_t Address, const void *Decoder);
301 static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn,
302 uint64_t Address, const void *Decoder);
303 static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn,
304 uint64_t Address, const void *Decoder);
305 static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn,
306 uint64_t Address, const void *Decoder);
307 static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn,
308 uint64_t Address, const void *Decoder);
309 static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn,
310 uint64_t Address, const void *Decoder);
311 static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn,
312 uint64_t Address, const void *Decoder);
315 static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn,
316 uint64_t Address, const void *Decoder);
317 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val,
318 uint64_t Address, const void *Decoder);
319 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val,
320 uint64_t Address, const void *Decoder);
321 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val,
322 uint64_t Address, const void *Decoder);
323 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val,
324 uint64_t Address, const void *Decoder);
325 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val,
326 uint64_t Address, const void *Decoder);
327 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val,
328 uint64_t Address, const void *Decoder);
329 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val,
330 uint64_t Address, const void *Decoder);
331 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val,
332 uint64_t Address, const void *Decoder);
333 static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Val,
334 uint64_t Address, const void *Decoder);
335 static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn,
336 uint64_t Address, const void* Decoder);
337 static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn,
338 uint64_t Address, const void* Decoder);
339 static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn,
340 uint64_t Address, const void* Decoder);
341 static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn,
342 uint64_t Address, const void* Decoder);
343 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val,
344 uint64_t Address, const void *Decoder);
345 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val,
346 uint64_t Address, const void *Decoder);
347 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val,
348 uint64_t Address, const void *Decoder);
349 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val,
350 uint64_t Address, const void *Decoder);
351 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val,
352 uint64_t Address, const void *Decoder);
353 static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Val,
354 uint64_t Address, const void *Decoder);
355 static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn,
356 uint64_t Address, const void *Decoder);
357 static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn,
358 uint64_t Address, const void *Decoder);
359 static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn,
360 uint64_t Address, const void *Decoder);
361 static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Insn,
362 uint64_t Address, const void *Decoder);
363 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val,
364 uint64_t Address, const void *Decoder);
365 static DecodeStatus DecodeThumbTableBranch(MCInst &Inst, unsigned Val,
366 uint64_t Address, const void *Decoder);
367 static DecodeStatus DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Val,
368 uint64_t Address, const void *Decoder);
369 static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val,
370 uint64_t Address, const void *Decoder);
371 static DecodeStatus DecodeThumbBCCTargetOperand(MCInst &Inst,unsigned Val,
372 uint64_t Address, const void *Decoder);
373 static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val,
374 uint64_t Address, const void *Decoder);
375 static DecodeStatus DecodeIT(MCInst &Inst, unsigned Val,
376 uint64_t Address, const void *Decoder);
377 static DecodeStatus DecodeT2LDRDPreInstruction(MCInst &Inst,unsigned Insn,
378 uint64_t Address, const void *Decoder);
379 static DecodeStatus DecodeT2STRDPreInstruction(MCInst &Inst,unsigned Insn,
380 uint64_t Address, const void *Decoder);
381 static DecodeStatus DecodeT2Adr(MCInst &Inst, unsigned Val,
382 uint64_t Address, const void *Decoder);
383 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Val,
384 uint64_t Address, const void *Decoder);
385 static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, unsigned Val,
386 uint64_t Address, const void *Decoder);
388 static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val,
389 uint64_t Address, const void *Decoder);
390 static DecodeStatus DecodeMRRC2(llvm::MCInst &Inst, unsigned Val,
391 uint64_t Address, const void *Decoder);
392 #include "ARMGenDisassemblerTables.inc"
394 static MCDisassembler *createARMDisassembler(const Target &T,
395 const MCSubtargetInfo &STI,
397 return new ARMDisassembler(STI, Ctx);
400 static MCDisassembler *createThumbDisassembler(const Target &T,
401 const MCSubtargetInfo &STI,
403 return new ThumbDisassembler(STI, Ctx);
406 // Post-decoding checks
407 static DecodeStatus checkDecodedInstruction(MCInst &MI, uint64_t &Size,
408 uint64_t Address, raw_ostream &OS,
413 switch (MI.getOpcode()) {
415 // HVC is undefined if condition = 0xf otherwise upredictable
416 // if condition != 0xe
417 uint32_t Cond = (Insn >> 28) & 0xF;
419 return MCDisassembler::Fail;
421 return MCDisassembler::SoftFail;
424 default: return Result;
428 DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
429 ArrayRef<uint8_t> Bytes,
430 uint64_t Address, raw_ostream &OS,
431 raw_ostream &CS) const {
434 assert(!STI.getFeatureBits()[ARM::ModeThumb] &&
435 "Asked to disassemble an ARM instruction but Subtarget is in Thumb "
438 // We want to read exactly 4 bytes of data.
439 if (Bytes.size() < 4) {
441 return MCDisassembler::Fail;
444 // Encoded as a small-endian 32-bit word in the stream.
446 (Bytes[3] << 24) | (Bytes[2] << 16) | (Bytes[1] << 8) | (Bytes[0] << 0);
448 // Calling the auto-generated decoder function.
449 DecodeStatus Result =
450 decodeInstruction(DecoderTableARM32, MI, Insn, Address, this, STI);
451 if (Result != MCDisassembler::Fail) {
453 return checkDecodedInstruction(MI, Size, Address, OS, CS, Insn, Result);
456 // VFP and NEON instructions, similarly, are shared between ARM
459 Result = decodeInstruction(DecoderTableVFP32, MI, Insn, Address, this, STI);
460 if (Result != MCDisassembler::Fail) {
466 Result = decodeInstruction(DecoderTableVFPV832, MI, Insn, Address, this, STI);
467 if (Result != MCDisassembler::Fail) {
474 decodeInstruction(DecoderTableNEONData32, MI, Insn, Address, this, STI);
475 if (Result != MCDisassembler::Fail) {
477 // Add a fake predicate operand, because we share these instruction
478 // definitions with Thumb2 where these instructions are predicable.
479 if (!DecodePredicateOperand(MI, 0xE, Address, this))
480 return MCDisassembler::Fail;
485 Result = decodeInstruction(DecoderTableNEONLoadStore32, MI, Insn, Address,
487 if (Result != MCDisassembler::Fail) {
489 // Add a fake predicate operand, because we share these instruction
490 // definitions with Thumb2 where these instructions are predicable.
491 if (!DecodePredicateOperand(MI, 0xE, Address, this))
492 return MCDisassembler::Fail;
498 decodeInstruction(DecoderTableNEONDup32, MI, Insn, Address, this, STI);
499 if (Result != MCDisassembler::Fail) {
501 // Add a fake predicate operand, because we share these instruction
502 // definitions with Thumb2 where these instructions are predicable.
503 if (!DecodePredicateOperand(MI, 0xE, Address, this))
504 return MCDisassembler::Fail;
510 decodeInstruction(DecoderTablev8NEON32, MI, Insn, Address, this, STI);
511 if (Result != MCDisassembler::Fail) {
518 decodeInstruction(DecoderTablev8Crypto32, MI, Insn, Address, this, STI);
519 if (Result != MCDisassembler::Fail) {
526 return MCDisassembler::Fail;
530 extern const MCInstrDesc ARMInsts[];
533 /// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the
534 /// immediate Value in the MCInst. The immediate Value has had any PC
535 /// adjustment made by the caller. If the instruction is a branch instruction
536 /// then isBranch is true, else false. If the getOpInfo() function was set as
537 /// part of the setupForSymbolicDisassembly() call then that function is called
538 /// to get any symbolic information at the Address for this instruction. If
539 /// that returns non-zero then the symbolic information it returns is used to
540 /// create an MCExpr and that is added as an operand to the MCInst. If
541 /// getOpInfo() returns zero and isBranch is true then a symbol look up for
542 /// Value is done and if a symbol is found an MCExpr is created with that, else
543 /// an MCExpr with Value is created. This function returns true if it adds an
544 /// operand to the MCInst and false otherwise.
545 static bool tryAddingSymbolicOperand(uint64_t Address, int32_t Value,
546 bool isBranch, uint64_t InstSize,
547 MCInst &MI, const void *Decoder) {
548 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
549 // FIXME: Does it make sense for value to be negative?
550 return Dis->tryAddingSymbolicOperand(MI, (uint32_t)Value, Address, isBranch,
551 /* Offset */ 0, InstSize);
554 /// tryAddingPcLoadReferenceComment - trys to add a comment as to what is being
555 /// referenced by a load instruction with the base register that is the Pc.
556 /// These can often be values in a literal pool near the Address of the
557 /// instruction. The Address of the instruction and its immediate Value are
558 /// used as a possible literal pool entry. The SymbolLookUp call back will
559 /// return the name of a symbol referenced by the literal pool's entry if
560 /// the referenced address is that of a symbol. Or it will return a pointer to
561 /// a literal 'C' string if the referenced address of the literal pool's entry
562 /// is an address into a section with 'C' string literals.
563 static void tryAddingPcLoadReferenceComment(uint64_t Address, int Value,
564 const void *Decoder) {
565 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
566 Dis->tryAddingPcLoadReferenceComment(Value, Address);
569 // Thumb1 instructions don't have explicit S bits. Rather, they
570 // implicitly set CPSR. Since it's not represented in the encoding, the
571 // auto-generated decoder won't inject the CPSR operand. We need to fix
572 // that as a post-pass.
573 static void AddThumb1SBit(MCInst &MI, bool InITBlock) {
574 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
575 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
576 MCInst::iterator I = MI.begin();
577 for (unsigned i = 0; i < NumOps; ++i, ++I) {
578 if (I == MI.end()) break;
579 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) {
580 if (i > 0 && OpInfo[i-1].isPredicate()) continue;
581 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR));
586 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR));
589 // Most Thumb instructions don't have explicit predicates in the
590 // encoding, but rather get their predicates from IT context. We need
591 // to fix up the predicate operands using this context information as a
593 MCDisassembler::DecodeStatus
594 ThumbDisassembler::AddThumbPredicate(MCInst &MI) const {
595 MCDisassembler::DecodeStatus S = Success;
597 // A few instructions actually have predicates encoded in them. Don't
598 // try to overwrite it if we're seeing one of those.
599 switch (MI.getOpcode()) {
610 // Some instructions (mostly conditional branches) are not
611 // allowed in IT blocks.
612 if (ITBlock.instrInITBlock())
621 // Some instructions (mostly unconditional branches) can
622 // only appears at the end of, or outside of, an IT.
623 if (ITBlock.instrInITBlock() && !ITBlock.instrLastInITBlock())
630 // If we're in an IT block, base the predicate on that. Otherwise,
631 // assume a predicate of AL.
633 CC = ITBlock.getITCC();
636 if (ITBlock.instrInITBlock())
637 ITBlock.advanceITState();
639 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
640 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
641 MCInst::iterator I = MI.begin();
642 for (unsigned i = 0; i < NumOps; ++i, ++I) {
643 if (I == MI.end()) break;
644 if (OpInfo[i].isPredicate()) {
645 I = MI.insert(I, MCOperand::CreateImm(CC));
648 MI.insert(I, MCOperand::CreateReg(0));
650 MI.insert(I, MCOperand::CreateReg(ARM::CPSR));
655 I = MI.insert(I, MCOperand::CreateImm(CC));
658 MI.insert(I, MCOperand::CreateReg(0));
660 MI.insert(I, MCOperand::CreateReg(ARM::CPSR));
665 // Thumb VFP instructions are a special case. Because we share their
666 // encodings between ARM and Thumb modes, and they are predicable in ARM
667 // mode, the auto-generated decoder will give them an (incorrect)
668 // predicate operand. We need to rewrite these operands based on the IT
669 // context as a post-pass.
670 void ThumbDisassembler::UpdateThumbVFPPredicate(MCInst &MI) const {
672 CC = ITBlock.getITCC();
673 if (ITBlock.instrInITBlock())
674 ITBlock.advanceITState();
676 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
677 MCInst::iterator I = MI.begin();
678 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
679 for (unsigned i = 0; i < NumOps; ++i, ++I) {
680 if (OpInfo[i].isPredicate() ) {
686 I->setReg(ARM::CPSR);
692 DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
693 ArrayRef<uint8_t> Bytes,
696 raw_ostream &CS) const {
699 assert(STI.getFeatureBits()[ARM::ModeThumb] &&
700 "Asked to disassemble in Thumb mode but Subtarget is in ARM mode!");
702 // We want to read exactly 2 bytes of data.
703 if (Bytes.size() < 2) {
705 return MCDisassembler::Fail;
708 uint16_t Insn16 = (Bytes[1] << 8) | Bytes[0];
709 DecodeStatus Result =
710 decodeInstruction(DecoderTableThumb16, MI, Insn16, Address, this, STI);
711 if (Result != MCDisassembler::Fail) {
713 Check(Result, AddThumbPredicate(MI));
718 Result = decodeInstruction(DecoderTableThumbSBit16, MI, Insn16, Address, this,
722 bool InITBlock = ITBlock.instrInITBlock();
723 Check(Result, AddThumbPredicate(MI));
724 AddThumb1SBit(MI, InITBlock);
730 decodeInstruction(DecoderTableThumb216, MI, Insn16, Address, this, STI);
731 if (Result != MCDisassembler::Fail) {
734 // Nested IT blocks are UNPREDICTABLE. Must be checked before we add
735 // the Thumb predicate.
736 if (MI.getOpcode() == ARM::t2IT && ITBlock.instrInITBlock())
737 Result = MCDisassembler::SoftFail;
739 Check(Result, AddThumbPredicate(MI));
741 // If we find an IT instruction, we need to parse its condition
742 // code and mask operands so that we can apply them correctly
743 // to the subsequent instructions.
744 if (MI.getOpcode() == ARM::t2IT) {
746 unsigned Firstcond = MI.getOperand(0).getImm();
747 unsigned Mask = MI.getOperand(1).getImm();
748 ITBlock.setITState(Firstcond, Mask);
754 // We want to read exactly 4 bytes of data.
755 if (Bytes.size() < 4) {
757 return MCDisassembler::Fail;
761 (Bytes[3] << 8) | (Bytes[2] << 0) | (Bytes[1] << 24) | (Bytes[0] << 16);
764 decodeInstruction(DecoderTableThumb32, MI, Insn32, Address, this, STI);
765 if (Result != MCDisassembler::Fail) {
767 bool InITBlock = ITBlock.instrInITBlock();
768 Check(Result, AddThumbPredicate(MI));
769 AddThumb1SBit(MI, InITBlock);
775 decodeInstruction(DecoderTableThumb232, MI, Insn32, Address, this, STI);
776 if (Result != MCDisassembler::Fail) {
778 Check(Result, AddThumbPredicate(MI));
782 if (fieldFromInstruction(Insn32, 28, 4) == 0xE) {
785 decodeInstruction(DecoderTableVFP32, MI, Insn32, Address, this, STI);
786 if (Result != MCDisassembler::Fail) {
788 UpdateThumbVFPPredicate(MI);
795 decodeInstruction(DecoderTableVFPV832, MI, Insn32, Address, this, STI);
796 if (Result != MCDisassembler::Fail) {
801 if (fieldFromInstruction(Insn32, 28, 4) == 0xE) {
803 Result = decodeInstruction(DecoderTableNEONDup32, MI, Insn32, Address, this,
805 if (Result != MCDisassembler::Fail) {
807 Check(Result, AddThumbPredicate(MI));
812 if (fieldFromInstruction(Insn32, 24, 8) == 0xF9) {
814 uint32_t NEONLdStInsn = Insn32;
815 NEONLdStInsn &= 0xF0FFFFFF;
816 NEONLdStInsn |= 0x04000000;
817 Result = decodeInstruction(DecoderTableNEONLoadStore32, MI, NEONLdStInsn,
819 if (Result != MCDisassembler::Fail) {
821 Check(Result, AddThumbPredicate(MI));
826 if (fieldFromInstruction(Insn32, 24, 4) == 0xF) {
828 uint32_t NEONDataInsn = Insn32;
829 NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24
830 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24
831 NEONDataInsn |= 0x12000000; // Set bits 28 and 25
832 Result = decodeInstruction(DecoderTableNEONData32, MI, NEONDataInsn,
834 if (Result != MCDisassembler::Fail) {
836 Check(Result, AddThumbPredicate(MI));
841 uint32_t NEONCryptoInsn = Insn32;
842 NEONCryptoInsn &= 0xF0FFFFFF; // Clear bits 27-24
843 NEONCryptoInsn |= (NEONCryptoInsn & 0x10000000) >> 4; // Move bit 28 to bit 24
844 NEONCryptoInsn |= 0x12000000; // Set bits 28 and 25
845 Result = decodeInstruction(DecoderTablev8Crypto32, MI, NEONCryptoInsn,
847 if (Result != MCDisassembler::Fail) {
853 uint32_t NEONv8Insn = Insn32;
854 NEONv8Insn &= 0xF3FFFFFF; // Clear bits 27-26
855 Result = decodeInstruction(DecoderTablev8NEON32, MI, NEONv8Insn, Address,
857 if (Result != MCDisassembler::Fail) {
865 return MCDisassembler::Fail;
869 extern "C" void LLVMInitializeARMDisassembler() {
870 TargetRegistry::RegisterMCDisassembler(TheARMLETarget,
871 createARMDisassembler);
872 TargetRegistry::RegisterMCDisassembler(TheARMBETarget,
873 createARMDisassembler);
874 TargetRegistry::RegisterMCDisassembler(TheThumbLETarget,
875 createThumbDisassembler);
876 TargetRegistry::RegisterMCDisassembler(TheThumbBETarget,
877 createThumbDisassembler);
880 static const uint16_t GPRDecoderTable[] = {
881 ARM::R0, ARM::R1, ARM::R2, ARM::R3,
882 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
883 ARM::R8, ARM::R9, ARM::R10, ARM::R11,
884 ARM::R12, ARM::SP, ARM::LR, ARM::PC
887 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo,
888 uint64_t Address, const void *Decoder) {
890 return MCDisassembler::Fail;
892 unsigned Register = GPRDecoderTable[RegNo];
893 Inst.addOperand(MCOperand::CreateReg(Register));
894 return MCDisassembler::Success;
898 DecodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo,
899 uint64_t Address, const void *Decoder) {
900 DecodeStatus S = MCDisassembler::Success;
903 S = MCDisassembler::SoftFail;
905 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
911 DecodeGPRwithAPSRRegisterClass(MCInst &Inst, unsigned RegNo,
912 uint64_t Address, const void *Decoder) {
913 DecodeStatus S = MCDisassembler::Success;
917 Inst.addOperand(MCOperand::CreateReg(ARM::APSR_NZCV));
918 return MCDisassembler::Success;
921 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
925 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo,
926 uint64_t Address, const void *Decoder) {
928 return MCDisassembler::Fail;
929 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
932 static const uint16_t GPRPairDecoderTable[] = {
933 ARM::R0_R1, ARM::R2_R3, ARM::R4_R5, ARM::R6_R7,
934 ARM::R8_R9, ARM::R10_R11, ARM::R12_SP
937 static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo,
938 uint64_t Address, const void *Decoder) {
939 DecodeStatus S = MCDisassembler::Success;
942 return MCDisassembler::Fail;
944 if ((RegNo & 1) || RegNo == 0xe)
945 S = MCDisassembler::SoftFail;
947 unsigned RegisterPair = GPRPairDecoderTable[RegNo/2];
948 Inst.addOperand(MCOperand::CreateReg(RegisterPair));
952 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo,
953 uint64_t Address, const void *Decoder) {
954 unsigned Register = 0;
975 return MCDisassembler::Fail;
978 Inst.addOperand(MCOperand::CreateReg(Register));
979 return MCDisassembler::Success;
982 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo,
983 uint64_t Address, const void *Decoder) {
984 DecodeStatus S = MCDisassembler::Success;
985 if (RegNo == 13 || RegNo == 15)
986 S = MCDisassembler::SoftFail;
987 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
991 static const uint16_t SPRDecoderTable[] = {
992 ARM::S0, ARM::S1, ARM::S2, ARM::S3,
993 ARM::S4, ARM::S5, ARM::S6, ARM::S7,
994 ARM::S8, ARM::S9, ARM::S10, ARM::S11,
995 ARM::S12, ARM::S13, ARM::S14, ARM::S15,
996 ARM::S16, ARM::S17, ARM::S18, ARM::S19,
997 ARM::S20, ARM::S21, ARM::S22, ARM::S23,
998 ARM::S24, ARM::S25, ARM::S26, ARM::S27,
999 ARM::S28, ARM::S29, ARM::S30, ARM::S31
1002 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo,
1003 uint64_t Address, const void *Decoder) {
1005 return MCDisassembler::Fail;
1007 unsigned Register = SPRDecoderTable[RegNo];
1008 Inst.addOperand(MCOperand::CreateReg(Register));
1009 return MCDisassembler::Success;
1012 static const uint16_t DPRDecoderTable[] = {
1013 ARM::D0, ARM::D1, ARM::D2, ARM::D3,
1014 ARM::D4, ARM::D5, ARM::D6, ARM::D7,
1015 ARM::D8, ARM::D9, ARM::D10, ARM::D11,
1016 ARM::D12, ARM::D13, ARM::D14, ARM::D15,
1017 ARM::D16, ARM::D17, ARM::D18, ARM::D19,
1018 ARM::D20, ARM::D21, ARM::D22, ARM::D23,
1019 ARM::D24, ARM::D25, ARM::D26, ARM::D27,
1020 ARM::D28, ARM::D29, ARM::D30, ARM::D31
1023 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo,
1024 uint64_t Address, const void *Decoder) {
1025 const FeatureBitset &featureBits =
1026 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
1028 bool hasD16 = featureBits[ARM::FeatureD16];
1030 if (RegNo > 31 || (hasD16 && RegNo > 15))
1031 return MCDisassembler::Fail;
1033 unsigned Register = DPRDecoderTable[RegNo];
1034 Inst.addOperand(MCOperand::CreateReg(Register));
1035 return MCDisassembler::Success;
1038 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo,
1039 uint64_t Address, const void *Decoder) {
1041 return MCDisassembler::Fail;
1042 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
1046 DecodeDPR_VFP2RegisterClass(MCInst &Inst, unsigned RegNo,
1047 uint64_t Address, const void *Decoder) {
1049 return MCDisassembler::Fail;
1050 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
1053 static const uint16_t QPRDecoderTable[] = {
1054 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3,
1055 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7,
1056 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11,
1057 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15
1061 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo,
1062 uint64_t Address, const void *Decoder) {
1063 if (RegNo > 31 || (RegNo & 1) != 0)
1064 return MCDisassembler::Fail;
1067 unsigned Register = QPRDecoderTable[RegNo];
1068 Inst.addOperand(MCOperand::CreateReg(Register));
1069 return MCDisassembler::Success;
1072 static const uint16_t DPairDecoderTable[] = {
1073 ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6,
1074 ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12,
1075 ARM::Q6, ARM::D13_D14, ARM::Q7, ARM::D15_D16, ARM::Q8, ARM::D17_D18,
1076 ARM::Q9, ARM::D19_D20, ARM::Q10, ARM::D21_D22, ARM::Q11, ARM::D23_D24,
1077 ARM::Q12, ARM::D25_D26, ARM::Q13, ARM::D27_D28, ARM::Q14, ARM::D29_D30,
1081 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo,
1082 uint64_t Address, const void *Decoder) {
1084 return MCDisassembler::Fail;
1086 unsigned Register = DPairDecoderTable[RegNo];
1087 Inst.addOperand(MCOperand::CreateReg(Register));
1088 return MCDisassembler::Success;
1091 static const uint16_t DPairSpacedDecoderTable[] = {
1092 ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5,
1093 ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9,
1094 ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13,
1095 ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17,
1096 ARM::D16_D18, ARM::D17_D19, ARM::D18_D20, ARM::D19_D21,
1097 ARM::D20_D22, ARM::D21_D23, ARM::D22_D24, ARM::D23_D25,
1098 ARM::D24_D26, ARM::D25_D27, ARM::D26_D28, ARM::D27_D29,
1099 ARM::D28_D30, ARM::D29_D31
1102 static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst,
1105 const void *Decoder) {
1107 return MCDisassembler::Fail;
1109 unsigned Register = DPairSpacedDecoderTable[RegNo];
1110 Inst.addOperand(MCOperand::CreateReg(Register));
1111 return MCDisassembler::Success;
1114 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val,
1115 uint64_t Address, const void *Decoder) {
1116 if (Val == 0xF) return MCDisassembler::Fail;
1117 // AL predicate is not allowed on Thumb1 branches.
1118 if (Inst.getOpcode() == ARM::tBcc && Val == 0xE)
1119 return MCDisassembler::Fail;
1120 Inst.addOperand(MCOperand::CreateImm(Val));
1121 if (Val == ARMCC::AL) {
1122 Inst.addOperand(MCOperand::CreateReg(0));
1124 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1125 return MCDisassembler::Success;
1128 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val,
1129 uint64_t Address, const void *Decoder) {
1131 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1133 Inst.addOperand(MCOperand::CreateReg(0));
1134 return MCDisassembler::Success;
1137 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Val,
1138 uint64_t Address, const void *Decoder) {
1139 DecodeStatus S = MCDisassembler::Success;
1141 unsigned Rm = fieldFromInstruction(Val, 0, 4);
1142 unsigned type = fieldFromInstruction(Val, 5, 2);
1143 unsigned imm = fieldFromInstruction(Val, 7, 5);
1145 // Register-immediate
1146 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1147 return MCDisassembler::Fail;
1149 ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
1152 Shift = ARM_AM::lsl;
1155 Shift = ARM_AM::lsr;
1158 Shift = ARM_AM::asr;
1161 Shift = ARM_AM::ror;
1165 if (Shift == ARM_AM::ror && imm == 0)
1166 Shift = ARM_AM::rrx;
1168 unsigned Op = Shift | (imm << 3);
1169 Inst.addOperand(MCOperand::CreateImm(Op));
1174 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Val,
1175 uint64_t Address, const void *Decoder) {
1176 DecodeStatus S = MCDisassembler::Success;
1178 unsigned Rm = fieldFromInstruction(Val, 0, 4);
1179 unsigned type = fieldFromInstruction(Val, 5, 2);
1180 unsigned Rs = fieldFromInstruction(Val, 8, 4);
1182 // Register-register
1183 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1184 return MCDisassembler::Fail;
1185 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder)))
1186 return MCDisassembler::Fail;
1188 ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
1191 Shift = ARM_AM::lsl;
1194 Shift = ARM_AM::lsr;
1197 Shift = ARM_AM::asr;
1200 Shift = ARM_AM::ror;
1204 Inst.addOperand(MCOperand::CreateImm(Shift));
1209 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val,
1210 uint64_t Address, const void *Decoder) {
1211 DecodeStatus S = MCDisassembler::Success;
1213 bool NeedDisjointWriteback = false;
1214 unsigned WritebackReg = 0;
1215 switch (Inst.getOpcode()) {
1218 case ARM::LDMIA_UPD:
1219 case ARM::LDMDB_UPD:
1220 case ARM::LDMIB_UPD:
1221 case ARM::LDMDA_UPD:
1222 case ARM::t2LDMIA_UPD:
1223 case ARM::t2LDMDB_UPD:
1224 case ARM::t2STMIA_UPD:
1225 case ARM::t2STMDB_UPD:
1226 NeedDisjointWriteback = true;
1227 WritebackReg = Inst.getOperand(0).getReg();
1231 // Empty register lists are not allowed.
1232 if (Val == 0) return MCDisassembler::Fail;
1233 for (unsigned i = 0; i < 16; ++i) {
1234 if (Val & (1 << i)) {
1235 if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder)))
1236 return MCDisassembler::Fail;
1237 // Writeback not allowed if Rn is in the target list.
1238 if (NeedDisjointWriteback && WritebackReg == Inst.end()[-1].getReg())
1239 Check(S, MCDisassembler::SoftFail);
1246 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val,
1247 uint64_t Address, const void *Decoder) {
1248 DecodeStatus S = MCDisassembler::Success;
1250 unsigned Vd = fieldFromInstruction(Val, 8, 5);
1251 unsigned regs = fieldFromInstruction(Val, 0, 8);
1253 // In case of unpredictable encoding, tweak the operands.
1254 if (regs == 0 || (Vd + regs) > 32) {
1255 regs = Vd + regs > 32 ? 32 - Vd : regs;
1256 regs = std::max( 1u, regs);
1257 S = MCDisassembler::SoftFail;
1260 if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder)))
1261 return MCDisassembler::Fail;
1262 for (unsigned i = 0; i < (regs - 1); ++i) {
1263 if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder)))
1264 return MCDisassembler::Fail;
1270 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val,
1271 uint64_t Address, const void *Decoder) {
1272 DecodeStatus S = MCDisassembler::Success;
1274 unsigned Vd = fieldFromInstruction(Val, 8, 5);
1275 unsigned regs = fieldFromInstruction(Val, 1, 7);
1277 // In case of unpredictable encoding, tweak the operands.
1278 if (regs == 0 || regs > 16 || (Vd + regs) > 32) {
1279 regs = Vd + regs > 32 ? 32 - Vd : regs;
1280 regs = std::max( 1u, regs);
1281 regs = std::min(16u, regs);
1282 S = MCDisassembler::SoftFail;
1285 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
1286 return MCDisassembler::Fail;
1287 for (unsigned i = 0; i < (regs - 1); ++i) {
1288 if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder)))
1289 return MCDisassembler::Fail;
1295 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Val,
1296 uint64_t Address, const void *Decoder) {
1297 // This operand encodes a mask of contiguous zeros between a specified MSB
1298 // and LSB. To decode it, we create the mask of all bits MSB-and-lower,
1299 // the mask of all bits LSB-and-lower, and then xor them to create
1300 // the mask of that's all ones on [msb, lsb]. Finally we not it to
1301 // create the final mask.
1302 unsigned msb = fieldFromInstruction(Val, 5, 5);
1303 unsigned lsb = fieldFromInstruction(Val, 0, 5);
1305 DecodeStatus S = MCDisassembler::Success;
1307 Check(S, MCDisassembler::SoftFail);
1308 // The check above will cause the warning for the "potentially undefined
1309 // instruction encoding" but we can't build a bad MCOperand value here
1310 // with a lsb > msb or else printing the MCInst will cause a crash.
1314 uint32_t msb_mask = 0xFFFFFFFF;
1315 if (msb != 31) msb_mask = (1U << (msb+1)) - 1;
1316 uint32_t lsb_mask = (1U << lsb) - 1;
1318 Inst.addOperand(MCOperand::CreateImm(~(msb_mask ^ lsb_mask)));
1322 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn,
1323 uint64_t Address, const void *Decoder) {
1324 DecodeStatus S = MCDisassembler::Success;
1326 unsigned pred = fieldFromInstruction(Insn, 28, 4);
1327 unsigned CRd = fieldFromInstruction(Insn, 12, 4);
1328 unsigned coproc = fieldFromInstruction(Insn, 8, 4);
1329 unsigned imm = fieldFromInstruction(Insn, 0, 8);
1330 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1331 unsigned U = fieldFromInstruction(Insn, 23, 1);
1333 switch (Inst.getOpcode()) {
1334 case ARM::LDC_OFFSET:
1337 case ARM::LDC_OPTION:
1338 case ARM::LDCL_OFFSET:
1340 case ARM::LDCL_POST:
1341 case ARM::LDCL_OPTION:
1342 case ARM::STC_OFFSET:
1345 case ARM::STC_OPTION:
1346 case ARM::STCL_OFFSET:
1348 case ARM::STCL_POST:
1349 case ARM::STCL_OPTION:
1350 case ARM::t2LDC_OFFSET:
1351 case ARM::t2LDC_PRE:
1352 case ARM::t2LDC_POST:
1353 case ARM::t2LDC_OPTION:
1354 case ARM::t2LDCL_OFFSET:
1355 case ARM::t2LDCL_PRE:
1356 case ARM::t2LDCL_POST:
1357 case ARM::t2LDCL_OPTION:
1358 case ARM::t2STC_OFFSET:
1359 case ARM::t2STC_PRE:
1360 case ARM::t2STC_POST:
1361 case ARM::t2STC_OPTION:
1362 case ARM::t2STCL_OFFSET:
1363 case ARM::t2STCL_PRE:
1364 case ARM::t2STCL_POST:
1365 case ARM::t2STCL_OPTION:
1366 if (coproc == 0xA || coproc == 0xB)
1367 return MCDisassembler::Fail;
1373 const FeatureBitset &featureBits =
1374 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
1375 if (featureBits[ARM::HasV8Ops] && (coproc != 14))
1376 return MCDisassembler::Fail;
1378 Inst.addOperand(MCOperand::CreateImm(coproc));
1379 Inst.addOperand(MCOperand::CreateImm(CRd));
1380 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1381 return MCDisassembler::Fail;
1383 switch (Inst.getOpcode()) {
1384 case ARM::t2LDC2_OFFSET:
1385 case ARM::t2LDC2L_OFFSET:
1386 case ARM::t2LDC2_PRE:
1387 case ARM::t2LDC2L_PRE:
1388 case ARM::t2STC2_OFFSET:
1389 case ARM::t2STC2L_OFFSET:
1390 case ARM::t2STC2_PRE:
1391 case ARM::t2STC2L_PRE:
1392 case ARM::LDC2_OFFSET:
1393 case ARM::LDC2L_OFFSET:
1395 case ARM::LDC2L_PRE:
1396 case ARM::STC2_OFFSET:
1397 case ARM::STC2L_OFFSET:
1399 case ARM::STC2L_PRE:
1400 case ARM::t2LDC_OFFSET:
1401 case ARM::t2LDCL_OFFSET:
1402 case ARM::t2LDC_PRE:
1403 case ARM::t2LDCL_PRE:
1404 case ARM::t2STC_OFFSET:
1405 case ARM::t2STCL_OFFSET:
1406 case ARM::t2STC_PRE:
1407 case ARM::t2STCL_PRE:
1408 case ARM::LDC_OFFSET:
1409 case ARM::LDCL_OFFSET:
1412 case ARM::STC_OFFSET:
1413 case ARM::STCL_OFFSET:
1416 imm = ARM_AM::getAM5Opc(U ? ARM_AM::add : ARM_AM::sub, imm);
1417 Inst.addOperand(MCOperand::CreateImm(imm));
1419 case ARM::t2LDC2_POST:
1420 case ARM::t2LDC2L_POST:
1421 case ARM::t2STC2_POST:
1422 case ARM::t2STC2L_POST:
1423 case ARM::LDC2_POST:
1424 case ARM::LDC2L_POST:
1425 case ARM::STC2_POST:
1426 case ARM::STC2L_POST:
1427 case ARM::t2LDC_POST:
1428 case ARM::t2LDCL_POST:
1429 case ARM::t2STC_POST:
1430 case ARM::t2STCL_POST:
1432 case ARM::LDCL_POST:
1434 case ARM::STCL_POST:
1438 // The 'option' variant doesn't encode 'U' in the immediate since
1439 // the immediate is unsigned [0,255].
1440 Inst.addOperand(MCOperand::CreateImm(imm));
1444 switch (Inst.getOpcode()) {
1445 case ARM::LDC_OFFSET:
1448 case ARM::LDC_OPTION:
1449 case ARM::LDCL_OFFSET:
1451 case ARM::LDCL_POST:
1452 case ARM::LDCL_OPTION:
1453 case ARM::STC_OFFSET:
1456 case ARM::STC_OPTION:
1457 case ARM::STCL_OFFSET:
1459 case ARM::STCL_POST:
1460 case ARM::STCL_OPTION:
1461 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1462 return MCDisassembler::Fail;
1472 DecodeAddrMode2IdxInstruction(MCInst &Inst, unsigned Insn,
1473 uint64_t Address, const void *Decoder) {
1474 DecodeStatus S = MCDisassembler::Success;
1476 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1477 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
1478 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
1479 unsigned imm = fieldFromInstruction(Insn, 0, 12);
1480 unsigned pred = fieldFromInstruction(Insn, 28, 4);
1481 unsigned reg = fieldFromInstruction(Insn, 25, 1);
1482 unsigned P = fieldFromInstruction(Insn, 24, 1);
1483 unsigned W = fieldFromInstruction(Insn, 21, 1);
1485 // On stores, the writeback operand precedes Rt.
1486 switch (Inst.getOpcode()) {
1487 case ARM::STR_POST_IMM:
1488 case ARM::STR_POST_REG:
1489 case ARM::STRB_POST_IMM:
1490 case ARM::STRB_POST_REG:
1491 case ARM::STRT_POST_REG:
1492 case ARM::STRT_POST_IMM:
1493 case ARM::STRBT_POST_REG:
1494 case ARM::STRBT_POST_IMM:
1495 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1496 return MCDisassembler::Fail;
1502 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
1503 return MCDisassembler::Fail;
1505 // On loads, the writeback operand comes after Rt.
1506 switch (Inst.getOpcode()) {
1507 case ARM::LDR_POST_IMM:
1508 case ARM::LDR_POST_REG:
1509 case ARM::LDRB_POST_IMM:
1510 case ARM::LDRB_POST_REG:
1511 case ARM::LDRBT_POST_REG:
1512 case ARM::LDRBT_POST_IMM:
1513 case ARM::LDRT_POST_REG:
1514 case ARM::LDRT_POST_IMM:
1515 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1516 return MCDisassembler::Fail;
1522 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1523 return MCDisassembler::Fail;
1525 ARM_AM::AddrOpc Op = ARM_AM::add;
1526 if (!fieldFromInstruction(Insn, 23, 1))
1529 bool writeback = (P == 0) || (W == 1);
1530 unsigned idx_mode = 0;
1532 idx_mode = ARMII::IndexModePre;
1533 else if (!P && writeback)
1534 idx_mode = ARMII::IndexModePost;
1536 if (writeback && (Rn == 15 || Rn == Rt))
1537 S = MCDisassembler::SoftFail; // UNPREDICTABLE
1540 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1541 return MCDisassembler::Fail;
1542 ARM_AM::ShiftOpc Opc = ARM_AM::lsl;
1543 switch( fieldFromInstruction(Insn, 5, 2)) {
1557 return MCDisassembler::Fail;
1559 unsigned amt = fieldFromInstruction(Insn, 7, 5);
1560 if (Opc == ARM_AM::ror && amt == 0)
1562 unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode);
1564 Inst.addOperand(MCOperand::CreateImm(imm));
1566 Inst.addOperand(MCOperand::CreateReg(0));
1567 unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode);
1568 Inst.addOperand(MCOperand::CreateImm(tmp));
1571 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1572 return MCDisassembler::Fail;
1577 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Val,
1578 uint64_t Address, const void *Decoder) {
1579 DecodeStatus S = MCDisassembler::Success;
1581 unsigned Rn = fieldFromInstruction(Val, 13, 4);
1582 unsigned Rm = fieldFromInstruction(Val, 0, 4);
1583 unsigned type = fieldFromInstruction(Val, 5, 2);
1584 unsigned imm = fieldFromInstruction(Val, 7, 5);
1585 unsigned U = fieldFromInstruction(Val, 12, 1);
1587 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl;
1603 if (ShOp == ARM_AM::ror && imm == 0)
1606 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1607 return MCDisassembler::Fail;
1608 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1609 return MCDisassembler::Fail;
1612 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp);
1614 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp);
1615 Inst.addOperand(MCOperand::CreateImm(shift));
1621 DecodeAddrMode3Instruction(MCInst &Inst, unsigned Insn,
1622 uint64_t Address, const void *Decoder) {
1623 DecodeStatus S = MCDisassembler::Success;
1625 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
1626 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1627 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
1628 unsigned type = fieldFromInstruction(Insn, 22, 1);
1629 unsigned imm = fieldFromInstruction(Insn, 8, 4);
1630 unsigned U = ((~fieldFromInstruction(Insn, 23, 1)) & 1) << 8;
1631 unsigned pred = fieldFromInstruction(Insn, 28, 4);
1632 unsigned W = fieldFromInstruction(Insn, 21, 1);
1633 unsigned P = fieldFromInstruction(Insn, 24, 1);
1634 unsigned Rt2 = Rt + 1;
1636 bool writeback = (W == 1) | (P == 0);
1638 // For {LD,ST}RD, Rt must be even, else undefined.
1639 switch (Inst.getOpcode()) {
1642 case ARM::STRD_POST:
1645 case ARM::LDRD_POST:
1646 if (Rt & 0x1) S = MCDisassembler::SoftFail;
1651 switch (Inst.getOpcode()) {
1654 case ARM::STRD_POST:
1655 if (P == 0 && W == 1)
1656 S = MCDisassembler::SoftFail;
1658 if (writeback && (Rn == 15 || Rn == Rt || Rn == Rt2))
1659 S = MCDisassembler::SoftFail;
1660 if (type && Rm == 15)
1661 S = MCDisassembler::SoftFail;
1663 S = MCDisassembler::SoftFail;
1664 if (!type && fieldFromInstruction(Insn, 8, 4))
1665 S = MCDisassembler::SoftFail;
1669 case ARM::STRH_POST:
1671 S = MCDisassembler::SoftFail;
1672 if (writeback && (Rn == 15 || Rn == Rt))
1673 S = MCDisassembler::SoftFail;
1674 if (!type && Rm == 15)
1675 S = MCDisassembler::SoftFail;
1679 case ARM::LDRD_POST:
1680 if (type && Rn == 15){
1682 S = MCDisassembler::SoftFail;
1685 if (P == 0 && W == 1)
1686 S = MCDisassembler::SoftFail;
1687 if (!type && (Rt2 == 15 || Rm == 15 || Rm == Rt || Rm == Rt2))
1688 S = MCDisassembler::SoftFail;
1689 if (!type && writeback && Rn == 15)
1690 S = MCDisassembler::SoftFail;
1691 if (writeback && (Rn == Rt || Rn == Rt2))
1692 S = MCDisassembler::SoftFail;
1696 case ARM::LDRH_POST:
1697 if (type && Rn == 15){
1699 S = MCDisassembler::SoftFail;
1703 S = MCDisassembler::SoftFail;
1704 if (!type && Rm == 15)
1705 S = MCDisassembler::SoftFail;
1706 if (!type && writeback && (Rn == 15 || Rn == Rt))
1707 S = MCDisassembler::SoftFail;
1710 case ARM::LDRSH_PRE:
1711 case ARM::LDRSH_POST:
1713 case ARM::LDRSB_PRE:
1714 case ARM::LDRSB_POST:
1715 if (type && Rn == 15){
1717 S = MCDisassembler::SoftFail;
1720 if (type && (Rt == 15 || (writeback && Rn == Rt)))
1721 S = MCDisassembler::SoftFail;
1722 if (!type && (Rt == 15 || Rm == 15))
1723 S = MCDisassembler::SoftFail;
1724 if (!type && writeback && (Rn == 15 || Rn == Rt))
1725 S = MCDisassembler::SoftFail;
1731 if (writeback) { // Writeback
1733 U |= ARMII::IndexModePre << 9;
1735 U |= ARMII::IndexModePost << 9;
1737 // On stores, the writeback operand precedes Rt.
1738 switch (Inst.getOpcode()) {
1741 case ARM::STRD_POST:
1744 case ARM::STRH_POST:
1745 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1746 return MCDisassembler::Fail;
1753 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
1754 return MCDisassembler::Fail;
1755 switch (Inst.getOpcode()) {
1758 case ARM::STRD_POST:
1761 case ARM::LDRD_POST:
1762 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
1763 return MCDisassembler::Fail;
1770 // On loads, the writeback operand comes after Rt.
1771 switch (Inst.getOpcode()) {
1774 case ARM::LDRD_POST:
1777 case ARM::LDRH_POST:
1779 case ARM::LDRSH_PRE:
1780 case ARM::LDRSH_POST:
1782 case ARM::LDRSB_PRE:
1783 case ARM::LDRSB_POST:
1786 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1787 return MCDisassembler::Fail;
1794 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1795 return MCDisassembler::Fail;
1798 Inst.addOperand(MCOperand::CreateReg(0));
1799 Inst.addOperand(MCOperand::CreateImm(U | (imm << 4) | Rm));
1801 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1802 return MCDisassembler::Fail;
1803 Inst.addOperand(MCOperand::CreateImm(U));
1806 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1807 return MCDisassembler::Fail;
1812 static DecodeStatus DecodeRFEInstruction(MCInst &Inst, unsigned Insn,
1813 uint64_t Address, const void *Decoder) {
1814 DecodeStatus S = MCDisassembler::Success;
1816 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1817 unsigned mode = fieldFromInstruction(Insn, 23, 2);
1834 Inst.addOperand(MCOperand::CreateImm(mode));
1835 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1836 return MCDisassembler::Fail;
1841 static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn,
1842 uint64_t Address, const void *Decoder) {
1843 DecodeStatus S = MCDisassembler::Success;
1845 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
1846 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
1847 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1848 unsigned pred = fieldFromInstruction(Insn, 28, 4);
1851 return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
1853 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
1854 return MCDisassembler::Fail;
1855 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1856 return MCDisassembler::Fail;
1857 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
1858 return MCDisassembler::Fail;
1859 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1860 return MCDisassembler::Fail;
1864 static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst &Inst,
1866 uint64_t Address, const void *Decoder) {
1867 DecodeStatus S = MCDisassembler::Success;
1869 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1870 unsigned pred = fieldFromInstruction(Insn, 28, 4);
1871 unsigned reglist = fieldFromInstruction(Insn, 0, 16);
1874 // Ambiguous with RFE and SRS
1875 switch (Inst.getOpcode()) {
1877 Inst.setOpcode(ARM::RFEDA);
1879 case ARM::LDMDA_UPD:
1880 Inst.setOpcode(ARM::RFEDA_UPD);
1883 Inst.setOpcode(ARM::RFEDB);
1885 case ARM::LDMDB_UPD:
1886 Inst.setOpcode(ARM::RFEDB_UPD);
1889 Inst.setOpcode(ARM::RFEIA);
1891 case ARM::LDMIA_UPD:
1892 Inst.setOpcode(ARM::RFEIA_UPD);
1895 Inst.setOpcode(ARM::RFEIB);
1897 case ARM::LDMIB_UPD:
1898 Inst.setOpcode(ARM::RFEIB_UPD);
1901 Inst.setOpcode(ARM::SRSDA);
1903 case ARM::STMDA_UPD:
1904 Inst.setOpcode(ARM::SRSDA_UPD);
1907 Inst.setOpcode(ARM::SRSDB);
1909 case ARM::STMDB_UPD:
1910 Inst.setOpcode(ARM::SRSDB_UPD);
1913 Inst.setOpcode(ARM::SRSIA);
1915 case ARM::STMIA_UPD:
1916 Inst.setOpcode(ARM::SRSIA_UPD);
1919 Inst.setOpcode(ARM::SRSIB);
1921 case ARM::STMIB_UPD:
1922 Inst.setOpcode(ARM::SRSIB_UPD);
1925 return MCDisassembler::Fail;
1928 // For stores (which become SRS's, the only operand is the mode.
1929 if (fieldFromInstruction(Insn, 20, 1) == 0) {
1930 // Check SRS encoding constraints
1931 if (!(fieldFromInstruction(Insn, 22, 1) == 1 &&
1932 fieldFromInstruction(Insn, 20, 1) == 0))
1933 return MCDisassembler::Fail;
1936 MCOperand::CreateImm(fieldFromInstruction(Insn, 0, 4)));
1940 return DecodeRFEInstruction(Inst, Insn, Address, Decoder);
1943 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1944 return MCDisassembler::Fail;
1945 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1946 return MCDisassembler::Fail; // Tied
1947 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1948 return MCDisassembler::Fail;
1949 if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder)))
1950 return MCDisassembler::Fail;
1955 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn,
1956 uint64_t Address, const void *Decoder) {
1957 unsigned imod = fieldFromInstruction(Insn, 18, 2);
1958 unsigned M = fieldFromInstruction(Insn, 17, 1);
1959 unsigned iflags = fieldFromInstruction(Insn, 6, 3);
1960 unsigned mode = fieldFromInstruction(Insn, 0, 5);
1962 DecodeStatus S = MCDisassembler::Success;
1964 // This decoder is called from multiple location that do not check
1965 // the full encoding is valid before they do.
1966 if (fieldFromInstruction(Insn, 5, 1) != 0 ||
1967 fieldFromInstruction(Insn, 16, 1) != 0 ||
1968 fieldFromInstruction(Insn, 20, 8) != 0x10)
1969 return MCDisassembler::Fail;
1971 // imod == '01' --> UNPREDICTABLE
1972 // NOTE: Even though this is technically UNPREDICTABLE, we choose to
1973 // return failure here. The '01' imod value is unprintable, so there's
1974 // nothing useful we could do even if we returned UNPREDICTABLE.
1976 if (imod == 1) return MCDisassembler::Fail;
1979 Inst.setOpcode(ARM::CPS3p);
1980 Inst.addOperand(MCOperand::CreateImm(imod));
1981 Inst.addOperand(MCOperand::CreateImm(iflags));
1982 Inst.addOperand(MCOperand::CreateImm(mode));
1983 } else if (imod && !M) {
1984 Inst.setOpcode(ARM::CPS2p);
1985 Inst.addOperand(MCOperand::CreateImm(imod));
1986 Inst.addOperand(MCOperand::CreateImm(iflags));
1987 if (mode) S = MCDisassembler::SoftFail;
1988 } else if (!imod && M) {
1989 Inst.setOpcode(ARM::CPS1p);
1990 Inst.addOperand(MCOperand::CreateImm(mode));
1991 if (iflags) S = MCDisassembler::SoftFail;
1993 // imod == '00' && M == '0' --> UNPREDICTABLE
1994 Inst.setOpcode(ARM::CPS1p);
1995 Inst.addOperand(MCOperand::CreateImm(mode));
1996 S = MCDisassembler::SoftFail;
2002 static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn,
2003 uint64_t Address, const void *Decoder) {
2004 unsigned imod = fieldFromInstruction(Insn, 9, 2);
2005 unsigned M = fieldFromInstruction(Insn, 8, 1);
2006 unsigned iflags = fieldFromInstruction(Insn, 5, 3);
2007 unsigned mode = fieldFromInstruction(Insn, 0, 5);
2009 DecodeStatus S = MCDisassembler::Success;
2011 // imod == '01' --> UNPREDICTABLE
2012 // NOTE: Even though this is technically UNPREDICTABLE, we choose to
2013 // return failure here. The '01' imod value is unprintable, so there's
2014 // nothing useful we could do even if we returned UNPREDICTABLE.
2016 if (imod == 1) return MCDisassembler::Fail;
2019 Inst.setOpcode(ARM::t2CPS3p);
2020 Inst.addOperand(MCOperand::CreateImm(imod));
2021 Inst.addOperand(MCOperand::CreateImm(iflags));
2022 Inst.addOperand(MCOperand::CreateImm(mode));
2023 } else if (imod && !M) {
2024 Inst.setOpcode(ARM::t2CPS2p);
2025 Inst.addOperand(MCOperand::CreateImm(imod));
2026 Inst.addOperand(MCOperand::CreateImm(iflags));
2027 if (mode) S = MCDisassembler::SoftFail;
2028 } else if (!imod && M) {
2029 Inst.setOpcode(ARM::t2CPS1p);
2030 Inst.addOperand(MCOperand::CreateImm(mode));
2031 if (iflags) S = MCDisassembler::SoftFail;
2033 // imod == '00' && M == '0' --> this is a HINT instruction
2034 int imm = fieldFromInstruction(Insn, 0, 8);
2035 // HINT are defined only for immediate in [0..4]
2036 if(imm > 4) return MCDisassembler::Fail;
2037 Inst.setOpcode(ARM::t2HINT);
2038 Inst.addOperand(MCOperand::CreateImm(imm));
2044 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn,
2045 uint64_t Address, const void *Decoder) {
2046 DecodeStatus S = MCDisassembler::Success;
2048 unsigned Rd = fieldFromInstruction(Insn, 8, 4);
2051 imm |= (fieldFromInstruction(Insn, 0, 8) << 0);
2052 imm |= (fieldFromInstruction(Insn, 12, 3) << 8);
2053 imm |= (fieldFromInstruction(Insn, 16, 4) << 12);
2054 imm |= (fieldFromInstruction(Insn, 26, 1) << 11);
2056 if (Inst.getOpcode() == ARM::t2MOVTi16)
2057 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
2058 return MCDisassembler::Fail;
2059 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
2060 return MCDisassembler::Fail;
2062 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder))
2063 Inst.addOperand(MCOperand::CreateImm(imm));
2068 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn,
2069 uint64_t Address, const void *Decoder) {
2070 DecodeStatus S = MCDisassembler::Success;
2072 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2073 unsigned pred = fieldFromInstruction(Insn, 28, 4);
2076 imm |= (fieldFromInstruction(Insn, 0, 12) << 0);
2077 imm |= (fieldFromInstruction(Insn, 16, 4) << 12);
2079 if (Inst.getOpcode() == ARM::MOVTi16)
2080 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
2081 return MCDisassembler::Fail;
2083 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
2084 return MCDisassembler::Fail;
2086 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder))
2087 Inst.addOperand(MCOperand::CreateImm(imm));
2089 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2090 return MCDisassembler::Fail;
2095 static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn,
2096 uint64_t Address, const void *Decoder) {
2097 DecodeStatus S = MCDisassembler::Success;
2099 unsigned Rd = fieldFromInstruction(Insn, 16, 4);
2100 unsigned Rn = fieldFromInstruction(Insn, 0, 4);
2101 unsigned Rm = fieldFromInstruction(Insn, 8, 4);
2102 unsigned Ra = fieldFromInstruction(Insn, 12, 4);
2103 unsigned pred = fieldFromInstruction(Insn, 28, 4);
2106 return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
2108 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
2109 return MCDisassembler::Fail;
2110 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
2111 return MCDisassembler::Fail;
2112 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
2113 return MCDisassembler::Fail;
2114 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder)))
2115 return MCDisassembler::Fail;
2117 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2118 return MCDisassembler::Fail;
2123 static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val,
2124 uint64_t Address, const void *Decoder) {
2125 DecodeStatus S = MCDisassembler::Success;
2127 unsigned add = fieldFromInstruction(Val, 12, 1);
2128 unsigned imm = fieldFromInstruction(Val, 0, 12);
2129 unsigned Rn = fieldFromInstruction(Val, 13, 4);
2131 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2132 return MCDisassembler::Fail;
2134 if (!add) imm *= -1;
2135 if (imm == 0 && !add) imm = INT32_MIN;
2136 Inst.addOperand(MCOperand::CreateImm(imm));
2138 tryAddingPcLoadReferenceComment(Address, Address + imm + 8, Decoder);
2143 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val,
2144 uint64_t Address, const void *Decoder) {
2145 DecodeStatus S = MCDisassembler::Success;
2147 unsigned Rn = fieldFromInstruction(Val, 9, 4);
2148 unsigned U = fieldFromInstruction(Val, 8, 1);
2149 unsigned imm = fieldFromInstruction(Val, 0, 8);
2151 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2152 return MCDisassembler::Fail;
2155 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::add, imm)));
2157 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm)));
2162 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val,
2163 uint64_t Address, const void *Decoder) {
2164 return DecodeGPRRegisterClass(Inst, Val, Address, Decoder);
2168 DecodeT2BInstruction(MCInst &Inst, unsigned Insn,
2169 uint64_t Address, const void *Decoder) {
2170 DecodeStatus Status = MCDisassembler::Success;
2172 // Note the J1 and J2 values are from the encoded instruction. So here
2173 // change them to I1 and I2 values via as documented:
2174 // I1 = NOT(J1 EOR S);
2175 // I2 = NOT(J2 EOR S);
2176 // and build the imm32 with one trailing zero as documented:
2177 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32);
2178 unsigned S = fieldFromInstruction(Insn, 26, 1);
2179 unsigned J1 = fieldFromInstruction(Insn, 13, 1);
2180 unsigned J2 = fieldFromInstruction(Insn, 11, 1);
2181 unsigned I1 = !(J1 ^ S);
2182 unsigned I2 = !(J2 ^ S);
2183 unsigned imm10 = fieldFromInstruction(Insn, 16, 10);
2184 unsigned imm11 = fieldFromInstruction(Insn, 0, 11);
2185 unsigned tmp = (S << 23) | (I1 << 22) | (I2 << 21) | (imm10 << 11) | imm11;
2186 int imm32 = SignExtend32<25>(tmp << 1);
2187 if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4,
2188 true, 4, Inst, Decoder))
2189 Inst.addOperand(MCOperand::CreateImm(imm32));
2195 DecodeBranchImmInstruction(MCInst &Inst, unsigned Insn,
2196 uint64_t Address, const void *Decoder) {
2197 DecodeStatus S = MCDisassembler::Success;
2199 unsigned pred = fieldFromInstruction(Insn, 28, 4);
2200 unsigned imm = fieldFromInstruction(Insn, 0, 24) << 2;
2203 Inst.setOpcode(ARM::BLXi);
2204 imm |= fieldFromInstruction(Insn, 24, 1) << 1;
2205 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8,
2206 true, 4, Inst, Decoder))
2207 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm)));
2211 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8,
2212 true, 4, Inst, Decoder))
2213 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm)));
2214 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2215 return MCDisassembler::Fail;
2221 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val,
2222 uint64_t Address, const void *Decoder) {
2223 DecodeStatus S = MCDisassembler::Success;
2225 unsigned Rm = fieldFromInstruction(Val, 0, 4);
2226 unsigned align = fieldFromInstruction(Val, 4, 2);
2228 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2229 return MCDisassembler::Fail;
2231 Inst.addOperand(MCOperand::CreateImm(0));
2233 Inst.addOperand(MCOperand::CreateImm(4 << align));
2238 static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Insn,
2239 uint64_t Address, const void *Decoder) {
2240 DecodeStatus S = MCDisassembler::Success;
2242 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2243 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2244 unsigned wb = fieldFromInstruction(Insn, 16, 4);
2245 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2246 Rn |= fieldFromInstruction(Insn, 4, 2) << 4;
2247 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2249 // First output register
2250 switch (Inst.getOpcode()) {
2251 case ARM::VLD1q16: case ARM::VLD1q32: case ARM::VLD1q64: case ARM::VLD1q8:
2252 case ARM::VLD1q16wb_fixed: case ARM::VLD1q16wb_register:
2253 case ARM::VLD1q32wb_fixed: case ARM::VLD1q32wb_register:
2254 case ARM::VLD1q64wb_fixed: case ARM::VLD1q64wb_register:
2255 case ARM::VLD1q8wb_fixed: case ARM::VLD1q8wb_register:
2256 case ARM::VLD2d16: case ARM::VLD2d32: case ARM::VLD2d8:
2257 case ARM::VLD2d16wb_fixed: case ARM::VLD2d16wb_register:
2258 case ARM::VLD2d32wb_fixed: case ARM::VLD2d32wb_register:
2259 case ARM::VLD2d8wb_fixed: case ARM::VLD2d8wb_register:
2260 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2261 return MCDisassembler::Fail;
2266 case ARM::VLD2b16wb_fixed:
2267 case ARM::VLD2b16wb_register:
2268 case ARM::VLD2b32wb_fixed:
2269 case ARM::VLD2b32wb_register:
2270 case ARM::VLD2b8wb_fixed:
2271 case ARM::VLD2b8wb_register:
2272 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
2273 return MCDisassembler::Fail;
2276 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2277 return MCDisassembler::Fail;
2280 // Second output register
2281 switch (Inst.getOpcode()) {
2285 case ARM::VLD3d8_UPD:
2286 case ARM::VLD3d16_UPD:
2287 case ARM::VLD3d32_UPD:
2291 case ARM::VLD4d8_UPD:
2292 case ARM::VLD4d16_UPD:
2293 case ARM::VLD4d32_UPD:
2294 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
2295 return MCDisassembler::Fail;
2300 case ARM::VLD3q8_UPD:
2301 case ARM::VLD3q16_UPD:
2302 case ARM::VLD3q32_UPD:
2306 case ARM::VLD4q8_UPD:
2307 case ARM::VLD4q16_UPD:
2308 case ARM::VLD4q32_UPD:
2309 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2310 return MCDisassembler::Fail;
2315 // Third output register
2316 switch(Inst.getOpcode()) {
2320 case ARM::VLD3d8_UPD:
2321 case ARM::VLD3d16_UPD:
2322 case ARM::VLD3d32_UPD:
2326 case ARM::VLD4d8_UPD:
2327 case ARM::VLD4d16_UPD:
2328 case ARM::VLD4d32_UPD:
2329 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2330 return MCDisassembler::Fail;
2335 case ARM::VLD3q8_UPD:
2336 case ARM::VLD3q16_UPD:
2337 case ARM::VLD3q32_UPD:
2341 case ARM::VLD4q8_UPD:
2342 case ARM::VLD4q16_UPD:
2343 case ARM::VLD4q32_UPD:
2344 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
2345 return MCDisassembler::Fail;
2351 // Fourth output register
2352 switch (Inst.getOpcode()) {
2356 case ARM::VLD4d8_UPD:
2357 case ARM::VLD4d16_UPD:
2358 case ARM::VLD4d32_UPD:
2359 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
2360 return MCDisassembler::Fail;
2365 case ARM::VLD4q8_UPD:
2366 case ARM::VLD4q16_UPD:
2367 case ARM::VLD4q32_UPD:
2368 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
2369 return MCDisassembler::Fail;
2375 // Writeback operand
2376 switch (Inst.getOpcode()) {
2377 case ARM::VLD1d8wb_fixed:
2378 case ARM::VLD1d16wb_fixed:
2379 case ARM::VLD1d32wb_fixed:
2380 case ARM::VLD1d64wb_fixed:
2381 case ARM::VLD1d8wb_register:
2382 case ARM::VLD1d16wb_register:
2383 case ARM::VLD1d32wb_register:
2384 case ARM::VLD1d64wb_register:
2385 case ARM::VLD1q8wb_fixed:
2386 case ARM::VLD1q16wb_fixed:
2387 case ARM::VLD1q32wb_fixed:
2388 case ARM::VLD1q64wb_fixed:
2389 case ARM::VLD1q8wb_register:
2390 case ARM::VLD1q16wb_register:
2391 case ARM::VLD1q32wb_register:
2392 case ARM::VLD1q64wb_register:
2393 case ARM::VLD1d8Twb_fixed:
2394 case ARM::VLD1d8Twb_register:
2395 case ARM::VLD1d16Twb_fixed:
2396 case ARM::VLD1d16Twb_register:
2397 case ARM::VLD1d32Twb_fixed:
2398 case ARM::VLD1d32Twb_register:
2399 case ARM::VLD1d64Twb_fixed:
2400 case ARM::VLD1d64Twb_register:
2401 case ARM::VLD1d8Qwb_fixed:
2402 case ARM::VLD1d8Qwb_register:
2403 case ARM::VLD1d16Qwb_fixed:
2404 case ARM::VLD1d16Qwb_register:
2405 case ARM::VLD1d32Qwb_fixed:
2406 case ARM::VLD1d32Qwb_register:
2407 case ARM::VLD1d64Qwb_fixed:
2408 case ARM::VLD1d64Qwb_register:
2409 case ARM::VLD2d8wb_fixed:
2410 case ARM::VLD2d16wb_fixed:
2411 case ARM::VLD2d32wb_fixed:
2412 case ARM::VLD2q8wb_fixed:
2413 case ARM::VLD2q16wb_fixed:
2414 case ARM::VLD2q32wb_fixed:
2415 case ARM::VLD2d8wb_register:
2416 case ARM::VLD2d16wb_register:
2417 case ARM::VLD2d32wb_register:
2418 case ARM::VLD2q8wb_register:
2419 case ARM::VLD2q16wb_register:
2420 case ARM::VLD2q32wb_register:
2421 case ARM::VLD2b8wb_fixed:
2422 case ARM::VLD2b16wb_fixed:
2423 case ARM::VLD2b32wb_fixed:
2424 case ARM::VLD2b8wb_register:
2425 case ARM::VLD2b16wb_register:
2426 case ARM::VLD2b32wb_register:
2427 Inst.addOperand(MCOperand::CreateImm(0));
2429 case ARM::VLD3d8_UPD:
2430 case ARM::VLD3d16_UPD:
2431 case ARM::VLD3d32_UPD:
2432 case ARM::VLD3q8_UPD:
2433 case ARM::VLD3q16_UPD:
2434 case ARM::VLD3q32_UPD:
2435 case ARM::VLD4d8_UPD:
2436 case ARM::VLD4d16_UPD:
2437 case ARM::VLD4d32_UPD:
2438 case ARM::VLD4q8_UPD:
2439 case ARM::VLD4q16_UPD:
2440 case ARM::VLD4q32_UPD:
2441 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
2442 return MCDisassembler::Fail;
2448 // AddrMode6 Base (register+alignment)
2449 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
2450 return MCDisassembler::Fail;
2452 // AddrMode6 Offset (register)
2453 switch (Inst.getOpcode()) {
2455 // The below have been updated to have explicit am6offset split
2456 // between fixed and register offset. For those instructions not
2457 // yet updated, we need to add an additional reg0 operand for the
2460 // The fixed offset encodes as Rm == 0xd, so we check for that.
2462 Inst.addOperand(MCOperand::CreateReg(0));
2465 // Fall through to handle the register offset variant.
2466 case ARM::VLD1d8wb_fixed:
2467 case ARM::VLD1d16wb_fixed:
2468 case ARM::VLD1d32wb_fixed:
2469 case ARM::VLD1d64wb_fixed:
2470 case ARM::VLD1d8Twb_fixed:
2471 case ARM::VLD1d16Twb_fixed:
2472 case ARM::VLD1d32Twb_fixed:
2473 case ARM::VLD1d64Twb_fixed:
2474 case ARM::VLD1d8Qwb_fixed:
2475 case ARM::VLD1d16Qwb_fixed:
2476 case ARM::VLD1d32Qwb_fixed:
2477 case ARM::VLD1d64Qwb_fixed:
2478 case ARM::VLD1d8wb_register:
2479 case ARM::VLD1d16wb_register:
2480 case ARM::VLD1d32wb_register:
2481 case ARM::VLD1d64wb_register:
2482 case ARM::VLD1q8wb_fixed:
2483 case ARM::VLD1q16wb_fixed:
2484 case ARM::VLD1q32wb_fixed:
2485 case ARM::VLD1q64wb_fixed:
2486 case ARM::VLD1q8wb_register:
2487 case ARM::VLD1q16wb_register:
2488 case ARM::VLD1q32wb_register:
2489 case ARM::VLD1q64wb_register:
2490 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback
2491 // variant encodes Rm == 0xf. Anything else is a register offset post-
2492 // increment and we need to add the register operand to the instruction.
2493 if (Rm != 0xD && Rm != 0xF &&
2494 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2495 return MCDisassembler::Fail;
2497 case ARM::VLD2d8wb_fixed:
2498 case ARM::VLD2d16wb_fixed:
2499 case ARM::VLD2d32wb_fixed:
2500 case ARM::VLD2b8wb_fixed:
2501 case ARM::VLD2b16wb_fixed:
2502 case ARM::VLD2b32wb_fixed:
2503 case ARM::VLD2q8wb_fixed:
2504 case ARM::VLD2q16wb_fixed:
2505 case ARM::VLD2q32wb_fixed:
2512 static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Insn,
2513 uint64_t Address, const void *Decoder) {
2514 unsigned type = fieldFromInstruction(Insn, 8, 4);
2515 unsigned align = fieldFromInstruction(Insn, 4, 2);
2516 if (type == 6 && (align & 2)) return MCDisassembler::Fail;
2517 if (type == 7 && (align & 2)) return MCDisassembler::Fail;
2518 if (type == 10 && align == 3) return MCDisassembler::Fail;
2520 unsigned load = fieldFromInstruction(Insn, 21, 1);
2521 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
2522 : DecodeVSTInstruction(Inst, Insn, Address, Decoder);
2525 static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Insn,
2526 uint64_t Address, const void *Decoder) {
2527 unsigned size = fieldFromInstruction(Insn, 6, 2);
2528 if (size == 3) return MCDisassembler::Fail;
2530 unsigned type = fieldFromInstruction(Insn, 8, 4);
2531 unsigned align = fieldFromInstruction(Insn, 4, 2);
2532 if (type == 8 && align == 3) return MCDisassembler::Fail;
2533 if (type == 9 && align == 3) return MCDisassembler::Fail;
2535 unsigned load = fieldFromInstruction(Insn, 21, 1);
2536 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
2537 : DecodeVSTInstruction(Inst, Insn, Address, Decoder);
2540 static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Insn,
2541 uint64_t Address, const void *Decoder) {
2542 unsigned size = fieldFromInstruction(Insn, 6, 2);
2543 if (size == 3) return MCDisassembler::Fail;
2545 unsigned align = fieldFromInstruction(Insn, 4, 2);
2546 if (align & 2) return MCDisassembler::Fail;
2548 unsigned load = fieldFromInstruction(Insn, 21, 1);
2549 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
2550 : DecodeVSTInstruction(Inst, Insn, Address, Decoder);
2553 static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Insn,
2554 uint64_t Address, const void *Decoder) {
2555 unsigned size = fieldFromInstruction(Insn, 6, 2);
2556 if (size == 3) return MCDisassembler::Fail;
2558 unsigned load = fieldFromInstruction(Insn, 21, 1);
2559 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
2560 : DecodeVSTInstruction(Inst, Insn, Address, Decoder);
2563 static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Insn,
2564 uint64_t Address, const void *Decoder) {
2565 DecodeStatus S = MCDisassembler::Success;
2567 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2568 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2569 unsigned wb = fieldFromInstruction(Insn, 16, 4);
2570 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2571 Rn |= fieldFromInstruction(Insn, 4, 2) << 4;
2572 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2574 // Writeback Operand
2575 switch (Inst.getOpcode()) {
2576 case ARM::VST1d8wb_fixed:
2577 case ARM::VST1d16wb_fixed:
2578 case ARM::VST1d32wb_fixed:
2579 case ARM::VST1d64wb_fixed:
2580 case ARM::VST1d8wb_register:
2581 case ARM::VST1d16wb_register:
2582 case ARM::VST1d32wb_register:
2583 case ARM::VST1d64wb_register:
2584 case ARM::VST1q8wb_fixed:
2585 case ARM::VST1q16wb_fixed:
2586 case ARM::VST1q32wb_fixed:
2587 case ARM::VST1q64wb_fixed:
2588 case ARM::VST1q8wb_register:
2589 case ARM::VST1q16wb_register:
2590 case ARM::VST1q32wb_register:
2591 case ARM::VST1q64wb_register:
2592 case ARM::VST1d8Twb_fixed:
2593 case ARM::VST1d16Twb_fixed:
2594 case ARM::VST1d32Twb_fixed:
2595 case ARM::VST1d64Twb_fixed:
2596 case ARM::VST1d8Twb_register:
2597 case ARM::VST1d16Twb_register:
2598 case ARM::VST1d32Twb_register:
2599 case ARM::VST1d64Twb_register:
2600 case ARM::VST1d8Qwb_fixed:
2601 case ARM::VST1d16Qwb_fixed:
2602 case ARM::VST1d32Qwb_fixed:
2603 case ARM::VST1d64Qwb_fixed:
2604 case ARM::VST1d8Qwb_register:
2605 case ARM::VST1d16Qwb_register:
2606 case ARM::VST1d32Qwb_register:
2607 case ARM::VST1d64Qwb_register:
2608 case ARM::VST2d8wb_fixed:
2609 case ARM::VST2d16wb_fixed:
2610 case ARM::VST2d32wb_fixed:
2611 case ARM::VST2d8wb_register:
2612 case ARM::VST2d16wb_register:
2613 case ARM::VST2d32wb_register:
2614 case ARM::VST2q8wb_fixed:
2615 case ARM::VST2q16wb_fixed:
2616 case ARM::VST2q32wb_fixed:
2617 case ARM::VST2q8wb_register:
2618 case ARM::VST2q16wb_register:
2619 case ARM::VST2q32wb_register:
2620 case ARM::VST2b8wb_fixed:
2621 case ARM::VST2b16wb_fixed:
2622 case ARM::VST2b32wb_fixed:
2623 case ARM::VST2b8wb_register:
2624 case ARM::VST2b16wb_register:
2625 case ARM::VST2b32wb_register:
2627 return MCDisassembler::Fail;
2628 Inst.addOperand(MCOperand::CreateImm(0));
2630 case ARM::VST3d8_UPD:
2631 case ARM::VST3d16_UPD:
2632 case ARM::VST3d32_UPD:
2633 case ARM::VST3q8_UPD:
2634 case ARM::VST3q16_UPD:
2635 case ARM::VST3q32_UPD:
2636 case ARM::VST4d8_UPD:
2637 case ARM::VST4d16_UPD:
2638 case ARM::VST4d32_UPD:
2639 case ARM::VST4q8_UPD:
2640 case ARM::VST4q16_UPD:
2641 case ARM::VST4q32_UPD:
2642 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
2643 return MCDisassembler::Fail;
2649 // AddrMode6 Base (register+alignment)
2650 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
2651 return MCDisassembler::Fail;
2653 // AddrMode6 Offset (register)
2654 switch (Inst.getOpcode()) {
2657 Inst.addOperand(MCOperand::CreateReg(0));
2658 else if (Rm != 0xF) {
2659 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2660 return MCDisassembler::Fail;
2663 case ARM::VST1d8wb_fixed:
2664 case ARM::VST1d16wb_fixed:
2665 case ARM::VST1d32wb_fixed:
2666 case ARM::VST1d64wb_fixed:
2667 case ARM::VST1q8wb_fixed:
2668 case ARM::VST1q16wb_fixed:
2669 case ARM::VST1q32wb_fixed:
2670 case ARM::VST1q64wb_fixed:
2671 case ARM::VST1d8Twb_fixed:
2672 case ARM::VST1d16Twb_fixed:
2673 case ARM::VST1d32Twb_fixed:
2674 case ARM::VST1d64Twb_fixed:
2675 case ARM::VST1d8Qwb_fixed:
2676 case ARM::VST1d16Qwb_fixed:
2677 case ARM::VST1d32Qwb_fixed:
2678 case ARM::VST1d64Qwb_fixed:
2679 case ARM::VST2d8wb_fixed:
2680 case ARM::VST2d16wb_fixed:
2681 case ARM::VST2d32wb_fixed:
2682 case ARM::VST2q8wb_fixed:
2683 case ARM::VST2q16wb_fixed:
2684 case ARM::VST2q32wb_fixed:
2685 case ARM::VST2b8wb_fixed:
2686 case ARM::VST2b16wb_fixed:
2687 case ARM::VST2b32wb_fixed:
2692 // First input register
2693 switch (Inst.getOpcode()) {
2698 case ARM::VST1q16wb_fixed:
2699 case ARM::VST1q16wb_register:
2700 case ARM::VST1q32wb_fixed:
2701 case ARM::VST1q32wb_register:
2702 case ARM::VST1q64wb_fixed:
2703 case ARM::VST1q64wb_register:
2704 case ARM::VST1q8wb_fixed:
2705 case ARM::VST1q8wb_register:
2709 case ARM::VST2d16wb_fixed:
2710 case ARM::VST2d16wb_register:
2711 case ARM::VST2d32wb_fixed:
2712 case ARM::VST2d32wb_register:
2713 case ARM::VST2d8wb_fixed:
2714 case ARM::VST2d8wb_register:
2715 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2716 return MCDisassembler::Fail;
2721 case ARM::VST2b16wb_fixed:
2722 case ARM::VST2b16wb_register:
2723 case ARM::VST2b32wb_fixed:
2724 case ARM::VST2b32wb_register:
2725 case ARM::VST2b8wb_fixed:
2726 case ARM::VST2b8wb_register:
2727 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
2728 return MCDisassembler::Fail;
2731 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2732 return MCDisassembler::Fail;
2735 // Second input register
2736 switch (Inst.getOpcode()) {
2740 case ARM::VST3d8_UPD:
2741 case ARM::VST3d16_UPD:
2742 case ARM::VST3d32_UPD:
2746 case ARM::VST4d8_UPD:
2747 case ARM::VST4d16_UPD:
2748 case ARM::VST4d32_UPD:
2749 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
2750 return MCDisassembler::Fail;
2755 case ARM::VST3q8_UPD:
2756 case ARM::VST3q16_UPD:
2757 case ARM::VST3q32_UPD:
2761 case ARM::VST4q8_UPD:
2762 case ARM::VST4q16_UPD:
2763 case ARM::VST4q32_UPD:
2764 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2765 return MCDisassembler::Fail;
2771 // Third input register
2772 switch (Inst.getOpcode()) {
2776 case ARM::VST3d8_UPD:
2777 case ARM::VST3d16_UPD:
2778 case ARM::VST3d32_UPD:
2782 case ARM::VST4d8_UPD:
2783 case ARM::VST4d16_UPD:
2784 case ARM::VST4d32_UPD:
2785 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2786 return MCDisassembler::Fail;
2791 case ARM::VST3q8_UPD:
2792 case ARM::VST3q16_UPD:
2793 case ARM::VST3q32_UPD:
2797 case ARM::VST4q8_UPD:
2798 case ARM::VST4q16_UPD:
2799 case ARM::VST4q32_UPD:
2800 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
2801 return MCDisassembler::Fail;
2807 // Fourth input register
2808 switch (Inst.getOpcode()) {
2812 case ARM::VST4d8_UPD:
2813 case ARM::VST4d16_UPD:
2814 case ARM::VST4d32_UPD:
2815 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
2816 return MCDisassembler::Fail;
2821 case ARM::VST4q8_UPD:
2822 case ARM::VST4q16_UPD:
2823 case ARM::VST4q32_UPD:
2824 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
2825 return MCDisassembler::Fail;
2834 static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Insn,
2835 uint64_t Address, const void *Decoder) {
2836 DecodeStatus S = MCDisassembler::Success;
2838 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2839 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2840 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2841 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2842 unsigned align = fieldFromInstruction(Insn, 4, 1);
2843 unsigned size = fieldFromInstruction(Insn, 6, 2);
2845 if (size == 0 && align == 1)
2846 return MCDisassembler::Fail;
2847 align *= (1 << size);
2849 switch (Inst.getOpcode()) {
2850 case ARM::VLD1DUPq16: case ARM::VLD1DUPq32: case ARM::VLD1DUPq8:
2851 case ARM::VLD1DUPq16wb_fixed: case ARM::VLD1DUPq16wb_register:
2852 case ARM::VLD1DUPq32wb_fixed: case ARM::VLD1DUPq32wb_register:
2853 case ARM::VLD1DUPq8wb_fixed: case ARM::VLD1DUPq8wb_register:
2854 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2855 return MCDisassembler::Fail;
2858 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2859 return MCDisassembler::Fail;
2863 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2864 return MCDisassembler::Fail;
2867 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2868 return MCDisassembler::Fail;
2869 Inst.addOperand(MCOperand::CreateImm(align));
2871 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback
2872 // variant encodes Rm == 0xf. Anything else is a register offset post-
2873 // increment and we need to add the register operand to the instruction.
2874 if (Rm != 0xD && Rm != 0xF &&
2875 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2876 return MCDisassembler::Fail;
2881 static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Insn,
2882 uint64_t Address, const void *Decoder) {
2883 DecodeStatus S = MCDisassembler::Success;
2885 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2886 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2887 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2888 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2889 unsigned align = fieldFromInstruction(Insn, 4, 1);
2890 unsigned size = 1 << fieldFromInstruction(Insn, 6, 2);
2893 switch (Inst.getOpcode()) {
2894 case ARM::VLD2DUPd16: case ARM::VLD2DUPd32: case ARM::VLD2DUPd8:
2895 case ARM::VLD2DUPd16wb_fixed: case ARM::VLD2DUPd16wb_register:
2896 case ARM::VLD2DUPd32wb_fixed: case ARM::VLD2DUPd32wb_register:
2897 case ARM::VLD2DUPd8wb_fixed: case ARM::VLD2DUPd8wb_register:
2898 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2899 return MCDisassembler::Fail;
2901 case ARM::VLD2DUPd16x2: case ARM::VLD2DUPd32x2: case ARM::VLD2DUPd8x2:
2902 case ARM::VLD2DUPd16x2wb_fixed: case ARM::VLD2DUPd16x2wb_register:
2903 case ARM::VLD2DUPd32x2wb_fixed: case ARM::VLD2DUPd32x2wb_register:
2904 case ARM::VLD2DUPd8x2wb_fixed: case ARM::VLD2DUPd8x2wb_register:
2905 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
2906 return MCDisassembler::Fail;
2909 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2910 return MCDisassembler::Fail;
2915 Inst.addOperand(MCOperand::CreateImm(0));
2917 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2918 return MCDisassembler::Fail;
2919 Inst.addOperand(MCOperand::CreateImm(align));
2921 if (Rm != 0xD && Rm != 0xF) {
2922 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2923 return MCDisassembler::Fail;
2929 static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Insn,
2930 uint64_t Address, const void *Decoder) {
2931 DecodeStatus S = MCDisassembler::Success;
2933 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2934 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2935 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2936 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2937 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1;
2939 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2940 return MCDisassembler::Fail;
2941 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
2942 return MCDisassembler::Fail;
2943 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
2944 return MCDisassembler::Fail;
2946 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2947 return MCDisassembler::Fail;
2950 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2951 return MCDisassembler::Fail;
2952 Inst.addOperand(MCOperand::CreateImm(0));
2955 Inst.addOperand(MCOperand::CreateReg(0));
2956 else if (Rm != 0xF) {
2957 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2958 return MCDisassembler::Fail;
2964 static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Insn,
2965 uint64_t Address, const void *Decoder) {
2966 DecodeStatus S = MCDisassembler::Success;
2968 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2969 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2970 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2971 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2972 unsigned size = fieldFromInstruction(Insn, 6, 2);
2973 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1;
2974 unsigned align = fieldFromInstruction(Insn, 4, 1);
2978 return MCDisassembler::Fail;
2989 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2990 return MCDisassembler::Fail;
2991 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
2992 return MCDisassembler::Fail;
2993 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
2994 return MCDisassembler::Fail;
2995 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder)))
2996 return MCDisassembler::Fail;
2998 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2999 return MCDisassembler::Fail;
3002 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3003 return MCDisassembler::Fail;
3004 Inst.addOperand(MCOperand::CreateImm(align));
3007 Inst.addOperand(MCOperand::CreateReg(0));
3008 else if (Rm != 0xF) {
3009 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3010 return MCDisassembler::Fail;
3017 DecodeNEONModImmInstruction(MCInst &Inst, unsigned Insn,
3018 uint64_t Address, const void *Decoder) {
3019 DecodeStatus S = MCDisassembler::Success;
3021 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3022 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3023 unsigned imm = fieldFromInstruction(Insn, 0, 4);
3024 imm |= fieldFromInstruction(Insn, 16, 3) << 4;
3025 imm |= fieldFromInstruction(Insn, 24, 1) << 7;
3026 imm |= fieldFromInstruction(Insn, 8, 4) << 8;
3027 imm |= fieldFromInstruction(Insn, 5, 1) << 12;
3028 unsigned Q = fieldFromInstruction(Insn, 6, 1);
3031 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
3032 return MCDisassembler::Fail;
3034 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3035 return MCDisassembler::Fail;
3038 Inst.addOperand(MCOperand::CreateImm(imm));
3040 switch (Inst.getOpcode()) {
3041 case ARM::VORRiv4i16:
3042 case ARM::VORRiv2i32:
3043 case ARM::VBICiv4i16:
3044 case ARM::VBICiv2i32:
3045 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3046 return MCDisassembler::Fail;
3048 case ARM::VORRiv8i16:
3049 case ARM::VORRiv4i32:
3050 case ARM::VBICiv8i16:
3051 case ARM::VBICiv4i32:
3052 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
3053 return MCDisassembler::Fail;
3062 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Insn,
3063 uint64_t Address, const void *Decoder) {
3064 DecodeStatus S = MCDisassembler::Success;
3066 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3067 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3068 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3069 Rm |= fieldFromInstruction(Insn, 5, 1) << 4;
3070 unsigned size = fieldFromInstruction(Insn, 18, 2);
3072 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
3073 return MCDisassembler::Fail;
3074 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
3075 return MCDisassembler::Fail;
3076 Inst.addOperand(MCOperand::CreateImm(8 << size));
3081 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val,
3082 uint64_t Address, const void *Decoder) {
3083 Inst.addOperand(MCOperand::CreateImm(8 - Val));
3084 return MCDisassembler::Success;
3087 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val,
3088 uint64_t Address, const void *Decoder) {
3089 Inst.addOperand(MCOperand::CreateImm(16 - Val));
3090 return MCDisassembler::Success;
3093 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val,
3094 uint64_t Address, const void *Decoder) {
3095 Inst.addOperand(MCOperand::CreateImm(32 - Val));
3096 return MCDisassembler::Success;
3099 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val,
3100 uint64_t Address, const void *Decoder) {
3101 Inst.addOperand(MCOperand::CreateImm(64 - Val));
3102 return MCDisassembler::Success;
3105 static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn,
3106 uint64_t Address, const void *Decoder) {
3107 DecodeStatus S = MCDisassembler::Success;
3109 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3110 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3111 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3112 Rn |= fieldFromInstruction(Insn, 7, 1) << 4;
3113 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3114 Rm |= fieldFromInstruction(Insn, 5, 1) << 4;
3115 unsigned op = fieldFromInstruction(Insn, 6, 1);
3117 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3118 return MCDisassembler::Fail;
3120 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3121 return MCDisassembler::Fail; // Writeback
3124 switch (Inst.getOpcode()) {
3127 if (!Check(S, DecodeDPairRegisterClass(Inst, Rn, Address, Decoder)))
3128 return MCDisassembler::Fail;
3131 if (!Check(S, DecodeDPRRegisterClass(Inst, Rn, Address, Decoder)))
3132 return MCDisassembler::Fail;
3135 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
3136 return MCDisassembler::Fail;
3141 static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn,
3142 uint64_t Address, const void *Decoder) {
3143 DecodeStatus S = MCDisassembler::Success;
3145 unsigned dst = fieldFromInstruction(Insn, 8, 3);
3146 unsigned imm = fieldFromInstruction(Insn, 0, 8);
3148 if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder)))
3149 return MCDisassembler::Fail;
3151 switch(Inst.getOpcode()) {
3153 return MCDisassembler::Fail;
3155 break; // tADR does not explicitly represent the PC as an operand.
3157 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3161 Inst.addOperand(MCOperand::CreateImm(imm));
3165 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val,
3166 uint64_t Address, const void *Decoder) {
3167 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<12>(Val<<1) + 4,
3168 true, 2, Inst, Decoder))
3169 Inst.addOperand(MCOperand::CreateImm(SignExtend32<12>(Val << 1)));
3170 return MCDisassembler::Success;
3173 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val,
3174 uint64_t Address, const void *Decoder) {
3175 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<21>(Val) + 4,
3176 true, 4, Inst, Decoder))
3177 Inst.addOperand(MCOperand::CreateImm(SignExtend32<21>(Val)));
3178 return MCDisassembler::Success;
3181 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val,
3182 uint64_t Address, const void *Decoder) {
3183 if (!tryAddingSymbolicOperand(Address, Address + (Val<<1) + 4,
3184 true, 2, Inst, Decoder))
3185 Inst.addOperand(MCOperand::CreateImm(Val << 1));
3186 return MCDisassembler::Success;
3189 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val,
3190 uint64_t Address, const void *Decoder) {
3191 DecodeStatus S = MCDisassembler::Success;
3193 unsigned Rn = fieldFromInstruction(Val, 0, 3);
3194 unsigned Rm = fieldFromInstruction(Val, 3, 3);
3196 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
3197 return MCDisassembler::Fail;
3198 if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder)))
3199 return MCDisassembler::Fail;
3204 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val,
3205 uint64_t Address, const void *Decoder) {
3206 DecodeStatus S = MCDisassembler::Success;
3208 unsigned Rn = fieldFromInstruction(Val, 0, 3);
3209 unsigned imm = fieldFromInstruction(Val, 3, 5);
3211 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
3212 return MCDisassembler::Fail;
3213 Inst.addOperand(MCOperand::CreateImm(imm));
3218 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val,
3219 uint64_t Address, const void *Decoder) {
3220 unsigned imm = Val << 2;
3222 Inst.addOperand(MCOperand::CreateImm(imm));
3223 tryAddingPcLoadReferenceComment(Address, (Address & ~2u) + imm + 4, Decoder);
3225 return MCDisassembler::Success;
3228 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val,
3229 uint64_t Address, const void *Decoder) {
3230 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3231 Inst.addOperand(MCOperand::CreateImm(Val));
3233 return MCDisassembler::Success;
3236 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val,
3237 uint64_t Address, const void *Decoder) {
3238 DecodeStatus S = MCDisassembler::Success;
3240 unsigned Rn = fieldFromInstruction(Val, 6, 4);
3241 unsigned Rm = fieldFromInstruction(Val, 2, 4);
3242 unsigned imm = fieldFromInstruction(Val, 0, 2);
3244 // Thumb stores cannot use PC as dest register.
3245 switch (Inst.getOpcode()) {
3250 return MCDisassembler::Fail;
3255 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3256 return MCDisassembler::Fail;
3257 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
3258 return MCDisassembler::Fail;
3259 Inst.addOperand(MCOperand::CreateImm(imm));
3264 static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Insn,
3265 uint64_t Address, const void *Decoder) {
3266 DecodeStatus S = MCDisassembler::Success;
3268 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3269 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3271 const FeatureBitset &featureBits =
3272 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
3274 bool hasMP = featureBits[ARM::FeatureMP];
3275 bool hasV7Ops = featureBits[ARM::HasV7Ops];
3278 switch (Inst.getOpcode()) {
3280 Inst.setOpcode(ARM::t2LDRBpci);
3283 Inst.setOpcode(ARM::t2LDRHpci);
3286 Inst.setOpcode(ARM::t2LDRSHpci);
3289 Inst.setOpcode(ARM::t2LDRSBpci);
3292 Inst.setOpcode(ARM::t2LDRpci);
3295 Inst.setOpcode(ARM::t2PLDpci);
3298 Inst.setOpcode(ARM::t2PLIpci);
3301 return MCDisassembler::Fail;
3304 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
3308 switch (Inst.getOpcode()) {
3310 return MCDisassembler::Fail;
3312 Inst.setOpcode(ARM::t2PLDWs);
3315 Inst.setOpcode(ARM::t2PLIs);
3321 switch (Inst.getOpcode()) {
3326 return MCDisassembler::Fail;
3329 if (!hasV7Ops || !hasMP)
3330 return MCDisassembler::Fail;
3333 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3334 return MCDisassembler::Fail;
3337 unsigned addrmode = fieldFromInstruction(Insn, 4, 2);
3338 addrmode |= fieldFromInstruction(Insn, 0, 4) << 2;
3339 addrmode |= fieldFromInstruction(Insn, 16, 4) << 6;
3340 if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder)))
3341 return MCDisassembler::Fail;
3346 static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn,
3347 uint64_t Address, const void* Decoder) {
3348 DecodeStatus S = MCDisassembler::Success;
3350 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3351 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3352 unsigned U = fieldFromInstruction(Insn, 9, 1);
3353 unsigned imm = fieldFromInstruction(Insn, 0, 8);
3356 unsigned add = fieldFromInstruction(Insn, 9, 1);
3358 const FeatureBitset &featureBits =
3359 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
3361 bool hasMP = featureBits[ARM::FeatureMP];
3362 bool hasV7Ops = featureBits[ARM::HasV7Ops];
3365 switch (Inst.getOpcode()) {
3367 Inst.setOpcode(ARM::t2LDRpci);
3370 Inst.setOpcode(ARM::t2LDRBpci);
3372 case ARM::t2LDRSBi8:
3373 Inst.setOpcode(ARM::t2LDRSBpci);
3376 Inst.setOpcode(ARM::t2LDRHpci);
3378 case ARM::t2LDRSHi8:
3379 Inst.setOpcode(ARM::t2LDRSHpci);
3382 Inst.setOpcode(ARM::t2PLDpci);
3385 Inst.setOpcode(ARM::t2PLIpci);
3388 return MCDisassembler::Fail;
3390 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
3394 switch (Inst.getOpcode()) {
3395 case ARM::t2LDRSHi8:
3396 return MCDisassembler::Fail;
3399 Inst.setOpcode(ARM::t2PLDWi8);
3401 case ARM::t2LDRSBi8:
3402 Inst.setOpcode(ARM::t2PLIi8);
3409 switch (Inst.getOpcode()) {
3414 return MCDisassembler::Fail;
3417 if (!hasV7Ops || !hasMP)
3418 return MCDisassembler::Fail;
3421 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3422 return MCDisassembler::Fail;
3425 if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder)))
3426 return MCDisassembler::Fail;
3430 static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn,
3431 uint64_t Address, const void* Decoder) {
3432 DecodeStatus S = MCDisassembler::Success;
3434 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3435 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3436 unsigned imm = fieldFromInstruction(Insn, 0, 12);
3439 const FeatureBitset &featureBits =
3440 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
3442 bool hasMP = featureBits[ARM::FeatureMP];
3443 bool hasV7Ops = featureBits[ARM::HasV7Ops];
3446 switch (Inst.getOpcode()) {
3448 Inst.setOpcode(ARM::t2LDRpci);
3450 case ARM::t2LDRHi12:
3451 Inst.setOpcode(ARM::t2LDRHpci);
3453 case ARM::t2LDRSHi12:
3454 Inst.setOpcode(ARM::t2LDRSHpci);
3456 case ARM::t2LDRBi12:
3457 Inst.setOpcode(ARM::t2LDRBpci);
3459 case ARM::t2LDRSBi12:
3460 Inst.setOpcode(ARM::t2LDRSBpci);
3463 Inst.setOpcode(ARM::t2PLDpci);
3466 Inst.setOpcode(ARM::t2PLIpci);
3469 return MCDisassembler::Fail;
3471 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
3475 switch (Inst.getOpcode()) {
3476 case ARM::t2LDRSHi12:
3477 return MCDisassembler::Fail;
3478 case ARM::t2LDRHi12:
3479 Inst.setOpcode(ARM::t2PLDWi12);
3481 case ARM::t2LDRSBi12:
3482 Inst.setOpcode(ARM::t2PLIi12);
3489 switch (Inst.getOpcode()) {
3494 return MCDisassembler::Fail;
3496 case ARM::t2PLDWi12:
3497 if (!hasV7Ops || !hasMP)
3498 return MCDisassembler::Fail;
3501 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3502 return MCDisassembler::Fail;
3505 if (!Check(S, DecodeT2AddrModeImm12(Inst, imm, Address, Decoder)))
3506 return MCDisassembler::Fail;
3510 static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn,
3511 uint64_t Address, const void* Decoder) {
3512 DecodeStatus S = MCDisassembler::Success;
3514 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3515 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3516 unsigned imm = fieldFromInstruction(Insn, 0, 8);
3520 switch (Inst.getOpcode()) {
3522 Inst.setOpcode(ARM::t2LDRpci);
3525 Inst.setOpcode(ARM::t2LDRBpci);
3528 Inst.setOpcode(ARM::t2LDRHpci);
3531 Inst.setOpcode(ARM::t2LDRSBpci);
3534 Inst.setOpcode(ARM::t2LDRSHpci);
3537 return MCDisassembler::Fail;
3539 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
3542 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
3543 return MCDisassembler::Fail;
3544 if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder)))
3545 return MCDisassembler::Fail;
3549 static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn,
3550 uint64_t Address, const void* Decoder) {
3551 DecodeStatus S = MCDisassembler::Success;
3553 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3554 unsigned U = fieldFromInstruction(Insn, 23, 1);
3555 int imm = fieldFromInstruction(Insn, 0, 12);
3557 const FeatureBitset &featureBits =
3558 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
3560 bool hasV7Ops = featureBits[ARM::HasV7Ops];
3563 switch (Inst.getOpcode()) {
3564 case ARM::t2LDRBpci:
3565 case ARM::t2LDRHpci:
3566 Inst.setOpcode(ARM::t2PLDpci);
3568 case ARM::t2LDRSBpci:
3569 Inst.setOpcode(ARM::t2PLIpci);
3571 case ARM::t2LDRSHpci:
3572 return MCDisassembler::Fail;
3578 switch(Inst.getOpcode()) {
3583 return MCDisassembler::Fail;
3586 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3587 return MCDisassembler::Fail;
3591 // Special case for #-0.
3597 Inst.addOperand(MCOperand::CreateImm(imm));
3602 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val,
3603 uint64_t Address, const void *Decoder) {
3605 Inst.addOperand(MCOperand::CreateImm(INT32_MIN));
3607 int imm = Val & 0xFF;
3609 if (!(Val & 0x100)) imm *= -1;
3610 Inst.addOperand(MCOperand::CreateImm(imm * 4));
3613 return MCDisassembler::Success;
3616 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val,
3617 uint64_t Address, const void *Decoder) {
3618 DecodeStatus S = MCDisassembler::Success;
3620 unsigned Rn = fieldFromInstruction(Val, 9, 4);
3621 unsigned imm = fieldFromInstruction(Val, 0, 9);
3623 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3624 return MCDisassembler::Fail;
3625 if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder)))
3626 return MCDisassembler::Fail;
3631 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val,
3632 uint64_t Address, const void *Decoder) {
3633 DecodeStatus S = MCDisassembler::Success;
3635 unsigned Rn = fieldFromInstruction(Val, 8, 4);
3636 unsigned imm = fieldFromInstruction(Val, 0, 8);
3638 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
3639 return MCDisassembler::Fail;
3641 Inst.addOperand(MCOperand::CreateImm(imm));
3646 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val,
3647 uint64_t Address, const void *Decoder) {
3648 int imm = Val & 0xFF;
3651 else if (!(Val & 0x100))
3653 Inst.addOperand(MCOperand::CreateImm(imm));
3655 return MCDisassembler::Success;
3659 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val,
3660 uint64_t Address, const void *Decoder) {
3661 DecodeStatus S = MCDisassembler::Success;
3663 unsigned Rn = fieldFromInstruction(Val, 9, 4);
3664 unsigned imm = fieldFromInstruction(Val, 0, 9);
3666 // Thumb stores cannot use PC as dest register.
3667 switch (Inst.getOpcode()) {
3675 return MCDisassembler::Fail;
3681 // Some instructions always use an additive offset.
3682 switch (Inst.getOpcode()) {
3697 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3698 return MCDisassembler::Fail;
3699 if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder)))
3700 return MCDisassembler::Fail;
3705 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Insn,
3706 uint64_t Address, const void *Decoder) {
3707 DecodeStatus S = MCDisassembler::Success;
3709 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3710 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3711 unsigned addr = fieldFromInstruction(Insn, 0, 8);
3712 addr |= fieldFromInstruction(Insn, 9, 1) << 8;
3714 unsigned load = fieldFromInstruction(Insn, 20, 1);
3717 switch (Inst.getOpcode()) {
3718 case ARM::t2LDR_PRE:
3719 case ARM::t2LDR_POST:
3720 Inst.setOpcode(ARM::t2LDRpci);
3722 case ARM::t2LDRB_PRE:
3723 case ARM::t2LDRB_POST:
3724 Inst.setOpcode(ARM::t2LDRBpci);
3726 case ARM::t2LDRH_PRE:
3727 case ARM::t2LDRH_POST:
3728 Inst.setOpcode(ARM::t2LDRHpci);
3730 case ARM::t2LDRSB_PRE:
3731 case ARM::t2LDRSB_POST:
3733 Inst.setOpcode(ARM::t2PLIpci);
3735 Inst.setOpcode(ARM::t2LDRSBpci);
3737 case ARM::t2LDRSH_PRE:
3738 case ARM::t2LDRSH_POST:
3739 Inst.setOpcode(ARM::t2LDRSHpci);
3742 return MCDisassembler::Fail;
3744 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
3748 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3749 return MCDisassembler::Fail;
3752 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3753 return MCDisassembler::Fail;
3756 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3757 return MCDisassembler::Fail;
3760 if (!Check(S, DecodeT2AddrModeImm8(Inst, addr, Address, Decoder)))
3761 return MCDisassembler::Fail;
3766 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val,
3767 uint64_t Address, const void *Decoder) {
3768 DecodeStatus S = MCDisassembler::Success;
3770 unsigned Rn = fieldFromInstruction(Val, 13, 4);
3771 unsigned imm = fieldFromInstruction(Val, 0, 12);
3773 // Thumb stores cannot use PC as dest register.
3774 switch (Inst.getOpcode()) {
3776 case ARM::t2STRBi12:
3777 case ARM::t2STRHi12:
3779 return MCDisassembler::Fail;
3784 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3785 return MCDisassembler::Fail;
3786 Inst.addOperand(MCOperand::CreateImm(imm));
3792 static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Insn,
3793 uint64_t Address, const void *Decoder) {
3794 unsigned imm = fieldFromInstruction(Insn, 0, 7);
3796 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3797 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3798 Inst.addOperand(MCOperand::CreateImm(imm));
3800 return MCDisassembler::Success;
3803 static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn,
3804 uint64_t Address, const void *Decoder) {
3805 DecodeStatus S = MCDisassembler::Success;
3807 if (Inst.getOpcode() == ARM::tADDrSP) {
3808 unsigned Rdm = fieldFromInstruction(Insn, 0, 3);
3809 Rdm |= fieldFromInstruction(Insn, 7, 1) << 3;
3811 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
3812 return MCDisassembler::Fail;
3813 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3814 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
3815 return MCDisassembler::Fail;
3816 } else if (Inst.getOpcode() == ARM::tADDspr) {
3817 unsigned Rm = fieldFromInstruction(Insn, 3, 4);
3819 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3820 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3821 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3822 return MCDisassembler::Fail;
3828 static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn,
3829 uint64_t Address, const void *Decoder) {
3830 unsigned imod = fieldFromInstruction(Insn, 4, 1) | 0x2;
3831 unsigned flags = fieldFromInstruction(Insn, 0, 3);
3833 Inst.addOperand(MCOperand::CreateImm(imod));
3834 Inst.addOperand(MCOperand::CreateImm(flags));
3836 return MCDisassembler::Success;
3839 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn,
3840 uint64_t Address, const void *Decoder) {
3841 DecodeStatus S = MCDisassembler::Success;
3842 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3843 unsigned add = fieldFromInstruction(Insn, 4, 1);
3845 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
3846 return MCDisassembler::Fail;
3847 Inst.addOperand(MCOperand::CreateImm(add));
3852 static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Val,
3853 uint64_t Address, const void *Decoder) {
3854 // Val is passed in as S:J1:J2:imm10H:imm10L:'0'
3855 // Note only one trailing zero not two. Also the J1 and J2 values are from
3856 // the encoded instruction. So here change to I1 and I2 values via:
3857 // I1 = NOT(J1 EOR S);
3858 // I2 = NOT(J2 EOR S);
3859 // and build the imm32 with two trailing zeros as documented:
3860 // imm32 = SignExtend(S:I1:I2:imm10H:imm10L:'00', 32);
3861 unsigned S = (Val >> 23) & 1;
3862 unsigned J1 = (Val >> 22) & 1;
3863 unsigned J2 = (Val >> 21) & 1;
3864 unsigned I1 = !(J1 ^ S);
3865 unsigned I2 = !(J2 ^ S);
3866 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21);
3867 int imm32 = SignExtend32<25>(tmp << 1);
3869 if (!tryAddingSymbolicOperand(Address,
3870 (Address & ~2u) + imm32 + 4,
3871 true, 4, Inst, Decoder))
3872 Inst.addOperand(MCOperand::CreateImm(imm32));
3873 return MCDisassembler::Success;
3876 static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Val,
3877 uint64_t Address, const void *Decoder) {
3878 if (Val == 0xA || Val == 0xB)
3879 return MCDisassembler::Fail;
3881 const FeatureBitset &featureBits =
3882 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
3884 if (featureBits[ARM::HasV8Ops] && !(Val == 14 || Val == 15))
3885 return MCDisassembler::Fail;
3887 Inst.addOperand(MCOperand::CreateImm(Val));
3888 return MCDisassembler::Success;
3892 DecodeThumbTableBranch(MCInst &Inst, unsigned Insn,
3893 uint64_t Address, const void *Decoder) {
3894 DecodeStatus S = MCDisassembler::Success;
3896 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3897 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3899 if (Rn == ARM::SP) S = MCDisassembler::SoftFail;
3900 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3901 return MCDisassembler::Fail;
3902 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
3903 return MCDisassembler::Fail;
3908 DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Insn,
3909 uint64_t Address, const void *Decoder) {
3910 DecodeStatus S = MCDisassembler::Success;
3912 unsigned pred = fieldFromInstruction(Insn, 22, 4);
3913 if (pred == 0xE || pred == 0xF) {
3914 unsigned opc = fieldFromInstruction(Insn, 4, 28);
3917 return MCDisassembler::Fail;
3919 Inst.setOpcode(ARM::t2DSB);
3922 Inst.setOpcode(ARM::t2DMB);
3925 Inst.setOpcode(ARM::t2ISB);
3929 unsigned imm = fieldFromInstruction(Insn, 0, 4);
3930 return DecodeMemBarrierOption(Inst, imm, Address, Decoder);
3933 unsigned brtarget = fieldFromInstruction(Insn, 0, 11) << 1;
3934 brtarget |= fieldFromInstruction(Insn, 11, 1) << 19;
3935 brtarget |= fieldFromInstruction(Insn, 13, 1) << 18;
3936 brtarget |= fieldFromInstruction(Insn, 16, 6) << 12;
3937 brtarget |= fieldFromInstruction(Insn, 26, 1) << 20;
3939 if (!Check(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder)))
3940 return MCDisassembler::Fail;
3941 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3942 return MCDisassembler::Fail;
3947 // Decode a shifted immediate operand. These basically consist
3948 // of an 8-bit value, and a 4-bit directive that specifies either
3949 // a splat operation or a rotation.
3950 static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val,
3951 uint64_t Address, const void *Decoder) {
3952 unsigned ctrl = fieldFromInstruction(Val, 10, 2);
3954 unsigned byte = fieldFromInstruction(Val, 8, 2);
3955 unsigned imm = fieldFromInstruction(Val, 0, 8);
3958 Inst.addOperand(MCOperand::CreateImm(imm));
3961 Inst.addOperand(MCOperand::CreateImm((imm << 16) | imm));
3964 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 8)));
3967 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 16) |
3972 unsigned unrot = fieldFromInstruction(Val, 0, 7) | 0x80;
3973 unsigned rot = fieldFromInstruction(Val, 7, 5);
3974 unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31));
3975 Inst.addOperand(MCOperand::CreateImm(imm));
3978 return MCDisassembler::Success;
3982 DecodeThumbBCCTargetOperand(MCInst &Inst, unsigned Val,
3983 uint64_t Address, const void *Decoder){
3984 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<9>(Val<<1) + 4,
3985 true, 2, Inst, Decoder))
3986 Inst.addOperand(MCOperand::CreateImm(SignExtend32<9>(Val << 1)));
3987 return MCDisassembler::Success;
3990 static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val,
3991 uint64_t Address, const void *Decoder){
3992 // Val is passed in as S:J1:J2:imm10:imm11
3993 // Note no trailing zero after imm11. Also the J1 and J2 values are from
3994 // the encoded instruction. So here change to I1 and I2 values via:
3995 // I1 = NOT(J1 EOR S);
3996 // I2 = NOT(J2 EOR S);
3997 // and build the imm32 with one trailing zero as documented:
3998 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32);
3999 unsigned S = (Val >> 23) & 1;
4000 unsigned J1 = (Val >> 22) & 1;
4001 unsigned J2 = (Val >> 21) & 1;
4002 unsigned I1 = !(J1 ^ S);
4003 unsigned I2 = !(J2 ^ S);
4004 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21);
4005 int imm32 = SignExtend32<25>(tmp << 1);
4007 if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4,
4008 true, 4, Inst, Decoder))
4009 Inst.addOperand(MCOperand::CreateImm(imm32));
4010 return MCDisassembler::Success;
4013 static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Val,
4014 uint64_t Address, const void *Decoder) {
4016 return MCDisassembler::Fail;
4018 Inst.addOperand(MCOperand::CreateImm(Val));
4019 return MCDisassembler::Success;
4022 static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Val,
4023 uint64_t Address, const void *Decoder) {
4025 return MCDisassembler::Fail;
4027 Inst.addOperand(MCOperand::CreateImm(Val));
4028 return MCDisassembler::Success;
4031 static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Val,
4032 uint64_t Address, const void *Decoder) {
4033 DecodeStatus S = MCDisassembler::Success;
4034 const FeatureBitset &FeatureBits =
4035 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
4037 if (FeatureBits[ARM::FeatureMClass]) {
4038 unsigned ValLow = Val & 0xff;
4040 // Validate the SYSm value first.
4055 case 18: // basepri_max
4056 case 19: // faultmask
4057 if (!(FeatureBits[ARM::HasV7Ops]))
4058 // Values basepri, basepri_max and faultmask are only valid for v7m.
4059 return MCDisassembler::Fail;
4062 return MCDisassembler::Fail;
4065 if (Inst.getOpcode() == ARM::t2MSR_M) {
4066 unsigned Mask = fieldFromInstruction(Val, 10, 2);
4067 if (!(FeatureBits[ARM::HasV7Ops])) {
4068 // The ARMv6-M MSR bits {11-10} can be only 0b10, other values are
4071 S = MCDisassembler::SoftFail;
4074 // The ARMv7-M architecture stores an additional 2-bit mask value in
4075 // MSR bits {11-10}. The mask is used only with apsr, iapsr, eapsr and
4076 // xpsr, it has to be 0b10 in other cases. Bit mask{1} indicates if
4077 // the NZCVQ bits should be moved by the instruction. Bit mask{0}
4078 // indicates the move for the GE{3:0} bits, the mask{0} bit can be set
4079 // only if the processor includes the DSP extension.
4080 if (Mask == 0 || (Mask != 2 && ValLow > 3) ||
4081 (!(FeatureBits[ARM::FeatureDSPThumb2]) && (Mask & 1)))
4082 S = MCDisassembler::SoftFail;
4088 return MCDisassembler::Fail;
4090 Inst.addOperand(MCOperand::CreateImm(Val));
4094 static DecodeStatus DecodeBankedReg(MCInst &Inst, unsigned Val,
4095 uint64_t Address, const void *Decoder) {
4097 unsigned R = fieldFromInstruction(Val, 5, 1);
4098 unsigned SysM = fieldFromInstruction(Val, 0, 5);
4100 // The table of encodings for these banked registers comes from B9.2.3 of the
4101 // ARM ARM. There are patterns, but nothing regular enough to make this logic
4102 // neater. So by fiat, these values are UNPREDICTABLE:
4104 if (SysM == 0x7 || SysM == 0xf || SysM == 0x18 || SysM == 0x19 ||
4105 SysM == 0x1a || SysM == 0x1b)
4106 return MCDisassembler::SoftFail;
4108 if (SysM != 0xe && SysM != 0x10 && SysM != 0x12 && SysM != 0x14 &&
4109 SysM != 0x16 && SysM != 0x1c && SysM != 0x1e)
4110 return MCDisassembler::SoftFail;
4113 Inst.addOperand(MCOperand::CreateImm(Val));
4114 return MCDisassembler::Success;
4117 static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn,
4118 uint64_t Address, const void *Decoder) {
4119 DecodeStatus S = MCDisassembler::Success;
4121 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4122 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4123 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4126 S = MCDisassembler::SoftFail;
4128 if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder)))
4129 return MCDisassembler::Fail;
4130 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4131 return MCDisassembler::Fail;
4132 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4133 return MCDisassembler::Fail;
4138 static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn,
4139 uint64_t Address, const void *Decoder){
4140 DecodeStatus S = MCDisassembler::Success;
4142 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4143 unsigned Rt = fieldFromInstruction(Insn, 0, 4);
4144 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4145 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4147 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
4148 return MCDisassembler::Fail;
4150 if (Rn == 0xF || Rd == Rn || Rd == Rt || Rd == Rt+1)
4151 S = MCDisassembler::SoftFail;
4153 if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder)))
4154 return MCDisassembler::Fail;
4155 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4156 return MCDisassembler::Fail;
4157 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4158 return MCDisassembler::Fail;
4163 static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn,
4164 uint64_t Address, const void *Decoder) {
4165 DecodeStatus S = MCDisassembler::Success;
4167 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4168 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4169 unsigned imm = fieldFromInstruction(Insn, 0, 12);
4170 imm |= fieldFromInstruction(Insn, 16, 4) << 13;
4171 imm |= fieldFromInstruction(Insn, 23, 1) << 12;
4172 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4174 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
4176 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
4177 return MCDisassembler::Fail;
4178 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4179 return MCDisassembler::Fail;
4180 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
4181 return MCDisassembler::Fail;
4182 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4183 return MCDisassembler::Fail;
4188 static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn,
4189 uint64_t Address, const void *Decoder) {
4190 DecodeStatus S = MCDisassembler::Success;
4192 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4193 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4194 unsigned imm = fieldFromInstruction(Insn, 0, 12);
4195 imm |= fieldFromInstruction(Insn, 16, 4) << 13;
4196 imm |= fieldFromInstruction(Insn, 23, 1) << 12;
4197 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4198 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4200 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
4201 if (Rm == 0xF) S = MCDisassembler::SoftFail;
4203 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
4204 return MCDisassembler::Fail;
4205 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4206 return MCDisassembler::Fail;
4207 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
4208 return MCDisassembler::Fail;
4209 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4210 return MCDisassembler::Fail;
4216 static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn,
4217 uint64_t Address, const void *Decoder) {
4218 DecodeStatus S = MCDisassembler::Success;
4220 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4221 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4222 unsigned imm = fieldFromInstruction(Insn, 0, 12);
4223 imm |= fieldFromInstruction(Insn, 16, 4) << 13;
4224 imm |= fieldFromInstruction(Insn, 23, 1) << 12;
4225 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4227 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
4229 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4230 return MCDisassembler::Fail;
4231 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
4232 return MCDisassembler::Fail;
4233 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
4234 return MCDisassembler::Fail;
4235 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4236 return MCDisassembler::Fail;
4241 static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn,
4242 uint64_t Address, const void *Decoder) {
4243 DecodeStatus S = MCDisassembler::Success;
4245 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4246 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4247 unsigned imm = fieldFromInstruction(Insn, 0, 12);
4248 imm |= fieldFromInstruction(Insn, 16, 4) << 13;
4249 imm |= fieldFromInstruction(Insn, 23, 1) << 12;
4250 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4252 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
4254 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4255 return MCDisassembler::Fail;
4256 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
4257 return MCDisassembler::Fail;
4258 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
4259 return MCDisassembler::Fail;
4260 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4261 return MCDisassembler::Fail;
4266 static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn,
4267 uint64_t Address, const void *Decoder) {
4268 DecodeStatus S = MCDisassembler::Success;
4270 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4271 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4272 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4273 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4274 unsigned size = fieldFromInstruction(Insn, 10, 2);
4280 return MCDisassembler::Fail;
4282 if (fieldFromInstruction(Insn, 4, 1))
4283 return MCDisassembler::Fail; // UNDEFINED
4284 index = fieldFromInstruction(Insn, 5, 3);
4287 if (fieldFromInstruction(Insn, 5, 1))
4288 return MCDisassembler::Fail; // UNDEFINED
4289 index = fieldFromInstruction(Insn, 6, 2);
4290 if (fieldFromInstruction(Insn, 4, 1))
4294 if (fieldFromInstruction(Insn, 6, 1))
4295 return MCDisassembler::Fail; // UNDEFINED
4296 index = fieldFromInstruction(Insn, 7, 1);
4298 switch (fieldFromInstruction(Insn, 4, 2)) {
4304 return MCDisassembler::Fail;
4309 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4310 return MCDisassembler::Fail;
4311 if (Rm != 0xF) { // Writeback
4312 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4313 return MCDisassembler::Fail;
4315 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4316 return MCDisassembler::Fail;
4317 Inst.addOperand(MCOperand::CreateImm(align));
4320 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4321 return MCDisassembler::Fail;
4323 Inst.addOperand(MCOperand::CreateReg(0));
4326 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4327 return MCDisassembler::Fail;
4328 Inst.addOperand(MCOperand::CreateImm(index));
4333 static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn,
4334 uint64_t Address, const void *Decoder) {
4335 DecodeStatus S = MCDisassembler::Success;
4337 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4338 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4339 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4340 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4341 unsigned size = fieldFromInstruction(Insn, 10, 2);
4347 return MCDisassembler::Fail;
4349 if (fieldFromInstruction(Insn, 4, 1))
4350 return MCDisassembler::Fail; // UNDEFINED
4351 index = fieldFromInstruction(Insn, 5, 3);
4354 if (fieldFromInstruction(Insn, 5, 1))
4355 return MCDisassembler::Fail; // UNDEFINED
4356 index = fieldFromInstruction(Insn, 6, 2);
4357 if (fieldFromInstruction(Insn, 4, 1))
4361 if (fieldFromInstruction(Insn, 6, 1))
4362 return MCDisassembler::Fail; // UNDEFINED
4363 index = fieldFromInstruction(Insn, 7, 1);
4365 switch (fieldFromInstruction(Insn, 4, 2)) {
4371 return MCDisassembler::Fail;
4376 if (Rm != 0xF) { // Writeback
4377 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4378 return MCDisassembler::Fail;
4380 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4381 return MCDisassembler::Fail;
4382 Inst.addOperand(MCOperand::CreateImm(align));
4385 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4386 return MCDisassembler::Fail;
4388 Inst.addOperand(MCOperand::CreateReg(0));
4391 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4392 return MCDisassembler::Fail;
4393 Inst.addOperand(MCOperand::CreateImm(index));
4399 static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn,
4400 uint64_t Address, const void *Decoder) {
4401 DecodeStatus S = MCDisassembler::Success;
4403 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4404 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4405 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4406 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4407 unsigned size = fieldFromInstruction(Insn, 10, 2);
4414 return MCDisassembler::Fail;
4416 index = fieldFromInstruction(Insn, 5, 3);
4417 if (fieldFromInstruction(Insn, 4, 1))
4421 index = fieldFromInstruction(Insn, 6, 2);
4422 if (fieldFromInstruction(Insn, 4, 1))
4424 if (fieldFromInstruction(Insn, 5, 1))
4428 if (fieldFromInstruction(Insn, 5, 1))
4429 return MCDisassembler::Fail; // UNDEFINED
4430 index = fieldFromInstruction(Insn, 7, 1);
4431 if (fieldFromInstruction(Insn, 4, 1) != 0)
4433 if (fieldFromInstruction(Insn, 6, 1))
4438 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4439 return MCDisassembler::Fail;
4440 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4441 return MCDisassembler::Fail;
4442 if (Rm != 0xF) { // Writeback
4443 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4444 return MCDisassembler::Fail;
4446 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4447 return MCDisassembler::Fail;
4448 Inst.addOperand(MCOperand::CreateImm(align));
4451 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4452 return MCDisassembler::Fail;
4454 Inst.addOperand(MCOperand::CreateReg(0));
4457 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4458 return MCDisassembler::Fail;
4459 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4460 return MCDisassembler::Fail;
4461 Inst.addOperand(MCOperand::CreateImm(index));
4466 static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn,
4467 uint64_t Address, const void *Decoder) {
4468 DecodeStatus S = MCDisassembler::Success;
4470 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4471 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4472 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4473 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4474 unsigned size = fieldFromInstruction(Insn, 10, 2);
4481 return MCDisassembler::Fail;
4483 index = fieldFromInstruction(Insn, 5, 3);
4484 if (fieldFromInstruction(Insn, 4, 1))
4488 index = fieldFromInstruction(Insn, 6, 2);
4489 if (fieldFromInstruction(Insn, 4, 1))
4491 if (fieldFromInstruction(Insn, 5, 1))
4495 if (fieldFromInstruction(Insn, 5, 1))
4496 return MCDisassembler::Fail; // UNDEFINED
4497 index = fieldFromInstruction(Insn, 7, 1);
4498 if (fieldFromInstruction(Insn, 4, 1) != 0)
4500 if (fieldFromInstruction(Insn, 6, 1))
4505 if (Rm != 0xF) { // Writeback
4506 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4507 return MCDisassembler::Fail;
4509 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4510 return MCDisassembler::Fail;
4511 Inst.addOperand(MCOperand::CreateImm(align));
4514 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4515 return MCDisassembler::Fail;
4517 Inst.addOperand(MCOperand::CreateReg(0));
4520 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4521 return MCDisassembler::Fail;
4522 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4523 return MCDisassembler::Fail;
4524 Inst.addOperand(MCOperand::CreateImm(index));
4530 static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn,
4531 uint64_t Address, const void *Decoder) {
4532 DecodeStatus S = MCDisassembler::Success;
4534 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4535 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4536 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4537 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4538 unsigned size = fieldFromInstruction(Insn, 10, 2);
4545 return MCDisassembler::Fail;
4547 if (fieldFromInstruction(Insn, 4, 1))
4548 return MCDisassembler::Fail; // UNDEFINED
4549 index = fieldFromInstruction(Insn, 5, 3);
4552 if (fieldFromInstruction(Insn, 4, 1))
4553 return MCDisassembler::Fail; // UNDEFINED
4554 index = fieldFromInstruction(Insn, 6, 2);
4555 if (fieldFromInstruction(Insn, 5, 1))
4559 if (fieldFromInstruction(Insn, 4, 2))
4560 return MCDisassembler::Fail; // UNDEFINED
4561 index = fieldFromInstruction(Insn, 7, 1);
4562 if (fieldFromInstruction(Insn, 6, 1))
4567 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4568 return MCDisassembler::Fail;
4569 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4570 return MCDisassembler::Fail;
4571 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4572 return MCDisassembler::Fail;
4574 if (Rm != 0xF) { // Writeback
4575 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4576 return MCDisassembler::Fail;
4578 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4579 return MCDisassembler::Fail;
4580 Inst.addOperand(MCOperand::CreateImm(align));
4583 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4584 return MCDisassembler::Fail;
4586 Inst.addOperand(MCOperand::CreateReg(0));
4589 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4590 return MCDisassembler::Fail;
4591 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4592 return MCDisassembler::Fail;
4593 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4594 return MCDisassembler::Fail;
4595 Inst.addOperand(MCOperand::CreateImm(index));
4600 static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn,
4601 uint64_t Address, const void *Decoder) {
4602 DecodeStatus S = MCDisassembler::Success;
4604 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4605 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4606 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4607 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4608 unsigned size = fieldFromInstruction(Insn, 10, 2);
4615 return MCDisassembler::Fail;
4617 if (fieldFromInstruction(Insn, 4, 1))
4618 return MCDisassembler::Fail; // UNDEFINED
4619 index = fieldFromInstruction(Insn, 5, 3);
4622 if (fieldFromInstruction(Insn, 4, 1))
4623 return MCDisassembler::Fail; // UNDEFINED
4624 index = fieldFromInstruction(Insn, 6, 2);
4625 if (fieldFromInstruction(Insn, 5, 1))
4629 if (fieldFromInstruction(Insn, 4, 2))
4630 return MCDisassembler::Fail; // UNDEFINED
4631 index = fieldFromInstruction(Insn, 7, 1);
4632 if (fieldFromInstruction(Insn, 6, 1))
4637 if (Rm != 0xF) { // Writeback
4638 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4639 return MCDisassembler::Fail;
4641 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4642 return MCDisassembler::Fail;
4643 Inst.addOperand(MCOperand::CreateImm(align));
4646 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4647 return MCDisassembler::Fail;
4649 Inst.addOperand(MCOperand::CreateReg(0));
4652 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4653 return MCDisassembler::Fail;
4654 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4655 return MCDisassembler::Fail;
4656 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4657 return MCDisassembler::Fail;
4658 Inst.addOperand(MCOperand::CreateImm(index));
4664 static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn,
4665 uint64_t Address, const void *Decoder) {
4666 DecodeStatus S = MCDisassembler::Success;
4668 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4669 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4670 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4671 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4672 unsigned size = fieldFromInstruction(Insn, 10, 2);
4679 return MCDisassembler::Fail;
4681 if (fieldFromInstruction(Insn, 4, 1))
4683 index = fieldFromInstruction(Insn, 5, 3);
4686 if (fieldFromInstruction(Insn, 4, 1))
4688 index = fieldFromInstruction(Insn, 6, 2);
4689 if (fieldFromInstruction(Insn, 5, 1))
4693 switch (fieldFromInstruction(Insn, 4, 2)) {
4697 return MCDisassembler::Fail;
4699 align = 4 << fieldFromInstruction(Insn, 4, 2); break;
4702 index = fieldFromInstruction(Insn, 7, 1);
4703 if (fieldFromInstruction(Insn, 6, 1))
4708 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4709 return MCDisassembler::Fail;
4710 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4711 return MCDisassembler::Fail;
4712 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4713 return MCDisassembler::Fail;
4714 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
4715 return MCDisassembler::Fail;
4717 if (Rm != 0xF) { // Writeback
4718 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4719 return MCDisassembler::Fail;
4721 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4722 return MCDisassembler::Fail;
4723 Inst.addOperand(MCOperand::CreateImm(align));
4726 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4727 return MCDisassembler::Fail;
4729 Inst.addOperand(MCOperand::CreateReg(0));
4732 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4733 return MCDisassembler::Fail;
4734 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4735 return MCDisassembler::Fail;
4736 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4737 return MCDisassembler::Fail;
4738 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
4739 return MCDisassembler::Fail;
4740 Inst.addOperand(MCOperand::CreateImm(index));
4745 static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn,
4746 uint64_t Address, const void *Decoder) {
4747 DecodeStatus S = MCDisassembler::Success;
4749 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4750 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4751 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4752 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4753 unsigned size = fieldFromInstruction(Insn, 10, 2);
4760 return MCDisassembler::Fail;
4762 if (fieldFromInstruction(Insn, 4, 1))
4764 index = fieldFromInstruction(Insn, 5, 3);
4767 if (fieldFromInstruction(Insn, 4, 1))
4769 index = fieldFromInstruction(Insn, 6, 2);
4770 if (fieldFromInstruction(Insn, 5, 1))
4774 switch (fieldFromInstruction(Insn, 4, 2)) {
4778 return MCDisassembler::Fail;
4780 align = 4 << fieldFromInstruction(Insn, 4, 2); break;
4783 index = fieldFromInstruction(Insn, 7, 1);
4784 if (fieldFromInstruction(Insn, 6, 1))
4789 if (Rm != 0xF) { // Writeback
4790 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4791 return MCDisassembler::Fail;
4793 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4794 return MCDisassembler::Fail;
4795 Inst.addOperand(MCOperand::CreateImm(align));
4798 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4799 return MCDisassembler::Fail;
4801 Inst.addOperand(MCOperand::CreateReg(0));
4804 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4805 return MCDisassembler::Fail;
4806 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4807 return MCDisassembler::Fail;
4808 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4809 return MCDisassembler::Fail;
4810 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
4811 return MCDisassembler::Fail;
4812 Inst.addOperand(MCOperand::CreateImm(index));
4817 static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn,
4818 uint64_t Address, const void *Decoder) {
4819 DecodeStatus S = MCDisassembler::Success;
4820 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4821 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4);
4822 unsigned Rm = fieldFromInstruction(Insn, 5, 1);
4823 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4824 Rm |= fieldFromInstruction(Insn, 0, 4) << 1;
4826 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
4827 S = MCDisassembler::SoftFail;
4829 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)))
4830 return MCDisassembler::Fail;
4831 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
4832 return MCDisassembler::Fail;
4833 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder)))
4834 return MCDisassembler::Fail;
4835 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
4836 return MCDisassembler::Fail;
4837 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4838 return MCDisassembler::Fail;
4843 static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn,
4844 uint64_t Address, const void *Decoder) {
4845 DecodeStatus S = MCDisassembler::Success;
4846 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4847 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4);
4848 unsigned Rm = fieldFromInstruction(Insn, 5, 1);
4849 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4850 Rm |= fieldFromInstruction(Insn, 0, 4) << 1;
4852 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
4853 S = MCDisassembler::SoftFail;
4855 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder)))
4856 return MCDisassembler::Fail;
4857 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
4858 return MCDisassembler::Fail;
4859 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)))
4860 return MCDisassembler::Fail;
4861 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
4862 return MCDisassembler::Fail;
4863 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4864 return MCDisassembler::Fail;
4869 static DecodeStatus DecodeIT(MCInst &Inst, unsigned Insn,
4870 uint64_t Address, const void *Decoder) {
4871 DecodeStatus S = MCDisassembler::Success;
4872 unsigned pred = fieldFromInstruction(Insn, 4, 4);
4873 unsigned mask = fieldFromInstruction(Insn, 0, 4);
4877 S = MCDisassembler::SoftFail;
4881 return MCDisassembler::Fail;
4883 Inst.addOperand(MCOperand::CreateImm(pred));
4884 Inst.addOperand(MCOperand::CreateImm(mask));
4889 DecodeT2LDRDPreInstruction(MCInst &Inst, unsigned Insn,
4890 uint64_t Address, const void *Decoder) {
4891 DecodeStatus S = MCDisassembler::Success;
4893 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4894 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4);
4895 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4896 unsigned addr = fieldFromInstruction(Insn, 0, 8);
4897 unsigned W = fieldFromInstruction(Insn, 21, 1);
4898 unsigned U = fieldFromInstruction(Insn, 23, 1);
4899 unsigned P = fieldFromInstruction(Insn, 24, 1);
4900 bool writeback = (W == 1) | (P == 0);
4902 addr |= (U << 8) | (Rn << 9);
4904 if (writeback && (Rn == Rt || Rn == Rt2))
4905 Check(S, MCDisassembler::SoftFail);
4907 Check(S, MCDisassembler::SoftFail);
4910 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
4911 return MCDisassembler::Fail;
4913 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
4914 return MCDisassembler::Fail;
4915 // Writeback operand
4916 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
4917 return MCDisassembler::Fail;
4919 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
4920 return MCDisassembler::Fail;
4926 DecodeT2STRDPreInstruction(MCInst &Inst, unsigned Insn,
4927 uint64_t Address, const void *Decoder) {
4928 DecodeStatus S = MCDisassembler::Success;
4930 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4931 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4);
4932 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4933 unsigned addr = fieldFromInstruction(Insn, 0, 8);
4934 unsigned W = fieldFromInstruction(Insn, 21, 1);
4935 unsigned U = fieldFromInstruction(Insn, 23, 1);
4936 unsigned P = fieldFromInstruction(Insn, 24, 1);
4937 bool writeback = (W == 1) | (P == 0);
4939 addr |= (U << 8) | (Rn << 9);
4941 if (writeback && (Rn == Rt || Rn == Rt2))
4942 Check(S, MCDisassembler::SoftFail);
4944 // Writeback operand
4945 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
4946 return MCDisassembler::Fail;
4948 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
4949 return MCDisassembler::Fail;
4951 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
4952 return MCDisassembler::Fail;
4954 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
4955 return MCDisassembler::Fail;
4960 static DecodeStatus DecodeT2Adr(MCInst &Inst, uint32_t Insn,
4961 uint64_t Address, const void *Decoder) {
4962 unsigned sign1 = fieldFromInstruction(Insn, 21, 1);
4963 unsigned sign2 = fieldFromInstruction(Insn, 23, 1);
4964 if (sign1 != sign2) return MCDisassembler::Fail;
4966 unsigned Val = fieldFromInstruction(Insn, 0, 8);
4967 Val |= fieldFromInstruction(Insn, 12, 3) << 8;
4968 Val |= fieldFromInstruction(Insn, 26, 1) << 11;
4970 Inst.addOperand(MCOperand::CreateImm(SignExtend32<13>(Val)));
4972 return MCDisassembler::Success;
4975 static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, uint32_t Val,
4977 const void *Decoder) {
4978 DecodeStatus S = MCDisassembler::Success;
4980 // Shift of "asr #32" is not allowed in Thumb2 mode.
4981 if (Val == 0x20) S = MCDisassembler::Fail;
4982 Inst.addOperand(MCOperand::CreateImm(Val));
4986 static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn,
4987 uint64_t Address, const void *Decoder) {
4988 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4989 unsigned Rt2 = fieldFromInstruction(Insn, 0, 4);
4990 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4991 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4994 return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
4996 DecodeStatus S = MCDisassembler::Success;
4998 if (Rt == Rn || Rn == Rt2)
4999 S = MCDisassembler::SoftFail;
5001 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
5002 return MCDisassembler::Fail;
5003 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder)))
5004 return MCDisassembler::Fail;
5005 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
5006 return MCDisassembler::Fail;
5007 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
5008 return MCDisassembler::Fail;
5013 static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn,
5014 uint64_t Address, const void *Decoder) {
5015 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0);
5016 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4);
5017 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0);
5018 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4);
5019 unsigned imm = fieldFromInstruction(Insn, 16, 6);
5020 unsigned cmode = fieldFromInstruction(Insn, 8, 4);
5021 unsigned op = fieldFromInstruction(Insn, 5, 1);
5023 DecodeStatus S = MCDisassembler::Success;
5025 // VMOVv2f32 is ambiguous with these decodings.
5026 if (!(imm & 0x38) && cmode == 0xF) {
5027 if (op == 1) return MCDisassembler::Fail;
5028 Inst.setOpcode(ARM::VMOVv2f32);
5029 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder);
5032 if (!(imm & 0x20)) return MCDisassembler::Fail;
5034 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
5035 return MCDisassembler::Fail;
5036 if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder)))
5037 return MCDisassembler::Fail;
5038 Inst.addOperand(MCOperand::CreateImm(64 - imm));
5043 static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn,
5044 uint64_t Address, const void *Decoder) {
5045 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0);
5046 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4);
5047 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0);
5048 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4);
5049 unsigned imm = fieldFromInstruction(Insn, 16, 6);
5050 unsigned cmode = fieldFromInstruction(Insn, 8, 4);
5051 unsigned op = fieldFromInstruction(Insn, 5, 1);
5053 DecodeStatus S = MCDisassembler::Success;
5055 // VMOVv4f32 is ambiguous with these decodings.
5056 if (!(imm & 0x38) && cmode == 0xF) {
5057 if (op == 1) return MCDisassembler::Fail;
5058 Inst.setOpcode(ARM::VMOVv4f32);
5059 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder);
5062 if (!(imm & 0x20)) return MCDisassembler::Fail;
5064 if (!Check(S, DecodeQPRRegisterClass(Inst, Vd, Address, Decoder)))
5065 return MCDisassembler::Fail;
5066 if (!Check(S, DecodeQPRRegisterClass(Inst, Vm, Address, Decoder)))
5067 return MCDisassembler::Fail;
5068 Inst.addOperand(MCOperand::CreateImm(64 - imm));
5073 static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val,
5074 uint64_t Address, const void *Decoder) {
5075 DecodeStatus S = MCDisassembler::Success;
5077 unsigned Rn = fieldFromInstruction(Val, 16, 4);
5078 unsigned Rt = fieldFromInstruction(Val, 12, 4);
5079 unsigned Rm = fieldFromInstruction(Val, 0, 4);
5080 Rm |= (fieldFromInstruction(Val, 23, 1) << 4);
5081 unsigned Cond = fieldFromInstruction(Val, 28, 4);
5083 if (fieldFromInstruction(Val, 8, 4) != 0 || Rn == Rt)
5084 S = MCDisassembler::SoftFail;
5086 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
5087 return MCDisassembler::Fail;
5088 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
5089 return MCDisassembler::Fail;
5090 if (!Check(S, DecodeAddrMode7Operand(Inst, Rn, Address, Decoder)))
5091 return MCDisassembler::Fail;
5092 if (!Check(S, DecodePostIdxReg(Inst, Rm, Address, Decoder)))
5093 return MCDisassembler::Fail;
5094 if (!Check(S, DecodePredicateOperand(Inst, Cond, Address, Decoder)))
5095 return MCDisassembler::Fail;
5100 static DecodeStatus DecodeMRRC2(llvm::MCInst &Inst, unsigned Val,
5101 uint64_t Address, const void *Decoder) {
5103 DecodeStatus S = MCDisassembler::Success;
5105 unsigned CRm = fieldFromInstruction(Val, 0, 4);
5106 unsigned opc1 = fieldFromInstruction(Val, 4, 4);
5107 unsigned cop = fieldFromInstruction(Val, 8, 4);
5108 unsigned Rt = fieldFromInstruction(Val, 12, 4);
5109 unsigned Rt2 = fieldFromInstruction(Val, 16, 4);
5111 if ((cop & ~0x1) == 0xa)
5112 return MCDisassembler::Fail;
5115 S = MCDisassembler::SoftFail;
5117 Inst.addOperand(MCOperand::CreateImm(cop));
5118 Inst.addOperand(MCOperand::CreateImm(opc1));
5119 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
5120 return MCDisassembler::Fail;
5121 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder)))
5122 return MCDisassembler::Fail;
5123 Inst.addOperand(MCOperand::CreateImm(CRm));