1 //===-- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA --------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #define DEBUG_TYPE "arm-disassembler"
12 #include "MCTargetDesc/ARMAddressingModes.h"
13 #include "MCTargetDesc/ARMMCExpr.h"
14 #include "MCTargetDesc/ARMBaseInfo.h"
15 #include "llvm/MC/EDInstInfo.h"
16 #include "llvm/MC/MCInst.h"
17 #include "llvm/MC/MCInstrDesc.h"
18 #include "llvm/MC/MCExpr.h"
19 #include "llvm/MC/MCContext.h"
20 #include "llvm/MC/MCDisassembler.h"
21 #include "llvm/MC/MCSubtargetInfo.h"
22 #include "llvm/Support/Debug.h"
23 #include "llvm/Support/MemoryObject.h"
24 #include "llvm/Support/ErrorHandling.h"
25 #include "llvm/Support/TargetRegistry.h"
26 #include "llvm/Support/raw_ostream.h"
31 typedef MCDisassembler::DecodeStatus DecodeStatus;
34 // Handles the condition code status of instructions in IT blocks
38 // Returns the condition code for instruction in IT block
40 unsigned CC = ARMCC::AL;
46 // Advances the IT block state to the next T or E
47 void advanceITState() {
51 // Returns true if the current instruction is in an IT block
52 bool instrInITBlock() {
53 return !ITStates.empty();
56 // Returns true if current instruction is the last instruction in an IT block
57 bool instrLastInITBlock() {
58 return ITStates.size() == 1;
61 // Called when decoding an IT instruction. Sets the IT state for the following
62 // instructions that for the IT block. Firstcond and Mask correspond to the
63 // fields in the IT instruction encoding.
64 void setITState(char Firstcond, char Mask) {
65 // (3 - the number of trailing zeros) is the number of then / else.
66 unsigned CondBit0 = Firstcond & 1;
67 unsigned NumTZ = CountTrailingZeros_32(Mask);
68 unsigned char CCBits = static_cast<unsigned char>(Firstcond & 0xf);
69 assert(NumTZ <= 3 && "Invalid IT mask!");
70 // push condition codes onto the stack the correct order for the pops
71 for (unsigned Pos = NumTZ+1; Pos <= 3; ++Pos) {
72 bool T = ((Mask >> Pos) & 1) == CondBit0;
74 ITStates.push_back(CCBits);
76 ITStates.push_back(CCBits ^ 1);
78 ITStates.push_back(CCBits);
82 std::vector<unsigned char> ITStates;
87 /// ARMDisassembler - ARM disassembler for all ARM platforms.
88 class ARMDisassembler : public MCDisassembler {
90 /// Constructor - Initializes the disassembler.
92 ARMDisassembler(const MCSubtargetInfo &STI) :
99 /// getInstruction - See MCDisassembler.
100 DecodeStatus getInstruction(MCInst &instr,
102 const MemoryObject ®ion,
104 raw_ostream &vStream,
105 raw_ostream &cStream) const;
107 /// getEDInfo - See MCDisassembler.
108 const EDInstInfo *getEDInfo() const;
112 /// ThumbDisassembler - Thumb disassembler for all Thumb platforms.
113 class ThumbDisassembler : public MCDisassembler {
115 /// Constructor - Initializes the disassembler.
117 ThumbDisassembler(const MCSubtargetInfo &STI) :
118 MCDisassembler(STI) {
121 ~ThumbDisassembler() {
124 /// getInstruction - See MCDisassembler.
125 DecodeStatus getInstruction(MCInst &instr,
127 const MemoryObject ®ion,
129 raw_ostream &vStream,
130 raw_ostream &cStream) const;
132 /// getEDInfo - See MCDisassembler.
133 const EDInstInfo *getEDInfo() const;
135 mutable ITStatus ITBlock;
136 DecodeStatus AddThumbPredicate(MCInst&) const;
137 void UpdateThumbVFPPredicate(MCInst&) const;
141 static bool Check(DecodeStatus &Out, DecodeStatus In) {
143 case MCDisassembler::Success:
144 // Out stays the same.
146 case MCDisassembler::SoftFail:
149 case MCDisassembler::Fail:
153 llvm_unreachable("Invalid DecodeStatus!");
157 // Forward declare these because the autogenerated code will reference them.
158 // Definitions are further down.
159 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo,
160 uint64_t Address, const void *Decoder);
161 static DecodeStatus DecodeGPRnopcRegisterClass(MCInst &Inst,
162 unsigned RegNo, uint64_t Address,
163 const void *Decoder);
164 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo,
165 uint64_t Address, const void *Decoder);
166 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo,
167 uint64_t Address, const void *Decoder);
168 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo,
169 uint64_t Address, const void *Decoder);
170 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo,
171 uint64_t Address, const void *Decoder);
172 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo,
173 uint64_t Address, const void *Decoder);
174 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo,
175 uint64_t Address, const void *Decoder);
176 static DecodeStatus DecodeDPR_VFP2RegisterClass(MCInst &Inst,
179 const void *Decoder);
180 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo,
181 uint64_t Address, const void *Decoder);
182 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo,
183 uint64_t Address, const void *Decoder);
184 static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst,
185 unsigned RegNo, uint64_t Address,
186 const void *Decoder);
188 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val,
189 uint64_t Address, const void *Decoder);
190 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val,
191 uint64_t Address, const void *Decoder);
192 static DecodeStatus DecodeSOImmOperand(MCInst &Inst, unsigned Val,
193 uint64_t Address, const void *Decoder);
194 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val,
195 uint64_t Address, const void *Decoder);
196 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val,
197 uint64_t Address, const void *Decoder);
198 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val,
199 uint64_t Address, const void *Decoder);
201 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Insn,
202 uint64_t Address, const void *Decoder);
203 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn,
204 uint64_t Address, const void *Decoder);
205 static DecodeStatus DecodeAddrMode2IdxInstruction(MCInst &Inst,
208 const void *Decoder);
209 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Insn,
210 uint64_t Address, const void *Decoder);
211 static DecodeStatus DecodeAddrMode3Instruction(MCInst &Inst,unsigned Insn,
212 uint64_t Address, const void *Decoder);
213 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Insn,
214 uint64_t Address, const void *Decoder);
215 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Insn,
216 uint64_t Address, const void *Decoder);
218 static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst & Inst,
221 const void *Decoder);
222 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn,
223 uint64_t Address, const void *Decoder);
224 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn,
225 uint64_t Address, const void *Decoder);
226 static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn,
227 uint64_t Address, const void *Decoder);
228 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn,
229 uint64_t Address, const void *Decoder);
230 static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn,
231 uint64_t Address, const void *Decoder);
232 static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val,
233 uint64_t Address, const void *Decoder);
234 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val,
235 uint64_t Address, const void *Decoder);
236 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val,
237 uint64_t Address, const void *Decoder);
238 static DecodeStatus DecodeT2BInstruction(MCInst &Inst, unsigned Insn,
239 uint64_t Address, const void *Decoder);
240 static DecodeStatus DecodeBranchImmInstruction(MCInst &Inst,unsigned Insn,
241 uint64_t Address, const void *Decoder);
242 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val,
243 uint64_t Address, const void *Decoder);
244 static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Val,
245 uint64_t Address, const void *Decoder);
246 static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Val,
247 uint64_t Address, const void *Decoder);
248 static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Val,
249 uint64_t Address, const void *Decoder);
250 static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Val,
251 uint64_t Address, const void *Decoder);
252 static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Val,
253 uint64_t Address, const void *Decoder);
254 static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Val,
255 uint64_t Address, const void *Decoder);
256 static DecodeStatus DecodeNEONModImmInstruction(MCInst &Inst,unsigned Val,
257 uint64_t Address, const void *Decoder);
258 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Val,
259 uint64_t Address, const void *Decoder);
260 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val,
261 uint64_t Address, const void *Decoder);
262 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val,
263 uint64_t Address, const void *Decoder);
264 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val,
265 uint64_t Address, const void *Decoder);
266 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val,
267 uint64_t Address, const void *Decoder);
268 static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn,
269 uint64_t Address, const void *Decoder);
270 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn,
271 uint64_t Address, const void *Decoder);
272 static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Insn,
273 uint64_t Address, const void *Decoder);
274 static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Insn,
275 uint64_t Address, const void *Decoder);
276 static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Insn,
277 uint64_t Address, const void *Decoder);
278 static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn,
279 uint64_t Address, const void *Decoder);
280 static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn,
281 uint64_t Address, const void *Decoder);
282 static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn,
283 uint64_t Address, const void *Decoder);
284 static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn,
285 uint64_t Address, const void *Decoder);
286 static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn,
287 uint64_t Address, const void *Decoder);
288 static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn,
289 uint64_t Address, const void *Decoder);
290 static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn,
291 uint64_t Address, const void *Decoder);
292 static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn,
293 uint64_t Address, const void *Decoder);
294 static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn,
295 uint64_t Address, const void *Decoder);
296 static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn,
297 uint64_t Address, const void *Decoder);
298 static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn,
299 uint64_t Address, const void *Decoder);
300 static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn,
301 uint64_t Address, const void *Decoder);
302 static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn,
303 uint64_t Address, const void *Decoder);
304 static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn,
305 uint64_t Address, const void *Decoder);
306 static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn,
307 uint64_t Address, const void *Decoder);
308 static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn,
309 uint64_t Address, const void *Decoder);
310 static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn,
311 uint64_t Address, const void *Decoder);
312 static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn,
313 uint64_t Address, const void *Decoder);
314 static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn,
315 uint64_t Address, const void *Decoder);
318 static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn,
319 uint64_t Address, const void *Decoder);
320 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val,
321 uint64_t Address, const void *Decoder);
322 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val,
323 uint64_t Address, const void *Decoder);
324 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val,
325 uint64_t Address, const void *Decoder);
326 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val,
327 uint64_t Address, const void *Decoder);
328 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val,
329 uint64_t Address, const void *Decoder);
330 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val,
331 uint64_t Address, const void *Decoder);
332 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val,
333 uint64_t Address, const void *Decoder);
334 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val,
335 uint64_t Address, const void *Decoder);
336 static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Val,
337 uint64_t Address, const void *Decoder);
338 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val,
339 uint64_t Address, const void *Decoder);
340 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val,
341 uint64_t Address, const void *Decoder);
342 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val,
343 uint64_t Address, const void *Decoder);
344 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val,
345 uint64_t Address, const void *Decoder);
346 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val,
347 uint64_t Address, const void *Decoder);
348 static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Val,
349 uint64_t Address, const void *Decoder);
350 static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn,
351 uint64_t Address, const void *Decoder);
352 static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn,
353 uint64_t Address, const void *Decoder);
354 static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Insn,
355 uint64_t Address, const void *Decoder);
356 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val,
357 uint64_t Address, const void *Decoder);
358 static DecodeStatus DecodeThumbTableBranch(MCInst &Inst, unsigned Val,
359 uint64_t Address, const void *Decoder);
360 static DecodeStatus DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Val,
361 uint64_t Address, const void *Decoder);
362 static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val,
363 uint64_t Address, const void *Decoder);
364 static DecodeStatus DecodeThumbBCCTargetOperand(MCInst &Inst,unsigned Val,
365 uint64_t Address, const void *Decoder);
366 static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val,
367 uint64_t Address, const void *Decoder);
368 static DecodeStatus DecodeIT(MCInst &Inst, unsigned Val,
369 uint64_t Address, const void *Decoder);
370 static DecodeStatus DecodeT2LDRDPreInstruction(MCInst &Inst,unsigned Insn,
371 uint64_t Address, const void *Decoder);
372 static DecodeStatus DecodeT2STRDPreInstruction(MCInst &Inst,unsigned Insn,
373 uint64_t Address, const void *Decoder);
374 static DecodeStatus DecodeT2Adr(MCInst &Inst, unsigned Val,
375 uint64_t Address, const void *Decoder);
376 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Val,
377 uint64_t Address, const void *Decoder);
378 static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, unsigned Val,
379 uint64_t Address, const void *Decoder);
381 static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val,
382 uint64_t Address, const void *Decoder);
383 static DecodeStatus DecodeMRRC2(llvm::MCInst &Inst, unsigned Val,
384 uint64_t Address, const void *Decoder);
385 #include "ARMGenDisassemblerTables.inc"
386 #include "ARMGenInstrInfo.inc"
387 #include "ARMGenEDInfo.inc"
389 static MCDisassembler *createARMDisassembler(const Target &T, const MCSubtargetInfo &STI) {
390 return new ARMDisassembler(STI);
393 static MCDisassembler *createThumbDisassembler(const Target &T, const MCSubtargetInfo &STI) {
394 return new ThumbDisassembler(STI);
397 const EDInstInfo *ARMDisassembler::getEDInfo() const {
401 const EDInstInfo *ThumbDisassembler::getEDInfo() const {
405 DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
406 const MemoryObject &Region,
409 raw_ostream &cs) const {
414 assert(!(STI.getFeatureBits() & ARM::ModeThumb) &&
415 "Asked to disassemble an ARM instruction but Subtarget is in Thumb mode!");
417 // We want to read exactly 4 bytes of data.
418 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) {
420 return MCDisassembler::Fail;
423 // Encoded as a small-endian 32-bit word in the stream.
424 uint32_t insn = (bytes[3] << 24) |
429 // Calling the auto-generated decoder function.
430 DecodeStatus result = decodeARMInstruction32(MI, insn, Address, this, STI);
431 if (result != MCDisassembler::Fail) {
436 // VFP and NEON instructions, similarly, are shared between ARM
439 result = decodeVFPInstruction32(MI, insn, Address, this, STI);
440 if (result != MCDisassembler::Fail) {
446 result = decodeNEONDataInstruction32(MI, insn, Address, this, STI);
447 if (result != MCDisassembler::Fail) {
449 // Add a fake predicate operand, because we share these instruction
450 // definitions with Thumb2 where these instructions are predicable.
451 if (!DecodePredicateOperand(MI, 0xE, Address, this))
452 return MCDisassembler::Fail;
457 result = decodeNEONLoadStoreInstruction32(MI, insn, Address, this, STI);
458 if (result != MCDisassembler::Fail) {
460 // Add a fake predicate operand, because we share these instruction
461 // definitions with Thumb2 where these instructions are predicable.
462 if (!DecodePredicateOperand(MI, 0xE, Address, this))
463 return MCDisassembler::Fail;
468 result = decodeNEONDupInstruction32(MI, insn, Address, this, STI);
469 if (result != MCDisassembler::Fail) {
471 // Add a fake predicate operand, because we share these instruction
472 // definitions with Thumb2 where these instructions are predicable.
473 if (!DecodePredicateOperand(MI, 0xE, Address, this))
474 return MCDisassembler::Fail;
481 return MCDisassembler::Fail;
485 extern const MCInstrDesc ARMInsts[];
488 /// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the
489 /// immediate Value in the MCInst. The immediate Value has had any PC
490 /// adjustment made by the caller. If the instruction is a branch instruction
491 /// then isBranch is true, else false. If the getOpInfo() function was set as
492 /// part of the setupForSymbolicDisassembly() call then that function is called
493 /// to get any symbolic information at the Address for this instruction. If
494 /// that returns non-zero then the symbolic information it returns is used to
495 /// create an MCExpr and that is added as an operand to the MCInst. If
496 /// getOpInfo() returns zero and isBranch is true then a symbol look up for
497 /// Value is done and if a symbol is found an MCExpr is created with that, else
498 /// an MCExpr with Value is created. This function returns true if it adds an
499 /// operand to the MCInst and false otherwise.
500 static bool tryAddingSymbolicOperand(uint64_t Address, int32_t Value,
501 bool isBranch, uint64_t InstSize,
502 MCInst &MI, const void *Decoder) {
503 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
504 LLVMOpInfoCallback getOpInfo = Dis->getLLVMOpInfoCallback();
505 struct LLVMOpInfo1 SymbolicOp;
506 memset(&SymbolicOp, '\0', sizeof(struct LLVMOpInfo1));
507 SymbolicOp.Value = Value;
508 void *DisInfo = Dis->getDisInfoBlock();
511 !getOpInfo(DisInfo, Address, 0 /* Offset */, InstSize, 1, &SymbolicOp)) {
512 // Clear SymbolicOp.Value from above and also all other fields.
513 memset(&SymbolicOp, '\0', sizeof(struct LLVMOpInfo1));
514 LLVMSymbolLookupCallback SymbolLookUp = Dis->getLLVMSymbolLookupCallback();
517 uint64_t ReferenceType;
519 ReferenceType = LLVMDisassembler_ReferenceType_In_Branch;
521 ReferenceType = LLVMDisassembler_ReferenceType_InOut_None;
522 const char *ReferenceName;
523 const char *Name = SymbolLookUp(DisInfo, Value, &ReferenceType, Address,
526 SymbolicOp.AddSymbol.Name = Name;
527 SymbolicOp.AddSymbol.Present = true;
529 // For branches always create an MCExpr so it gets printed as hex address.
531 SymbolicOp.Value = Value;
533 if(ReferenceType == LLVMDisassembler_ReferenceType_Out_SymbolStub)
534 (*Dis->CommentStream) << "symbol stub for: " << ReferenceName;
535 if (!Name && !isBranch)
539 MCContext *Ctx = Dis->getMCContext();
540 const MCExpr *Add = NULL;
541 if (SymbolicOp.AddSymbol.Present) {
542 if (SymbolicOp.AddSymbol.Name) {
543 StringRef Name(SymbolicOp.AddSymbol.Name);
544 MCSymbol *Sym = Ctx->GetOrCreateSymbol(Name);
545 Add = MCSymbolRefExpr::Create(Sym, *Ctx);
547 Add = MCConstantExpr::Create(SymbolicOp.AddSymbol.Value, *Ctx);
551 const MCExpr *Sub = NULL;
552 if (SymbolicOp.SubtractSymbol.Present) {
553 if (SymbolicOp.SubtractSymbol.Name) {
554 StringRef Name(SymbolicOp.SubtractSymbol.Name);
555 MCSymbol *Sym = Ctx->GetOrCreateSymbol(Name);
556 Sub = MCSymbolRefExpr::Create(Sym, *Ctx);
558 Sub = MCConstantExpr::Create(SymbolicOp.SubtractSymbol.Value, *Ctx);
562 const MCExpr *Off = NULL;
563 if (SymbolicOp.Value != 0)
564 Off = MCConstantExpr::Create(SymbolicOp.Value, *Ctx);
570 LHS = MCBinaryExpr::CreateSub(Add, Sub, *Ctx);
572 LHS = MCUnaryExpr::CreateMinus(Sub, *Ctx);
574 Expr = MCBinaryExpr::CreateAdd(LHS, Off, *Ctx);
579 Expr = MCBinaryExpr::CreateAdd(Add, Off, *Ctx);
586 Expr = MCConstantExpr::Create(0, *Ctx);
589 if (SymbolicOp.VariantKind == LLVMDisassembler_VariantKind_ARM_HI16)
590 MI.addOperand(MCOperand::CreateExpr(ARMMCExpr::CreateUpper16(Expr, *Ctx)));
591 else if (SymbolicOp.VariantKind == LLVMDisassembler_VariantKind_ARM_LO16)
592 MI.addOperand(MCOperand::CreateExpr(ARMMCExpr::CreateLower16(Expr, *Ctx)));
593 else if (SymbolicOp.VariantKind == LLVMDisassembler_VariantKind_None)
594 MI.addOperand(MCOperand::CreateExpr(Expr));
596 llvm_unreachable("bad SymbolicOp.VariantKind");
601 /// tryAddingPcLoadReferenceComment - trys to add a comment as to what is being
602 /// referenced by a load instruction with the base register that is the Pc.
603 /// These can often be values in a literal pool near the Address of the
604 /// instruction. The Address of the instruction and its immediate Value are
605 /// used as a possible literal pool entry. The SymbolLookUp call back will
606 /// return the name of a symbol referenced by the the literal pool's entry if
607 /// the referenced address is that of a symbol. Or it will return a pointer to
608 /// a literal 'C' string if the referenced address of the literal pool's entry
609 /// is an address into a section with 'C' string literals.
610 static void tryAddingPcLoadReferenceComment(uint64_t Address, int Value,
611 const void *Decoder) {
612 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
613 LLVMSymbolLookupCallback SymbolLookUp = Dis->getLLVMSymbolLookupCallback();
615 void *DisInfo = Dis->getDisInfoBlock();
616 uint64_t ReferenceType;
617 ReferenceType = LLVMDisassembler_ReferenceType_In_PCrel_Load;
618 const char *ReferenceName;
619 (void)SymbolLookUp(DisInfo, Value, &ReferenceType, Address, &ReferenceName);
620 if(ReferenceType == LLVMDisassembler_ReferenceType_Out_LitPool_SymAddr ||
621 ReferenceType == LLVMDisassembler_ReferenceType_Out_LitPool_CstrAddr)
622 (*Dis->CommentStream) << "literal pool for: " << ReferenceName;
626 // Thumb1 instructions don't have explicit S bits. Rather, they
627 // implicitly set CPSR. Since it's not represented in the encoding, the
628 // auto-generated decoder won't inject the CPSR operand. We need to fix
629 // that as a post-pass.
630 static void AddThumb1SBit(MCInst &MI, bool InITBlock) {
631 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
632 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
633 MCInst::iterator I = MI.begin();
634 for (unsigned i = 0; i < NumOps; ++i, ++I) {
635 if (I == MI.end()) break;
636 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) {
637 if (i > 0 && OpInfo[i-1].isPredicate()) continue;
638 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR));
643 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR));
646 // Most Thumb instructions don't have explicit predicates in the
647 // encoding, but rather get their predicates from IT context. We need
648 // to fix up the predicate operands using this context information as a
650 MCDisassembler::DecodeStatus
651 ThumbDisassembler::AddThumbPredicate(MCInst &MI) const {
652 MCDisassembler::DecodeStatus S = Success;
654 // A few instructions actually have predicates encoded in them. Don't
655 // try to overwrite it if we're seeing one of those.
656 switch (MI.getOpcode()) {
667 // Some instructions (mostly conditional branches) are not
668 // allowed in IT blocks.
669 if (ITBlock.instrInITBlock())
678 // Some instructions (mostly unconditional branches) can
679 // only appears at the end of, or outside of, an IT.
680 if (ITBlock.instrInITBlock() && !ITBlock.instrLastInITBlock())
687 // If we're in an IT block, base the predicate on that. Otherwise,
688 // assume a predicate of AL.
690 CC = ITBlock.getITCC();
693 if (ITBlock.instrInITBlock())
694 ITBlock.advanceITState();
696 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
697 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
698 MCInst::iterator I = MI.begin();
699 for (unsigned i = 0; i < NumOps; ++i, ++I) {
700 if (I == MI.end()) break;
701 if (OpInfo[i].isPredicate()) {
702 I = MI.insert(I, MCOperand::CreateImm(CC));
705 MI.insert(I, MCOperand::CreateReg(0));
707 MI.insert(I, MCOperand::CreateReg(ARM::CPSR));
712 I = MI.insert(I, MCOperand::CreateImm(CC));
715 MI.insert(I, MCOperand::CreateReg(0));
717 MI.insert(I, MCOperand::CreateReg(ARM::CPSR));
722 // Thumb VFP instructions are a special case. Because we share their
723 // encodings between ARM and Thumb modes, and they are predicable in ARM
724 // mode, the auto-generated decoder will give them an (incorrect)
725 // predicate operand. We need to rewrite these operands based on the IT
726 // context as a post-pass.
727 void ThumbDisassembler::UpdateThumbVFPPredicate(MCInst &MI) const {
729 CC = ITBlock.getITCC();
730 if (ITBlock.instrInITBlock())
731 ITBlock.advanceITState();
733 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
734 MCInst::iterator I = MI.begin();
735 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
736 for (unsigned i = 0; i < NumOps; ++i, ++I) {
737 if (OpInfo[i].isPredicate() ) {
743 I->setReg(ARM::CPSR);
749 DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
750 const MemoryObject &Region,
753 raw_ostream &cs) const {
758 assert((STI.getFeatureBits() & ARM::ModeThumb) &&
759 "Asked to disassemble in Thumb mode but Subtarget is in ARM mode!");
761 // We want to read exactly 2 bytes of data.
762 if (Region.readBytes(Address, 2, (uint8_t*)bytes, NULL) == -1) {
764 return MCDisassembler::Fail;
767 uint16_t insn16 = (bytes[1] << 8) | bytes[0];
768 DecodeStatus result = decodeThumbInstruction16(MI, insn16, Address, this, STI);
769 if (result != MCDisassembler::Fail) {
771 Check(result, AddThumbPredicate(MI));
776 result = decodeThumbSBitInstruction16(MI, insn16, Address, this, STI);
779 bool InITBlock = ITBlock.instrInITBlock();
780 Check(result, AddThumbPredicate(MI));
781 AddThumb1SBit(MI, InITBlock);
786 result = decodeThumb2Instruction16(MI, insn16, Address, this, STI);
787 if (result != MCDisassembler::Fail) {
790 // Nested IT blocks are UNPREDICTABLE. Must be checked before we add
791 // the Thumb predicate.
792 if (MI.getOpcode() == ARM::t2IT && ITBlock.instrInITBlock())
793 result = MCDisassembler::SoftFail;
795 Check(result, AddThumbPredicate(MI));
797 // If we find an IT instruction, we need to parse its condition
798 // code and mask operands so that we can apply them correctly
799 // to the subsequent instructions.
800 if (MI.getOpcode() == ARM::t2IT) {
802 unsigned Firstcond = MI.getOperand(0).getImm();
803 unsigned Mask = MI.getOperand(1).getImm();
804 ITBlock.setITState(Firstcond, Mask);
810 // We want to read exactly 4 bytes of data.
811 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) {
813 return MCDisassembler::Fail;
816 uint32_t insn32 = (bytes[3] << 8) |
821 result = decodeThumbInstruction32(MI, insn32, Address, this, STI);
822 if (result != MCDisassembler::Fail) {
824 bool InITBlock = ITBlock.instrInITBlock();
825 Check(result, AddThumbPredicate(MI));
826 AddThumb1SBit(MI, InITBlock);
831 result = decodeThumb2Instruction32(MI, insn32, Address, this, STI);
832 if (result != MCDisassembler::Fail) {
834 Check(result, AddThumbPredicate(MI));
839 result = decodeVFPInstruction32(MI, insn32, Address, this, STI);
840 if (result != MCDisassembler::Fail) {
842 UpdateThumbVFPPredicate(MI);
847 result = decodeNEONDupInstruction32(MI, insn32, Address, this, STI);
848 if (result != MCDisassembler::Fail) {
850 Check(result, AddThumbPredicate(MI));
854 if (fieldFromInstruction32(insn32, 24, 8) == 0xF9) {
856 uint32_t NEONLdStInsn = insn32;
857 NEONLdStInsn &= 0xF0FFFFFF;
858 NEONLdStInsn |= 0x04000000;
859 result = decodeNEONLoadStoreInstruction32(MI, NEONLdStInsn, Address, this, STI);
860 if (result != MCDisassembler::Fail) {
862 Check(result, AddThumbPredicate(MI));
867 if (fieldFromInstruction32(insn32, 24, 4) == 0xF) {
869 uint32_t NEONDataInsn = insn32;
870 NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24
871 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24
872 NEONDataInsn |= 0x12000000; // Set bits 28 and 25
873 result = decodeNEONDataInstruction32(MI, NEONDataInsn, Address, this, STI);
874 if (result != MCDisassembler::Fail) {
876 Check(result, AddThumbPredicate(MI));
882 return MCDisassembler::Fail;
886 extern "C" void LLVMInitializeARMDisassembler() {
887 TargetRegistry::RegisterMCDisassembler(TheARMTarget,
888 createARMDisassembler);
889 TargetRegistry::RegisterMCDisassembler(TheThumbTarget,
890 createThumbDisassembler);
893 static const uint16_t GPRDecoderTable[] = {
894 ARM::R0, ARM::R1, ARM::R2, ARM::R3,
895 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
896 ARM::R8, ARM::R9, ARM::R10, ARM::R11,
897 ARM::R12, ARM::SP, ARM::LR, ARM::PC
900 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo,
901 uint64_t Address, const void *Decoder) {
903 return MCDisassembler::Fail;
905 unsigned Register = GPRDecoderTable[RegNo];
906 Inst.addOperand(MCOperand::CreateReg(Register));
907 return MCDisassembler::Success;
911 DecodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo,
912 uint64_t Address, const void *Decoder) {
913 DecodeStatus S = MCDisassembler::Success;
916 S = MCDisassembler::SoftFail;
918 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
923 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo,
924 uint64_t Address, const void *Decoder) {
926 return MCDisassembler::Fail;
927 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
930 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo,
931 uint64_t Address, const void *Decoder) {
932 unsigned Register = 0;
953 return MCDisassembler::Fail;
956 Inst.addOperand(MCOperand::CreateReg(Register));
957 return MCDisassembler::Success;
960 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo,
961 uint64_t Address, const void *Decoder) {
962 if (RegNo == 13 || RegNo == 15) return MCDisassembler::Fail;
963 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
966 static const uint16_t SPRDecoderTable[] = {
967 ARM::S0, ARM::S1, ARM::S2, ARM::S3,
968 ARM::S4, ARM::S5, ARM::S6, ARM::S7,
969 ARM::S8, ARM::S9, ARM::S10, ARM::S11,
970 ARM::S12, ARM::S13, ARM::S14, ARM::S15,
971 ARM::S16, ARM::S17, ARM::S18, ARM::S19,
972 ARM::S20, ARM::S21, ARM::S22, ARM::S23,
973 ARM::S24, ARM::S25, ARM::S26, ARM::S27,
974 ARM::S28, ARM::S29, ARM::S30, ARM::S31
977 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo,
978 uint64_t Address, const void *Decoder) {
980 return MCDisassembler::Fail;
982 unsigned Register = SPRDecoderTable[RegNo];
983 Inst.addOperand(MCOperand::CreateReg(Register));
984 return MCDisassembler::Success;
987 static const uint16_t DPRDecoderTable[] = {
988 ARM::D0, ARM::D1, ARM::D2, ARM::D3,
989 ARM::D4, ARM::D5, ARM::D6, ARM::D7,
990 ARM::D8, ARM::D9, ARM::D10, ARM::D11,
991 ARM::D12, ARM::D13, ARM::D14, ARM::D15,
992 ARM::D16, ARM::D17, ARM::D18, ARM::D19,
993 ARM::D20, ARM::D21, ARM::D22, ARM::D23,
994 ARM::D24, ARM::D25, ARM::D26, ARM::D27,
995 ARM::D28, ARM::D29, ARM::D30, ARM::D31
998 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo,
999 uint64_t Address, const void *Decoder) {
1001 return MCDisassembler::Fail;
1003 unsigned Register = DPRDecoderTable[RegNo];
1004 Inst.addOperand(MCOperand::CreateReg(Register));
1005 return MCDisassembler::Success;
1008 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo,
1009 uint64_t Address, const void *Decoder) {
1011 return MCDisassembler::Fail;
1012 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
1016 DecodeDPR_VFP2RegisterClass(MCInst &Inst, unsigned RegNo,
1017 uint64_t Address, const void *Decoder) {
1019 return MCDisassembler::Fail;
1020 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
1023 static const uint16_t QPRDecoderTable[] = {
1024 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3,
1025 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7,
1026 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11,
1027 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15
1031 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo,
1032 uint64_t Address, const void *Decoder) {
1034 return MCDisassembler::Fail;
1037 unsigned Register = QPRDecoderTable[RegNo];
1038 Inst.addOperand(MCOperand::CreateReg(Register));
1039 return MCDisassembler::Success;
1042 static const uint16_t DPairDecoderTable[] = {
1043 ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6,
1044 ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12,
1045 ARM::Q6, ARM::D13_D14, ARM::Q7, ARM::D15_D16, ARM::Q8, ARM::D17_D18,
1046 ARM::Q9, ARM::D19_D20, ARM::Q10, ARM::D21_D22, ARM::Q11, ARM::D23_D24,
1047 ARM::Q12, ARM::D25_D26, ARM::Q13, ARM::D27_D28, ARM::Q14, ARM::D29_D30,
1051 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo,
1052 uint64_t Address, const void *Decoder) {
1054 return MCDisassembler::Fail;
1056 unsigned Register = DPairDecoderTable[RegNo];
1057 Inst.addOperand(MCOperand::CreateReg(Register));
1058 return MCDisassembler::Success;
1061 static const uint16_t DPairSpacedDecoderTable[] = {
1062 ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5,
1063 ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9,
1064 ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13,
1065 ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17,
1066 ARM::D16_D18, ARM::D17_D19, ARM::D18_D20, ARM::D19_D21,
1067 ARM::D20_D22, ARM::D21_D23, ARM::D22_D24, ARM::D23_D25,
1068 ARM::D24_D26, ARM::D25_D27, ARM::D26_D28, ARM::D27_D29,
1069 ARM::D28_D30, ARM::D29_D31
1072 static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst,
1075 const void *Decoder) {
1077 return MCDisassembler::Fail;
1079 unsigned Register = DPairSpacedDecoderTable[RegNo];
1080 Inst.addOperand(MCOperand::CreateReg(Register));
1081 return MCDisassembler::Success;
1084 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val,
1085 uint64_t Address, const void *Decoder) {
1086 if (Val == 0xF) return MCDisassembler::Fail;
1087 // AL predicate is not allowed on Thumb1 branches.
1088 if (Inst.getOpcode() == ARM::tBcc && Val == 0xE)
1089 return MCDisassembler::Fail;
1090 Inst.addOperand(MCOperand::CreateImm(Val));
1091 if (Val == ARMCC::AL) {
1092 Inst.addOperand(MCOperand::CreateReg(0));
1094 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1095 return MCDisassembler::Success;
1098 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val,
1099 uint64_t Address, const void *Decoder) {
1101 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1103 Inst.addOperand(MCOperand::CreateReg(0));
1104 return MCDisassembler::Success;
1107 static DecodeStatus DecodeSOImmOperand(MCInst &Inst, unsigned Val,
1108 uint64_t Address, const void *Decoder) {
1109 uint32_t imm = Val & 0xFF;
1110 uint32_t rot = (Val & 0xF00) >> 7;
1111 uint32_t rot_imm = (imm >> rot) | (imm << ((32-rot) & 0x1F));
1112 Inst.addOperand(MCOperand::CreateImm(rot_imm));
1113 return MCDisassembler::Success;
1116 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Val,
1117 uint64_t Address, const void *Decoder) {
1118 DecodeStatus S = MCDisassembler::Success;
1120 unsigned Rm = fieldFromInstruction32(Val, 0, 4);
1121 unsigned type = fieldFromInstruction32(Val, 5, 2);
1122 unsigned imm = fieldFromInstruction32(Val, 7, 5);
1124 // Register-immediate
1125 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1126 return MCDisassembler::Fail;
1128 ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
1131 Shift = ARM_AM::lsl;
1134 Shift = ARM_AM::lsr;
1137 Shift = ARM_AM::asr;
1140 Shift = ARM_AM::ror;
1144 if (Shift == ARM_AM::ror && imm == 0)
1145 Shift = ARM_AM::rrx;
1147 unsigned Op = Shift | (imm << 3);
1148 Inst.addOperand(MCOperand::CreateImm(Op));
1153 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Val,
1154 uint64_t Address, const void *Decoder) {
1155 DecodeStatus S = MCDisassembler::Success;
1157 unsigned Rm = fieldFromInstruction32(Val, 0, 4);
1158 unsigned type = fieldFromInstruction32(Val, 5, 2);
1159 unsigned Rs = fieldFromInstruction32(Val, 8, 4);
1161 // Register-register
1162 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1163 return MCDisassembler::Fail;
1164 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder)))
1165 return MCDisassembler::Fail;
1167 ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
1170 Shift = ARM_AM::lsl;
1173 Shift = ARM_AM::lsr;
1176 Shift = ARM_AM::asr;
1179 Shift = ARM_AM::ror;
1183 Inst.addOperand(MCOperand::CreateImm(Shift));
1188 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val,
1189 uint64_t Address, const void *Decoder) {
1190 DecodeStatus S = MCDisassembler::Success;
1192 bool writebackLoad = false;
1193 unsigned writebackReg = 0;
1194 switch (Inst.getOpcode()) {
1197 case ARM::LDMIA_UPD:
1198 case ARM::LDMDB_UPD:
1199 case ARM::LDMIB_UPD:
1200 case ARM::LDMDA_UPD:
1201 case ARM::t2LDMIA_UPD:
1202 case ARM::t2LDMDB_UPD:
1203 writebackLoad = true;
1204 writebackReg = Inst.getOperand(0).getReg();
1208 // Empty register lists are not allowed.
1209 if (CountPopulation_32(Val) == 0) return MCDisassembler::Fail;
1210 for (unsigned i = 0; i < 16; ++i) {
1211 if (Val & (1 << i)) {
1212 if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder)))
1213 return MCDisassembler::Fail;
1214 // Writeback not allowed if Rn is in the target list.
1215 if (writebackLoad && writebackReg == Inst.end()[-1].getReg())
1216 Check(S, MCDisassembler::SoftFail);
1223 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val,
1224 uint64_t Address, const void *Decoder) {
1225 DecodeStatus S = MCDisassembler::Success;
1227 unsigned Vd = fieldFromInstruction32(Val, 8, 4);
1228 unsigned regs = Val & 0xFF;
1230 if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder)))
1231 return MCDisassembler::Fail;
1232 for (unsigned i = 0; i < (regs - 1); ++i) {
1233 if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder)))
1234 return MCDisassembler::Fail;
1240 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val,
1241 uint64_t Address, const void *Decoder) {
1242 DecodeStatus S = MCDisassembler::Success;
1244 unsigned Vd = fieldFromInstruction32(Val, 8, 4);
1245 unsigned regs = (Val & 0xFF) / 2;
1247 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
1248 return MCDisassembler::Fail;
1249 for (unsigned i = 0; i < (regs - 1); ++i) {
1250 if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder)))
1251 return MCDisassembler::Fail;
1257 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Val,
1258 uint64_t Address, const void *Decoder) {
1259 // This operand encodes a mask of contiguous zeros between a specified MSB
1260 // and LSB. To decode it, we create the mask of all bits MSB-and-lower,
1261 // the mask of all bits LSB-and-lower, and then xor them to create
1262 // the mask of that's all ones on [msb, lsb]. Finally we not it to
1263 // create the final mask.
1264 unsigned msb = fieldFromInstruction32(Val, 5, 5);
1265 unsigned lsb = fieldFromInstruction32(Val, 0, 5);
1267 DecodeStatus S = MCDisassembler::Success;
1268 if (lsb > msb) Check(S, MCDisassembler::SoftFail);
1270 uint32_t msb_mask = 0xFFFFFFFF;
1271 if (msb != 31) msb_mask = (1U << (msb+1)) - 1;
1272 uint32_t lsb_mask = (1U << lsb) - 1;
1274 Inst.addOperand(MCOperand::CreateImm(~(msb_mask ^ lsb_mask)));
1278 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn,
1279 uint64_t Address, const void *Decoder) {
1280 DecodeStatus S = MCDisassembler::Success;
1282 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1283 unsigned CRd = fieldFromInstruction32(Insn, 12, 4);
1284 unsigned coproc = fieldFromInstruction32(Insn, 8, 4);
1285 unsigned imm = fieldFromInstruction32(Insn, 0, 8);
1286 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1287 unsigned U = fieldFromInstruction32(Insn, 23, 1);
1289 switch (Inst.getOpcode()) {
1290 case ARM::LDC_OFFSET:
1293 case ARM::LDC_OPTION:
1294 case ARM::LDCL_OFFSET:
1296 case ARM::LDCL_POST:
1297 case ARM::LDCL_OPTION:
1298 case ARM::STC_OFFSET:
1301 case ARM::STC_OPTION:
1302 case ARM::STCL_OFFSET:
1304 case ARM::STCL_POST:
1305 case ARM::STCL_OPTION:
1306 case ARM::t2LDC_OFFSET:
1307 case ARM::t2LDC_PRE:
1308 case ARM::t2LDC_POST:
1309 case ARM::t2LDC_OPTION:
1310 case ARM::t2LDCL_OFFSET:
1311 case ARM::t2LDCL_PRE:
1312 case ARM::t2LDCL_POST:
1313 case ARM::t2LDCL_OPTION:
1314 case ARM::t2STC_OFFSET:
1315 case ARM::t2STC_PRE:
1316 case ARM::t2STC_POST:
1317 case ARM::t2STC_OPTION:
1318 case ARM::t2STCL_OFFSET:
1319 case ARM::t2STCL_PRE:
1320 case ARM::t2STCL_POST:
1321 case ARM::t2STCL_OPTION:
1322 if (coproc == 0xA || coproc == 0xB)
1323 return MCDisassembler::Fail;
1329 Inst.addOperand(MCOperand::CreateImm(coproc));
1330 Inst.addOperand(MCOperand::CreateImm(CRd));
1331 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1332 return MCDisassembler::Fail;
1334 switch (Inst.getOpcode()) {
1335 case ARM::t2LDC2_OFFSET:
1336 case ARM::t2LDC2L_OFFSET:
1337 case ARM::t2LDC2_PRE:
1338 case ARM::t2LDC2L_PRE:
1339 case ARM::t2STC2_OFFSET:
1340 case ARM::t2STC2L_OFFSET:
1341 case ARM::t2STC2_PRE:
1342 case ARM::t2STC2L_PRE:
1343 case ARM::LDC2_OFFSET:
1344 case ARM::LDC2L_OFFSET:
1346 case ARM::LDC2L_PRE:
1347 case ARM::STC2_OFFSET:
1348 case ARM::STC2L_OFFSET:
1350 case ARM::STC2L_PRE:
1351 case ARM::t2LDC_OFFSET:
1352 case ARM::t2LDCL_OFFSET:
1353 case ARM::t2LDC_PRE:
1354 case ARM::t2LDCL_PRE:
1355 case ARM::t2STC_OFFSET:
1356 case ARM::t2STCL_OFFSET:
1357 case ARM::t2STC_PRE:
1358 case ARM::t2STCL_PRE:
1359 case ARM::LDC_OFFSET:
1360 case ARM::LDCL_OFFSET:
1363 case ARM::STC_OFFSET:
1364 case ARM::STCL_OFFSET:
1367 imm = ARM_AM::getAM5Opc(U ? ARM_AM::add : ARM_AM::sub, imm);
1368 Inst.addOperand(MCOperand::CreateImm(imm));
1370 case ARM::t2LDC2_POST:
1371 case ARM::t2LDC2L_POST:
1372 case ARM::t2STC2_POST:
1373 case ARM::t2STC2L_POST:
1374 case ARM::LDC2_POST:
1375 case ARM::LDC2L_POST:
1376 case ARM::STC2_POST:
1377 case ARM::STC2L_POST:
1378 case ARM::t2LDC_POST:
1379 case ARM::t2LDCL_POST:
1380 case ARM::t2STC_POST:
1381 case ARM::t2STCL_POST:
1383 case ARM::LDCL_POST:
1385 case ARM::STCL_POST:
1389 // The 'option' variant doesn't encode 'U' in the immediate since
1390 // the immediate is unsigned [0,255].
1391 Inst.addOperand(MCOperand::CreateImm(imm));
1395 switch (Inst.getOpcode()) {
1396 case ARM::LDC_OFFSET:
1399 case ARM::LDC_OPTION:
1400 case ARM::LDCL_OFFSET:
1402 case ARM::LDCL_POST:
1403 case ARM::LDCL_OPTION:
1404 case ARM::STC_OFFSET:
1407 case ARM::STC_OPTION:
1408 case ARM::STCL_OFFSET:
1410 case ARM::STCL_POST:
1411 case ARM::STCL_OPTION:
1412 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1413 return MCDisassembler::Fail;
1423 DecodeAddrMode2IdxInstruction(MCInst &Inst, unsigned Insn,
1424 uint64_t Address, const void *Decoder) {
1425 DecodeStatus S = MCDisassembler::Success;
1427 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1428 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
1429 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
1430 unsigned imm = fieldFromInstruction32(Insn, 0, 12);
1431 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1432 unsigned reg = fieldFromInstruction32(Insn, 25, 1);
1433 unsigned P = fieldFromInstruction32(Insn, 24, 1);
1434 unsigned W = fieldFromInstruction32(Insn, 21, 1);
1436 // On stores, the writeback operand precedes Rt.
1437 switch (Inst.getOpcode()) {
1438 case ARM::STR_POST_IMM:
1439 case ARM::STR_POST_REG:
1440 case ARM::STRB_POST_IMM:
1441 case ARM::STRB_POST_REG:
1442 case ARM::STRT_POST_REG:
1443 case ARM::STRT_POST_IMM:
1444 case ARM::STRBT_POST_REG:
1445 case ARM::STRBT_POST_IMM:
1446 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1447 return MCDisassembler::Fail;
1453 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
1454 return MCDisassembler::Fail;
1456 // On loads, the writeback operand comes after Rt.
1457 switch (Inst.getOpcode()) {
1458 case ARM::LDR_POST_IMM:
1459 case ARM::LDR_POST_REG:
1460 case ARM::LDRB_POST_IMM:
1461 case ARM::LDRB_POST_REG:
1462 case ARM::LDRBT_POST_REG:
1463 case ARM::LDRBT_POST_IMM:
1464 case ARM::LDRT_POST_REG:
1465 case ARM::LDRT_POST_IMM:
1466 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1467 return MCDisassembler::Fail;
1473 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1474 return MCDisassembler::Fail;
1476 ARM_AM::AddrOpc Op = ARM_AM::add;
1477 if (!fieldFromInstruction32(Insn, 23, 1))
1480 bool writeback = (P == 0) || (W == 1);
1481 unsigned idx_mode = 0;
1483 idx_mode = ARMII::IndexModePre;
1484 else if (!P && writeback)
1485 idx_mode = ARMII::IndexModePost;
1487 if (writeback && (Rn == 15 || Rn == Rt))
1488 S = MCDisassembler::SoftFail; // UNPREDICTABLE
1491 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1492 return MCDisassembler::Fail;
1493 ARM_AM::ShiftOpc Opc = ARM_AM::lsl;
1494 switch( fieldFromInstruction32(Insn, 5, 2)) {
1508 return MCDisassembler::Fail;
1510 unsigned amt = fieldFromInstruction32(Insn, 7, 5);
1511 unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode);
1513 Inst.addOperand(MCOperand::CreateImm(imm));
1515 Inst.addOperand(MCOperand::CreateReg(0));
1516 unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode);
1517 Inst.addOperand(MCOperand::CreateImm(tmp));
1520 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1521 return MCDisassembler::Fail;
1526 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Val,
1527 uint64_t Address, const void *Decoder) {
1528 DecodeStatus S = MCDisassembler::Success;
1530 unsigned Rn = fieldFromInstruction32(Val, 13, 4);
1531 unsigned Rm = fieldFromInstruction32(Val, 0, 4);
1532 unsigned type = fieldFromInstruction32(Val, 5, 2);
1533 unsigned imm = fieldFromInstruction32(Val, 7, 5);
1534 unsigned U = fieldFromInstruction32(Val, 12, 1);
1536 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl;
1552 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1553 return MCDisassembler::Fail;
1554 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1555 return MCDisassembler::Fail;
1558 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp);
1560 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp);
1561 Inst.addOperand(MCOperand::CreateImm(shift));
1567 DecodeAddrMode3Instruction(MCInst &Inst, unsigned Insn,
1568 uint64_t Address, const void *Decoder) {
1569 DecodeStatus S = MCDisassembler::Success;
1571 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
1572 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1573 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
1574 unsigned type = fieldFromInstruction32(Insn, 22, 1);
1575 unsigned imm = fieldFromInstruction32(Insn, 8, 4);
1576 unsigned U = ((~fieldFromInstruction32(Insn, 23, 1)) & 1) << 8;
1577 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1578 unsigned W = fieldFromInstruction32(Insn, 21, 1);
1579 unsigned P = fieldFromInstruction32(Insn, 24, 1);
1580 unsigned Rt2 = Rt + 1;
1582 bool writeback = (W == 1) | (P == 0);
1584 // For {LD,ST}RD, Rt must be even, else undefined.
1585 switch (Inst.getOpcode()) {
1588 case ARM::STRD_POST:
1591 case ARM::LDRD_POST:
1592 if (Rt & 0x1) S = MCDisassembler::SoftFail;
1597 switch (Inst.getOpcode()) {
1600 case ARM::STRD_POST:
1601 if (P == 0 && W == 1)
1602 S = MCDisassembler::SoftFail;
1604 if (writeback && (Rn == 15 || Rn == Rt || Rn == Rt2))
1605 S = MCDisassembler::SoftFail;
1606 if (type && Rm == 15)
1607 S = MCDisassembler::SoftFail;
1609 S = MCDisassembler::SoftFail;
1610 if (!type && fieldFromInstruction32(Insn, 8, 4))
1611 S = MCDisassembler::SoftFail;
1615 case ARM::STRH_POST:
1617 S = MCDisassembler::SoftFail;
1618 if (writeback && (Rn == 15 || Rn == Rt))
1619 S = MCDisassembler::SoftFail;
1620 if (!type && Rm == 15)
1621 S = MCDisassembler::SoftFail;
1625 case ARM::LDRD_POST:
1626 if (type && Rn == 15){
1628 S = MCDisassembler::SoftFail;
1631 if (P == 0 && W == 1)
1632 S = MCDisassembler::SoftFail;
1633 if (!type && (Rt2 == 15 || Rm == 15 || Rm == Rt || Rm == Rt2))
1634 S = MCDisassembler::SoftFail;
1635 if (!type && writeback && Rn == 15)
1636 S = MCDisassembler::SoftFail;
1637 if (writeback && (Rn == Rt || Rn == Rt2))
1638 S = MCDisassembler::SoftFail;
1642 case ARM::LDRH_POST:
1643 if (type && Rn == 15){
1645 S = MCDisassembler::SoftFail;
1649 S = MCDisassembler::SoftFail;
1650 if (!type && Rm == 15)
1651 S = MCDisassembler::SoftFail;
1652 if (!type && writeback && (Rn == 15 || Rn == Rt))
1653 S = MCDisassembler::SoftFail;
1656 case ARM::LDRSH_PRE:
1657 case ARM::LDRSH_POST:
1659 case ARM::LDRSB_PRE:
1660 case ARM::LDRSB_POST:
1661 if (type && Rn == 15){
1663 S = MCDisassembler::SoftFail;
1666 if (type && (Rt == 15 || (writeback && Rn == Rt)))
1667 S = MCDisassembler::SoftFail;
1668 if (!type && (Rt == 15 || Rm == 15))
1669 S = MCDisassembler::SoftFail;
1670 if (!type && writeback && (Rn == 15 || Rn == Rt))
1671 S = MCDisassembler::SoftFail;
1677 if (writeback) { // Writeback
1679 U |= ARMII::IndexModePre << 9;
1681 U |= ARMII::IndexModePost << 9;
1683 // On stores, the writeback operand precedes Rt.
1684 switch (Inst.getOpcode()) {
1687 case ARM::STRD_POST:
1690 case ARM::STRH_POST:
1691 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1692 return MCDisassembler::Fail;
1699 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
1700 return MCDisassembler::Fail;
1701 switch (Inst.getOpcode()) {
1704 case ARM::STRD_POST:
1707 case ARM::LDRD_POST:
1708 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
1709 return MCDisassembler::Fail;
1716 // On loads, the writeback operand comes after Rt.
1717 switch (Inst.getOpcode()) {
1720 case ARM::LDRD_POST:
1723 case ARM::LDRH_POST:
1725 case ARM::LDRSH_PRE:
1726 case ARM::LDRSH_POST:
1728 case ARM::LDRSB_PRE:
1729 case ARM::LDRSB_POST:
1732 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1733 return MCDisassembler::Fail;
1740 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1741 return MCDisassembler::Fail;
1744 Inst.addOperand(MCOperand::CreateReg(0));
1745 Inst.addOperand(MCOperand::CreateImm(U | (imm << 4) | Rm));
1747 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1748 return MCDisassembler::Fail;
1749 Inst.addOperand(MCOperand::CreateImm(U));
1752 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1753 return MCDisassembler::Fail;
1758 static DecodeStatus DecodeRFEInstruction(MCInst &Inst, unsigned Insn,
1759 uint64_t Address, const void *Decoder) {
1760 DecodeStatus S = MCDisassembler::Success;
1762 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1763 unsigned mode = fieldFromInstruction32(Insn, 23, 2);
1780 Inst.addOperand(MCOperand::CreateImm(mode));
1781 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1782 return MCDisassembler::Fail;
1787 static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst &Inst,
1789 uint64_t Address, const void *Decoder) {
1790 DecodeStatus S = MCDisassembler::Success;
1792 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1793 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1794 unsigned reglist = fieldFromInstruction32(Insn, 0, 16);
1797 switch (Inst.getOpcode()) {
1799 Inst.setOpcode(ARM::RFEDA);
1801 case ARM::LDMDA_UPD:
1802 Inst.setOpcode(ARM::RFEDA_UPD);
1805 Inst.setOpcode(ARM::RFEDB);
1807 case ARM::LDMDB_UPD:
1808 Inst.setOpcode(ARM::RFEDB_UPD);
1811 Inst.setOpcode(ARM::RFEIA);
1813 case ARM::LDMIA_UPD:
1814 Inst.setOpcode(ARM::RFEIA_UPD);
1817 Inst.setOpcode(ARM::RFEIB);
1819 case ARM::LDMIB_UPD:
1820 Inst.setOpcode(ARM::RFEIB_UPD);
1823 Inst.setOpcode(ARM::SRSDA);
1825 case ARM::STMDA_UPD:
1826 Inst.setOpcode(ARM::SRSDA_UPD);
1829 Inst.setOpcode(ARM::SRSDB);
1831 case ARM::STMDB_UPD:
1832 Inst.setOpcode(ARM::SRSDB_UPD);
1835 Inst.setOpcode(ARM::SRSIA);
1837 case ARM::STMIA_UPD:
1838 Inst.setOpcode(ARM::SRSIA_UPD);
1841 Inst.setOpcode(ARM::SRSIB);
1843 case ARM::STMIB_UPD:
1844 Inst.setOpcode(ARM::SRSIB_UPD);
1847 if (!Check(S, MCDisassembler::Fail)) return MCDisassembler::Fail;
1850 // For stores (which become SRS's, the only operand is the mode.
1851 if (fieldFromInstruction32(Insn, 20, 1) == 0) {
1853 MCOperand::CreateImm(fieldFromInstruction32(Insn, 0, 4)));
1857 return DecodeRFEInstruction(Inst, Insn, Address, Decoder);
1860 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1861 return MCDisassembler::Fail;
1862 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1863 return MCDisassembler::Fail; // Tied
1864 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1865 return MCDisassembler::Fail;
1866 if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder)))
1867 return MCDisassembler::Fail;
1872 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn,
1873 uint64_t Address, const void *Decoder) {
1874 unsigned imod = fieldFromInstruction32(Insn, 18, 2);
1875 unsigned M = fieldFromInstruction32(Insn, 17, 1);
1876 unsigned iflags = fieldFromInstruction32(Insn, 6, 3);
1877 unsigned mode = fieldFromInstruction32(Insn, 0, 5);
1879 DecodeStatus S = MCDisassembler::Success;
1881 // imod == '01' --> UNPREDICTABLE
1882 // NOTE: Even though this is technically UNPREDICTABLE, we choose to
1883 // return failure here. The '01' imod value is unprintable, so there's
1884 // nothing useful we could do even if we returned UNPREDICTABLE.
1886 if (imod == 1) return MCDisassembler::Fail;
1889 Inst.setOpcode(ARM::CPS3p);
1890 Inst.addOperand(MCOperand::CreateImm(imod));
1891 Inst.addOperand(MCOperand::CreateImm(iflags));
1892 Inst.addOperand(MCOperand::CreateImm(mode));
1893 } else if (imod && !M) {
1894 Inst.setOpcode(ARM::CPS2p);
1895 Inst.addOperand(MCOperand::CreateImm(imod));
1896 Inst.addOperand(MCOperand::CreateImm(iflags));
1897 if (mode) S = MCDisassembler::SoftFail;
1898 } else if (!imod && M) {
1899 Inst.setOpcode(ARM::CPS1p);
1900 Inst.addOperand(MCOperand::CreateImm(mode));
1901 if (iflags) S = MCDisassembler::SoftFail;
1903 // imod == '00' && M == '0' --> UNPREDICTABLE
1904 Inst.setOpcode(ARM::CPS1p);
1905 Inst.addOperand(MCOperand::CreateImm(mode));
1906 S = MCDisassembler::SoftFail;
1912 static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn,
1913 uint64_t Address, const void *Decoder) {
1914 unsigned imod = fieldFromInstruction32(Insn, 9, 2);
1915 unsigned M = fieldFromInstruction32(Insn, 8, 1);
1916 unsigned iflags = fieldFromInstruction32(Insn, 5, 3);
1917 unsigned mode = fieldFromInstruction32(Insn, 0, 5);
1919 DecodeStatus S = MCDisassembler::Success;
1921 // imod == '01' --> UNPREDICTABLE
1922 // NOTE: Even though this is technically UNPREDICTABLE, we choose to
1923 // return failure here. The '01' imod value is unprintable, so there's
1924 // nothing useful we could do even if we returned UNPREDICTABLE.
1926 if (imod == 1) return MCDisassembler::Fail;
1929 Inst.setOpcode(ARM::t2CPS3p);
1930 Inst.addOperand(MCOperand::CreateImm(imod));
1931 Inst.addOperand(MCOperand::CreateImm(iflags));
1932 Inst.addOperand(MCOperand::CreateImm(mode));
1933 } else if (imod && !M) {
1934 Inst.setOpcode(ARM::t2CPS2p);
1935 Inst.addOperand(MCOperand::CreateImm(imod));
1936 Inst.addOperand(MCOperand::CreateImm(iflags));
1937 if (mode) S = MCDisassembler::SoftFail;
1938 } else if (!imod && M) {
1939 Inst.setOpcode(ARM::t2CPS1p);
1940 Inst.addOperand(MCOperand::CreateImm(mode));
1941 if (iflags) S = MCDisassembler::SoftFail;
1943 // imod == '00' && M == '0' --> UNPREDICTABLE
1944 Inst.setOpcode(ARM::t2CPS1p);
1945 Inst.addOperand(MCOperand::CreateImm(mode));
1946 S = MCDisassembler::SoftFail;
1952 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn,
1953 uint64_t Address, const void *Decoder) {
1954 DecodeStatus S = MCDisassembler::Success;
1956 unsigned Rd = fieldFromInstruction32(Insn, 8, 4);
1959 imm |= (fieldFromInstruction32(Insn, 0, 8) << 0);
1960 imm |= (fieldFromInstruction32(Insn, 12, 3) << 8);
1961 imm |= (fieldFromInstruction32(Insn, 16, 4) << 12);
1962 imm |= (fieldFromInstruction32(Insn, 26, 1) << 11);
1964 if (Inst.getOpcode() == ARM::t2MOVTi16)
1965 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
1966 return MCDisassembler::Fail;
1967 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
1968 return MCDisassembler::Fail;
1970 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder))
1971 Inst.addOperand(MCOperand::CreateImm(imm));
1976 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn,
1977 uint64_t Address, const void *Decoder) {
1978 DecodeStatus S = MCDisassembler::Success;
1980 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
1981 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1984 imm |= (fieldFromInstruction32(Insn, 0, 12) << 0);
1985 imm |= (fieldFromInstruction32(Insn, 16, 4) << 12);
1987 if (Inst.getOpcode() == ARM::MOVTi16)
1988 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
1989 return MCDisassembler::Fail;
1990 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
1991 return MCDisassembler::Fail;
1993 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder))
1994 Inst.addOperand(MCOperand::CreateImm(imm));
1996 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1997 return MCDisassembler::Fail;
2002 static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn,
2003 uint64_t Address, const void *Decoder) {
2004 DecodeStatus S = MCDisassembler::Success;
2006 unsigned Rd = fieldFromInstruction32(Insn, 16, 4);
2007 unsigned Rn = fieldFromInstruction32(Insn, 0, 4);
2008 unsigned Rm = fieldFromInstruction32(Insn, 8, 4);
2009 unsigned Ra = fieldFromInstruction32(Insn, 12, 4);
2010 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
2013 return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
2015 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
2016 return MCDisassembler::Fail;
2017 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
2018 return MCDisassembler::Fail;
2019 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
2020 return MCDisassembler::Fail;
2021 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder)))
2022 return MCDisassembler::Fail;
2024 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2025 return MCDisassembler::Fail;
2030 static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val,
2031 uint64_t Address, const void *Decoder) {
2032 DecodeStatus S = MCDisassembler::Success;
2034 unsigned add = fieldFromInstruction32(Val, 12, 1);
2035 unsigned imm = fieldFromInstruction32(Val, 0, 12);
2036 unsigned Rn = fieldFromInstruction32(Val, 13, 4);
2038 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2039 return MCDisassembler::Fail;
2041 if (!add) imm *= -1;
2042 if (imm == 0 && !add) imm = INT32_MIN;
2043 Inst.addOperand(MCOperand::CreateImm(imm));
2045 tryAddingPcLoadReferenceComment(Address, Address + imm + 8, Decoder);
2050 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val,
2051 uint64_t Address, const void *Decoder) {
2052 DecodeStatus S = MCDisassembler::Success;
2054 unsigned Rn = fieldFromInstruction32(Val, 9, 4);
2055 unsigned U = fieldFromInstruction32(Val, 8, 1);
2056 unsigned imm = fieldFromInstruction32(Val, 0, 8);
2058 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2059 return MCDisassembler::Fail;
2062 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::add, imm)));
2064 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm)));
2069 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val,
2070 uint64_t Address, const void *Decoder) {
2071 return DecodeGPRRegisterClass(Inst, Val, Address, Decoder);
2075 DecodeT2BInstruction(MCInst &Inst, unsigned Insn,
2076 uint64_t Address, const void *Decoder) {
2077 DecodeStatus S = MCDisassembler::Success;
2078 unsigned imm = (fieldFromInstruction32(Insn, 0, 11) << 0) |
2079 (fieldFromInstruction32(Insn, 11, 1) << 18) |
2080 (fieldFromInstruction32(Insn, 13, 1) << 17) |
2081 (fieldFromInstruction32(Insn, 16, 6) << 11) |
2082 (fieldFromInstruction32(Insn, 26, 1) << 19);
2083 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<20>(imm<<1) + 4,
2084 true, 4, Inst, Decoder))
2085 Inst.addOperand(MCOperand::CreateImm(SignExtend32<20>(imm << 1)));
2090 DecodeBranchImmInstruction(MCInst &Inst, unsigned Insn,
2091 uint64_t Address, const void *Decoder) {
2092 DecodeStatus S = MCDisassembler::Success;
2094 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
2095 unsigned imm = fieldFromInstruction32(Insn, 0, 24) << 2;
2098 Inst.setOpcode(ARM::BLXi);
2099 imm |= fieldFromInstruction32(Insn, 24, 1) << 1;
2100 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8,
2101 true, 4, Inst, Decoder))
2102 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm)));
2106 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8,
2107 true, 4, Inst, Decoder))
2108 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm)));
2109 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2110 return MCDisassembler::Fail;
2116 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val,
2117 uint64_t Address, const void *Decoder) {
2118 DecodeStatus S = MCDisassembler::Success;
2120 unsigned Rm = fieldFromInstruction32(Val, 0, 4);
2121 unsigned align = fieldFromInstruction32(Val, 4, 2);
2123 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2124 return MCDisassembler::Fail;
2126 Inst.addOperand(MCOperand::CreateImm(0));
2128 Inst.addOperand(MCOperand::CreateImm(4 << align));
2133 static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Insn,
2134 uint64_t Address, const void *Decoder) {
2135 DecodeStatus S = MCDisassembler::Success;
2137 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2138 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2139 unsigned wb = fieldFromInstruction32(Insn, 16, 4);
2140 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2141 Rn |= fieldFromInstruction32(Insn, 4, 2) << 4;
2142 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2144 // First output register
2145 switch (Inst.getOpcode()) {
2146 case ARM::VLD1q16: case ARM::VLD1q32: case ARM::VLD1q64: case ARM::VLD1q8:
2147 case ARM::VLD1q16wb_fixed: case ARM::VLD1q16wb_register:
2148 case ARM::VLD1q32wb_fixed: case ARM::VLD1q32wb_register:
2149 case ARM::VLD1q64wb_fixed: case ARM::VLD1q64wb_register:
2150 case ARM::VLD1q8wb_fixed: case ARM::VLD1q8wb_register:
2151 case ARM::VLD2d16: case ARM::VLD2d32: case ARM::VLD2d8:
2152 case ARM::VLD2d16wb_fixed: case ARM::VLD2d16wb_register:
2153 case ARM::VLD2d32wb_fixed: case ARM::VLD2d32wb_register:
2154 case ARM::VLD2d8wb_fixed: case ARM::VLD2d8wb_register:
2155 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2156 return MCDisassembler::Fail;
2161 case ARM::VLD2b16wb_fixed:
2162 case ARM::VLD2b16wb_register:
2163 case ARM::VLD2b32wb_fixed:
2164 case ARM::VLD2b32wb_register:
2165 case ARM::VLD2b8wb_fixed:
2166 case ARM::VLD2b8wb_register:
2167 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
2168 return MCDisassembler::Fail;
2171 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2172 return MCDisassembler::Fail;
2175 // Second output register
2176 switch (Inst.getOpcode()) {
2180 case ARM::VLD3d8_UPD:
2181 case ARM::VLD3d16_UPD:
2182 case ARM::VLD3d32_UPD:
2186 case ARM::VLD4d8_UPD:
2187 case ARM::VLD4d16_UPD:
2188 case ARM::VLD4d32_UPD:
2189 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
2190 return MCDisassembler::Fail;
2195 case ARM::VLD3q8_UPD:
2196 case ARM::VLD3q16_UPD:
2197 case ARM::VLD3q32_UPD:
2201 case ARM::VLD4q8_UPD:
2202 case ARM::VLD4q16_UPD:
2203 case ARM::VLD4q32_UPD:
2204 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2205 return MCDisassembler::Fail;
2210 // Third output register
2211 switch(Inst.getOpcode()) {
2215 case ARM::VLD3d8_UPD:
2216 case ARM::VLD3d16_UPD:
2217 case ARM::VLD3d32_UPD:
2221 case ARM::VLD4d8_UPD:
2222 case ARM::VLD4d16_UPD:
2223 case ARM::VLD4d32_UPD:
2224 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2225 return MCDisassembler::Fail;
2230 case ARM::VLD3q8_UPD:
2231 case ARM::VLD3q16_UPD:
2232 case ARM::VLD3q32_UPD:
2236 case ARM::VLD4q8_UPD:
2237 case ARM::VLD4q16_UPD:
2238 case ARM::VLD4q32_UPD:
2239 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
2240 return MCDisassembler::Fail;
2246 // Fourth output register
2247 switch (Inst.getOpcode()) {
2251 case ARM::VLD4d8_UPD:
2252 case ARM::VLD4d16_UPD:
2253 case ARM::VLD4d32_UPD:
2254 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
2255 return MCDisassembler::Fail;
2260 case ARM::VLD4q8_UPD:
2261 case ARM::VLD4q16_UPD:
2262 case ARM::VLD4q32_UPD:
2263 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
2264 return MCDisassembler::Fail;
2270 // Writeback operand
2271 switch (Inst.getOpcode()) {
2272 case ARM::VLD1d8wb_fixed:
2273 case ARM::VLD1d16wb_fixed:
2274 case ARM::VLD1d32wb_fixed:
2275 case ARM::VLD1d64wb_fixed:
2276 case ARM::VLD1d8wb_register:
2277 case ARM::VLD1d16wb_register:
2278 case ARM::VLD1d32wb_register:
2279 case ARM::VLD1d64wb_register:
2280 case ARM::VLD1q8wb_fixed:
2281 case ARM::VLD1q16wb_fixed:
2282 case ARM::VLD1q32wb_fixed:
2283 case ARM::VLD1q64wb_fixed:
2284 case ARM::VLD1q8wb_register:
2285 case ARM::VLD1q16wb_register:
2286 case ARM::VLD1q32wb_register:
2287 case ARM::VLD1q64wb_register:
2288 case ARM::VLD1d8Twb_fixed:
2289 case ARM::VLD1d8Twb_register:
2290 case ARM::VLD1d16Twb_fixed:
2291 case ARM::VLD1d16Twb_register:
2292 case ARM::VLD1d32Twb_fixed:
2293 case ARM::VLD1d32Twb_register:
2294 case ARM::VLD1d64Twb_fixed:
2295 case ARM::VLD1d64Twb_register:
2296 case ARM::VLD1d8Qwb_fixed:
2297 case ARM::VLD1d8Qwb_register:
2298 case ARM::VLD1d16Qwb_fixed:
2299 case ARM::VLD1d16Qwb_register:
2300 case ARM::VLD1d32Qwb_fixed:
2301 case ARM::VLD1d32Qwb_register:
2302 case ARM::VLD1d64Qwb_fixed:
2303 case ARM::VLD1d64Qwb_register:
2304 case ARM::VLD2d8wb_fixed:
2305 case ARM::VLD2d16wb_fixed:
2306 case ARM::VLD2d32wb_fixed:
2307 case ARM::VLD2q8wb_fixed:
2308 case ARM::VLD2q16wb_fixed:
2309 case ARM::VLD2q32wb_fixed:
2310 case ARM::VLD2d8wb_register:
2311 case ARM::VLD2d16wb_register:
2312 case ARM::VLD2d32wb_register:
2313 case ARM::VLD2q8wb_register:
2314 case ARM::VLD2q16wb_register:
2315 case ARM::VLD2q32wb_register:
2316 case ARM::VLD2b8wb_fixed:
2317 case ARM::VLD2b16wb_fixed:
2318 case ARM::VLD2b32wb_fixed:
2319 case ARM::VLD2b8wb_register:
2320 case ARM::VLD2b16wb_register:
2321 case ARM::VLD2b32wb_register:
2322 Inst.addOperand(MCOperand::CreateImm(0));
2324 case ARM::VLD3d8_UPD:
2325 case ARM::VLD3d16_UPD:
2326 case ARM::VLD3d32_UPD:
2327 case ARM::VLD3q8_UPD:
2328 case ARM::VLD3q16_UPD:
2329 case ARM::VLD3q32_UPD:
2330 case ARM::VLD4d8_UPD:
2331 case ARM::VLD4d16_UPD:
2332 case ARM::VLD4d32_UPD:
2333 case ARM::VLD4q8_UPD:
2334 case ARM::VLD4q16_UPD:
2335 case ARM::VLD4q32_UPD:
2336 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
2337 return MCDisassembler::Fail;
2343 // AddrMode6 Base (register+alignment)
2344 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
2345 return MCDisassembler::Fail;
2347 // AddrMode6 Offset (register)
2348 switch (Inst.getOpcode()) {
2350 // The below have been updated to have explicit am6offset split
2351 // between fixed and register offset. For those instructions not
2352 // yet updated, we need to add an additional reg0 operand for the
2355 // The fixed offset encodes as Rm == 0xd, so we check for that.
2357 Inst.addOperand(MCOperand::CreateReg(0));
2360 // Fall through to handle the register offset variant.
2361 case ARM::VLD1d8wb_fixed:
2362 case ARM::VLD1d16wb_fixed:
2363 case ARM::VLD1d32wb_fixed:
2364 case ARM::VLD1d64wb_fixed:
2365 case ARM::VLD1d8Twb_fixed:
2366 case ARM::VLD1d16Twb_fixed:
2367 case ARM::VLD1d32Twb_fixed:
2368 case ARM::VLD1d64Twb_fixed:
2369 case ARM::VLD1d8Qwb_fixed:
2370 case ARM::VLD1d16Qwb_fixed:
2371 case ARM::VLD1d32Qwb_fixed:
2372 case ARM::VLD1d64Qwb_fixed:
2373 case ARM::VLD1d8wb_register:
2374 case ARM::VLD1d16wb_register:
2375 case ARM::VLD1d32wb_register:
2376 case ARM::VLD1d64wb_register:
2377 case ARM::VLD1q8wb_fixed:
2378 case ARM::VLD1q16wb_fixed:
2379 case ARM::VLD1q32wb_fixed:
2380 case ARM::VLD1q64wb_fixed:
2381 case ARM::VLD1q8wb_register:
2382 case ARM::VLD1q16wb_register:
2383 case ARM::VLD1q32wb_register:
2384 case ARM::VLD1q64wb_register:
2385 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback
2386 // variant encodes Rm == 0xf. Anything else is a register offset post-
2387 // increment and we need to add the register operand to the instruction.
2388 if (Rm != 0xD && Rm != 0xF &&
2389 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2390 return MCDisassembler::Fail;
2392 case ARM::VLD2d8wb_fixed:
2393 case ARM::VLD2d16wb_fixed:
2394 case ARM::VLD2d32wb_fixed:
2395 case ARM::VLD2b8wb_fixed:
2396 case ARM::VLD2b16wb_fixed:
2397 case ARM::VLD2b32wb_fixed:
2398 case ARM::VLD2q8wb_fixed:
2399 case ARM::VLD2q16wb_fixed:
2400 case ARM::VLD2q32wb_fixed:
2407 static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Insn,
2408 uint64_t Address, const void *Decoder) {
2409 DecodeStatus S = MCDisassembler::Success;
2411 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2412 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2413 unsigned wb = fieldFromInstruction32(Insn, 16, 4);
2414 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2415 Rn |= fieldFromInstruction32(Insn, 4, 2) << 4;
2416 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2418 // Writeback Operand
2419 switch (Inst.getOpcode()) {
2420 case ARM::VST1d8wb_fixed:
2421 case ARM::VST1d16wb_fixed:
2422 case ARM::VST1d32wb_fixed:
2423 case ARM::VST1d64wb_fixed:
2424 case ARM::VST1d8wb_register:
2425 case ARM::VST1d16wb_register:
2426 case ARM::VST1d32wb_register:
2427 case ARM::VST1d64wb_register:
2428 case ARM::VST1q8wb_fixed:
2429 case ARM::VST1q16wb_fixed:
2430 case ARM::VST1q32wb_fixed:
2431 case ARM::VST1q64wb_fixed:
2432 case ARM::VST1q8wb_register:
2433 case ARM::VST1q16wb_register:
2434 case ARM::VST1q32wb_register:
2435 case ARM::VST1q64wb_register:
2436 case ARM::VST1d8Twb_fixed:
2437 case ARM::VST1d16Twb_fixed:
2438 case ARM::VST1d32Twb_fixed:
2439 case ARM::VST1d64Twb_fixed:
2440 case ARM::VST1d8Twb_register:
2441 case ARM::VST1d16Twb_register:
2442 case ARM::VST1d32Twb_register:
2443 case ARM::VST1d64Twb_register:
2444 case ARM::VST1d8Qwb_fixed:
2445 case ARM::VST1d16Qwb_fixed:
2446 case ARM::VST1d32Qwb_fixed:
2447 case ARM::VST1d64Qwb_fixed:
2448 case ARM::VST1d8Qwb_register:
2449 case ARM::VST1d16Qwb_register:
2450 case ARM::VST1d32Qwb_register:
2451 case ARM::VST1d64Qwb_register:
2452 case ARM::VST2d8wb_fixed:
2453 case ARM::VST2d16wb_fixed:
2454 case ARM::VST2d32wb_fixed:
2455 case ARM::VST2d8wb_register:
2456 case ARM::VST2d16wb_register:
2457 case ARM::VST2d32wb_register:
2458 case ARM::VST2q8wb_fixed:
2459 case ARM::VST2q16wb_fixed:
2460 case ARM::VST2q32wb_fixed:
2461 case ARM::VST2q8wb_register:
2462 case ARM::VST2q16wb_register:
2463 case ARM::VST2q32wb_register:
2464 case ARM::VST2b8wb_fixed:
2465 case ARM::VST2b16wb_fixed:
2466 case ARM::VST2b32wb_fixed:
2467 case ARM::VST2b8wb_register:
2468 case ARM::VST2b16wb_register:
2469 case ARM::VST2b32wb_register:
2471 return MCDisassembler::Fail;
2472 Inst.addOperand(MCOperand::CreateImm(0));
2474 case ARM::VST3d8_UPD:
2475 case ARM::VST3d16_UPD:
2476 case ARM::VST3d32_UPD:
2477 case ARM::VST3q8_UPD:
2478 case ARM::VST3q16_UPD:
2479 case ARM::VST3q32_UPD:
2480 case ARM::VST4d8_UPD:
2481 case ARM::VST4d16_UPD:
2482 case ARM::VST4d32_UPD:
2483 case ARM::VST4q8_UPD:
2484 case ARM::VST4q16_UPD:
2485 case ARM::VST4q32_UPD:
2486 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
2487 return MCDisassembler::Fail;
2493 // AddrMode6 Base (register+alignment)
2494 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
2495 return MCDisassembler::Fail;
2497 // AddrMode6 Offset (register)
2498 switch (Inst.getOpcode()) {
2501 Inst.addOperand(MCOperand::CreateReg(0));
2502 else if (Rm != 0xF) {
2503 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2504 return MCDisassembler::Fail;
2507 case ARM::VST1d8wb_fixed:
2508 case ARM::VST1d16wb_fixed:
2509 case ARM::VST1d32wb_fixed:
2510 case ARM::VST1d64wb_fixed:
2511 case ARM::VST1q8wb_fixed:
2512 case ARM::VST1q16wb_fixed:
2513 case ARM::VST1q32wb_fixed:
2514 case ARM::VST1q64wb_fixed:
2515 case ARM::VST1d8Twb_fixed:
2516 case ARM::VST1d16Twb_fixed:
2517 case ARM::VST1d32Twb_fixed:
2518 case ARM::VST1d64Twb_fixed:
2519 case ARM::VST1d8Qwb_fixed:
2520 case ARM::VST1d16Qwb_fixed:
2521 case ARM::VST1d32Qwb_fixed:
2522 case ARM::VST1d64Qwb_fixed:
2523 case ARM::VST2d8wb_fixed:
2524 case ARM::VST2d16wb_fixed:
2525 case ARM::VST2d32wb_fixed:
2526 case ARM::VST2q8wb_fixed:
2527 case ARM::VST2q16wb_fixed:
2528 case ARM::VST2q32wb_fixed:
2529 case ARM::VST2b8wb_fixed:
2530 case ARM::VST2b16wb_fixed:
2531 case ARM::VST2b32wb_fixed:
2536 // First input register
2537 switch (Inst.getOpcode()) {
2542 case ARM::VST1q16wb_fixed:
2543 case ARM::VST1q16wb_register:
2544 case ARM::VST1q32wb_fixed:
2545 case ARM::VST1q32wb_register:
2546 case ARM::VST1q64wb_fixed:
2547 case ARM::VST1q64wb_register:
2548 case ARM::VST1q8wb_fixed:
2549 case ARM::VST1q8wb_register:
2553 case ARM::VST2d16wb_fixed:
2554 case ARM::VST2d16wb_register:
2555 case ARM::VST2d32wb_fixed:
2556 case ARM::VST2d32wb_register:
2557 case ARM::VST2d8wb_fixed:
2558 case ARM::VST2d8wb_register:
2559 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2560 return MCDisassembler::Fail;
2565 case ARM::VST2b16wb_fixed:
2566 case ARM::VST2b16wb_register:
2567 case ARM::VST2b32wb_fixed:
2568 case ARM::VST2b32wb_register:
2569 case ARM::VST2b8wb_fixed:
2570 case ARM::VST2b8wb_register:
2571 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
2572 return MCDisassembler::Fail;
2575 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2576 return MCDisassembler::Fail;
2579 // Second input register
2580 switch (Inst.getOpcode()) {
2584 case ARM::VST3d8_UPD:
2585 case ARM::VST3d16_UPD:
2586 case ARM::VST3d32_UPD:
2590 case ARM::VST4d8_UPD:
2591 case ARM::VST4d16_UPD:
2592 case ARM::VST4d32_UPD:
2593 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
2594 return MCDisassembler::Fail;
2599 case ARM::VST3q8_UPD:
2600 case ARM::VST3q16_UPD:
2601 case ARM::VST3q32_UPD:
2605 case ARM::VST4q8_UPD:
2606 case ARM::VST4q16_UPD:
2607 case ARM::VST4q32_UPD:
2608 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2609 return MCDisassembler::Fail;
2615 // Third input register
2616 switch (Inst.getOpcode()) {
2620 case ARM::VST3d8_UPD:
2621 case ARM::VST3d16_UPD:
2622 case ARM::VST3d32_UPD:
2626 case ARM::VST4d8_UPD:
2627 case ARM::VST4d16_UPD:
2628 case ARM::VST4d32_UPD:
2629 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2630 return MCDisassembler::Fail;
2635 case ARM::VST3q8_UPD:
2636 case ARM::VST3q16_UPD:
2637 case ARM::VST3q32_UPD:
2641 case ARM::VST4q8_UPD:
2642 case ARM::VST4q16_UPD:
2643 case ARM::VST4q32_UPD:
2644 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
2645 return MCDisassembler::Fail;
2651 // Fourth input register
2652 switch (Inst.getOpcode()) {
2656 case ARM::VST4d8_UPD:
2657 case ARM::VST4d16_UPD:
2658 case ARM::VST4d32_UPD:
2659 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
2660 return MCDisassembler::Fail;
2665 case ARM::VST4q8_UPD:
2666 case ARM::VST4q16_UPD:
2667 case ARM::VST4q32_UPD:
2668 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
2669 return MCDisassembler::Fail;
2678 static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Insn,
2679 uint64_t Address, const void *Decoder) {
2680 DecodeStatus S = MCDisassembler::Success;
2682 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2683 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2684 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2685 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2686 unsigned align = fieldFromInstruction32(Insn, 4, 1);
2687 unsigned size = fieldFromInstruction32(Insn, 6, 2);
2689 align *= (1 << size);
2691 switch (Inst.getOpcode()) {
2692 case ARM::VLD1DUPq16: case ARM::VLD1DUPq32: case ARM::VLD1DUPq8:
2693 case ARM::VLD1DUPq16wb_fixed: case ARM::VLD1DUPq16wb_register:
2694 case ARM::VLD1DUPq32wb_fixed: case ARM::VLD1DUPq32wb_register:
2695 case ARM::VLD1DUPq8wb_fixed: case ARM::VLD1DUPq8wb_register:
2696 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2697 return MCDisassembler::Fail;
2700 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2701 return MCDisassembler::Fail;
2705 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2706 return MCDisassembler::Fail;
2709 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2710 return MCDisassembler::Fail;
2711 Inst.addOperand(MCOperand::CreateImm(align));
2713 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback
2714 // variant encodes Rm == 0xf. Anything else is a register offset post-
2715 // increment and we need to add the register operand to the instruction.
2716 if (Rm != 0xD && Rm != 0xF &&
2717 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2718 return MCDisassembler::Fail;
2723 static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Insn,
2724 uint64_t Address, const void *Decoder) {
2725 DecodeStatus S = MCDisassembler::Success;
2727 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2728 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2729 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2730 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2731 unsigned align = fieldFromInstruction32(Insn, 4, 1);
2732 unsigned size = 1 << fieldFromInstruction32(Insn, 6, 2);
2735 switch (Inst.getOpcode()) {
2736 case ARM::VLD2DUPd16: case ARM::VLD2DUPd32: case ARM::VLD2DUPd8:
2737 case ARM::VLD2DUPd16wb_fixed: case ARM::VLD2DUPd16wb_register:
2738 case ARM::VLD2DUPd32wb_fixed: case ARM::VLD2DUPd32wb_register:
2739 case ARM::VLD2DUPd8wb_fixed: case ARM::VLD2DUPd8wb_register:
2740 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2741 return MCDisassembler::Fail;
2743 case ARM::VLD2DUPd16x2: case ARM::VLD2DUPd32x2: case ARM::VLD2DUPd8x2:
2744 case ARM::VLD2DUPd16x2wb_fixed: case ARM::VLD2DUPd16x2wb_register:
2745 case ARM::VLD2DUPd32x2wb_fixed: case ARM::VLD2DUPd32x2wb_register:
2746 case ARM::VLD2DUPd8x2wb_fixed: case ARM::VLD2DUPd8x2wb_register:
2747 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
2748 return MCDisassembler::Fail;
2751 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2752 return MCDisassembler::Fail;
2757 Inst.addOperand(MCOperand::CreateImm(0));
2759 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2760 return MCDisassembler::Fail;
2761 Inst.addOperand(MCOperand::CreateImm(align));
2763 if (Rm != 0xD && Rm != 0xF) {
2764 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2765 return MCDisassembler::Fail;
2771 static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Insn,
2772 uint64_t Address, const void *Decoder) {
2773 DecodeStatus S = MCDisassembler::Success;
2775 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2776 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2777 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2778 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2779 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1;
2781 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2782 return MCDisassembler::Fail;
2783 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
2784 return MCDisassembler::Fail;
2785 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
2786 return MCDisassembler::Fail;
2788 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2789 return MCDisassembler::Fail;
2792 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2793 return MCDisassembler::Fail;
2794 Inst.addOperand(MCOperand::CreateImm(0));
2797 Inst.addOperand(MCOperand::CreateReg(0));
2798 else if (Rm != 0xF) {
2799 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2800 return MCDisassembler::Fail;
2806 static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Insn,
2807 uint64_t Address, const void *Decoder) {
2808 DecodeStatus S = MCDisassembler::Success;
2810 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2811 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2812 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2813 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2814 unsigned size = fieldFromInstruction32(Insn, 6, 2);
2815 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1;
2816 unsigned align = fieldFromInstruction32(Insn, 4, 1);
2831 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2832 return MCDisassembler::Fail;
2833 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
2834 return MCDisassembler::Fail;
2835 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
2836 return MCDisassembler::Fail;
2837 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder)))
2838 return MCDisassembler::Fail;
2840 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2841 return MCDisassembler::Fail;
2844 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2845 return MCDisassembler::Fail;
2846 Inst.addOperand(MCOperand::CreateImm(align));
2849 Inst.addOperand(MCOperand::CreateReg(0));
2850 else if (Rm != 0xF) {
2851 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2852 return MCDisassembler::Fail;
2859 DecodeNEONModImmInstruction(MCInst &Inst, unsigned Insn,
2860 uint64_t Address, const void *Decoder) {
2861 DecodeStatus S = MCDisassembler::Success;
2863 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2864 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2865 unsigned imm = fieldFromInstruction32(Insn, 0, 4);
2866 imm |= fieldFromInstruction32(Insn, 16, 3) << 4;
2867 imm |= fieldFromInstruction32(Insn, 24, 1) << 7;
2868 imm |= fieldFromInstruction32(Insn, 8, 4) << 8;
2869 imm |= fieldFromInstruction32(Insn, 5, 1) << 12;
2870 unsigned Q = fieldFromInstruction32(Insn, 6, 1);
2873 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
2874 return MCDisassembler::Fail;
2876 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2877 return MCDisassembler::Fail;
2880 Inst.addOperand(MCOperand::CreateImm(imm));
2882 switch (Inst.getOpcode()) {
2883 case ARM::VORRiv4i16:
2884 case ARM::VORRiv2i32:
2885 case ARM::VBICiv4i16:
2886 case ARM::VBICiv2i32:
2887 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2888 return MCDisassembler::Fail;
2890 case ARM::VORRiv8i16:
2891 case ARM::VORRiv4i32:
2892 case ARM::VBICiv8i16:
2893 case ARM::VBICiv4i32:
2894 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
2895 return MCDisassembler::Fail;
2904 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Insn,
2905 uint64_t Address, const void *Decoder) {
2906 DecodeStatus S = MCDisassembler::Success;
2908 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2909 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2910 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2911 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4;
2912 unsigned size = fieldFromInstruction32(Insn, 18, 2);
2914 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
2915 return MCDisassembler::Fail;
2916 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
2917 return MCDisassembler::Fail;
2918 Inst.addOperand(MCOperand::CreateImm(8 << size));
2923 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val,
2924 uint64_t Address, const void *Decoder) {
2925 Inst.addOperand(MCOperand::CreateImm(8 - Val));
2926 return MCDisassembler::Success;
2929 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val,
2930 uint64_t Address, const void *Decoder) {
2931 Inst.addOperand(MCOperand::CreateImm(16 - Val));
2932 return MCDisassembler::Success;
2935 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val,
2936 uint64_t Address, const void *Decoder) {
2937 Inst.addOperand(MCOperand::CreateImm(32 - Val));
2938 return MCDisassembler::Success;
2941 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val,
2942 uint64_t Address, const void *Decoder) {
2943 Inst.addOperand(MCOperand::CreateImm(64 - Val));
2944 return MCDisassembler::Success;
2947 static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn,
2948 uint64_t Address, const void *Decoder) {
2949 DecodeStatus S = MCDisassembler::Success;
2951 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2952 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2953 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2954 Rn |= fieldFromInstruction32(Insn, 7, 1) << 4;
2955 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2956 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4;
2957 unsigned op = fieldFromInstruction32(Insn, 6, 1);
2959 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2960 return MCDisassembler::Fail;
2962 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2963 return MCDisassembler::Fail; // Writeback
2966 switch (Inst.getOpcode()) {
2969 if (!Check(S, DecodeDPairRegisterClass(Inst, Rn, Address, Decoder)))
2970 return MCDisassembler::Fail;
2973 if (!Check(S, DecodeDPRRegisterClass(Inst, Rn, Address, Decoder)))
2974 return MCDisassembler::Fail;
2977 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
2978 return MCDisassembler::Fail;
2983 static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn,
2984 uint64_t Address, const void *Decoder) {
2985 DecodeStatus S = MCDisassembler::Success;
2987 unsigned dst = fieldFromInstruction16(Insn, 8, 3);
2988 unsigned imm = fieldFromInstruction16(Insn, 0, 8);
2990 if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder)))
2991 return MCDisassembler::Fail;
2993 switch(Inst.getOpcode()) {
2995 return MCDisassembler::Fail;
2997 break; // tADR does not explicitly represent the PC as an operand.
2999 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3003 Inst.addOperand(MCOperand::CreateImm(imm));
3007 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val,
3008 uint64_t Address, const void *Decoder) {
3009 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<12>(Val<<1) + 4,
3010 true, 2, Inst, Decoder))
3011 Inst.addOperand(MCOperand::CreateImm(SignExtend32<12>(Val << 1)));
3012 return MCDisassembler::Success;
3015 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val,
3016 uint64_t Address, const void *Decoder) {
3017 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<22>(Val<<1) + 4,
3018 true, 4, Inst, Decoder))
3019 Inst.addOperand(MCOperand::CreateImm(SignExtend32<21>(Val)));
3020 return MCDisassembler::Success;
3023 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val,
3024 uint64_t Address, const void *Decoder) {
3025 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<7>(Val<<1) + 4,
3026 true, 2, Inst, Decoder))
3027 Inst.addOperand(MCOperand::CreateImm(SignExtend32<7>(Val << 1)));
3028 return MCDisassembler::Success;
3031 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val,
3032 uint64_t Address, const void *Decoder) {
3033 DecodeStatus S = MCDisassembler::Success;
3035 unsigned Rn = fieldFromInstruction32(Val, 0, 3);
3036 unsigned Rm = fieldFromInstruction32(Val, 3, 3);
3038 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
3039 return MCDisassembler::Fail;
3040 if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder)))
3041 return MCDisassembler::Fail;
3046 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val,
3047 uint64_t Address, const void *Decoder) {
3048 DecodeStatus S = MCDisassembler::Success;
3050 unsigned Rn = fieldFromInstruction32(Val, 0, 3);
3051 unsigned imm = fieldFromInstruction32(Val, 3, 5);
3053 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
3054 return MCDisassembler::Fail;
3055 Inst.addOperand(MCOperand::CreateImm(imm));
3060 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val,
3061 uint64_t Address, const void *Decoder) {
3062 unsigned imm = Val << 2;
3064 Inst.addOperand(MCOperand::CreateImm(imm));
3065 tryAddingPcLoadReferenceComment(Address, (Address & ~2u) + imm + 4, Decoder);
3067 return MCDisassembler::Success;
3070 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val,
3071 uint64_t Address, const void *Decoder) {
3072 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3073 Inst.addOperand(MCOperand::CreateImm(Val));
3075 return MCDisassembler::Success;
3078 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val,
3079 uint64_t Address, const void *Decoder) {
3080 DecodeStatus S = MCDisassembler::Success;
3082 unsigned Rn = fieldFromInstruction32(Val, 6, 4);
3083 unsigned Rm = fieldFromInstruction32(Val, 2, 4);
3084 unsigned imm = fieldFromInstruction32(Val, 0, 2);
3086 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3087 return MCDisassembler::Fail;
3088 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
3089 return MCDisassembler::Fail;
3090 Inst.addOperand(MCOperand::CreateImm(imm));
3095 static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Insn,
3096 uint64_t Address, const void *Decoder) {
3097 DecodeStatus S = MCDisassembler::Success;
3099 switch (Inst.getOpcode()) {
3105 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3106 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
3107 return MCDisassembler::Fail;
3111 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3113 switch (Inst.getOpcode()) {
3115 Inst.setOpcode(ARM::t2LDRBpci);
3118 Inst.setOpcode(ARM::t2LDRHpci);
3121 Inst.setOpcode(ARM::t2LDRSHpci);
3124 Inst.setOpcode(ARM::t2LDRSBpci);
3127 Inst.setOpcode(ARM::t2PLDi12);
3128 Inst.addOperand(MCOperand::CreateReg(ARM::PC));
3131 return MCDisassembler::Fail;
3134 int imm = fieldFromInstruction32(Insn, 0, 12);
3135 if (!fieldFromInstruction32(Insn, 23, 1)) imm *= -1;
3136 Inst.addOperand(MCOperand::CreateImm(imm));
3141 unsigned addrmode = fieldFromInstruction32(Insn, 4, 2);
3142 addrmode |= fieldFromInstruction32(Insn, 0, 4) << 2;
3143 addrmode |= fieldFromInstruction32(Insn, 16, 4) << 6;
3144 if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder)))
3145 return MCDisassembler::Fail;
3150 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val,
3151 uint64_t Address, const void *Decoder) {
3152 int imm = Val & 0xFF;
3153 if (!(Val & 0x100)) imm *= -1;
3154 Inst.addOperand(MCOperand::CreateImm(imm << 2));
3156 return MCDisassembler::Success;
3159 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val,
3160 uint64_t Address, const void *Decoder) {
3161 DecodeStatus S = MCDisassembler::Success;
3163 unsigned Rn = fieldFromInstruction32(Val, 9, 4);
3164 unsigned imm = fieldFromInstruction32(Val, 0, 9);
3166 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3167 return MCDisassembler::Fail;
3168 if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder)))
3169 return MCDisassembler::Fail;
3174 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val,
3175 uint64_t Address, const void *Decoder) {
3176 DecodeStatus S = MCDisassembler::Success;
3178 unsigned Rn = fieldFromInstruction32(Val, 8, 4);
3179 unsigned imm = fieldFromInstruction32(Val, 0, 8);
3181 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
3182 return MCDisassembler::Fail;
3184 Inst.addOperand(MCOperand::CreateImm(imm));
3189 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val,
3190 uint64_t Address, const void *Decoder) {
3191 int imm = Val & 0xFF;
3194 else if (!(Val & 0x100))
3196 Inst.addOperand(MCOperand::CreateImm(imm));
3198 return MCDisassembler::Success;
3202 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val,
3203 uint64_t Address, const void *Decoder) {
3204 DecodeStatus S = MCDisassembler::Success;
3206 unsigned Rn = fieldFromInstruction32(Val, 9, 4);
3207 unsigned imm = fieldFromInstruction32(Val, 0, 9);
3209 // Some instructions always use an additive offset.
3210 switch (Inst.getOpcode()) {
3225 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3226 return MCDisassembler::Fail;
3227 if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder)))
3228 return MCDisassembler::Fail;
3233 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Insn,
3234 uint64_t Address, const void *Decoder) {
3235 DecodeStatus S = MCDisassembler::Success;
3237 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3238 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3239 unsigned addr = fieldFromInstruction32(Insn, 0, 8);
3240 addr |= fieldFromInstruction32(Insn, 9, 1) << 8;
3242 unsigned load = fieldFromInstruction32(Insn, 20, 1);
3245 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3246 return MCDisassembler::Fail;
3249 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
3250 return MCDisassembler::Fail;
3253 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3254 return MCDisassembler::Fail;
3257 if (!Check(S, DecodeT2AddrModeImm8(Inst, addr, Address, Decoder)))
3258 return MCDisassembler::Fail;
3263 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val,
3264 uint64_t Address, const void *Decoder) {
3265 DecodeStatus S = MCDisassembler::Success;
3267 unsigned Rn = fieldFromInstruction32(Val, 13, 4);
3268 unsigned imm = fieldFromInstruction32(Val, 0, 12);
3270 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3271 return MCDisassembler::Fail;
3272 Inst.addOperand(MCOperand::CreateImm(imm));
3278 static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Insn,
3279 uint64_t Address, const void *Decoder) {
3280 unsigned imm = fieldFromInstruction16(Insn, 0, 7);
3282 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3283 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3284 Inst.addOperand(MCOperand::CreateImm(imm));
3286 return MCDisassembler::Success;
3289 static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn,
3290 uint64_t Address, const void *Decoder) {
3291 DecodeStatus S = MCDisassembler::Success;
3293 if (Inst.getOpcode() == ARM::tADDrSP) {
3294 unsigned Rdm = fieldFromInstruction16(Insn, 0, 3);
3295 Rdm |= fieldFromInstruction16(Insn, 7, 1) << 3;
3297 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
3298 return MCDisassembler::Fail;
3299 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3300 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
3301 return MCDisassembler::Fail;
3302 } else if (Inst.getOpcode() == ARM::tADDspr) {
3303 unsigned Rm = fieldFromInstruction16(Insn, 3, 4);
3305 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3306 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3307 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3308 return MCDisassembler::Fail;
3314 static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn,
3315 uint64_t Address, const void *Decoder) {
3316 unsigned imod = fieldFromInstruction16(Insn, 4, 1) | 0x2;
3317 unsigned flags = fieldFromInstruction16(Insn, 0, 3);
3319 Inst.addOperand(MCOperand::CreateImm(imod));
3320 Inst.addOperand(MCOperand::CreateImm(flags));
3322 return MCDisassembler::Success;
3325 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn,
3326 uint64_t Address, const void *Decoder) {
3327 DecodeStatus S = MCDisassembler::Success;
3328 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3329 unsigned add = fieldFromInstruction32(Insn, 4, 1);
3331 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
3332 return MCDisassembler::Fail;
3333 Inst.addOperand(MCOperand::CreateImm(add));
3338 static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Val,
3339 uint64_t Address, const void *Decoder) {
3340 if (!tryAddingSymbolicOperand(Address,
3341 (Address & ~2u) + SignExtend32<22>(Val << 1) + 4,
3342 true, 4, Inst, Decoder))
3343 Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1)));
3344 return MCDisassembler::Success;
3347 static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Val,
3348 uint64_t Address, const void *Decoder) {
3349 if (Val == 0xA || Val == 0xB)
3350 return MCDisassembler::Fail;
3352 Inst.addOperand(MCOperand::CreateImm(Val));
3353 return MCDisassembler::Success;
3357 DecodeThumbTableBranch(MCInst &Inst, unsigned Insn,
3358 uint64_t Address, const void *Decoder) {
3359 DecodeStatus S = MCDisassembler::Success;
3361 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3362 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3364 if (Rn == ARM::SP) S = MCDisassembler::SoftFail;
3365 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3366 return MCDisassembler::Fail;
3367 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
3368 return MCDisassembler::Fail;
3373 DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Insn,
3374 uint64_t Address, const void *Decoder) {
3375 DecodeStatus S = MCDisassembler::Success;
3377 unsigned pred = fieldFromInstruction32(Insn, 22, 4);
3378 if (pred == 0xE || pred == 0xF) {
3379 unsigned opc = fieldFromInstruction32(Insn, 4, 28);
3382 return MCDisassembler::Fail;
3384 Inst.setOpcode(ARM::t2DSB);
3387 Inst.setOpcode(ARM::t2DMB);
3390 Inst.setOpcode(ARM::t2ISB);
3394 unsigned imm = fieldFromInstruction32(Insn, 0, 4);
3395 return DecodeMemBarrierOption(Inst, imm, Address, Decoder);
3398 unsigned brtarget = fieldFromInstruction32(Insn, 0, 11) << 1;
3399 brtarget |= fieldFromInstruction32(Insn, 11, 1) << 19;
3400 brtarget |= fieldFromInstruction32(Insn, 13, 1) << 18;
3401 brtarget |= fieldFromInstruction32(Insn, 16, 6) << 12;
3402 brtarget |= fieldFromInstruction32(Insn, 26, 1) << 20;
3404 if (!Check(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder)))
3405 return MCDisassembler::Fail;
3406 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3407 return MCDisassembler::Fail;
3412 // Decode a shifted immediate operand. These basically consist
3413 // of an 8-bit value, and a 4-bit directive that specifies either
3414 // a splat operation or a rotation.
3415 static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val,
3416 uint64_t Address, const void *Decoder) {
3417 unsigned ctrl = fieldFromInstruction32(Val, 10, 2);
3419 unsigned byte = fieldFromInstruction32(Val, 8, 2);
3420 unsigned imm = fieldFromInstruction32(Val, 0, 8);
3423 Inst.addOperand(MCOperand::CreateImm(imm));
3426 Inst.addOperand(MCOperand::CreateImm((imm << 16) | imm));
3429 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 8)));
3432 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 16) |
3437 unsigned unrot = fieldFromInstruction32(Val, 0, 7) | 0x80;
3438 unsigned rot = fieldFromInstruction32(Val, 7, 5);
3439 unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31));
3440 Inst.addOperand(MCOperand::CreateImm(imm));
3443 return MCDisassembler::Success;
3447 DecodeThumbBCCTargetOperand(MCInst &Inst, unsigned Val,
3448 uint64_t Address, const void *Decoder){
3449 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<8>(Val<<1) + 4,
3450 true, 2, Inst, Decoder))
3451 Inst.addOperand(MCOperand::CreateImm(SignExtend32<8>(Val << 1)));
3452 return MCDisassembler::Success;
3455 static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val,
3456 uint64_t Address, const void *Decoder){
3457 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<22>(Val<<1) + 4,
3458 true, 4, Inst, Decoder))
3459 Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1)));
3460 return MCDisassembler::Success;
3463 static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Val,
3464 uint64_t Address, const void *Decoder) {
3467 return MCDisassembler::Fail;
3479 Inst.addOperand(MCOperand::CreateImm(Val));
3480 return MCDisassembler::Success;
3483 static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Val,
3484 uint64_t Address, const void *Decoder) {
3485 if (!Val) return MCDisassembler::Fail;
3486 Inst.addOperand(MCOperand::CreateImm(Val));
3487 return MCDisassembler::Success;
3490 static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn,
3491 uint64_t Address, const void *Decoder) {
3492 DecodeStatus S = MCDisassembler::Success;
3494 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3495 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3496 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3498 if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return MCDisassembler::Fail;
3500 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3501 return MCDisassembler::Fail;
3502 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
3503 return MCDisassembler::Fail;
3504 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3505 return MCDisassembler::Fail;
3506 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3507 return MCDisassembler::Fail;
3513 static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn,
3514 uint64_t Address, const void *Decoder){
3515 DecodeStatus S = MCDisassembler::Success;
3517 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3518 unsigned Rt = fieldFromInstruction32(Insn, 0, 4);
3519 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3520 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3522 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
3523 return MCDisassembler::Fail;
3525 if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return MCDisassembler::Fail;
3526 if (Rd == Rn || Rd == Rt || Rd == Rt+1) return MCDisassembler::Fail;
3528 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3529 return MCDisassembler::Fail;
3530 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
3531 return MCDisassembler::Fail;
3532 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3533 return MCDisassembler::Fail;
3534 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3535 return MCDisassembler::Fail;
3540 static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn,
3541 uint64_t Address, const void *Decoder) {
3542 DecodeStatus S = MCDisassembler::Success;
3544 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3545 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3546 unsigned imm = fieldFromInstruction32(Insn, 0, 12);
3547 imm |= fieldFromInstruction32(Insn, 16, 4) << 13;
3548 imm |= fieldFromInstruction32(Insn, 23, 1) << 12;
3549 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3551 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
3553 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3554 return MCDisassembler::Fail;
3555 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3556 return MCDisassembler::Fail;
3557 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
3558 return MCDisassembler::Fail;
3559 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3560 return MCDisassembler::Fail;
3565 static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn,
3566 uint64_t Address, const void *Decoder) {
3567 DecodeStatus S = MCDisassembler::Success;
3569 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3570 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3571 unsigned imm = fieldFromInstruction32(Insn, 0, 12);
3572 imm |= fieldFromInstruction32(Insn, 16, 4) << 13;
3573 imm |= fieldFromInstruction32(Insn, 23, 1) << 12;
3574 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3575 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3577 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
3578 if (Rm == 0xF) S = MCDisassembler::SoftFail;
3580 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3581 return MCDisassembler::Fail;
3582 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3583 return MCDisassembler::Fail;
3584 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
3585 return MCDisassembler::Fail;
3586 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3587 return MCDisassembler::Fail;
3593 static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn,
3594 uint64_t Address, const void *Decoder) {
3595 DecodeStatus S = MCDisassembler::Success;
3597 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3598 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3599 unsigned imm = fieldFromInstruction32(Insn, 0, 12);
3600 imm |= fieldFromInstruction32(Insn, 16, 4) << 13;
3601 imm |= fieldFromInstruction32(Insn, 23, 1) << 12;
3602 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3604 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
3606 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3607 return MCDisassembler::Fail;
3608 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3609 return MCDisassembler::Fail;
3610 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
3611 return MCDisassembler::Fail;
3612 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3613 return MCDisassembler::Fail;
3618 static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn,
3619 uint64_t Address, const void *Decoder) {
3620 DecodeStatus S = MCDisassembler::Success;
3622 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3623 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3624 unsigned imm = fieldFromInstruction32(Insn, 0, 12);
3625 imm |= fieldFromInstruction32(Insn, 16, 4) << 13;
3626 imm |= fieldFromInstruction32(Insn, 23, 1) << 12;
3627 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3629 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
3631 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3632 return MCDisassembler::Fail;
3633 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3634 return MCDisassembler::Fail;
3635 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
3636 return MCDisassembler::Fail;
3637 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3638 return MCDisassembler::Fail;
3643 static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn,
3644 uint64_t Address, const void *Decoder) {
3645 DecodeStatus S = MCDisassembler::Success;
3647 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3648 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3649 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3650 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3651 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3657 return MCDisassembler::Fail;
3659 if (fieldFromInstruction32(Insn, 4, 1))
3660 return MCDisassembler::Fail; // UNDEFINED
3661 index = fieldFromInstruction32(Insn, 5, 3);
3664 if (fieldFromInstruction32(Insn, 5, 1))
3665 return MCDisassembler::Fail; // UNDEFINED
3666 index = fieldFromInstruction32(Insn, 6, 2);
3667 if (fieldFromInstruction32(Insn, 4, 1))
3671 if (fieldFromInstruction32(Insn, 6, 1))
3672 return MCDisassembler::Fail; // UNDEFINED
3673 index = fieldFromInstruction32(Insn, 7, 1);
3674 if (fieldFromInstruction32(Insn, 4, 2) != 0)
3678 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3679 return MCDisassembler::Fail;
3680 if (Rm != 0xF) { // Writeback
3681 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3682 return MCDisassembler::Fail;
3684 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3685 return MCDisassembler::Fail;
3686 Inst.addOperand(MCOperand::CreateImm(align));
3689 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3690 return MCDisassembler::Fail;
3692 Inst.addOperand(MCOperand::CreateReg(0));
3695 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3696 return MCDisassembler::Fail;
3697 Inst.addOperand(MCOperand::CreateImm(index));
3702 static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn,
3703 uint64_t Address, const void *Decoder) {
3704 DecodeStatus S = MCDisassembler::Success;
3706 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3707 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3708 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3709 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3710 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3716 return MCDisassembler::Fail;
3718 if (fieldFromInstruction32(Insn, 4, 1))
3719 return MCDisassembler::Fail; // UNDEFINED
3720 index = fieldFromInstruction32(Insn, 5, 3);
3723 if (fieldFromInstruction32(Insn, 5, 1))
3724 return MCDisassembler::Fail; // UNDEFINED
3725 index = fieldFromInstruction32(Insn, 6, 2);
3726 if (fieldFromInstruction32(Insn, 4, 1))
3730 if (fieldFromInstruction32(Insn, 6, 1))
3731 return MCDisassembler::Fail; // UNDEFINED
3732 index = fieldFromInstruction32(Insn, 7, 1);
3733 if (fieldFromInstruction32(Insn, 4, 2) != 0)
3737 if (Rm != 0xF) { // Writeback
3738 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3739 return MCDisassembler::Fail;
3741 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3742 return MCDisassembler::Fail;
3743 Inst.addOperand(MCOperand::CreateImm(align));
3746 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3747 return MCDisassembler::Fail;
3749 Inst.addOperand(MCOperand::CreateReg(0));
3752 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3753 return MCDisassembler::Fail;
3754 Inst.addOperand(MCOperand::CreateImm(index));
3760 static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn,
3761 uint64_t Address, const void *Decoder) {
3762 DecodeStatus S = MCDisassembler::Success;
3764 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3765 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3766 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3767 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3768 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3775 return MCDisassembler::Fail;
3777 index = fieldFromInstruction32(Insn, 5, 3);
3778 if (fieldFromInstruction32(Insn, 4, 1))
3782 index = fieldFromInstruction32(Insn, 6, 2);
3783 if (fieldFromInstruction32(Insn, 4, 1))
3785 if (fieldFromInstruction32(Insn, 5, 1))
3789 if (fieldFromInstruction32(Insn, 5, 1))
3790 return MCDisassembler::Fail; // UNDEFINED
3791 index = fieldFromInstruction32(Insn, 7, 1);
3792 if (fieldFromInstruction32(Insn, 4, 1) != 0)
3794 if (fieldFromInstruction32(Insn, 6, 1))
3799 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3800 return MCDisassembler::Fail;
3801 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3802 return MCDisassembler::Fail;
3803 if (Rm != 0xF) { // Writeback
3804 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3805 return MCDisassembler::Fail;
3807 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3808 return MCDisassembler::Fail;
3809 Inst.addOperand(MCOperand::CreateImm(align));
3812 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3813 return MCDisassembler::Fail;
3815 Inst.addOperand(MCOperand::CreateReg(0));
3818 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3819 return MCDisassembler::Fail;
3820 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3821 return MCDisassembler::Fail;
3822 Inst.addOperand(MCOperand::CreateImm(index));
3827 static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn,
3828 uint64_t Address, const void *Decoder) {
3829 DecodeStatus S = MCDisassembler::Success;
3831 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3832 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3833 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3834 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3835 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3842 return MCDisassembler::Fail;
3844 index = fieldFromInstruction32(Insn, 5, 3);
3845 if (fieldFromInstruction32(Insn, 4, 1))
3849 index = fieldFromInstruction32(Insn, 6, 2);
3850 if (fieldFromInstruction32(Insn, 4, 1))
3852 if (fieldFromInstruction32(Insn, 5, 1))
3856 if (fieldFromInstruction32(Insn, 5, 1))
3857 return MCDisassembler::Fail; // UNDEFINED
3858 index = fieldFromInstruction32(Insn, 7, 1);
3859 if (fieldFromInstruction32(Insn, 4, 1) != 0)
3861 if (fieldFromInstruction32(Insn, 6, 1))
3866 if (Rm != 0xF) { // Writeback
3867 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3868 return MCDisassembler::Fail;
3870 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3871 return MCDisassembler::Fail;
3872 Inst.addOperand(MCOperand::CreateImm(align));
3875 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3876 return MCDisassembler::Fail;
3878 Inst.addOperand(MCOperand::CreateReg(0));
3881 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3882 return MCDisassembler::Fail;
3883 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3884 return MCDisassembler::Fail;
3885 Inst.addOperand(MCOperand::CreateImm(index));
3891 static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn,
3892 uint64_t Address, const void *Decoder) {
3893 DecodeStatus S = MCDisassembler::Success;
3895 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3896 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3897 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3898 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3899 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3906 return MCDisassembler::Fail;
3908 if (fieldFromInstruction32(Insn, 4, 1))
3909 return MCDisassembler::Fail; // UNDEFINED
3910 index = fieldFromInstruction32(Insn, 5, 3);
3913 if (fieldFromInstruction32(Insn, 4, 1))
3914 return MCDisassembler::Fail; // UNDEFINED
3915 index = fieldFromInstruction32(Insn, 6, 2);
3916 if (fieldFromInstruction32(Insn, 5, 1))
3920 if (fieldFromInstruction32(Insn, 4, 2))
3921 return MCDisassembler::Fail; // UNDEFINED
3922 index = fieldFromInstruction32(Insn, 7, 1);
3923 if (fieldFromInstruction32(Insn, 6, 1))
3928 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3929 return MCDisassembler::Fail;
3930 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3931 return MCDisassembler::Fail;
3932 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
3933 return MCDisassembler::Fail;
3935 if (Rm != 0xF) { // Writeback
3936 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3937 return MCDisassembler::Fail;
3939 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3940 return MCDisassembler::Fail;
3941 Inst.addOperand(MCOperand::CreateImm(align));
3944 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3945 return MCDisassembler::Fail;
3947 Inst.addOperand(MCOperand::CreateReg(0));
3950 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3951 return MCDisassembler::Fail;
3952 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3953 return MCDisassembler::Fail;
3954 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
3955 return MCDisassembler::Fail;
3956 Inst.addOperand(MCOperand::CreateImm(index));
3961 static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn,
3962 uint64_t Address, const void *Decoder) {
3963 DecodeStatus S = MCDisassembler::Success;
3965 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3966 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3967 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3968 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3969 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3976 return MCDisassembler::Fail;
3978 if (fieldFromInstruction32(Insn, 4, 1))
3979 return MCDisassembler::Fail; // UNDEFINED
3980 index = fieldFromInstruction32(Insn, 5, 3);
3983 if (fieldFromInstruction32(Insn, 4, 1))
3984 return MCDisassembler::Fail; // UNDEFINED
3985 index = fieldFromInstruction32(Insn, 6, 2);
3986 if (fieldFromInstruction32(Insn, 5, 1))
3990 if (fieldFromInstruction32(Insn, 4, 2))
3991 return MCDisassembler::Fail; // UNDEFINED
3992 index = fieldFromInstruction32(Insn, 7, 1);
3993 if (fieldFromInstruction32(Insn, 6, 1))
3998 if (Rm != 0xF) { // Writeback
3999 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4000 return MCDisassembler::Fail;
4002 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4003 return MCDisassembler::Fail;
4004 Inst.addOperand(MCOperand::CreateImm(align));
4007 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4008 return MCDisassembler::Fail;
4010 Inst.addOperand(MCOperand::CreateReg(0));
4013 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4014 return MCDisassembler::Fail;
4015 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4016 return MCDisassembler::Fail;
4017 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4018 return MCDisassembler::Fail;
4019 Inst.addOperand(MCOperand::CreateImm(index));
4025 static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn,
4026 uint64_t Address, const void *Decoder) {
4027 DecodeStatus S = MCDisassembler::Success;
4029 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
4030 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
4031 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
4032 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
4033 unsigned size = fieldFromInstruction32(Insn, 10, 2);
4040 return MCDisassembler::Fail;
4042 if (fieldFromInstruction32(Insn, 4, 1))
4044 index = fieldFromInstruction32(Insn, 5, 3);
4047 if (fieldFromInstruction32(Insn, 4, 1))
4049 index = fieldFromInstruction32(Insn, 6, 2);
4050 if (fieldFromInstruction32(Insn, 5, 1))
4054 if (fieldFromInstruction32(Insn, 4, 2))
4055 align = 4 << fieldFromInstruction32(Insn, 4, 2);
4056 index = fieldFromInstruction32(Insn, 7, 1);
4057 if (fieldFromInstruction32(Insn, 6, 1))
4062 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4063 return MCDisassembler::Fail;
4064 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4065 return MCDisassembler::Fail;
4066 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4067 return MCDisassembler::Fail;
4068 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
4069 return MCDisassembler::Fail;
4071 if (Rm != 0xF) { // Writeback
4072 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4073 return MCDisassembler::Fail;
4075 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4076 return MCDisassembler::Fail;
4077 Inst.addOperand(MCOperand::CreateImm(align));
4080 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4081 return MCDisassembler::Fail;
4083 Inst.addOperand(MCOperand::CreateReg(0));
4086 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4087 return MCDisassembler::Fail;
4088 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4089 return MCDisassembler::Fail;
4090 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4091 return MCDisassembler::Fail;
4092 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
4093 return MCDisassembler::Fail;
4094 Inst.addOperand(MCOperand::CreateImm(index));
4099 static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn,
4100 uint64_t Address, const void *Decoder) {
4101 DecodeStatus S = MCDisassembler::Success;
4103 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
4104 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
4105 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
4106 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
4107 unsigned size = fieldFromInstruction32(Insn, 10, 2);
4114 return MCDisassembler::Fail;
4116 if (fieldFromInstruction32(Insn, 4, 1))
4118 index = fieldFromInstruction32(Insn, 5, 3);
4121 if (fieldFromInstruction32(Insn, 4, 1))
4123 index = fieldFromInstruction32(Insn, 6, 2);
4124 if (fieldFromInstruction32(Insn, 5, 1))
4128 if (fieldFromInstruction32(Insn, 4, 2))
4129 align = 4 << fieldFromInstruction32(Insn, 4, 2);
4130 index = fieldFromInstruction32(Insn, 7, 1);
4131 if (fieldFromInstruction32(Insn, 6, 1))
4136 if (Rm != 0xF) { // Writeback
4137 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4138 return MCDisassembler::Fail;
4140 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4141 return MCDisassembler::Fail;
4142 Inst.addOperand(MCOperand::CreateImm(align));
4145 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4146 return MCDisassembler::Fail;
4148 Inst.addOperand(MCOperand::CreateReg(0));
4151 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4152 return MCDisassembler::Fail;
4153 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4154 return MCDisassembler::Fail;
4155 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4156 return MCDisassembler::Fail;
4157 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
4158 return MCDisassembler::Fail;
4159 Inst.addOperand(MCOperand::CreateImm(index));
4164 static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn,
4165 uint64_t Address, const void *Decoder) {
4166 DecodeStatus S = MCDisassembler::Success;
4167 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
4168 unsigned Rt2 = fieldFromInstruction32(Insn, 16, 4);
4169 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
4170 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
4171 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4;
4173 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
4174 S = MCDisassembler::SoftFail;
4176 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)))
4177 return MCDisassembler::Fail;
4178 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
4179 return MCDisassembler::Fail;
4180 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder)))
4181 return MCDisassembler::Fail;
4182 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
4183 return MCDisassembler::Fail;
4184 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4185 return MCDisassembler::Fail;
4190 static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn,
4191 uint64_t Address, const void *Decoder) {
4192 DecodeStatus S = MCDisassembler::Success;
4193 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
4194 unsigned Rt2 = fieldFromInstruction32(Insn, 16, 4);
4195 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
4196 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
4197 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4;
4199 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
4200 S = MCDisassembler::SoftFail;
4202 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder)))
4203 return MCDisassembler::Fail;
4204 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
4205 return MCDisassembler::Fail;
4206 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)))
4207 return MCDisassembler::Fail;
4208 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
4209 return MCDisassembler::Fail;
4210 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4211 return MCDisassembler::Fail;
4216 static DecodeStatus DecodeIT(MCInst &Inst, unsigned Insn,
4217 uint64_t Address, const void *Decoder) {
4218 DecodeStatus S = MCDisassembler::Success;
4219 unsigned pred = fieldFromInstruction16(Insn, 4, 4);
4220 unsigned mask = fieldFromInstruction16(Insn, 0, 4);
4224 S = MCDisassembler::SoftFail;
4229 S = MCDisassembler::SoftFail;
4232 Inst.addOperand(MCOperand::CreateImm(pred));
4233 Inst.addOperand(MCOperand::CreateImm(mask));
4238 DecodeT2LDRDPreInstruction(MCInst &Inst, unsigned Insn,
4239 uint64_t Address, const void *Decoder) {
4240 DecodeStatus S = MCDisassembler::Success;
4242 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
4243 unsigned Rt2 = fieldFromInstruction32(Insn, 8, 4);
4244 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
4245 unsigned addr = fieldFromInstruction32(Insn, 0, 8);
4246 unsigned W = fieldFromInstruction32(Insn, 21, 1);
4247 unsigned U = fieldFromInstruction32(Insn, 23, 1);
4248 unsigned P = fieldFromInstruction32(Insn, 24, 1);
4249 bool writeback = (W == 1) | (P == 0);
4251 addr |= (U << 8) | (Rn << 9);
4253 if (writeback && (Rn == Rt || Rn == Rt2))
4254 Check(S, MCDisassembler::SoftFail);
4256 Check(S, MCDisassembler::SoftFail);
4259 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
4260 return MCDisassembler::Fail;
4262 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
4263 return MCDisassembler::Fail;
4264 // Writeback operand
4265 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
4266 return MCDisassembler::Fail;
4268 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
4269 return MCDisassembler::Fail;
4275 DecodeT2STRDPreInstruction(MCInst &Inst, unsigned Insn,
4276 uint64_t Address, const void *Decoder) {
4277 DecodeStatus S = MCDisassembler::Success;
4279 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
4280 unsigned Rt2 = fieldFromInstruction32(Insn, 8, 4);
4281 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
4282 unsigned addr = fieldFromInstruction32(Insn, 0, 8);
4283 unsigned W = fieldFromInstruction32(Insn, 21, 1);
4284 unsigned U = fieldFromInstruction32(Insn, 23, 1);
4285 unsigned P = fieldFromInstruction32(Insn, 24, 1);
4286 bool writeback = (W == 1) | (P == 0);
4288 addr |= (U << 8) | (Rn << 9);
4290 if (writeback && (Rn == Rt || Rn == Rt2))
4291 Check(S, MCDisassembler::SoftFail);
4293 // Writeback operand
4294 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
4295 return MCDisassembler::Fail;
4297 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
4298 return MCDisassembler::Fail;
4300 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
4301 return MCDisassembler::Fail;
4303 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
4304 return MCDisassembler::Fail;
4309 static DecodeStatus DecodeT2Adr(MCInst &Inst, uint32_t Insn,
4310 uint64_t Address, const void *Decoder) {
4311 unsigned sign1 = fieldFromInstruction32(Insn, 21, 1);
4312 unsigned sign2 = fieldFromInstruction32(Insn, 23, 1);
4313 if (sign1 != sign2) return MCDisassembler::Fail;
4315 unsigned Val = fieldFromInstruction32(Insn, 0, 8);
4316 Val |= fieldFromInstruction32(Insn, 12, 3) << 8;
4317 Val |= fieldFromInstruction32(Insn, 26, 1) << 11;
4319 Inst.addOperand(MCOperand::CreateImm(SignExtend32<13>(Val)));
4321 return MCDisassembler::Success;
4324 static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, uint32_t Val,
4326 const void *Decoder) {
4327 DecodeStatus S = MCDisassembler::Success;
4329 // Shift of "asr #32" is not allowed in Thumb2 mode.
4330 if (Val == 0x20) S = MCDisassembler::SoftFail;
4331 Inst.addOperand(MCOperand::CreateImm(Val));
4335 static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn,
4336 uint64_t Address, const void *Decoder) {
4337 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
4338 unsigned Rt2 = fieldFromInstruction32(Insn, 0, 4);
4339 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
4340 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
4343 return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
4345 DecodeStatus S = MCDisassembler::Success;
4347 if (Rt == Rn || Rn == Rt2)
4348 S = MCDisassembler::SoftFail;
4350 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
4351 return MCDisassembler::Fail;
4352 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder)))
4353 return MCDisassembler::Fail;
4354 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
4355 return MCDisassembler::Fail;
4356 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4357 return MCDisassembler::Fail;
4362 static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn,
4363 uint64_t Address, const void *Decoder) {
4364 unsigned Vd = (fieldFromInstruction32(Insn, 12, 4) << 0);
4365 Vd |= (fieldFromInstruction32(Insn, 22, 1) << 4);
4366 unsigned Vm = (fieldFromInstruction32(Insn, 0, 4) << 0);
4367 Vm |= (fieldFromInstruction32(Insn, 5, 1) << 4);
4368 unsigned imm = fieldFromInstruction32(Insn, 16, 6);
4369 unsigned cmode = fieldFromInstruction32(Insn, 8, 4);
4371 DecodeStatus S = MCDisassembler::Success;
4373 // VMOVv2f32 is ambiguous with these decodings.
4374 if (!(imm & 0x38) && cmode == 0xF) {
4375 Inst.setOpcode(ARM::VMOVv2f32);
4376 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder);
4379 if (!(imm & 0x20)) Check(S, MCDisassembler::SoftFail);
4381 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
4382 return MCDisassembler::Fail;
4383 if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder)))
4384 return MCDisassembler::Fail;
4385 Inst.addOperand(MCOperand::CreateImm(64 - imm));
4390 static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn,
4391 uint64_t Address, const void *Decoder) {
4392 unsigned Vd = (fieldFromInstruction32(Insn, 12, 4) << 0);
4393 Vd |= (fieldFromInstruction32(Insn, 22, 1) << 4);
4394 unsigned Vm = (fieldFromInstruction32(Insn, 0, 4) << 0);
4395 Vm |= (fieldFromInstruction32(Insn, 5, 1) << 4);
4396 unsigned imm = fieldFromInstruction32(Insn, 16, 6);
4397 unsigned cmode = fieldFromInstruction32(Insn, 8, 4);
4399 DecodeStatus S = MCDisassembler::Success;
4401 // VMOVv4f32 is ambiguous with these decodings.
4402 if (!(imm & 0x38) && cmode == 0xF) {
4403 Inst.setOpcode(ARM::VMOVv4f32);
4404 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder);
4407 if (!(imm & 0x20)) Check(S, MCDisassembler::SoftFail);
4409 if (!Check(S, DecodeQPRRegisterClass(Inst, Vd, Address, Decoder)))
4410 return MCDisassembler::Fail;
4411 if (!Check(S, DecodeQPRRegisterClass(Inst, Vm, Address, Decoder)))
4412 return MCDisassembler::Fail;
4413 Inst.addOperand(MCOperand::CreateImm(64 - imm));
4418 static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val,
4419 uint64_t Address, const void *Decoder) {
4420 DecodeStatus S = MCDisassembler::Success;
4422 unsigned Rn = fieldFromInstruction32(Val, 16, 4);
4423 unsigned Rt = fieldFromInstruction32(Val, 12, 4);
4424 unsigned Rm = fieldFromInstruction32(Val, 0, 4);
4425 Rm |= (fieldFromInstruction32(Val, 23, 1) << 4);
4426 unsigned Cond = fieldFromInstruction32(Val, 28, 4);
4428 if (fieldFromInstruction32(Val, 8, 4) != 0 || Rn == Rt)
4429 S = MCDisassembler::SoftFail;
4431 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
4432 return MCDisassembler::Fail;
4433 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
4434 return MCDisassembler::Fail;
4435 if (!Check(S, DecodeAddrMode7Operand(Inst, Rn, Address, Decoder)))
4436 return MCDisassembler::Fail;
4437 if (!Check(S, DecodePostIdxReg(Inst, Rm, Address, Decoder)))
4438 return MCDisassembler::Fail;
4439 if (!Check(S, DecodePredicateOperand(Inst, Cond, Address, Decoder)))
4440 return MCDisassembler::Fail;
4445 static DecodeStatus DecodeMRRC2(llvm::MCInst &Inst, unsigned Val,
4446 uint64_t Address, const void *Decoder) {
4448 DecodeStatus S = MCDisassembler::Success;
4450 unsigned CRm = fieldFromInstruction32(Val, 0, 4);
4451 unsigned opc1 = fieldFromInstruction32(Val, 4, 4);
4452 unsigned cop = fieldFromInstruction32(Val, 8, 4);
4453 unsigned Rt = fieldFromInstruction32(Val, 12, 4);
4454 unsigned Rt2 = fieldFromInstruction32(Val, 16, 4);
4456 if ((cop & ~0x1) == 0xa)
4457 return MCDisassembler::Fail;
4460 S = MCDisassembler::SoftFail;
4462 Inst.addOperand(MCOperand::CreateImm(cop));
4463 Inst.addOperand(MCOperand::CreateImm(opc1));
4464 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
4465 return MCDisassembler::Fail;
4466 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder)))
4467 return MCDisassembler::Fail;
4468 Inst.addOperand(MCOperand::CreateImm(CRm));