1 //===-- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA --------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #define DEBUG_TYPE "arm-disassembler"
13 #include "ARMSubtarget.h"
14 #include "MCTargetDesc/ARMAddressingModes.h"
15 #include "MCTargetDesc/ARMMCExpr.h"
16 #include "MCTargetDesc/ARMBaseInfo.h"
17 #include "llvm/MC/EDInstInfo.h"
18 #include "llvm/MC/MCInst.h"
19 #include "llvm/MC/MCInstrDesc.h"
20 #include "llvm/MC/MCExpr.h"
21 #include "llvm/MC/MCContext.h"
22 #include "llvm/MC/MCDisassembler.h"
23 #include "llvm/Support/Debug.h"
24 #include "llvm/Support/MemoryObject.h"
25 #include "llvm/Support/ErrorHandling.h"
26 #include "llvm/Support/TargetRegistry.h"
27 #include "llvm/Support/raw_ostream.h"
31 typedef MCDisassembler::DecodeStatus DecodeStatus;
34 /// ARMDisassembler - ARM disassembler for all ARM platforms.
35 class ARMDisassembler : public MCDisassembler {
37 /// Constructor - Initializes the disassembler.
39 ARMDisassembler(const MCSubtargetInfo &STI) :
46 /// getInstruction - See MCDisassembler.
47 DecodeStatus getInstruction(MCInst &instr,
49 const MemoryObject ®ion,
52 raw_ostream &cStream) const;
54 /// getEDInfo - See MCDisassembler.
55 const EDInstInfo *getEDInfo() const;
59 /// ThumbDisassembler - Thumb disassembler for all Thumb platforms.
60 class ThumbDisassembler : public MCDisassembler {
62 /// Constructor - Initializes the disassembler.
64 ThumbDisassembler(const MCSubtargetInfo &STI) :
68 ~ThumbDisassembler() {
71 /// getInstruction - See MCDisassembler.
72 DecodeStatus getInstruction(MCInst &instr,
74 const MemoryObject ®ion,
77 raw_ostream &cStream) const;
79 /// getEDInfo - See MCDisassembler.
80 const EDInstInfo *getEDInfo() const;
82 mutable std::vector<unsigned> ITBlock;
83 DecodeStatus AddThumbPredicate(MCInst&) const;
84 void UpdateThumbVFPPredicate(MCInst&) const;
88 static bool Check(DecodeStatus &Out, DecodeStatus In) {
90 case MCDisassembler::Success:
91 // Out stays the same.
93 case MCDisassembler::SoftFail:
96 case MCDisassembler::Fail:
100 llvm_unreachable("Invalid DecodeStatus!");
104 // Forward declare these because the autogenerated code will reference them.
105 // Definitions are further down.
106 static DecodeStatus DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
107 uint64_t Address, const void *Decoder);
108 static DecodeStatus DecodeGPRnopcRegisterClass(llvm::MCInst &Inst,
109 unsigned RegNo, uint64_t Address,
110 const void *Decoder);
111 static DecodeStatus DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
112 uint64_t Address, const void *Decoder);
113 static DecodeStatus DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
114 uint64_t Address, const void *Decoder);
115 static DecodeStatus DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
116 uint64_t Address, const void *Decoder);
117 static DecodeStatus DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
118 uint64_t Address, const void *Decoder);
119 static DecodeStatus DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
120 uint64_t Address, const void *Decoder);
121 static DecodeStatus DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
122 uint64_t Address, const void *Decoder);
123 static DecodeStatus DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst,
126 const void *Decoder);
127 static DecodeStatus DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
128 uint64_t Address, const void *Decoder);
129 static DecodeStatus DecodeDPairRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
130 uint64_t Address, const void *Decoder);
131 static DecodeStatus DecodeDPairSpacedRegisterClass(llvm::MCInst &Inst,
132 unsigned RegNo, uint64_t Address,
133 const void *Decoder);
135 static DecodeStatus DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val,
136 uint64_t Address, const void *Decoder);
137 static DecodeStatus DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val,
138 uint64_t Address, const void *Decoder);
139 static DecodeStatus DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val,
140 uint64_t Address, const void *Decoder);
141 static DecodeStatus DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val,
142 uint64_t Address, const void *Decoder);
143 static DecodeStatus DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned Val,
144 uint64_t Address, const void *Decoder);
145 static DecodeStatus DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned Val,
146 uint64_t Address, const void *Decoder);
148 static DecodeStatus DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Insn,
149 uint64_t Address, const void *Decoder);
150 static DecodeStatus DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn,
151 uint64_t Address, const void *Decoder);
152 static DecodeStatus DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst,
155 const void *Decoder);
156 static DecodeStatus DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Insn,
157 uint64_t Address, const void *Decoder);
158 static DecodeStatus DecodeAddrMode3Instruction(llvm::MCInst &Inst,unsigned Insn,
159 uint64_t Address, const void *Decoder);
160 static DecodeStatus DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Insn,
161 uint64_t Address, const void *Decoder);
162 static DecodeStatus DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Insn,
163 uint64_t Address, const void *Decoder);
165 static DecodeStatus DecodeMemMultipleWritebackInstruction(llvm::MCInst & Inst,
168 const void *Decoder);
169 static DecodeStatus DecodeT2MOVTWInstruction(llvm::MCInst &Inst, unsigned Insn,
170 uint64_t Address, const void *Decoder);
171 static DecodeStatus DecodeArmMOVTWInstruction(llvm::MCInst &Inst, unsigned Insn,
172 uint64_t Address, const void *Decoder);
173 static DecodeStatus DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn,
174 uint64_t Address, const void *Decoder);
175 static DecodeStatus DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn,
176 uint64_t Address, const void *Decoder);
177 static DecodeStatus DecodeT2CPSInstruction(llvm::MCInst &Inst, unsigned Insn,
178 uint64_t Address, const void *Decoder);
179 static DecodeStatus DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val,
180 uint64_t Address, const void *Decoder);
181 static DecodeStatus DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val,
182 uint64_t Address, const void *Decoder);
183 static DecodeStatus DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val,
184 uint64_t Address, const void *Decoder);
185 static DecodeStatus DecodeBranchImmInstruction(llvm::MCInst &Inst,unsigned Insn,
186 uint64_t Address, const void *Decoder);
187 static DecodeStatus DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val,
188 uint64_t Address, const void *Decoder);
189 static DecodeStatus DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Val,
190 uint64_t Address, const void *Decoder);
191 static DecodeStatus DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Val,
192 uint64_t Address, const void *Decoder);
193 static DecodeStatus DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Val,
194 uint64_t Address, const void *Decoder);
195 static DecodeStatus DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Val,
196 uint64_t Address, const void *Decoder);
197 static DecodeStatus DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Val,
198 uint64_t Address, const void *Decoder);
199 static DecodeStatus DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Val,
200 uint64_t Address, const void *Decoder);
201 static DecodeStatus DecodeNEONModImmInstruction(llvm::MCInst &Inst,unsigned Val,
202 uint64_t Address, const void *Decoder);
203 static DecodeStatus DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned Val,
204 uint64_t Address, const void *Decoder);
205 static DecodeStatus DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned Val,
206 uint64_t Address, const void *Decoder);
207 static DecodeStatus DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned Val,
208 uint64_t Address, const void *Decoder);
209 static DecodeStatus DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned Val,
210 uint64_t Address, const void *Decoder);
211 static DecodeStatus DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned Val,
212 uint64_t Address, const void *Decoder);
213 static DecodeStatus DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn,
214 uint64_t Address, const void *Decoder);
215 static DecodeStatus DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn,
216 uint64_t Address, const void *Decoder);
217 static DecodeStatus DecodeCoprocessor(llvm::MCInst &Inst, unsigned Insn,
218 uint64_t Address, const void *Decoder);
219 static DecodeStatus DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Insn,
220 uint64_t Address, const void *Decoder);
221 static DecodeStatus DecodeMSRMask(llvm::MCInst &Inst, unsigned Insn,
222 uint64_t Address, const void *Decoder);
223 static DecodeStatus DecodeDoubleRegLoad(llvm::MCInst &Inst, unsigned Insn,
224 uint64_t Address, const void *Decoder);
225 static DecodeStatus DecodeDoubleRegStore(llvm::MCInst &Inst, unsigned Insn,
226 uint64_t Address, const void *Decoder);
227 static DecodeStatus DecodeLDRPreImm(llvm::MCInst &Inst, unsigned Insn,
228 uint64_t Address, const void *Decoder);
229 static DecodeStatus DecodeLDRPreReg(llvm::MCInst &Inst, unsigned Insn,
230 uint64_t Address, const void *Decoder);
231 static DecodeStatus DecodeSTRPreImm(llvm::MCInst &Inst, unsigned Insn,
232 uint64_t Address, const void *Decoder);
233 static DecodeStatus DecodeSTRPreReg(llvm::MCInst &Inst, unsigned Insn,
234 uint64_t Address, const void *Decoder);
235 static DecodeStatus DecodeVLD1LN(llvm::MCInst &Inst, unsigned Insn,
236 uint64_t Address, const void *Decoder);
237 static DecodeStatus DecodeVLD2LN(llvm::MCInst &Inst, unsigned Insn,
238 uint64_t Address, const void *Decoder);
239 static DecodeStatus DecodeVLD3LN(llvm::MCInst &Inst, unsigned Insn,
240 uint64_t Address, const void *Decoder);
241 static DecodeStatus DecodeVLD4LN(llvm::MCInst &Inst, unsigned Insn,
242 uint64_t Address, const void *Decoder);
243 static DecodeStatus DecodeVST1LN(llvm::MCInst &Inst, unsigned Insn,
244 uint64_t Address, const void *Decoder);
245 static DecodeStatus DecodeVST2LN(llvm::MCInst &Inst, unsigned Insn,
246 uint64_t Address, const void *Decoder);
247 static DecodeStatus DecodeVST3LN(llvm::MCInst &Inst, unsigned Insn,
248 uint64_t Address, const void *Decoder);
249 static DecodeStatus DecodeVST4LN(llvm::MCInst &Inst, unsigned Insn,
250 uint64_t Address, const void *Decoder);
251 static DecodeStatus DecodeVMOVSRR(llvm::MCInst &Inst, unsigned Insn,
252 uint64_t Address, const void *Decoder);
253 static DecodeStatus DecodeVMOVRRS(llvm::MCInst &Inst, unsigned Insn,
254 uint64_t Address, const void *Decoder);
255 static DecodeStatus DecodeSwap(llvm::MCInst &Inst, unsigned Insn,
256 uint64_t Address, const void *Decoder);
257 static DecodeStatus DecodeVCVTD(llvm::MCInst &Inst, unsigned Insn,
258 uint64_t Address, const void *Decoder);
259 static DecodeStatus DecodeVCVTQ(llvm::MCInst &Inst, unsigned Insn,
260 uint64_t Address, const void *Decoder);
263 static DecodeStatus DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn,
264 uint64_t Address, const void *Decoder);
265 static DecodeStatus DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val,
266 uint64_t Address, const void *Decoder);
267 static DecodeStatus DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val,
268 uint64_t Address, const void *Decoder);
269 static DecodeStatus DecodeThumbCmpBROperand(llvm::MCInst &Inst, unsigned Val,
270 uint64_t Address, const void *Decoder);
271 static DecodeStatus DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned Val,
272 uint64_t Address, const void *Decoder);
273 static DecodeStatus DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned Val,
274 uint64_t Address, const void *Decoder);
275 static DecodeStatus DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned Val,
276 uint64_t Address, const void *Decoder);
277 static DecodeStatus DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val,
278 uint64_t Address, const void *Decoder);
279 static DecodeStatus DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned Val,
280 uint64_t Address, const void *Decoder);
281 static DecodeStatus DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Val,
282 uint64_t Address, const void *Decoder);
283 static DecodeStatus DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val,
284 uint64_t Address, const void *Decoder);
285 static DecodeStatus DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned Val,
286 uint64_t Address, const void *Decoder);
287 static DecodeStatus DecodeT2AddrModeImm0_1020s4(llvm::MCInst &Inst,unsigned Val,
288 uint64_t Address, const void *Decoder);
289 static DecodeStatus DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val,
290 uint64_t Address, const void *Decoder);
291 static DecodeStatus DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val,
292 uint64_t Address, const void *Decoder);
293 static DecodeStatus DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Val,
294 uint64_t Address, const void *Decoder);
295 static DecodeStatus DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn,
296 uint64_t Address, const void *Decoder);
297 static DecodeStatus DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn,
298 uint64_t Address, const void *Decoder);
299 static DecodeStatus DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Insn,
300 uint64_t Address, const void *Decoder);
301 static DecodeStatus DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val,
302 uint64_t Address, const void *Decoder);
303 static DecodeStatus DecodeThumbTableBranch(llvm::MCInst &Inst, unsigned Val,
304 uint64_t Address, const void *Decoder);
305 static DecodeStatus DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Val,
306 uint64_t Address, const void *Decoder);
307 static DecodeStatus DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val,
308 uint64_t Address, const void *Decoder);
309 static DecodeStatus DecodeThumbBCCTargetOperand(llvm::MCInst &Inst,unsigned Val,
310 uint64_t Address, const void *Decoder);
311 static DecodeStatus DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val,
312 uint64_t Address, const void *Decoder);
313 static DecodeStatus DecodeIT(llvm::MCInst &Inst, unsigned Val,
314 uint64_t Address, const void *Decoder);
315 static DecodeStatus DecodeT2LDRDPreInstruction(llvm::MCInst &Inst,unsigned Insn,
316 uint64_t Address, const void *Decoder);
317 static DecodeStatus DecodeT2STRDPreInstruction(llvm::MCInst &Inst,unsigned Insn,
318 uint64_t Address, const void *Decoder);
319 static DecodeStatus DecodeT2Adr(llvm::MCInst &Inst, unsigned Val,
320 uint64_t Address, const void *Decoder);
321 static DecodeStatus DecodeT2LdStPre(llvm::MCInst &Inst, unsigned Val,
322 uint64_t Address, const void *Decoder);
323 static DecodeStatus DecodeT2ShifterImmOperand(llvm::MCInst &Inst, unsigned Val,
324 uint64_t Address, const void *Decoder);
328 #include "ARMGenDisassemblerTables.inc"
329 #include "ARMGenInstrInfo.inc"
330 #include "ARMGenEDInfo.inc"
332 static MCDisassembler *createARMDisassembler(const Target &T, const MCSubtargetInfo &STI) {
333 return new ARMDisassembler(STI);
336 static MCDisassembler *createThumbDisassembler(const Target &T, const MCSubtargetInfo &STI) {
337 return new ThumbDisassembler(STI);
340 const EDInstInfo *ARMDisassembler::getEDInfo() const {
344 const EDInstInfo *ThumbDisassembler::getEDInfo() const {
348 DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
349 const MemoryObject &Region,
352 raw_ostream &cs) const {
357 assert(!(STI.getFeatureBits() & ARM::ModeThumb) &&
358 "Asked to disassemble an ARM instruction but Subtarget is in Thumb mode!");
360 // We want to read exactly 4 bytes of data.
361 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) {
363 return MCDisassembler::Fail;
366 // Encoded as a small-endian 32-bit word in the stream.
367 uint32_t insn = (bytes[3] << 24) |
372 // Calling the auto-generated decoder function.
373 DecodeStatus result = decodeARMInstruction32(MI, insn, Address, this, STI);
374 if (result != MCDisassembler::Fail) {
379 // VFP and NEON instructions, similarly, are shared between ARM
382 result = decodeVFPInstruction32(MI, insn, Address, this, STI);
383 if (result != MCDisassembler::Fail) {
389 result = decodeNEONDataInstruction32(MI, insn, Address, this, STI);
390 if (result != MCDisassembler::Fail) {
392 // Add a fake predicate operand, because we share these instruction
393 // definitions with Thumb2 where these instructions are predicable.
394 if (!DecodePredicateOperand(MI, 0xE, Address, this))
395 return MCDisassembler::Fail;
400 result = decodeNEONLoadStoreInstruction32(MI, insn, Address, this, STI);
401 if (result != MCDisassembler::Fail) {
403 // Add a fake predicate operand, because we share these instruction
404 // definitions with Thumb2 where these instructions are predicable.
405 if (!DecodePredicateOperand(MI, 0xE, Address, this))
406 return MCDisassembler::Fail;
411 result = decodeNEONDupInstruction32(MI, insn, Address, this, STI);
412 if (result != MCDisassembler::Fail) {
414 // Add a fake predicate operand, because we share these instruction
415 // definitions with Thumb2 where these instructions are predicable.
416 if (!DecodePredicateOperand(MI, 0xE, Address, this))
417 return MCDisassembler::Fail;
424 return MCDisassembler::Fail;
428 extern const MCInstrDesc ARMInsts[];
431 /// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the
432 /// immediate Value in the MCInst. The immediate Value has had any PC
433 /// adjustment made by the caller. If the instruction is a branch instruction
434 /// then isBranch is true, else false. If the getOpInfo() function was set as
435 /// part of the setupForSymbolicDisassembly() call then that function is called
436 /// to get any symbolic information at the Address for this instruction. If
437 /// that returns non-zero then the symbolic information it returns is used to
438 /// create an MCExpr and that is added as an operand to the MCInst. If
439 /// getOpInfo() returns zero and isBranch is true then a symbol look up for
440 /// Value is done and if a symbol is found an MCExpr is created with that, else
441 /// an MCExpr with Value is created. This function returns true if it adds an
442 /// operand to the MCInst and false otherwise.
443 static bool tryAddingSymbolicOperand(uint64_t Address, int32_t Value,
444 bool isBranch, uint64_t InstSize,
445 MCInst &MI, const void *Decoder) {
446 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
447 LLVMOpInfoCallback getOpInfo = Dis->getLLVMOpInfoCallback();
448 struct LLVMOpInfo1 SymbolicOp;
449 memset(&SymbolicOp, '\0', sizeof(struct LLVMOpInfo1));
450 SymbolicOp.Value = Value;
451 void *DisInfo = Dis->getDisInfoBlock();
454 !getOpInfo(DisInfo, Address, 0 /* Offset */, InstSize, 1, &SymbolicOp)) {
455 // Clear SymbolicOp.Value from above and also all other fields.
456 memset(&SymbolicOp, '\0', sizeof(struct LLVMOpInfo1));
457 LLVMSymbolLookupCallback SymbolLookUp = Dis->getLLVMSymbolLookupCallback();
460 uint64_t ReferenceType;
462 ReferenceType = LLVMDisassembler_ReferenceType_In_Branch;
464 ReferenceType = LLVMDisassembler_ReferenceType_InOut_None;
465 const char *ReferenceName;
466 const char *Name = SymbolLookUp(DisInfo, Value, &ReferenceType, Address,
469 SymbolicOp.AddSymbol.Name = Name;
470 SymbolicOp.AddSymbol.Present = true;
472 // For branches always create an MCExpr so it gets printed as hex address.
474 SymbolicOp.Value = Value;
476 if(ReferenceType == LLVMDisassembler_ReferenceType_Out_SymbolStub)
477 (*Dis->CommentStream) << "symbol stub for: " << ReferenceName;
478 if (!Name && !isBranch)
482 MCContext *Ctx = Dis->getMCContext();
483 const MCExpr *Add = NULL;
484 if (SymbolicOp.AddSymbol.Present) {
485 if (SymbolicOp.AddSymbol.Name) {
486 StringRef Name(SymbolicOp.AddSymbol.Name);
487 MCSymbol *Sym = Ctx->GetOrCreateSymbol(Name);
488 Add = MCSymbolRefExpr::Create(Sym, *Ctx);
490 Add = MCConstantExpr::Create(SymbolicOp.AddSymbol.Value, *Ctx);
494 const MCExpr *Sub = NULL;
495 if (SymbolicOp.SubtractSymbol.Present) {
496 if (SymbolicOp.SubtractSymbol.Name) {
497 StringRef Name(SymbolicOp.SubtractSymbol.Name);
498 MCSymbol *Sym = Ctx->GetOrCreateSymbol(Name);
499 Sub = MCSymbolRefExpr::Create(Sym, *Ctx);
501 Sub = MCConstantExpr::Create(SymbolicOp.SubtractSymbol.Value, *Ctx);
505 const MCExpr *Off = NULL;
506 if (SymbolicOp.Value != 0)
507 Off = MCConstantExpr::Create(SymbolicOp.Value, *Ctx);
513 LHS = MCBinaryExpr::CreateSub(Add, Sub, *Ctx);
515 LHS = MCUnaryExpr::CreateMinus(Sub, *Ctx);
517 Expr = MCBinaryExpr::CreateAdd(LHS, Off, *Ctx);
522 Expr = MCBinaryExpr::CreateAdd(Add, Off, *Ctx);
529 Expr = MCConstantExpr::Create(0, *Ctx);
532 if (SymbolicOp.VariantKind == LLVMDisassembler_VariantKind_ARM_HI16)
533 MI.addOperand(MCOperand::CreateExpr(ARMMCExpr::CreateUpper16(Expr, *Ctx)));
534 else if (SymbolicOp.VariantKind == LLVMDisassembler_VariantKind_ARM_LO16)
535 MI.addOperand(MCOperand::CreateExpr(ARMMCExpr::CreateLower16(Expr, *Ctx)));
536 else if (SymbolicOp.VariantKind == LLVMDisassembler_VariantKind_None)
537 MI.addOperand(MCOperand::CreateExpr(Expr));
539 llvm_unreachable("bad SymbolicOp.VariantKind");
544 /// tryAddingPcLoadReferenceComment - trys to add a comment as to what is being
545 /// referenced by a load instruction with the base register that is the Pc.
546 /// These can often be values in a literal pool near the Address of the
547 /// instruction. The Address of the instruction and its immediate Value are
548 /// used as a possible literal pool entry. The SymbolLookUp call back will
549 /// return the name of a symbol referenced by the the literal pool's entry if
550 /// the referenced address is that of a symbol. Or it will return a pointer to
551 /// a literal 'C' string if the referenced address of the literal pool's entry
552 /// is an address into a section with 'C' string literals.
553 static void tryAddingPcLoadReferenceComment(uint64_t Address, int Value,
554 const void *Decoder) {
555 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
556 LLVMSymbolLookupCallback SymbolLookUp = Dis->getLLVMSymbolLookupCallback();
558 void *DisInfo = Dis->getDisInfoBlock();
559 uint64_t ReferenceType;
560 ReferenceType = LLVMDisassembler_ReferenceType_In_PCrel_Load;
561 const char *ReferenceName;
562 (void)SymbolLookUp(DisInfo, Value, &ReferenceType, Address, &ReferenceName);
563 if(ReferenceType == LLVMDisassembler_ReferenceType_Out_LitPool_SymAddr ||
564 ReferenceType == LLVMDisassembler_ReferenceType_Out_LitPool_CstrAddr)
565 (*Dis->CommentStream) << "literal pool for: " << ReferenceName;
569 // Thumb1 instructions don't have explicit S bits. Rather, they
570 // implicitly set CPSR. Since it's not represented in the encoding, the
571 // auto-generated decoder won't inject the CPSR operand. We need to fix
572 // that as a post-pass.
573 static void AddThumb1SBit(MCInst &MI, bool InITBlock) {
574 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
575 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
576 MCInst::iterator I = MI.begin();
577 for (unsigned i = 0; i < NumOps; ++i, ++I) {
578 if (I == MI.end()) break;
579 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) {
580 if (i > 0 && OpInfo[i-1].isPredicate()) continue;
581 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR));
586 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR));
589 // Most Thumb instructions don't have explicit predicates in the
590 // encoding, but rather get their predicates from IT context. We need
591 // to fix up the predicate operands using this context information as a
593 MCDisassembler::DecodeStatus
594 ThumbDisassembler::AddThumbPredicate(MCInst &MI) const {
595 MCDisassembler::DecodeStatus S = Success;
597 // A few instructions actually have predicates encoded in them. Don't
598 // try to overwrite it if we're seeing one of those.
599 switch (MI.getOpcode()) {
610 // Some instructions (mostly conditional branches) are not
611 // allowed in IT blocks.
612 if (!ITBlock.empty())
621 // Some instructions (mostly unconditional branches) can
622 // only appears at the end of, or outside of, an IT.
623 if (ITBlock.size() > 1)
630 // If we're in an IT block, base the predicate on that. Otherwise,
631 // assume a predicate of AL.
633 if (!ITBlock.empty()) {
641 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
642 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
643 MCInst::iterator I = MI.begin();
644 for (unsigned i = 0; i < NumOps; ++i, ++I) {
645 if (I == MI.end()) break;
646 if (OpInfo[i].isPredicate()) {
647 I = MI.insert(I, MCOperand::CreateImm(CC));
650 MI.insert(I, MCOperand::CreateReg(0));
652 MI.insert(I, MCOperand::CreateReg(ARM::CPSR));
657 I = MI.insert(I, MCOperand::CreateImm(CC));
660 MI.insert(I, MCOperand::CreateReg(0));
662 MI.insert(I, MCOperand::CreateReg(ARM::CPSR));
667 // Thumb VFP instructions are a special case. Because we share their
668 // encodings between ARM and Thumb modes, and they are predicable in ARM
669 // mode, the auto-generated decoder will give them an (incorrect)
670 // predicate operand. We need to rewrite these operands based on the IT
671 // context as a post-pass.
672 void ThumbDisassembler::UpdateThumbVFPPredicate(MCInst &MI) const {
674 if (!ITBlock.empty()) {
680 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
681 MCInst::iterator I = MI.begin();
682 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
683 for (unsigned i = 0; i < NumOps; ++i, ++I) {
684 if (OpInfo[i].isPredicate() ) {
690 I->setReg(ARM::CPSR);
696 DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
697 const MemoryObject &Region,
700 raw_ostream &cs) const {
705 assert((STI.getFeatureBits() & ARM::ModeThumb) &&
706 "Asked to disassemble in Thumb mode but Subtarget is in ARM mode!");
708 // We want to read exactly 2 bytes of data.
709 if (Region.readBytes(Address, 2, (uint8_t*)bytes, NULL) == -1) {
711 return MCDisassembler::Fail;
714 uint16_t insn16 = (bytes[1] << 8) | bytes[0];
715 DecodeStatus result = decodeThumbInstruction16(MI, insn16, Address, this, STI);
716 if (result != MCDisassembler::Fail) {
718 Check(result, AddThumbPredicate(MI));
723 result = decodeThumbSBitInstruction16(MI, insn16, Address, this, STI);
726 bool InITBlock = !ITBlock.empty();
727 Check(result, AddThumbPredicate(MI));
728 AddThumb1SBit(MI, InITBlock);
733 result = decodeThumb2Instruction16(MI, insn16, Address, this, STI);
734 if (result != MCDisassembler::Fail) {
737 // Nested IT blocks are UNPREDICTABLE. Must be checked before we add
738 // the Thumb predicate.
739 if (MI.getOpcode() == ARM::t2IT && !ITBlock.empty())
740 result = MCDisassembler::SoftFail;
742 Check(result, AddThumbPredicate(MI));
744 // If we find an IT instruction, we need to parse its condition
745 // code and mask operands so that we can apply them correctly
746 // to the subsequent instructions.
747 if (MI.getOpcode() == ARM::t2IT) {
749 // (3 - the number of trailing zeros) is the number of then / else.
750 unsigned firstcond = MI.getOperand(0).getImm();
751 unsigned Mask = MI.getOperand(1).getImm();
752 unsigned CondBit0 = Mask >> 4 & 1;
753 unsigned NumTZ = CountTrailingZeros_32(Mask);
754 assert(NumTZ <= 3 && "Invalid IT mask!");
755 for (unsigned Pos = 3, e = NumTZ; Pos > e; --Pos) {
756 bool T = ((Mask >> Pos) & 1) == CondBit0;
758 ITBlock.insert(ITBlock.begin(), firstcond);
760 ITBlock.insert(ITBlock.begin(), firstcond ^ 1);
763 ITBlock.push_back(firstcond);
769 // We want to read exactly 4 bytes of data.
770 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) {
772 return MCDisassembler::Fail;
775 uint32_t insn32 = (bytes[3] << 8) |
780 result = decodeThumbInstruction32(MI, insn32, Address, this, STI);
781 if (result != MCDisassembler::Fail) {
783 bool InITBlock = ITBlock.size();
784 Check(result, AddThumbPredicate(MI));
785 AddThumb1SBit(MI, InITBlock);
790 result = decodeThumb2Instruction32(MI, insn32, Address, this, STI);
791 if (result != MCDisassembler::Fail) {
793 Check(result, AddThumbPredicate(MI));
798 result = decodeVFPInstruction32(MI, insn32, Address, this, STI);
799 if (result != MCDisassembler::Fail) {
801 UpdateThumbVFPPredicate(MI);
806 result = decodeNEONDupInstruction32(MI, insn32, Address, this, STI);
807 if (result != MCDisassembler::Fail) {
809 Check(result, AddThumbPredicate(MI));
813 if (fieldFromInstruction32(insn32, 24, 8) == 0xF9) {
815 uint32_t NEONLdStInsn = insn32;
816 NEONLdStInsn &= 0xF0FFFFFF;
817 NEONLdStInsn |= 0x04000000;
818 result = decodeNEONLoadStoreInstruction32(MI, NEONLdStInsn, Address, this, STI);
819 if (result != MCDisassembler::Fail) {
821 Check(result, AddThumbPredicate(MI));
826 if (fieldFromInstruction32(insn32, 24, 4) == 0xF) {
828 uint32_t NEONDataInsn = insn32;
829 NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24
830 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24
831 NEONDataInsn |= 0x12000000; // Set bits 28 and 25
832 result = decodeNEONDataInstruction32(MI, NEONDataInsn, Address, this, STI);
833 if (result != MCDisassembler::Fail) {
835 Check(result, AddThumbPredicate(MI));
841 return MCDisassembler::Fail;
845 extern "C" void LLVMInitializeARMDisassembler() {
846 TargetRegistry::RegisterMCDisassembler(TheARMTarget,
847 createARMDisassembler);
848 TargetRegistry::RegisterMCDisassembler(TheThumbTarget,
849 createThumbDisassembler);
852 static const unsigned GPRDecoderTable[] = {
853 ARM::R0, ARM::R1, ARM::R2, ARM::R3,
854 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
855 ARM::R8, ARM::R9, ARM::R10, ARM::R11,
856 ARM::R12, ARM::SP, ARM::LR, ARM::PC
859 static DecodeStatus DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
860 uint64_t Address, const void *Decoder) {
862 return MCDisassembler::Fail;
864 unsigned Register = GPRDecoderTable[RegNo];
865 Inst.addOperand(MCOperand::CreateReg(Register));
866 return MCDisassembler::Success;
870 DecodeGPRnopcRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
871 uint64_t Address, const void *Decoder) {
872 if (RegNo == 15) return MCDisassembler::Fail;
873 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
876 static DecodeStatus DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
877 uint64_t Address, const void *Decoder) {
879 return MCDisassembler::Fail;
880 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
883 static DecodeStatus DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
884 uint64_t Address, const void *Decoder) {
885 unsigned Register = 0;
906 return MCDisassembler::Fail;
909 Inst.addOperand(MCOperand::CreateReg(Register));
910 return MCDisassembler::Success;
913 static DecodeStatus DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
914 uint64_t Address, const void *Decoder) {
915 if (RegNo == 13 || RegNo == 15) return MCDisassembler::Fail;
916 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
919 static const unsigned SPRDecoderTable[] = {
920 ARM::S0, ARM::S1, ARM::S2, ARM::S3,
921 ARM::S4, ARM::S5, ARM::S6, ARM::S7,
922 ARM::S8, ARM::S9, ARM::S10, ARM::S11,
923 ARM::S12, ARM::S13, ARM::S14, ARM::S15,
924 ARM::S16, ARM::S17, ARM::S18, ARM::S19,
925 ARM::S20, ARM::S21, ARM::S22, ARM::S23,
926 ARM::S24, ARM::S25, ARM::S26, ARM::S27,
927 ARM::S28, ARM::S29, ARM::S30, ARM::S31
930 static DecodeStatus DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
931 uint64_t Address, const void *Decoder) {
933 return MCDisassembler::Fail;
935 unsigned Register = SPRDecoderTable[RegNo];
936 Inst.addOperand(MCOperand::CreateReg(Register));
937 return MCDisassembler::Success;
940 static const unsigned DPRDecoderTable[] = {
941 ARM::D0, ARM::D1, ARM::D2, ARM::D3,
942 ARM::D4, ARM::D5, ARM::D6, ARM::D7,
943 ARM::D8, ARM::D9, ARM::D10, ARM::D11,
944 ARM::D12, ARM::D13, ARM::D14, ARM::D15,
945 ARM::D16, ARM::D17, ARM::D18, ARM::D19,
946 ARM::D20, ARM::D21, ARM::D22, ARM::D23,
947 ARM::D24, ARM::D25, ARM::D26, ARM::D27,
948 ARM::D28, ARM::D29, ARM::D30, ARM::D31
951 static DecodeStatus DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
952 uint64_t Address, const void *Decoder) {
954 return MCDisassembler::Fail;
956 unsigned Register = DPRDecoderTable[RegNo];
957 Inst.addOperand(MCOperand::CreateReg(Register));
958 return MCDisassembler::Success;
961 static DecodeStatus DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
962 uint64_t Address, const void *Decoder) {
964 return MCDisassembler::Fail;
965 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
969 DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
970 uint64_t Address, const void *Decoder) {
972 return MCDisassembler::Fail;
973 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
976 static const unsigned QPRDecoderTable[] = {
977 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3,
978 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7,
979 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11,
980 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15
984 static DecodeStatus DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
985 uint64_t Address, const void *Decoder) {
987 return MCDisassembler::Fail;
990 unsigned Register = QPRDecoderTable[RegNo];
991 Inst.addOperand(MCOperand::CreateReg(Register));
992 return MCDisassembler::Success;
995 static const unsigned DPairDecoderTable[] = {
996 ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6,
997 ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12,
998 ARM::Q6, ARM::D13_D14, ARM::Q7, ARM::D15_D16, ARM::Q8, ARM::D17_D18,
999 ARM::Q9, ARM::D19_D20, ARM::Q10, ARM::D21_D22, ARM::Q11, ARM::D23_D24,
1000 ARM::Q12, ARM::D25_D26, ARM::Q13, ARM::D27_D28, ARM::Q14, ARM::D29_D30,
1004 static DecodeStatus DecodeDPairRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
1005 uint64_t Address, const void *Decoder) {
1007 return MCDisassembler::Fail;
1009 unsigned Register = DPairDecoderTable[RegNo];
1010 Inst.addOperand(MCOperand::CreateReg(Register));
1011 return MCDisassembler::Success;
1014 static const unsigned DPairSpacedDecoderTable[] = {
1015 ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5,
1016 ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9,
1017 ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13,
1018 ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17,
1019 ARM::D16_D18, ARM::D17_D19, ARM::D18_D20, ARM::D19_D21,
1020 ARM::D20_D22, ARM::D21_D23, ARM::D22_D24, ARM::D23_D25,
1021 ARM::D24_D26, ARM::D25_D27, ARM::D26_D28, ARM::D27_D29,
1022 ARM::D28_D30, ARM::D29_D31
1025 static DecodeStatus DecodeDPairSpacedRegisterClass(llvm::MCInst &Inst,
1028 const void *Decoder) {
1030 return MCDisassembler::Fail;
1032 unsigned Register = DPairSpacedDecoderTable[RegNo];
1033 Inst.addOperand(MCOperand::CreateReg(Register));
1034 return MCDisassembler::Success;
1037 static DecodeStatus DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val,
1038 uint64_t Address, const void *Decoder) {
1039 if (Val == 0xF) return MCDisassembler::Fail;
1040 // AL predicate is not allowed on Thumb1 branches.
1041 if (Inst.getOpcode() == ARM::tBcc && Val == 0xE)
1042 return MCDisassembler::Fail;
1043 Inst.addOperand(MCOperand::CreateImm(Val));
1044 if (Val == ARMCC::AL) {
1045 Inst.addOperand(MCOperand::CreateReg(0));
1047 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1048 return MCDisassembler::Success;
1051 static DecodeStatus DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val,
1052 uint64_t Address, const void *Decoder) {
1054 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1056 Inst.addOperand(MCOperand::CreateReg(0));
1057 return MCDisassembler::Success;
1060 static DecodeStatus DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val,
1061 uint64_t Address, const void *Decoder) {
1062 uint32_t imm = Val & 0xFF;
1063 uint32_t rot = (Val & 0xF00) >> 7;
1064 uint32_t rot_imm = (imm >> rot) | (imm << ((32-rot) & 0x1F));
1065 Inst.addOperand(MCOperand::CreateImm(rot_imm));
1066 return MCDisassembler::Success;
1069 static DecodeStatus DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Val,
1070 uint64_t Address, const void *Decoder) {
1071 DecodeStatus S = MCDisassembler::Success;
1073 unsigned Rm = fieldFromInstruction32(Val, 0, 4);
1074 unsigned type = fieldFromInstruction32(Val, 5, 2);
1075 unsigned imm = fieldFromInstruction32(Val, 7, 5);
1077 // Register-immediate
1078 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1079 return MCDisassembler::Fail;
1081 ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
1084 Shift = ARM_AM::lsl;
1087 Shift = ARM_AM::lsr;
1090 Shift = ARM_AM::asr;
1093 Shift = ARM_AM::ror;
1097 if (Shift == ARM_AM::ror && imm == 0)
1098 Shift = ARM_AM::rrx;
1100 unsigned Op = Shift | (imm << 3);
1101 Inst.addOperand(MCOperand::CreateImm(Op));
1106 static DecodeStatus DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Val,
1107 uint64_t Address, const void *Decoder) {
1108 DecodeStatus S = MCDisassembler::Success;
1110 unsigned Rm = fieldFromInstruction32(Val, 0, 4);
1111 unsigned type = fieldFromInstruction32(Val, 5, 2);
1112 unsigned Rs = fieldFromInstruction32(Val, 8, 4);
1114 // Register-register
1115 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1116 return MCDisassembler::Fail;
1117 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder)))
1118 return MCDisassembler::Fail;
1120 ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
1123 Shift = ARM_AM::lsl;
1126 Shift = ARM_AM::lsr;
1129 Shift = ARM_AM::asr;
1132 Shift = ARM_AM::ror;
1136 Inst.addOperand(MCOperand::CreateImm(Shift));
1141 static DecodeStatus DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val,
1142 uint64_t Address, const void *Decoder) {
1143 DecodeStatus S = MCDisassembler::Success;
1145 bool writebackLoad = false;
1146 unsigned writebackReg = 0;
1147 switch (Inst.getOpcode()) {
1150 case ARM::LDMIA_UPD:
1151 case ARM::LDMDB_UPD:
1152 case ARM::LDMIB_UPD:
1153 case ARM::LDMDA_UPD:
1154 case ARM::t2LDMIA_UPD:
1155 case ARM::t2LDMDB_UPD:
1156 writebackLoad = true;
1157 writebackReg = Inst.getOperand(0).getReg();
1161 // Empty register lists are not allowed.
1162 if (CountPopulation_32(Val) == 0) return MCDisassembler::Fail;
1163 for (unsigned i = 0; i < 16; ++i) {
1164 if (Val & (1 << i)) {
1165 if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder)))
1166 return MCDisassembler::Fail;
1167 // Writeback not allowed if Rn is in the target list.
1168 if (writebackLoad && writebackReg == Inst.end()[-1].getReg())
1169 Check(S, MCDisassembler::SoftFail);
1176 static DecodeStatus DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned Val,
1177 uint64_t Address, const void *Decoder) {
1178 DecodeStatus S = MCDisassembler::Success;
1180 unsigned Vd = fieldFromInstruction32(Val, 8, 4);
1181 unsigned regs = Val & 0xFF;
1183 if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder)))
1184 return MCDisassembler::Fail;
1185 for (unsigned i = 0; i < (regs - 1); ++i) {
1186 if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder)))
1187 return MCDisassembler::Fail;
1193 static DecodeStatus DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned Val,
1194 uint64_t Address, const void *Decoder) {
1195 DecodeStatus S = MCDisassembler::Success;
1197 unsigned Vd = fieldFromInstruction32(Val, 8, 4);
1198 unsigned regs = (Val & 0xFF) / 2;
1200 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
1201 return MCDisassembler::Fail;
1202 for (unsigned i = 0; i < (regs - 1); ++i) {
1203 if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder)))
1204 return MCDisassembler::Fail;
1210 static DecodeStatus DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Val,
1211 uint64_t Address, const void *Decoder) {
1212 // This operand encodes a mask of contiguous zeros between a specified MSB
1213 // and LSB. To decode it, we create the mask of all bits MSB-and-lower,
1214 // the mask of all bits LSB-and-lower, and then xor them to create
1215 // the mask of that's all ones on [msb, lsb]. Finally we not it to
1216 // create the final mask.
1217 unsigned msb = fieldFromInstruction32(Val, 5, 5);
1218 unsigned lsb = fieldFromInstruction32(Val, 0, 5);
1220 DecodeStatus S = MCDisassembler::Success;
1221 if (lsb > msb) Check(S, MCDisassembler::SoftFail);
1223 uint32_t msb_mask = 0xFFFFFFFF;
1224 if (msb != 31) msb_mask = (1U << (msb+1)) - 1;
1225 uint32_t lsb_mask = (1U << lsb) - 1;
1227 Inst.addOperand(MCOperand::CreateImm(~(msb_mask ^ lsb_mask)));
1231 static DecodeStatus DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn,
1232 uint64_t Address, const void *Decoder) {
1233 DecodeStatus S = MCDisassembler::Success;
1235 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1236 unsigned CRd = fieldFromInstruction32(Insn, 12, 4);
1237 unsigned coproc = fieldFromInstruction32(Insn, 8, 4);
1238 unsigned imm = fieldFromInstruction32(Insn, 0, 8);
1239 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1240 unsigned U = fieldFromInstruction32(Insn, 23, 1);
1242 switch (Inst.getOpcode()) {
1243 case ARM::LDC_OFFSET:
1246 case ARM::LDC_OPTION:
1247 case ARM::LDCL_OFFSET:
1249 case ARM::LDCL_POST:
1250 case ARM::LDCL_OPTION:
1251 case ARM::STC_OFFSET:
1254 case ARM::STC_OPTION:
1255 case ARM::STCL_OFFSET:
1257 case ARM::STCL_POST:
1258 case ARM::STCL_OPTION:
1259 case ARM::t2LDC_OFFSET:
1260 case ARM::t2LDC_PRE:
1261 case ARM::t2LDC_POST:
1262 case ARM::t2LDC_OPTION:
1263 case ARM::t2LDCL_OFFSET:
1264 case ARM::t2LDCL_PRE:
1265 case ARM::t2LDCL_POST:
1266 case ARM::t2LDCL_OPTION:
1267 case ARM::t2STC_OFFSET:
1268 case ARM::t2STC_PRE:
1269 case ARM::t2STC_POST:
1270 case ARM::t2STC_OPTION:
1271 case ARM::t2STCL_OFFSET:
1272 case ARM::t2STCL_PRE:
1273 case ARM::t2STCL_POST:
1274 case ARM::t2STCL_OPTION:
1275 if (coproc == 0xA || coproc == 0xB)
1276 return MCDisassembler::Fail;
1282 Inst.addOperand(MCOperand::CreateImm(coproc));
1283 Inst.addOperand(MCOperand::CreateImm(CRd));
1284 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1285 return MCDisassembler::Fail;
1287 switch (Inst.getOpcode()) {
1288 case ARM::t2LDC2_OFFSET:
1289 case ARM::t2LDC2L_OFFSET:
1290 case ARM::t2LDC2_PRE:
1291 case ARM::t2LDC2L_PRE:
1292 case ARM::t2STC2_OFFSET:
1293 case ARM::t2STC2L_OFFSET:
1294 case ARM::t2STC2_PRE:
1295 case ARM::t2STC2L_PRE:
1296 case ARM::LDC2_OFFSET:
1297 case ARM::LDC2L_OFFSET:
1299 case ARM::LDC2L_PRE:
1300 case ARM::STC2_OFFSET:
1301 case ARM::STC2L_OFFSET:
1303 case ARM::STC2L_PRE:
1304 case ARM::t2LDC_OFFSET:
1305 case ARM::t2LDCL_OFFSET:
1306 case ARM::t2LDC_PRE:
1307 case ARM::t2LDCL_PRE:
1308 case ARM::t2STC_OFFSET:
1309 case ARM::t2STCL_OFFSET:
1310 case ARM::t2STC_PRE:
1311 case ARM::t2STCL_PRE:
1312 case ARM::LDC_OFFSET:
1313 case ARM::LDCL_OFFSET:
1316 case ARM::STC_OFFSET:
1317 case ARM::STCL_OFFSET:
1320 imm = ARM_AM::getAM5Opc(U ? ARM_AM::add : ARM_AM::sub, imm);
1321 Inst.addOperand(MCOperand::CreateImm(imm));
1323 case ARM::t2LDC2_POST:
1324 case ARM::t2LDC2L_POST:
1325 case ARM::t2STC2_POST:
1326 case ARM::t2STC2L_POST:
1327 case ARM::LDC2_POST:
1328 case ARM::LDC2L_POST:
1329 case ARM::STC2_POST:
1330 case ARM::STC2L_POST:
1331 case ARM::t2LDC_POST:
1332 case ARM::t2LDCL_POST:
1333 case ARM::t2STC_POST:
1334 case ARM::t2STCL_POST:
1336 case ARM::LDCL_POST:
1338 case ARM::STCL_POST:
1342 // The 'option' variant doesn't encode 'U' in the immediate since
1343 // the immediate is unsigned [0,255].
1344 Inst.addOperand(MCOperand::CreateImm(imm));
1348 switch (Inst.getOpcode()) {
1349 case ARM::LDC_OFFSET:
1352 case ARM::LDC_OPTION:
1353 case ARM::LDCL_OFFSET:
1355 case ARM::LDCL_POST:
1356 case ARM::LDCL_OPTION:
1357 case ARM::STC_OFFSET:
1360 case ARM::STC_OPTION:
1361 case ARM::STCL_OFFSET:
1363 case ARM::STCL_POST:
1364 case ARM::STCL_OPTION:
1365 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1366 return MCDisassembler::Fail;
1376 DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, unsigned Insn,
1377 uint64_t Address, const void *Decoder) {
1378 DecodeStatus S = MCDisassembler::Success;
1380 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1381 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
1382 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
1383 unsigned imm = fieldFromInstruction32(Insn, 0, 12);
1384 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1385 unsigned reg = fieldFromInstruction32(Insn, 25, 1);
1386 unsigned P = fieldFromInstruction32(Insn, 24, 1);
1387 unsigned W = fieldFromInstruction32(Insn, 21, 1);
1389 // On stores, the writeback operand precedes Rt.
1390 switch (Inst.getOpcode()) {
1391 case ARM::STR_POST_IMM:
1392 case ARM::STR_POST_REG:
1393 case ARM::STRB_POST_IMM:
1394 case ARM::STRB_POST_REG:
1395 case ARM::STRT_POST_REG:
1396 case ARM::STRT_POST_IMM:
1397 case ARM::STRBT_POST_REG:
1398 case ARM::STRBT_POST_IMM:
1399 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1400 return MCDisassembler::Fail;
1406 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
1407 return MCDisassembler::Fail;
1409 // On loads, the writeback operand comes after Rt.
1410 switch (Inst.getOpcode()) {
1411 case ARM::LDR_POST_IMM:
1412 case ARM::LDR_POST_REG:
1413 case ARM::LDRB_POST_IMM:
1414 case ARM::LDRB_POST_REG:
1415 case ARM::LDRBT_POST_REG:
1416 case ARM::LDRBT_POST_IMM:
1417 case ARM::LDRT_POST_REG:
1418 case ARM::LDRT_POST_IMM:
1419 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1420 return MCDisassembler::Fail;
1426 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1427 return MCDisassembler::Fail;
1429 ARM_AM::AddrOpc Op = ARM_AM::add;
1430 if (!fieldFromInstruction32(Insn, 23, 1))
1433 bool writeback = (P == 0) || (W == 1);
1434 unsigned idx_mode = 0;
1436 idx_mode = ARMII::IndexModePre;
1437 else if (!P && writeback)
1438 idx_mode = ARMII::IndexModePost;
1440 if (writeback && (Rn == 15 || Rn == Rt))
1441 S = MCDisassembler::SoftFail; // UNPREDICTABLE
1444 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1445 return MCDisassembler::Fail;
1446 ARM_AM::ShiftOpc Opc = ARM_AM::lsl;
1447 switch( fieldFromInstruction32(Insn, 5, 2)) {
1461 return MCDisassembler::Fail;
1463 unsigned amt = fieldFromInstruction32(Insn, 7, 5);
1464 unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode);
1466 Inst.addOperand(MCOperand::CreateImm(imm));
1468 Inst.addOperand(MCOperand::CreateReg(0));
1469 unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode);
1470 Inst.addOperand(MCOperand::CreateImm(tmp));
1473 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1474 return MCDisassembler::Fail;
1479 static DecodeStatus DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Val,
1480 uint64_t Address, const void *Decoder) {
1481 DecodeStatus S = MCDisassembler::Success;
1483 unsigned Rn = fieldFromInstruction32(Val, 13, 4);
1484 unsigned Rm = fieldFromInstruction32(Val, 0, 4);
1485 unsigned type = fieldFromInstruction32(Val, 5, 2);
1486 unsigned imm = fieldFromInstruction32(Val, 7, 5);
1487 unsigned U = fieldFromInstruction32(Val, 12, 1);
1489 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl;
1505 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1506 return MCDisassembler::Fail;
1507 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1508 return MCDisassembler::Fail;
1511 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp);
1513 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp);
1514 Inst.addOperand(MCOperand::CreateImm(shift));
1520 DecodeAddrMode3Instruction(llvm::MCInst &Inst, unsigned Insn,
1521 uint64_t Address, const void *Decoder) {
1522 DecodeStatus S = MCDisassembler::Success;
1524 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
1525 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1526 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
1527 unsigned type = fieldFromInstruction32(Insn, 22, 1);
1528 unsigned imm = fieldFromInstruction32(Insn, 8, 4);
1529 unsigned U = ((~fieldFromInstruction32(Insn, 23, 1)) & 1) << 8;
1530 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1531 unsigned W = fieldFromInstruction32(Insn, 21, 1);
1532 unsigned P = fieldFromInstruction32(Insn, 24, 1);
1534 bool writeback = (W == 1) | (P == 0);
1536 // For {LD,ST}RD, Rt must be even, else undefined.
1537 switch (Inst.getOpcode()) {
1540 case ARM::STRD_POST:
1543 case ARM::LDRD_POST:
1544 if (Rt & 0x1) return MCDisassembler::Fail;
1550 if (writeback) { // Writeback
1552 U |= ARMII::IndexModePre << 9;
1554 U |= ARMII::IndexModePost << 9;
1556 // On stores, the writeback operand precedes Rt.
1557 switch (Inst.getOpcode()) {
1560 case ARM::STRD_POST:
1563 case ARM::STRH_POST:
1564 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1565 return MCDisassembler::Fail;
1572 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
1573 return MCDisassembler::Fail;
1574 switch (Inst.getOpcode()) {
1577 case ARM::STRD_POST:
1580 case ARM::LDRD_POST:
1581 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
1582 return MCDisassembler::Fail;
1589 // On loads, the writeback operand comes after Rt.
1590 switch (Inst.getOpcode()) {
1593 case ARM::LDRD_POST:
1596 case ARM::LDRH_POST:
1598 case ARM::LDRSH_PRE:
1599 case ARM::LDRSH_POST:
1601 case ARM::LDRSB_PRE:
1602 case ARM::LDRSB_POST:
1605 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1606 return MCDisassembler::Fail;
1613 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1614 return MCDisassembler::Fail;
1617 Inst.addOperand(MCOperand::CreateReg(0));
1618 Inst.addOperand(MCOperand::CreateImm(U | (imm << 4) | Rm));
1620 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1621 return MCDisassembler::Fail;
1622 Inst.addOperand(MCOperand::CreateImm(U));
1625 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1626 return MCDisassembler::Fail;
1631 static DecodeStatus DecodeRFEInstruction(llvm::MCInst &Inst, unsigned Insn,
1632 uint64_t Address, const void *Decoder) {
1633 DecodeStatus S = MCDisassembler::Success;
1635 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1636 unsigned mode = fieldFromInstruction32(Insn, 23, 2);
1653 Inst.addOperand(MCOperand::CreateImm(mode));
1654 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1655 return MCDisassembler::Fail;
1660 static DecodeStatus DecodeMemMultipleWritebackInstruction(llvm::MCInst &Inst,
1662 uint64_t Address, const void *Decoder) {
1663 DecodeStatus S = MCDisassembler::Success;
1665 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1666 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1667 unsigned reglist = fieldFromInstruction32(Insn, 0, 16);
1670 switch (Inst.getOpcode()) {
1672 Inst.setOpcode(ARM::RFEDA);
1674 case ARM::LDMDA_UPD:
1675 Inst.setOpcode(ARM::RFEDA_UPD);
1678 Inst.setOpcode(ARM::RFEDB);
1680 case ARM::LDMDB_UPD:
1681 Inst.setOpcode(ARM::RFEDB_UPD);
1684 Inst.setOpcode(ARM::RFEIA);
1686 case ARM::LDMIA_UPD:
1687 Inst.setOpcode(ARM::RFEIA_UPD);
1690 Inst.setOpcode(ARM::RFEIB);
1692 case ARM::LDMIB_UPD:
1693 Inst.setOpcode(ARM::RFEIB_UPD);
1696 Inst.setOpcode(ARM::SRSDA);
1698 case ARM::STMDA_UPD:
1699 Inst.setOpcode(ARM::SRSDA_UPD);
1702 Inst.setOpcode(ARM::SRSDB);
1704 case ARM::STMDB_UPD:
1705 Inst.setOpcode(ARM::SRSDB_UPD);
1708 Inst.setOpcode(ARM::SRSIA);
1710 case ARM::STMIA_UPD:
1711 Inst.setOpcode(ARM::SRSIA_UPD);
1714 Inst.setOpcode(ARM::SRSIB);
1716 case ARM::STMIB_UPD:
1717 Inst.setOpcode(ARM::SRSIB_UPD);
1720 if (!Check(S, MCDisassembler::Fail)) return MCDisassembler::Fail;
1723 // For stores (which become SRS's, the only operand is the mode.
1724 if (fieldFromInstruction32(Insn, 20, 1) == 0) {
1726 MCOperand::CreateImm(fieldFromInstruction32(Insn, 0, 4)));
1730 return DecodeRFEInstruction(Inst, Insn, Address, Decoder);
1733 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1734 return MCDisassembler::Fail;
1735 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1736 return MCDisassembler::Fail; // Tied
1737 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1738 return MCDisassembler::Fail;
1739 if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder)))
1740 return MCDisassembler::Fail;
1745 static DecodeStatus DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn,
1746 uint64_t Address, const void *Decoder) {
1747 unsigned imod = fieldFromInstruction32(Insn, 18, 2);
1748 unsigned M = fieldFromInstruction32(Insn, 17, 1);
1749 unsigned iflags = fieldFromInstruction32(Insn, 6, 3);
1750 unsigned mode = fieldFromInstruction32(Insn, 0, 5);
1752 DecodeStatus S = MCDisassembler::Success;
1754 // imod == '01' --> UNPREDICTABLE
1755 // NOTE: Even though this is technically UNPREDICTABLE, we choose to
1756 // return failure here. The '01' imod value is unprintable, so there's
1757 // nothing useful we could do even if we returned UNPREDICTABLE.
1759 if (imod == 1) return MCDisassembler::Fail;
1762 Inst.setOpcode(ARM::CPS3p);
1763 Inst.addOperand(MCOperand::CreateImm(imod));
1764 Inst.addOperand(MCOperand::CreateImm(iflags));
1765 Inst.addOperand(MCOperand::CreateImm(mode));
1766 } else if (imod && !M) {
1767 Inst.setOpcode(ARM::CPS2p);
1768 Inst.addOperand(MCOperand::CreateImm(imod));
1769 Inst.addOperand(MCOperand::CreateImm(iflags));
1770 if (mode) S = MCDisassembler::SoftFail;
1771 } else if (!imod && M) {
1772 Inst.setOpcode(ARM::CPS1p);
1773 Inst.addOperand(MCOperand::CreateImm(mode));
1774 if (iflags) S = MCDisassembler::SoftFail;
1776 // imod == '00' && M == '0' --> UNPREDICTABLE
1777 Inst.setOpcode(ARM::CPS1p);
1778 Inst.addOperand(MCOperand::CreateImm(mode));
1779 S = MCDisassembler::SoftFail;
1785 static DecodeStatus DecodeT2CPSInstruction(llvm::MCInst &Inst, unsigned Insn,
1786 uint64_t Address, const void *Decoder) {
1787 unsigned imod = fieldFromInstruction32(Insn, 9, 2);
1788 unsigned M = fieldFromInstruction32(Insn, 8, 1);
1789 unsigned iflags = fieldFromInstruction32(Insn, 5, 3);
1790 unsigned mode = fieldFromInstruction32(Insn, 0, 5);
1792 DecodeStatus S = MCDisassembler::Success;
1794 // imod == '01' --> UNPREDICTABLE
1795 // NOTE: Even though this is technically UNPREDICTABLE, we choose to
1796 // return failure here. The '01' imod value is unprintable, so there's
1797 // nothing useful we could do even if we returned UNPREDICTABLE.
1799 if (imod == 1) return MCDisassembler::Fail;
1802 Inst.setOpcode(ARM::t2CPS3p);
1803 Inst.addOperand(MCOperand::CreateImm(imod));
1804 Inst.addOperand(MCOperand::CreateImm(iflags));
1805 Inst.addOperand(MCOperand::CreateImm(mode));
1806 } else if (imod && !M) {
1807 Inst.setOpcode(ARM::t2CPS2p);
1808 Inst.addOperand(MCOperand::CreateImm(imod));
1809 Inst.addOperand(MCOperand::CreateImm(iflags));
1810 if (mode) S = MCDisassembler::SoftFail;
1811 } else if (!imod && M) {
1812 Inst.setOpcode(ARM::t2CPS1p);
1813 Inst.addOperand(MCOperand::CreateImm(mode));
1814 if (iflags) S = MCDisassembler::SoftFail;
1816 // imod == '00' && M == '0' --> UNPREDICTABLE
1817 Inst.setOpcode(ARM::t2CPS1p);
1818 Inst.addOperand(MCOperand::CreateImm(mode));
1819 S = MCDisassembler::SoftFail;
1825 static DecodeStatus DecodeT2MOVTWInstruction(llvm::MCInst &Inst, unsigned Insn,
1826 uint64_t Address, const void *Decoder) {
1827 DecodeStatus S = MCDisassembler::Success;
1829 unsigned Rd = fieldFromInstruction32(Insn, 8, 4);
1832 imm |= (fieldFromInstruction32(Insn, 0, 8) << 0);
1833 imm |= (fieldFromInstruction32(Insn, 12, 3) << 8);
1834 imm |= (fieldFromInstruction32(Insn, 16, 4) << 12);
1835 imm |= (fieldFromInstruction32(Insn, 26, 1) << 11);
1837 if (Inst.getOpcode() == ARM::t2MOVTi16)
1838 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
1839 return MCDisassembler::Fail;
1840 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
1841 return MCDisassembler::Fail;
1843 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder))
1844 Inst.addOperand(MCOperand::CreateImm(imm));
1849 static DecodeStatus DecodeArmMOVTWInstruction(llvm::MCInst &Inst, unsigned Insn,
1850 uint64_t Address, const void *Decoder) {
1851 DecodeStatus S = MCDisassembler::Success;
1853 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
1854 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1857 imm |= (fieldFromInstruction32(Insn, 0, 12) << 0);
1858 imm |= (fieldFromInstruction32(Insn, 16, 4) << 12);
1860 if (Inst.getOpcode() == ARM::MOVTi16)
1861 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
1862 return MCDisassembler::Fail;
1863 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
1864 return MCDisassembler::Fail;
1866 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder))
1867 Inst.addOperand(MCOperand::CreateImm(imm));
1869 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1870 return MCDisassembler::Fail;
1875 static DecodeStatus DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn,
1876 uint64_t Address, const void *Decoder) {
1877 DecodeStatus S = MCDisassembler::Success;
1879 unsigned Rd = fieldFromInstruction32(Insn, 16, 4);
1880 unsigned Rn = fieldFromInstruction32(Insn, 0, 4);
1881 unsigned Rm = fieldFromInstruction32(Insn, 8, 4);
1882 unsigned Ra = fieldFromInstruction32(Insn, 12, 4);
1883 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1886 return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
1888 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
1889 return MCDisassembler::Fail;
1890 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
1891 return MCDisassembler::Fail;
1892 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1893 return MCDisassembler::Fail;
1894 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder)))
1895 return MCDisassembler::Fail;
1897 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1898 return MCDisassembler::Fail;
1903 static DecodeStatus DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val,
1904 uint64_t Address, const void *Decoder) {
1905 DecodeStatus S = MCDisassembler::Success;
1907 unsigned add = fieldFromInstruction32(Val, 12, 1);
1908 unsigned imm = fieldFromInstruction32(Val, 0, 12);
1909 unsigned Rn = fieldFromInstruction32(Val, 13, 4);
1911 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1912 return MCDisassembler::Fail;
1914 if (!add) imm *= -1;
1915 if (imm == 0 && !add) imm = INT32_MIN;
1916 Inst.addOperand(MCOperand::CreateImm(imm));
1918 tryAddingPcLoadReferenceComment(Address, Address + imm + 8, Decoder);
1923 static DecodeStatus DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val,
1924 uint64_t Address, const void *Decoder) {
1925 DecodeStatus S = MCDisassembler::Success;
1927 unsigned Rn = fieldFromInstruction32(Val, 9, 4);
1928 unsigned U = fieldFromInstruction32(Val, 8, 1);
1929 unsigned imm = fieldFromInstruction32(Val, 0, 8);
1931 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1932 return MCDisassembler::Fail;
1935 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::add, imm)));
1937 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm)));
1942 static DecodeStatus DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val,
1943 uint64_t Address, const void *Decoder) {
1944 return DecodeGPRRegisterClass(Inst, Val, Address, Decoder);
1948 DecodeBranchImmInstruction(llvm::MCInst &Inst, unsigned Insn,
1949 uint64_t Address, const void *Decoder) {
1950 DecodeStatus S = MCDisassembler::Success;
1952 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1953 unsigned imm = fieldFromInstruction32(Insn, 0, 24) << 2;
1956 Inst.setOpcode(ARM::BLXi);
1957 imm |= fieldFromInstruction32(Insn, 24, 1) << 1;
1958 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8,
1959 true, 4, Inst, Decoder))
1960 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm)));
1964 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8,
1965 true, 4, Inst, Decoder))
1966 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm)));
1967 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1968 return MCDisassembler::Fail;
1974 static DecodeStatus DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val,
1975 uint64_t Address, const void *Decoder) {
1976 DecodeStatus S = MCDisassembler::Success;
1978 unsigned Rm = fieldFromInstruction32(Val, 0, 4);
1979 unsigned align = fieldFromInstruction32(Val, 4, 2);
1981 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1982 return MCDisassembler::Fail;
1984 Inst.addOperand(MCOperand::CreateImm(0));
1986 Inst.addOperand(MCOperand::CreateImm(4 << align));
1991 static DecodeStatus DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Insn,
1992 uint64_t Address, const void *Decoder) {
1993 DecodeStatus S = MCDisassembler::Success;
1995 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
1996 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
1997 unsigned wb = fieldFromInstruction32(Insn, 16, 4);
1998 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1999 Rn |= fieldFromInstruction32(Insn, 4, 2) << 4;
2000 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2002 // First output register
2003 switch (Inst.getOpcode()) {
2004 case ARM::VLD1q16: case ARM::VLD1q32: case ARM::VLD1q64: case ARM::VLD1q8:
2005 case ARM::VLD1q16wb_fixed: case ARM::VLD1q16wb_register:
2006 case ARM::VLD1q32wb_fixed: case ARM::VLD1q32wb_register:
2007 case ARM::VLD1q64wb_fixed: case ARM::VLD1q64wb_register:
2008 case ARM::VLD1q8wb_fixed: case ARM::VLD1q8wb_register:
2009 case ARM::VLD2d16: case ARM::VLD2d32: case ARM::VLD2d8:
2010 case ARM::VLD2d16wb_fixed: case ARM::VLD2d16wb_register:
2011 case ARM::VLD2d32wb_fixed: case ARM::VLD2d32wb_register:
2012 case ARM::VLD2d8wb_fixed: case ARM::VLD2d8wb_register:
2013 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2014 return MCDisassembler::Fail;
2019 case ARM::VLD2b16wb_fixed:
2020 case ARM::VLD2b16wb_register:
2021 case ARM::VLD2b32wb_fixed:
2022 case ARM::VLD2b32wb_register:
2023 case ARM::VLD2b8wb_fixed:
2024 case ARM::VLD2b8wb_register:
2025 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
2026 return MCDisassembler::Fail;
2029 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2030 return MCDisassembler::Fail;
2033 // Second output register
2034 switch (Inst.getOpcode()) {
2038 case ARM::VLD3d8_UPD:
2039 case ARM::VLD3d16_UPD:
2040 case ARM::VLD3d32_UPD:
2044 case ARM::VLD4d8_UPD:
2045 case ARM::VLD4d16_UPD:
2046 case ARM::VLD4d32_UPD:
2047 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
2048 return MCDisassembler::Fail;
2053 case ARM::VLD3q8_UPD:
2054 case ARM::VLD3q16_UPD:
2055 case ARM::VLD3q32_UPD:
2059 case ARM::VLD4q8_UPD:
2060 case ARM::VLD4q16_UPD:
2061 case ARM::VLD4q32_UPD:
2062 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2063 return MCDisassembler::Fail;
2068 // Third output register
2069 switch(Inst.getOpcode()) {
2073 case ARM::VLD3d8_UPD:
2074 case ARM::VLD3d16_UPD:
2075 case ARM::VLD3d32_UPD:
2079 case ARM::VLD4d8_UPD:
2080 case ARM::VLD4d16_UPD:
2081 case ARM::VLD4d32_UPD:
2082 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2083 return MCDisassembler::Fail;
2088 case ARM::VLD3q8_UPD:
2089 case ARM::VLD3q16_UPD:
2090 case ARM::VLD3q32_UPD:
2094 case ARM::VLD4q8_UPD:
2095 case ARM::VLD4q16_UPD:
2096 case ARM::VLD4q32_UPD:
2097 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
2098 return MCDisassembler::Fail;
2104 // Fourth output register
2105 switch (Inst.getOpcode()) {
2109 case ARM::VLD4d8_UPD:
2110 case ARM::VLD4d16_UPD:
2111 case ARM::VLD4d32_UPD:
2112 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
2113 return MCDisassembler::Fail;
2118 case ARM::VLD4q8_UPD:
2119 case ARM::VLD4q16_UPD:
2120 case ARM::VLD4q32_UPD:
2121 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
2122 return MCDisassembler::Fail;
2128 // Writeback operand
2129 switch (Inst.getOpcode()) {
2130 case ARM::VLD1d8wb_fixed:
2131 case ARM::VLD1d16wb_fixed:
2132 case ARM::VLD1d32wb_fixed:
2133 case ARM::VLD1d64wb_fixed:
2134 case ARM::VLD1d8wb_register:
2135 case ARM::VLD1d16wb_register:
2136 case ARM::VLD1d32wb_register:
2137 case ARM::VLD1d64wb_register:
2138 case ARM::VLD1q8wb_fixed:
2139 case ARM::VLD1q16wb_fixed:
2140 case ARM::VLD1q32wb_fixed:
2141 case ARM::VLD1q64wb_fixed:
2142 case ARM::VLD1q8wb_register:
2143 case ARM::VLD1q16wb_register:
2144 case ARM::VLD1q32wb_register:
2145 case ARM::VLD1q64wb_register:
2146 case ARM::VLD1d8Twb_fixed:
2147 case ARM::VLD1d8Twb_register:
2148 case ARM::VLD1d16Twb_fixed:
2149 case ARM::VLD1d16Twb_register:
2150 case ARM::VLD1d32Twb_fixed:
2151 case ARM::VLD1d32Twb_register:
2152 case ARM::VLD1d64Twb_fixed:
2153 case ARM::VLD1d64Twb_register:
2154 case ARM::VLD1d8Qwb_fixed:
2155 case ARM::VLD1d8Qwb_register:
2156 case ARM::VLD1d16Qwb_fixed:
2157 case ARM::VLD1d16Qwb_register:
2158 case ARM::VLD1d32Qwb_fixed:
2159 case ARM::VLD1d32Qwb_register:
2160 case ARM::VLD1d64Qwb_fixed:
2161 case ARM::VLD1d64Qwb_register:
2162 case ARM::VLD2d8wb_fixed:
2163 case ARM::VLD2d16wb_fixed:
2164 case ARM::VLD2d32wb_fixed:
2165 case ARM::VLD2q8wb_fixed:
2166 case ARM::VLD2q16wb_fixed:
2167 case ARM::VLD2q32wb_fixed:
2168 case ARM::VLD2d8wb_register:
2169 case ARM::VLD2d16wb_register:
2170 case ARM::VLD2d32wb_register:
2171 case ARM::VLD2q8wb_register:
2172 case ARM::VLD2q16wb_register:
2173 case ARM::VLD2q32wb_register:
2174 case ARM::VLD2b8wb_fixed:
2175 case ARM::VLD2b16wb_fixed:
2176 case ARM::VLD2b32wb_fixed:
2177 case ARM::VLD2b8wb_register:
2178 case ARM::VLD2b16wb_register:
2179 case ARM::VLD2b32wb_register:
2180 case ARM::VLD3d8_UPD:
2181 case ARM::VLD3d16_UPD:
2182 case ARM::VLD3d32_UPD:
2183 case ARM::VLD3q8_UPD:
2184 case ARM::VLD3q16_UPD:
2185 case ARM::VLD3q32_UPD:
2186 case ARM::VLD4d8_UPD:
2187 case ARM::VLD4d16_UPD:
2188 case ARM::VLD4d32_UPD:
2189 case ARM::VLD4q8_UPD:
2190 case ARM::VLD4q16_UPD:
2191 case ARM::VLD4q32_UPD:
2192 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
2193 return MCDisassembler::Fail;
2199 // AddrMode6 Base (register+alignment)
2200 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
2201 return MCDisassembler::Fail;
2203 // AddrMode6 Offset (register)
2204 switch (Inst.getOpcode()) {
2206 // The below have been updated to have explicit am6offset split
2207 // between fixed and register offset. For those instructions not
2208 // yet updated, we need to add an additional reg0 operand for the
2211 // The fixed offset encodes as Rm == 0xd, so we check for that.
2213 Inst.addOperand(MCOperand::CreateReg(0));
2216 // Fall through to handle the register offset variant.
2217 case ARM::VLD1d8wb_fixed:
2218 case ARM::VLD1d16wb_fixed:
2219 case ARM::VLD1d32wb_fixed:
2220 case ARM::VLD1d64wb_fixed:
2221 case ARM::VLD1d8Twb_fixed:
2222 case ARM::VLD1d16Twb_fixed:
2223 case ARM::VLD1d32Twb_fixed:
2224 case ARM::VLD1d64Twb_fixed:
2225 case ARM::VLD1d8Qwb_fixed:
2226 case ARM::VLD1d16Qwb_fixed:
2227 case ARM::VLD1d32Qwb_fixed:
2228 case ARM::VLD1d64Qwb_fixed:
2229 case ARM::VLD1d8wb_register:
2230 case ARM::VLD1d16wb_register:
2231 case ARM::VLD1d32wb_register:
2232 case ARM::VLD1d64wb_register:
2233 case ARM::VLD1q8wb_fixed:
2234 case ARM::VLD1q16wb_fixed:
2235 case ARM::VLD1q32wb_fixed:
2236 case ARM::VLD1q64wb_fixed:
2237 case ARM::VLD1q8wb_register:
2238 case ARM::VLD1q16wb_register:
2239 case ARM::VLD1q32wb_register:
2240 case ARM::VLD1q64wb_register:
2241 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback
2242 // variant encodes Rm == 0xf. Anything else is a register offset post-
2243 // increment and we need to add the register operand to the instruction.
2244 if (Rm != 0xD && Rm != 0xF &&
2245 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2246 return MCDisassembler::Fail;
2253 static DecodeStatus DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Insn,
2254 uint64_t Address, const void *Decoder) {
2255 DecodeStatus S = MCDisassembler::Success;
2257 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2258 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2259 unsigned wb = fieldFromInstruction32(Insn, 16, 4);
2260 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2261 Rn |= fieldFromInstruction32(Insn, 4, 2) << 4;
2262 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2264 // Writeback Operand
2265 switch (Inst.getOpcode()) {
2266 case ARM::VST1d8wb_fixed:
2267 case ARM::VST1d16wb_fixed:
2268 case ARM::VST1d32wb_fixed:
2269 case ARM::VST1d64wb_fixed:
2270 case ARM::VST1d8wb_register:
2271 case ARM::VST1d16wb_register:
2272 case ARM::VST1d32wb_register:
2273 case ARM::VST1d64wb_register:
2274 case ARM::VST1q8wb_fixed:
2275 case ARM::VST1q16wb_fixed:
2276 case ARM::VST1q32wb_fixed:
2277 case ARM::VST1q64wb_fixed:
2278 case ARM::VST1q8wb_register:
2279 case ARM::VST1q16wb_register:
2280 case ARM::VST1q32wb_register:
2281 case ARM::VST1q64wb_register:
2282 case ARM::VST1d8Twb_fixed:
2283 case ARM::VST1d16Twb_fixed:
2284 case ARM::VST1d32Twb_fixed:
2285 case ARM::VST1d64Twb_fixed:
2286 case ARM::VST1d8Twb_register:
2287 case ARM::VST1d16Twb_register:
2288 case ARM::VST1d32Twb_register:
2289 case ARM::VST1d64Twb_register:
2290 case ARM::VST1d8Qwb_fixed:
2291 case ARM::VST1d16Qwb_fixed:
2292 case ARM::VST1d32Qwb_fixed:
2293 case ARM::VST1d64Qwb_fixed:
2294 case ARM::VST1d8Qwb_register:
2295 case ARM::VST1d16Qwb_register:
2296 case ARM::VST1d32Qwb_register:
2297 case ARM::VST1d64Qwb_register:
2298 case ARM::VST2d8wb_fixed:
2299 case ARM::VST2d16wb_fixed:
2300 case ARM::VST2d32wb_fixed:
2301 case ARM::VST2d8wb_register:
2302 case ARM::VST2d16wb_register:
2303 case ARM::VST2d32wb_register:
2304 case ARM::VST2q8wb_fixed:
2305 case ARM::VST2q16wb_fixed:
2306 case ARM::VST2q32wb_fixed:
2307 case ARM::VST2q8wb_register:
2308 case ARM::VST2q16wb_register:
2309 case ARM::VST2q32wb_register:
2310 case ARM::VST2b8wb_fixed:
2311 case ARM::VST2b16wb_fixed:
2312 case ARM::VST2b32wb_fixed:
2313 case ARM::VST2b8wb_register:
2314 case ARM::VST2b16wb_register:
2315 case ARM::VST2b32wb_register:
2316 case ARM::VST3d8_UPD:
2317 case ARM::VST3d16_UPD:
2318 case ARM::VST3d32_UPD:
2319 case ARM::VST3q8_UPD:
2320 case ARM::VST3q16_UPD:
2321 case ARM::VST3q32_UPD:
2322 case ARM::VST4d8_UPD:
2323 case ARM::VST4d16_UPD:
2324 case ARM::VST4d32_UPD:
2325 case ARM::VST4q8_UPD:
2326 case ARM::VST4q16_UPD:
2327 case ARM::VST4q32_UPD:
2328 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
2329 return MCDisassembler::Fail;
2335 // AddrMode6 Base (register+alignment)
2336 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
2337 return MCDisassembler::Fail;
2339 // AddrMode6 Offset (register)
2340 switch (Inst.getOpcode()) {
2343 Inst.addOperand(MCOperand::CreateReg(0));
2344 else if (Rm != 0xF) {
2345 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2346 return MCDisassembler::Fail;
2349 case ARM::VST1d8wb_fixed:
2350 case ARM::VST1d16wb_fixed:
2351 case ARM::VST1d32wb_fixed:
2352 case ARM::VST1d64wb_fixed:
2353 case ARM::VST1q8wb_fixed:
2354 case ARM::VST1q16wb_fixed:
2355 case ARM::VST1q32wb_fixed:
2356 case ARM::VST1q64wb_fixed:
2361 // First input register
2362 switch (Inst.getOpcode()) {
2367 case ARM::VST1q16wb_fixed:
2368 case ARM::VST1q16wb_register:
2369 case ARM::VST1q32wb_fixed:
2370 case ARM::VST1q32wb_register:
2371 case ARM::VST1q64wb_fixed:
2372 case ARM::VST1q64wb_register:
2373 case ARM::VST1q8wb_fixed:
2374 case ARM::VST1q8wb_register:
2378 case ARM::VST2d16wb_fixed:
2379 case ARM::VST2d16wb_register:
2380 case ARM::VST2d32wb_fixed:
2381 case ARM::VST2d32wb_register:
2382 case ARM::VST2d8wb_fixed:
2383 case ARM::VST2d8wb_register:
2384 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2385 return MCDisassembler::Fail;
2390 case ARM::VST2b16wb_fixed:
2391 case ARM::VST2b16wb_register:
2392 case ARM::VST2b32wb_fixed:
2393 case ARM::VST2b32wb_register:
2394 case ARM::VST2b8wb_fixed:
2395 case ARM::VST2b8wb_register:
2396 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
2397 return MCDisassembler::Fail;
2400 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2401 return MCDisassembler::Fail;
2404 // Second input register
2405 switch (Inst.getOpcode()) {
2409 case ARM::VST3d8_UPD:
2410 case ARM::VST3d16_UPD:
2411 case ARM::VST3d32_UPD:
2415 case ARM::VST4d8_UPD:
2416 case ARM::VST4d16_UPD:
2417 case ARM::VST4d32_UPD:
2418 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
2419 return MCDisassembler::Fail;
2424 case ARM::VST3q8_UPD:
2425 case ARM::VST3q16_UPD:
2426 case ARM::VST3q32_UPD:
2430 case ARM::VST4q8_UPD:
2431 case ARM::VST4q16_UPD:
2432 case ARM::VST4q32_UPD:
2433 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2434 return MCDisassembler::Fail;
2440 // Third input register
2441 switch (Inst.getOpcode()) {
2445 case ARM::VST3d8_UPD:
2446 case ARM::VST3d16_UPD:
2447 case ARM::VST3d32_UPD:
2451 case ARM::VST4d8_UPD:
2452 case ARM::VST4d16_UPD:
2453 case ARM::VST4d32_UPD:
2454 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2455 return MCDisassembler::Fail;
2460 case ARM::VST3q8_UPD:
2461 case ARM::VST3q16_UPD:
2462 case ARM::VST3q32_UPD:
2466 case ARM::VST4q8_UPD:
2467 case ARM::VST4q16_UPD:
2468 case ARM::VST4q32_UPD:
2469 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
2470 return MCDisassembler::Fail;
2476 // Fourth input register
2477 switch (Inst.getOpcode()) {
2481 case ARM::VST4d8_UPD:
2482 case ARM::VST4d16_UPD:
2483 case ARM::VST4d32_UPD:
2484 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
2485 return MCDisassembler::Fail;
2490 case ARM::VST4q8_UPD:
2491 case ARM::VST4q16_UPD:
2492 case ARM::VST4q32_UPD:
2493 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
2494 return MCDisassembler::Fail;
2503 static DecodeStatus DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Insn,
2504 uint64_t Address, const void *Decoder) {
2505 DecodeStatus S = MCDisassembler::Success;
2507 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2508 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2509 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2510 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2511 unsigned align = fieldFromInstruction32(Insn, 4, 1);
2512 unsigned size = fieldFromInstruction32(Insn, 6, 2);
2514 align *= (1 << size);
2516 switch (Inst.getOpcode()) {
2517 case ARM::VLD1DUPq16: case ARM::VLD1DUPq32: case ARM::VLD1DUPq8:
2518 case ARM::VLD1DUPq16wb_fixed: case ARM::VLD1DUPq16wb_register:
2519 case ARM::VLD1DUPq32wb_fixed: case ARM::VLD1DUPq32wb_register:
2520 case ARM::VLD1DUPq8wb_fixed: case ARM::VLD1DUPq8wb_register:
2521 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2522 return MCDisassembler::Fail;
2525 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2526 return MCDisassembler::Fail;
2530 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2531 return MCDisassembler::Fail;
2534 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2535 return MCDisassembler::Fail;
2536 Inst.addOperand(MCOperand::CreateImm(align));
2538 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback
2539 // variant encodes Rm == 0xf. Anything else is a register offset post-
2540 // increment and we need to add the register operand to the instruction.
2541 if (Rm != 0xD && Rm != 0xF &&
2542 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2543 return MCDisassembler::Fail;
2548 static DecodeStatus DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Insn,
2549 uint64_t Address, const void *Decoder) {
2550 DecodeStatus S = MCDisassembler::Success;
2552 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2553 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2554 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2555 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2556 unsigned align = fieldFromInstruction32(Insn, 4, 1);
2557 unsigned size = 1 << fieldFromInstruction32(Insn, 6, 2);
2558 unsigned pred = fieldFromInstruction32(Insn, 22, 4);
2561 switch (Inst.getOpcode()) {
2562 case ARM::VLD2DUPd16: case ARM::VLD2DUPd32: case ARM::VLD2DUPd8:
2563 case ARM::VLD2DUPd16wb_fixed: case ARM::VLD2DUPd16wb_register:
2564 case ARM::VLD2DUPd32wb_fixed: case ARM::VLD2DUPd32wb_register:
2565 case ARM::VLD2DUPd8wb_fixed: case ARM::VLD2DUPd8wb_register:
2566 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2567 return MCDisassembler::Fail;
2569 case ARM::VLD2DUPd16x2: case ARM::VLD2DUPd32x2: case ARM::VLD2DUPd8x2:
2570 case ARM::VLD2DUPd16x2wb_fixed: case ARM::VLD2DUPd16x2wb_register:
2571 case ARM::VLD2DUPd32x2wb_fixed: case ARM::VLD2DUPd32x2wb_register:
2572 case ARM::VLD2DUPd8x2wb_fixed: case ARM::VLD2DUPd8x2wb_register:
2573 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
2574 return MCDisassembler::Fail;
2577 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2578 return MCDisassembler::Fail;
2583 Inst.addOperand(MCOperand::CreateImm(0));
2585 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2586 return MCDisassembler::Fail;
2587 Inst.addOperand(MCOperand::CreateImm(align));
2590 Inst.addOperand(MCOperand::CreateReg(0));
2591 else if (Rm != 0xF) {
2592 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2593 return MCDisassembler::Fail;
2596 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2597 return MCDisassembler::Fail;
2602 static DecodeStatus DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Insn,
2603 uint64_t Address, const void *Decoder) {
2604 DecodeStatus S = MCDisassembler::Success;
2606 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2607 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2608 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2609 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2610 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1;
2612 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2613 return MCDisassembler::Fail;
2614 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
2615 return MCDisassembler::Fail;
2616 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
2617 return MCDisassembler::Fail;
2619 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2620 return MCDisassembler::Fail;
2623 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2624 return MCDisassembler::Fail;
2625 Inst.addOperand(MCOperand::CreateImm(0));
2628 Inst.addOperand(MCOperand::CreateReg(0));
2629 else if (Rm != 0xF) {
2630 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2631 return MCDisassembler::Fail;
2637 static DecodeStatus DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Insn,
2638 uint64_t Address, const void *Decoder) {
2639 DecodeStatus S = MCDisassembler::Success;
2641 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2642 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2643 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2644 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2645 unsigned size = fieldFromInstruction32(Insn, 6, 2);
2646 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1;
2647 unsigned align = fieldFromInstruction32(Insn, 4, 1);
2662 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2663 return MCDisassembler::Fail;
2664 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
2665 return MCDisassembler::Fail;
2666 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
2667 return MCDisassembler::Fail;
2668 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder)))
2669 return MCDisassembler::Fail;
2671 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2672 return MCDisassembler::Fail;
2675 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2676 return MCDisassembler::Fail;
2677 Inst.addOperand(MCOperand::CreateImm(align));
2680 Inst.addOperand(MCOperand::CreateReg(0));
2681 else if (Rm != 0xF) {
2682 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2683 return MCDisassembler::Fail;
2690 DecodeNEONModImmInstruction(llvm::MCInst &Inst, unsigned Insn,
2691 uint64_t Address, const void *Decoder) {
2692 DecodeStatus S = MCDisassembler::Success;
2694 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2695 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2696 unsigned imm = fieldFromInstruction32(Insn, 0, 4);
2697 imm |= fieldFromInstruction32(Insn, 16, 3) << 4;
2698 imm |= fieldFromInstruction32(Insn, 24, 1) << 7;
2699 imm |= fieldFromInstruction32(Insn, 8, 4) << 8;
2700 imm |= fieldFromInstruction32(Insn, 5, 1) << 12;
2701 unsigned Q = fieldFromInstruction32(Insn, 6, 1);
2704 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
2705 return MCDisassembler::Fail;
2707 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2708 return MCDisassembler::Fail;
2711 Inst.addOperand(MCOperand::CreateImm(imm));
2713 switch (Inst.getOpcode()) {
2714 case ARM::VORRiv4i16:
2715 case ARM::VORRiv2i32:
2716 case ARM::VBICiv4i16:
2717 case ARM::VBICiv2i32:
2718 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2719 return MCDisassembler::Fail;
2721 case ARM::VORRiv8i16:
2722 case ARM::VORRiv4i32:
2723 case ARM::VBICiv8i16:
2724 case ARM::VBICiv4i32:
2725 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
2726 return MCDisassembler::Fail;
2735 static DecodeStatus DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned Insn,
2736 uint64_t Address, const void *Decoder) {
2737 DecodeStatus S = MCDisassembler::Success;
2739 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2740 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2741 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2742 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4;
2743 unsigned size = fieldFromInstruction32(Insn, 18, 2);
2745 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
2746 return MCDisassembler::Fail;
2747 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
2748 return MCDisassembler::Fail;
2749 Inst.addOperand(MCOperand::CreateImm(8 << size));
2754 static DecodeStatus DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned Val,
2755 uint64_t Address, const void *Decoder) {
2756 Inst.addOperand(MCOperand::CreateImm(8 - Val));
2757 return MCDisassembler::Success;
2760 static DecodeStatus DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned Val,
2761 uint64_t Address, const void *Decoder) {
2762 Inst.addOperand(MCOperand::CreateImm(16 - Val));
2763 return MCDisassembler::Success;
2766 static DecodeStatus DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned Val,
2767 uint64_t Address, const void *Decoder) {
2768 Inst.addOperand(MCOperand::CreateImm(32 - Val));
2769 return MCDisassembler::Success;
2772 static DecodeStatus DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned Val,
2773 uint64_t Address, const void *Decoder) {
2774 Inst.addOperand(MCOperand::CreateImm(64 - Val));
2775 return MCDisassembler::Success;
2778 static DecodeStatus DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn,
2779 uint64_t Address, const void *Decoder) {
2780 DecodeStatus S = MCDisassembler::Success;
2782 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2783 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2784 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2785 Rn |= fieldFromInstruction32(Insn, 7, 1) << 4;
2786 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2787 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4;
2788 unsigned op = fieldFromInstruction32(Insn, 6, 1);
2790 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2791 return MCDisassembler::Fail;
2793 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2794 return MCDisassembler::Fail; // Writeback
2797 switch (Inst.getOpcode()) {
2800 if (!Check(S, DecodeDPairRegisterClass(Inst, Rn, Address, Decoder)))
2801 return MCDisassembler::Fail;
2804 if (!Check(S, DecodeDPRRegisterClass(Inst, Rn, Address, Decoder)))
2805 return MCDisassembler::Fail;
2808 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
2809 return MCDisassembler::Fail;
2814 static DecodeStatus DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn,
2815 uint64_t Address, const void *Decoder) {
2816 DecodeStatus S = MCDisassembler::Success;
2818 unsigned dst = fieldFromInstruction16(Insn, 8, 3);
2819 unsigned imm = fieldFromInstruction16(Insn, 0, 8);
2821 if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder)))
2822 return MCDisassembler::Fail;
2824 switch(Inst.getOpcode()) {
2826 return MCDisassembler::Fail;
2828 break; // tADR does not explicitly represent the PC as an operand.
2830 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
2834 Inst.addOperand(MCOperand::CreateImm(imm));
2838 static DecodeStatus DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val,
2839 uint64_t Address, const void *Decoder) {
2840 Inst.addOperand(MCOperand::CreateImm(SignExtend32<12>(Val << 1)));
2841 return MCDisassembler::Success;
2844 static DecodeStatus DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val,
2845 uint64_t Address, const void *Decoder) {
2846 Inst.addOperand(MCOperand::CreateImm(SignExtend32<21>(Val)));
2847 return MCDisassembler::Success;
2850 static DecodeStatus DecodeThumbCmpBROperand(llvm::MCInst &Inst, unsigned Val,
2851 uint64_t Address, const void *Decoder) {
2852 Inst.addOperand(MCOperand::CreateImm(SignExtend32<7>(Val << 1)));
2853 return MCDisassembler::Success;
2856 static DecodeStatus DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned Val,
2857 uint64_t Address, const void *Decoder) {
2858 DecodeStatus S = MCDisassembler::Success;
2860 unsigned Rn = fieldFromInstruction32(Val, 0, 3);
2861 unsigned Rm = fieldFromInstruction32(Val, 3, 3);
2863 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
2864 return MCDisassembler::Fail;
2865 if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder)))
2866 return MCDisassembler::Fail;
2871 static DecodeStatus DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned Val,
2872 uint64_t Address, const void *Decoder) {
2873 DecodeStatus S = MCDisassembler::Success;
2875 unsigned Rn = fieldFromInstruction32(Val, 0, 3);
2876 unsigned imm = fieldFromInstruction32(Val, 3, 5);
2878 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
2879 return MCDisassembler::Fail;
2880 Inst.addOperand(MCOperand::CreateImm(imm));
2885 static DecodeStatus DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned Val,
2886 uint64_t Address, const void *Decoder) {
2887 unsigned imm = Val << 2;
2889 Inst.addOperand(MCOperand::CreateImm(imm));
2890 tryAddingPcLoadReferenceComment(Address, (Address & ~2u) + imm + 4, Decoder);
2892 return MCDisassembler::Success;
2895 static DecodeStatus DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val,
2896 uint64_t Address, const void *Decoder) {
2897 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
2898 Inst.addOperand(MCOperand::CreateImm(Val));
2900 return MCDisassembler::Success;
2903 static DecodeStatus DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned Val,
2904 uint64_t Address, const void *Decoder) {
2905 DecodeStatus S = MCDisassembler::Success;
2907 unsigned Rn = fieldFromInstruction32(Val, 6, 4);
2908 unsigned Rm = fieldFromInstruction32(Val, 2, 4);
2909 unsigned imm = fieldFromInstruction32(Val, 0, 2);
2911 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2912 return MCDisassembler::Fail;
2913 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
2914 return MCDisassembler::Fail;
2915 Inst.addOperand(MCOperand::CreateImm(imm));
2920 static DecodeStatus DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Insn,
2921 uint64_t Address, const void *Decoder) {
2922 DecodeStatus S = MCDisassembler::Success;
2924 switch (Inst.getOpcode()) {
2930 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
2931 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
2932 return MCDisassembler::Fail;
2936 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2938 switch (Inst.getOpcode()) {
2940 Inst.setOpcode(ARM::t2LDRBpci);
2943 Inst.setOpcode(ARM::t2LDRHpci);
2946 Inst.setOpcode(ARM::t2LDRSHpci);
2949 Inst.setOpcode(ARM::t2LDRSBpci);
2952 Inst.setOpcode(ARM::t2PLDi12);
2953 Inst.addOperand(MCOperand::CreateReg(ARM::PC));
2956 return MCDisassembler::Fail;
2959 int imm = fieldFromInstruction32(Insn, 0, 12);
2960 if (!fieldFromInstruction32(Insn, 23, 1)) imm *= -1;
2961 Inst.addOperand(MCOperand::CreateImm(imm));
2966 unsigned addrmode = fieldFromInstruction32(Insn, 4, 2);
2967 addrmode |= fieldFromInstruction32(Insn, 0, 4) << 2;
2968 addrmode |= fieldFromInstruction32(Insn, 16, 4) << 6;
2969 if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder)))
2970 return MCDisassembler::Fail;
2975 static DecodeStatus DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val,
2976 uint64_t Address, const void *Decoder) {
2977 int imm = Val & 0xFF;
2978 if (!(Val & 0x100)) imm *= -1;
2979 Inst.addOperand(MCOperand::CreateImm(imm << 2));
2981 return MCDisassembler::Success;
2984 static DecodeStatus DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned Val,
2985 uint64_t Address, const void *Decoder) {
2986 DecodeStatus S = MCDisassembler::Success;
2988 unsigned Rn = fieldFromInstruction32(Val, 9, 4);
2989 unsigned imm = fieldFromInstruction32(Val, 0, 9);
2991 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2992 return MCDisassembler::Fail;
2993 if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder)))
2994 return MCDisassembler::Fail;
2999 static DecodeStatus DecodeT2AddrModeImm0_1020s4(llvm::MCInst &Inst,unsigned Val,
3000 uint64_t Address, const void *Decoder) {
3001 DecodeStatus S = MCDisassembler::Success;
3003 unsigned Rn = fieldFromInstruction32(Val, 8, 4);
3004 unsigned imm = fieldFromInstruction32(Val, 0, 8);
3006 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
3007 return MCDisassembler::Fail;
3009 Inst.addOperand(MCOperand::CreateImm(imm));
3014 static DecodeStatus DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val,
3015 uint64_t Address, const void *Decoder) {
3016 int imm = Val & 0xFF;
3019 else if (!(Val & 0x100))
3021 Inst.addOperand(MCOperand::CreateImm(imm));
3023 return MCDisassembler::Success;
3027 static DecodeStatus DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val,
3028 uint64_t Address, const void *Decoder) {
3029 DecodeStatus S = MCDisassembler::Success;
3031 unsigned Rn = fieldFromInstruction32(Val, 9, 4);
3032 unsigned imm = fieldFromInstruction32(Val, 0, 9);
3034 // Some instructions always use an additive offset.
3035 switch (Inst.getOpcode()) {
3050 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3051 return MCDisassembler::Fail;
3052 if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder)))
3053 return MCDisassembler::Fail;
3058 static DecodeStatus DecodeT2LdStPre(llvm::MCInst &Inst, unsigned Insn,
3059 uint64_t Address, const void *Decoder) {
3060 DecodeStatus S = MCDisassembler::Success;
3062 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3063 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3064 unsigned addr = fieldFromInstruction32(Insn, 0, 8);
3065 addr |= fieldFromInstruction32(Insn, 9, 1) << 8;
3067 unsigned load = fieldFromInstruction32(Insn, 20, 1);
3070 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3071 return MCDisassembler::Fail;
3074 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
3075 return MCDisassembler::Fail;
3078 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3079 return MCDisassembler::Fail;
3082 if (!Check(S, DecodeT2AddrModeImm8(Inst, addr, Address, Decoder)))
3083 return MCDisassembler::Fail;
3088 static DecodeStatus DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val,
3089 uint64_t Address, const void *Decoder) {
3090 DecodeStatus S = MCDisassembler::Success;
3092 unsigned Rn = fieldFromInstruction32(Val, 13, 4);
3093 unsigned imm = fieldFromInstruction32(Val, 0, 12);
3095 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3096 return MCDisassembler::Fail;
3097 Inst.addOperand(MCOperand::CreateImm(imm));
3103 static DecodeStatus DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Insn,
3104 uint64_t Address, const void *Decoder) {
3105 unsigned imm = fieldFromInstruction16(Insn, 0, 7);
3107 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3108 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3109 Inst.addOperand(MCOperand::CreateImm(imm));
3111 return MCDisassembler::Success;
3114 static DecodeStatus DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn,
3115 uint64_t Address, const void *Decoder) {
3116 DecodeStatus S = MCDisassembler::Success;
3118 if (Inst.getOpcode() == ARM::tADDrSP) {
3119 unsigned Rdm = fieldFromInstruction16(Insn, 0, 3);
3120 Rdm |= fieldFromInstruction16(Insn, 7, 1) << 3;
3122 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
3123 return MCDisassembler::Fail;
3124 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
3125 return MCDisassembler::Fail;
3126 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3127 } else if (Inst.getOpcode() == ARM::tADDspr) {
3128 unsigned Rm = fieldFromInstruction16(Insn, 3, 4);
3130 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3131 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3132 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3133 return MCDisassembler::Fail;
3139 static DecodeStatus DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn,
3140 uint64_t Address, const void *Decoder) {
3141 unsigned imod = fieldFromInstruction16(Insn, 4, 1) | 0x2;
3142 unsigned flags = fieldFromInstruction16(Insn, 0, 3);
3144 Inst.addOperand(MCOperand::CreateImm(imod));
3145 Inst.addOperand(MCOperand::CreateImm(flags));
3147 return MCDisassembler::Success;
3150 static DecodeStatus DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn,
3151 uint64_t Address, const void *Decoder) {
3152 DecodeStatus S = MCDisassembler::Success;
3153 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3154 unsigned add = fieldFromInstruction32(Insn, 4, 1);
3156 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3157 return MCDisassembler::Fail;
3158 Inst.addOperand(MCOperand::CreateImm(add));
3163 static DecodeStatus DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Val,
3164 uint64_t Address, const void *Decoder) {
3165 if (!tryAddingSymbolicOperand(Address,
3166 (Address & ~2u) + SignExtend32<22>(Val << 1) + 4,
3167 true, 4, Inst, Decoder))
3168 Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1)));
3169 return MCDisassembler::Success;
3172 static DecodeStatus DecodeCoprocessor(llvm::MCInst &Inst, unsigned Val,
3173 uint64_t Address, const void *Decoder) {
3174 if (Val == 0xA || Val == 0xB)
3175 return MCDisassembler::Fail;
3177 Inst.addOperand(MCOperand::CreateImm(Val));
3178 return MCDisassembler::Success;
3182 DecodeThumbTableBranch(llvm::MCInst &Inst, unsigned Insn,
3183 uint64_t Address, const void *Decoder) {
3184 DecodeStatus S = MCDisassembler::Success;
3186 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3187 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3189 if (Rn == ARM::SP) S = MCDisassembler::SoftFail;
3190 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3191 return MCDisassembler::Fail;
3192 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
3193 return MCDisassembler::Fail;
3198 DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Insn,
3199 uint64_t Address, const void *Decoder) {
3200 DecodeStatus S = MCDisassembler::Success;
3202 unsigned pred = fieldFromInstruction32(Insn, 22, 4);
3203 if (pred == 0xE || pred == 0xF) {
3204 unsigned opc = fieldFromInstruction32(Insn, 4, 28);
3207 return MCDisassembler::Fail;
3209 Inst.setOpcode(ARM::t2DSB);
3212 Inst.setOpcode(ARM::t2DMB);
3215 Inst.setOpcode(ARM::t2ISB);
3219 unsigned imm = fieldFromInstruction32(Insn, 0, 4);
3220 return DecodeMemBarrierOption(Inst, imm, Address, Decoder);
3223 unsigned brtarget = fieldFromInstruction32(Insn, 0, 11) << 1;
3224 brtarget |= fieldFromInstruction32(Insn, 11, 1) << 19;
3225 brtarget |= fieldFromInstruction32(Insn, 13, 1) << 18;
3226 brtarget |= fieldFromInstruction32(Insn, 16, 6) << 12;
3227 brtarget |= fieldFromInstruction32(Insn, 26, 1) << 20;
3229 if (!Check(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder)))
3230 return MCDisassembler::Fail;
3231 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3232 return MCDisassembler::Fail;
3237 // Decode a shifted immediate operand. These basically consist
3238 // of an 8-bit value, and a 4-bit directive that specifies either
3239 // a splat operation or a rotation.
3240 static DecodeStatus DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val,
3241 uint64_t Address, const void *Decoder) {
3242 unsigned ctrl = fieldFromInstruction32(Val, 10, 2);
3244 unsigned byte = fieldFromInstruction32(Val, 8, 2);
3245 unsigned imm = fieldFromInstruction32(Val, 0, 8);
3248 Inst.addOperand(MCOperand::CreateImm(imm));
3251 Inst.addOperand(MCOperand::CreateImm((imm << 16) | imm));
3254 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 8)));
3257 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 16) |
3262 unsigned unrot = fieldFromInstruction32(Val, 0, 7) | 0x80;
3263 unsigned rot = fieldFromInstruction32(Val, 7, 5);
3264 unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31));
3265 Inst.addOperand(MCOperand::CreateImm(imm));
3268 return MCDisassembler::Success;
3272 DecodeThumbBCCTargetOperand(llvm::MCInst &Inst, unsigned Val,
3273 uint64_t Address, const void *Decoder){
3274 Inst.addOperand(MCOperand::CreateImm(Val << 1));
3275 return MCDisassembler::Success;
3278 static DecodeStatus DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val,
3279 uint64_t Address, const void *Decoder){
3280 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<22>(Val<<1) + 4,
3281 true, 4, Inst, Decoder))
3282 Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1)));
3283 return MCDisassembler::Success;
3286 static DecodeStatus DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Val,
3287 uint64_t Address, const void *Decoder) {
3290 return MCDisassembler::Fail;
3302 Inst.addOperand(MCOperand::CreateImm(Val));
3303 return MCDisassembler::Success;
3306 static DecodeStatus DecodeMSRMask(llvm::MCInst &Inst, unsigned Val,
3307 uint64_t Address, const void *Decoder) {
3308 if (!Val) return MCDisassembler::Fail;
3309 Inst.addOperand(MCOperand::CreateImm(Val));
3310 return MCDisassembler::Success;
3313 static DecodeStatus DecodeDoubleRegLoad(llvm::MCInst &Inst, unsigned Insn,
3314 uint64_t Address, const void *Decoder) {
3315 DecodeStatus S = MCDisassembler::Success;
3317 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3318 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3319 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3321 if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return MCDisassembler::Fail;
3323 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3324 return MCDisassembler::Fail;
3325 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
3326 return MCDisassembler::Fail;
3327 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3328 return MCDisassembler::Fail;
3329 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3330 return MCDisassembler::Fail;
3336 static DecodeStatus DecodeDoubleRegStore(llvm::MCInst &Inst, unsigned Insn,
3337 uint64_t Address, const void *Decoder){
3338 DecodeStatus S = MCDisassembler::Success;
3340 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3341 unsigned Rt = fieldFromInstruction32(Insn, 0, 4);
3342 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3343 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3345 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
3346 return MCDisassembler::Fail;
3348 if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return MCDisassembler::Fail;
3349 if (Rd == Rn || Rd == Rt || Rd == Rt+1) return MCDisassembler::Fail;
3351 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3352 return MCDisassembler::Fail;
3353 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
3354 return MCDisassembler::Fail;
3355 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3356 return MCDisassembler::Fail;
3357 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3358 return MCDisassembler::Fail;
3363 static DecodeStatus DecodeLDRPreImm(llvm::MCInst &Inst, unsigned Insn,
3364 uint64_t Address, const void *Decoder) {
3365 DecodeStatus S = MCDisassembler::Success;
3367 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3368 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3369 unsigned imm = fieldFromInstruction32(Insn, 0, 12);
3370 imm |= fieldFromInstruction32(Insn, 16, 4) << 13;
3371 imm |= fieldFromInstruction32(Insn, 23, 1) << 12;
3372 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3374 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
3376 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3377 return MCDisassembler::Fail;
3378 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3379 return MCDisassembler::Fail;
3380 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
3381 return MCDisassembler::Fail;
3382 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3383 return MCDisassembler::Fail;
3388 static DecodeStatus DecodeLDRPreReg(llvm::MCInst &Inst, unsigned Insn,
3389 uint64_t Address, const void *Decoder) {
3390 DecodeStatus S = MCDisassembler::Success;
3392 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3393 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3394 unsigned imm = fieldFromInstruction32(Insn, 0, 12);
3395 imm |= fieldFromInstruction32(Insn, 16, 4) << 13;
3396 imm |= fieldFromInstruction32(Insn, 23, 1) << 12;
3397 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3398 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3400 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
3401 if (Rm == 0xF) S = MCDisassembler::SoftFail;
3403 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3404 return MCDisassembler::Fail;
3405 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3406 return MCDisassembler::Fail;
3407 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
3408 return MCDisassembler::Fail;
3409 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3410 return MCDisassembler::Fail;
3416 static DecodeStatus DecodeSTRPreImm(llvm::MCInst &Inst, unsigned Insn,
3417 uint64_t Address, const void *Decoder) {
3418 DecodeStatus S = MCDisassembler::Success;
3420 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3421 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3422 unsigned imm = fieldFromInstruction32(Insn, 0, 12);
3423 imm |= fieldFromInstruction32(Insn, 16, 4) << 13;
3424 imm |= fieldFromInstruction32(Insn, 23, 1) << 12;
3425 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3427 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
3429 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3430 return MCDisassembler::Fail;
3431 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3432 return MCDisassembler::Fail;
3433 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
3434 return MCDisassembler::Fail;
3435 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3436 return MCDisassembler::Fail;
3441 static DecodeStatus DecodeSTRPreReg(llvm::MCInst &Inst, unsigned Insn,
3442 uint64_t Address, const void *Decoder) {
3443 DecodeStatus S = MCDisassembler::Success;
3445 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3446 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3447 unsigned imm = fieldFromInstruction32(Insn, 0, 12);
3448 imm |= fieldFromInstruction32(Insn, 16, 4) << 13;
3449 imm |= fieldFromInstruction32(Insn, 23, 1) << 12;
3450 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3452 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
3454 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3455 return MCDisassembler::Fail;
3456 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3457 return MCDisassembler::Fail;
3458 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
3459 return MCDisassembler::Fail;
3460 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3461 return MCDisassembler::Fail;
3466 static DecodeStatus DecodeVLD1LN(llvm::MCInst &Inst, unsigned Insn,
3467 uint64_t Address, const void *Decoder) {
3468 DecodeStatus S = MCDisassembler::Success;
3470 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3471 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3472 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3473 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3474 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3480 return MCDisassembler::Fail;
3482 if (fieldFromInstruction32(Insn, 4, 1))
3483 return MCDisassembler::Fail; // UNDEFINED
3484 index = fieldFromInstruction32(Insn, 5, 3);
3487 if (fieldFromInstruction32(Insn, 5, 1))
3488 return MCDisassembler::Fail; // UNDEFINED
3489 index = fieldFromInstruction32(Insn, 6, 2);
3490 if (fieldFromInstruction32(Insn, 4, 1))
3494 if (fieldFromInstruction32(Insn, 6, 1))
3495 return MCDisassembler::Fail; // UNDEFINED
3496 index = fieldFromInstruction32(Insn, 7, 1);
3497 if (fieldFromInstruction32(Insn, 4, 2) != 0)
3501 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3502 return MCDisassembler::Fail;
3503 if (Rm != 0xF) { // Writeback
3504 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3505 return MCDisassembler::Fail;
3507 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3508 return MCDisassembler::Fail;
3509 Inst.addOperand(MCOperand::CreateImm(align));
3512 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3513 return MCDisassembler::Fail;
3515 Inst.addOperand(MCOperand::CreateReg(0));
3518 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3519 return MCDisassembler::Fail;
3520 Inst.addOperand(MCOperand::CreateImm(index));
3525 static DecodeStatus DecodeVST1LN(llvm::MCInst &Inst, unsigned Insn,
3526 uint64_t Address, const void *Decoder) {
3527 DecodeStatus S = MCDisassembler::Success;
3529 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3530 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3531 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3532 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3533 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3539 return MCDisassembler::Fail;
3541 if (fieldFromInstruction32(Insn, 4, 1))
3542 return MCDisassembler::Fail; // UNDEFINED
3543 index = fieldFromInstruction32(Insn, 5, 3);
3546 if (fieldFromInstruction32(Insn, 5, 1))
3547 return MCDisassembler::Fail; // UNDEFINED
3548 index = fieldFromInstruction32(Insn, 6, 2);
3549 if (fieldFromInstruction32(Insn, 4, 1))
3553 if (fieldFromInstruction32(Insn, 6, 1))
3554 return MCDisassembler::Fail; // UNDEFINED
3555 index = fieldFromInstruction32(Insn, 7, 1);
3556 if (fieldFromInstruction32(Insn, 4, 2) != 0)
3560 if (Rm != 0xF) { // Writeback
3561 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3562 return MCDisassembler::Fail;
3564 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3565 return MCDisassembler::Fail;
3566 Inst.addOperand(MCOperand::CreateImm(align));
3569 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3570 return MCDisassembler::Fail;
3572 Inst.addOperand(MCOperand::CreateReg(0));
3575 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3576 return MCDisassembler::Fail;
3577 Inst.addOperand(MCOperand::CreateImm(index));
3583 static DecodeStatus DecodeVLD2LN(llvm::MCInst &Inst, unsigned Insn,
3584 uint64_t Address, const void *Decoder) {
3585 DecodeStatus S = MCDisassembler::Success;
3587 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3588 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3589 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3590 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3591 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3598 return MCDisassembler::Fail;
3600 index = fieldFromInstruction32(Insn, 5, 3);
3601 if (fieldFromInstruction32(Insn, 4, 1))
3605 index = fieldFromInstruction32(Insn, 6, 2);
3606 if (fieldFromInstruction32(Insn, 4, 1))
3608 if (fieldFromInstruction32(Insn, 5, 1))
3612 if (fieldFromInstruction32(Insn, 5, 1))
3613 return MCDisassembler::Fail; // UNDEFINED
3614 index = fieldFromInstruction32(Insn, 7, 1);
3615 if (fieldFromInstruction32(Insn, 4, 1) != 0)
3617 if (fieldFromInstruction32(Insn, 6, 1))
3622 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3623 return MCDisassembler::Fail;
3624 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3625 return MCDisassembler::Fail;
3626 if (Rm != 0xF) { // Writeback
3627 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3628 return MCDisassembler::Fail;
3630 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3631 return MCDisassembler::Fail;
3632 Inst.addOperand(MCOperand::CreateImm(align));
3635 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3636 return MCDisassembler::Fail;
3638 Inst.addOperand(MCOperand::CreateReg(0));
3641 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3642 return MCDisassembler::Fail;
3643 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3644 return MCDisassembler::Fail;
3645 Inst.addOperand(MCOperand::CreateImm(index));
3650 static DecodeStatus DecodeVST2LN(llvm::MCInst &Inst, unsigned Insn,
3651 uint64_t Address, const void *Decoder) {
3652 DecodeStatus S = MCDisassembler::Success;
3654 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3655 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3656 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3657 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3658 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3665 return MCDisassembler::Fail;
3667 index = fieldFromInstruction32(Insn, 5, 3);
3668 if (fieldFromInstruction32(Insn, 4, 1))
3672 index = fieldFromInstruction32(Insn, 6, 2);
3673 if (fieldFromInstruction32(Insn, 4, 1))
3675 if (fieldFromInstruction32(Insn, 5, 1))
3679 if (fieldFromInstruction32(Insn, 5, 1))
3680 return MCDisassembler::Fail; // UNDEFINED
3681 index = fieldFromInstruction32(Insn, 7, 1);
3682 if (fieldFromInstruction32(Insn, 4, 1) != 0)
3684 if (fieldFromInstruction32(Insn, 6, 1))
3689 if (Rm != 0xF) { // Writeback
3690 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3691 return MCDisassembler::Fail;
3693 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3694 return MCDisassembler::Fail;
3695 Inst.addOperand(MCOperand::CreateImm(align));
3698 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3699 return MCDisassembler::Fail;
3701 Inst.addOperand(MCOperand::CreateReg(0));
3704 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3705 return MCDisassembler::Fail;
3706 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3707 return MCDisassembler::Fail;
3708 Inst.addOperand(MCOperand::CreateImm(index));
3714 static DecodeStatus DecodeVLD3LN(llvm::MCInst &Inst, unsigned Insn,
3715 uint64_t Address, const void *Decoder) {
3716 DecodeStatus S = MCDisassembler::Success;
3718 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3719 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3720 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3721 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3722 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3729 return MCDisassembler::Fail;
3731 if (fieldFromInstruction32(Insn, 4, 1))
3732 return MCDisassembler::Fail; // UNDEFINED
3733 index = fieldFromInstruction32(Insn, 5, 3);
3736 if (fieldFromInstruction32(Insn, 4, 1))
3737 return MCDisassembler::Fail; // UNDEFINED
3738 index = fieldFromInstruction32(Insn, 6, 2);
3739 if (fieldFromInstruction32(Insn, 5, 1))
3743 if (fieldFromInstruction32(Insn, 4, 2))
3744 return MCDisassembler::Fail; // UNDEFINED
3745 index = fieldFromInstruction32(Insn, 7, 1);
3746 if (fieldFromInstruction32(Insn, 6, 1))
3751 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3752 return MCDisassembler::Fail;
3753 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3754 return MCDisassembler::Fail;
3755 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
3756 return MCDisassembler::Fail;
3758 if (Rm != 0xF) { // Writeback
3759 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3760 return MCDisassembler::Fail;
3762 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3763 return MCDisassembler::Fail;
3764 Inst.addOperand(MCOperand::CreateImm(align));
3767 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3768 return MCDisassembler::Fail;
3770 Inst.addOperand(MCOperand::CreateReg(0));
3773 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3774 return MCDisassembler::Fail;
3775 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3776 return MCDisassembler::Fail;
3777 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
3778 return MCDisassembler::Fail;
3779 Inst.addOperand(MCOperand::CreateImm(index));
3784 static DecodeStatus DecodeVST3LN(llvm::MCInst &Inst, unsigned Insn,
3785 uint64_t Address, const void *Decoder) {
3786 DecodeStatus S = MCDisassembler::Success;
3788 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3789 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3790 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3791 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3792 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3799 return MCDisassembler::Fail;
3801 if (fieldFromInstruction32(Insn, 4, 1))
3802 return MCDisassembler::Fail; // UNDEFINED
3803 index = fieldFromInstruction32(Insn, 5, 3);
3806 if (fieldFromInstruction32(Insn, 4, 1))
3807 return MCDisassembler::Fail; // UNDEFINED
3808 index = fieldFromInstruction32(Insn, 6, 2);
3809 if (fieldFromInstruction32(Insn, 5, 1))
3813 if (fieldFromInstruction32(Insn, 4, 2))
3814 return MCDisassembler::Fail; // UNDEFINED
3815 index = fieldFromInstruction32(Insn, 7, 1);
3816 if (fieldFromInstruction32(Insn, 6, 1))
3821 if (Rm != 0xF) { // Writeback
3822 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3823 return MCDisassembler::Fail;
3825 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3826 return MCDisassembler::Fail;
3827 Inst.addOperand(MCOperand::CreateImm(align));
3830 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3831 return MCDisassembler::Fail;
3833 Inst.addOperand(MCOperand::CreateReg(0));
3836 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3837 return MCDisassembler::Fail;
3838 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3839 return MCDisassembler::Fail;
3840 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
3841 return MCDisassembler::Fail;
3842 Inst.addOperand(MCOperand::CreateImm(index));
3848 static DecodeStatus DecodeVLD4LN(llvm::MCInst &Inst, unsigned Insn,
3849 uint64_t Address, const void *Decoder) {
3850 DecodeStatus S = MCDisassembler::Success;
3852 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3853 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3854 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3855 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3856 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3863 return MCDisassembler::Fail;
3865 if (fieldFromInstruction32(Insn, 4, 1))
3867 index = fieldFromInstruction32(Insn, 5, 3);
3870 if (fieldFromInstruction32(Insn, 4, 1))
3872 index = fieldFromInstruction32(Insn, 6, 2);
3873 if (fieldFromInstruction32(Insn, 5, 1))
3877 if (fieldFromInstruction32(Insn, 4, 2))
3878 align = 4 << fieldFromInstruction32(Insn, 4, 2);
3879 index = fieldFromInstruction32(Insn, 7, 1);
3880 if (fieldFromInstruction32(Insn, 6, 1))
3885 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3886 return MCDisassembler::Fail;
3887 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3888 return MCDisassembler::Fail;
3889 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
3890 return MCDisassembler::Fail;
3891 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
3892 return MCDisassembler::Fail;
3894 if (Rm != 0xF) { // Writeback
3895 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3896 return MCDisassembler::Fail;
3898 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3899 return MCDisassembler::Fail;
3900 Inst.addOperand(MCOperand::CreateImm(align));
3903 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3904 return MCDisassembler::Fail;
3906 Inst.addOperand(MCOperand::CreateReg(0));
3909 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3910 return MCDisassembler::Fail;
3911 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3912 return MCDisassembler::Fail;
3913 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
3914 return MCDisassembler::Fail;
3915 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
3916 return MCDisassembler::Fail;
3917 Inst.addOperand(MCOperand::CreateImm(index));
3922 static DecodeStatus DecodeVST4LN(llvm::MCInst &Inst, unsigned Insn,
3923 uint64_t Address, const void *Decoder) {
3924 DecodeStatus S = MCDisassembler::Success;
3926 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3927 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3928 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3929 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3930 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3937 return MCDisassembler::Fail;
3939 if (fieldFromInstruction32(Insn, 4, 1))
3941 index = fieldFromInstruction32(Insn, 5, 3);
3944 if (fieldFromInstruction32(Insn, 4, 1))
3946 index = fieldFromInstruction32(Insn, 6, 2);
3947 if (fieldFromInstruction32(Insn, 5, 1))
3951 if (fieldFromInstruction32(Insn, 4, 2))
3952 align = 4 << fieldFromInstruction32(Insn, 4, 2);
3953 index = fieldFromInstruction32(Insn, 7, 1);
3954 if (fieldFromInstruction32(Insn, 6, 1))
3959 if (Rm != 0xF) { // Writeback
3960 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3961 return MCDisassembler::Fail;
3963 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3964 return MCDisassembler::Fail;
3965 Inst.addOperand(MCOperand::CreateImm(align));
3968 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3969 return MCDisassembler::Fail;
3971 Inst.addOperand(MCOperand::CreateReg(0));
3974 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3975 return MCDisassembler::Fail;
3976 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3977 return MCDisassembler::Fail;
3978 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
3979 return MCDisassembler::Fail;
3980 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
3981 return MCDisassembler::Fail;
3982 Inst.addOperand(MCOperand::CreateImm(index));
3987 static DecodeStatus DecodeVMOVSRR(llvm::MCInst &Inst, unsigned Insn,
3988 uint64_t Address, const void *Decoder) {
3989 DecodeStatus S = MCDisassembler::Success;
3990 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3991 unsigned Rt2 = fieldFromInstruction32(Insn, 16, 4);
3992 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3993 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3994 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4;
3996 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
3997 S = MCDisassembler::SoftFail;
3999 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)))
4000 return MCDisassembler::Fail;
4001 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
4002 return MCDisassembler::Fail;
4003 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder)))
4004 return MCDisassembler::Fail;
4005 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
4006 return MCDisassembler::Fail;
4007 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4008 return MCDisassembler::Fail;
4013 static DecodeStatus DecodeVMOVRRS(llvm::MCInst &Inst, unsigned Insn,
4014 uint64_t Address, const void *Decoder) {
4015 DecodeStatus S = MCDisassembler::Success;
4016 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
4017 unsigned Rt2 = fieldFromInstruction32(Insn, 16, 4);
4018 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
4019 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
4020 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4;
4022 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
4023 S = MCDisassembler::SoftFail;
4025 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder)))
4026 return MCDisassembler::Fail;
4027 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
4028 return MCDisassembler::Fail;
4029 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)))
4030 return MCDisassembler::Fail;
4031 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
4032 return MCDisassembler::Fail;
4033 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4034 return MCDisassembler::Fail;
4039 static DecodeStatus DecodeIT(llvm::MCInst &Inst, unsigned Insn,
4040 uint64_t Address, const void *Decoder) {
4041 DecodeStatus S = MCDisassembler::Success;
4042 unsigned pred = fieldFromInstruction16(Insn, 4, 4);
4043 // The InstPrinter needs to have the low bit of the predicate in
4044 // the mask operand to be able to print it properly.
4045 unsigned mask = fieldFromInstruction16(Insn, 0, 5);
4049 S = MCDisassembler::SoftFail;
4052 if ((mask & 0xF) == 0) {
4053 // Preserve the high bit of the mask, which is the low bit of
4057 S = MCDisassembler::SoftFail;
4060 Inst.addOperand(MCOperand::CreateImm(pred));
4061 Inst.addOperand(MCOperand::CreateImm(mask));
4066 DecodeT2LDRDPreInstruction(llvm::MCInst &Inst, unsigned Insn,
4067 uint64_t Address, const void *Decoder) {
4068 DecodeStatus S = MCDisassembler::Success;
4070 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
4071 unsigned Rt2 = fieldFromInstruction32(Insn, 8, 4);
4072 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
4073 unsigned addr = fieldFromInstruction32(Insn, 0, 8);
4074 unsigned W = fieldFromInstruction32(Insn, 21, 1);
4075 unsigned U = fieldFromInstruction32(Insn, 23, 1);
4076 unsigned P = fieldFromInstruction32(Insn, 24, 1);
4077 bool writeback = (W == 1) | (P == 0);
4079 addr |= (U << 8) | (Rn << 9);
4081 if (writeback && (Rn == Rt || Rn == Rt2))
4082 Check(S, MCDisassembler::SoftFail);
4084 Check(S, MCDisassembler::SoftFail);
4087 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
4088 return MCDisassembler::Fail;
4090 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
4091 return MCDisassembler::Fail;
4092 // Writeback operand
4093 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
4094 return MCDisassembler::Fail;
4096 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
4097 return MCDisassembler::Fail;
4103 DecodeT2STRDPreInstruction(llvm::MCInst &Inst, unsigned Insn,
4104 uint64_t Address, const void *Decoder) {
4105 DecodeStatus S = MCDisassembler::Success;
4107 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
4108 unsigned Rt2 = fieldFromInstruction32(Insn, 8, 4);
4109 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
4110 unsigned addr = fieldFromInstruction32(Insn, 0, 8);
4111 unsigned W = fieldFromInstruction32(Insn, 21, 1);
4112 unsigned U = fieldFromInstruction32(Insn, 23, 1);
4113 unsigned P = fieldFromInstruction32(Insn, 24, 1);
4114 bool writeback = (W == 1) | (P == 0);
4116 addr |= (U << 8) | (Rn << 9);
4118 if (writeback && (Rn == Rt || Rn == Rt2))
4119 Check(S, MCDisassembler::SoftFail);
4121 // Writeback operand
4122 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
4123 return MCDisassembler::Fail;
4125 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
4126 return MCDisassembler::Fail;
4128 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
4129 return MCDisassembler::Fail;
4131 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
4132 return MCDisassembler::Fail;
4137 static DecodeStatus DecodeT2Adr(llvm::MCInst &Inst, uint32_t Insn,
4138 uint64_t Address, const void *Decoder) {
4139 unsigned sign1 = fieldFromInstruction32(Insn, 21, 1);
4140 unsigned sign2 = fieldFromInstruction32(Insn, 23, 1);
4141 if (sign1 != sign2) return MCDisassembler::Fail;
4143 unsigned Val = fieldFromInstruction32(Insn, 0, 8);
4144 Val |= fieldFromInstruction32(Insn, 12, 3) << 8;
4145 Val |= fieldFromInstruction32(Insn, 26, 1) << 11;
4147 Inst.addOperand(MCOperand::CreateImm(SignExtend32<13>(Val)));
4149 return MCDisassembler::Success;
4152 static DecodeStatus DecodeT2ShifterImmOperand(llvm::MCInst &Inst, uint32_t Val,
4154 const void *Decoder) {
4155 DecodeStatus S = MCDisassembler::Success;
4157 // Shift of "asr #32" is not allowed in Thumb2 mode.
4158 if (Val == 0x20) S = MCDisassembler::SoftFail;
4159 Inst.addOperand(MCOperand::CreateImm(Val));
4163 static DecodeStatus DecodeSwap(llvm::MCInst &Inst, unsigned Insn,
4164 uint64_t Address, const void *Decoder) {
4165 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
4166 unsigned Rt2 = fieldFromInstruction32(Insn, 0, 4);
4167 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
4168 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
4171 return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
4173 DecodeStatus S = MCDisassembler::Success;
4174 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
4175 return MCDisassembler::Fail;
4176 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder)))
4177 return MCDisassembler::Fail;
4178 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
4179 return MCDisassembler::Fail;
4180 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4181 return MCDisassembler::Fail;
4186 static DecodeStatus DecodeVCVTD(llvm::MCInst &Inst, unsigned Insn,
4187 uint64_t Address, const void *Decoder) {
4188 unsigned Vd = (fieldFromInstruction32(Insn, 12, 4) << 0);
4189 Vd |= (fieldFromInstruction32(Insn, 22, 1) << 4);
4190 unsigned Vm = (fieldFromInstruction32(Insn, 0, 4) << 0);
4191 Vm |= (fieldFromInstruction32(Insn, 5, 1) << 4);
4192 unsigned imm = fieldFromInstruction32(Insn, 16, 6);
4193 unsigned cmode = fieldFromInstruction32(Insn, 8, 4);
4195 DecodeStatus S = MCDisassembler::Success;
4197 // VMOVv2f32 is ambiguous with these decodings.
4198 if (!(imm & 0x38) && cmode == 0xF) {
4199 Inst.setOpcode(ARM::VMOVv2f32);
4200 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder);
4203 if (!(imm & 0x20)) Check(S, MCDisassembler::SoftFail);
4205 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
4206 return MCDisassembler::Fail;
4207 if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder)))
4208 return MCDisassembler::Fail;
4209 Inst.addOperand(MCOperand::CreateImm(64 - imm));
4214 static DecodeStatus DecodeVCVTQ(llvm::MCInst &Inst, unsigned Insn,
4215 uint64_t Address, const void *Decoder) {
4216 unsigned Vd = (fieldFromInstruction32(Insn, 12, 4) << 0);
4217 Vd |= (fieldFromInstruction32(Insn, 22, 1) << 4);
4218 unsigned Vm = (fieldFromInstruction32(Insn, 0, 4) << 0);
4219 Vm |= (fieldFromInstruction32(Insn, 5, 1) << 4);
4220 unsigned imm = fieldFromInstruction32(Insn, 16, 6);
4221 unsigned cmode = fieldFromInstruction32(Insn, 8, 4);
4223 DecodeStatus S = MCDisassembler::Success;
4225 // VMOVv4f32 is ambiguous with these decodings.
4226 if (!(imm & 0x38) && cmode == 0xF) {
4227 Inst.setOpcode(ARM::VMOVv4f32);
4228 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder);
4231 if (!(imm & 0x20)) Check(S, MCDisassembler::SoftFail);
4233 if (!Check(S, DecodeQPRRegisterClass(Inst, Vd, Address, Decoder)))
4234 return MCDisassembler::Fail;
4235 if (!Check(S, DecodeQPRRegisterClass(Inst, Vm, Address, Decoder)))
4236 return MCDisassembler::Fail;
4237 Inst.addOperand(MCOperand::CreateImm(64 - imm));