1 //===-- ARMAsmPrinter.cpp - Print machine code to an ARM .s file ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains a printer that converts from our internal representation
11 // of machine-dependent LLVM code to GAS-format ARM assembly language.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "asm-printer"
17 #include "ARMBuildAttrs.h"
18 #include "ARMAddressingModes.h"
19 #include "ARMConstantPoolValue.h"
20 #include "ARMInstPrinter.h"
21 #include "ARMMachineFunctionInfo.h"
22 #include "ARMMCInstLower.h"
23 #include "ARMTargetMachine.h"
24 #include "llvm/Analysis/DebugInfo.h"
25 #include "llvm/Constants.h"
26 #include "llvm/Module.h"
27 #include "llvm/Type.h"
28 #include "llvm/Assembly/Writer.h"
29 #include "llvm/CodeGen/AsmPrinter.h"
30 #include "llvm/CodeGen/MachineModuleInfoImpls.h"
31 #include "llvm/CodeGen/MachineFunctionPass.h"
32 #include "llvm/CodeGen/MachineJumpTableInfo.h"
33 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
34 #include "llvm/MC/MCAsmInfo.h"
35 #include "llvm/MC/MCContext.h"
36 #include "llvm/MC/MCExpr.h"
37 #include "llvm/MC/MCInst.h"
38 #include "llvm/MC/MCSectionMachO.h"
39 #include "llvm/MC/MCStreamer.h"
40 #include "llvm/MC/MCSymbol.h"
41 #include "llvm/Target/Mangler.h"
42 #include "llvm/Target/TargetData.h"
43 #include "llvm/Target/TargetMachine.h"
44 #include "llvm/Target/TargetOptions.h"
45 #include "llvm/Target/TargetRegistry.h"
46 #include "llvm/ADT/SmallPtrSet.h"
47 #include "llvm/ADT/SmallString.h"
48 #include "llvm/ADT/StringExtras.h"
49 #include "llvm/Support/CommandLine.h"
50 #include "llvm/Support/ErrorHandling.h"
51 #include "llvm/Support/raw_ostream.h"
56 EnableMCInst("enable-arm-mcinst-printer", cl::Hidden,
57 cl::desc("enable experimental asmprinter gunk in the arm backend"));
60 class ARMAsmPrinter : public AsmPrinter {
62 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
63 /// make the right decision when printing asm code for different targets.
64 const ARMSubtarget *Subtarget;
66 /// AFI - Keep a pointer to ARMFunctionInfo for the current
70 /// MCP - Keep a pointer to constantpool entries of the current
72 const MachineConstantPool *MCP;
75 explicit ARMAsmPrinter(TargetMachine &TM, MCStreamer &Streamer)
76 : AsmPrinter(TM, Streamer), AFI(NULL), MCP(NULL) {
77 Subtarget = &TM.getSubtarget<ARMSubtarget>();
80 virtual const char *getPassName() const {
81 return "ARM Assembly Printer";
84 void printInstructionThroughMCStreamer(const MachineInstr *MI);
87 void printOperand(const MachineInstr *MI, int OpNum, raw_ostream &O,
88 const char *Modifier = 0);
89 void printSOImmOperand(const MachineInstr *MI, int OpNum, raw_ostream &O);
90 void printSOImm2PartOperand(const MachineInstr *MI, int OpNum,
92 void printSORegOperand(const MachineInstr *MI, int OpNum,
94 void printAddrMode2Operand(const MachineInstr *MI, int OpNum,
96 void printAddrMode2OffsetOperand(const MachineInstr *MI, int OpNum,
98 void printAddrMode3Operand(const MachineInstr *MI, int OpNum,
100 void printAddrMode3OffsetOperand(const MachineInstr *MI, int OpNum,
102 void printAddrMode4Operand(const MachineInstr *MI, int OpNum,raw_ostream &O,
103 const char *Modifier = 0);
104 void printAddrMode5Operand(const MachineInstr *MI, int OpNum,raw_ostream &O,
105 const char *Modifier = 0);
106 void printAddrMode6Operand(const MachineInstr *MI, int OpNum,
108 void printAddrMode6OffsetOperand(const MachineInstr *MI, int OpNum,
110 void printAddrModePCOperand(const MachineInstr *MI, int OpNum,
112 const char *Modifier = 0);
113 void printBitfieldInvMaskImmOperand (const MachineInstr *MI, int OpNum,
116 void printThumbS4ImmOperand(const MachineInstr *MI, int OpNum,
118 void printThumbITMask(const MachineInstr *MI, int OpNum, raw_ostream &O);
119 void printThumbAddrModeRROperand(const MachineInstr *MI, int OpNum,
121 void printThumbAddrModeRI5Operand(const MachineInstr *MI, int OpNum,
124 void printThumbAddrModeS1Operand(const MachineInstr *MI, int OpNum,
126 void printThumbAddrModeS2Operand(const MachineInstr *MI, int OpNum,
128 void printThumbAddrModeS4Operand(const MachineInstr *MI, int OpNum,
130 void printThumbAddrModeSPOperand(const MachineInstr *MI, int OpNum,
133 void printT2SOOperand(const MachineInstr *MI, int OpNum, raw_ostream &O);
134 void printT2AddrModeImm12Operand(const MachineInstr *MI, int OpNum,
136 void printT2AddrModeImm8Operand(const MachineInstr *MI, int OpNum,
138 void printT2AddrModeImm8s4Operand(const MachineInstr *MI, int OpNum,
140 void printT2AddrModeImm8OffsetOperand(const MachineInstr *MI, int OpNum,
142 void printT2AddrModeImm8s4OffsetOperand(const MachineInstr *MI, int OpNum,
144 void printT2AddrModeSoRegOperand(const MachineInstr *MI, int OpNum,
147 void printCPSOptionOperand(const MachineInstr *MI, int OpNum,
149 void printMSRMaskOperand(const MachineInstr *MI, int OpNum,
151 void printNegZeroOperand(const MachineInstr *MI, int OpNum,
153 void printPredicateOperand(const MachineInstr *MI, int OpNum,
155 void printMandatoryPredicateOperand(const MachineInstr *MI, int OpNum,
157 void printSBitModifierOperand(const MachineInstr *MI, int OpNum,
159 void printPCLabel(const MachineInstr *MI, int OpNum,
161 void printRegisterList(const MachineInstr *MI, int OpNum,
163 void printCPInstOperand(const MachineInstr *MI, int OpNum,
165 const char *Modifier);
166 void printJTBlockOperand(const MachineInstr *MI, int OpNum,
168 void printJT2BlockOperand(const MachineInstr *MI, int OpNum,
170 void printTBAddrMode(const MachineInstr *MI, int OpNum,
172 void printNoHashImmediate(const MachineInstr *MI, int OpNum,
174 void printVFPf32ImmOperand(const MachineInstr *MI, int OpNum,
176 void printVFPf64ImmOperand(const MachineInstr *MI, int OpNum,
179 void printHex8ImmOperand(const MachineInstr *MI, int OpNum,
181 O << "#0x" << utohexstr(MI->getOperand(OpNum).getImm() & 0xff);
183 void printHex16ImmOperand(const MachineInstr *MI, int OpNum,
185 O << "#0x" << utohexstr(MI->getOperand(OpNum).getImm() & 0xffff);
187 void printHex32ImmOperand(const MachineInstr *MI, int OpNum,
189 O << "#0x" << utohexstr(MI->getOperand(OpNum).getImm() & 0xffffffff);
191 void printHex64ImmOperand(const MachineInstr *MI, int OpNum,
193 O << "#0x" << utohexstr(MI->getOperand(OpNum).getImm());
196 virtual bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
197 unsigned AsmVariant, const char *ExtraCode,
199 virtual bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNum,
201 const char *ExtraCode, raw_ostream &O);
203 void printInstruction(const MachineInstr *MI, raw_ostream &O); // autogen
204 static const char *getRegisterName(unsigned RegNo);
206 virtual void EmitInstruction(const MachineInstr *MI);
207 bool runOnMachineFunction(MachineFunction &F);
209 virtual void EmitConstantPool() {} // we emit constant pools customly!
210 virtual void EmitFunctionEntryLabel();
211 void EmitStartOfAsmFile(Module &M);
212 void EmitEndOfAsmFile(Module &M);
214 MCSymbol *GetARMSetPICJumpTableLabel2(unsigned uid, unsigned uid2,
215 const MachineBasicBlock *MBB) const;
216 MCSymbol *GetARMJTIPICJumpTableLabel2(unsigned uid, unsigned uid2) const;
218 /// EmitMachineConstantPoolValue - Print a machine constantpool value to
220 virtual void EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV) {
221 SmallString<128> Str;
222 raw_svector_ostream OS(Str);
223 EmitMachineConstantPoolValue(MCPV, OS);
224 OutStreamer.EmitRawText(OS.str());
227 void EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV,
229 switch (TM.getTargetData()->getTypeAllocSize(MCPV->getType())) {
230 case 1: O << MAI->getData8bitsDirective(0); break;
231 case 2: O << MAI->getData16bitsDirective(0); break;
232 case 4: O << MAI->getData32bitsDirective(0); break;
233 default: assert(0 && "Unknown CPV size");
236 ARMConstantPoolValue *ACPV = static_cast<ARMConstantPoolValue*>(MCPV);
238 if (ACPV->isLSDA()) {
239 O << MAI->getPrivateGlobalPrefix() << "_LSDA_" << getFunctionNumber();
240 } else if (ACPV->isBlockAddress()) {
241 O << *GetBlockAddressSymbol(ACPV->getBlockAddress());
242 } else if (ACPV->isGlobalValue()) {
243 const GlobalValue *GV = ACPV->getGV();
244 bool isIndirect = Subtarget->isTargetDarwin() &&
245 Subtarget->GVIsIndirectSymbol(GV, TM.getRelocationModel());
247 O << *Mang->getSymbol(GV);
249 // FIXME: Remove this when Darwin transition to @GOT like syntax.
250 MCSymbol *Sym = GetSymbolWithGlobalValueBase(GV, "$non_lazy_ptr");
253 MachineModuleInfoMachO &MMIMachO =
254 MMI->getObjFileInfo<MachineModuleInfoMachO>();
255 MachineModuleInfoImpl::StubValueTy &StubSym =
256 GV->hasHiddenVisibility() ? MMIMachO.getHiddenGVStubEntry(Sym) :
257 MMIMachO.getGVStubEntry(Sym);
258 if (StubSym.getPointer() == 0)
259 StubSym = MachineModuleInfoImpl::
260 StubValueTy(Mang->getSymbol(GV), !GV->hasInternalLinkage());
263 assert(ACPV->isExtSymbol() && "unrecognized constant pool value");
264 O << *GetExternalSymbolSymbol(ACPV->getSymbol());
267 if (ACPV->hasModifier()) O << "(" << ACPV->getModifier() << ")";
268 if (ACPV->getPCAdjustment() != 0) {
269 O << "-(" << MAI->getPrivateGlobalPrefix() << "PC"
270 << getFunctionNumber() << "_" << ACPV->getLabelId()
271 << "+" << (unsigned)ACPV->getPCAdjustment();
272 if (ACPV->mustAddCurrentAddress())
278 } // end of anonymous namespace
280 #include "ARMGenAsmWriter.inc"
282 void ARMAsmPrinter::EmitFunctionEntryLabel() {
283 if (AFI->isThumbFunction()) {
284 OutStreamer.EmitRawText(StringRef("\t.code\t16"));
285 if (!Subtarget->isTargetDarwin())
286 OutStreamer.EmitRawText(StringRef("\t.thumb_func"));
288 // This needs to emit to a temporary string to get properly quoted
289 // MCSymbols when they have spaces in them.
290 SmallString<128> Tmp;
291 raw_svector_ostream OS(Tmp);
292 OS << "\t.thumb_func\t" << *CurrentFnSym;
293 OutStreamer.EmitRawText(OS.str());
297 OutStreamer.EmitLabel(CurrentFnSym);
300 /// runOnMachineFunction - This uses the printInstruction()
301 /// method to print assembly for each instruction.
303 bool ARMAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
304 AFI = MF.getInfo<ARMFunctionInfo>();
305 MCP = MF.getConstantPool();
307 return AsmPrinter::runOnMachineFunction(MF);
310 void ARMAsmPrinter::printOperand(const MachineInstr *MI, int OpNum,
311 raw_ostream &O, const char *Modifier) {
312 const MachineOperand &MO = MI->getOperand(OpNum);
313 unsigned TF = MO.getTargetFlags();
315 switch (MO.getType()) {
317 assert(0 && "<unknown operand type>");
318 case MachineOperand::MO_Register: {
319 unsigned Reg = MO.getReg();
320 assert(TargetRegisterInfo::isPhysicalRegister(Reg));
321 if (Modifier && strcmp(Modifier, "dregpair") == 0) {
322 unsigned DRegLo = TM.getRegisterInfo()->getSubReg(Reg, ARM::dsub_0);
323 unsigned DRegHi = TM.getRegisterInfo()->getSubReg(Reg, ARM::dsub_1);
325 << getRegisterName(DRegLo) << ',' << getRegisterName(DRegHi)
327 } else if (Modifier && strcmp(Modifier, "lane") == 0) {
328 unsigned RegNum = ARMRegisterInfo::getRegisterNumbering(Reg);
330 TM.getRegisterInfo()->getMatchingSuperReg(Reg, RegNum & 1 ? 2 : 1,
331 &ARM::DPR_VFP2RegClass);
332 O << getRegisterName(DReg) << '[' << (RegNum & 1) << ']';
334 assert(!MO.getSubReg() && "Subregs should be eliminated!");
335 O << getRegisterName(Reg);
339 case MachineOperand::MO_Immediate: {
340 int64_t Imm = MO.getImm();
342 if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
343 (TF & ARMII::MO_LO16))
345 else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
346 (TF & ARMII::MO_HI16))
351 case MachineOperand::MO_MachineBasicBlock:
352 O << *MO.getMBB()->getSymbol();
354 case MachineOperand::MO_GlobalAddress: {
355 bool isCallOp = Modifier && !strcmp(Modifier, "call");
356 const GlobalValue *GV = MO.getGlobal();
358 if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
359 (TF & ARMII::MO_LO16))
361 else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
362 (TF & ARMII::MO_HI16))
364 O << *Mang->getSymbol(GV);
366 printOffset(MO.getOffset(), O);
368 if (isCallOp && Subtarget->isTargetELF() &&
369 TM.getRelocationModel() == Reloc::PIC_)
373 case MachineOperand::MO_ExternalSymbol: {
374 bool isCallOp = Modifier && !strcmp(Modifier, "call");
375 O << *GetExternalSymbolSymbol(MO.getSymbolName());
377 if (isCallOp && Subtarget->isTargetELF() &&
378 TM.getRelocationModel() == Reloc::PIC_)
382 case MachineOperand::MO_ConstantPoolIndex:
383 O << *GetCPISymbol(MO.getIndex());
385 case MachineOperand::MO_JumpTableIndex:
386 O << *GetJTISymbol(MO.getIndex());
391 static void printSOImm(raw_ostream &O, int64_t V, bool VerboseAsm,
392 const MCAsmInfo *MAI) {
393 // Break it up into two parts that make up a shifter immediate.
394 V = ARM_AM::getSOImmVal(V);
395 assert(V != -1 && "Not a valid so_imm value!");
397 unsigned Imm = ARM_AM::getSOImmValImm(V);
398 unsigned Rot = ARM_AM::getSOImmValRot(V);
400 // Print low-level immediate formation info, per
401 // A5.1.3: "Data-processing operands - Immediate".
403 O << "#" << Imm << ", " << Rot;
404 // Pretty printed version.
406 O << "\t" << MAI->getCommentString() << ' ';
407 O << (int)ARM_AM::rotr32(Imm, Rot);
414 /// printSOImmOperand - SOImm is 4-bit rotate amount in bits 8-11 with 8-bit
415 /// immediate in bits 0-7.
416 void ARMAsmPrinter::printSOImmOperand(const MachineInstr *MI, int OpNum,
418 const MachineOperand &MO = MI->getOperand(OpNum);
419 assert(MO.isImm() && "Not a valid so_imm value!");
420 printSOImm(O, MO.getImm(), isVerbose(), MAI);
423 /// printSOImm2PartOperand - SOImm is broken into two pieces using a 'mov'
424 /// followed by an 'orr' to materialize.
425 void ARMAsmPrinter::printSOImm2PartOperand(const MachineInstr *MI, int OpNum,
427 const MachineOperand &MO = MI->getOperand(OpNum);
428 assert(MO.isImm() && "Not a valid so_imm value!");
429 unsigned V1 = ARM_AM::getSOImmTwoPartFirst(MO.getImm());
430 unsigned V2 = ARM_AM::getSOImmTwoPartSecond(MO.getImm());
431 printSOImm(O, V1, isVerbose(), MAI);
433 printPredicateOperand(MI, 2, O);
435 printOperand(MI, 0, O);
437 printOperand(MI, 0, O);
439 printSOImm(O, V2, isVerbose(), MAI);
442 // so_reg is a 4-operand unit corresponding to register forms of the A5.1
443 // "Addressing Mode 1 - Data-processing operands" forms. This includes:
445 // REG REG 0,SH_OPC - e.g. R5, ROR R3
446 // REG 0 IMM,SH_OPC - e.g. R5, LSL #3
447 void ARMAsmPrinter::printSORegOperand(const MachineInstr *MI, int Op,
449 const MachineOperand &MO1 = MI->getOperand(Op);
450 const MachineOperand &MO2 = MI->getOperand(Op+1);
451 const MachineOperand &MO3 = MI->getOperand(Op+2);
453 O << getRegisterName(MO1.getReg());
455 // Print the shift opc.
457 << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO3.getImm()))
461 O << getRegisterName(MO2.getReg());
462 assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0);
464 O << "#" << ARM_AM::getSORegOffset(MO3.getImm());
468 void ARMAsmPrinter::printAddrMode2Operand(const MachineInstr *MI, int Op,
470 const MachineOperand &MO1 = MI->getOperand(Op);
471 const MachineOperand &MO2 = MI->getOperand(Op+1);
472 const MachineOperand &MO3 = MI->getOperand(Op+2);
474 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
475 printOperand(MI, Op, O);
479 O << "[" << getRegisterName(MO1.getReg());
482 if (ARM_AM::getAM2Offset(MO3.getImm())) // Don't print +0.
484 << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm()))
485 << ARM_AM::getAM2Offset(MO3.getImm());
491 << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm()))
492 << getRegisterName(MO2.getReg());
494 if (unsigned ShImm = ARM_AM::getAM2Offset(MO3.getImm()))
496 << ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO3.getImm()))
501 void ARMAsmPrinter::printAddrMode2OffsetOperand(const MachineInstr *MI, int Op,
503 const MachineOperand &MO1 = MI->getOperand(Op);
504 const MachineOperand &MO2 = MI->getOperand(Op+1);
507 unsigned ImmOffs = ARM_AM::getAM2Offset(MO2.getImm());
509 << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO2.getImm()))
514 O << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO2.getImm()))
515 << getRegisterName(MO1.getReg());
517 if (unsigned ShImm = ARM_AM::getAM2Offset(MO2.getImm()))
519 << ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO2.getImm()))
523 void ARMAsmPrinter::printAddrMode3Operand(const MachineInstr *MI, int Op,
525 const MachineOperand &MO1 = MI->getOperand(Op);
526 const MachineOperand &MO2 = MI->getOperand(Op+1);
527 const MachineOperand &MO3 = MI->getOperand(Op+2);
529 assert(TargetRegisterInfo::isPhysicalRegister(MO1.getReg()));
530 O << "[" << getRegisterName(MO1.getReg());
534 << (char)ARM_AM::getAM3Op(MO3.getImm())
535 << getRegisterName(MO2.getReg())
540 if (unsigned ImmOffs = ARM_AM::getAM3Offset(MO3.getImm()))
542 << ARM_AM::getAddrOpcStr(ARM_AM::getAM3Op(MO3.getImm()))
547 void ARMAsmPrinter::printAddrMode3OffsetOperand(const MachineInstr *MI, int Op,
549 const MachineOperand &MO1 = MI->getOperand(Op);
550 const MachineOperand &MO2 = MI->getOperand(Op+1);
553 O << (char)ARM_AM::getAM3Op(MO2.getImm())
554 << getRegisterName(MO1.getReg());
558 unsigned ImmOffs = ARM_AM::getAM3Offset(MO2.getImm());
560 << ARM_AM::getAddrOpcStr(ARM_AM::getAM3Op(MO2.getImm()))
564 void ARMAsmPrinter::printAddrMode4Operand(const MachineInstr *MI, int Op,
566 const char *Modifier) {
567 const MachineOperand &MO2 = MI->getOperand(Op+1);
568 ARM_AM::AMSubMode Mode = ARM_AM::getAM4SubMode(MO2.getImm());
569 if (Modifier && strcmp(Modifier, "submode") == 0) {
570 O << ARM_AM::getAMSubModeStr(Mode);
571 } else if (Modifier && strcmp(Modifier, "wide") == 0) {
572 ARM_AM::AMSubMode Mode = ARM_AM::getAM4SubMode(MO2.getImm());
573 if (Mode == ARM_AM::ia)
576 printOperand(MI, Op, O);
580 void ARMAsmPrinter::printAddrMode5Operand(const MachineInstr *MI, int Op,
582 const char *Modifier) {
583 const MachineOperand &MO1 = MI->getOperand(Op);
584 const MachineOperand &MO2 = MI->getOperand(Op+1);
586 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
587 printOperand(MI, Op, O);
591 assert(TargetRegisterInfo::isPhysicalRegister(MO1.getReg()));
593 if (Modifier && strcmp(Modifier, "submode") == 0) {
594 ARM_AM::AMSubMode Mode = ARM_AM::getAM5SubMode(MO2.getImm());
595 O << ARM_AM::getAMSubModeStr(Mode);
597 } else if (Modifier && strcmp(Modifier, "base") == 0) {
598 // Used for FSTM{D|S} and LSTM{D|S} operations.
599 O << getRegisterName(MO1.getReg());
603 O << "[" << getRegisterName(MO1.getReg());
605 if (unsigned ImmOffs = ARM_AM::getAM5Offset(MO2.getImm())) {
607 << ARM_AM::getAddrOpcStr(ARM_AM::getAM5Op(MO2.getImm()))
613 void ARMAsmPrinter::printAddrMode6Operand(const MachineInstr *MI, int Op,
615 const MachineOperand &MO1 = MI->getOperand(Op);
616 const MachineOperand &MO2 = MI->getOperand(Op+1);
618 O << "[" << getRegisterName(MO1.getReg());
620 // FIXME: Both darwin as and GNU as violate ARM docs here.
621 O << ", :" << MO2.getImm();
626 void ARMAsmPrinter::printAddrMode6OffsetOperand(const MachineInstr *MI, int Op,
628 const MachineOperand &MO = MI->getOperand(Op);
629 if (MO.getReg() == 0)
632 O << ", " << getRegisterName(MO.getReg());
635 void ARMAsmPrinter::printAddrModePCOperand(const MachineInstr *MI, int Op,
637 const char *Modifier) {
638 if (Modifier && strcmp(Modifier, "label") == 0) {
639 printPCLabel(MI, Op+1, O);
643 const MachineOperand &MO1 = MI->getOperand(Op);
644 assert(TargetRegisterInfo::isPhysicalRegister(MO1.getReg()));
645 O << "[pc, " << getRegisterName(MO1.getReg()) << "]";
649 ARMAsmPrinter::printBitfieldInvMaskImmOperand(const MachineInstr *MI, int Op,
651 const MachineOperand &MO = MI->getOperand(Op);
652 uint32_t v = ~MO.getImm();
653 int32_t lsb = CountTrailingZeros_32(v);
654 int32_t width = (32 - CountLeadingZeros_32 (v)) - lsb;
655 assert(MO.isImm() && "Not a valid bf_inv_mask_imm value!");
656 O << "#" << lsb << ", #" << width;
659 //===--------------------------------------------------------------------===//
661 void ARMAsmPrinter::printThumbS4ImmOperand(const MachineInstr *MI, int Op,
663 O << "#" << MI->getOperand(Op).getImm() * 4;
667 ARMAsmPrinter::printThumbITMask(const MachineInstr *MI, int Op,
669 // (3 - the number of trailing zeros) is the number of then / else.
670 unsigned Mask = MI->getOperand(Op).getImm();
671 unsigned CondBit0 = Mask >> 4 & 1;
672 unsigned NumTZ = CountTrailingZeros_32(Mask);
673 assert(NumTZ <= 3 && "Invalid IT mask!");
674 for (unsigned Pos = 3, e = NumTZ; Pos > e; --Pos) {
675 bool T = ((Mask >> Pos) & 1) == CondBit0;
684 ARMAsmPrinter::printThumbAddrModeRROperand(const MachineInstr *MI, int Op,
686 const MachineOperand &MO1 = MI->getOperand(Op);
687 const MachineOperand &MO2 = MI->getOperand(Op+1);
688 O << "[" << getRegisterName(MO1.getReg());
689 O << ", " << getRegisterName(MO2.getReg()) << "]";
693 ARMAsmPrinter::printThumbAddrModeRI5Operand(const MachineInstr *MI, int Op,
696 const MachineOperand &MO1 = MI->getOperand(Op);
697 const MachineOperand &MO2 = MI->getOperand(Op+1);
698 const MachineOperand &MO3 = MI->getOperand(Op+2);
700 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
701 printOperand(MI, Op, O);
705 O << "[" << getRegisterName(MO1.getReg());
707 O << ", " << getRegisterName(MO3.getReg());
708 else if (unsigned ImmOffs = MO2.getImm())
709 O << ", #" << ImmOffs * Scale;
714 ARMAsmPrinter::printThumbAddrModeS1Operand(const MachineInstr *MI, int Op,
716 printThumbAddrModeRI5Operand(MI, Op, O, 1);
719 ARMAsmPrinter::printThumbAddrModeS2Operand(const MachineInstr *MI, int Op,
721 printThumbAddrModeRI5Operand(MI, Op, O, 2);
724 ARMAsmPrinter::printThumbAddrModeS4Operand(const MachineInstr *MI, int Op,
726 printThumbAddrModeRI5Operand(MI, Op, O, 4);
729 void ARMAsmPrinter::printThumbAddrModeSPOperand(const MachineInstr *MI,int Op,
731 const MachineOperand &MO1 = MI->getOperand(Op);
732 const MachineOperand &MO2 = MI->getOperand(Op+1);
733 O << "[" << getRegisterName(MO1.getReg());
734 if (unsigned ImmOffs = MO2.getImm())
735 O << ", #" << ImmOffs*4;
739 //===--------------------------------------------------------------------===//
741 // Constant shifts t2_so_reg is a 2-operand unit corresponding to the Thumb2
742 // register with shift forms.
744 // REG IMM, SH_OPC - e.g. R5, LSL #3
745 void ARMAsmPrinter::printT2SOOperand(const MachineInstr *MI, int OpNum,
747 const MachineOperand &MO1 = MI->getOperand(OpNum);
748 const MachineOperand &MO2 = MI->getOperand(OpNum+1);
750 unsigned Reg = MO1.getReg();
751 assert(TargetRegisterInfo::isPhysicalRegister(Reg));
752 O << getRegisterName(Reg);
754 // Print the shift opc.
756 << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO2.getImm()))
759 assert(MO2.isImm() && "Not a valid t2_so_reg value!");
760 O << "#" << ARM_AM::getSORegOffset(MO2.getImm());
763 void ARMAsmPrinter::printT2AddrModeImm12Operand(const MachineInstr *MI,
766 const MachineOperand &MO1 = MI->getOperand(OpNum);
767 const MachineOperand &MO2 = MI->getOperand(OpNum+1);
769 O << "[" << getRegisterName(MO1.getReg());
771 unsigned OffImm = MO2.getImm();
772 if (OffImm) // Don't print +0.
773 O << ", #" << OffImm;
777 void ARMAsmPrinter::printT2AddrModeImm8Operand(const MachineInstr *MI,
780 const MachineOperand &MO1 = MI->getOperand(OpNum);
781 const MachineOperand &MO2 = MI->getOperand(OpNum+1);
783 O << "[" << getRegisterName(MO1.getReg());
785 int32_t OffImm = (int32_t)MO2.getImm();
788 O << ", #-" << -OffImm;
790 O << ", #" << OffImm;
794 void ARMAsmPrinter::printT2AddrModeImm8s4Operand(const MachineInstr *MI,
797 const MachineOperand &MO1 = MI->getOperand(OpNum);
798 const MachineOperand &MO2 = MI->getOperand(OpNum+1);
800 O << "[" << getRegisterName(MO1.getReg());
802 int32_t OffImm = (int32_t)MO2.getImm() / 4;
805 O << ", #-" << -OffImm * 4;
807 O << ", #" << OffImm * 4;
811 void ARMAsmPrinter::printT2AddrModeImm8OffsetOperand(const MachineInstr *MI,
814 const MachineOperand &MO1 = MI->getOperand(OpNum);
815 int32_t OffImm = (int32_t)MO1.getImm();
818 O << "#-" << -OffImm;
823 void ARMAsmPrinter::printT2AddrModeSoRegOperand(const MachineInstr *MI,
826 const MachineOperand &MO1 = MI->getOperand(OpNum);
827 const MachineOperand &MO2 = MI->getOperand(OpNum+1);
828 const MachineOperand &MO3 = MI->getOperand(OpNum+2);
830 O << "[" << getRegisterName(MO1.getReg());
832 assert(MO2.getReg() && "Invalid so_reg load / store address!");
833 O << ", " << getRegisterName(MO2.getReg());
835 unsigned ShAmt = MO3.getImm();
837 assert(ShAmt <= 3 && "Not a valid Thumb2 addressing mode!");
838 O << ", lsl #" << ShAmt;
844 //===--------------------------------------------------------------------===//
846 void ARMAsmPrinter::printPredicateOperand(const MachineInstr *MI, int OpNum,
848 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
850 O << ARMCondCodeToString(CC);
853 void ARMAsmPrinter::printMandatoryPredicateOperand(const MachineInstr *MI,
856 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
857 O << ARMCondCodeToString(CC);
860 void ARMAsmPrinter::printSBitModifierOperand(const MachineInstr *MI, int OpNum,
862 unsigned Reg = MI->getOperand(OpNum).getReg();
864 assert(Reg == ARM::CPSR && "Expect ARM CPSR register!");
869 void ARMAsmPrinter::printPCLabel(const MachineInstr *MI, int OpNum,
871 int Id = (int)MI->getOperand(OpNum).getImm();
872 O << MAI->getPrivateGlobalPrefix()
873 << "PC" << getFunctionNumber() << "_" << Id;
876 void ARMAsmPrinter::printRegisterList(const MachineInstr *MI, int OpNum,
879 for (unsigned i = OpNum, e = MI->getNumOperands(); i != e; ++i) {
880 if (MI->getOperand(i).isImplicit())
882 if ((int)i != OpNum) O << ", ";
883 printOperand(MI, i, O);
888 void ARMAsmPrinter::printCPInstOperand(const MachineInstr *MI, int OpNum,
889 raw_ostream &O, const char *Modifier) {
890 assert(Modifier && "This operand only works with a modifier!");
891 // There are two aspects to a CONSTANTPOOL_ENTRY operand, the label and the
893 if (!strcmp(Modifier, "label")) {
894 unsigned ID = MI->getOperand(OpNum).getImm();
895 OutStreamer.EmitLabel(GetCPISymbol(ID));
897 assert(!strcmp(Modifier, "cpentry") && "Unknown modifier for CPE");
898 unsigned CPI = MI->getOperand(OpNum).getIndex();
900 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPI];
902 if (MCPE.isMachineConstantPoolEntry()) {
903 EmitMachineConstantPoolValue(MCPE.Val.MachineCPVal);
905 EmitGlobalConstant(MCPE.Val.ConstVal);
910 MCSymbol *ARMAsmPrinter::
911 GetARMSetPICJumpTableLabel2(unsigned uid, unsigned uid2,
912 const MachineBasicBlock *MBB) const {
913 SmallString<60> Name;
914 raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix()
915 << getFunctionNumber() << '_' << uid << '_' << uid2
916 << "_set_" << MBB->getNumber();
917 return OutContext.GetOrCreateSymbol(Name.str());
920 MCSymbol *ARMAsmPrinter::
921 GetARMJTIPICJumpTableLabel2(unsigned uid, unsigned uid2) const {
922 SmallString<60> Name;
923 raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix() << "JTI"
924 << getFunctionNumber() << '_' << uid << '_' << uid2;
925 return OutContext.GetOrCreateSymbol(Name.str());
928 void ARMAsmPrinter::printJTBlockOperand(const MachineInstr *MI, int OpNum,
930 assert(!Subtarget->isThumb2() && "Thumb2 should use double-jump jumptables!");
932 const MachineOperand &MO1 = MI->getOperand(OpNum);
933 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
935 unsigned JTI = MO1.getIndex();
936 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
937 // Can't use EmitLabel until instprinter happens, label comes out in the wrong
939 O << *JTISymbol << ":\n";
941 const char *JTEntryDirective = MAI->getData32bitsDirective();
943 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
944 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
945 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
946 bool UseSet= MAI->hasSetDirective() && TM.getRelocationModel() == Reloc::PIC_;
947 SmallPtrSet<MachineBasicBlock*, 8> JTSets;
948 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
949 MachineBasicBlock *MBB = JTBBs[i];
950 bool isNew = JTSets.insert(MBB);
952 if (UseSet && isNew) {
954 << *GetARMSetPICJumpTableLabel2(JTI, MO2.getImm(), MBB) << ','
955 << *MBB->getSymbol() << '-' << *JTISymbol << '\n';
958 O << JTEntryDirective << ' ';
960 O << *GetARMSetPICJumpTableLabel2(JTI, MO2.getImm(), MBB);
961 else if (TM.getRelocationModel() == Reloc::PIC_)
962 O << *MBB->getSymbol() << '-' << *JTISymbol;
964 O << *MBB->getSymbol();
971 void ARMAsmPrinter::printJT2BlockOperand(const MachineInstr *MI, int OpNum,
973 const MachineOperand &MO1 = MI->getOperand(OpNum);
974 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
975 unsigned JTI = MO1.getIndex();
977 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
979 // Can't use EmitLabel until instprinter happens, label comes out in the wrong
981 O << *JTISymbol << ":\n";
983 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
984 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
985 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
986 bool ByteOffset = false, HalfWordOffset = false;
987 if (MI->getOpcode() == ARM::t2TBB)
989 else if (MI->getOpcode() == ARM::t2TBH)
990 HalfWordOffset = true;
992 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
993 MachineBasicBlock *MBB = JTBBs[i];
995 O << MAI->getData8bitsDirective();
996 else if (HalfWordOffset)
997 O << MAI->getData16bitsDirective();
999 if (ByteOffset || HalfWordOffset)
1000 O << '(' << *MBB->getSymbol() << "-" << *JTISymbol << ")/2";
1002 O << "\tb.w " << *MBB->getSymbol();
1009 void ARMAsmPrinter::printTBAddrMode(const MachineInstr *MI, int OpNum,
1011 O << "[pc, " << getRegisterName(MI->getOperand(OpNum).getReg());
1012 if (MI->getOpcode() == ARM::t2TBH)
1017 void ARMAsmPrinter::printNoHashImmediate(const MachineInstr *MI, int OpNum,
1019 O << MI->getOperand(OpNum).getImm();
1022 void ARMAsmPrinter::printVFPf32ImmOperand(const MachineInstr *MI, int OpNum,
1024 const ConstantFP *FP = MI->getOperand(OpNum).getFPImm();
1025 O << '#' << FP->getValueAPF().convertToFloat();
1027 O << "\t\t" << MAI->getCommentString() << ' ';
1028 WriteAsOperand(O, FP, /*PrintType=*/false);
1032 void ARMAsmPrinter::printVFPf64ImmOperand(const MachineInstr *MI, int OpNum,
1034 const ConstantFP *FP = MI->getOperand(OpNum).getFPImm();
1035 O << '#' << FP->getValueAPF().convertToDouble();
1037 O << "\t\t" << MAI->getCommentString() << ' ';
1038 WriteAsOperand(O, FP, /*PrintType=*/false);
1042 bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
1043 unsigned AsmVariant, const char *ExtraCode,
1045 // Does this asm operand have a single letter operand modifier?
1046 if (ExtraCode && ExtraCode[0]) {
1047 if (ExtraCode[1] != 0) return true; // Unknown modifier.
1049 switch (ExtraCode[0]) {
1050 default: return true; // Unknown modifier.
1051 case 'a': // Print as a memory address.
1052 if (MI->getOperand(OpNum).isReg()) {
1053 O << "[" << getRegisterName(MI->getOperand(OpNum).getReg()) << "]";
1057 case 'c': // Don't print "#" before an immediate operand.
1058 if (!MI->getOperand(OpNum).isImm())
1060 printNoHashImmediate(MI, OpNum, O);
1062 case 'P': // Print a VFP double precision register.
1063 case 'q': // Print a NEON quad precision register.
1064 printOperand(MI, OpNum, O);
1067 if (TM.getTargetData()->isLittleEndian())
1071 if (TM.getTargetData()->isBigEndian())
1074 case 'H': // Write second word of DI / DF reference.
1075 // Verify that this operand has two consecutive registers.
1076 if (!MI->getOperand(OpNum).isReg() ||
1077 OpNum+1 == MI->getNumOperands() ||
1078 !MI->getOperand(OpNum+1).isReg())
1080 ++OpNum; // Return the high-part.
1084 printOperand(MI, OpNum, O);
1088 bool ARMAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
1089 unsigned OpNum, unsigned AsmVariant,
1090 const char *ExtraCode,
1092 if (ExtraCode && ExtraCode[0])
1093 return true; // Unknown modifier.
1095 const MachineOperand &MO = MI->getOperand(OpNum);
1096 assert(MO.isReg() && "unexpected inline asm memory operand");
1097 O << "[" << getRegisterName(MO.getReg()) << "]";
1101 void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) {
1103 printInstructionThroughMCStreamer(MI);
1107 if (MI->getOpcode() == ARM::CONSTPOOL_ENTRY)
1110 SmallString<128> Str;
1111 raw_svector_ostream OS(Str);
1112 if (MI->getOpcode() == ARM::DBG_VALUE) {
1113 unsigned NOps = MI->getNumOperands();
1115 OS << '\t' << MAI->getCommentString() << "DEBUG_VALUE: ";
1116 // cast away const; DIetc do not take const operands for some reason.
1117 DIVariable V(const_cast<MDNode *>(MI->getOperand(NOps-1).getMetadata()));
1120 // Frame address. Currently handles register +- offset only.
1121 assert(MI->getOperand(0).isReg() && MI->getOperand(1).isImm());
1122 OS << '['; printOperand(MI, 0, OS); OS << '+'; printOperand(MI, 1, OS);
1125 printOperand(MI, NOps-2, OS);
1126 OutStreamer.EmitRawText(OS.str());
1130 printInstruction(MI, OS);
1131 OutStreamer.EmitRawText(OS.str());
1133 // Make sure the instruction that follows TBB is 2-byte aligned.
1134 // FIXME: Constant island pass should insert an "ALIGN" instruction instead.
1135 if (MI->getOpcode() == ARM::t2TBB)
1139 void ARMAsmPrinter::EmitStartOfAsmFile(Module &M) {
1140 if (Subtarget->isTargetDarwin()) {
1141 Reloc::Model RelocM = TM.getRelocationModel();
1142 if (RelocM == Reloc::PIC_ || RelocM == Reloc::DynamicNoPIC) {
1143 // Declare all the text sections up front (before the DWARF sections
1144 // emitted by AsmPrinter::doInitialization) so the assembler will keep
1145 // them together at the beginning of the object file. This helps
1146 // avoid out-of-range branches that are due a fundamental limitation of
1147 // the way symbol offsets are encoded with the current Darwin ARM
1149 const TargetLoweringObjectFileMachO &TLOFMacho =
1150 static_cast<const TargetLoweringObjectFileMachO &>(
1151 getObjFileLowering());
1152 OutStreamer.SwitchSection(TLOFMacho.getTextSection());
1153 OutStreamer.SwitchSection(TLOFMacho.getTextCoalSection());
1154 OutStreamer.SwitchSection(TLOFMacho.getConstTextCoalSection());
1155 if (RelocM == Reloc::DynamicNoPIC) {
1156 const MCSection *sect =
1157 OutContext.getMachOSection("__TEXT", "__symbol_stub4",
1158 MCSectionMachO::S_SYMBOL_STUBS,
1159 12, SectionKind::getText());
1160 OutStreamer.SwitchSection(sect);
1162 const MCSection *sect =
1163 OutContext.getMachOSection("__TEXT", "__picsymbolstub4",
1164 MCSectionMachO::S_SYMBOL_STUBS,
1165 16, SectionKind::getText());
1166 OutStreamer.SwitchSection(sect);
1171 // Use unified assembler syntax.
1172 OutStreamer.EmitRawText(StringRef("\t.syntax unified"));
1174 // Emit ARM Build Attributes
1175 if (Subtarget->isTargetELF()) {
1177 std::string CPUString = Subtarget->getCPUString();
1178 if (CPUString != "generic")
1179 OutStreamer.EmitRawText("\t.cpu " + Twine(CPUString));
1181 // FIXME: Emit FPU type
1182 if (Subtarget->hasVFP2())
1183 OutStreamer.EmitRawText("\t.eabi_attribute " +
1184 Twine(ARMBuildAttrs::VFP_arch) + ", 2");
1186 // Signal various FP modes.
1187 if (!UnsafeFPMath) {
1188 OutStreamer.EmitRawText("\t.eabi_attribute " +
1189 Twine(ARMBuildAttrs::ABI_FP_denormal) + ", 1");
1190 OutStreamer.EmitRawText("\t.eabi_attribute " +
1191 Twine(ARMBuildAttrs::ABI_FP_exceptions) + ", 1");
1194 if (FiniteOnlyFPMath())
1195 OutStreamer.EmitRawText("\t.eabi_attribute " +
1196 Twine(ARMBuildAttrs::ABI_FP_number_model)+ ", 1");
1198 OutStreamer.EmitRawText("\t.eabi_attribute " +
1199 Twine(ARMBuildAttrs::ABI_FP_number_model)+ ", 3");
1201 // 8-bytes alignment stuff.
1202 OutStreamer.EmitRawText("\t.eabi_attribute " +
1203 Twine(ARMBuildAttrs::ABI_align8_needed) + ", 1");
1204 OutStreamer.EmitRawText("\t.eabi_attribute " +
1205 Twine(ARMBuildAttrs::ABI_align8_preserved) + ", 1");
1207 // Hard float. Use both S and D registers and conform to AAPCS-VFP.
1208 if (Subtarget->isAAPCS_ABI() && FloatABIType == FloatABI::Hard) {
1209 OutStreamer.EmitRawText("\t.eabi_attribute " +
1210 Twine(ARMBuildAttrs::ABI_HardFP_use) + ", 3");
1211 OutStreamer.EmitRawText("\t.eabi_attribute " +
1212 Twine(ARMBuildAttrs::ABI_VFP_args) + ", 1");
1214 // FIXME: Should we signal R9 usage?
1219 void ARMAsmPrinter::EmitEndOfAsmFile(Module &M) {
1220 if (Subtarget->isTargetDarwin()) {
1221 // All darwin targets use mach-o.
1222 const TargetLoweringObjectFileMachO &TLOFMacho =
1223 static_cast<const TargetLoweringObjectFileMachO &>(getObjFileLowering());
1224 MachineModuleInfoMachO &MMIMacho =
1225 MMI->getObjFileInfo<MachineModuleInfoMachO>();
1227 // Output non-lazy-pointers for external and common global variables.
1228 MachineModuleInfoMachO::SymbolListTy Stubs = MMIMacho.GetGVStubList();
1230 if (!Stubs.empty()) {
1231 // Switch with ".non_lazy_symbol_pointer" directive.
1232 OutStreamer.SwitchSection(TLOFMacho.getNonLazySymbolPointerSection());
1234 for (unsigned i = 0, e = Stubs.size(); i != e; ++i) {
1236 OutStreamer.EmitLabel(Stubs[i].first);
1237 // .indirect_symbol _foo
1238 MachineModuleInfoImpl::StubValueTy &MCSym = Stubs[i].second;
1239 OutStreamer.EmitSymbolAttribute(MCSym.getPointer(),MCSA_IndirectSymbol);
1242 // External to current translation unit.
1243 OutStreamer.EmitIntValue(0, 4/*size*/, 0/*addrspace*/);
1245 // Internal to current translation unit.
1247 // When we place the LSDA into the TEXT section, the type info pointers
1248 // need to be indirect and pc-rel. We accomplish this by using NLPs.
1249 // However, sometimes the types are local to the file. So we need to
1250 // fill in the value for the NLP in those cases.
1251 OutStreamer.EmitValue(MCSymbolRefExpr::Create(MCSym.getPointer(),
1253 4/*size*/, 0/*addrspace*/);
1257 OutStreamer.AddBlankLine();
1260 Stubs = MMIMacho.GetHiddenGVStubList();
1261 if (!Stubs.empty()) {
1262 OutStreamer.SwitchSection(getObjFileLowering().getDataSection());
1264 for (unsigned i = 0, e = Stubs.size(); i != e; ++i) {
1266 OutStreamer.EmitLabel(Stubs[i].first);
1268 OutStreamer.EmitValue(MCSymbolRefExpr::
1269 Create(Stubs[i].second.getPointer(),
1271 4/*size*/, 0/*addrspace*/);
1275 OutStreamer.AddBlankLine();
1278 // Funny Darwin hack: This flag tells the linker that no global symbols
1279 // contain code that falls through to other global symbols (e.g. the obvious
1280 // implementation of multiple entry points). If this doesn't occur, the
1281 // linker can safely perform dead code stripping. Since LLVM never
1282 // generates code that does this, it is always safe to set.
1283 OutStreamer.EmitAssemblerFlag(MCAF_SubsectionsViaSymbols);
1287 //===----------------------------------------------------------------------===//
1289 void ARMAsmPrinter::printInstructionThroughMCStreamer(const MachineInstr *MI) {
1290 ARMMCInstLower MCInstLowering(OutContext, *Mang, *this);
1291 switch (MI->getOpcode()) {
1292 case ARM::t2MOVi32imm:
1293 assert(0 && "Should be lowered by thumb2it pass");
1295 case ARM::PICADD: { // FIXME: Remove asm string from td file.
1296 // This is a pseudo op for a label + instruction sequence, which looks like:
1299 // This adds the address of LPC0 to r0.
1302 // FIXME: MOVE TO SHARED PLACE.
1303 unsigned Id = (unsigned)MI->getOperand(2).getImm();
1304 const char *Prefix = MAI->getPrivateGlobalPrefix();
1305 MCSymbol *Label =OutContext.GetOrCreateSymbol(Twine(Prefix)
1306 + "PC" + Twine(getFunctionNumber()) + "_" + Twine(Id));
1307 OutStreamer.EmitLabel(Label);
1310 // Form and emit tha dd.
1312 AddInst.setOpcode(ARM::ADDrr);
1313 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1314 AddInst.addOperand(MCOperand::CreateReg(ARM::PC));
1315 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1316 OutStreamer.EmitInstruction(AddInst);
1319 case ARM::CONSTPOOL_ENTRY: { // FIXME: Remove asm string from td file.
1320 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool
1321 /// in the function. The first operand is the ID# for this instruction, the
1322 /// second is the index into the MachineConstantPool that this is, the third
1323 /// is the size in bytes of this constant pool entry.
1324 unsigned LabelId = (unsigned)MI->getOperand(0).getImm();
1325 unsigned CPIdx = (unsigned)MI->getOperand(1).getIndex();
1328 OutStreamer.EmitLabel(GetCPISymbol(LabelId));
1330 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPIdx];
1331 if (MCPE.isMachineConstantPoolEntry())
1332 EmitMachineConstantPoolValue(MCPE.Val.MachineCPVal);
1334 EmitGlobalConstant(MCPE.Val.ConstVal);
1338 case ARM::MOVi2pieces: { // FIXME: Remove asmstring from td file.
1339 // This is a hack that lowers as a two instruction sequence.
1340 unsigned DstReg = MI->getOperand(0).getReg();
1341 unsigned ImmVal = (unsigned)MI->getOperand(1).getImm();
1343 unsigned SOImmValV1 = ARM_AM::getSOImmTwoPartFirst(ImmVal);
1344 unsigned SOImmValV2 = ARM_AM::getSOImmTwoPartSecond(ImmVal);
1348 TmpInst.setOpcode(ARM::MOVi);
1349 TmpInst.addOperand(MCOperand::CreateReg(DstReg));
1350 TmpInst.addOperand(MCOperand::CreateImm(SOImmValV1));
1353 TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
1354 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(3).getReg()));
1356 TmpInst.addOperand(MCOperand::CreateReg(0)); // cc_out
1357 OutStreamer.EmitInstruction(TmpInst);
1362 TmpInst.setOpcode(ARM::ORRri);
1363 TmpInst.addOperand(MCOperand::CreateReg(DstReg)); // dstreg
1364 TmpInst.addOperand(MCOperand::CreateReg(DstReg)); // inreg
1365 TmpInst.addOperand(MCOperand::CreateImm(SOImmValV2)); // so_imm
1367 TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
1368 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(3).getReg()));
1370 TmpInst.addOperand(MCOperand::CreateReg(0)); // cc_out
1371 OutStreamer.EmitInstruction(TmpInst);
1375 case ARM::MOVi32imm: { // FIXME: Remove asmstring from td file.
1376 // This is a hack that lowers as a two instruction sequence.
1377 unsigned DstReg = MI->getOperand(0).getReg();
1378 const MachineOperand &MO = MI->getOperand(1);
1381 unsigned ImmVal = (unsigned)MI->getOperand(1).getImm();
1382 V1 = MCOperand::CreateImm(ImmVal & 65535);
1383 V2 = MCOperand::CreateImm(ImmVal >> 16);
1384 } else if (MO.isGlobal()) {
1385 MCSymbol *Symbol = MCInstLowering.GetGlobalAddressSymbol(MO);
1386 const MCSymbolRefExpr *SymRef1 =
1387 MCSymbolRefExpr::Create(Symbol,
1388 MCSymbolRefExpr::VK_ARM_LO16, OutContext);
1389 const MCSymbolRefExpr *SymRef2 =
1390 MCSymbolRefExpr::Create(Symbol,
1391 MCSymbolRefExpr::VK_ARM_HI16, OutContext);
1392 V1 = MCOperand::CreateExpr(SymRef1);
1393 V2 = MCOperand::CreateExpr(SymRef2);
1396 llvm_unreachable("cannot handle this operand");
1401 TmpInst.setOpcode(ARM::MOVi16);
1402 TmpInst.addOperand(MCOperand::CreateReg(DstReg)); // dstreg
1403 TmpInst.addOperand(V1); // lower16(imm)
1406 TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
1407 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(3).getReg()));
1409 OutStreamer.EmitInstruction(TmpInst);
1414 TmpInst.setOpcode(ARM::MOVTi16);
1415 TmpInst.addOperand(MCOperand::CreateReg(DstReg)); // dstreg
1416 TmpInst.addOperand(MCOperand::CreateReg(DstReg)); // srcreg
1417 TmpInst.addOperand(V2); // upper16(imm)
1420 TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
1421 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(3).getReg()));
1423 OutStreamer.EmitInstruction(TmpInst);
1431 MCInstLowering.Lower(MI, TmpInst);
1432 OutStreamer.EmitInstruction(TmpInst);
1435 //===----------------------------------------------------------------------===//
1436 // Target Registry Stuff
1437 //===----------------------------------------------------------------------===//
1439 static MCInstPrinter *createARMMCInstPrinter(const Target &T,
1440 unsigned SyntaxVariant,
1441 const MCAsmInfo &MAI) {
1442 if (SyntaxVariant == 0)
1443 return new ARMInstPrinter(MAI, false);
1447 // Force static initialization.
1448 extern "C" void LLVMInitializeARMAsmPrinter() {
1449 RegisterAsmPrinter<ARMAsmPrinter> X(TheARMTarget);
1450 RegisterAsmPrinter<ARMAsmPrinter> Y(TheThumbTarget);
1452 TargetRegistry::RegisterMCInstPrinter(TheARMTarget, createARMMCInstPrinter);
1453 TargetRegistry::RegisterMCInstPrinter(TheThumbTarget, createARMMCInstPrinter);