1 //===-- ARMAsmPrinter.cpp - Print machine code to an ARM .s file ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains a printer that converts from our internal representation
11 // of machine-dependent LLVM code to GAS-format ARM assembly language.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "asm-printer"
17 #include "ARMBuildAttrs.h"
18 #include "ARMAddressingModes.h"
19 #include "ARMConstantPoolValue.h"
20 #include "ARMInstPrinter.h"
21 #include "ARMMachineFunctionInfo.h"
22 #include "ARMMCInstLower.h"
23 #include "ARMTargetMachine.h"
24 #include "llvm/Analysis/DebugInfo.h"
25 #include "llvm/Constants.h"
26 #include "llvm/Module.h"
27 #include "llvm/Type.h"
28 #include "llvm/Assembly/Writer.h"
29 #include "llvm/CodeGen/AsmPrinter.h"
30 #include "llvm/CodeGen/MachineModuleInfoImpls.h"
31 #include "llvm/CodeGen/MachineFunctionPass.h"
32 #include "llvm/CodeGen/MachineJumpTableInfo.h"
33 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
34 #include "llvm/MC/MCAsmInfo.h"
35 #include "llvm/MC/MCContext.h"
36 #include "llvm/MC/MCExpr.h"
37 #include "llvm/MC/MCInst.h"
38 #include "llvm/MC/MCSectionMachO.h"
39 #include "llvm/MC/MCStreamer.h"
40 #include "llvm/MC/MCSymbol.h"
41 #include "llvm/Target/Mangler.h"
42 #include "llvm/Target/TargetData.h"
43 #include "llvm/Target/TargetMachine.h"
44 #include "llvm/Target/TargetOptions.h"
45 #include "llvm/Target/TargetRegistry.h"
46 #include "llvm/ADT/SmallPtrSet.h"
47 #include "llvm/ADT/SmallString.h"
48 #include "llvm/ADT/StringExtras.h"
49 #include "llvm/Support/CommandLine.h"
50 #include "llvm/Support/ErrorHandling.h"
51 #include "llvm/Support/raw_ostream.h"
56 EnableMCInst("enable-arm-mcinst-printer", cl::Hidden,
57 cl::desc("enable experimental asmprinter gunk in the arm backend"));
60 class ARMAsmPrinter : public AsmPrinter {
62 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
63 /// make the right decision when printing asm code for different targets.
64 const ARMSubtarget *Subtarget;
66 /// AFI - Keep a pointer to ARMFunctionInfo for the current
70 /// MCP - Keep a pointer to constantpool entries of the current
72 const MachineConstantPool *MCP;
75 explicit ARMAsmPrinter(TargetMachine &TM, MCStreamer &Streamer)
76 : AsmPrinter(TM, Streamer), AFI(NULL), MCP(NULL) {
77 Subtarget = &TM.getSubtarget<ARMSubtarget>();
80 virtual const char *getPassName() const {
81 return "ARM Assembly Printer";
84 void printInstructionThroughMCStreamer(const MachineInstr *MI);
87 void printOperand(const MachineInstr *MI, int OpNum, raw_ostream &O,
88 const char *Modifier = 0);
89 void printSOImmOperand(const MachineInstr *MI, int OpNum, raw_ostream &O);
90 void printSOImm2PartOperand(const MachineInstr *MI, int OpNum,
92 void printSORegOperand(const MachineInstr *MI, int OpNum,
94 void printAddrMode2Operand(const MachineInstr *MI, int OpNum,
96 void printAddrMode2OffsetOperand(const MachineInstr *MI, int OpNum,
98 void printAddrMode3Operand(const MachineInstr *MI, int OpNum,
100 void printAddrMode3OffsetOperand(const MachineInstr *MI, int OpNum,
102 void printAddrMode4Operand(const MachineInstr *MI, int OpNum,raw_ostream &O,
103 const char *Modifier = 0);
104 void printAddrMode5Operand(const MachineInstr *MI, int OpNum,raw_ostream &O,
105 const char *Modifier = 0);
106 void printAddrMode6Operand(const MachineInstr *MI, int OpNum,
108 void printAddrMode6OffsetOperand(const MachineInstr *MI, int OpNum,
110 void printAddrModePCOperand(const MachineInstr *MI, int OpNum,
112 const char *Modifier = 0);
113 void printBitfieldInvMaskImmOperand (const MachineInstr *MI, int OpNum,
116 void printThumbS4ImmOperand(const MachineInstr *MI, int OpNum,
118 void printThumbITMask(const MachineInstr *MI, int OpNum, raw_ostream &O);
119 void printThumbAddrModeRROperand(const MachineInstr *MI, int OpNum,
121 void printThumbAddrModeRI5Operand(const MachineInstr *MI, int OpNum,
124 void printThumbAddrModeS1Operand(const MachineInstr *MI, int OpNum,
126 void printThumbAddrModeS2Operand(const MachineInstr *MI, int OpNum,
128 void printThumbAddrModeS4Operand(const MachineInstr *MI, int OpNum,
130 void printThumbAddrModeSPOperand(const MachineInstr *MI, int OpNum,
133 void printT2SOOperand(const MachineInstr *MI, int OpNum, raw_ostream &O);
134 void printT2AddrModeImm12Operand(const MachineInstr *MI, int OpNum,
136 void printT2AddrModeImm8Operand(const MachineInstr *MI, int OpNum,
138 void printT2AddrModeImm8s4Operand(const MachineInstr *MI, int OpNum,
140 void printT2AddrModeImm8OffsetOperand(const MachineInstr *MI, int OpNum,
142 void printT2AddrModeImm8s4OffsetOperand(const MachineInstr *MI, int OpNum,
144 void printT2AddrModeSoRegOperand(const MachineInstr *MI, int OpNum,
147 void printCPSOptionOperand(const MachineInstr *MI, int OpNum,
149 void printMSRMaskOperand(const MachineInstr *MI, int OpNum,
151 void printNegZeroOperand(const MachineInstr *MI, int OpNum,
153 void printPredicateOperand(const MachineInstr *MI, int OpNum,
155 void printMandatoryPredicateOperand(const MachineInstr *MI, int OpNum,
157 void printSBitModifierOperand(const MachineInstr *MI, int OpNum,
159 void printPCLabel(const MachineInstr *MI, int OpNum,
161 void printRegisterList(const MachineInstr *MI, int OpNum,
163 void printCPInstOperand(const MachineInstr *MI, int OpNum,
165 const char *Modifier);
166 void printJTBlockOperand(const MachineInstr *MI, int OpNum,
168 void printJT2BlockOperand(const MachineInstr *MI, int OpNum,
170 void printTBAddrMode(const MachineInstr *MI, int OpNum,
172 void printNoHashImmediate(const MachineInstr *MI, int OpNum,
174 void printVFPf32ImmOperand(const MachineInstr *MI, int OpNum,
176 void printVFPf64ImmOperand(const MachineInstr *MI, int OpNum,
178 void printNEONModImmOperand(const MachineInstr *MI, int OpNum,
181 virtual bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
182 unsigned AsmVariant, const char *ExtraCode,
184 virtual bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNum,
186 const char *ExtraCode, raw_ostream &O);
188 void printInstruction(const MachineInstr *MI, raw_ostream &O); // autogen
189 static const char *getRegisterName(unsigned RegNo);
191 virtual void EmitInstruction(const MachineInstr *MI);
192 bool runOnMachineFunction(MachineFunction &F);
194 virtual void EmitConstantPool() {} // we emit constant pools customly!
195 virtual void EmitFunctionEntryLabel();
196 void EmitStartOfAsmFile(Module &M);
197 void EmitEndOfAsmFile(Module &M);
199 MCSymbol *GetARMSetPICJumpTableLabel2(unsigned uid, unsigned uid2,
200 const MachineBasicBlock *MBB) const;
201 MCSymbol *GetARMJTIPICJumpTableLabel2(unsigned uid, unsigned uid2) const;
203 /// EmitMachineConstantPoolValue - Print a machine constantpool value to
205 virtual void EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV) {
206 SmallString<128> Str;
207 raw_svector_ostream OS(Str);
208 EmitMachineConstantPoolValue(MCPV, OS);
209 OutStreamer.EmitRawText(OS.str());
212 void EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV,
214 switch (TM.getTargetData()->getTypeAllocSize(MCPV->getType())) {
215 case 1: O << MAI->getData8bitsDirective(0); break;
216 case 2: O << MAI->getData16bitsDirective(0); break;
217 case 4: O << MAI->getData32bitsDirective(0); break;
218 default: assert(0 && "Unknown CPV size");
221 ARMConstantPoolValue *ACPV = static_cast<ARMConstantPoolValue*>(MCPV);
223 if (ACPV->isLSDA()) {
224 O << MAI->getPrivateGlobalPrefix() << "_LSDA_" << getFunctionNumber();
225 } else if (ACPV->isBlockAddress()) {
226 O << *GetBlockAddressSymbol(ACPV->getBlockAddress());
227 } else if (ACPV->isGlobalValue()) {
228 const GlobalValue *GV = ACPV->getGV();
229 bool isIndirect = Subtarget->isTargetDarwin() &&
230 Subtarget->GVIsIndirectSymbol(GV, TM.getRelocationModel());
232 O << *Mang->getSymbol(GV);
234 // FIXME: Remove this when Darwin transition to @GOT like syntax.
235 MCSymbol *Sym = GetSymbolWithGlobalValueBase(GV, "$non_lazy_ptr");
238 MachineModuleInfoMachO &MMIMachO =
239 MMI->getObjFileInfo<MachineModuleInfoMachO>();
240 MachineModuleInfoImpl::StubValueTy &StubSym =
241 GV->hasHiddenVisibility() ? MMIMachO.getHiddenGVStubEntry(Sym) :
242 MMIMachO.getGVStubEntry(Sym);
243 if (StubSym.getPointer() == 0)
244 StubSym = MachineModuleInfoImpl::
245 StubValueTy(Mang->getSymbol(GV), !GV->hasInternalLinkage());
248 assert(ACPV->isExtSymbol() && "unrecognized constant pool value");
249 O << *GetExternalSymbolSymbol(ACPV->getSymbol());
252 if (ACPV->hasModifier()) O << "(" << ACPV->getModifier() << ")";
253 if (ACPV->getPCAdjustment() != 0) {
254 O << "-(" << MAI->getPrivateGlobalPrefix() << "PC"
255 << getFunctionNumber() << "_" << ACPV->getLabelId()
256 << "+" << (unsigned)ACPV->getPCAdjustment();
257 if (ACPV->mustAddCurrentAddress())
263 } // end of anonymous namespace
265 #include "ARMGenAsmWriter.inc"
267 void ARMAsmPrinter::EmitFunctionEntryLabel() {
268 if (AFI->isThumbFunction()) {
269 OutStreamer.EmitRawText(StringRef("\t.code\t16"));
270 if (!Subtarget->isTargetDarwin())
271 OutStreamer.EmitRawText(StringRef("\t.thumb_func"));
273 // This needs to emit to a temporary string to get properly quoted
274 // MCSymbols when they have spaces in them.
275 SmallString<128> Tmp;
276 raw_svector_ostream OS(Tmp);
277 OS << "\t.thumb_func\t" << *CurrentFnSym;
278 OutStreamer.EmitRawText(OS.str());
282 OutStreamer.EmitLabel(CurrentFnSym);
285 /// runOnMachineFunction - This uses the printInstruction()
286 /// method to print assembly for each instruction.
288 bool ARMAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
289 AFI = MF.getInfo<ARMFunctionInfo>();
290 MCP = MF.getConstantPool();
292 return AsmPrinter::runOnMachineFunction(MF);
295 void ARMAsmPrinter::printOperand(const MachineInstr *MI, int OpNum,
296 raw_ostream &O, const char *Modifier) {
297 const MachineOperand &MO = MI->getOperand(OpNum);
298 unsigned TF = MO.getTargetFlags();
300 switch (MO.getType()) {
302 assert(0 && "<unknown operand type>");
303 case MachineOperand::MO_Register: {
304 unsigned Reg = MO.getReg();
305 assert(TargetRegisterInfo::isPhysicalRegister(Reg));
306 if (Modifier && strcmp(Modifier, "dregpair") == 0) {
307 unsigned DRegLo = TM.getRegisterInfo()->getSubReg(Reg, ARM::dsub_0);
308 unsigned DRegHi = TM.getRegisterInfo()->getSubReg(Reg, ARM::dsub_1);
310 << getRegisterName(DRegLo) << ',' << getRegisterName(DRegHi)
312 } else if (Modifier && strcmp(Modifier, "lane") == 0) {
313 unsigned RegNum = ARMRegisterInfo::getRegisterNumbering(Reg);
315 TM.getRegisterInfo()->getMatchingSuperReg(Reg,
316 RegNum & 1 ? ARM::ssub_1 : ARM::ssub_0, &ARM::DPR_VFP2RegClass);
317 O << getRegisterName(DReg) << '[' << (RegNum & 1) << ']';
319 assert(!MO.getSubReg() && "Subregs should be eliminated!");
320 O << getRegisterName(Reg);
324 case MachineOperand::MO_Immediate: {
325 int64_t Imm = MO.getImm();
327 if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
328 (TF & ARMII::MO_LO16))
330 else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
331 (TF & ARMII::MO_HI16))
336 case MachineOperand::MO_MachineBasicBlock:
337 O << *MO.getMBB()->getSymbol();
339 case MachineOperand::MO_GlobalAddress: {
340 bool isCallOp = Modifier && !strcmp(Modifier, "call");
341 const GlobalValue *GV = MO.getGlobal();
343 if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
344 (TF & ARMII::MO_LO16))
346 else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
347 (TF & ARMII::MO_HI16))
349 O << *Mang->getSymbol(GV);
351 printOffset(MO.getOffset(), O);
353 if (isCallOp && Subtarget->isTargetELF() &&
354 TM.getRelocationModel() == Reloc::PIC_)
358 case MachineOperand::MO_ExternalSymbol: {
359 bool isCallOp = Modifier && !strcmp(Modifier, "call");
360 O << *GetExternalSymbolSymbol(MO.getSymbolName());
362 if (isCallOp && Subtarget->isTargetELF() &&
363 TM.getRelocationModel() == Reloc::PIC_)
367 case MachineOperand::MO_ConstantPoolIndex:
368 O << *GetCPISymbol(MO.getIndex());
370 case MachineOperand::MO_JumpTableIndex:
371 O << *GetJTISymbol(MO.getIndex());
376 static void printSOImm(raw_ostream &O, int64_t V, bool VerboseAsm,
377 const MCAsmInfo *MAI) {
378 // Break it up into two parts that make up a shifter immediate.
379 V = ARM_AM::getSOImmVal(V);
380 assert(V != -1 && "Not a valid so_imm value!");
382 unsigned Imm = ARM_AM::getSOImmValImm(V);
383 unsigned Rot = ARM_AM::getSOImmValRot(V);
385 // Print low-level immediate formation info, per
386 // A5.1.3: "Data-processing operands - Immediate".
388 O << "#" << Imm << ", " << Rot;
389 // Pretty printed version.
391 O << "\t" << MAI->getCommentString() << ' ';
392 O << (int)ARM_AM::rotr32(Imm, Rot);
399 /// printSOImmOperand - SOImm is 4-bit rotate amount in bits 8-11 with 8-bit
400 /// immediate in bits 0-7.
401 void ARMAsmPrinter::printSOImmOperand(const MachineInstr *MI, int OpNum,
403 const MachineOperand &MO = MI->getOperand(OpNum);
404 assert(MO.isImm() && "Not a valid so_imm value!");
405 printSOImm(O, MO.getImm(), isVerbose(), MAI);
408 /// printSOImm2PartOperand - SOImm is broken into two pieces using a 'mov'
409 /// followed by an 'orr' to materialize.
410 void ARMAsmPrinter::printSOImm2PartOperand(const MachineInstr *MI, int OpNum,
412 const MachineOperand &MO = MI->getOperand(OpNum);
413 assert(MO.isImm() && "Not a valid so_imm value!");
414 unsigned V1 = ARM_AM::getSOImmTwoPartFirst(MO.getImm());
415 unsigned V2 = ARM_AM::getSOImmTwoPartSecond(MO.getImm());
416 printSOImm(O, V1, isVerbose(), MAI);
418 printPredicateOperand(MI, 2, O);
420 printOperand(MI, 0, O);
422 printOperand(MI, 0, O);
424 printSOImm(O, V2, isVerbose(), MAI);
427 // so_reg is a 4-operand unit corresponding to register forms of the A5.1
428 // "Addressing Mode 1 - Data-processing operands" forms. This includes:
430 // REG REG 0,SH_OPC - e.g. R5, ROR R3
431 // REG 0 IMM,SH_OPC - e.g. R5, LSL #3
432 void ARMAsmPrinter::printSORegOperand(const MachineInstr *MI, int Op,
434 const MachineOperand &MO1 = MI->getOperand(Op);
435 const MachineOperand &MO2 = MI->getOperand(Op+1);
436 const MachineOperand &MO3 = MI->getOperand(Op+2);
438 O << getRegisterName(MO1.getReg());
440 // Print the shift opc.
442 << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO3.getImm()))
446 O << getRegisterName(MO2.getReg());
447 assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0);
449 O << "#" << ARM_AM::getSORegOffset(MO3.getImm());
453 void ARMAsmPrinter::printAddrMode2Operand(const MachineInstr *MI, int Op,
455 const MachineOperand &MO1 = MI->getOperand(Op);
456 const MachineOperand &MO2 = MI->getOperand(Op+1);
457 const MachineOperand &MO3 = MI->getOperand(Op+2);
459 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
460 printOperand(MI, Op, O);
464 O << "[" << getRegisterName(MO1.getReg());
467 if (ARM_AM::getAM2Offset(MO3.getImm())) // Don't print +0.
469 << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm()))
470 << ARM_AM::getAM2Offset(MO3.getImm());
476 << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm()))
477 << getRegisterName(MO2.getReg());
479 if (unsigned ShImm = ARM_AM::getAM2Offset(MO3.getImm()))
481 << ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO3.getImm()))
486 void ARMAsmPrinter::printAddrMode2OffsetOperand(const MachineInstr *MI, int Op,
488 const MachineOperand &MO1 = MI->getOperand(Op);
489 const MachineOperand &MO2 = MI->getOperand(Op+1);
492 unsigned ImmOffs = ARM_AM::getAM2Offset(MO2.getImm());
494 << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO2.getImm()))
499 O << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO2.getImm()))
500 << getRegisterName(MO1.getReg());
502 if (unsigned ShImm = ARM_AM::getAM2Offset(MO2.getImm()))
504 << ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO2.getImm()))
508 void ARMAsmPrinter::printAddrMode3Operand(const MachineInstr *MI, int Op,
510 const MachineOperand &MO1 = MI->getOperand(Op);
511 const MachineOperand &MO2 = MI->getOperand(Op+1);
512 const MachineOperand &MO3 = MI->getOperand(Op+2);
514 assert(TargetRegisterInfo::isPhysicalRegister(MO1.getReg()));
515 O << "[" << getRegisterName(MO1.getReg());
519 << (char)ARM_AM::getAM3Op(MO3.getImm())
520 << getRegisterName(MO2.getReg())
525 if (unsigned ImmOffs = ARM_AM::getAM3Offset(MO3.getImm()))
527 << ARM_AM::getAddrOpcStr(ARM_AM::getAM3Op(MO3.getImm()))
532 void ARMAsmPrinter::printAddrMode3OffsetOperand(const MachineInstr *MI, int Op,
534 const MachineOperand &MO1 = MI->getOperand(Op);
535 const MachineOperand &MO2 = MI->getOperand(Op+1);
538 O << (char)ARM_AM::getAM3Op(MO2.getImm())
539 << getRegisterName(MO1.getReg());
543 unsigned ImmOffs = ARM_AM::getAM3Offset(MO2.getImm());
545 << ARM_AM::getAddrOpcStr(ARM_AM::getAM3Op(MO2.getImm()))
549 void ARMAsmPrinter::printAddrMode4Operand(const MachineInstr *MI, int Op,
551 const char *Modifier) {
552 const MachineOperand &MO2 = MI->getOperand(Op+1);
553 ARM_AM::AMSubMode Mode = ARM_AM::getAM4SubMode(MO2.getImm());
554 if (Modifier && strcmp(Modifier, "submode") == 0) {
555 O << ARM_AM::getAMSubModeStr(Mode);
556 } else if (Modifier && strcmp(Modifier, "wide") == 0) {
557 ARM_AM::AMSubMode Mode = ARM_AM::getAM4SubMode(MO2.getImm());
558 if (Mode == ARM_AM::ia)
561 printOperand(MI, Op, O);
565 void ARMAsmPrinter::printAddrMode5Operand(const MachineInstr *MI, int Op,
567 const char *Modifier) {
568 const MachineOperand &MO1 = MI->getOperand(Op);
569 const MachineOperand &MO2 = MI->getOperand(Op+1);
571 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
572 printOperand(MI, Op, O);
576 assert(TargetRegisterInfo::isPhysicalRegister(MO1.getReg()));
578 if (Modifier && strcmp(Modifier, "submode") == 0) {
579 ARM_AM::AMSubMode Mode = ARM_AM::getAM5SubMode(MO2.getImm());
580 O << ARM_AM::getAMSubModeStr(Mode);
582 } else if (Modifier && strcmp(Modifier, "base") == 0) {
583 // Used for FSTM{D|S} and LSTM{D|S} operations.
584 O << getRegisterName(MO1.getReg());
588 O << "[" << getRegisterName(MO1.getReg());
590 if (unsigned ImmOffs = ARM_AM::getAM5Offset(MO2.getImm())) {
592 << ARM_AM::getAddrOpcStr(ARM_AM::getAM5Op(MO2.getImm()))
598 void ARMAsmPrinter::printAddrMode6Operand(const MachineInstr *MI, int Op,
600 const MachineOperand &MO1 = MI->getOperand(Op);
601 const MachineOperand &MO2 = MI->getOperand(Op+1);
603 O << "[" << getRegisterName(MO1.getReg());
605 unsigned Align = MO2.getImm();
606 assert((Align == 8 || Align == 16 || Align == 32) &&
607 "unexpected NEON load/store alignment");
609 // FIXME: Both darwin as and GNU as violate ARM docs here.
615 void ARMAsmPrinter::printAddrMode6OffsetOperand(const MachineInstr *MI, int Op,
617 const MachineOperand &MO = MI->getOperand(Op);
618 if (MO.getReg() == 0)
621 O << ", " << getRegisterName(MO.getReg());
624 void ARMAsmPrinter::printAddrModePCOperand(const MachineInstr *MI, int Op,
626 const char *Modifier) {
627 if (Modifier && strcmp(Modifier, "label") == 0) {
628 printPCLabel(MI, Op+1, O);
632 const MachineOperand &MO1 = MI->getOperand(Op);
633 assert(TargetRegisterInfo::isPhysicalRegister(MO1.getReg()));
634 O << "[pc, " << getRegisterName(MO1.getReg()) << "]";
638 ARMAsmPrinter::printBitfieldInvMaskImmOperand(const MachineInstr *MI, int Op,
640 const MachineOperand &MO = MI->getOperand(Op);
641 uint32_t v = ~MO.getImm();
642 int32_t lsb = CountTrailingZeros_32(v);
643 int32_t width = (32 - CountLeadingZeros_32 (v)) - lsb;
644 assert(MO.isImm() && "Not a valid bf_inv_mask_imm value!");
645 O << "#" << lsb << ", #" << width;
648 //===--------------------------------------------------------------------===//
650 void ARMAsmPrinter::printThumbS4ImmOperand(const MachineInstr *MI, int Op,
652 O << "#" << MI->getOperand(Op).getImm() * 4;
656 ARMAsmPrinter::printThumbITMask(const MachineInstr *MI, int Op,
658 // (3 - the number of trailing zeros) is the number of then / else.
659 unsigned Mask = MI->getOperand(Op).getImm();
660 unsigned CondBit0 = Mask >> 4 & 1;
661 unsigned NumTZ = CountTrailingZeros_32(Mask);
662 assert(NumTZ <= 3 && "Invalid IT mask!");
663 for (unsigned Pos = 3, e = NumTZ; Pos > e; --Pos) {
664 bool T = ((Mask >> Pos) & 1) == CondBit0;
673 ARMAsmPrinter::printThumbAddrModeRROperand(const MachineInstr *MI, int Op,
675 const MachineOperand &MO1 = MI->getOperand(Op);
676 const MachineOperand &MO2 = MI->getOperand(Op+1);
677 O << "[" << getRegisterName(MO1.getReg());
678 O << ", " << getRegisterName(MO2.getReg()) << "]";
682 ARMAsmPrinter::printThumbAddrModeRI5Operand(const MachineInstr *MI, int Op,
685 const MachineOperand &MO1 = MI->getOperand(Op);
686 const MachineOperand &MO2 = MI->getOperand(Op+1);
687 const MachineOperand &MO3 = MI->getOperand(Op+2);
689 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
690 printOperand(MI, Op, O);
694 O << "[" << getRegisterName(MO1.getReg());
696 O << ", " << getRegisterName(MO3.getReg());
697 else if (unsigned ImmOffs = MO2.getImm())
698 O << ", #" << ImmOffs * Scale;
703 ARMAsmPrinter::printThumbAddrModeS1Operand(const MachineInstr *MI, int Op,
705 printThumbAddrModeRI5Operand(MI, Op, O, 1);
708 ARMAsmPrinter::printThumbAddrModeS2Operand(const MachineInstr *MI, int Op,
710 printThumbAddrModeRI5Operand(MI, Op, O, 2);
713 ARMAsmPrinter::printThumbAddrModeS4Operand(const MachineInstr *MI, int Op,
715 printThumbAddrModeRI5Operand(MI, Op, O, 4);
718 void ARMAsmPrinter::printThumbAddrModeSPOperand(const MachineInstr *MI,int Op,
720 const MachineOperand &MO1 = MI->getOperand(Op);
721 const MachineOperand &MO2 = MI->getOperand(Op+1);
722 O << "[" << getRegisterName(MO1.getReg());
723 if (unsigned ImmOffs = MO2.getImm())
724 O << ", #" << ImmOffs*4;
728 //===--------------------------------------------------------------------===//
730 // Constant shifts t2_so_reg is a 2-operand unit corresponding to the Thumb2
731 // register with shift forms.
733 // REG IMM, SH_OPC - e.g. R5, LSL #3
734 void ARMAsmPrinter::printT2SOOperand(const MachineInstr *MI, int OpNum,
736 const MachineOperand &MO1 = MI->getOperand(OpNum);
737 const MachineOperand &MO2 = MI->getOperand(OpNum+1);
739 unsigned Reg = MO1.getReg();
740 assert(TargetRegisterInfo::isPhysicalRegister(Reg));
741 O << getRegisterName(Reg);
743 // Print the shift opc.
745 << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO2.getImm()))
748 assert(MO2.isImm() && "Not a valid t2_so_reg value!");
749 O << "#" << ARM_AM::getSORegOffset(MO2.getImm());
752 void ARMAsmPrinter::printT2AddrModeImm12Operand(const MachineInstr *MI,
755 const MachineOperand &MO1 = MI->getOperand(OpNum);
756 const MachineOperand &MO2 = MI->getOperand(OpNum+1);
758 O << "[" << getRegisterName(MO1.getReg());
760 unsigned OffImm = MO2.getImm();
761 if (OffImm) // Don't print +0.
762 O << ", #" << OffImm;
766 void ARMAsmPrinter::printT2AddrModeImm8Operand(const MachineInstr *MI,
769 const MachineOperand &MO1 = MI->getOperand(OpNum);
770 const MachineOperand &MO2 = MI->getOperand(OpNum+1);
772 O << "[" << getRegisterName(MO1.getReg());
774 int32_t OffImm = (int32_t)MO2.getImm();
777 O << ", #-" << -OffImm;
779 O << ", #" << OffImm;
783 void ARMAsmPrinter::printT2AddrModeImm8s4Operand(const MachineInstr *MI,
786 const MachineOperand &MO1 = MI->getOperand(OpNum);
787 const MachineOperand &MO2 = MI->getOperand(OpNum+1);
789 O << "[" << getRegisterName(MO1.getReg());
791 int32_t OffImm = (int32_t)MO2.getImm() / 4;
794 O << ", #-" << -OffImm * 4;
796 O << ", #" << OffImm * 4;
800 void ARMAsmPrinter::printT2AddrModeImm8OffsetOperand(const MachineInstr *MI,
803 const MachineOperand &MO1 = MI->getOperand(OpNum);
804 int32_t OffImm = (int32_t)MO1.getImm();
807 O << "#-" << -OffImm;
812 void ARMAsmPrinter::printT2AddrModeSoRegOperand(const MachineInstr *MI,
815 const MachineOperand &MO1 = MI->getOperand(OpNum);
816 const MachineOperand &MO2 = MI->getOperand(OpNum+1);
817 const MachineOperand &MO3 = MI->getOperand(OpNum+2);
819 O << "[" << getRegisterName(MO1.getReg());
821 assert(MO2.getReg() && "Invalid so_reg load / store address!");
822 O << ", " << getRegisterName(MO2.getReg());
824 unsigned ShAmt = MO3.getImm();
826 assert(ShAmt <= 3 && "Not a valid Thumb2 addressing mode!");
827 O << ", lsl #" << ShAmt;
833 //===--------------------------------------------------------------------===//
835 void ARMAsmPrinter::printPredicateOperand(const MachineInstr *MI, int OpNum,
837 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
839 O << ARMCondCodeToString(CC);
842 void ARMAsmPrinter::printMandatoryPredicateOperand(const MachineInstr *MI,
845 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
846 O << ARMCondCodeToString(CC);
849 void ARMAsmPrinter::printSBitModifierOperand(const MachineInstr *MI, int OpNum,
851 unsigned Reg = MI->getOperand(OpNum).getReg();
853 assert(Reg == ARM::CPSR && "Expect ARM CPSR register!");
858 void ARMAsmPrinter::printPCLabel(const MachineInstr *MI, int OpNum,
860 int Id = (int)MI->getOperand(OpNum).getImm();
861 O << MAI->getPrivateGlobalPrefix()
862 << "PC" << getFunctionNumber() << "_" << Id;
865 void ARMAsmPrinter::printRegisterList(const MachineInstr *MI, int OpNum,
868 for (unsigned i = OpNum, e = MI->getNumOperands(); i != e; ++i) {
869 if (MI->getOperand(i).isImplicit())
871 if ((int)i != OpNum) O << ", ";
872 printOperand(MI, i, O);
877 void ARMAsmPrinter::printCPInstOperand(const MachineInstr *MI, int OpNum,
878 raw_ostream &O, const char *Modifier) {
879 assert(Modifier && "This operand only works with a modifier!");
880 // There are two aspects to a CONSTANTPOOL_ENTRY operand, the label and the
882 if (!strcmp(Modifier, "label")) {
883 unsigned ID = MI->getOperand(OpNum).getImm();
884 OutStreamer.EmitLabel(GetCPISymbol(ID));
886 assert(!strcmp(Modifier, "cpentry") && "Unknown modifier for CPE");
887 unsigned CPI = MI->getOperand(OpNum).getIndex();
889 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPI];
891 if (MCPE.isMachineConstantPoolEntry()) {
892 EmitMachineConstantPoolValue(MCPE.Val.MachineCPVal);
894 EmitGlobalConstant(MCPE.Val.ConstVal);
899 MCSymbol *ARMAsmPrinter::
900 GetARMSetPICJumpTableLabel2(unsigned uid, unsigned uid2,
901 const MachineBasicBlock *MBB) const {
902 SmallString<60> Name;
903 raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix()
904 << getFunctionNumber() << '_' << uid << '_' << uid2
905 << "_set_" << MBB->getNumber();
906 return OutContext.GetOrCreateSymbol(Name.str());
909 MCSymbol *ARMAsmPrinter::
910 GetARMJTIPICJumpTableLabel2(unsigned uid, unsigned uid2) const {
911 SmallString<60> Name;
912 raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix() << "JTI"
913 << getFunctionNumber() << '_' << uid << '_' << uid2;
914 return OutContext.GetOrCreateSymbol(Name.str());
917 void ARMAsmPrinter::printJTBlockOperand(const MachineInstr *MI, int OpNum,
919 assert(!Subtarget->isThumb2() && "Thumb2 should use double-jump jumptables!");
921 const MachineOperand &MO1 = MI->getOperand(OpNum);
922 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
924 unsigned JTI = MO1.getIndex();
925 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
926 // Can't use EmitLabel until instprinter happens, label comes out in the wrong
928 O << *JTISymbol << ":\n";
930 const char *JTEntryDirective = MAI->getData32bitsDirective();
932 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
933 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
934 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
935 bool UseSet= MAI->hasSetDirective() && TM.getRelocationModel() == Reloc::PIC_;
936 SmallPtrSet<MachineBasicBlock*, 8> JTSets;
937 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
938 MachineBasicBlock *MBB = JTBBs[i];
939 bool isNew = JTSets.insert(MBB);
941 if (UseSet && isNew) {
943 << *GetARMSetPICJumpTableLabel2(JTI, MO2.getImm(), MBB) << ','
944 << *MBB->getSymbol() << '-' << *JTISymbol << '\n';
947 O << JTEntryDirective << ' ';
949 O << *GetARMSetPICJumpTableLabel2(JTI, MO2.getImm(), MBB);
950 else if (TM.getRelocationModel() == Reloc::PIC_)
951 O << *MBB->getSymbol() << '-' << *JTISymbol;
953 O << *MBB->getSymbol();
960 void ARMAsmPrinter::printJT2BlockOperand(const MachineInstr *MI, int OpNum,
962 const MachineOperand &MO1 = MI->getOperand(OpNum);
963 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
964 unsigned JTI = MO1.getIndex();
966 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
968 // Can't use EmitLabel until instprinter happens, label comes out in the wrong
970 O << *JTISymbol << ":\n";
972 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
973 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
974 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
975 bool ByteOffset = false, HalfWordOffset = false;
976 if (MI->getOpcode() == ARM::t2TBB)
978 else if (MI->getOpcode() == ARM::t2TBH)
979 HalfWordOffset = true;
981 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
982 MachineBasicBlock *MBB = JTBBs[i];
984 O << MAI->getData8bitsDirective();
985 else if (HalfWordOffset)
986 O << MAI->getData16bitsDirective();
988 if (ByteOffset || HalfWordOffset)
989 O << '(' << *MBB->getSymbol() << "-" << *JTISymbol << ")/2";
991 O << "\tb.w " << *MBB->getSymbol();
998 void ARMAsmPrinter::printTBAddrMode(const MachineInstr *MI, int OpNum,
1000 O << "[pc, " << getRegisterName(MI->getOperand(OpNum).getReg());
1001 if (MI->getOpcode() == ARM::t2TBH)
1006 void ARMAsmPrinter::printNoHashImmediate(const MachineInstr *MI, int OpNum,
1008 O << MI->getOperand(OpNum).getImm();
1011 void ARMAsmPrinter::printVFPf32ImmOperand(const MachineInstr *MI, int OpNum,
1013 const ConstantFP *FP = MI->getOperand(OpNum).getFPImm();
1014 O << '#' << FP->getValueAPF().convertToFloat();
1016 O << "\t\t" << MAI->getCommentString() << ' ';
1017 WriteAsOperand(O, FP, /*PrintType=*/false);
1021 void ARMAsmPrinter::printVFPf64ImmOperand(const MachineInstr *MI, int OpNum,
1023 const ConstantFP *FP = MI->getOperand(OpNum).getFPImm();
1024 O << '#' << FP->getValueAPF().convertToDouble();
1026 O << "\t\t" << MAI->getCommentString() << ' ';
1027 WriteAsOperand(O, FP, /*PrintType=*/false);
1031 void ARMAsmPrinter::printNEONModImmOperand(const MachineInstr *MI, int OpNum,
1033 unsigned Imm = MI->getOperand(OpNum).getImm();
1034 unsigned OpCmode = (Imm >> 8) & 0x1f;
1035 unsigned Imm8 = Imm & 0xff;
1038 if (OpCmode == 0xe) {
1039 // 8-bit vector elements
1041 } else if ((OpCmode & 0xc) == 0x8) {
1042 // 16-bit vector elements
1043 unsigned ByteNum = (OpCmode & 0x6) >> 1;
1044 Val = Imm8 << (8 * ByteNum);
1045 } else if ((OpCmode & 0x8) == 0) {
1046 // 32-bit vector elements, zero with one byte set
1047 unsigned ByteNum = (OpCmode & 0x6) >> 1;
1048 Val = Imm8 << (8 * ByteNum);
1049 } else if ((OpCmode & 0xe) == 0xc) {
1050 // 32-bit vector elements, one byte with low bits set
1051 unsigned ByteNum = 1 + (OpCmode & 0x1);
1052 Val = (Imm8 << (8 * ByteNum)) | (0xffff >> (8 * (2 - ByteNum)));
1053 } else if (OpCmode == 0x1e) {
1054 // 64-bit vector elements
1055 for (unsigned ByteNum = 0; ByteNum < 8; ++ByteNum) {
1056 if ((Imm >> ByteNum) & 1)
1057 Val |= (uint64_t)0xff << (8 * ByteNum);
1060 assert(false && "Unsupported NEON immediate");
1062 O << "#0x" << utohexstr(Val);
1065 bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
1066 unsigned AsmVariant, const char *ExtraCode,
1068 // Does this asm operand have a single letter operand modifier?
1069 if (ExtraCode && ExtraCode[0]) {
1070 if (ExtraCode[1] != 0) return true; // Unknown modifier.
1072 switch (ExtraCode[0]) {
1073 default: return true; // Unknown modifier.
1074 case 'a': // Print as a memory address.
1075 if (MI->getOperand(OpNum).isReg()) {
1076 O << "[" << getRegisterName(MI->getOperand(OpNum).getReg()) << "]";
1080 case 'c': // Don't print "#" before an immediate operand.
1081 if (!MI->getOperand(OpNum).isImm())
1083 printNoHashImmediate(MI, OpNum, O);
1085 case 'P': // Print a VFP double precision register.
1086 case 'q': // Print a NEON quad precision register.
1087 printOperand(MI, OpNum, O);
1092 report_fatal_error("llvm does not support 'Q', 'R', and 'H' modifiers!");
1097 printOperand(MI, OpNum, O);
1101 bool ARMAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
1102 unsigned OpNum, unsigned AsmVariant,
1103 const char *ExtraCode,
1105 if (ExtraCode && ExtraCode[0])
1106 return true; // Unknown modifier.
1108 const MachineOperand &MO = MI->getOperand(OpNum);
1109 assert(MO.isReg() && "unexpected inline asm memory operand");
1110 O << "[" << getRegisterName(MO.getReg()) << "]";
1114 void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) {
1116 printInstructionThroughMCStreamer(MI);
1120 if (MI->getOpcode() == ARM::CONSTPOOL_ENTRY)
1123 SmallString<128> Str;
1124 raw_svector_ostream OS(Str);
1125 if (MI->getOpcode() == ARM::DBG_VALUE) {
1126 unsigned NOps = MI->getNumOperands();
1128 OS << '\t' << MAI->getCommentString() << "DEBUG_VALUE: ";
1129 // cast away const; DIetc do not take const operands for some reason.
1130 DIVariable V(const_cast<MDNode *>(MI->getOperand(NOps-1).getMetadata()));
1133 // Frame address. Currently handles register +- offset only.
1134 assert(MI->getOperand(0).isReg() && MI->getOperand(1).isImm());
1135 OS << '['; printOperand(MI, 0, OS); OS << '+'; printOperand(MI, 1, OS);
1138 printOperand(MI, NOps-2, OS);
1139 OutStreamer.EmitRawText(OS.str());
1143 printInstruction(MI, OS);
1144 OutStreamer.EmitRawText(OS.str());
1146 // Make sure the instruction that follows TBB is 2-byte aligned.
1147 // FIXME: Constant island pass should insert an "ALIGN" instruction instead.
1148 if (MI->getOpcode() == ARM::t2TBB)
1152 void ARMAsmPrinter::EmitStartOfAsmFile(Module &M) {
1153 if (Subtarget->isTargetDarwin()) {
1154 Reloc::Model RelocM = TM.getRelocationModel();
1155 if (RelocM == Reloc::PIC_ || RelocM == Reloc::DynamicNoPIC) {
1156 // Declare all the text sections up front (before the DWARF sections
1157 // emitted by AsmPrinter::doInitialization) so the assembler will keep
1158 // them together at the beginning of the object file. This helps
1159 // avoid out-of-range branches that are due a fundamental limitation of
1160 // the way symbol offsets are encoded with the current Darwin ARM
1162 const TargetLoweringObjectFileMachO &TLOFMacho =
1163 static_cast<const TargetLoweringObjectFileMachO &>(
1164 getObjFileLowering());
1165 OutStreamer.SwitchSection(TLOFMacho.getTextSection());
1166 OutStreamer.SwitchSection(TLOFMacho.getTextCoalSection());
1167 OutStreamer.SwitchSection(TLOFMacho.getConstTextCoalSection());
1168 if (RelocM == Reloc::DynamicNoPIC) {
1169 const MCSection *sect =
1170 OutContext.getMachOSection("__TEXT", "__symbol_stub4",
1171 MCSectionMachO::S_SYMBOL_STUBS,
1172 12, SectionKind::getText());
1173 OutStreamer.SwitchSection(sect);
1175 const MCSection *sect =
1176 OutContext.getMachOSection("__TEXT", "__picsymbolstub4",
1177 MCSectionMachO::S_SYMBOL_STUBS,
1178 16, SectionKind::getText());
1179 OutStreamer.SwitchSection(sect);
1184 // Use unified assembler syntax.
1185 OutStreamer.EmitRawText(StringRef("\t.syntax unified"));
1187 // Emit ARM Build Attributes
1188 if (Subtarget->isTargetELF()) {
1190 std::string CPUString = Subtarget->getCPUString();
1191 if (CPUString != "generic")
1192 OutStreamer.EmitRawText("\t.cpu " + Twine(CPUString));
1194 // FIXME: Emit FPU type
1195 if (Subtarget->hasVFP2())
1196 OutStreamer.EmitRawText("\t.eabi_attribute " +
1197 Twine(ARMBuildAttrs::VFP_arch) + ", 2");
1199 // Signal various FP modes.
1200 if (!UnsafeFPMath) {
1201 OutStreamer.EmitRawText("\t.eabi_attribute " +
1202 Twine(ARMBuildAttrs::ABI_FP_denormal) + ", 1");
1203 OutStreamer.EmitRawText("\t.eabi_attribute " +
1204 Twine(ARMBuildAttrs::ABI_FP_exceptions) + ", 1");
1207 if (FiniteOnlyFPMath())
1208 OutStreamer.EmitRawText("\t.eabi_attribute " +
1209 Twine(ARMBuildAttrs::ABI_FP_number_model)+ ", 1");
1211 OutStreamer.EmitRawText("\t.eabi_attribute " +
1212 Twine(ARMBuildAttrs::ABI_FP_number_model)+ ", 3");
1214 // 8-bytes alignment stuff.
1215 OutStreamer.EmitRawText("\t.eabi_attribute " +
1216 Twine(ARMBuildAttrs::ABI_align8_needed) + ", 1");
1217 OutStreamer.EmitRawText("\t.eabi_attribute " +
1218 Twine(ARMBuildAttrs::ABI_align8_preserved) + ", 1");
1220 // Hard float. Use both S and D registers and conform to AAPCS-VFP.
1221 if (Subtarget->isAAPCS_ABI() && FloatABIType == FloatABI::Hard) {
1222 OutStreamer.EmitRawText("\t.eabi_attribute " +
1223 Twine(ARMBuildAttrs::ABI_HardFP_use) + ", 3");
1224 OutStreamer.EmitRawText("\t.eabi_attribute " +
1225 Twine(ARMBuildAttrs::ABI_VFP_args) + ", 1");
1227 // FIXME: Should we signal R9 usage?
1232 void ARMAsmPrinter::EmitEndOfAsmFile(Module &M) {
1233 if (Subtarget->isTargetDarwin()) {
1234 // All darwin targets use mach-o.
1235 const TargetLoweringObjectFileMachO &TLOFMacho =
1236 static_cast<const TargetLoweringObjectFileMachO &>(getObjFileLowering());
1237 MachineModuleInfoMachO &MMIMacho =
1238 MMI->getObjFileInfo<MachineModuleInfoMachO>();
1240 // Output non-lazy-pointers for external and common global variables.
1241 MachineModuleInfoMachO::SymbolListTy Stubs = MMIMacho.GetGVStubList();
1243 if (!Stubs.empty()) {
1244 // Switch with ".non_lazy_symbol_pointer" directive.
1245 OutStreamer.SwitchSection(TLOFMacho.getNonLazySymbolPointerSection());
1247 for (unsigned i = 0, e = Stubs.size(); i != e; ++i) {
1249 OutStreamer.EmitLabel(Stubs[i].first);
1250 // .indirect_symbol _foo
1251 MachineModuleInfoImpl::StubValueTy &MCSym = Stubs[i].second;
1252 OutStreamer.EmitSymbolAttribute(MCSym.getPointer(),MCSA_IndirectSymbol);
1255 // External to current translation unit.
1256 OutStreamer.EmitIntValue(0, 4/*size*/, 0/*addrspace*/);
1258 // Internal to current translation unit.
1260 // When we place the LSDA into the TEXT section, the type info pointers
1261 // need to be indirect and pc-rel. We accomplish this by using NLPs.
1262 // However, sometimes the types are local to the file. So we need to
1263 // fill in the value for the NLP in those cases.
1264 OutStreamer.EmitValue(MCSymbolRefExpr::Create(MCSym.getPointer(),
1266 4/*size*/, 0/*addrspace*/);
1270 OutStreamer.AddBlankLine();
1273 Stubs = MMIMacho.GetHiddenGVStubList();
1274 if (!Stubs.empty()) {
1275 OutStreamer.SwitchSection(getObjFileLowering().getDataSection());
1277 for (unsigned i = 0, e = Stubs.size(); i != e; ++i) {
1279 OutStreamer.EmitLabel(Stubs[i].first);
1281 OutStreamer.EmitValue(MCSymbolRefExpr::
1282 Create(Stubs[i].second.getPointer(),
1284 4/*size*/, 0/*addrspace*/);
1288 OutStreamer.AddBlankLine();
1291 // Funny Darwin hack: This flag tells the linker that no global symbols
1292 // contain code that falls through to other global symbols (e.g. the obvious
1293 // implementation of multiple entry points). If this doesn't occur, the
1294 // linker can safely perform dead code stripping. Since LLVM never
1295 // generates code that does this, it is always safe to set.
1296 OutStreamer.EmitAssemblerFlag(MCAF_SubsectionsViaSymbols);
1300 //===----------------------------------------------------------------------===//
1302 void ARMAsmPrinter::printInstructionThroughMCStreamer(const MachineInstr *MI) {
1303 ARMMCInstLower MCInstLowering(OutContext, *Mang, *this);
1304 switch (MI->getOpcode()) {
1305 case ARM::t2MOVi32imm:
1306 assert(0 && "Should be lowered by thumb2it pass");
1308 case ARM::PICADD: { // FIXME: Remove asm string from td file.
1309 // This is a pseudo op for a label + instruction sequence, which looks like:
1312 // This adds the address of LPC0 to r0.
1315 // FIXME: MOVE TO SHARED PLACE.
1316 unsigned Id = (unsigned)MI->getOperand(2).getImm();
1317 const char *Prefix = MAI->getPrivateGlobalPrefix();
1318 MCSymbol *Label =OutContext.GetOrCreateSymbol(Twine(Prefix)
1319 + "PC" + Twine(getFunctionNumber()) + "_" + Twine(Id));
1320 OutStreamer.EmitLabel(Label);
1323 // Form and emit tha dd.
1325 AddInst.setOpcode(ARM::ADDrr);
1326 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1327 AddInst.addOperand(MCOperand::CreateReg(ARM::PC));
1328 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1329 OutStreamer.EmitInstruction(AddInst);
1332 case ARM::CONSTPOOL_ENTRY: { // FIXME: Remove asm string from td file.
1333 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool
1334 /// in the function. The first operand is the ID# for this instruction, the
1335 /// second is the index into the MachineConstantPool that this is, the third
1336 /// is the size in bytes of this constant pool entry.
1337 unsigned LabelId = (unsigned)MI->getOperand(0).getImm();
1338 unsigned CPIdx = (unsigned)MI->getOperand(1).getIndex();
1341 OutStreamer.EmitLabel(GetCPISymbol(LabelId));
1343 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPIdx];
1344 if (MCPE.isMachineConstantPoolEntry())
1345 EmitMachineConstantPoolValue(MCPE.Val.MachineCPVal);
1347 EmitGlobalConstant(MCPE.Val.ConstVal);
1351 case ARM::MOVi2pieces: { // FIXME: Remove asmstring from td file.
1352 // This is a hack that lowers as a two instruction sequence.
1353 unsigned DstReg = MI->getOperand(0).getReg();
1354 unsigned ImmVal = (unsigned)MI->getOperand(1).getImm();
1356 unsigned SOImmValV1 = ARM_AM::getSOImmTwoPartFirst(ImmVal);
1357 unsigned SOImmValV2 = ARM_AM::getSOImmTwoPartSecond(ImmVal);
1361 TmpInst.setOpcode(ARM::MOVi);
1362 TmpInst.addOperand(MCOperand::CreateReg(DstReg));
1363 TmpInst.addOperand(MCOperand::CreateImm(SOImmValV1));
1366 TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
1367 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(3).getReg()));
1369 TmpInst.addOperand(MCOperand::CreateReg(0)); // cc_out
1370 OutStreamer.EmitInstruction(TmpInst);
1375 TmpInst.setOpcode(ARM::ORRri);
1376 TmpInst.addOperand(MCOperand::CreateReg(DstReg)); // dstreg
1377 TmpInst.addOperand(MCOperand::CreateReg(DstReg)); // inreg
1378 TmpInst.addOperand(MCOperand::CreateImm(SOImmValV2)); // so_imm
1380 TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
1381 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(3).getReg()));
1383 TmpInst.addOperand(MCOperand::CreateReg(0)); // cc_out
1384 OutStreamer.EmitInstruction(TmpInst);
1388 case ARM::MOVi32imm: { // FIXME: Remove asmstring from td file.
1389 // This is a hack that lowers as a two instruction sequence.
1390 unsigned DstReg = MI->getOperand(0).getReg();
1391 const MachineOperand &MO = MI->getOperand(1);
1394 unsigned ImmVal = (unsigned)MI->getOperand(1).getImm();
1395 V1 = MCOperand::CreateImm(ImmVal & 65535);
1396 V2 = MCOperand::CreateImm(ImmVal >> 16);
1397 } else if (MO.isGlobal()) {
1398 MCSymbol *Symbol = MCInstLowering.GetGlobalAddressSymbol(MO);
1399 const MCSymbolRefExpr *SymRef1 =
1400 MCSymbolRefExpr::Create(Symbol,
1401 MCSymbolRefExpr::VK_ARM_LO16, OutContext);
1402 const MCSymbolRefExpr *SymRef2 =
1403 MCSymbolRefExpr::Create(Symbol,
1404 MCSymbolRefExpr::VK_ARM_HI16, OutContext);
1405 V1 = MCOperand::CreateExpr(SymRef1);
1406 V2 = MCOperand::CreateExpr(SymRef2);
1409 llvm_unreachable("cannot handle this operand");
1414 TmpInst.setOpcode(ARM::MOVi16);
1415 TmpInst.addOperand(MCOperand::CreateReg(DstReg)); // dstreg
1416 TmpInst.addOperand(V1); // lower16(imm)
1419 TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
1420 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(3).getReg()));
1422 OutStreamer.EmitInstruction(TmpInst);
1427 TmpInst.setOpcode(ARM::MOVTi16);
1428 TmpInst.addOperand(MCOperand::CreateReg(DstReg)); // dstreg
1429 TmpInst.addOperand(MCOperand::CreateReg(DstReg)); // srcreg
1430 TmpInst.addOperand(V2); // upper16(imm)
1433 TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
1434 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(3).getReg()));
1436 OutStreamer.EmitInstruction(TmpInst);
1444 MCInstLowering.Lower(MI, TmpInst);
1445 OutStreamer.EmitInstruction(TmpInst);
1448 //===----------------------------------------------------------------------===//
1449 // Target Registry Stuff
1450 //===----------------------------------------------------------------------===//
1452 static MCInstPrinter *createARMMCInstPrinter(const Target &T,
1453 unsigned SyntaxVariant,
1454 const MCAsmInfo &MAI) {
1455 if (SyntaxVariant == 0)
1456 return new ARMInstPrinter(MAI, false);
1460 // Force static initialization.
1461 extern "C" void LLVMInitializeARMAsmPrinter() {
1462 RegisterAsmPrinter<ARMAsmPrinter> X(TheARMTarget);
1463 RegisterAsmPrinter<ARMAsmPrinter> Y(TheThumbTarget);
1465 TargetRegistry::RegisterMCInstPrinter(TheARMTarget, createARMMCInstPrinter);
1466 TargetRegistry::RegisterMCInstPrinter(TheThumbTarget, createARMMCInstPrinter);