1 //===-- ARMAsmPrinter.cpp - Print machine code to an ARM .s file ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains a printer that converts from our internal representation
11 // of machine-dependent LLVM code to GAS-format ARM assembly language.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "asm-printer"
17 #include "ARMBuildAttrs.h"
18 #include "ARMAddressingModes.h"
19 #include "ARMConstantPoolValue.h"
20 #include "ARMInstPrinter.h"
21 #include "ARMMachineFunctionInfo.h"
22 #include "ARMMCInstLower.h"
23 #include "ARMTargetMachine.h"
24 #include "llvm/Constants.h"
25 #include "llvm/Module.h"
26 #include "llvm/Type.h"
27 #include "llvm/Assembly/Writer.h"
28 #include "llvm/CodeGen/AsmPrinter.h"
29 #include "llvm/CodeGen/DwarfWriter.h"
30 #include "llvm/CodeGen/MachineModuleInfoImpls.h"
31 #include "llvm/CodeGen/MachineFunctionPass.h"
32 #include "llvm/CodeGen/MachineJumpTableInfo.h"
33 #include "llvm/MC/MCAsmInfo.h"
34 #include "llvm/MC/MCContext.h"
35 #include "llvm/MC/MCInst.h"
36 #include "llvm/MC/MCSectionMachO.h"
37 #include "llvm/MC/MCStreamer.h"
38 #include "llvm/MC/MCSymbol.h"
39 #include "llvm/Target/TargetData.h"
40 #include "llvm/Target/TargetLoweringObjectFile.h"
41 #include "llvm/Target/TargetMachine.h"
42 #include "llvm/Target/TargetOptions.h"
43 #include "llvm/Target/TargetRegistry.h"
44 #include "llvm/ADT/SmallPtrSet.h"
45 #include "llvm/ADT/SmallString.h"
46 #include "llvm/ADT/Statistic.h"
47 #include "llvm/ADT/StringExtras.h"
48 #include "llvm/ADT/StringSet.h"
49 #include "llvm/Support/CommandLine.h"
50 #include "llvm/Support/ErrorHandling.h"
51 #include "llvm/Support/FormattedStream.h"
52 #include "llvm/Support/MathExtras.h"
56 STATISTIC(EmittedInsts, "Number of machine instrs printed");
59 EnableMCInst("enable-arm-mcinst-printer", cl::Hidden,
60 cl::desc("enable experimental asmprinter gunk in the arm backend"));
63 class ARMAsmPrinter : public AsmPrinter {
65 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
66 /// make the right decision when printing asm code for different targets.
67 const ARMSubtarget *Subtarget;
69 /// AFI - Keep a pointer to ARMFunctionInfo for the current
73 /// MCP - Keep a pointer to constantpool entries of the current
75 const MachineConstantPool *MCP;
78 explicit ARMAsmPrinter(formatted_raw_ostream &O, TargetMachine &TM,
79 const MCAsmInfo *T, bool V)
80 : AsmPrinter(O, TM, T, V), AFI(NULL), MCP(NULL) {
81 Subtarget = &TM.getSubtarget<ARMSubtarget>();
84 virtual const char *getPassName() const {
85 return "ARM Assembly Printer";
88 void printMCInst(const MCInst *MI) {
89 ARMInstPrinter(O, *MAI, VerboseAsm).printInstruction(MI);
92 void printInstructionThroughMCStreamer(const MachineInstr *MI);
95 void printOperand(const MachineInstr *MI, int OpNum,
96 const char *Modifier = 0);
97 void printSOImmOperand(const MachineInstr *MI, int OpNum);
98 void printSOImm2PartOperand(const MachineInstr *MI, int OpNum);
99 void printSORegOperand(const MachineInstr *MI, int OpNum);
100 void printAddrMode2Operand(const MachineInstr *MI, int OpNum);
101 void printAddrMode2OffsetOperand(const MachineInstr *MI, int OpNum);
102 void printAddrMode3Operand(const MachineInstr *MI, int OpNum);
103 void printAddrMode3OffsetOperand(const MachineInstr *MI, int OpNum);
104 void printAddrMode4Operand(const MachineInstr *MI, int OpNum,
105 const char *Modifier = 0);
106 void printAddrMode5Operand(const MachineInstr *MI, int OpNum,
107 const char *Modifier = 0);
108 void printAddrMode6Operand(const MachineInstr *MI, int OpNum);
109 void printAddrModePCOperand(const MachineInstr *MI, int OpNum,
110 const char *Modifier = 0);
111 void printBitfieldInvMaskImmOperand (const MachineInstr *MI, int OpNum);
113 void printThumbS4ImmOperand(const MachineInstr *MI, int OpNum);
114 void printThumbITMask(const MachineInstr *MI, int OpNum);
115 void printThumbAddrModeRROperand(const MachineInstr *MI, int OpNum);
116 void printThumbAddrModeRI5Operand(const MachineInstr *MI, int OpNum,
118 void printThumbAddrModeS1Operand(const MachineInstr *MI, int OpNum);
119 void printThumbAddrModeS2Operand(const MachineInstr *MI, int OpNum);
120 void printThumbAddrModeS4Operand(const MachineInstr *MI, int OpNum);
121 void printThumbAddrModeSPOperand(const MachineInstr *MI, int OpNum);
123 void printT2SOOperand(const MachineInstr *MI, int OpNum);
124 void printT2AddrModeImm12Operand(const MachineInstr *MI, int OpNum);
125 void printT2AddrModeImm8Operand(const MachineInstr *MI, int OpNum);
126 void printT2AddrModeImm8s4Operand(const MachineInstr *MI, int OpNum);
127 void printT2AddrModeImm8OffsetOperand(const MachineInstr *MI, int OpNum);
128 void printT2AddrModeSoRegOperand(const MachineInstr *MI, int OpNum);
130 void printPredicateOperand(const MachineInstr *MI, int OpNum);
131 void printSBitModifierOperand(const MachineInstr *MI, int OpNum);
132 void printPCLabel(const MachineInstr *MI, int OpNum);
133 void printRegisterList(const MachineInstr *MI, int OpNum);
134 void printCPInstOperand(const MachineInstr *MI, int OpNum,
135 const char *Modifier);
136 void printJTBlockOperand(const MachineInstr *MI, int OpNum);
137 void printJT2BlockOperand(const MachineInstr *MI, int OpNum);
138 void printTBAddrMode(const MachineInstr *MI, int OpNum);
139 void printNoHashImmediate(const MachineInstr *MI, int OpNum);
140 void printVFPf32ImmOperand(const MachineInstr *MI, int OpNum);
141 void printVFPf64ImmOperand(const MachineInstr *MI, int OpNum);
143 void printHex8ImmOperand(const MachineInstr *MI, int OpNum) {
144 O << "#0x" << utohexstr(MI->getOperand(OpNum).getImm() & 0xff);
146 void printHex16ImmOperand(const MachineInstr *MI, int OpNum) {
147 O << "#0x" << utohexstr(MI->getOperand(OpNum).getImm() & 0xffff);
149 void printHex32ImmOperand(const MachineInstr *MI, int OpNum) {
150 O << "#0x" << utohexstr(MI->getOperand(OpNum).getImm() & 0xffffffff);
152 void printHex64ImmOperand(const MachineInstr *MI, int OpNum) {
153 O << "#0x" << utohexstr(MI->getOperand(OpNum).getImm());
156 virtual bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
157 unsigned AsmVariant, const char *ExtraCode);
158 virtual bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNum,
160 const char *ExtraCode);
162 void printInstruction(const MachineInstr *MI); // autogenerated.
163 static const char *getRegisterName(unsigned RegNo);
165 void printMachineInstruction(const MachineInstr *MI);
166 bool runOnMachineFunction(MachineFunction &F);
167 void EmitStartOfAsmFile(Module &M);
168 void EmitEndOfAsmFile(Module &M);
170 MCSymbol *GetARMSetPICJumpTableLabel2(unsigned uid, unsigned uid2,
171 const MachineBasicBlock *MBB) const;
172 MCSymbol *GetARMJTIPICJumpTableLabel2(unsigned uid, unsigned uid2) const;
174 /// EmitMachineConstantPoolValue - Print a machine constantpool value to
176 virtual void EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV) {
177 switch (TM.getTargetData()->getTypeAllocSize(MCPV->getType())) {
178 case 1: O << MAI->getData8bitsDirective(0); break;
179 case 2: O << MAI->getData16bitsDirective(0); break;
180 case 4: O << MAI->getData32bitsDirective(0); break;
181 default: assert(0 && "Unknown CPV size");
184 ARMConstantPoolValue *ACPV = static_cast<ARMConstantPoolValue*>(MCPV);
185 SmallString<128> TmpNameStr;
187 if (ACPV->isLSDA()) {
188 raw_svector_ostream(TmpNameStr) << MAI->getPrivateGlobalPrefix() <<
189 "_LSDA_" << getFunctionNumber();
190 O << TmpNameStr.str();
191 } else if (ACPV->isBlockAddress()) {
192 O << GetBlockAddressSymbol(ACPV->getBlockAddress())->getName();
193 } else if (ACPV->isGlobalValue()) {
194 GlobalValue *GV = ACPV->getGV();
195 bool isIndirect = Subtarget->isTargetDarwin() &&
196 Subtarget->GVIsIndirectSymbol(GV, TM.getRelocationModel());
198 O << *GetGlobalValueSymbol(GV);
200 // FIXME: Remove this when Darwin transition to @GOT like syntax.
201 MCSymbol *Sym = GetSymbolWithGlobalValueBase(GV, "$non_lazy_ptr");
204 MachineModuleInfoMachO &MMIMachO =
205 MMI->getObjFileInfo<MachineModuleInfoMachO>();
206 const MCSymbol *&StubSym =
207 GV->hasHiddenVisibility() ? MMIMachO.getHiddenGVStubEntry(Sym) :
208 MMIMachO.getGVStubEntry(Sym);
210 StubSym = GetGlobalValueSymbol(GV);
213 assert(ACPV->isExtSymbol() && "unrecognized constant pool value");
214 O << *GetExternalSymbolSymbol(ACPV->getSymbol());
217 if (ACPV->hasModifier()) O << "(" << ACPV->getModifier() << ")";
218 if (ACPV->getPCAdjustment() != 0) {
219 O << "-(" << MAI->getPrivateGlobalPrefix() << "PC"
220 << getFunctionNumber() << "_" << ACPV->getLabelId()
221 << "+" << (unsigned)ACPV->getPCAdjustment();
222 if (ACPV->mustAddCurrentAddress())
229 void getAnalysisUsage(AnalysisUsage &AU) const {
230 AsmPrinter::getAnalysisUsage(AU);
231 AU.setPreservesAll();
232 AU.addRequired<MachineModuleInfo>();
233 AU.addRequired<DwarfWriter>();
236 } // end of anonymous namespace
238 #include "ARMGenAsmWriter.inc"
240 /// runOnMachineFunction - This uses the printInstruction()
241 /// method to print assembly for each instruction.
243 bool ARMAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
244 AFI = MF.getInfo<ARMFunctionInfo>();
245 MCP = MF.getConstantPool();
247 SetupMachineFunction(MF);
250 // NOTE: we don't print out constant pools here, they are handled as
255 // Print out labels for the function.
256 const Function *F = MF.getFunction();
257 OutStreamer.SwitchSection(getObjFileLowering().SectionForGlobal(F, Mang, TM));
259 switch (F->getLinkage()) {
260 default: llvm_unreachable("Unknown linkage type!");
261 case Function::PrivateLinkage:
262 case Function::InternalLinkage:
264 case Function::ExternalLinkage:
265 O << "\t.globl\t" << *CurrentFnSym << "\n";
267 case Function::LinkerPrivateLinkage:
268 case Function::WeakAnyLinkage:
269 case Function::WeakODRLinkage:
270 case Function::LinkOnceAnyLinkage:
271 case Function::LinkOnceODRLinkage:
272 if (Subtarget->isTargetDarwin()) {
273 O << "\t.globl\t" << *CurrentFnSym << "\n";
274 O << "\t.weak_definition\t" << *CurrentFnSym << "\n";
276 O << MAI->getWeakRefDirective() << *CurrentFnSym << "\n";
281 printVisibility(CurrentFnSym, F->getVisibility());
283 unsigned FnAlign = 1 << MF.getAlignment(); // MF alignment is log2.
284 if (AFI->isThumbFunction()) {
285 EmitAlignment(FnAlign, F, AFI->getAlign());
286 O << "\t.code\t16\n";
287 O << "\t.thumb_func";
288 if (Subtarget->isTargetDarwin())
289 O << "\t" << *CurrentFnSym;
292 EmitAlignment(FnAlign, F);
295 O << *CurrentFnSym << ":\n";
296 // Emit pre-function debug information.
297 DW->BeginFunction(&MF);
299 if (Subtarget->isTargetDarwin()) {
300 // If the function is empty, then we need to emit *something*. Otherwise,
301 // the function's label might be associated with something that it wasn't
302 // meant to be associated with. We emit a noop in this situation.
303 MachineFunction::iterator I = MF.begin();
305 if (++I == MF.end() && MF.front().empty())
309 // Print out code for the function.
310 for (MachineFunction::const_iterator I = MF.begin(), E = MF.end();
312 // Print a label for the basic block.
314 EmitBasicBlockStart(I);
316 // Print the assembly for the instruction.
317 for (MachineBasicBlock::const_iterator II = I->begin(), E = I->end();
319 printMachineInstruction(II);
322 if (MAI->hasDotTypeDotSizeDirective())
323 O << "\t.size " << *CurrentFnSym << ", .-" << *CurrentFnSym << "\n";
325 // Emit post-function debug information.
326 DW->EndFunction(&MF);
331 void ARMAsmPrinter::printOperand(const MachineInstr *MI, int OpNum,
332 const char *Modifier) {
333 const MachineOperand &MO = MI->getOperand(OpNum);
334 unsigned TF = MO.getTargetFlags();
336 switch (MO.getType()) {
338 assert(0 && "<unknown operand type>");
339 case MachineOperand::MO_Register: {
340 unsigned Reg = MO.getReg();
341 assert(TargetRegisterInfo::isPhysicalRegister(Reg));
342 if (Modifier && strcmp(Modifier, "dregpair") == 0) {
343 unsigned DRegLo = TRI->getSubReg(Reg, 5); // arm_dsubreg_0
344 unsigned DRegHi = TRI->getSubReg(Reg, 6); // arm_dsubreg_1
346 << getRegisterName(DRegLo) << ',' << getRegisterName(DRegHi)
348 } else if (Modifier && strcmp(Modifier, "lane") == 0) {
349 unsigned RegNum = ARMRegisterInfo::getRegisterNumbering(Reg);
350 unsigned DReg = TRI->getMatchingSuperReg(Reg, RegNum & 1 ? 2 : 1,
351 &ARM::DPR_VFP2RegClass);
352 O << getRegisterName(DReg) << '[' << (RegNum & 1) << ']';
354 assert(!MO.getSubReg() && "Subregs should be eliminated!");
355 O << getRegisterName(Reg);
359 case MachineOperand::MO_Immediate: {
360 int64_t Imm = MO.getImm();
362 if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
363 (TF & ARMII::MO_LO16))
365 else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
366 (TF & ARMII::MO_HI16))
371 case MachineOperand::MO_MachineBasicBlock:
372 O << *MO.getMBB()->getSymbol(OutContext);
374 case MachineOperand::MO_GlobalAddress: {
375 bool isCallOp = Modifier && !strcmp(Modifier, "call");
376 GlobalValue *GV = MO.getGlobal();
378 if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
379 (TF & ARMII::MO_LO16))
381 else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
382 (TF & ARMII::MO_HI16))
384 O << *GetGlobalValueSymbol(GV);
386 printOffset(MO.getOffset());
388 if (isCallOp && Subtarget->isTargetELF() &&
389 TM.getRelocationModel() == Reloc::PIC_)
393 case MachineOperand::MO_ExternalSymbol: {
394 bool isCallOp = Modifier && !strcmp(Modifier, "call");
395 O << *GetExternalSymbolSymbol(MO.getSymbolName());
397 if (isCallOp && Subtarget->isTargetELF() &&
398 TM.getRelocationModel() == Reloc::PIC_)
402 case MachineOperand::MO_ConstantPoolIndex:
403 O << *GetCPISymbol(MO.getIndex());
405 case MachineOperand::MO_JumpTableIndex:
406 O << *GetJTISymbol(MO.getIndex());
411 static void printSOImm(formatted_raw_ostream &O, int64_t V, bool VerboseAsm,
412 const MCAsmInfo *MAI) {
413 // Break it up into two parts that make up a shifter immediate.
414 V = ARM_AM::getSOImmVal(V);
415 assert(V != -1 && "Not a valid so_imm value!");
417 unsigned Imm = ARM_AM::getSOImmValImm(V);
418 unsigned Rot = ARM_AM::getSOImmValRot(V);
420 // Print low-level immediate formation info, per
421 // A5.1.3: "Data-processing operands - Immediate".
423 O << "#" << Imm << ", " << Rot;
424 // Pretty printed version.
426 O.PadToColumn(MAI->getCommentColumn());
427 O << MAI->getCommentString() << ' ';
428 O << (int)ARM_AM::rotr32(Imm, Rot);
435 /// printSOImmOperand - SOImm is 4-bit rotate amount in bits 8-11 with 8-bit
436 /// immediate in bits 0-7.
437 void ARMAsmPrinter::printSOImmOperand(const MachineInstr *MI, int OpNum) {
438 const MachineOperand &MO = MI->getOperand(OpNum);
439 assert(MO.isImm() && "Not a valid so_imm value!");
440 printSOImm(O, MO.getImm(), VerboseAsm, MAI);
443 /// printSOImm2PartOperand - SOImm is broken into two pieces using a 'mov'
444 /// followed by an 'orr' to materialize.
445 void ARMAsmPrinter::printSOImm2PartOperand(const MachineInstr *MI, int OpNum) {
446 const MachineOperand &MO = MI->getOperand(OpNum);
447 assert(MO.isImm() && "Not a valid so_imm value!");
448 unsigned V1 = ARM_AM::getSOImmTwoPartFirst(MO.getImm());
449 unsigned V2 = ARM_AM::getSOImmTwoPartSecond(MO.getImm());
450 printSOImm(O, V1, VerboseAsm, MAI);
452 printPredicateOperand(MI, 2);
458 printSOImm(O, V2, VerboseAsm, MAI);
461 // so_reg is a 4-operand unit corresponding to register forms of the A5.1
462 // "Addressing Mode 1 - Data-processing operands" forms. This includes:
464 // REG REG 0,SH_OPC - e.g. R5, ROR R3
465 // REG 0 IMM,SH_OPC - e.g. R5, LSL #3
466 void ARMAsmPrinter::printSORegOperand(const MachineInstr *MI, int Op) {
467 const MachineOperand &MO1 = MI->getOperand(Op);
468 const MachineOperand &MO2 = MI->getOperand(Op+1);
469 const MachineOperand &MO3 = MI->getOperand(Op+2);
471 O << getRegisterName(MO1.getReg());
473 // Print the shift opc.
475 << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO3.getImm()))
479 O << getRegisterName(MO2.getReg());
480 assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0);
482 O << "#" << ARM_AM::getSORegOffset(MO3.getImm());
486 void ARMAsmPrinter::printAddrMode2Operand(const MachineInstr *MI, int Op) {
487 const MachineOperand &MO1 = MI->getOperand(Op);
488 const MachineOperand &MO2 = MI->getOperand(Op+1);
489 const MachineOperand &MO3 = MI->getOperand(Op+2);
491 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
492 printOperand(MI, Op);
496 O << "[" << getRegisterName(MO1.getReg());
499 if (ARM_AM::getAM2Offset(MO3.getImm())) // Don't print +0.
501 << (char)ARM_AM::getAM2Op(MO3.getImm())
502 << ARM_AM::getAM2Offset(MO3.getImm());
508 << (char)ARM_AM::getAM2Op(MO3.getImm())
509 << getRegisterName(MO2.getReg());
511 if (unsigned ShImm = ARM_AM::getAM2Offset(MO3.getImm()))
513 << ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO3.getImm()))
518 void ARMAsmPrinter::printAddrMode2OffsetOperand(const MachineInstr *MI, int Op){
519 const MachineOperand &MO1 = MI->getOperand(Op);
520 const MachineOperand &MO2 = MI->getOperand(Op+1);
523 unsigned ImmOffs = ARM_AM::getAM2Offset(MO2.getImm());
524 assert(ImmOffs && "Malformed indexed load / store!");
526 << (char)ARM_AM::getAM2Op(MO2.getImm())
531 O << (char)ARM_AM::getAM2Op(MO2.getImm())
532 << getRegisterName(MO1.getReg());
534 if (unsigned ShImm = ARM_AM::getAM2Offset(MO2.getImm()))
536 << ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO2.getImm()))
540 void ARMAsmPrinter::printAddrMode3Operand(const MachineInstr *MI, int Op) {
541 const MachineOperand &MO1 = MI->getOperand(Op);
542 const MachineOperand &MO2 = MI->getOperand(Op+1);
543 const MachineOperand &MO3 = MI->getOperand(Op+2);
545 assert(TargetRegisterInfo::isPhysicalRegister(MO1.getReg()));
546 O << "[" << getRegisterName(MO1.getReg());
550 << (char)ARM_AM::getAM3Op(MO3.getImm())
551 << getRegisterName(MO2.getReg())
556 if (unsigned ImmOffs = ARM_AM::getAM3Offset(MO3.getImm()))
558 << (char)ARM_AM::getAM3Op(MO3.getImm())
563 void ARMAsmPrinter::printAddrMode3OffsetOperand(const MachineInstr *MI, int Op){
564 const MachineOperand &MO1 = MI->getOperand(Op);
565 const MachineOperand &MO2 = MI->getOperand(Op+1);
568 O << (char)ARM_AM::getAM3Op(MO2.getImm())
569 << getRegisterName(MO1.getReg());
573 unsigned ImmOffs = ARM_AM::getAM3Offset(MO2.getImm());
574 assert(ImmOffs && "Malformed indexed load / store!");
576 << (char)ARM_AM::getAM3Op(MO2.getImm())
580 void ARMAsmPrinter::printAddrMode4Operand(const MachineInstr *MI, int Op,
581 const char *Modifier) {
582 const MachineOperand &MO1 = MI->getOperand(Op);
583 const MachineOperand &MO2 = MI->getOperand(Op+1);
584 ARM_AM::AMSubMode Mode = ARM_AM::getAM4SubMode(MO2.getImm());
585 if (Modifier && strcmp(Modifier, "submode") == 0) {
586 if (MO1.getReg() == ARM::SP) {
588 bool isLDM = (MI->getOpcode() == ARM::LDM ||
589 MI->getOpcode() == ARM::LDM_RET ||
590 MI->getOpcode() == ARM::t2LDM ||
591 MI->getOpcode() == ARM::t2LDM_RET);
592 O << ARM_AM::getAMSubModeAltStr(Mode, isLDM);
594 O << ARM_AM::getAMSubModeStr(Mode);
595 } else if (Modifier && strcmp(Modifier, "wide") == 0) {
596 ARM_AM::AMSubMode Mode = ARM_AM::getAM4SubMode(MO2.getImm());
597 if (Mode == ARM_AM::ia)
600 printOperand(MI, Op);
601 if (ARM_AM::getAM4WBFlag(MO2.getImm()))
606 void ARMAsmPrinter::printAddrMode5Operand(const MachineInstr *MI, int Op,
607 const char *Modifier) {
608 const MachineOperand &MO1 = MI->getOperand(Op);
609 const MachineOperand &MO2 = MI->getOperand(Op+1);
611 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
612 printOperand(MI, Op);
616 assert(TargetRegisterInfo::isPhysicalRegister(MO1.getReg()));
618 if (Modifier && strcmp(Modifier, "submode") == 0) {
619 ARM_AM::AMSubMode Mode = ARM_AM::getAM5SubMode(MO2.getImm());
620 O << ARM_AM::getAMSubModeStr(Mode);
622 } else if (Modifier && strcmp(Modifier, "base") == 0) {
623 // Used for FSTM{D|S} and LSTM{D|S} operations.
624 O << getRegisterName(MO1.getReg());
625 if (ARM_AM::getAM5WBFlag(MO2.getImm()))
630 O << "[" << getRegisterName(MO1.getReg());
632 if (unsigned ImmOffs = ARM_AM::getAM5Offset(MO2.getImm())) {
634 << (char)ARM_AM::getAM5Op(MO2.getImm())
640 void ARMAsmPrinter::printAddrMode6Operand(const MachineInstr *MI, int Op) {
641 const MachineOperand &MO1 = MI->getOperand(Op);
642 const MachineOperand &MO2 = MI->getOperand(Op+1);
643 const MachineOperand &MO3 = MI->getOperand(Op+2);
644 const MachineOperand &MO4 = MI->getOperand(Op+3);
646 O << "[" << getRegisterName(MO1.getReg());
648 // FIXME: Both darwin as and GNU as violate ARM docs here.
649 O << ", :" << MO4.getImm();
653 if (ARM_AM::getAM6WBFlag(MO3.getImm())) {
654 if (MO2.getReg() == 0)
657 O << ", " << getRegisterName(MO2.getReg());
661 void ARMAsmPrinter::printAddrModePCOperand(const MachineInstr *MI, int Op,
662 const char *Modifier) {
663 if (Modifier && strcmp(Modifier, "label") == 0) {
664 printPCLabel(MI, Op+1);
668 const MachineOperand &MO1 = MI->getOperand(Op);
669 assert(TargetRegisterInfo::isPhysicalRegister(MO1.getReg()));
670 O << "[pc, +" << getRegisterName(MO1.getReg()) << "]";
674 ARMAsmPrinter::printBitfieldInvMaskImmOperand(const MachineInstr *MI, int Op) {
675 const MachineOperand &MO = MI->getOperand(Op);
676 uint32_t v = ~MO.getImm();
677 int32_t lsb = CountTrailingZeros_32(v);
678 int32_t width = (32 - CountLeadingZeros_32 (v)) - lsb;
679 assert(MO.isImm() && "Not a valid bf_inv_mask_imm value!");
680 O << "#" << lsb << ", #" << width;
683 //===--------------------------------------------------------------------===//
685 void ARMAsmPrinter::printThumbS4ImmOperand(const MachineInstr *MI, int Op) {
686 O << "#" << MI->getOperand(Op).getImm() * 4;
690 ARMAsmPrinter::printThumbITMask(const MachineInstr *MI, int Op) {
691 // (3 - the number of trailing zeros) is the number of then / else.
692 unsigned Mask = MI->getOperand(Op).getImm();
693 unsigned NumTZ = CountTrailingZeros_32(Mask);
694 assert(NumTZ <= 3 && "Invalid IT mask!");
695 for (unsigned Pos = 3, e = NumTZ; Pos > e; --Pos) {
696 bool T = (Mask & (1 << Pos)) == 0;
705 ARMAsmPrinter::printThumbAddrModeRROperand(const MachineInstr *MI, int Op) {
706 const MachineOperand &MO1 = MI->getOperand(Op);
707 const MachineOperand &MO2 = MI->getOperand(Op+1);
708 O << "[" << getRegisterName(MO1.getReg());
709 O << ", " << getRegisterName(MO2.getReg()) << "]";
713 ARMAsmPrinter::printThumbAddrModeRI5Operand(const MachineInstr *MI, int Op,
715 const MachineOperand &MO1 = MI->getOperand(Op);
716 const MachineOperand &MO2 = MI->getOperand(Op+1);
717 const MachineOperand &MO3 = MI->getOperand(Op+2);
719 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
720 printOperand(MI, Op);
724 O << "[" << getRegisterName(MO1.getReg());
726 O << ", " << getRegisterName(MO3.getReg());
727 else if (unsigned ImmOffs = MO2.getImm())
728 O << ", #+" << ImmOffs * Scale;
733 ARMAsmPrinter::printThumbAddrModeS1Operand(const MachineInstr *MI, int Op) {
734 printThumbAddrModeRI5Operand(MI, Op, 1);
737 ARMAsmPrinter::printThumbAddrModeS2Operand(const MachineInstr *MI, int Op) {
738 printThumbAddrModeRI5Operand(MI, Op, 2);
741 ARMAsmPrinter::printThumbAddrModeS4Operand(const MachineInstr *MI, int Op) {
742 printThumbAddrModeRI5Operand(MI, Op, 4);
745 void ARMAsmPrinter::printThumbAddrModeSPOperand(const MachineInstr *MI,int Op) {
746 const MachineOperand &MO1 = MI->getOperand(Op);
747 const MachineOperand &MO2 = MI->getOperand(Op+1);
748 O << "[" << getRegisterName(MO1.getReg());
749 if (unsigned ImmOffs = MO2.getImm())
750 O << ", #+" << ImmOffs*4;
754 //===--------------------------------------------------------------------===//
756 // Constant shifts t2_so_reg is a 2-operand unit corresponding to the Thumb2
757 // register with shift forms.
759 // REG IMM, SH_OPC - e.g. R5, LSL #3
760 void ARMAsmPrinter::printT2SOOperand(const MachineInstr *MI, int OpNum) {
761 const MachineOperand &MO1 = MI->getOperand(OpNum);
762 const MachineOperand &MO2 = MI->getOperand(OpNum+1);
764 unsigned Reg = MO1.getReg();
765 assert(TargetRegisterInfo::isPhysicalRegister(Reg));
766 O << getRegisterName(Reg);
768 // Print the shift opc.
770 << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO2.getImm()))
773 assert(MO2.isImm() && "Not a valid t2_so_reg value!");
774 O << "#" << ARM_AM::getSORegOffset(MO2.getImm());
777 void ARMAsmPrinter::printT2AddrModeImm12Operand(const MachineInstr *MI,
779 const MachineOperand &MO1 = MI->getOperand(OpNum);
780 const MachineOperand &MO2 = MI->getOperand(OpNum+1);
782 O << "[" << getRegisterName(MO1.getReg());
784 unsigned OffImm = MO2.getImm();
785 if (OffImm) // Don't print +0.
786 O << ", #+" << OffImm;
790 void ARMAsmPrinter::printT2AddrModeImm8Operand(const MachineInstr *MI,
792 const MachineOperand &MO1 = MI->getOperand(OpNum);
793 const MachineOperand &MO2 = MI->getOperand(OpNum+1);
795 O << "[" << getRegisterName(MO1.getReg());
797 int32_t OffImm = (int32_t)MO2.getImm();
800 O << ", #-" << -OffImm;
802 O << ", #+" << OffImm;
806 void ARMAsmPrinter::printT2AddrModeImm8s4Operand(const MachineInstr *MI,
808 const MachineOperand &MO1 = MI->getOperand(OpNum);
809 const MachineOperand &MO2 = MI->getOperand(OpNum+1);
811 O << "[" << getRegisterName(MO1.getReg());
813 int32_t OffImm = (int32_t)MO2.getImm() / 4;
816 O << ", #-" << -OffImm * 4;
818 O << ", #+" << OffImm * 4;
822 void ARMAsmPrinter::printT2AddrModeImm8OffsetOperand(const MachineInstr *MI,
824 const MachineOperand &MO1 = MI->getOperand(OpNum);
825 int32_t OffImm = (int32_t)MO1.getImm();
828 O << "#-" << -OffImm;
833 void ARMAsmPrinter::printT2AddrModeSoRegOperand(const MachineInstr *MI,
835 const MachineOperand &MO1 = MI->getOperand(OpNum);
836 const MachineOperand &MO2 = MI->getOperand(OpNum+1);
837 const MachineOperand &MO3 = MI->getOperand(OpNum+2);
839 O << "[" << getRegisterName(MO1.getReg());
841 assert(MO2.getReg() && "Invalid so_reg load / store address!");
842 O << ", " << getRegisterName(MO2.getReg());
844 unsigned ShAmt = MO3.getImm();
846 assert(ShAmt <= 3 && "Not a valid Thumb2 addressing mode!");
847 O << ", lsl #" << ShAmt;
853 //===--------------------------------------------------------------------===//
855 void ARMAsmPrinter::printPredicateOperand(const MachineInstr *MI, int OpNum) {
856 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
858 O << ARMCondCodeToString(CC);
861 void ARMAsmPrinter::printSBitModifierOperand(const MachineInstr *MI, int OpNum){
862 unsigned Reg = MI->getOperand(OpNum).getReg();
864 assert(Reg == ARM::CPSR && "Expect ARM CPSR register!");
869 void ARMAsmPrinter::printPCLabel(const MachineInstr *MI, int OpNum) {
870 int Id = (int)MI->getOperand(OpNum).getImm();
871 O << MAI->getPrivateGlobalPrefix()
872 << "PC" << getFunctionNumber() << "_" << Id;
875 void ARMAsmPrinter::printRegisterList(const MachineInstr *MI, int OpNum) {
877 // Always skip the first operand, it's the optional (and implicit writeback).
878 for (unsigned i = OpNum+1, e = MI->getNumOperands(); i != e; ++i) {
879 if (MI->getOperand(i).isImplicit())
881 if ((int)i != OpNum+1) O << ", ";
887 void ARMAsmPrinter::printCPInstOperand(const MachineInstr *MI, int OpNum,
888 const char *Modifier) {
889 assert(Modifier && "This operand only works with a modifier!");
890 // There are two aspects to a CONSTANTPOOL_ENTRY operand, the label and the
892 if (!strcmp(Modifier, "label")) {
893 unsigned ID = MI->getOperand(OpNum).getImm();
894 O << *GetCPISymbol(ID) << ":\n";
896 assert(!strcmp(Modifier, "cpentry") && "Unknown modifier for CPE");
897 unsigned CPI = MI->getOperand(OpNum).getIndex();
899 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPI];
901 if (MCPE.isMachineConstantPoolEntry()) {
902 EmitMachineConstantPoolValue(MCPE.Val.MachineCPVal);
904 EmitGlobalConstant(MCPE.Val.ConstVal);
909 MCSymbol *ARMAsmPrinter::
910 GetARMSetPICJumpTableLabel2(unsigned uid, unsigned uid2,
911 const MachineBasicBlock *MBB) const {
912 SmallString<60> Name;
913 raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix()
914 << getFunctionNumber() << '_' << uid << '_' << uid2
915 << "_set_" << MBB->getNumber();
916 return OutContext.GetOrCreateSymbol(Name.str());
919 MCSymbol *ARMAsmPrinter::
920 GetARMJTIPICJumpTableLabel2(unsigned uid, unsigned uid2) const {
921 SmallString<60> Name;
922 raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix() << "JTI"
923 << getFunctionNumber() << '_' << uid << '_' << uid2;
924 return OutContext.GetOrCreateSymbol(Name.str());
927 void ARMAsmPrinter::printJTBlockOperand(const MachineInstr *MI, int OpNum) {
928 assert(!Subtarget->isThumb2() && "Thumb2 should use double-jump jumptables!");
930 const MachineOperand &MO1 = MI->getOperand(OpNum);
931 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
933 unsigned JTI = MO1.getIndex();
934 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
935 OutStreamer.EmitLabel(JTISymbol);
937 const char *JTEntryDirective = MAI->getData32bitsDirective();
939 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
940 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
941 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
942 bool UseSet= MAI->getSetDirective() && TM.getRelocationModel() == Reloc::PIC_;
943 SmallPtrSet<MachineBasicBlock*, 8> JTSets;
944 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
945 MachineBasicBlock *MBB = JTBBs[i];
946 bool isNew = JTSets.insert(MBB);
948 if (UseSet && isNew) {
949 O << MAI->getSetDirective() << ' '
950 << *GetARMSetPICJumpTableLabel2(JTI, MO2.getImm(), MBB) << ','
951 << *MBB->getSymbol(OutContext) << '-' << *JTISymbol << '\n';
954 O << JTEntryDirective << ' ';
956 O << *GetARMSetPICJumpTableLabel2(JTI, MO2.getImm(), MBB);
957 else if (TM.getRelocationModel() == Reloc::PIC_)
958 O << *MBB->getSymbol(OutContext) << '-' << *JTISymbol;
960 O << *MBB->getSymbol(OutContext);
967 void ARMAsmPrinter::printJT2BlockOperand(const MachineInstr *MI, int OpNum) {
968 const MachineOperand &MO1 = MI->getOperand(OpNum);
969 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
970 unsigned JTI = MO1.getIndex();
972 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
973 OutStreamer.EmitLabel(JTISymbol);
975 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
976 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
977 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
978 bool ByteOffset = false, HalfWordOffset = false;
979 if (MI->getOpcode() == ARM::t2TBB)
981 else if (MI->getOpcode() == ARM::t2TBH)
982 HalfWordOffset = true;
984 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
985 MachineBasicBlock *MBB = JTBBs[i];
987 O << MAI->getData8bitsDirective();
988 else if (HalfWordOffset)
989 O << MAI->getData16bitsDirective();
991 if (ByteOffset || HalfWordOffset)
992 O << '(' << *MBB->getSymbol(OutContext) << "-" << *JTISymbol << ")/2";
994 O << "\tb.w " << *MBB->getSymbol(OutContext);
1000 // Make sure the instruction that follows TBB is 2-byte aligned.
1001 // FIXME: Constant island pass should insert an "ALIGN" instruction instead.
1002 if (ByteOffset && (JTBBs.size() & 1)) {
1008 void ARMAsmPrinter::printTBAddrMode(const MachineInstr *MI, int OpNum) {
1009 O << "[pc, " << getRegisterName(MI->getOperand(OpNum).getReg());
1010 if (MI->getOpcode() == ARM::t2TBH)
1015 void ARMAsmPrinter::printNoHashImmediate(const MachineInstr *MI, int OpNum) {
1016 O << MI->getOperand(OpNum).getImm();
1019 void ARMAsmPrinter::printVFPf32ImmOperand(const MachineInstr *MI, int OpNum) {
1020 const ConstantFP *FP = MI->getOperand(OpNum).getFPImm();
1021 O << '#' << FP->getValueAPF().convertToFloat();
1023 O.PadToColumn(MAI->getCommentColumn());
1024 O << MAI->getCommentString() << ' ';
1025 WriteAsOperand(O, FP, /*PrintType=*/false);
1029 void ARMAsmPrinter::printVFPf64ImmOperand(const MachineInstr *MI, int OpNum) {
1030 const ConstantFP *FP = MI->getOperand(OpNum).getFPImm();
1031 O << '#' << FP->getValueAPF().convertToDouble();
1033 O.PadToColumn(MAI->getCommentColumn());
1034 O << MAI->getCommentString() << ' ';
1035 WriteAsOperand(O, FP, /*PrintType=*/false);
1039 bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
1040 unsigned AsmVariant, const char *ExtraCode){
1041 // Does this asm operand have a single letter operand modifier?
1042 if (ExtraCode && ExtraCode[0]) {
1043 if (ExtraCode[1] != 0) return true; // Unknown modifier.
1045 switch (ExtraCode[0]) {
1046 default: return true; // Unknown modifier.
1047 case 'a': // Print as a memory address.
1048 if (MI->getOperand(OpNum).isReg()) {
1049 O << "[" << getRegisterName(MI->getOperand(OpNum).getReg()) << "]";
1053 case 'c': // Don't print "#" before an immediate operand.
1054 if (!MI->getOperand(OpNum).isImm())
1056 printNoHashImmediate(MI, OpNum);
1058 case 'P': // Print a VFP double precision register.
1059 case 'q': // Print a NEON quad precision register.
1060 printOperand(MI, OpNum);
1063 if (TM.getTargetData()->isLittleEndian())
1067 if (TM.getTargetData()->isBigEndian())
1070 case 'H': // Write second word of DI / DF reference.
1071 // Verify that this operand has two consecutive registers.
1072 if (!MI->getOperand(OpNum).isReg() ||
1073 OpNum+1 == MI->getNumOperands() ||
1074 !MI->getOperand(OpNum+1).isReg())
1076 ++OpNum; // Return the high-part.
1080 printOperand(MI, OpNum);
1084 bool ARMAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
1085 unsigned OpNum, unsigned AsmVariant,
1086 const char *ExtraCode) {
1087 if (ExtraCode && ExtraCode[0])
1088 return true; // Unknown modifier.
1090 const MachineOperand &MO = MI->getOperand(OpNum);
1091 assert(MO.isReg() && "unexpected inline asm memory operand");
1092 O << "[" << getRegisterName(MO.getReg()) << "]";
1096 void ARMAsmPrinter::printMachineInstruction(const MachineInstr *MI) {
1099 // Call the autogenerated instruction printer routines.
1100 processDebugLoc(MI, true);
1103 printInstructionThroughMCStreamer(MI);
1105 int Opc = MI->getOpcode();
1106 if (Opc == ARM::CONSTPOOL_ENTRY)
1109 printInstruction(MI);
1115 processDebugLoc(MI, false);
1118 void ARMAsmPrinter::EmitStartOfAsmFile(Module &M) {
1119 if (Subtarget->isTargetDarwin()) {
1120 Reloc::Model RelocM = TM.getRelocationModel();
1121 if (RelocM == Reloc::PIC_ || RelocM == Reloc::DynamicNoPIC) {
1122 // Declare all the text sections up front (before the DWARF sections
1123 // emitted by AsmPrinter::doInitialization) so the assembler will keep
1124 // them together at the beginning of the object file. This helps
1125 // avoid out-of-range branches that are due a fundamental limitation of
1126 // the way symbol offsets are encoded with the current Darwin ARM
1128 TargetLoweringObjectFileMachO &TLOFMacho =
1129 static_cast<TargetLoweringObjectFileMachO &>(getObjFileLowering());
1130 OutStreamer.SwitchSection(TLOFMacho.getTextSection());
1131 OutStreamer.SwitchSection(TLOFMacho.getTextCoalSection());
1132 OutStreamer.SwitchSection(TLOFMacho.getConstTextCoalSection());
1133 if (RelocM == Reloc::DynamicNoPIC) {
1134 const MCSection *sect =
1135 TLOFMacho.getMachOSection("__TEXT", "__symbol_stub4",
1136 MCSectionMachO::S_SYMBOL_STUBS,
1137 12, SectionKind::getText());
1138 OutStreamer.SwitchSection(sect);
1140 const MCSection *sect =
1141 TLOFMacho.getMachOSection("__TEXT", "__picsymbolstub4",
1142 MCSectionMachO::S_SYMBOL_STUBS,
1143 16, SectionKind::getText());
1144 OutStreamer.SwitchSection(sect);
1149 // Use unified assembler syntax.
1150 O << "\t.syntax unified\n";
1152 // Emit ARM Build Attributes
1153 if (Subtarget->isTargetELF()) {
1155 std::string CPUString = Subtarget->getCPUString();
1156 if (CPUString != "generic")
1157 O << "\t.cpu " << CPUString << '\n';
1159 // FIXME: Emit FPU type
1160 if (Subtarget->hasVFP2())
1161 O << "\t.eabi_attribute " << ARMBuildAttrs::VFP_arch << ", 2\n";
1163 // Signal various FP modes.
1165 O << "\t.eabi_attribute " << ARMBuildAttrs::ABI_FP_denormal << ", 1\n"
1166 << "\t.eabi_attribute " << ARMBuildAttrs::ABI_FP_exceptions << ", 1\n";
1168 if (FiniteOnlyFPMath())
1169 O << "\t.eabi_attribute " << ARMBuildAttrs::ABI_FP_number_model << ", 1\n";
1171 O << "\t.eabi_attribute " << ARMBuildAttrs::ABI_FP_number_model << ", 3\n";
1173 // 8-bytes alignment stuff.
1174 O << "\t.eabi_attribute " << ARMBuildAttrs::ABI_align8_needed << ", 1\n"
1175 << "\t.eabi_attribute " << ARMBuildAttrs::ABI_align8_preserved << ", 1\n";
1177 // Hard float. Use both S and D registers and conform to AAPCS-VFP.
1178 if (Subtarget->isAAPCS_ABI() && FloatABIType == FloatABI::Hard)
1179 O << "\t.eabi_attribute " << ARMBuildAttrs::ABI_HardFP_use << ", 3\n"
1180 << "\t.eabi_attribute " << ARMBuildAttrs::ABI_VFP_args << ", 1\n";
1182 // FIXME: Should we signal R9 usage?
1187 void ARMAsmPrinter::EmitEndOfAsmFile(Module &M) {
1188 if (Subtarget->isTargetDarwin()) {
1189 // All darwin targets use mach-o.
1190 TargetLoweringObjectFileMachO &TLOFMacho =
1191 static_cast<TargetLoweringObjectFileMachO &>(getObjFileLowering());
1192 MachineModuleInfoMachO &MMIMacho =
1193 MMI->getObjFileInfo<MachineModuleInfoMachO>();
1197 // Output non-lazy-pointers for external and common global variables.
1198 MachineModuleInfoMachO::SymbolListTy Stubs = MMIMacho.GetGVStubList();
1200 if (!Stubs.empty()) {
1201 // Switch with ".non_lazy_symbol_pointer" directive.
1202 OutStreamer.SwitchSection(TLOFMacho.getNonLazySymbolPointerSection());
1204 for (unsigned i = 0, e = Stubs.size(); i != e; ++i) {
1205 O << *Stubs[i].first << ":\n\t.indirect_symbol ";
1206 O << *Stubs[i].second << "\n\t.long\t0\n";
1210 Stubs = MMIMacho.GetHiddenGVStubList();
1211 if (!Stubs.empty()) {
1212 OutStreamer.SwitchSection(getObjFileLowering().getDataSection());
1214 for (unsigned i = 0, e = Stubs.size(); i != e; ++i)
1215 O << *Stubs[i].first << ":\n\t.long " << *Stubs[i].second << "\n";
1218 // Funny Darwin hack: This flag tells the linker that no global symbols
1219 // contain code that falls through to other global symbols (e.g. the obvious
1220 // implementation of multiple entry points). If this doesn't occur, the
1221 // linker can safely perform dead code stripping. Since LLVM never
1222 // generates code that does this, it is always safe to set.
1223 OutStreamer.EmitAssemblerFlag(MCAF_SubsectionsViaSymbols);
1227 //===----------------------------------------------------------------------===//
1229 void ARMAsmPrinter::printInstructionThroughMCStreamer(const MachineInstr *MI) {
1230 ARMMCInstLower MCInstLowering(OutContext, *Mang, *this);
1231 switch (MI->getOpcode()) {
1232 case ARM::t2MOVi32imm:
1233 assert(0 && "Should be lowered by thumb2it pass");
1235 case TargetInstrInfo::DBG_LABEL:
1236 case TargetInstrInfo::EH_LABEL:
1237 case TargetInstrInfo::GC_LABEL:
1240 case TargetInstrInfo::KILL:
1243 case TargetInstrInfo::INLINEASM:
1246 case TargetInstrInfo::IMPLICIT_DEF:
1247 printImplicitDef(MI);
1249 case ARM::PICADD: { // FIXME: Remove asm string from td file.
1250 // This is a pseudo op for a label + instruction sequence, which looks like:
1253 // This adds the address of LPC0 to r0.
1256 // FIXME: MOVE TO SHARED PLACE.
1257 unsigned Id = (unsigned)MI->getOperand(2).getImm();
1258 const char *Prefix = MAI->getPrivateGlobalPrefix();
1259 MCSymbol *Label =OutContext.GetOrCreateSymbol(Twine(Prefix)
1260 + "PC" + Twine(getFunctionNumber()) + "_" + Twine(Id));
1261 OutStreamer.EmitLabel(Label);
1264 // Form and emit tha dd.
1266 AddInst.setOpcode(ARM::ADDrr);
1267 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1268 AddInst.addOperand(MCOperand::CreateReg(ARM::PC));
1269 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1270 printMCInst(&AddInst);
1273 case ARM::CONSTPOOL_ENTRY: { // FIXME: Remove asm string from td file.
1274 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool
1275 /// in the function. The first operand is the ID# for this instruction, the
1276 /// second is the index into the MachineConstantPool that this is, the third
1277 /// is the size in bytes of this constant pool entry.
1278 unsigned LabelId = (unsigned)MI->getOperand(0).getImm();
1279 unsigned CPIdx = (unsigned)MI->getOperand(1).getIndex();
1282 OutStreamer.EmitLabel(GetCPISymbol(LabelId));
1284 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPIdx];
1285 if (MCPE.isMachineConstantPoolEntry())
1286 EmitMachineConstantPoolValue(MCPE.Val.MachineCPVal);
1288 EmitGlobalConstant(MCPE.Val.ConstVal);
1292 case ARM::MOVi2pieces: { // FIXME: Remove asmstring from td file.
1293 // This is a hack that lowers as a two instruction sequence.
1294 unsigned DstReg = MI->getOperand(0).getReg();
1295 unsigned ImmVal = (unsigned)MI->getOperand(1).getImm();
1297 unsigned SOImmValV1 = ARM_AM::getSOImmTwoPartFirst(ImmVal);
1298 unsigned SOImmValV2 = ARM_AM::getSOImmTwoPartSecond(ImmVal);
1302 TmpInst.setOpcode(ARM::MOVi);
1303 TmpInst.addOperand(MCOperand::CreateReg(DstReg));
1304 TmpInst.addOperand(MCOperand::CreateImm(SOImmValV1));
1307 TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
1308 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(3).getReg()));
1310 TmpInst.addOperand(MCOperand::CreateReg(0)); // cc_out
1311 printMCInst(&TmpInst);
1317 TmpInst.setOpcode(ARM::ORRri);
1318 TmpInst.addOperand(MCOperand::CreateReg(DstReg)); // dstreg
1319 TmpInst.addOperand(MCOperand::CreateReg(DstReg)); // inreg
1320 TmpInst.addOperand(MCOperand::CreateImm(SOImmValV2)); // so_imm
1322 TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
1323 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(3).getReg()));
1325 TmpInst.addOperand(MCOperand::CreateReg(0)); // cc_out
1326 printMCInst(&TmpInst);
1330 case ARM::MOVi32imm: { // FIXME: Remove asmstring from td file.
1331 // This is a hack that lowers as a two instruction sequence.
1332 unsigned DstReg = MI->getOperand(0).getReg();
1333 unsigned ImmVal = (unsigned)MI->getOperand(1).getImm();
1337 TmpInst.setOpcode(ARM::MOVi16);
1338 TmpInst.addOperand(MCOperand::CreateReg(DstReg)); // dstreg
1339 TmpInst.addOperand(MCOperand::CreateImm(ImmVal & 65535)); // lower16(imm)
1342 TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
1343 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(3).getReg()));
1345 printMCInst(&TmpInst);
1351 TmpInst.setOpcode(ARM::MOVTi16);
1352 TmpInst.addOperand(MCOperand::CreateReg(DstReg)); // dstreg
1353 TmpInst.addOperand(MCOperand::CreateReg(DstReg)); // srcreg
1354 TmpInst.addOperand(MCOperand::CreateImm(ImmVal >> 16)); // upper16(imm)
1357 TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
1358 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(3).getReg()));
1360 printMCInst(&TmpInst);
1368 MCInstLowering.Lower(MI, TmpInst);
1370 printMCInst(&TmpInst);
1373 //===----------------------------------------------------------------------===//
1374 // Target Registry Stuff
1375 //===----------------------------------------------------------------------===//
1377 static MCInstPrinter *createARMMCInstPrinter(const Target &T,
1378 unsigned SyntaxVariant,
1379 const MCAsmInfo &MAI,
1381 if (SyntaxVariant == 0)
1382 return new ARMInstPrinter(O, MAI, false);
1386 // Force static initialization.
1387 extern "C" void LLVMInitializeARMAsmPrinter() {
1388 RegisterAsmPrinter<ARMAsmPrinter> X(TheARMTarget);
1389 RegisterAsmPrinter<ARMAsmPrinter> Y(TheThumbTarget);
1391 TargetRegistry::RegisterMCInstPrinter(TheARMTarget, createARMMCInstPrinter);
1392 TargetRegistry::RegisterMCInstPrinter(TheThumbTarget, createARMMCInstPrinter);