1 //===-- ARMAsmPrinter.cpp - ARM LLVM assembly writer ----------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains a printer that converts from our internal representation
11 // of machine-dependent LLVM code to GAS-format ARM assembly language.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "asm-printer"
17 #include "ARMBuildAttrs.h"
18 #include "ARMTargetMachine.h"
19 #include "ARMAddressingModes.h"
20 #include "ARMConstantPoolValue.h"
21 #include "ARMMachineFunctionInfo.h"
22 #include "llvm/Constants.h"
23 #include "llvm/Module.h"
24 #include "llvm/MDNode.h"
25 #include "llvm/CodeGen/AsmPrinter.h"
26 #include "llvm/CodeGen/DwarfWriter.h"
27 #include "llvm/CodeGen/MachineModuleInfo.h"
28 #include "llvm/CodeGen/MachineFunctionPass.h"
29 #include "llvm/CodeGen/MachineJumpTableInfo.h"
30 #include "llvm/Target/TargetAsmInfo.h"
31 #include "llvm/Target/TargetData.h"
32 #include "llvm/Target/TargetMachine.h"
33 #include "llvm/Target/TargetOptions.h"
34 #include "llvm/ADT/Statistic.h"
35 #include "llvm/ADT/StringExtras.h"
36 #include "llvm/ADT/StringSet.h"
37 #include "llvm/Support/Compiler.h"
38 #include "llvm/Support/ErrorHandling.h"
39 #include "llvm/Support/Mangler.h"
40 #include "llvm/Support/MathExtras.h"
41 #include "llvm/Support/raw_ostream.h"
45 STATISTIC(EmittedInsts, "Number of machine instrs printed");
48 class VISIBILITY_HIDDEN ARMAsmPrinter : public AsmPrinter {
51 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
52 /// make the right decision when printing asm code for different targets.
53 const ARMSubtarget *Subtarget;
55 /// AFI - Keep a pointer to ARMFunctionInfo for the current
59 /// MCP - Keep a pointer to constantpool entries of the current
61 const MachineConstantPool *MCP;
63 /// We name each basic block in a Function with a unique number, so
64 /// that we can consistently refer to them later. This is cleared
65 /// at the beginning of each call to runOnMachineFunction().
67 typedef std::map<const Value *, unsigned> ValueMapTy;
68 ValueMapTy NumberForBB;
70 /// GVNonLazyPtrs - Keeps the set of GlobalValues that require
71 /// non-lazy-pointers for indirect access.
72 StringSet<> GVNonLazyPtrs;
74 /// HiddenGVNonLazyPtrs - Keeps the set of GlobalValues with hidden
75 /// visibility that require non-lazy-pointers for indirect access.
76 StringSet<> HiddenGVNonLazyPtrs;
78 /// FnStubs - Keeps the set of external function GlobalAddresses that the
79 /// asm printer should generate stubs for.
82 /// True if asm printer is printing a series of CONSTPOOL_ENTRY.
85 explicit ARMAsmPrinter(raw_ostream &O, TargetMachine &TM,
86 const TargetAsmInfo *T, bool V)
87 : AsmPrinter(O, TM, T, V), DW(0), AFI(NULL), MCP(NULL),
89 Subtarget = &TM.getSubtarget<ARMSubtarget>();
92 virtual const char *getPassName() const {
93 return "ARM Assembly Printer";
96 void printOperand(const MachineInstr *MI, int OpNum,
97 const char *Modifier = 0);
98 void printSOImmOperand(const MachineInstr *MI, int OpNum);
99 void printSOImm2PartOperand(const MachineInstr *MI, int OpNum);
100 void printSORegOperand(const MachineInstr *MI, int OpNum);
101 void printAddrMode2Operand(const MachineInstr *MI, int OpNum);
102 void printAddrMode2OffsetOperand(const MachineInstr *MI, int OpNum);
103 void printAddrMode3Operand(const MachineInstr *MI, int OpNum);
104 void printAddrMode3OffsetOperand(const MachineInstr *MI, int OpNum);
105 void printAddrMode4Operand(const MachineInstr *MI, int OpNum,
106 const char *Modifier = 0);
107 void printAddrMode5Operand(const MachineInstr *MI, int OpNum,
108 const char *Modifier = 0);
109 void printAddrMode6Operand(const MachineInstr *MI, int OpNum);
110 void printAddrModePCOperand(const MachineInstr *MI, int OpNum,
111 const char *Modifier = 0);
112 void printBitfieldInvMaskImmOperand (const MachineInstr *MI, int OpNum);
114 void printThumbITMask(const MachineInstr *MI, int OpNum);
115 void printThumbAddrModeRROperand(const MachineInstr *MI, int OpNum);
116 void printThumbAddrModeRI5Operand(const MachineInstr *MI, int OpNum,
118 void printThumbAddrModeS1Operand(const MachineInstr *MI, int OpNum);
119 void printThumbAddrModeS2Operand(const MachineInstr *MI, int OpNum);
120 void printThumbAddrModeS4Operand(const MachineInstr *MI, int OpNum);
121 void printThumbAddrModeSPOperand(const MachineInstr *MI, int OpNum);
123 void printT2SOOperand(const MachineInstr *MI, int OpNum);
124 void printT2AddrModeImm12Operand(const MachineInstr *MI, int OpNum);
125 void printT2AddrModeImm8Operand(const MachineInstr *MI, int OpNum);
126 void printT2AddrModeImm8s4Operand(const MachineInstr *MI, int OpNum);
127 void printT2AddrModeImm8OffsetOperand(const MachineInstr *MI, int OpNum);
128 void printT2AddrModeSoRegOperand(const MachineInstr *MI, int OpNum);
130 void printPredicateOperand(const MachineInstr *MI, int OpNum);
131 void printSBitModifierOperand(const MachineInstr *MI, int OpNum);
132 void printPCLabel(const MachineInstr *MI, int OpNum);
133 void printRegisterList(const MachineInstr *MI, int OpNum);
134 void printCPInstOperand(const MachineInstr *MI, int OpNum,
135 const char *Modifier);
136 void printJTBlockOperand(const MachineInstr *MI, int OpNum);
138 virtual bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
139 unsigned AsmVariant, const char *ExtraCode);
140 virtual bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNum,
142 const char *ExtraCode);
144 void printModuleLevelGV(const GlobalVariable* GVar);
145 bool printInstruction(const MachineInstr *MI); // autogenerated.
146 void printMachineInstruction(const MachineInstr *MI);
147 bool runOnMachineFunction(MachineFunction &F);
148 bool doInitialization(Module &M);
149 bool doFinalization(Module &M);
151 /// EmitMachineConstantPoolValue - Print a machine constantpool value to
153 virtual void EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV) {
154 printDataDirective(MCPV->getType());
156 ARMConstantPoolValue *ACPV = static_cast<ARMConstantPoolValue*>(MCPV);
157 GlobalValue *GV = ACPV->getGV();
158 std::string Name = GV ? Mang->getValueName(GV) : TAI->getGlobalPrefix();
160 Name += ACPV->getSymbol();
161 if (ACPV->isNonLazyPointer()) {
162 if (GV->hasHiddenVisibility())
163 HiddenGVNonLazyPtrs.insert(Name);
165 GVNonLazyPtrs.insert(Name);
166 printSuffixedName(Name, "$non_lazy_ptr");
167 } else if (ACPV->isStub()) {
168 FnStubs.insert(Name);
169 printSuffixedName(Name, "$stub");
172 if (ACPV->hasModifier()) O << "(" << ACPV->getModifier() << ")";
173 if (ACPV->getPCAdjustment() != 0) {
174 O << "-(" << TAI->getPrivateGlobalPrefix() << "PC"
175 << utostr(ACPV->getLabelId())
176 << "+" << (unsigned)ACPV->getPCAdjustment();
177 if (ACPV->mustAddCurrentAddress())
184 void getAnalysisUsage(AnalysisUsage &AU) const {
185 AsmPrinter::getAnalysisUsage(AU);
186 AU.setPreservesAll();
187 AU.addRequired<MachineModuleInfo>();
188 AU.addRequired<DwarfWriter>();
191 } // end of anonymous namespace
193 #include "ARMGenAsmWriter.inc"
195 /// runOnMachineFunction - This uses the printInstruction()
196 /// method to print assembly for each instruction.
198 bool ARMAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
201 AFI = MF.getInfo<ARMFunctionInfo>();
202 MCP = MF.getConstantPool();
204 SetupMachineFunction(MF);
207 // NOTE: we don't print out constant pools here, they are handled as
211 // Print out labels for the function.
212 const Function *F = MF.getFunction();
213 switch (F->getLinkage()) {
214 default: LLVM_UNREACHABLE("Unknown linkage type!");
215 case Function::PrivateLinkage:
216 case Function::InternalLinkage:
217 SwitchToTextSection("\t.text", F);
219 case Function::ExternalLinkage:
220 SwitchToTextSection("\t.text", F);
221 O << "\t.globl\t" << CurrentFnName << "\n";
223 case Function::WeakAnyLinkage:
224 case Function::WeakODRLinkage:
225 case Function::LinkOnceAnyLinkage:
226 case Function::LinkOnceODRLinkage:
227 if (Subtarget->isTargetDarwin()) {
229 ".section __TEXT,__textcoal_nt,coalesced,pure_instructions", F);
230 O << "\t.globl\t" << CurrentFnName << "\n";
231 O << "\t.weak_definition\t" << CurrentFnName << "\n";
233 O << TAI->getWeakRefDirective() << CurrentFnName << "\n";
238 printVisibility(CurrentFnName, F->getVisibility());
240 if (AFI->isThumbFunction()) {
241 EmitAlignment(MF.getAlignment(), F, AFI->getAlign());
242 O << "\t.code\t16\n";
243 O << "\t.thumb_func";
244 if (Subtarget->isTargetDarwin())
245 O << "\t" << CurrentFnName;
249 EmitAlignment(MF.getAlignment(), F);
252 O << CurrentFnName << ":\n";
253 // Emit pre-function debug information.
254 DW->BeginFunction(&MF);
256 if (Subtarget->isTargetDarwin()) {
257 // If the function is empty, then we need to emit *something*. Otherwise,
258 // the function's label might be associated with something that it wasn't
259 // meant to be associated with. We emit a noop in this situation.
260 MachineFunction::iterator I = MF.begin();
262 if (++I == MF.end() && MF.front().empty())
266 // Print out code for the function.
267 for (MachineFunction::const_iterator I = MF.begin(), E = MF.end();
269 // Print a label for the basic block.
270 if (I != MF.begin()) {
271 printBasicBlockLabel(I, true, true, VerboseAsm);
274 for (MachineBasicBlock::const_iterator II = I->begin(), E = I->end();
276 // Print the assembly for the instruction.
277 printMachineInstruction(II);
281 if (TAI->hasDotTypeDotSizeDirective())
282 O << "\t.size " << CurrentFnName << ", .-" << CurrentFnName << "\n";
284 // Emit post-function debug information.
285 DW->EndFunction(&MF);
292 void ARMAsmPrinter::printOperand(const MachineInstr *MI, int OpNum,
293 const char *Modifier) {
294 const MachineOperand &MO = MI->getOperand(OpNum);
295 switch (MO.getType()) {
296 case MachineOperand::MO_Register: {
297 unsigned Reg = MO.getReg();
298 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
299 if (Modifier && strcmp(Modifier, "dregpair") == 0) {
300 unsigned DRegLo = TRI->getSubReg(Reg, 5); // arm_dsubreg_0
301 unsigned DRegHi = TRI->getSubReg(Reg, 6); // arm_dsubreg_1
303 << TRI->getAsmName(DRegLo) << ',' << TRI->getAsmName(DRegHi)
305 } else if (Modifier && strcmp(Modifier, "dregsingle") == 0) {
306 O << '{' << TRI->getAsmName(Reg) << '}';
308 O << TRI->getAsmName(Reg);
311 LLVM_UNREACHABLE("not implemented");
314 case MachineOperand::MO_Immediate: {
315 if (!Modifier || strcmp(Modifier, "no_hash") != 0)
321 case MachineOperand::MO_MachineBasicBlock:
322 printBasicBlockLabel(MO.getMBB());
324 case MachineOperand::MO_GlobalAddress: {
325 bool isCallOp = Modifier && !strcmp(Modifier, "call");
326 GlobalValue *GV = MO.getGlobal();
327 std::string Name = Mang->getValueName(GV);
328 bool isExt = (GV->isDeclaration() || GV->hasWeakLinkage() ||
329 GV->hasLinkOnceLinkage());
330 if (isExt && isCallOp && Subtarget->isTargetDarwin() &&
331 TM.getRelocationModel() != Reloc::Static) {
332 printSuffixedName(Name, "$stub");
333 FnStubs.insert(Name);
337 printOffset(MO.getOffset());
339 if (isCallOp && Subtarget->isTargetELF() &&
340 TM.getRelocationModel() == Reloc::PIC_)
344 case MachineOperand::MO_ExternalSymbol: {
345 bool isCallOp = Modifier && !strcmp(Modifier, "call");
346 std::string Name(TAI->getGlobalPrefix());
347 Name += MO.getSymbolName();
348 if (isCallOp && Subtarget->isTargetDarwin() &&
349 TM.getRelocationModel() != Reloc::Static) {
350 printSuffixedName(Name, "$stub");
351 FnStubs.insert(Name);
354 if (isCallOp && Subtarget->isTargetELF() &&
355 TM.getRelocationModel() == Reloc::PIC_)
359 case MachineOperand::MO_ConstantPoolIndex:
360 O << TAI->getPrivateGlobalPrefix() << "CPI" << getFunctionNumber()
361 << '_' << MO.getIndex();
363 case MachineOperand::MO_JumpTableIndex:
364 O << TAI->getPrivateGlobalPrefix() << "JTI" << getFunctionNumber()
365 << '_' << MO.getIndex();
368 O << "<unknown operand type>"; abort (); break;
372 static void printSOImm(raw_ostream &O, int64_t V, bool VerboseAsm,
373 const TargetAsmInfo *TAI) {
374 // Break it up into two parts that make up a shifter immediate.
375 V = ARM_AM::getSOImmVal(V);
376 assert(V != -1 && "Not a valid so_imm value!");
378 unsigned Imm = ARM_AM::getSOImmValImm(V);
379 unsigned Rot = ARM_AM::getSOImmValRot(V);
381 // Print low-level immediate formation info, per
382 // A5.1.3: "Data-processing operands - Immediate".
384 O << "#" << Imm << ", " << Rot;
385 // Pretty printed version.
387 O << ' ' << TAI->getCommentString()
388 << ' ' << (int)ARM_AM::rotr32(Imm, Rot);
394 /// printSOImmOperand - SOImm is 4-bit rotate amount in bits 8-11 with 8-bit
395 /// immediate in bits 0-7.
396 void ARMAsmPrinter::printSOImmOperand(const MachineInstr *MI, int OpNum) {
397 const MachineOperand &MO = MI->getOperand(OpNum);
398 assert(MO.isImm() && "Not a valid so_imm value!");
399 printSOImm(O, MO.getImm(), VerboseAsm, TAI);
402 /// printSOImm2PartOperand - SOImm is broken into two pieces using a 'mov'
403 /// followed by an 'orr' to materialize.
404 void ARMAsmPrinter::printSOImm2PartOperand(const MachineInstr *MI, int OpNum) {
405 const MachineOperand &MO = MI->getOperand(OpNum);
406 assert(MO.isImm() && "Not a valid so_imm value!");
407 unsigned V1 = ARM_AM::getSOImmTwoPartFirst(MO.getImm());
408 unsigned V2 = ARM_AM::getSOImmTwoPartSecond(MO.getImm());
409 printSOImm(O, V1, VerboseAsm, TAI);
411 printPredicateOperand(MI, 2);
417 printSOImm(O, V2, VerboseAsm, TAI);
420 // so_reg is a 4-operand unit corresponding to register forms of the A5.1
421 // "Addressing Mode 1 - Data-processing operands" forms. This includes:
423 // REG REG 0,SH_OPC - e.g. R5, ROR R3
424 // REG 0 IMM,SH_OPC - e.g. R5, LSL #3
425 void ARMAsmPrinter::printSORegOperand(const MachineInstr *MI, int Op) {
426 const MachineOperand &MO1 = MI->getOperand(Op);
427 const MachineOperand &MO2 = MI->getOperand(Op+1);
428 const MachineOperand &MO3 = MI->getOperand(Op+2);
430 assert(TargetRegisterInfo::isPhysicalRegister(MO1.getReg()));
431 O << TRI->getAsmName(MO1.getReg());
433 // Print the shift opc.
435 << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO3.getImm()))
439 assert(TargetRegisterInfo::isPhysicalRegister(MO2.getReg()));
440 O << TRI->getAsmName(MO2.getReg());
441 assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0);
443 O << "#" << ARM_AM::getSORegOffset(MO3.getImm());
447 void ARMAsmPrinter::printAddrMode2Operand(const MachineInstr *MI, int Op) {
448 const MachineOperand &MO1 = MI->getOperand(Op);
449 const MachineOperand &MO2 = MI->getOperand(Op+1);
450 const MachineOperand &MO3 = MI->getOperand(Op+2);
452 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
453 printOperand(MI, Op);
457 O << "[" << TRI->getAsmName(MO1.getReg());
460 if (ARM_AM::getAM2Offset(MO3.getImm())) // Don't print +0.
462 << (char)ARM_AM::getAM2Op(MO3.getImm())
463 << ARM_AM::getAM2Offset(MO3.getImm());
469 << (char)ARM_AM::getAM2Op(MO3.getImm())
470 << TRI->getAsmName(MO2.getReg());
472 if (unsigned ShImm = ARM_AM::getAM2Offset(MO3.getImm()))
474 << ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO3.getImm()))
479 void ARMAsmPrinter::printAddrMode2OffsetOperand(const MachineInstr *MI, int Op){
480 const MachineOperand &MO1 = MI->getOperand(Op);
481 const MachineOperand &MO2 = MI->getOperand(Op+1);
484 unsigned ImmOffs = ARM_AM::getAM2Offset(MO2.getImm());
485 assert(ImmOffs && "Malformed indexed load / store!");
487 << (char)ARM_AM::getAM2Op(MO2.getImm())
492 O << (char)ARM_AM::getAM2Op(MO2.getImm())
493 << TRI->getAsmName(MO1.getReg());
495 if (unsigned ShImm = ARM_AM::getAM2Offset(MO2.getImm()))
497 << ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO2.getImm()))
501 void ARMAsmPrinter::printAddrMode3Operand(const MachineInstr *MI, int Op) {
502 const MachineOperand &MO1 = MI->getOperand(Op);
503 const MachineOperand &MO2 = MI->getOperand(Op+1);
504 const MachineOperand &MO3 = MI->getOperand(Op+2);
506 assert(TargetRegisterInfo::isPhysicalRegister(MO1.getReg()));
507 O << "[" << TRI->getAsmName(MO1.getReg());
511 << (char)ARM_AM::getAM3Op(MO3.getImm())
512 << TRI->getAsmName(MO2.getReg())
517 if (unsigned ImmOffs = ARM_AM::getAM3Offset(MO3.getImm()))
519 << (char)ARM_AM::getAM3Op(MO3.getImm())
524 void ARMAsmPrinter::printAddrMode3OffsetOperand(const MachineInstr *MI, int Op){
525 const MachineOperand &MO1 = MI->getOperand(Op);
526 const MachineOperand &MO2 = MI->getOperand(Op+1);
529 O << (char)ARM_AM::getAM3Op(MO2.getImm())
530 << TRI->getAsmName(MO1.getReg());
534 unsigned ImmOffs = ARM_AM::getAM3Offset(MO2.getImm());
535 assert(ImmOffs && "Malformed indexed load / store!");
537 << (char)ARM_AM::getAM3Op(MO2.getImm())
541 void ARMAsmPrinter::printAddrMode4Operand(const MachineInstr *MI, int Op,
542 const char *Modifier) {
543 const MachineOperand &MO1 = MI->getOperand(Op);
544 const MachineOperand &MO2 = MI->getOperand(Op+1);
545 ARM_AM::AMSubMode Mode = ARM_AM::getAM4SubMode(MO2.getImm());
546 if (Modifier && strcmp(Modifier, "submode") == 0) {
547 if (MO1.getReg() == ARM::SP) {
548 bool isLDM = (MI->getOpcode() == ARM::LDM ||
549 MI->getOpcode() == ARM::LDM_RET);
550 O << ARM_AM::getAMSubModeAltStr(Mode, isLDM);
552 O << ARM_AM::getAMSubModeStr(Mode);
554 printOperand(MI, Op);
555 if (ARM_AM::getAM4WBFlag(MO2.getImm()))
560 void ARMAsmPrinter::printAddrMode5Operand(const MachineInstr *MI, int Op,
561 const char *Modifier) {
562 const MachineOperand &MO1 = MI->getOperand(Op);
563 const MachineOperand &MO2 = MI->getOperand(Op+1);
565 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
566 printOperand(MI, Op);
570 assert(TargetRegisterInfo::isPhysicalRegister(MO1.getReg()));
572 if (Modifier && strcmp(Modifier, "submode") == 0) {
573 ARM_AM::AMSubMode Mode = ARM_AM::getAM5SubMode(MO2.getImm());
574 if (MO1.getReg() == ARM::SP) {
575 bool isFLDM = (MI->getOpcode() == ARM::FLDMD ||
576 MI->getOpcode() == ARM::FLDMS);
577 O << ARM_AM::getAMSubModeAltStr(Mode, isFLDM);
579 O << ARM_AM::getAMSubModeStr(Mode);
581 } else if (Modifier && strcmp(Modifier, "base") == 0) {
582 // Used for FSTM{D|S} and LSTM{D|S} operations.
583 O << TRI->getAsmName(MO1.getReg());
584 if (ARM_AM::getAM5WBFlag(MO2.getImm()))
589 O << "[" << TRI->getAsmName(MO1.getReg());
591 if (unsigned ImmOffs = ARM_AM::getAM5Offset(MO2.getImm())) {
593 << (char)ARM_AM::getAM5Op(MO2.getImm())
599 void ARMAsmPrinter::printAddrMode6Operand(const MachineInstr *MI, int Op) {
600 const MachineOperand &MO1 = MI->getOperand(Op);
601 const MachineOperand &MO2 = MI->getOperand(Op+1);
602 const MachineOperand &MO3 = MI->getOperand(Op+2);
604 // FIXME: No support yet for specifying alignment.
605 O << "[" << TRI->getAsmName(MO1.getReg()) << "]";
607 if (ARM_AM::getAM6WBFlag(MO3.getImm())) {
608 if (MO2.getReg() == 0)
611 O << ", " << TRI->getAsmName(MO2.getReg());
615 void ARMAsmPrinter::printAddrModePCOperand(const MachineInstr *MI, int Op,
616 const char *Modifier) {
617 if (Modifier && strcmp(Modifier, "label") == 0) {
618 printPCLabel(MI, Op+1);
622 const MachineOperand &MO1 = MI->getOperand(Op);
623 assert(TargetRegisterInfo::isPhysicalRegister(MO1.getReg()));
624 O << "[pc, +" << TRI->getAsmName(MO1.getReg()) << "]";
628 ARMAsmPrinter::printBitfieldInvMaskImmOperand(const MachineInstr *MI, int Op) {
629 const MachineOperand &MO = MI->getOperand(Op);
630 uint32_t v = ~MO.getImm();
631 int32_t lsb = CountTrailingZeros_32(v);
632 int32_t width = (32 - CountLeadingZeros_32 (v)) - lsb;
633 assert(MO.isImm() && "Not a valid bf_inv_mask_imm value!");
634 O << "#" << lsb << ", #" << width;
637 //===--------------------------------------------------------------------===//
640 ARMAsmPrinter::printThumbITMask(const MachineInstr *MI, int Op) {
641 // (3 - the number of trailing zeros) is the number of then / else.
642 unsigned Mask = MI->getOperand(Op).getImm();
643 unsigned NumTZ = CountTrailingZeros_32(Mask);
644 assert(NumTZ <= 3 && "Invalid IT mask!");
645 for (unsigned Pos = 3, e = NumTZ; Pos >= e; --Pos) {
646 bool T = (Mask & (1 << Pos)) != 0;
655 ARMAsmPrinter::printThumbAddrModeRROperand(const MachineInstr *MI, int Op) {
656 const MachineOperand &MO1 = MI->getOperand(Op);
657 const MachineOperand &MO2 = MI->getOperand(Op+1);
658 O << "[" << TRI->getAsmName(MO1.getReg());
659 O << ", " << TRI->getAsmName(MO2.getReg()) << "]";
663 ARMAsmPrinter::printThumbAddrModeRI5Operand(const MachineInstr *MI, int Op,
665 const MachineOperand &MO1 = MI->getOperand(Op);
666 const MachineOperand &MO2 = MI->getOperand(Op+1);
667 const MachineOperand &MO3 = MI->getOperand(Op+2);
669 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
670 printOperand(MI, Op);
674 O << "[" << TRI->getAsmName(MO1.getReg());
676 O << ", " << TRI->getAsmName(MO3.getReg());
677 else if (unsigned ImmOffs = MO2.getImm()) {
678 O << ", #" << ImmOffs;
686 ARMAsmPrinter::printThumbAddrModeS1Operand(const MachineInstr *MI, int Op) {
687 printThumbAddrModeRI5Operand(MI, Op, 1);
690 ARMAsmPrinter::printThumbAddrModeS2Operand(const MachineInstr *MI, int Op) {
691 printThumbAddrModeRI5Operand(MI, Op, 2);
694 ARMAsmPrinter::printThumbAddrModeS4Operand(const MachineInstr *MI, int Op) {
695 printThumbAddrModeRI5Operand(MI, Op, 4);
698 void ARMAsmPrinter::printThumbAddrModeSPOperand(const MachineInstr *MI,int Op) {
699 const MachineOperand &MO1 = MI->getOperand(Op);
700 const MachineOperand &MO2 = MI->getOperand(Op+1);
701 O << "[" << TRI->getAsmName(MO1.getReg());
702 if (unsigned ImmOffs = MO2.getImm())
703 O << ", #" << ImmOffs << " * 4";
707 //===--------------------------------------------------------------------===//
709 // Constant shifts t2_so_reg is a 2-operand unit corresponding to the Thumb2
710 // register with shift forms.
712 // REG IMM, SH_OPC - e.g. R5, LSL #3
713 void ARMAsmPrinter::printT2SOOperand(const MachineInstr *MI, int OpNum) {
714 const MachineOperand &MO1 = MI->getOperand(OpNum);
715 const MachineOperand &MO2 = MI->getOperand(OpNum+1);
717 unsigned Reg = MO1.getReg();
718 assert(TargetRegisterInfo::isPhysicalRegister(Reg));
719 O << TRI->getAsmName(Reg);
721 // Print the shift opc.
723 << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO2.getImm()))
726 assert(MO2.isImm() && "Not a valid t2_so_reg value!");
727 O << "#" << ARM_AM::getSORegOffset(MO2.getImm());
730 void ARMAsmPrinter::printT2AddrModeImm12Operand(const MachineInstr *MI,
732 const MachineOperand &MO1 = MI->getOperand(OpNum);
733 const MachineOperand &MO2 = MI->getOperand(OpNum+1);
735 O << "[" << TRI->getAsmName(MO1.getReg());
737 unsigned OffImm = MO2.getImm();
738 if (OffImm) // Don't print +0.
739 O << ", #+" << OffImm;
743 void ARMAsmPrinter::printT2AddrModeImm8Operand(const MachineInstr *MI,
745 const MachineOperand &MO1 = MI->getOperand(OpNum);
746 const MachineOperand &MO2 = MI->getOperand(OpNum+1);
748 O << "[" << TRI->getAsmName(MO1.getReg());
750 int32_t OffImm = (int32_t)MO2.getImm();
753 O << ", #-" << -OffImm;
755 O << ", #+" << OffImm;
759 void ARMAsmPrinter::printT2AddrModeImm8s4Operand(const MachineInstr *MI,
761 const MachineOperand &MO1 = MI->getOperand(OpNum);
762 const MachineOperand &MO2 = MI->getOperand(OpNum+1);
764 O << "[" << TRI->getAsmName(MO1.getReg());
766 int32_t OffImm = (int32_t)MO2.getImm() / 4;
769 O << ", #-" << -OffImm << " * 4";
771 O << ", #+" << OffImm << " * 4";
775 void ARMAsmPrinter::printT2AddrModeImm8OffsetOperand(const MachineInstr *MI,
777 const MachineOperand &MO1 = MI->getOperand(OpNum);
778 int32_t OffImm = (int32_t)MO1.getImm();
781 O << "#-" << -OffImm;
786 void ARMAsmPrinter::printT2AddrModeSoRegOperand(const MachineInstr *MI,
788 const MachineOperand &MO1 = MI->getOperand(OpNum);
789 const MachineOperand &MO2 = MI->getOperand(OpNum+1);
790 const MachineOperand &MO3 = MI->getOperand(OpNum+2);
792 O << "[" << TRI->getAsmName(MO1.getReg());
795 O << ", +" << TRI->getAsmName(MO2.getReg());
797 unsigned ShAmt = MO3.getImm();
799 assert(ShAmt <= 3 && "Not a valid Thumb2 addressing mode!");
800 O << ", lsl #" << ShAmt;
807 //===--------------------------------------------------------------------===//
809 void ARMAsmPrinter::printPredicateOperand(const MachineInstr *MI, int OpNum) {
810 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
812 O << ARMCondCodeToString(CC);
815 void ARMAsmPrinter::printSBitModifierOperand(const MachineInstr *MI, int OpNum){
816 unsigned Reg = MI->getOperand(OpNum).getReg();
818 assert(Reg == ARM::CPSR && "Expect ARM CPSR register!");
823 void ARMAsmPrinter::printPCLabel(const MachineInstr *MI, int OpNum) {
824 int Id = (int)MI->getOperand(OpNum).getImm();
825 O << TAI->getPrivateGlobalPrefix() << "PC" << Id;
828 void ARMAsmPrinter::printRegisterList(const MachineInstr *MI, int OpNum) {
830 for (unsigned i = OpNum, e = MI->getNumOperands(); i != e; ++i) {
832 if (i != e-1) O << ", ";
837 void ARMAsmPrinter::printCPInstOperand(const MachineInstr *MI, int OpNum,
838 const char *Modifier) {
839 assert(Modifier && "This operand only works with a modifier!");
840 // There are two aspects to a CONSTANTPOOL_ENTRY operand, the label and the
842 if (!strcmp(Modifier, "label")) {
843 unsigned ID = MI->getOperand(OpNum).getImm();
844 O << TAI->getPrivateGlobalPrefix() << "CPI" << getFunctionNumber()
845 << '_' << ID << ":\n";
847 assert(!strcmp(Modifier, "cpentry") && "Unknown modifier for CPE");
848 unsigned CPI = MI->getOperand(OpNum).getIndex();
850 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPI];
852 if (MCPE.isMachineConstantPoolEntry()) {
853 EmitMachineConstantPoolValue(MCPE.Val.MachineCPVal);
855 EmitGlobalConstant(MCPE.Val.ConstVal);
860 void ARMAsmPrinter::printJTBlockOperand(const MachineInstr *MI, int OpNum) {
861 const MachineOperand &MO1 = MI->getOperand(OpNum);
862 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
863 unsigned JTI = MO1.getIndex();
864 O << TAI->getPrivateGlobalPrefix() << "JTI" << getFunctionNumber()
865 << '_' << JTI << '_' << MO2.getImm() << ":\n";
867 const char *JTEntryDirective = TAI->getJumpTableDirective();
868 if (!JTEntryDirective)
869 JTEntryDirective = TAI->getData32bitsDirective();
871 const MachineFunction *MF = MI->getParent()->getParent();
872 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
873 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
874 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
875 bool UseSet= TAI->getSetDirective() && TM.getRelocationModel() == Reloc::PIC_;
876 std::set<MachineBasicBlock*> JTSets;
877 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
878 MachineBasicBlock *MBB = JTBBs[i];
879 if (UseSet && JTSets.insert(MBB).second)
880 printPICJumpTableSetLabel(JTI, MO2.getImm(), MBB);
882 O << JTEntryDirective << ' ';
884 O << TAI->getPrivateGlobalPrefix() << getFunctionNumber()
885 << '_' << JTI << '_' << MO2.getImm()
886 << "_set_" << MBB->getNumber();
887 else if (TM.getRelocationModel() == Reloc::PIC_) {
888 printBasicBlockLabel(MBB, false, false, false);
889 // If the arch uses custom Jump Table directives, don't calc relative to JT
890 if (!TAI->getJumpTableDirective())
891 O << '-' << TAI->getPrivateGlobalPrefix() << "JTI"
892 << getFunctionNumber() << '_' << JTI << '_' << MO2.getImm();
894 printBasicBlockLabel(MBB, false, false, false);
901 bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
902 unsigned AsmVariant, const char *ExtraCode){
903 // Does this asm operand have a single letter operand modifier?
904 if (ExtraCode && ExtraCode[0]) {
905 if (ExtraCode[1] != 0) return true; // Unknown modifier.
907 switch (ExtraCode[0]) {
908 default: return true; // Unknown modifier.
909 case 'a': // Print as a memory address.
910 if (MI->getOperand(OpNum).isReg()) {
911 O << "[" << TRI->getAsmName(MI->getOperand(OpNum).getReg()) << "]";
915 case 'c': // Don't print "#" before an immediate operand.
916 printOperand(MI, OpNum, "no_hash");
918 case 'P': // Print a VFP double precision register.
919 printOperand(MI, OpNum);
922 if (TM.getTargetData()->isLittleEndian())
926 if (TM.getTargetData()->isBigEndian())
929 case 'H': // Write second word of DI / DF reference.
930 // Verify that this operand has two consecutive registers.
931 if (!MI->getOperand(OpNum).isReg() ||
932 OpNum+1 == MI->getNumOperands() ||
933 !MI->getOperand(OpNum+1).isReg())
935 ++OpNum; // Return the high-part.
939 printOperand(MI, OpNum);
943 bool ARMAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
944 unsigned OpNum, unsigned AsmVariant,
945 const char *ExtraCode) {
946 if (ExtraCode && ExtraCode[0])
947 return true; // Unknown modifier.
948 printAddrMode2Operand(MI, OpNum);
952 void ARMAsmPrinter::printMachineInstruction(const MachineInstr *MI) {
955 int Opc = MI->getOpcode();
957 case ARM::CONSTPOOL_ENTRY:
958 if (!InCPMode && AFI->isThumbFunction()) {
964 if (InCPMode && AFI->isThumbFunction())
968 // Call the autogenerated instruction printer routines.
969 printInstruction(MI);
972 bool ARMAsmPrinter::doInitialization(Module &M) {
974 bool Result = AsmPrinter::doInitialization(M);
975 DW = getAnalysisIfAvailable<DwarfWriter>();
977 // Thumb-2 instructions are supported only in unified assembler syntax mode.
978 if (Subtarget->hasThumb2())
979 O << "\t.syntax unified\n";
981 // Emit ARM Build Attributes
982 if (Subtarget->isTargetELF()) {
984 std::string CPUString = Subtarget->getCPUString();
985 if (CPUString != "generic")
986 O << "\t.cpu " << CPUString << '\n';
988 // FIXME: Emit FPU type
989 if (Subtarget->hasVFP2())
990 O << "\t.eabi_attribute " << ARMBuildAttrs::VFP_arch << ", 2\n";
992 // Signal various FP modes.
994 O << "\t.eabi_attribute " << ARMBuildAttrs::ABI_FP_denormal << ", 1\n"
995 << "\t.eabi_attribute " << ARMBuildAttrs::ABI_FP_exceptions << ", 1\n";
997 if (FiniteOnlyFPMath())
998 O << "\t.eabi_attribute " << ARMBuildAttrs::ABI_FP_number_model << ", 1\n";
1000 O << "\t.eabi_attribute " << ARMBuildAttrs::ABI_FP_number_model << ", 3\n";
1002 // 8-bytes alignment stuff.
1003 O << "\t.eabi_attribute " << ARMBuildAttrs::ABI_align8_needed << ", 1\n"
1004 << "\t.eabi_attribute " << ARMBuildAttrs::ABI_align8_preserved << ", 1\n";
1006 // FIXME: Should we signal R9 usage?
1012 /// PrintUnmangledNameSafely - Print out the printable characters in the name.
1013 /// Don't print things like \\n or \\0.
1014 static void PrintUnmangledNameSafely(const Value *V, raw_ostream &OS) {
1015 for (const char *Name = V->getNameStart(), *E = Name+V->getNameLen();
1021 void ARMAsmPrinter::printModuleLevelGV(const GlobalVariable* GVar) {
1022 const TargetData *TD = TM.getTargetData();
1024 if (!GVar->hasInitializer()) // External global require no code
1027 // Check to see if this is a special global used by LLVM, if so, emit it.
1029 if (EmitSpecialLLVMGlobal(GVar)) {
1030 if (Subtarget->isTargetDarwin() &&
1031 TM.getRelocationModel() == Reloc::Static) {
1032 if (GVar->getName() == "llvm.global_ctors")
1033 O << ".reference .constructors_used\n";
1034 else if (GVar->getName() == "llvm.global_dtors")
1035 O << ".reference .destructors_used\n";
1040 std::string name = Mang->getValueName(GVar);
1041 Constant *C = GVar->getInitializer();
1042 if (isa<MDNode>(C) || isa<MDString>(C))
1044 const Type *Type = C->getType();
1045 unsigned Size = TD->getTypeAllocSize(Type);
1046 unsigned Align = TD->getPreferredAlignmentLog(GVar);
1047 bool isDarwin = Subtarget->isTargetDarwin();
1049 printVisibility(name, GVar->getVisibility());
1051 if (Subtarget->isTargetELF())
1052 O << "\t.type " << name << ",%object\n";
1054 if (C->isNullValue() && !GVar->hasSection() && !GVar->isThreadLocal() &&
1056 TAI->SectionKindForGlobal(GVar) == SectionKind::RODataMergeStr)) {
1057 // FIXME: This seems to be pretty darwin-specific
1059 if (GVar->hasExternalLinkage()) {
1060 SwitchToSection(TAI->SectionForGlobal(GVar));
1061 if (const char *Directive = TAI->getZeroFillDirective()) {
1062 O << "\t.globl\t" << name << "\n";
1063 O << Directive << "__DATA, __common, " << name << ", "
1064 << Size << ", " << Align << "\n";
1069 if (GVar->hasLocalLinkage() || GVar->isWeakForLinker()) {
1070 if (Size == 0) Size = 1; // .comm Foo, 0 is undefined, avoid it.
1073 if (GVar->hasLocalLinkage()) {
1074 O << TAI->getLCOMMDirective() << name << "," << Size
1076 } else if (GVar->hasCommonLinkage()) {
1077 O << TAI->getCOMMDirective() << name << "," << Size
1080 SwitchToSection(TAI->SectionForGlobal(GVar));
1081 O << "\t.globl " << name << '\n'
1082 << TAI->getWeakDefDirective() << name << '\n';
1083 EmitAlignment(Align, GVar);
1086 O << "\t\t\t\t" << TAI->getCommentString() << ' ';
1087 PrintUnmangledNameSafely(GVar, O);
1090 EmitGlobalConstant(C);
1093 } else if (TAI->getLCOMMDirective() != NULL) {
1094 if (GVar->hasLocalLinkage()) {
1095 O << TAI->getLCOMMDirective() << name << "," << Size;
1097 O << TAI->getCOMMDirective() << name << "," << Size;
1098 if (TAI->getCOMMDirectiveTakesAlignment())
1099 O << ',' << (TAI->getAlignmentIsInBytes() ? (1 << Align) : Align);
1102 SwitchToSection(TAI->SectionForGlobal(GVar));
1103 if (GVar->hasLocalLinkage())
1104 O << "\t.local\t" << name << "\n";
1105 O << TAI->getCOMMDirective() << name << "," << Size;
1106 if (TAI->getCOMMDirectiveTakesAlignment())
1107 O << "," << (TAI->getAlignmentIsInBytes() ? (1 << Align) : Align);
1110 O << "\t\t" << TAI->getCommentString() << " ";
1111 PrintUnmangledNameSafely(GVar, O);
1118 SwitchToSection(TAI->SectionForGlobal(GVar));
1119 switch (GVar->getLinkage()) {
1120 case GlobalValue::CommonLinkage:
1121 case GlobalValue::LinkOnceAnyLinkage:
1122 case GlobalValue::LinkOnceODRLinkage:
1123 case GlobalValue::WeakAnyLinkage:
1124 case GlobalValue::WeakODRLinkage:
1126 O << "\t.globl " << name << "\n"
1127 << "\t.weak_definition " << name << "\n";
1129 O << "\t.weak " << name << "\n";
1132 case GlobalValue::AppendingLinkage:
1133 // FIXME: appending linkage variables should go into a section of
1134 // their name or something. For now, just emit them as external.
1135 case GlobalValue::ExternalLinkage:
1136 O << "\t.globl " << name << "\n";
1138 case GlobalValue::PrivateLinkage:
1139 case GlobalValue::InternalLinkage:
1142 LLVM_UNREACHABLE("Unknown linkage type!");
1145 EmitAlignment(Align, GVar);
1148 O << "\t\t\t\t" << TAI->getCommentString() << " ";
1149 PrintUnmangledNameSafely(GVar, O);
1152 if (TAI->hasDotTypeDotSizeDirective())
1153 O << "\t.size " << name << ", " << Size << "\n";
1155 EmitGlobalConstant(C);
1160 bool ARMAsmPrinter::doFinalization(Module &M) {
1161 for (Module::const_global_iterator I = M.global_begin(), E = M.global_end();
1163 printModuleLevelGV(I);
1165 if (Subtarget->isTargetDarwin()) {
1166 SwitchToDataSection("");
1168 // Output stubs for dynamically-linked functions
1169 for (StringSet<>::iterator i = FnStubs.begin(), e = FnStubs.end();
1171 if (TM.getRelocationModel() == Reloc::PIC_)
1172 SwitchToTextSection(".section __TEXT,__picsymbolstub4,symbol_stubs,"
1175 SwitchToTextSection(".section __TEXT,__symbol_stub4,symbol_stubs,"
1179 O << "\t.code\t32\n";
1181 const char *p = i->getKeyData();
1182 printSuffixedName(p, "$stub");
1184 O << "\t.indirect_symbol " << p << "\n";
1186 printSuffixedName(p, "$slp");
1188 if (TM.getRelocationModel() == Reloc::PIC_) {
1189 printSuffixedName(p, "$scv");
1191 O << "\tadd ip, pc, ip\n";
1193 O << "\tldr pc, [ip, #0]\n";
1194 printSuffixedName(p, "$slp");
1197 printSuffixedName(p, "$lazy_ptr");
1198 if (TM.getRelocationModel() == Reloc::PIC_) {
1200 printSuffixedName(p, "$scv");
1204 SwitchToDataSection(".lazy_symbol_pointer", 0);
1205 printSuffixedName(p, "$lazy_ptr");
1207 O << "\t.indirect_symbol " << p << "\n";
1208 O << "\t.long\tdyld_stub_binding_helper\n";
1212 // Output non-lazy-pointers for external and common global variables.
1213 if (!GVNonLazyPtrs.empty()) {
1214 SwitchToDataSection("\t.non_lazy_symbol_pointer", 0);
1215 for (StringSet<>::iterator i = GVNonLazyPtrs.begin(),
1216 e = GVNonLazyPtrs.end(); i != e; ++i) {
1217 const char *p = i->getKeyData();
1218 printSuffixedName(p, "$non_lazy_ptr");
1220 O << "\t.indirect_symbol " << p << "\n";
1221 O << "\t.long\t0\n";
1225 if (!HiddenGVNonLazyPtrs.empty()) {
1226 SwitchToSection(TAI->getDataSection());
1227 for (StringSet<>::iterator i = HiddenGVNonLazyPtrs.begin(),
1228 e = HiddenGVNonLazyPtrs.end(); i != e; ++i) {
1229 const char *p = i->getKeyData();
1231 printSuffixedName(p, "$non_lazy_ptr");
1233 O << "\t.long " << p << "\n";
1238 // Funny Darwin hack: This flag tells the linker that no global symbols
1239 // contain code that falls through to other global symbols (e.g. the obvious
1240 // implementation of multiple entry points). If this doesn't occur, the
1241 // linker can safely perform dead code stripping. Since LLVM never
1242 // generates code that does this, it is always safe to set.
1243 O << "\t.subsections_via_symbols\n";
1246 return AsmPrinter::doFinalization(M);
1249 /// createARMCodePrinterPass - Returns a pass that prints the ARM
1250 /// assembly code for a MachineFunction to the given output stream,
1251 /// using the given target machine description. This should work
1252 /// regardless of whether the function is in SSA form.
1254 FunctionPass *llvm::createARMCodePrinterPass(raw_ostream &o,
1255 ARMBaseTargetMachine &tm,
1257 return new ARMAsmPrinter(o, tm, tm.getTargetAsmInfo(), verbose);
1261 static struct Register {
1263 ARMBaseTargetMachine::registerAsmPrinter(createARMCodePrinterPass);
1268 // Force static initialization.
1269 extern "C" void LLVMInitializeARMAsmPrinter() { }