1 //===-- ARMAsmPrinter.cpp - Print machine code to an ARM .s file ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains a printer that converts from our internal representation
11 // of machine-dependent LLVM code to GAS-format ARM assembly language.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "asm-printer"
17 #include "ARMBuildAttrs.h"
18 #include "ARMAddressingModes.h"
19 #include "ARMConstantPoolValue.h"
20 #include "ARMInstPrinter.h"
21 #include "ARMMachineFunctionInfo.h"
22 #include "ARMMCInstLower.h"
23 #include "ARMTargetMachine.h"
24 #include "llvm/Constants.h"
25 #include "llvm/Module.h"
26 #include "llvm/Type.h"
27 #include "llvm/Assembly/Writer.h"
28 #include "llvm/CodeGen/AsmPrinter.h"
29 #include "llvm/CodeGen/DwarfWriter.h"
30 #include "llvm/CodeGen/MachineModuleInfoImpls.h"
31 #include "llvm/CodeGen/MachineFunctionPass.h"
32 #include "llvm/CodeGen/MachineJumpTableInfo.h"
33 #include "llvm/MC/MCAsmInfo.h"
34 #include "llvm/MC/MCContext.h"
35 #include "llvm/MC/MCInst.h"
36 #include "llvm/MC/MCSectionMachO.h"
37 #include "llvm/MC/MCStreamer.h"
38 #include "llvm/MC/MCSymbol.h"
39 #include "llvm/Target/TargetData.h"
40 #include "llvm/Target/TargetLoweringObjectFile.h"
41 #include "llvm/Target/TargetMachine.h"
42 #include "llvm/Target/TargetOptions.h"
43 #include "llvm/Target/TargetRegistry.h"
44 #include "llvm/ADT/SmallPtrSet.h"
45 #include "llvm/ADT/SmallString.h"
46 #include "llvm/ADT/StringExtras.h"
47 #include "llvm/ADT/StringSet.h"
48 #include "llvm/Support/CommandLine.h"
49 #include "llvm/Support/ErrorHandling.h"
50 #include "llvm/Support/FormattedStream.h"
51 #include "llvm/Support/MathExtras.h"
56 EnableMCInst("enable-arm-mcinst-printer", cl::Hidden,
57 cl::desc("enable experimental asmprinter gunk in the arm backend"));
60 class ARMAsmPrinter : public AsmPrinter {
62 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
63 /// make the right decision when printing asm code for different targets.
64 const ARMSubtarget *Subtarget;
66 /// AFI - Keep a pointer to ARMFunctionInfo for the current
70 /// MCP - Keep a pointer to constantpool entries of the current
72 const MachineConstantPool *MCP;
75 explicit ARMAsmPrinter(formatted_raw_ostream &O, TargetMachine &TM,
76 const MCAsmInfo *T, bool V)
77 : AsmPrinter(O, TM, T, V), AFI(NULL), MCP(NULL) {
78 Subtarget = &TM.getSubtarget<ARMSubtarget>();
81 virtual const char *getPassName() const {
82 return "ARM Assembly Printer";
85 void printMCInst(const MCInst *MI) {
86 ARMInstPrinter(O, *MAI, VerboseAsm).printInstruction(MI);
89 void printInstructionThroughMCStreamer(const MachineInstr *MI);
92 void printOperand(const MachineInstr *MI, int OpNum,
93 const char *Modifier = 0);
94 void printSOImmOperand(const MachineInstr *MI, int OpNum);
95 void printSOImm2PartOperand(const MachineInstr *MI, int OpNum);
96 void printSORegOperand(const MachineInstr *MI, int OpNum);
97 void printAddrMode2Operand(const MachineInstr *MI, int OpNum);
98 void printAddrMode2OffsetOperand(const MachineInstr *MI, int OpNum);
99 void printAddrMode3Operand(const MachineInstr *MI, int OpNum);
100 void printAddrMode3OffsetOperand(const MachineInstr *MI, int OpNum);
101 void printAddrMode4Operand(const MachineInstr *MI, int OpNum,
102 const char *Modifier = 0);
103 void printAddrMode5Operand(const MachineInstr *MI, int OpNum,
104 const char *Modifier = 0);
105 void printAddrMode6Operand(const MachineInstr *MI, int OpNum);
106 void printAddrModePCOperand(const MachineInstr *MI, int OpNum,
107 const char *Modifier = 0);
108 void printBitfieldInvMaskImmOperand (const MachineInstr *MI, int OpNum);
110 void printThumbS4ImmOperand(const MachineInstr *MI, int OpNum);
111 void printThumbITMask(const MachineInstr *MI, int OpNum);
112 void printThumbAddrModeRROperand(const MachineInstr *MI, int OpNum);
113 void printThumbAddrModeRI5Operand(const MachineInstr *MI, int OpNum,
115 void printThumbAddrModeS1Operand(const MachineInstr *MI, int OpNum);
116 void printThumbAddrModeS2Operand(const MachineInstr *MI, int OpNum);
117 void printThumbAddrModeS4Operand(const MachineInstr *MI, int OpNum);
118 void printThumbAddrModeSPOperand(const MachineInstr *MI, int OpNum);
120 void printT2SOOperand(const MachineInstr *MI, int OpNum);
121 void printT2AddrModeImm12Operand(const MachineInstr *MI, int OpNum);
122 void printT2AddrModeImm8Operand(const MachineInstr *MI, int OpNum);
123 void printT2AddrModeImm8s4Operand(const MachineInstr *MI, int OpNum);
124 void printT2AddrModeImm8OffsetOperand(const MachineInstr *MI, int OpNum);
125 void printT2AddrModeSoRegOperand(const MachineInstr *MI, int OpNum);
127 void printPredicateOperand(const MachineInstr *MI, int OpNum);
128 void printSBitModifierOperand(const MachineInstr *MI, int OpNum);
129 void printPCLabel(const MachineInstr *MI, int OpNum);
130 void printRegisterList(const MachineInstr *MI, int OpNum);
131 void printCPInstOperand(const MachineInstr *MI, int OpNum,
132 const char *Modifier);
133 void printJTBlockOperand(const MachineInstr *MI, int OpNum);
134 void printJT2BlockOperand(const MachineInstr *MI, int OpNum);
135 void printTBAddrMode(const MachineInstr *MI, int OpNum);
136 void printNoHashImmediate(const MachineInstr *MI, int OpNum);
137 void printVFPf32ImmOperand(const MachineInstr *MI, int OpNum);
138 void printVFPf64ImmOperand(const MachineInstr *MI, int OpNum);
140 void printHex8ImmOperand(const MachineInstr *MI, int OpNum) {
141 O << "#0x" << utohexstr(MI->getOperand(OpNum).getImm() & 0xff);
143 void printHex16ImmOperand(const MachineInstr *MI, int OpNum) {
144 O << "#0x" << utohexstr(MI->getOperand(OpNum).getImm() & 0xffff);
146 void printHex32ImmOperand(const MachineInstr *MI, int OpNum) {
147 O << "#0x" << utohexstr(MI->getOperand(OpNum).getImm() & 0xffffffff);
149 void printHex64ImmOperand(const MachineInstr *MI, int OpNum) {
150 O << "#0x" << utohexstr(MI->getOperand(OpNum).getImm());
153 virtual bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
154 unsigned AsmVariant, const char *ExtraCode);
155 virtual bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNum,
157 const char *ExtraCode);
159 void printInstruction(const MachineInstr *MI); // autogenerated.
160 static const char *getRegisterName(unsigned RegNo);
162 virtual void EmitInstruction(const MachineInstr *MI);
163 bool runOnMachineFunction(MachineFunction &F);
165 virtual void EmitConstantPool() {} // we emit constant pools customly!
166 virtual void EmitFunctionEntryLabel();
167 void EmitStartOfAsmFile(Module &M);
168 void EmitEndOfAsmFile(Module &M);
170 MCSymbol *GetARMSetPICJumpTableLabel2(unsigned uid, unsigned uid2,
171 const MachineBasicBlock *MBB) const;
172 MCSymbol *GetARMJTIPICJumpTableLabel2(unsigned uid, unsigned uid2) const;
174 /// EmitMachineConstantPoolValue - Print a machine constantpool value to
176 virtual void EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV) {
177 switch (TM.getTargetData()->getTypeAllocSize(MCPV->getType())) {
178 case 1: O << MAI->getData8bitsDirective(0); break;
179 case 2: O << MAI->getData16bitsDirective(0); break;
180 case 4: O << MAI->getData32bitsDirective(0); break;
181 default: assert(0 && "Unknown CPV size");
184 ARMConstantPoolValue *ACPV = static_cast<ARMConstantPoolValue*>(MCPV);
185 SmallString<128> TmpNameStr;
187 if (ACPV->isLSDA()) {
188 raw_svector_ostream(TmpNameStr) << MAI->getPrivateGlobalPrefix() <<
189 "_LSDA_" << getFunctionNumber();
190 O << TmpNameStr.str();
191 } else if (ACPV->isBlockAddress()) {
192 O << GetBlockAddressSymbol(ACPV->getBlockAddress())->getName();
193 } else if (ACPV->isGlobalValue()) {
194 GlobalValue *GV = ACPV->getGV();
195 bool isIndirect = Subtarget->isTargetDarwin() &&
196 Subtarget->GVIsIndirectSymbol(GV, TM.getRelocationModel());
198 O << *GetGlobalValueSymbol(GV);
200 // FIXME: Remove this when Darwin transition to @GOT like syntax.
201 MCSymbol *Sym = GetSymbolWithGlobalValueBase(GV, "$non_lazy_ptr");
204 MachineModuleInfoMachO &MMIMachO =
205 MMI->getObjFileInfo<MachineModuleInfoMachO>();
206 const MCSymbol *&StubSym =
207 GV->hasHiddenVisibility() ? MMIMachO.getHiddenGVStubEntry(Sym) :
208 MMIMachO.getGVStubEntry(Sym);
210 StubSym = GetGlobalValueSymbol(GV);
213 assert(ACPV->isExtSymbol() && "unrecognized constant pool value");
214 O << *GetExternalSymbolSymbol(ACPV->getSymbol());
217 if (ACPV->hasModifier()) O << "(" << ACPV->getModifier() << ")";
218 if (ACPV->getPCAdjustment() != 0) {
219 O << "-(" << MAI->getPrivateGlobalPrefix() << "PC"
220 << getFunctionNumber() << "_" << ACPV->getLabelId()
221 << "+" << (unsigned)ACPV->getPCAdjustment();
222 if (ACPV->mustAddCurrentAddress())
229 void getAnalysisUsage(AnalysisUsage &AU) const {
230 AsmPrinter::getAnalysisUsage(AU);
231 AU.setPreservesAll();
232 AU.addRequired<MachineModuleInfo>();
233 AU.addRequired<DwarfWriter>();
236 } // end of anonymous namespace
238 #include "ARMGenAsmWriter.inc"
240 void ARMAsmPrinter::EmitFunctionEntryLabel() {
241 if (AFI->isThumbFunction()) {
242 O << "\t.code\t16\n";
243 O << "\t.thumb_func";
244 if (Subtarget->isTargetDarwin())
245 O << '\t' << *CurrentFnSym;
249 OutStreamer.EmitLabel(CurrentFnSym);
252 /// runOnMachineFunction - This uses the printInstruction()
253 /// method to print assembly for each instruction.
255 bool ARMAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
256 AFI = MF.getInfo<ARMFunctionInfo>();
257 MCP = MF.getConstantPool();
259 SetupMachineFunction(MF);
262 EmitFunctionHeader();
267 void ARMAsmPrinter::printOperand(const MachineInstr *MI, int OpNum,
268 const char *Modifier) {
269 const MachineOperand &MO = MI->getOperand(OpNum);
270 unsigned TF = MO.getTargetFlags();
272 switch (MO.getType()) {
274 assert(0 && "<unknown operand type>");
275 case MachineOperand::MO_Register: {
276 unsigned Reg = MO.getReg();
277 assert(TargetRegisterInfo::isPhysicalRegister(Reg));
278 if (Modifier && strcmp(Modifier, "dregpair") == 0) {
279 unsigned DRegLo = TRI->getSubReg(Reg, 5); // arm_dsubreg_0
280 unsigned DRegHi = TRI->getSubReg(Reg, 6); // arm_dsubreg_1
282 << getRegisterName(DRegLo) << ',' << getRegisterName(DRegHi)
284 } else if (Modifier && strcmp(Modifier, "lane") == 0) {
285 unsigned RegNum = ARMRegisterInfo::getRegisterNumbering(Reg);
286 unsigned DReg = TRI->getMatchingSuperReg(Reg, RegNum & 1 ? 2 : 1,
287 &ARM::DPR_VFP2RegClass);
288 O << getRegisterName(DReg) << '[' << (RegNum & 1) << ']';
290 assert(!MO.getSubReg() && "Subregs should be eliminated!");
291 O << getRegisterName(Reg);
295 case MachineOperand::MO_Immediate: {
296 int64_t Imm = MO.getImm();
298 if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
299 (TF & ARMII::MO_LO16))
301 else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
302 (TF & ARMII::MO_HI16))
307 case MachineOperand::MO_MachineBasicBlock:
308 O << *MO.getMBB()->getSymbol(OutContext);
310 case MachineOperand::MO_GlobalAddress: {
311 bool isCallOp = Modifier && !strcmp(Modifier, "call");
312 GlobalValue *GV = MO.getGlobal();
314 if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
315 (TF & ARMII::MO_LO16))
317 else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
318 (TF & ARMII::MO_HI16))
320 O << *GetGlobalValueSymbol(GV);
322 printOffset(MO.getOffset());
324 if (isCallOp && Subtarget->isTargetELF() &&
325 TM.getRelocationModel() == Reloc::PIC_)
329 case MachineOperand::MO_ExternalSymbol: {
330 bool isCallOp = Modifier && !strcmp(Modifier, "call");
331 O << *GetExternalSymbolSymbol(MO.getSymbolName());
333 if (isCallOp && Subtarget->isTargetELF() &&
334 TM.getRelocationModel() == Reloc::PIC_)
338 case MachineOperand::MO_ConstantPoolIndex:
339 O << *GetCPISymbol(MO.getIndex());
341 case MachineOperand::MO_JumpTableIndex:
342 O << *GetJTISymbol(MO.getIndex());
347 static void printSOImm(formatted_raw_ostream &O, int64_t V, bool VerboseAsm,
348 const MCAsmInfo *MAI) {
349 // Break it up into two parts that make up a shifter immediate.
350 V = ARM_AM::getSOImmVal(V);
351 assert(V != -1 && "Not a valid so_imm value!");
353 unsigned Imm = ARM_AM::getSOImmValImm(V);
354 unsigned Rot = ARM_AM::getSOImmValRot(V);
356 // Print low-level immediate formation info, per
357 // A5.1.3: "Data-processing operands - Immediate".
359 O << "#" << Imm << ", " << Rot;
360 // Pretty printed version.
362 O.PadToColumn(MAI->getCommentColumn());
363 O << MAI->getCommentString() << ' ';
364 O << (int)ARM_AM::rotr32(Imm, Rot);
371 /// printSOImmOperand - SOImm is 4-bit rotate amount in bits 8-11 with 8-bit
372 /// immediate in bits 0-7.
373 void ARMAsmPrinter::printSOImmOperand(const MachineInstr *MI, int OpNum) {
374 const MachineOperand &MO = MI->getOperand(OpNum);
375 assert(MO.isImm() && "Not a valid so_imm value!");
376 printSOImm(O, MO.getImm(), VerboseAsm, MAI);
379 /// printSOImm2PartOperand - SOImm is broken into two pieces using a 'mov'
380 /// followed by an 'orr' to materialize.
381 void ARMAsmPrinter::printSOImm2PartOperand(const MachineInstr *MI, int OpNum) {
382 const MachineOperand &MO = MI->getOperand(OpNum);
383 assert(MO.isImm() && "Not a valid so_imm value!");
384 unsigned V1 = ARM_AM::getSOImmTwoPartFirst(MO.getImm());
385 unsigned V2 = ARM_AM::getSOImmTwoPartSecond(MO.getImm());
386 printSOImm(O, V1, VerboseAsm, MAI);
388 printPredicateOperand(MI, 2);
394 printSOImm(O, V2, VerboseAsm, MAI);
397 // so_reg is a 4-operand unit corresponding to register forms of the A5.1
398 // "Addressing Mode 1 - Data-processing operands" forms. This includes:
400 // REG REG 0,SH_OPC - e.g. R5, ROR R3
401 // REG 0 IMM,SH_OPC - e.g. R5, LSL #3
402 void ARMAsmPrinter::printSORegOperand(const MachineInstr *MI, int Op) {
403 const MachineOperand &MO1 = MI->getOperand(Op);
404 const MachineOperand &MO2 = MI->getOperand(Op+1);
405 const MachineOperand &MO3 = MI->getOperand(Op+2);
407 O << getRegisterName(MO1.getReg());
409 // Print the shift opc.
411 << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO3.getImm()))
415 O << getRegisterName(MO2.getReg());
416 assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0);
418 O << "#" << ARM_AM::getSORegOffset(MO3.getImm());
422 void ARMAsmPrinter::printAddrMode2Operand(const MachineInstr *MI, int Op) {
423 const MachineOperand &MO1 = MI->getOperand(Op);
424 const MachineOperand &MO2 = MI->getOperand(Op+1);
425 const MachineOperand &MO3 = MI->getOperand(Op+2);
427 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
428 printOperand(MI, Op);
432 O << "[" << getRegisterName(MO1.getReg());
435 if (ARM_AM::getAM2Offset(MO3.getImm())) // Don't print +0.
437 << (char)ARM_AM::getAM2Op(MO3.getImm())
438 << ARM_AM::getAM2Offset(MO3.getImm());
444 << (char)ARM_AM::getAM2Op(MO3.getImm())
445 << getRegisterName(MO2.getReg());
447 if (unsigned ShImm = ARM_AM::getAM2Offset(MO3.getImm()))
449 << ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO3.getImm()))
454 void ARMAsmPrinter::printAddrMode2OffsetOperand(const MachineInstr *MI, int Op){
455 const MachineOperand &MO1 = MI->getOperand(Op);
456 const MachineOperand &MO2 = MI->getOperand(Op+1);
459 unsigned ImmOffs = ARM_AM::getAM2Offset(MO2.getImm());
460 assert(ImmOffs && "Malformed indexed load / store!");
462 << (char)ARM_AM::getAM2Op(MO2.getImm())
467 O << (char)ARM_AM::getAM2Op(MO2.getImm())
468 << getRegisterName(MO1.getReg());
470 if (unsigned ShImm = ARM_AM::getAM2Offset(MO2.getImm()))
472 << ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO2.getImm()))
476 void ARMAsmPrinter::printAddrMode3Operand(const MachineInstr *MI, int Op) {
477 const MachineOperand &MO1 = MI->getOperand(Op);
478 const MachineOperand &MO2 = MI->getOperand(Op+1);
479 const MachineOperand &MO3 = MI->getOperand(Op+2);
481 assert(TargetRegisterInfo::isPhysicalRegister(MO1.getReg()));
482 O << "[" << getRegisterName(MO1.getReg());
486 << (char)ARM_AM::getAM3Op(MO3.getImm())
487 << getRegisterName(MO2.getReg())
492 if (unsigned ImmOffs = ARM_AM::getAM3Offset(MO3.getImm()))
494 << (char)ARM_AM::getAM3Op(MO3.getImm())
499 void ARMAsmPrinter::printAddrMode3OffsetOperand(const MachineInstr *MI, int Op){
500 const MachineOperand &MO1 = MI->getOperand(Op);
501 const MachineOperand &MO2 = MI->getOperand(Op+1);
504 O << (char)ARM_AM::getAM3Op(MO2.getImm())
505 << getRegisterName(MO1.getReg());
509 unsigned ImmOffs = ARM_AM::getAM3Offset(MO2.getImm());
510 assert(ImmOffs && "Malformed indexed load / store!");
512 << (char)ARM_AM::getAM3Op(MO2.getImm())
516 void ARMAsmPrinter::printAddrMode4Operand(const MachineInstr *MI, int Op,
517 const char *Modifier) {
518 const MachineOperand &MO1 = MI->getOperand(Op);
519 const MachineOperand &MO2 = MI->getOperand(Op+1);
520 ARM_AM::AMSubMode Mode = ARM_AM::getAM4SubMode(MO2.getImm());
521 if (Modifier && strcmp(Modifier, "submode") == 0) {
522 if (MO1.getReg() == ARM::SP) {
524 bool isLDM = (MI->getOpcode() == ARM::LDM ||
525 MI->getOpcode() == ARM::LDM_RET ||
526 MI->getOpcode() == ARM::t2LDM ||
527 MI->getOpcode() == ARM::t2LDM_RET);
528 O << ARM_AM::getAMSubModeAltStr(Mode, isLDM);
530 O << ARM_AM::getAMSubModeStr(Mode);
531 } else if (Modifier && strcmp(Modifier, "wide") == 0) {
532 ARM_AM::AMSubMode Mode = ARM_AM::getAM4SubMode(MO2.getImm());
533 if (Mode == ARM_AM::ia)
536 printOperand(MI, Op);
537 if (ARM_AM::getAM4WBFlag(MO2.getImm()))
542 void ARMAsmPrinter::printAddrMode5Operand(const MachineInstr *MI, int Op,
543 const char *Modifier) {
544 const MachineOperand &MO1 = MI->getOperand(Op);
545 const MachineOperand &MO2 = MI->getOperand(Op+1);
547 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
548 printOperand(MI, Op);
552 assert(TargetRegisterInfo::isPhysicalRegister(MO1.getReg()));
554 if (Modifier && strcmp(Modifier, "submode") == 0) {
555 ARM_AM::AMSubMode Mode = ARM_AM::getAM5SubMode(MO2.getImm());
556 O << ARM_AM::getAMSubModeStr(Mode);
558 } else if (Modifier && strcmp(Modifier, "base") == 0) {
559 // Used for FSTM{D|S} and LSTM{D|S} operations.
560 O << getRegisterName(MO1.getReg());
561 if (ARM_AM::getAM5WBFlag(MO2.getImm()))
566 O << "[" << getRegisterName(MO1.getReg());
568 if (unsigned ImmOffs = ARM_AM::getAM5Offset(MO2.getImm())) {
570 << (char)ARM_AM::getAM5Op(MO2.getImm())
576 void ARMAsmPrinter::printAddrMode6Operand(const MachineInstr *MI, int Op) {
577 const MachineOperand &MO1 = MI->getOperand(Op);
578 const MachineOperand &MO2 = MI->getOperand(Op+1);
579 const MachineOperand &MO3 = MI->getOperand(Op+2);
580 const MachineOperand &MO4 = MI->getOperand(Op+3);
582 O << "[" << getRegisterName(MO1.getReg());
584 // FIXME: Both darwin as and GNU as violate ARM docs here.
585 O << ", :" << MO4.getImm();
589 if (ARM_AM::getAM6WBFlag(MO3.getImm())) {
590 if (MO2.getReg() == 0)
593 O << ", " << getRegisterName(MO2.getReg());
597 void ARMAsmPrinter::printAddrModePCOperand(const MachineInstr *MI, int Op,
598 const char *Modifier) {
599 if (Modifier && strcmp(Modifier, "label") == 0) {
600 printPCLabel(MI, Op+1);
604 const MachineOperand &MO1 = MI->getOperand(Op);
605 assert(TargetRegisterInfo::isPhysicalRegister(MO1.getReg()));
606 O << "[pc, +" << getRegisterName(MO1.getReg()) << "]";
610 ARMAsmPrinter::printBitfieldInvMaskImmOperand(const MachineInstr *MI, int Op) {
611 const MachineOperand &MO = MI->getOperand(Op);
612 uint32_t v = ~MO.getImm();
613 int32_t lsb = CountTrailingZeros_32(v);
614 int32_t width = (32 - CountLeadingZeros_32 (v)) - lsb;
615 assert(MO.isImm() && "Not a valid bf_inv_mask_imm value!");
616 O << "#" << lsb << ", #" << width;
619 //===--------------------------------------------------------------------===//
621 void ARMAsmPrinter::printThumbS4ImmOperand(const MachineInstr *MI, int Op) {
622 O << "#" << MI->getOperand(Op).getImm() * 4;
626 ARMAsmPrinter::printThumbITMask(const MachineInstr *MI, int Op) {
627 // (3 - the number of trailing zeros) is the number of then / else.
628 unsigned Mask = MI->getOperand(Op).getImm();
629 unsigned NumTZ = CountTrailingZeros_32(Mask);
630 assert(NumTZ <= 3 && "Invalid IT mask!");
631 for (unsigned Pos = 3, e = NumTZ; Pos > e; --Pos) {
632 bool T = (Mask & (1 << Pos)) == 0;
641 ARMAsmPrinter::printThumbAddrModeRROperand(const MachineInstr *MI, int Op) {
642 const MachineOperand &MO1 = MI->getOperand(Op);
643 const MachineOperand &MO2 = MI->getOperand(Op+1);
644 O << "[" << getRegisterName(MO1.getReg());
645 O << ", " << getRegisterName(MO2.getReg()) << "]";
649 ARMAsmPrinter::printThumbAddrModeRI5Operand(const MachineInstr *MI, int Op,
651 const MachineOperand &MO1 = MI->getOperand(Op);
652 const MachineOperand &MO2 = MI->getOperand(Op+1);
653 const MachineOperand &MO3 = MI->getOperand(Op+2);
655 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
656 printOperand(MI, Op);
660 O << "[" << getRegisterName(MO1.getReg());
662 O << ", " << getRegisterName(MO3.getReg());
663 else if (unsigned ImmOffs = MO2.getImm())
664 O << ", #+" << ImmOffs * Scale;
669 ARMAsmPrinter::printThumbAddrModeS1Operand(const MachineInstr *MI, int Op) {
670 printThumbAddrModeRI5Operand(MI, Op, 1);
673 ARMAsmPrinter::printThumbAddrModeS2Operand(const MachineInstr *MI, int Op) {
674 printThumbAddrModeRI5Operand(MI, Op, 2);
677 ARMAsmPrinter::printThumbAddrModeS4Operand(const MachineInstr *MI, int Op) {
678 printThumbAddrModeRI5Operand(MI, Op, 4);
681 void ARMAsmPrinter::printThumbAddrModeSPOperand(const MachineInstr *MI,int Op) {
682 const MachineOperand &MO1 = MI->getOperand(Op);
683 const MachineOperand &MO2 = MI->getOperand(Op+1);
684 O << "[" << getRegisterName(MO1.getReg());
685 if (unsigned ImmOffs = MO2.getImm())
686 O << ", #+" << ImmOffs*4;
690 //===--------------------------------------------------------------------===//
692 // Constant shifts t2_so_reg is a 2-operand unit corresponding to the Thumb2
693 // register with shift forms.
695 // REG IMM, SH_OPC - e.g. R5, LSL #3
696 void ARMAsmPrinter::printT2SOOperand(const MachineInstr *MI, int OpNum) {
697 const MachineOperand &MO1 = MI->getOperand(OpNum);
698 const MachineOperand &MO2 = MI->getOperand(OpNum+1);
700 unsigned Reg = MO1.getReg();
701 assert(TargetRegisterInfo::isPhysicalRegister(Reg));
702 O << getRegisterName(Reg);
704 // Print the shift opc.
706 << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO2.getImm()))
709 assert(MO2.isImm() && "Not a valid t2_so_reg value!");
710 O << "#" << ARM_AM::getSORegOffset(MO2.getImm());
713 void ARMAsmPrinter::printT2AddrModeImm12Operand(const MachineInstr *MI,
715 const MachineOperand &MO1 = MI->getOperand(OpNum);
716 const MachineOperand &MO2 = MI->getOperand(OpNum+1);
718 O << "[" << getRegisterName(MO1.getReg());
720 unsigned OffImm = MO2.getImm();
721 if (OffImm) // Don't print +0.
722 O << ", #+" << OffImm;
726 void ARMAsmPrinter::printT2AddrModeImm8Operand(const MachineInstr *MI,
728 const MachineOperand &MO1 = MI->getOperand(OpNum);
729 const MachineOperand &MO2 = MI->getOperand(OpNum+1);
731 O << "[" << getRegisterName(MO1.getReg());
733 int32_t OffImm = (int32_t)MO2.getImm();
736 O << ", #-" << -OffImm;
738 O << ", #+" << OffImm;
742 void ARMAsmPrinter::printT2AddrModeImm8s4Operand(const MachineInstr *MI,
744 const MachineOperand &MO1 = MI->getOperand(OpNum);
745 const MachineOperand &MO2 = MI->getOperand(OpNum+1);
747 O << "[" << getRegisterName(MO1.getReg());
749 int32_t OffImm = (int32_t)MO2.getImm() / 4;
752 O << ", #-" << -OffImm * 4;
754 O << ", #+" << OffImm * 4;
758 void ARMAsmPrinter::printT2AddrModeImm8OffsetOperand(const MachineInstr *MI,
760 const MachineOperand &MO1 = MI->getOperand(OpNum);
761 int32_t OffImm = (int32_t)MO1.getImm();
764 O << "#-" << -OffImm;
769 void ARMAsmPrinter::printT2AddrModeSoRegOperand(const MachineInstr *MI,
771 const MachineOperand &MO1 = MI->getOperand(OpNum);
772 const MachineOperand &MO2 = MI->getOperand(OpNum+1);
773 const MachineOperand &MO3 = MI->getOperand(OpNum+2);
775 O << "[" << getRegisterName(MO1.getReg());
777 assert(MO2.getReg() && "Invalid so_reg load / store address!");
778 O << ", " << getRegisterName(MO2.getReg());
780 unsigned ShAmt = MO3.getImm();
782 assert(ShAmt <= 3 && "Not a valid Thumb2 addressing mode!");
783 O << ", lsl #" << ShAmt;
789 //===--------------------------------------------------------------------===//
791 void ARMAsmPrinter::printPredicateOperand(const MachineInstr *MI, int OpNum) {
792 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
794 O << ARMCondCodeToString(CC);
797 void ARMAsmPrinter::printSBitModifierOperand(const MachineInstr *MI, int OpNum){
798 unsigned Reg = MI->getOperand(OpNum).getReg();
800 assert(Reg == ARM::CPSR && "Expect ARM CPSR register!");
805 void ARMAsmPrinter::printPCLabel(const MachineInstr *MI, int OpNum) {
806 int Id = (int)MI->getOperand(OpNum).getImm();
807 O << MAI->getPrivateGlobalPrefix()
808 << "PC" << getFunctionNumber() << "_" << Id;
811 void ARMAsmPrinter::printRegisterList(const MachineInstr *MI, int OpNum) {
813 // Always skip the first operand, it's the optional (and implicit writeback).
814 for (unsigned i = OpNum+1, e = MI->getNumOperands(); i != e; ++i) {
815 if (MI->getOperand(i).isImplicit())
817 if ((int)i != OpNum+1) O << ", ";
823 void ARMAsmPrinter::printCPInstOperand(const MachineInstr *MI, int OpNum,
824 const char *Modifier) {
825 assert(Modifier && "This operand only works with a modifier!");
826 // There are two aspects to a CONSTANTPOOL_ENTRY operand, the label and the
828 if (!strcmp(Modifier, "label")) {
829 unsigned ID = MI->getOperand(OpNum).getImm();
830 O << *GetCPISymbol(ID) << ":\n";
832 assert(!strcmp(Modifier, "cpentry") && "Unknown modifier for CPE");
833 unsigned CPI = MI->getOperand(OpNum).getIndex();
835 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPI];
837 if (MCPE.isMachineConstantPoolEntry()) {
838 EmitMachineConstantPoolValue(MCPE.Val.MachineCPVal);
840 EmitGlobalConstant(MCPE.Val.ConstVal);
845 MCSymbol *ARMAsmPrinter::
846 GetARMSetPICJumpTableLabel2(unsigned uid, unsigned uid2,
847 const MachineBasicBlock *MBB) const {
848 SmallString<60> Name;
849 raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix()
850 << getFunctionNumber() << '_' << uid << '_' << uid2
851 << "_set_" << MBB->getNumber();
852 return OutContext.GetOrCreateSymbol(Name.str());
855 MCSymbol *ARMAsmPrinter::
856 GetARMJTIPICJumpTableLabel2(unsigned uid, unsigned uid2) const {
857 SmallString<60> Name;
858 raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix() << "JTI"
859 << getFunctionNumber() << '_' << uid << '_' << uid2;
860 return OutContext.GetOrCreateSymbol(Name.str());
863 void ARMAsmPrinter::printJTBlockOperand(const MachineInstr *MI, int OpNum) {
864 assert(!Subtarget->isThumb2() && "Thumb2 should use double-jump jumptables!");
866 const MachineOperand &MO1 = MI->getOperand(OpNum);
867 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
869 unsigned JTI = MO1.getIndex();
870 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
871 OutStreamer.EmitLabel(JTISymbol);
873 const char *JTEntryDirective = MAI->getData32bitsDirective();
875 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
876 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
877 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
878 bool UseSet= MAI->hasSetDirective() && TM.getRelocationModel() == Reloc::PIC_;
879 SmallPtrSet<MachineBasicBlock*, 8> JTSets;
880 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
881 MachineBasicBlock *MBB = JTBBs[i];
882 bool isNew = JTSets.insert(MBB);
884 if (UseSet && isNew) {
886 << *GetARMSetPICJumpTableLabel2(JTI, MO2.getImm(), MBB) << ','
887 << *MBB->getSymbol(OutContext) << '-' << *JTISymbol << '\n';
890 O << JTEntryDirective << ' ';
892 O << *GetARMSetPICJumpTableLabel2(JTI, MO2.getImm(), MBB);
893 else if (TM.getRelocationModel() == Reloc::PIC_)
894 O << *MBB->getSymbol(OutContext) << '-' << *JTISymbol;
896 O << *MBB->getSymbol(OutContext);
903 void ARMAsmPrinter::printJT2BlockOperand(const MachineInstr *MI, int OpNum) {
904 const MachineOperand &MO1 = MI->getOperand(OpNum);
905 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
906 unsigned JTI = MO1.getIndex();
908 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
909 OutStreamer.EmitLabel(JTISymbol);
911 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
912 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
913 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
914 bool ByteOffset = false, HalfWordOffset = false;
915 if (MI->getOpcode() == ARM::t2TBB)
917 else if (MI->getOpcode() == ARM::t2TBH)
918 HalfWordOffset = true;
920 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
921 MachineBasicBlock *MBB = JTBBs[i];
923 O << MAI->getData8bitsDirective();
924 else if (HalfWordOffset)
925 O << MAI->getData16bitsDirective();
927 if (ByteOffset || HalfWordOffset)
928 O << '(' << *MBB->getSymbol(OutContext) << "-" << *JTISymbol << ")/2";
930 O << "\tb.w " << *MBB->getSymbol(OutContext);
936 // Make sure the instruction that follows TBB is 2-byte aligned.
937 // FIXME: Constant island pass should insert an "ALIGN" instruction instead.
938 if (ByteOffset && (JTBBs.size() & 1)) {
944 void ARMAsmPrinter::printTBAddrMode(const MachineInstr *MI, int OpNum) {
945 O << "[pc, " << getRegisterName(MI->getOperand(OpNum).getReg());
946 if (MI->getOpcode() == ARM::t2TBH)
951 void ARMAsmPrinter::printNoHashImmediate(const MachineInstr *MI, int OpNum) {
952 O << MI->getOperand(OpNum).getImm();
955 void ARMAsmPrinter::printVFPf32ImmOperand(const MachineInstr *MI, int OpNum) {
956 const ConstantFP *FP = MI->getOperand(OpNum).getFPImm();
957 O << '#' << FP->getValueAPF().convertToFloat();
959 O.PadToColumn(MAI->getCommentColumn());
960 O << MAI->getCommentString() << ' ';
961 WriteAsOperand(O, FP, /*PrintType=*/false);
965 void ARMAsmPrinter::printVFPf64ImmOperand(const MachineInstr *MI, int OpNum) {
966 const ConstantFP *FP = MI->getOperand(OpNum).getFPImm();
967 O << '#' << FP->getValueAPF().convertToDouble();
969 O.PadToColumn(MAI->getCommentColumn());
970 O << MAI->getCommentString() << ' ';
971 WriteAsOperand(O, FP, /*PrintType=*/false);
975 bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
976 unsigned AsmVariant, const char *ExtraCode){
977 // Does this asm operand have a single letter operand modifier?
978 if (ExtraCode && ExtraCode[0]) {
979 if (ExtraCode[1] != 0) return true; // Unknown modifier.
981 switch (ExtraCode[0]) {
982 default: return true; // Unknown modifier.
983 case 'a': // Print as a memory address.
984 if (MI->getOperand(OpNum).isReg()) {
985 O << "[" << getRegisterName(MI->getOperand(OpNum).getReg()) << "]";
989 case 'c': // Don't print "#" before an immediate operand.
990 if (!MI->getOperand(OpNum).isImm())
992 printNoHashImmediate(MI, OpNum);
994 case 'P': // Print a VFP double precision register.
995 case 'q': // Print a NEON quad precision register.
996 printOperand(MI, OpNum);
999 if (TM.getTargetData()->isLittleEndian())
1003 if (TM.getTargetData()->isBigEndian())
1006 case 'H': // Write second word of DI / DF reference.
1007 // Verify that this operand has two consecutive registers.
1008 if (!MI->getOperand(OpNum).isReg() ||
1009 OpNum+1 == MI->getNumOperands() ||
1010 !MI->getOperand(OpNum+1).isReg())
1012 ++OpNum; // Return the high-part.
1016 printOperand(MI, OpNum);
1020 bool ARMAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
1021 unsigned OpNum, unsigned AsmVariant,
1022 const char *ExtraCode) {
1023 if (ExtraCode && ExtraCode[0])
1024 return true; // Unknown modifier.
1026 const MachineOperand &MO = MI->getOperand(OpNum);
1027 assert(MO.isReg() && "unexpected inline asm memory operand");
1028 O << "[" << getRegisterName(MO.getReg()) << "]";
1032 void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) {
1034 printInstructionThroughMCStreamer(MI);
1036 int Opc = MI->getOpcode();
1037 if (Opc == ARM::CONSTPOOL_ENTRY)
1040 printInstruction(MI);
1044 void ARMAsmPrinter::EmitStartOfAsmFile(Module &M) {
1045 if (Subtarget->isTargetDarwin()) {
1046 Reloc::Model RelocM = TM.getRelocationModel();
1047 if (RelocM == Reloc::PIC_ || RelocM == Reloc::DynamicNoPIC) {
1048 // Declare all the text sections up front (before the DWARF sections
1049 // emitted by AsmPrinter::doInitialization) so the assembler will keep
1050 // them together at the beginning of the object file. This helps
1051 // avoid out-of-range branches that are due a fundamental limitation of
1052 // the way symbol offsets are encoded with the current Darwin ARM
1054 TargetLoweringObjectFileMachO &TLOFMacho =
1055 static_cast<TargetLoweringObjectFileMachO &>(getObjFileLowering());
1056 OutStreamer.SwitchSection(TLOFMacho.getTextSection());
1057 OutStreamer.SwitchSection(TLOFMacho.getTextCoalSection());
1058 OutStreamer.SwitchSection(TLOFMacho.getConstTextCoalSection());
1059 if (RelocM == Reloc::DynamicNoPIC) {
1060 const MCSection *sect =
1061 TLOFMacho.getMachOSection("__TEXT", "__symbol_stub4",
1062 MCSectionMachO::S_SYMBOL_STUBS,
1063 12, SectionKind::getText());
1064 OutStreamer.SwitchSection(sect);
1066 const MCSection *sect =
1067 TLOFMacho.getMachOSection("__TEXT", "__picsymbolstub4",
1068 MCSectionMachO::S_SYMBOL_STUBS,
1069 16, SectionKind::getText());
1070 OutStreamer.SwitchSection(sect);
1075 // Use unified assembler syntax.
1076 O << "\t.syntax unified\n";
1078 // Emit ARM Build Attributes
1079 if (Subtarget->isTargetELF()) {
1081 std::string CPUString = Subtarget->getCPUString();
1082 if (CPUString != "generic")
1083 O << "\t.cpu " << CPUString << '\n';
1085 // FIXME: Emit FPU type
1086 if (Subtarget->hasVFP2())
1087 O << "\t.eabi_attribute " << ARMBuildAttrs::VFP_arch << ", 2\n";
1089 // Signal various FP modes.
1091 O << "\t.eabi_attribute " << ARMBuildAttrs::ABI_FP_denormal << ", 1\n"
1092 << "\t.eabi_attribute " << ARMBuildAttrs::ABI_FP_exceptions << ", 1\n";
1094 if (FiniteOnlyFPMath())
1095 O << "\t.eabi_attribute " << ARMBuildAttrs::ABI_FP_number_model << ", 1\n";
1097 O << "\t.eabi_attribute " << ARMBuildAttrs::ABI_FP_number_model << ", 3\n";
1099 // 8-bytes alignment stuff.
1100 O << "\t.eabi_attribute " << ARMBuildAttrs::ABI_align8_needed << ", 1\n"
1101 << "\t.eabi_attribute " << ARMBuildAttrs::ABI_align8_preserved << ", 1\n";
1103 // Hard float. Use both S and D registers and conform to AAPCS-VFP.
1104 if (Subtarget->isAAPCS_ABI() && FloatABIType == FloatABI::Hard)
1105 O << "\t.eabi_attribute " << ARMBuildAttrs::ABI_HardFP_use << ", 3\n"
1106 << "\t.eabi_attribute " << ARMBuildAttrs::ABI_VFP_args << ", 1\n";
1108 // FIXME: Should we signal R9 usage?
1113 void ARMAsmPrinter::EmitEndOfAsmFile(Module &M) {
1114 if (Subtarget->isTargetDarwin()) {
1115 // All darwin targets use mach-o.
1116 TargetLoweringObjectFileMachO &TLOFMacho =
1117 static_cast<TargetLoweringObjectFileMachO &>(getObjFileLowering());
1118 MachineModuleInfoMachO &MMIMacho =
1119 MMI->getObjFileInfo<MachineModuleInfoMachO>();
1123 // Output non-lazy-pointers for external and common global variables.
1124 MachineModuleInfoMachO::SymbolListTy Stubs = MMIMacho.GetGVStubList();
1126 if (!Stubs.empty()) {
1127 // Switch with ".non_lazy_symbol_pointer" directive.
1128 OutStreamer.SwitchSection(TLOFMacho.getNonLazySymbolPointerSection());
1130 for (unsigned i = 0, e = Stubs.size(); i != e; ++i) {
1131 O << *Stubs[i].first << ":\n\t.indirect_symbol ";
1132 O << *Stubs[i].second << "\n\t.long\t0\n";
1136 Stubs = MMIMacho.GetHiddenGVStubList();
1137 if (!Stubs.empty()) {
1138 OutStreamer.SwitchSection(getObjFileLowering().getDataSection());
1140 for (unsigned i = 0, e = Stubs.size(); i != e; ++i)
1141 O << *Stubs[i].first << ":\n\t.long " << *Stubs[i].second << "\n";
1144 // Funny Darwin hack: This flag tells the linker that no global symbols
1145 // contain code that falls through to other global symbols (e.g. the obvious
1146 // implementation of multiple entry points). If this doesn't occur, the
1147 // linker can safely perform dead code stripping. Since LLVM never
1148 // generates code that does this, it is always safe to set.
1149 OutStreamer.EmitAssemblerFlag(MCAF_SubsectionsViaSymbols);
1153 //===----------------------------------------------------------------------===//
1155 void ARMAsmPrinter::printInstructionThroughMCStreamer(const MachineInstr *MI) {
1156 ARMMCInstLower MCInstLowering(OutContext, *Mang, *this);
1157 switch (MI->getOpcode()) {
1158 case ARM::t2MOVi32imm:
1159 assert(0 && "Should be lowered by thumb2it pass");
1161 case TargetInstrInfo::DBG_LABEL:
1162 case TargetInstrInfo::EH_LABEL:
1163 case TargetInstrInfo::GC_LABEL:
1166 case TargetInstrInfo::KILL:
1169 case TargetInstrInfo::INLINEASM:
1172 case TargetInstrInfo::IMPLICIT_DEF:
1173 printImplicitDef(MI);
1175 case ARM::PICADD: { // FIXME: Remove asm string from td file.
1176 // This is a pseudo op for a label + instruction sequence, which looks like:
1179 // This adds the address of LPC0 to r0.
1182 // FIXME: MOVE TO SHARED PLACE.
1183 unsigned Id = (unsigned)MI->getOperand(2).getImm();
1184 const char *Prefix = MAI->getPrivateGlobalPrefix();
1185 MCSymbol *Label =OutContext.GetOrCreateSymbol(Twine(Prefix)
1186 + "PC" + Twine(getFunctionNumber()) + "_" + Twine(Id));
1187 OutStreamer.EmitLabel(Label);
1190 // Form and emit tha dd.
1192 AddInst.setOpcode(ARM::ADDrr);
1193 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1194 AddInst.addOperand(MCOperand::CreateReg(ARM::PC));
1195 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1196 printMCInst(&AddInst);
1199 case ARM::CONSTPOOL_ENTRY: { // FIXME: Remove asm string from td file.
1200 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool
1201 /// in the function. The first operand is the ID# for this instruction, the
1202 /// second is the index into the MachineConstantPool that this is, the third
1203 /// is the size in bytes of this constant pool entry.
1204 unsigned LabelId = (unsigned)MI->getOperand(0).getImm();
1205 unsigned CPIdx = (unsigned)MI->getOperand(1).getIndex();
1208 OutStreamer.EmitLabel(GetCPISymbol(LabelId));
1210 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPIdx];
1211 if (MCPE.isMachineConstantPoolEntry())
1212 EmitMachineConstantPoolValue(MCPE.Val.MachineCPVal);
1214 EmitGlobalConstant(MCPE.Val.ConstVal);
1218 case ARM::MOVi2pieces: { // FIXME: Remove asmstring from td file.
1219 // This is a hack that lowers as a two instruction sequence.
1220 unsigned DstReg = MI->getOperand(0).getReg();
1221 unsigned ImmVal = (unsigned)MI->getOperand(1).getImm();
1223 unsigned SOImmValV1 = ARM_AM::getSOImmTwoPartFirst(ImmVal);
1224 unsigned SOImmValV2 = ARM_AM::getSOImmTwoPartSecond(ImmVal);
1228 TmpInst.setOpcode(ARM::MOVi);
1229 TmpInst.addOperand(MCOperand::CreateReg(DstReg));
1230 TmpInst.addOperand(MCOperand::CreateImm(SOImmValV1));
1233 TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
1234 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(3).getReg()));
1236 TmpInst.addOperand(MCOperand::CreateReg(0)); // cc_out
1237 printMCInst(&TmpInst);
1243 TmpInst.setOpcode(ARM::ORRri);
1244 TmpInst.addOperand(MCOperand::CreateReg(DstReg)); // dstreg
1245 TmpInst.addOperand(MCOperand::CreateReg(DstReg)); // inreg
1246 TmpInst.addOperand(MCOperand::CreateImm(SOImmValV2)); // so_imm
1248 TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
1249 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(3).getReg()));
1251 TmpInst.addOperand(MCOperand::CreateReg(0)); // cc_out
1252 printMCInst(&TmpInst);
1256 case ARM::MOVi32imm: { // FIXME: Remove asmstring from td file.
1257 // This is a hack that lowers as a two instruction sequence.
1258 unsigned DstReg = MI->getOperand(0).getReg();
1259 unsigned ImmVal = (unsigned)MI->getOperand(1).getImm();
1263 TmpInst.setOpcode(ARM::MOVi16);
1264 TmpInst.addOperand(MCOperand::CreateReg(DstReg)); // dstreg
1265 TmpInst.addOperand(MCOperand::CreateImm(ImmVal & 65535)); // lower16(imm)
1268 TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
1269 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(3).getReg()));
1271 printMCInst(&TmpInst);
1277 TmpInst.setOpcode(ARM::MOVTi16);
1278 TmpInst.addOperand(MCOperand::CreateReg(DstReg)); // dstreg
1279 TmpInst.addOperand(MCOperand::CreateReg(DstReg)); // srcreg
1280 TmpInst.addOperand(MCOperand::CreateImm(ImmVal >> 16)); // upper16(imm)
1283 TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
1284 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(3).getReg()));
1286 printMCInst(&TmpInst);
1294 MCInstLowering.Lower(MI, TmpInst);
1296 printMCInst(&TmpInst);
1299 //===----------------------------------------------------------------------===//
1300 // Target Registry Stuff
1301 //===----------------------------------------------------------------------===//
1303 static MCInstPrinter *createARMMCInstPrinter(const Target &T,
1304 unsigned SyntaxVariant,
1305 const MCAsmInfo &MAI,
1307 if (SyntaxVariant == 0)
1308 return new ARMInstPrinter(O, MAI, false);
1312 // Force static initialization.
1313 extern "C" void LLVMInitializeARMAsmPrinter() {
1314 RegisterAsmPrinter<ARMAsmPrinter> X(TheARMTarget);
1315 RegisterAsmPrinter<ARMAsmPrinter> Y(TheThumbTarget);
1317 TargetRegistry::RegisterMCInstPrinter(TheARMTarget, createARMMCInstPrinter);
1318 TargetRegistry::RegisterMCInstPrinter(TheThumbTarget, createARMMCInstPrinter);