1 //===-- ARMAsmParser.cpp - Parse ARM assembly to MCInst instructions ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 #include "ARMSubtarget.h"
12 #include "llvm/MC/MCParser/MCAsmLexer.h"
13 #include "llvm/MC/MCParser/MCAsmParser.h"
14 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
15 #include "llvm/MC/MCStreamer.h"
16 #include "llvm/MC/MCExpr.h"
17 #include "llvm/MC/MCInst.h"
18 #include "llvm/Target/TargetRegistry.h"
19 #include "llvm/Target/TargetAsmParser.h"
20 #include "llvm/Support/SourceMgr.h"
21 #include "llvm/Support/raw_ostream.h"
22 #include "llvm/ADT/SmallVector.h"
23 #include "llvm/ADT/StringSwitch.h"
24 #include "llvm/ADT/Twine.h"
27 // The shift types for register controlled shifts in arm memory addressing
39 class ARMAsmParser : public TargetAsmParser {
44 MCAsmParser &getParser() const { return Parser; }
46 MCAsmLexer &getLexer() const { return Parser.getLexer(); }
48 void Warning(SMLoc L, const Twine &Msg) { Parser.Warning(L, Msg); }
50 bool Error(SMLoc L, const Twine &Msg) { return Parser.Error(L, Msg); }
52 int TryParseRegister();
53 ARMOperand *TryParseRegisterWithWriteBack();
54 ARMOperand *ParseRegisterList();
55 ARMOperand *ParseMemory();
57 bool ParseMemoryOffsetReg(bool &Negative,
58 bool &OffsetRegShifted,
59 enum ShiftType &ShiftType,
60 const MCExpr *&ShiftAmount,
61 const MCExpr *&Offset,
66 bool ParseShift(enum ShiftType &St, const MCExpr *&ShiftAmount, SMLoc &E);
68 ARMOperand *ParseOperand();
70 bool ParseDirectiveWord(unsigned Size, SMLoc L);
72 bool ParseDirectiveThumb(SMLoc L);
74 bool ParseDirectiveThumbFunc(SMLoc L);
76 bool ParseDirectiveCode(SMLoc L);
78 bool ParseDirectiveSyntax(SMLoc L);
80 bool MatchAndEmitInstruction(SMLoc IDLoc,
81 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
84 /// @name Auto-generated Match Functions
87 #define GET_ASSEMBLER_HEADER
88 #include "ARMGenAsmMatcher.inc"
94 ARMAsmParser(const Target &T, MCAsmParser &_Parser, TargetMachine &_TM)
95 : TargetAsmParser(T), Parser(_Parser), TM(_TM) {}
97 virtual bool ParseInstruction(StringRef Name, SMLoc NameLoc,
98 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
100 virtual bool ParseDirective(AsmToken DirectiveID);
102 } // end anonymous namespace
106 /// ARMOperand - Instances of this class represent a parsed ARM machine
108 struct ARMOperand : public MCParsedAsmOperand {
118 SMLoc StartLoc, EndLoc;
122 ARMCC::CondCodes Val;
139 // This is for all forms of ARM address expressions
142 unsigned OffsetRegNum; // used when OffsetIsReg is true
143 const MCExpr *Offset; // used when OffsetIsReg is false
144 const MCExpr *ShiftAmount; // used when OffsetRegShifted is true
145 enum ShiftType ShiftType; // used when OffsetRegShifted is true
147 OffsetRegShifted : 1, // only used when OffsetIsReg is true
151 Negative : 1, // only used when OffsetIsReg is true
157 ARMOperand(const ARMOperand &o) : MCParsedAsmOperand() {
159 StartLoc = o.StartLoc;
180 /// getStartLoc - Get the location of the first token of this operand.
181 SMLoc getStartLoc() const { return StartLoc; }
182 /// getEndLoc - Get the location of the last token of this operand.
183 SMLoc getEndLoc() const { return EndLoc; }
185 ARMCC::CondCodes getCondCode() const {
186 assert(Kind == CondCode && "Invalid access!");
190 StringRef getToken() const {
191 assert(Kind == Token && "Invalid access!");
192 return StringRef(Tok.Data, Tok.Length);
195 unsigned getReg() const {
196 assert(Kind == Register && "Invalid access!");
200 const MCExpr *getImm() const {
201 assert(Kind == Immediate && "Invalid access!");
205 bool isCondCode() const { return Kind == CondCode; }
206 bool isImm() const { return Kind == Immediate; }
207 bool isReg() const { return Kind == Register; }
208 bool isToken() const { return Kind == Token; }
209 bool isMemory() const { return Kind == Memory; }
211 void addExpr(MCInst &Inst, const MCExpr *Expr) const {
212 // Add as immediates when possible. Null MCExpr = 0.
214 Inst.addOperand(MCOperand::CreateImm(0));
215 else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
216 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
218 Inst.addOperand(MCOperand::CreateExpr(Expr));
221 void addCondCodeOperands(MCInst &Inst, unsigned N) const {
222 assert(N == 2 && "Invalid number of operands!");
223 Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
224 // FIXME: What belongs here?
225 Inst.addOperand(MCOperand::CreateReg(0));
228 void addRegOperands(MCInst &Inst, unsigned N) const {
229 assert(N == 1 && "Invalid number of operands!");
230 Inst.addOperand(MCOperand::CreateReg(getReg()));
233 void addImmOperands(MCInst &Inst, unsigned N) const {
234 assert(N == 1 && "Invalid number of operands!");
235 addExpr(Inst, getImm());
239 bool isMemMode5() const {
240 if (!isMemory() || Mem.OffsetIsReg || Mem.OffsetRegShifted ||
241 Mem.Writeback || Mem.Negative)
243 // If there is an offset expression, make sure it's valid.
246 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Mem.Offset);
249 // The offset must be a multiple of 4 in the range 0-1020.
250 int64_t Value = CE->getValue();
251 return ((Value & 0x3) == 0 && Value <= 1020 && Value >= -1020);
254 void addMemMode5Operands(MCInst &Inst, unsigned N) const {
255 assert(N == 2 && isMemMode5() && "Invalid number of operands!");
257 Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
258 assert(!Mem.OffsetIsReg && "invalid mode 5 operand");
259 // FIXME: #-0 is encoded differently than #0. Does the parser preserve
262 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Mem.Offset);
263 assert(CE && "non-constant mode 5 offset operand!");
264 // The MCInst offset operand doesn't include the low two bits (like
265 // the instruction encoding).
266 Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4));
268 Inst.addOperand(MCOperand::CreateImm(0));
271 virtual void dump(raw_ostream &OS) const;
273 static ARMOperand *CreateCondCode(ARMCC::CondCodes CC, SMLoc S) {
274 ARMOperand *Op = new ARMOperand(CondCode);
281 static ARMOperand *CreateToken(StringRef Str, SMLoc S) {
282 ARMOperand *Op = new ARMOperand(Token);
283 Op->Tok.Data = Str.data();
284 Op->Tok.Length = Str.size();
290 static ARMOperand *CreateReg(unsigned RegNum, bool Writeback, SMLoc S,
292 ARMOperand *Op = new ARMOperand(Register);
293 Op->Reg.RegNum = RegNum;
294 Op->Reg.Writeback = Writeback;
300 static ARMOperand *CreateImm(const MCExpr *Val, SMLoc S, SMLoc E) {
301 ARMOperand *Op = new ARMOperand(Immediate);
308 static ARMOperand *CreateMem(unsigned BaseRegNum, bool OffsetIsReg,
309 const MCExpr *Offset, unsigned OffsetRegNum,
310 bool OffsetRegShifted, enum ShiftType ShiftType,
311 const MCExpr *ShiftAmount, bool Preindexed,
312 bool Postindexed, bool Negative, bool Writeback,
314 ARMOperand *Op = new ARMOperand(Memory);
315 Op->Mem.BaseRegNum = BaseRegNum;
316 Op->Mem.OffsetIsReg = OffsetIsReg;
317 Op->Mem.Offset = Offset;
318 Op->Mem.OffsetRegNum = OffsetRegNum;
319 Op->Mem.OffsetRegShifted = OffsetRegShifted;
320 Op->Mem.ShiftType = ShiftType;
321 Op->Mem.ShiftAmount = ShiftAmount;
322 Op->Mem.Preindexed = Preindexed;
323 Op->Mem.Postindexed = Postindexed;
324 Op->Mem.Negative = Negative;
325 Op->Mem.Writeback = Writeback;
333 ARMOperand(KindTy K) : Kind(K) {}
336 } // end anonymous namespace.
338 void ARMOperand::dump(raw_ostream &OS) const {
341 OS << ARMCondCodeToString(getCondCode());
350 OS << "<register " << getReg() << ">";
353 OS << "'" << getToken() << "'";
358 /// @name Auto-generated Match Functions
361 static unsigned MatchRegisterName(StringRef Name);
365 /// Try to parse a register name. The token must be an Identifier when called,
366 /// and if it is a register name the token is eaten and the register number is
367 /// returned. Otherwise return -1.
369 int ARMAsmParser::TryParseRegister() {
370 const AsmToken &Tok = Parser.getTok();
371 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
373 // FIXME: Validate register for the current architecture; we have to do
374 // validation later, so maybe there is no need for this here.
375 int RegNum = MatchRegisterName(Tok.getString());
378 Parser.Lex(); // Eat identifier token.
383 /// Try to parse a register name. The token must be an Identifier when called,
384 /// and if it is a register name the token is eaten and the register number is
385 /// returned. Otherwise return -1.
387 /// TODO this is likely to change to allow different register types and or to
388 /// parse for a specific register type.
389 ARMOperand *ARMAsmParser::TryParseRegisterWithWriteBack() {
390 SMLoc S = Parser.getTok().getLoc();
391 int RegNo = TryParseRegister();
392 if (RegNo == -1) return 0;
394 SMLoc E = Parser.getTok().getLoc();
396 bool Writeback = false;
397 const AsmToken &ExclaimTok = Parser.getTok();
398 if (ExclaimTok.is(AsmToken::Exclaim)) {
399 E = ExclaimTok.getLoc();
401 Parser.Lex(); // Eat exclaim token
404 return ARMOperand::CreateReg(RegNo, Writeback, S, E);
407 /// Parse a register list, return it if successful else return null. The first
408 /// token must be a '{' when called.
409 ARMOperand *ARMAsmParser::ParseRegisterList() {
411 assert(Parser.getTok().is(AsmToken::LCurly) &&
412 "Token is not an Left Curly Brace");
413 S = Parser.getTok().getLoc();
414 Parser.Lex(); // Eat left curly brace token.
416 const AsmToken &RegTok = Parser.getTok();
417 SMLoc RegLoc = RegTok.getLoc();
418 if (RegTok.isNot(AsmToken::Identifier)) {
419 Error(RegLoc, "register expected");
422 int RegNum = MatchRegisterName(RegTok.getString());
424 Error(RegLoc, "register expected");
428 Parser.Lex(); // Eat identifier token.
429 unsigned RegList = 1 << RegNum;
431 int HighRegNum = RegNum;
432 // TODO ranges like "{Rn-Rm}"
433 while (Parser.getTok().is(AsmToken::Comma)) {
434 Parser.Lex(); // Eat comma token.
436 const AsmToken &RegTok = Parser.getTok();
437 SMLoc RegLoc = RegTok.getLoc();
438 if (RegTok.isNot(AsmToken::Identifier)) {
439 Error(RegLoc, "register expected");
442 int RegNum = MatchRegisterName(RegTok.getString());
444 Error(RegLoc, "register expected");
448 if (RegList & (1 << RegNum))
449 Warning(RegLoc, "register duplicated in register list");
450 else if (RegNum <= HighRegNum)
451 Warning(RegLoc, "register not in ascending order in register list");
452 RegList |= 1 << RegNum;
455 Parser.Lex(); // Eat identifier token.
457 const AsmToken &RCurlyTok = Parser.getTok();
458 if (RCurlyTok.isNot(AsmToken::RCurly)) {
459 Error(RCurlyTok.getLoc(), "'}' expected");
462 E = RCurlyTok.getLoc();
463 Parser.Lex(); // Eat left curly brace token.
465 // FIXME: Need to return an operand!
466 Error(E, "FIXME: register list parsing not implemented");
470 /// Parse an arm memory expression, return false if successful else return true
471 /// or an error. The first token must be a '[' when called.
472 /// TODO Only preindexing and postindexing addressing are started, unindexed
473 /// with option, etc are still to do.
474 ARMOperand *ARMAsmParser::ParseMemory() {
476 assert(Parser.getTok().is(AsmToken::LBrac) &&
477 "Token is not an Left Bracket");
478 S = Parser.getTok().getLoc();
479 Parser.Lex(); // Eat left bracket token.
481 const AsmToken &BaseRegTok = Parser.getTok();
482 if (BaseRegTok.isNot(AsmToken::Identifier)) {
483 Error(BaseRegTok.getLoc(), "register expected");
486 int BaseRegNum = TryParseRegister();
487 if (BaseRegNum == -1) {
488 Error(BaseRegTok.getLoc(), "register expected");
492 bool Preindexed = false;
493 bool Postindexed = false;
494 bool OffsetIsReg = false;
495 bool Negative = false;
496 bool Writeback = false;
498 // First look for preindexed address forms, that is after the "[Rn" we now
499 // have to see if the next token is a comma.
500 const AsmToken &Tok = Parser.getTok();
501 if (Tok.is(AsmToken::Comma)) {
503 Parser.Lex(); // Eat comma token.
505 bool OffsetRegShifted;
506 enum ShiftType ShiftType;
507 const MCExpr *ShiftAmount;
508 const MCExpr *Offset;
509 if (ParseMemoryOffsetReg(Negative, OffsetRegShifted, ShiftType, ShiftAmount,
510 Offset, OffsetIsReg, OffsetRegNum, E))
512 const AsmToken &RBracTok = Parser.getTok();
513 if (RBracTok.isNot(AsmToken::RBrac)) {
514 Error(RBracTok.getLoc(), "']' expected");
517 E = RBracTok.getLoc();
518 Parser.Lex(); // Eat right bracket token.
520 const AsmToken &ExclaimTok = Parser.getTok();
521 if (ExclaimTok.is(AsmToken::Exclaim)) {
522 E = ExclaimTok.getLoc();
524 Parser.Lex(); // Eat exclaim token
526 return ARMOperand::CreateMem(BaseRegNum, OffsetIsReg, Offset, OffsetRegNum,
527 OffsetRegShifted, ShiftType, ShiftAmount,
528 Preindexed, Postindexed, Negative, Writeback,
531 // The "[Rn" we have so far was not followed by a comma.
532 else if (Tok.is(AsmToken::RBrac)) {
533 // If there's anything other than the right brace, this is a post indexing
536 Parser.Lex(); // Eat right bracket token.
538 int OffsetRegNum = 0;
539 bool OffsetRegShifted = false;
540 enum ShiftType ShiftType;
541 const MCExpr *ShiftAmount;
542 const MCExpr *Offset = 0;
544 const AsmToken &NextTok = Parser.getTok();
545 if (NextTok.isNot(AsmToken::EndOfStatement)) {
548 if (NextTok.isNot(AsmToken::Comma)) {
549 Error(NextTok.getLoc(), "',' expected");
552 Parser.Lex(); // Eat comma token.
553 if (ParseMemoryOffsetReg(Negative, OffsetRegShifted, ShiftType,
554 ShiftAmount, Offset, OffsetIsReg, OffsetRegNum,
559 return ARMOperand::CreateMem(BaseRegNum, OffsetIsReg, Offset, OffsetRegNum,
560 OffsetRegShifted, ShiftType, ShiftAmount,
561 Preindexed, Postindexed, Negative, Writeback,
568 /// Parse the offset of a memory operand after we have seen "[Rn," or "[Rn],"
569 /// we will parse the following (were +/- means that a plus or minus is
574 /// we return false on success or an error otherwise.
575 bool ARMAsmParser::ParseMemoryOffsetReg(bool &Negative,
576 bool &OffsetRegShifted,
577 enum ShiftType &ShiftType,
578 const MCExpr *&ShiftAmount,
579 const MCExpr *&Offset,
584 OffsetRegShifted = false;
587 const AsmToken &NextTok = Parser.getTok();
588 E = NextTok.getLoc();
589 if (NextTok.is(AsmToken::Plus))
590 Parser.Lex(); // Eat plus token.
591 else if (NextTok.is(AsmToken::Minus)) {
593 Parser.Lex(); // Eat minus token
595 // See if there is a register following the "[Rn," or "[Rn]," we have so far.
596 const AsmToken &OffsetRegTok = Parser.getTok();
597 if (OffsetRegTok.is(AsmToken::Identifier)) {
598 SMLoc CurLoc = OffsetRegTok.getLoc();
599 OffsetRegNum = TryParseRegister();
600 if (OffsetRegNum != -1) {
606 // If we parsed a register as the offset then their can be a shift after that
607 if (OffsetRegNum != -1) {
608 // Look for a comma then a shift
609 const AsmToken &Tok = Parser.getTok();
610 if (Tok.is(AsmToken::Comma)) {
611 Parser.Lex(); // Eat comma token.
613 const AsmToken &Tok = Parser.getTok();
614 if (ParseShift(ShiftType, ShiftAmount, E))
615 return Error(Tok.getLoc(), "shift expected");
616 OffsetRegShifted = true;
619 else { // the "[Rn," or "[Rn,]" we have so far was not followed by "Rm"
620 // Look for #offset following the "[Rn," or "[Rn],"
621 const AsmToken &HashTok = Parser.getTok();
622 if (HashTok.isNot(AsmToken::Hash))
623 return Error(HashTok.getLoc(), "'#' expected");
625 Parser.Lex(); // Eat hash token.
627 if (getParser().ParseExpression(Offset))
629 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
634 /// ParseShift as one of these two:
635 /// ( lsl | lsr | asr | ror ) , # shift_amount
637 /// and returns true if it parses a shift otherwise it returns false.
638 bool ARMAsmParser::ParseShift(ShiftType &St, const MCExpr *&ShiftAmount,
640 const AsmToken &Tok = Parser.getTok();
641 if (Tok.isNot(AsmToken::Identifier))
643 StringRef ShiftName = Tok.getString();
644 if (ShiftName == "lsl" || ShiftName == "LSL")
646 else if (ShiftName == "lsr" || ShiftName == "LSR")
648 else if (ShiftName == "asr" || ShiftName == "ASR")
650 else if (ShiftName == "ror" || ShiftName == "ROR")
652 else if (ShiftName == "rrx" || ShiftName == "RRX")
656 Parser.Lex(); // Eat shift type token.
662 // Otherwise, there must be a '#' and a shift amount.
663 const AsmToken &HashTok = Parser.getTok();
664 if (HashTok.isNot(AsmToken::Hash))
665 return Error(HashTok.getLoc(), "'#' expected");
666 Parser.Lex(); // Eat hash token.
668 if (getParser().ParseExpression(ShiftAmount))
674 /// Parse a arm instruction operand. For now this parses the operand regardless
676 ARMOperand *ARMAsmParser::ParseOperand() {
679 switch (getLexer().getKind()) {
680 case AsmToken::Identifier:
681 if (ARMOperand *Op = TryParseRegisterWithWriteBack())
684 // This was not a register so parse other operands that start with an
685 // identifier (like labels) as expressions and create them as immediates.
687 S = Parser.getTok().getLoc();
688 if (getParser().ParseExpression(IdVal))
690 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
691 return ARMOperand::CreateImm(IdVal, S, E);
692 case AsmToken::LBrac:
693 return ParseMemory();
694 case AsmToken::LCurly:
695 return ParseRegisterList();
698 // TODO: ":lower16:" and ":upper16:" modifiers after # before immediate
699 S = Parser.getTok().getLoc();
701 const MCExpr *ImmVal;
702 if (getParser().ParseExpression(ImmVal))
704 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
705 return ARMOperand::CreateImm(ImmVal, S, E);
707 Error(Parser.getTok().getLoc(), "unexpected token in operand");
712 /// Parse an arm instruction mnemonic followed by its operands.
713 bool ARMAsmParser::ParseInstruction(StringRef Name, SMLoc NameLoc,
714 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
715 // Create the leading tokens for the mnemonic, split by '.' characters.
716 size_t Start = 0, Next = Name.find('.');
717 StringRef Head = Name.slice(Start, Next);
719 // Determine the predicate, if any.
721 // FIXME: We need a way to check whether a prefix supports predication,
722 // otherwise we will end up with an ambiguity for instructions that happen to
723 // end with a predicate name.
724 // FIXME: Likewise, some arithmetic instructions have an 's' prefix which
725 // indicates to update the condition codes. Those instructions have an
726 // additional immediate operand which encodes the prefix as reg0 or CPSR.
727 // Just checking for a suffix of 's' definitely creates ambiguities; e.g,
728 // the SMMLS instruction.
729 unsigned CC = StringSwitch<unsigned>(Head.substr(Head.size()-2))
730 .Case("eq", ARMCC::EQ)
731 .Case("ne", ARMCC::NE)
732 .Case("hs", ARMCC::HS)
733 .Case("lo", ARMCC::LO)
734 .Case("mi", ARMCC::MI)
735 .Case("pl", ARMCC::PL)
736 .Case("vs", ARMCC::VS)
737 .Case("vc", ARMCC::VC)
738 .Case("hi", ARMCC::HI)
739 .Case("ls", ARMCC::LS)
740 .Case("ge", ARMCC::GE)
741 .Case("lt", ARMCC::LT)
742 .Case("gt", ARMCC::GT)
743 .Case("le", ARMCC::LE)
744 .Case("al", ARMCC::AL)
748 (CC == ARMCC::LS && (Head == "vmls" || Head == "vnmls"))) {
751 Head = Head.slice(0, Head.size() - 2);
754 Operands.push_back(ARMOperand::CreateToken(Head, NameLoc));
755 Operands.push_back(ARMOperand::CreateCondCode(ARMCC::CondCodes(CC), NameLoc));
757 // Add the remaining tokens in the mnemonic.
758 while (Next != StringRef::npos) {
760 Next = Name.find('.', Start + 1);
761 Head = Name.slice(Start, Next);
763 Operands.push_back(ARMOperand::CreateToken(Head, NameLoc));
766 // Read the remaining operands.
767 if (getLexer().isNot(AsmToken::EndOfStatement)) {
768 // Read the first operand.
769 if (ARMOperand *Op = ParseOperand())
770 Operands.push_back(Op);
772 Parser.EatToEndOfStatement();
776 while (getLexer().is(AsmToken::Comma)) {
777 Parser.Lex(); // Eat the comma.
779 // Parse and remember the operand.
780 if (ARMOperand *Op = ParseOperand())
781 Operands.push_back(Op);
783 Parser.EatToEndOfStatement();
789 if (getLexer().isNot(AsmToken::EndOfStatement)) {
790 Parser.EatToEndOfStatement();
791 return TokError("unexpected token in argument list");
793 Parser.Lex(); // Consume the EndOfStatement
798 MatchAndEmitInstruction(SMLoc IDLoc,
799 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
803 switch (MatchInstructionImpl(Operands, Inst, ErrorInfo)) {
805 Out.EmitInstruction(Inst);
808 case Match_MissingFeature:
809 Error(IDLoc, "instruction requires a CPU feature not currently enabled");
811 case Match_InvalidOperand: {
812 SMLoc ErrorLoc = IDLoc;
813 if (ErrorInfo != ~0U) {
814 if (ErrorInfo >= Operands.size())
815 return Error(IDLoc, "too few operands for instruction");
817 ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc();
818 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
821 return Error(ErrorLoc, "invalid operand for instruction");
823 case Match_MnemonicFail:
824 return Error(IDLoc, "unrecognized instruction mnemonic");
827 llvm_unreachable("Implement any new match types added!");
832 /// ParseDirective parses the arm specific directives
833 bool ARMAsmParser::ParseDirective(AsmToken DirectiveID) {
834 StringRef IDVal = DirectiveID.getIdentifier();
835 if (IDVal == ".word")
836 return ParseDirectiveWord(4, DirectiveID.getLoc());
837 else if (IDVal == ".thumb")
838 return ParseDirectiveThumb(DirectiveID.getLoc());
839 else if (IDVal == ".thumb_func")
840 return ParseDirectiveThumbFunc(DirectiveID.getLoc());
841 else if (IDVal == ".code")
842 return ParseDirectiveCode(DirectiveID.getLoc());
843 else if (IDVal == ".syntax")
844 return ParseDirectiveSyntax(DirectiveID.getLoc());
848 /// ParseDirectiveWord
849 /// ::= .word [ expression (, expression)* ]
850 bool ARMAsmParser::ParseDirectiveWord(unsigned Size, SMLoc L) {
851 if (getLexer().isNot(AsmToken::EndOfStatement)) {
854 if (getParser().ParseExpression(Value))
857 getParser().getStreamer().EmitValue(Value, Size, 0/*addrspace*/);
859 if (getLexer().is(AsmToken::EndOfStatement))
862 // FIXME: Improve diagnostic.
863 if (getLexer().isNot(AsmToken::Comma))
864 return Error(L, "unexpected token in directive");
873 /// ParseDirectiveThumb
875 bool ARMAsmParser::ParseDirectiveThumb(SMLoc L) {
876 if (getLexer().isNot(AsmToken::EndOfStatement))
877 return Error(L, "unexpected token in directive");
880 // TODO: set thumb mode
881 // TODO: tell the MC streamer the mode
882 // getParser().getStreamer().Emit???();
886 /// ParseDirectiveThumbFunc
887 /// ::= .thumbfunc symbol_name
888 bool ARMAsmParser::ParseDirectiveThumbFunc(SMLoc L) {
889 const AsmToken &Tok = Parser.getTok();
890 if (Tok.isNot(AsmToken::Identifier) && Tok.isNot(AsmToken::String))
891 return Error(L, "unexpected token in .syntax directive");
892 Parser.Lex(); // Consume the identifier token.
894 if (getLexer().isNot(AsmToken::EndOfStatement))
895 return Error(L, "unexpected token in directive");
898 // TODO: mark symbol as a thumb symbol
899 // getParser().getStreamer().Emit???();
903 /// ParseDirectiveSyntax
904 /// ::= .syntax unified | divided
905 bool ARMAsmParser::ParseDirectiveSyntax(SMLoc L) {
906 const AsmToken &Tok = Parser.getTok();
907 if (Tok.isNot(AsmToken::Identifier))
908 return Error(L, "unexpected token in .syntax directive");
909 StringRef Mode = Tok.getString();
910 if (Mode == "unified" || Mode == "UNIFIED")
912 else if (Mode == "divided" || Mode == "DIVIDED")
915 return Error(L, "unrecognized syntax mode in .syntax directive");
917 if (getLexer().isNot(AsmToken::EndOfStatement))
918 return Error(Parser.getTok().getLoc(), "unexpected token in directive");
921 // TODO tell the MC streamer the mode
922 // getParser().getStreamer().Emit???();
926 /// ParseDirectiveCode
927 /// ::= .code 16 | 32
928 bool ARMAsmParser::ParseDirectiveCode(SMLoc L) {
929 const AsmToken &Tok = Parser.getTok();
930 if (Tok.isNot(AsmToken::Integer))
931 return Error(L, "unexpected token in .code directive");
932 int64_t Val = Parser.getTok().getIntVal();
938 return Error(L, "invalid operand to .code directive");
940 if (getLexer().isNot(AsmToken::EndOfStatement))
941 return Error(Parser.getTok().getLoc(), "unexpected token in directive");
944 // TODO tell the MC streamer the mode
945 // getParser().getStreamer().Emit???();
949 extern "C" void LLVMInitializeARMAsmLexer();
951 /// Force static initialization.
952 extern "C" void LLVMInitializeARMAsmParser() {
953 RegisterAsmParser<ARMAsmParser> X(TheARMTarget);
954 RegisterAsmParser<ARMAsmParser> Y(TheThumbTarget);
955 LLVMInitializeARMAsmLexer();
958 #define GET_REGISTER_MATCHER
959 #define GET_MATCHER_IMPLEMENTATION
960 #include "ARMGenAsmMatcher.inc"