1 //===-- ARMAsmParser.cpp - Parse ARM assembly to MCInst instructions ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "ARMFPUName.h"
11 #include "ARMFeatures.h"
12 #include "MCTargetDesc/ARMAddressingModes.h"
13 #include "MCTargetDesc/ARMArchName.h"
14 #include "MCTargetDesc/ARMBaseInfo.h"
15 #include "MCTargetDesc/ARMMCExpr.h"
16 #include "llvm/ADT/STLExtras.h"
17 #include "llvm/ADT/SmallVector.h"
18 #include "llvm/ADT/StringExtras.h"
19 #include "llvm/ADT/StringSwitch.h"
20 #include "llvm/ADT/Twine.h"
21 #include "llvm/MC/MCAsmInfo.h"
22 #include "llvm/MC/MCAssembler.h"
23 #include "llvm/MC/MCContext.h"
24 #include "llvm/MC/MCDisassembler.h"
25 #include "llvm/MC/MCELFStreamer.h"
26 #include "llvm/MC/MCExpr.h"
27 #include "llvm/MC/MCInst.h"
28 #include "llvm/MC/MCInstrDesc.h"
29 #include "llvm/MC/MCInstrInfo.h"
30 #include "llvm/MC/MCObjectFileInfo.h"
31 #include "llvm/MC/MCParser/MCAsmLexer.h"
32 #include "llvm/MC/MCParser/MCAsmParser.h"
33 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
34 #include "llvm/MC/MCRegisterInfo.h"
35 #include "llvm/MC/MCSection.h"
36 #include "llvm/MC/MCStreamer.h"
37 #include "llvm/MC/MCSubtargetInfo.h"
38 #include "llvm/MC/MCSymbol.h"
39 #include "llvm/MC/MCTargetAsmParser.h"
40 #include "llvm/Support/ARMBuildAttributes.h"
41 #include "llvm/Support/ARMEHABI.h"
42 #include "llvm/Support/COFF.h"
43 #include "llvm/Support/Debug.h"
44 #include "llvm/Support/ELF.h"
45 #include "llvm/Support/MathExtras.h"
46 #include "llvm/Support/SourceMgr.h"
47 #include "llvm/Support/TargetRegistry.h"
48 #include "llvm/Support/raw_ostream.h"
56 enum VectorLaneTy { NoLanes, AllLanes, IndexedLane };
61 typedef SmallVector<SMLoc, 4> Locs;
66 Locs PersonalityIndexLocs;
71 UnwindContext(MCAsmParser &P) : Parser(P), FPReg(ARM::SP) {}
73 bool hasFnStart() const { return !FnStartLocs.empty(); }
74 bool cantUnwind() const { return !CantUnwindLocs.empty(); }
75 bool hasHandlerData() const { return !HandlerDataLocs.empty(); }
76 bool hasPersonality() const {
77 return !(PersonalityLocs.empty() && PersonalityIndexLocs.empty());
80 void recordFnStart(SMLoc L) { FnStartLocs.push_back(L); }
81 void recordCantUnwind(SMLoc L) { CantUnwindLocs.push_back(L); }
82 void recordPersonality(SMLoc L) { PersonalityLocs.push_back(L); }
83 void recordHandlerData(SMLoc L) { HandlerDataLocs.push_back(L); }
84 void recordPersonalityIndex(SMLoc L) { PersonalityIndexLocs.push_back(L); }
86 void saveFPReg(int Reg) { FPReg = Reg; }
87 int getFPReg() const { return FPReg; }
89 void emitFnStartLocNotes() const {
90 for (Locs::const_iterator FI = FnStartLocs.begin(), FE = FnStartLocs.end();
92 Parser.Note(*FI, ".fnstart was specified here");
94 void emitCantUnwindLocNotes() const {
95 for (Locs::const_iterator UI = CantUnwindLocs.begin(),
96 UE = CantUnwindLocs.end(); UI != UE; ++UI)
97 Parser.Note(*UI, ".cantunwind was specified here");
99 void emitHandlerDataLocNotes() const {
100 for (Locs::const_iterator HI = HandlerDataLocs.begin(),
101 HE = HandlerDataLocs.end(); HI != HE; ++HI)
102 Parser.Note(*HI, ".handlerdata was specified here");
104 void emitPersonalityLocNotes() const {
105 for (Locs::const_iterator PI = PersonalityLocs.begin(),
106 PE = PersonalityLocs.end(),
107 PII = PersonalityIndexLocs.begin(),
108 PIE = PersonalityIndexLocs.end();
109 PI != PE || PII != PIE;) {
110 if (PI != PE && (PII == PIE || PI->getPointer() < PII->getPointer()))
111 Parser.Note(*PI++, ".personality was specified here");
112 else if (PII != PIE && (PI == PE || PII->getPointer() < PI->getPointer()))
113 Parser.Note(*PII++, ".personalityindex was specified here");
115 llvm_unreachable(".personality and .personalityindex cannot be "
116 "at the same location");
121 FnStartLocs = Locs();
122 CantUnwindLocs = Locs();
123 PersonalityLocs = Locs();
124 HandlerDataLocs = Locs();
125 PersonalityIndexLocs = Locs();
130 class ARMAsmParser : public MCTargetAsmParser {
131 MCSubtargetInfo &STI;
132 const MCInstrInfo &MII;
133 const MCRegisterInfo *MRI;
136 ARMTargetStreamer &getTargetStreamer() {
137 assert(getParser().getStreamer().getTargetStreamer() &&
138 "do not have a target streamer");
139 MCTargetStreamer &TS = *getParser().getStreamer().getTargetStreamer();
140 return static_cast<ARMTargetStreamer &>(TS);
143 // Map of register aliases registers via the .req directive.
144 StringMap<unsigned> RegisterReqs;
146 bool NextSymbolIsThumb;
149 ARMCC::CondCodes Cond; // Condition for IT block.
150 unsigned Mask:4; // Condition mask for instructions.
151 // Starting at first 1 (from lsb).
152 // '1' condition as indicated in IT.
153 // '0' inverse of condition (else).
154 // Count of instructions in IT block is
155 // 4 - trailingzeroes(mask)
157 bool FirstCond; // Explicit flag for when we're parsing the
158 // First instruction in the IT block. It's
159 // implied in the mask, so needs special
162 unsigned CurPosition; // Current position in parsing of IT
163 // block. In range [0,3]. Initialized
164 // according to count of instructions in block.
165 // ~0U if no active IT block.
167 bool inITBlock() { return ITState.CurPosition != ~0U; }
168 bool lastInITBlock() {
169 return ITState.CurPosition == 4 - countTrailingZeros(ITState.Mask);
171 void forwardITPosition() {
172 if (!inITBlock()) return;
173 // Move to the next instruction in the IT block, if there is one. If not,
174 // mark the block as done.
175 unsigned TZ = countTrailingZeros(ITState.Mask);
176 if (++ITState.CurPosition == 5 - TZ)
177 ITState.CurPosition = ~0U; // Done with the IT block after this.
180 void Note(SMLoc L, const Twine &Msg, ArrayRef<SMRange> Ranges = None) {
181 return getParser().Note(L, Msg, Ranges);
183 bool Warning(SMLoc L, const Twine &Msg,
184 ArrayRef<SMRange> Ranges = None) {
185 return getParser().Warning(L, Msg, Ranges);
187 bool Error(SMLoc L, const Twine &Msg,
188 ArrayRef<SMRange> Ranges = None) {
189 return getParser().Error(L, Msg, Ranges);
192 bool validatetLDMRegList(MCInst Inst, const OperandVector &Operands,
193 unsigned ListNo, bool IsARPop = false);
194 bool validatetSTMRegList(MCInst Inst, const OperandVector &Operands,
197 int tryParseRegister();
198 bool tryParseRegisterWithWriteBack(OperandVector &);
199 int tryParseShiftRegister(OperandVector &);
200 bool parseRegisterList(OperandVector &);
201 bool parseMemory(OperandVector &);
202 bool parseOperand(OperandVector &, StringRef Mnemonic);
203 bool parsePrefix(ARMMCExpr::VariantKind &RefKind);
204 bool parseMemRegOffsetShift(ARM_AM::ShiftOpc &ShiftType,
205 unsigned &ShiftAmount);
206 bool parseLiteralValues(unsigned Size, SMLoc L);
207 bool parseDirectiveThumb(SMLoc L);
208 bool parseDirectiveARM(SMLoc L);
209 bool parseDirectiveThumbFunc(SMLoc L);
210 bool parseDirectiveCode(SMLoc L);
211 bool parseDirectiveSyntax(SMLoc L);
212 bool parseDirectiveReq(StringRef Name, SMLoc L);
213 bool parseDirectiveUnreq(SMLoc L);
214 bool parseDirectiveArch(SMLoc L);
215 bool parseDirectiveEabiAttr(SMLoc L);
216 bool parseDirectiveCPU(SMLoc L);
217 bool parseDirectiveFPU(SMLoc L);
218 bool parseDirectiveFnStart(SMLoc L);
219 bool parseDirectiveFnEnd(SMLoc L);
220 bool parseDirectiveCantUnwind(SMLoc L);
221 bool parseDirectivePersonality(SMLoc L);
222 bool parseDirectiveHandlerData(SMLoc L);
223 bool parseDirectiveSetFP(SMLoc L);
224 bool parseDirectivePad(SMLoc L);
225 bool parseDirectiveRegSave(SMLoc L, bool IsVector);
226 bool parseDirectiveInst(SMLoc L, char Suffix = '\0');
227 bool parseDirectiveLtorg(SMLoc L);
228 bool parseDirectiveEven(SMLoc L);
229 bool parseDirectivePersonalityIndex(SMLoc L);
230 bool parseDirectiveUnwindRaw(SMLoc L);
231 bool parseDirectiveTLSDescSeq(SMLoc L);
232 bool parseDirectiveMovSP(SMLoc L);
233 bool parseDirectiveObjectArch(SMLoc L);
234 bool parseDirectiveArchExtension(SMLoc L);
235 bool parseDirectiveAlign(SMLoc L);
236 bool parseDirectiveThumbSet(SMLoc L);
238 StringRef splitMnemonic(StringRef Mnemonic, unsigned &PredicationCode,
239 bool &CarrySetting, unsigned &ProcessorIMod,
241 void getMnemonicAcceptInfo(StringRef Mnemonic, StringRef FullInst,
242 bool &CanAcceptCarrySet,
243 bool &CanAcceptPredicationCode);
245 bool isThumb() const {
246 // FIXME: Can tablegen auto-generate this?
247 return (STI.getFeatureBits() & ARM::ModeThumb) != 0;
249 bool isThumbOne() const {
250 return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2) == 0;
252 bool isThumbTwo() const {
253 return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2);
255 bool hasThumb() const {
256 return STI.getFeatureBits() & ARM::HasV4TOps;
258 bool hasV6Ops() const {
259 return STI.getFeatureBits() & ARM::HasV6Ops;
261 bool hasV6MOps() const {
262 return STI.getFeatureBits() & ARM::HasV6MOps;
264 bool hasV7Ops() const {
265 return STI.getFeatureBits() & ARM::HasV7Ops;
267 bool hasV8Ops() const {
268 return STI.getFeatureBits() & ARM::HasV8Ops;
270 bool hasARM() const {
271 return !(STI.getFeatureBits() & ARM::FeatureNoARM);
273 bool hasThumb2DSP() const {
274 return STI.getFeatureBits() & ARM::FeatureDSPThumb2;
276 bool hasD16() const {
277 return STI.getFeatureBits() & ARM::FeatureD16;
281 uint64_t FB = ComputeAvailableFeatures(STI.ToggleFeature(ARM::ModeThumb));
282 setAvailableFeatures(FB);
284 bool isMClass() const {
285 return STI.getFeatureBits() & ARM::FeatureMClass;
288 /// @name Auto-generated Match Functions
291 #define GET_ASSEMBLER_HEADER
292 #include "ARMGenAsmMatcher.inc"
296 OperandMatchResultTy parseITCondCode(OperandVector &);
297 OperandMatchResultTy parseCoprocNumOperand(OperandVector &);
298 OperandMatchResultTy parseCoprocRegOperand(OperandVector &);
299 OperandMatchResultTy parseCoprocOptionOperand(OperandVector &);
300 OperandMatchResultTy parseMemBarrierOptOperand(OperandVector &);
301 OperandMatchResultTy parseInstSyncBarrierOptOperand(OperandVector &);
302 OperandMatchResultTy parseProcIFlagsOperand(OperandVector &);
303 OperandMatchResultTy parseMSRMaskOperand(OperandVector &);
304 OperandMatchResultTy parseBankedRegOperand(OperandVector &);
305 OperandMatchResultTy parsePKHImm(OperandVector &O, StringRef Op, int Low,
307 OperandMatchResultTy parsePKHLSLImm(OperandVector &O) {
308 return parsePKHImm(O, "lsl", 0, 31);
310 OperandMatchResultTy parsePKHASRImm(OperandVector &O) {
311 return parsePKHImm(O, "asr", 1, 32);
313 OperandMatchResultTy parseSetEndImm(OperandVector &);
314 OperandMatchResultTy parseShifterImm(OperandVector &);
315 OperandMatchResultTy parseRotImm(OperandVector &);
316 OperandMatchResultTy parseModImm(OperandVector &);
317 OperandMatchResultTy parseBitfield(OperandVector &);
318 OperandMatchResultTy parsePostIdxReg(OperandVector &);
319 OperandMatchResultTy parseAM3Offset(OperandVector &);
320 OperandMatchResultTy parseFPImm(OperandVector &);
321 OperandMatchResultTy parseVectorList(OperandVector &);
322 OperandMatchResultTy parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index,
325 // Asm Match Converter Methods
326 void cvtThumbMultiply(MCInst &Inst, const OperandVector &);
327 void cvtThumbBranches(MCInst &Inst, const OperandVector &);
329 bool validateInstruction(MCInst &Inst, const OperandVector &Ops);
330 bool processInstruction(MCInst &Inst, const OperandVector &Ops, MCStreamer &Out);
331 bool shouldOmitCCOutOperand(StringRef Mnemonic, OperandVector &Operands);
332 bool shouldOmitPredicateOperand(StringRef Mnemonic, OperandVector &Operands);
335 enum ARMMatchResultTy {
336 Match_RequiresITBlock = FIRST_TARGET_MATCH_RESULT_TY,
337 Match_RequiresNotITBlock,
339 Match_RequiresThumb2,
340 #define GET_OPERAND_DIAGNOSTIC_TYPES
341 #include "ARMGenAsmMatcher.inc"
345 ARMAsmParser(MCSubtargetInfo &STI, MCAsmParser &Parser,
346 const MCInstrInfo &MII, const MCTargetOptions &Options)
347 : STI(STI), MII(MII), UC(Parser) {
348 MCAsmParserExtension::Initialize(Parser);
350 // Cache the MCRegisterInfo.
351 MRI = getContext().getRegisterInfo();
353 // Initialize the set of available features.
354 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
356 // Not in an ITBlock to start with.
357 ITState.CurPosition = ~0U;
359 NextSymbolIsThumb = false;
362 // Implementation of the MCTargetAsmParser interface:
363 bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
364 bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
365 SMLoc NameLoc, OperandVector &Operands) override;
366 bool ParseDirective(AsmToken DirectiveID) override;
368 unsigned validateTargetOperandClass(MCParsedAsmOperand &Op,
369 unsigned Kind) override;
370 unsigned checkTargetMatchPredicate(MCInst &Inst) override;
372 bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
373 OperandVector &Operands, MCStreamer &Out,
375 bool MatchingInlineAsm) override;
376 void onLabelParsed(MCSymbol *Symbol) override;
378 } // end anonymous namespace
382 /// ARMOperand - Instances of this class represent a parsed ARM machine
384 class ARMOperand : public MCParsedAsmOperand {
394 k_InstSyncBarrierOpt,
406 k_VectorListAllLanes,
413 k_BitfieldDescriptor,
417 SMLoc StartLoc, EndLoc, AlignmentLoc;
418 SmallVector<unsigned, 8> Registers;
421 ARMCC::CondCodes Val;
428 struct CoprocOptionOp {
441 ARM_ISB::InstSyncBOpt Val;
445 ARM_PROC::IFlags Val;
465 // A vector register list is a sequential list of 1 to 4 registers.
466 struct VectorListOp {
473 struct VectorIndexOp {
481 /// Combined record for all forms of ARM address expressions.
484 // Offset is in OffsetReg or OffsetImm. If both are zero, no offset
486 const MCConstantExpr *OffsetImm; // Offset immediate value
487 unsigned OffsetRegNum; // Offset register num, when OffsetImm == NULL
488 ARM_AM::ShiftOpc ShiftType; // Shift type for OffsetReg
489 unsigned ShiftImm; // shift for OffsetReg.
490 unsigned Alignment; // 0 = no alignment specified
491 // n = alignment in bytes (2, 4, 8, 16, or 32)
492 unsigned isNegative : 1; // Negated OffsetReg? (~'U' bit)
495 struct PostIdxRegOp {
498 ARM_AM::ShiftOpc ShiftTy;
502 struct ShifterImmOp {
507 struct RegShiftedRegOp {
508 ARM_AM::ShiftOpc ShiftTy;
514 struct RegShiftedImmOp {
515 ARM_AM::ShiftOpc ShiftTy;
537 struct CoprocOptionOp CoprocOption;
538 struct MBOptOp MBOpt;
539 struct ISBOptOp ISBOpt;
540 struct ITMaskOp ITMask;
541 struct IFlagsOp IFlags;
542 struct MMaskOp MMask;
543 struct BankedRegOp BankedReg;
546 struct VectorListOp VectorList;
547 struct VectorIndexOp VectorIndex;
549 struct MemoryOp Memory;
550 struct PostIdxRegOp PostIdxReg;
551 struct ShifterImmOp ShifterImm;
552 struct RegShiftedRegOp RegShiftedReg;
553 struct RegShiftedImmOp RegShiftedImm;
554 struct RotImmOp RotImm;
555 struct ModImmOp ModImm;
556 struct BitfieldOp Bitfield;
560 ARMOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
561 ARMOperand(const ARMOperand &o) : MCParsedAsmOperand() {
563 StartLoc = o.StartLoc;
580 case k_DPRRegisterList:
581 case k_SPRRegisterList:
582 Registers = o.Registers;
585 case k_VectorListAllLanes:
586 case k_VectorListIndexed:
587 VectorList = o.VectorList;
594 CoprocOption = o.CoprocOption;
599 case k_MemBarrierOpt:
602 case k_InstSyncBarrierOpt:
607 case k_PostIndexRegister:
608 PostIdxReg = o.PostIdxReg;
614 BankedReg = o.BankedReg;
619 case k_ShifterImmediate:
620 ShifterImm = o.ShifterImm;
622 case k_ShiftedRegister:
623 RegShiftedReg = o.RegShiftedReg;
625 case k_ShiftedImmediate:
626 RegShiftedImm = o.RegShiftedImm;
628 case k_RotateImmediate:
631 case k_ModifiedImmediate:
634 case k_BitfieldDescriptor:
635 Bitfield = o.Bitfield;
638 VectorIndex = o.VectorIndex;
643 /// getStartLoc - Get the location of the first token of this operand.
644 SMLoc getStartLoc() const override { return StartLoc; }
645 /// getEndLoc - Get the location of the last token of this operand.
646 SMLoc getEndLoc() const override { return EndLoc; }
647 /// getLocRange - Get the range between the first and last token of this
649 SMRange getLocRange() const { return SMRange(StartLoc, EndLoc); }
651 /// getAlignmentLoc - Get the location of the Alignment token of this operand.
652 SMLoc getAlignmentLoc() const {
653 assert(Kind == k_Memory && "Invalid access!");
657 ARMCC::CondCodes getCondCode() const {
658 assert(Kind == k_CondCode && "Invalid access!");
662 unsigned getCoproc() const {
663 assert((Kind == k_CoprocNum || Kind == k_CoprocReg) && "Invalid access!");
667 StringRef getToken() const {
668 assert(Kind == k_Token && "Invalid access!");
669 return StringRef(Tok.Data, Tok.Length);
672 unsigned getReg() const override {
673 assert((Kind == k_Register || Kind == k_CCOut) && "Invalid access!");
677 const SmallVectorImpl<unsigned> &getRegList() const {
678 assert((Kind == k_RegisterList || Kind == k_DPRRegisterList ||
679 Kind == k_SPRRegisterList) && "Invalid access!");
683 const MCExpr *getImm() const {
684 assert(isImm() && "Invalid access!");
688 unsigned getVectorIndex() const {
689 assert(Kind == k_VectorIndex && "Invalid access!");
690 return VectorIndex.Val;
693 ARM_MB::MemBOpt getMemBarrierOpt() const {
694 assert(Kind == k_MemBarrierOpt && "Invalid access!");
698 ARM_ISB::InstSyncBOpt getInstSyncBarrierOpt() const {
699 assert(Kind == k_InstSyncBarrierOpt && "Invalid access!");
703 ARM_PROC::IFlags getProcIFlags() const {
704 assert(Kind == k_ProcIFlags && "Invalid access!");
708 unsigned getMSRMask() const {
709 assert(Kind == k_MSRMask && "Invalid access!");
713 unsigned getBankedReg() const {
714 assert(Kind == k_BankedReg && "Invalid access!");
715 return BankedReg.Val;
718 bool isCoprocNum() const { return Kind == k_CoprocNum; }
719 bool isCoprocReg() const { return Kind == k_CoprocReg; }
720 bool isCoprocOption() const { return Kind == k_CoprocOption; }
721 bool isCondCode() const { return Kind == k_CondCode; }
722 bool isCCOut() const { return Kind == k_CCOut; }
723 bool isITMask() const { return Kind == k_ITCondMask; }
724 bool isITCondCode() const { return Kind == k_CondCode; }
725 bool isImm() const override { return Kind == k_Immediate; }
726 // checks whether this operand is an unsigned offset which fits is a field
727 // of specified width and scaled by a specific number of bits
728 template<unsigned width, unsigned scale>
729 bool isUnsignedOffset() const {
730 if (!isImm()) return false;
731 if (isa<MCSymbolRefExpr>(Imm.Val)) return true;
732 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val)) {
733 int64_t Val = CE->getValue();
734 int64_t Align = 1LL << scale;
735 int64_t Max = Align * ((1LL << width) - 1);
736 return ((Val % Align) == 0) && (Val >= 0) && (Val <= Max);
740 // checks whether this operand is an signed offset which fits is a field
741 // of specified width and scaled by a specific number of bits
742 template<unsigned width, unsigned scale>
743 bool isSignedOffset() const {
744 if (!isImm()) return false;
745 if (isa<MCSymbolRefExpr>(Imm.Val)) return true;
746 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val)) {
747 int64_t Val = CE->getValue();
748 int64_t Align = 1LL << scale;
749 int64_t Max = Align * ((1LL << (width-1)) - 1);
750 int64_t Min = -Align * (1LL << (width-1));
751 return ((Val % Align) == 0) && (Val >= Min) && (Val <= Max);
756 // checks whether this operand is a memory operand computed as an offset
757 // applied to PC. the offset may have 8 bits of magnitude and is represented
758 // with two bits of shift. textually it may be either [pc, #imm], #imm or
759 // relocable expression...
760 bool isThumbMemPC() const {
763 if (isa<MCSymbolRefExpr>(Imm.Val)) return true;
764 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val);
765 if (!CE) return false;
766 Val = CE->getValue();
769 if(!Memory.OffsetImm || Memory.OffsetRegNum) return false;
770 if(Memory.BaseRegNum != ARM::PC) return false;
771 Val = Memory.OffsetImm->getValue();
774 return ((Val % 4) == 0) && (Val >= 0) && (Val <= 1020);
776 bool isFPImm() const {
777 if (!isImm()) return false;
778 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
779 if (!CE) return false;
780 int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue()));
783 bool isFBits16() const {
784 if (!isImm()) return false;
785 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
786 if (!CE) return false;
787 int64_t Value = CE->getValue();
788 return Value >= 0 && Value <= 16;
790 bool isFBits32() const {
791 if (!isImm()) return false;
792 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
793 if (!CE) return false;
794 int64_t Value = CE->getValue();
795 return Value >= 1 && Value <= 32;
797 bool isImm8s4() const {
798 if (!isImm()) return false;
799 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
800 if (!CE) return false;
801 int64_t Value = CE->getValue();
802 return ((Value & 3) == 0) && Value >= -1020 && Value <= 1020;
804 bool isImm0_1020s4() const {
805 if (!isImm()) return false;
806 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
807 if (!CE) return false;
808 int64_t Value = CE->getValue();
809 return ((Value & 3) == 0) && Value >= 0 && Value <= 1020;
811 bool isImm0_508s4() const {
812 if (!isImm()) return false;
813 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
814 if (!CE) return false;
815 int64_t Value = CE->getValue();
816 return ((Value & 3) == 0) && Value >= 0 && Value <= 508;
818 bool isImm0_508s4Neg() const {
819 if (!isImm()) return false;
820 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
821 if (!CE) return false;
822 int64_t Value = -CE->getValue();
823 // explicitly exclude zero. we want that to use the normal 0_508 version.
824 return ((Value & 3) == 0) && Value > 0 && Value <= 508;
826 bool isImm0_239() const {
827 if (!isImm()) return false;
828 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
829 if (!CE) return false;
830 int64_t Value = CE->getValue();
831 return Value >= 0 && Value < 240;
833 bool isImm0_255() const {
834 if (!isImm()) return false;
835 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
836 if (!CE) return false;
837 int64_t Value = CE->getValue();
838 return Value >= 0 && Value < 256;
840 bool isImm0_4095() const {
841 if (!isImm()) return false;
842 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
843 if (!CE) return false;
844 int64_t Value = CE->getValue();
845 return Value >= 0 && Value < 4096;
847 bool isImm0_4095Neg() const {
848 if (!isImm()) return false;
849 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
850 if (!CE) return false;
851 int64_t Value = -CE->getValue();
852 return Value > 0 && Value < 4096;
854 bool isImm0_1() const {
855 if (!isImm()) return false;
856 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
857 if (!CE) return false;
858 int64_t Value = CE->getValue();
859 return Value >= 0 && Value < 2;
861 bool isImm0_3() const {
862 if (!isImm()) return false;
863 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
864 if (!CE) return false;
865 int64_t Value = CE->getValue();
866 return Value >= 0 && Value < 4;
868 bool isImm0_7() const {
869 if (!isImm()) return false;
870 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
871 if (!CE) return false;
872 int64_t Value = CE->getValue();
873 return Value >= 0 && Value < 8;
875 bool isImm0_15() const {
876 if (!isImm()) return false;
877 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
878 if (!CE) return false;
879 int64_t Value = CE->getValue();
880 return Value >= 0 && Value < 16;
882 bool isImm0_31() const {
883 if (!isImm()) return false;
884 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
885 if (!CE) return false;
886 int64_t Value = CE->getValue();
887 return Value >= 0 && Value < 32;
889 bool isImm0_63() const {
890 if (!isImm()) return false;
891 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
892 if (!CE) return false;
893 int64_t Value = CE->getValue();
894 return Value >= 0 && Value < 64;
896 bool isImm8() const {
897 if (!isImm()) return false;
898 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
899 if (!CE) return false;
900 int64_t Value = CE->getValue();
903 bool isImm16() const {
904 if (!isImm()) return false;
905 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
906 if (!CE) return false;
907 int64_t Value = CE->getValue();
910 bool isImm32() const {
911 if (!isImm()) return false;
912 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
913 if (!CE) return false;
914 int64_t Value = CE->getValue();
917 bool isShrImm8() const {
918 if (!isImm()) return false;
919 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
920 if (!CE) return false;
921 int64_t Value = CE->getValue();
922 return Value > 0 && Value <= 8;
924 bool isShrImm16() const {
925 if (!isImm()) return false;
926 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
927 if (!CE) return false;
928 int64_t Value = CE->getValue();
929 return Value > 0 && Value <= 16;
931 bool isShrImm32() const {
932 if (!isImm()) return false;
933 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
934 if (!CE) return false;
935 int64_t Value = CE->getValue();
936 return Value > 0 && Value <= 32;
938 bool isShrImm64() const {
939 if (!isImm()) return false;
940 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
941 if (!CE) return false;
942 int64_t Value = CE->getValue();
943 return Value > 0 && Value <= 64;
945 bool isImm1_7() const {
946 if (!isImm()) return false;
947 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
948 if (!CE) return false;
949 int64_t Value = CE->getValue();
950 return Value > 0 && Value < 8;
952 bool isImm1_15() const {
953 if (!isImm()) return false;
954 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
955 if (!CE) return false;
956 int64_t Value = CE->getValue();
957 return Value > 0 && Value < 16;
959 bool isImm1_31() const {
960 if (!isImm()) return false;
961 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
962 if (!CE) return false;
963 int64_t Value = CE->getValue();
964 return Value > 0 && Value < 32;
966 bool isImm1_16() const {
967 if (!isImm()) return false;
968 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
969 if (!CE) return false;
970 int64_t Value = CE->getValue();
971 return Value > 0 && Value < 17;
973 bool isImm1_32() const {
974 if (!isImm()) return false;
975 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
976 if (!CE) return false;
977 int64_t Value = CE->getValue();
978 return Value > 0 && Value < 33;
980 bool isImm0_32() const {
981 if (!isImm()) return false;
982 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
983 if (!CE) return false;
984 int64_t Value = CE->getValue();
985 return Value >= 0 && Value < 33;
987 bool isImm0_65535() const {
988 if (!isImm()) return false;
989 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
990 if (!CE) return false;
991 int64_t Value = CE->getValue();
992 return Value >= 0 && Value < 65536;
994 bool isImm256_65535Expr() const {
995 if (!isImm()) return false;
996 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
997 // If it's not a constant expression, it'll generate a fixup and be
999 if (!CE) return true;
1000 int64_t Value = CE->getValue();
1001 return Value >= 256 && Value < 65536;
1003 bool isImm0_65535Expr() const {
1004 if (!isImm()) return false;
1005 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1006 // If it's not a constant expression, it'll generate a fixup and be
1008 if (!CE) return true;
1009 int64_t Value = CE->getValue();
1010 return Value >= 0 && Value < 65536;
1012 bool isImm24bit() const {
1013 if (!isImm()) return false;
1014 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1015 if (!CE) return false;
1016 int64_t Value = CE->getValue();
1017 return Value >= 0 && Value <= 0xffffff;
1019 bool isImmThumbSR() const {
1020 if (!isImm()) return false;
1021 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1022 if (!CE) return false;
1023 int64_t Value = CE->getValue();
1024 return Value > 0 && Value < 33;
1026 bool isPKHLSLImm() const {
1027 if (!isImm()) return false;
1028 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1029 if (!CE) return false;
1030 int64_t Value = CE->getValue();
1031 return Value >= 0 && Value < 32;
1033 bool isPKHASRImm() const {
1034 if (!isImm()) return false;
1035 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1036 if (!CE) return false;
1037 int64_t Value = CE->getValue();
1038 return Value > 0 && Value <= 32;
1040 bool isAdrLabel() const {
1041 // If we have an immediate that's not a constant, treat it as a label
1042 // reference needing a fixup.
1043 if (isImm() && !isa<MCConstantExpr>(getImm()))
1046 // If it is a constant, it must fit into a modified immediate encoding.
1047 if (!isImm()) return false;
1048 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1049 if (!CE) return false;
1050 int64_t Value = CE->getValue();
1051 return (ARM_AM::getSOImmVal(Value) != -1 ||
1052 ARM_AM::getSOImmVal(-Value) != -1);;
1054 bool isT2SOImm() const {
1055 if (!isImm()) return false;
1056 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1057 if (!CE) return false;
1058 int64_t Value = CE->getValue();
1059 return ARM_AM::getT2SOImmVal(Value) != -1;
1061 bool isT2SOImmNot() const {
1062 if (!isImm()) return false;
1063 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1064 if (!CE) return false;
1065 int64_t Value = CE->getValue();
1066 return ARM_AM::getT2SOImmVal(Value) == -1 &&
1067 ARM_AM::getT2SOImmVal(~Value) != -1;
1069 bool isT2SOImmNeg() const {
1070 if (!isImm()) return false;
1071 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1072 if (!CE) return false;
1073 int64_t Value = CE->getValue();
1074 // Only use this when not representable as a plain so_imm.
1075 return ARM_AM::getT2SOImmVal(Value) == -1 &&
1076 ARM_AM::getT2SOImmVal(-Value) != -1;
1078 bool isSetEndImm() const {
1079 if (!isImm()) return false;
1080 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1081 if (!CE) return false;
1082 int64_t Value = CE->getValue();
1083 return Value == 1 || Value == 0;
1085 bool isReg() const override { return Kind == k_Register; }
1086 bool isRegList() const { return Kind == k_RegisterList; }
1087 bool isDPRRegList() const { return Kind == k_DPRRegisterList; }
1088 bool isSPRRegList() const { return Kind == k_SPRRegisterList; }
1089 bool isToken() const override { return Kind == k_Token; }
1090 bool isMemBarrierOpt() const { return Kind == k_MemBarrierOpt; }
1091 bool isInstSyncBarrierOpt() const { return Kind == k_InstSyncBarrierOpt; }
1092 bool isMem() const override { return Kind == k_Memory; }
1093 bool isShifterImm() const { return Kind == k_ShifterImmediate; }
1094 bool isRegShiftedReg() const { return Kind == k_ShiftedRegister; }
1095 bool isRegShiftedImm() const { return Kind == k_ShiftedImmediate; }
1096 bool isRotImm() const { return Kind == k_RotateImmediate; }
1097 bool isModImm() const { return Kind == k_ModifiedImmediate; }
1098 bool isModImmNot() const {
1099 if (!isImm()) return false;
1100 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1101 if (!CE) return false;
1102 int64_t Value = CE->getValue();
1103 return ARM_AM::getSOImmVal(~Value) != -1;
1105 bool isModImmNeg() const {
1106 if (!isImm()) return false;
1107 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1108 if (!CE) return false;
1109 int64_t Value = CE->getValue();
1110 return ARM_AM::getSOImmVal(Value) == -1 &&
1111 ARM_AM::getSOImmVal(-Value) != -1;
1113 bool isBitfield() const { return Kind == k_BitfieldDescriptor; }
1114 bool isPostIdxRegShifted() const { return Kind == k_PostIndexRegister; }
1115 bool isPostIdxReg() const {
1116 return Kind == k_PostIndexRegister && PostIdxReg.ShiftTy ==ARM_AM::no_shift;
1118 bool isMemNoOffset(bool alignOK = false, unsigned Alignment = 0) const {
1121 // No offset of any kind.
1122 return Memory.OffsetRegNum == 0 && Memory.OffsetImm == nullptr &&
1123 (alignOK || Memory.Alignment == Alignment);
1125 bool isMemPCRelImm12() const {
1126 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1128 // Base register must be PC.
1129 if (Memory.BaseRegNum != ARM::PC)
1131 // Immediate offset in range [-4095, 4095].
1132 if (!Memory.OffsetImm) return true;
1133 int64_t Val = Memory.OffsetImm->getValue();
1134 return (Val > -4096 && Val < 4096) || (Val == INT32_MIN);
1136 bool isAlignedMemory() const {
1137 return isMemNoOffset(true);
1139 bool isAlignedMemoryNone() const {
1140 return isMemNoOffset(false, 0);
1142 bool isDupAlignedMemoryNone() const {
1143 return isMemNoOffset(false, 0);
1145 bool isAlignedMemory16() const {
1146 if (isMemNoOffset(false, 2)) // alignment in bytes for 16-bits is 2.
1148 return isMemNoOffset(false, 0);
1150 bool isDupAlignedMemory16() const {
1151 if (isMemNoOffset(false, 2)) // alignment in bytes for 16-bits is 2.
1153 return isMemNoOffset(false, 0);
1155 bool isAlignedMemory32() const {
1156 if (isMemNoOffset(false, 4)) // alignment in bytes for 32-bits is 4.
1158 return isMemNoOffset(false, 0);
1160 bool isDupAlignedMemory32() const {
1161 if (isMemNoOffset(false, 4)) // alignment in bytes for 32-bits is 4.
1163 return isMemNoOffset(false, 0);
1165 bool isAlignedMemory64() const {
1166 if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8.
1168 return isMemNoOffset(false, 0);
1170 bool isDupAlignedMemory64() const {
1171 if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8.
1173 return isMemNoOffset(false, 0);
1175 bool isAlignedMemory64or128() const {
1176 if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8.
1178 if (isMemNoOffset(false, 16)) // alignment in bytes for 128-bits is 16.
1180 return isMemNoOffset(false, 0);
1182 bool isDupAlignedMemory64or128() const {
1183 if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8.
1185 if (isMemNoOffset(false, 16)) // alignment in bytes for 128-bits is 16.
1187 return isMemNoOffset(false, 0);
1189 bool isAlignedMemory64or128or256() const {
1190 if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8.
1192 if (isMemNoOffset(false, 16)) // alignment in bytes for 128-bits is 16.
1194 if (isMemNoOffset(false, 32)) // alignment in bytes for 256-bits is 32.
1196 return isMemNoOffset(false, 0);
1198 bool isAddrMode2() const {
1199 if (!isMem() || Memory.Alignment != 0) return false;
1200 // Check for register offset.
1201 if (Memory.OffsetRegNum) return true;
1202 // Immediate offset in range [-4095, 4095].
1203 if (!Memory.OffsetImm) return true;
1204 int64_t Val = Memory.OffsetImm->getValue();
1205 return Val > -4096 && Val < 4096;
1207 bool isAM2OffsetImm() const {
1208 if (!isImm()) return false;
1209 // Immediate offset in range [-4095, 4095].
1210 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1211 if (!CE) return false;
1212 int64_t Val = CE->getValue();
1213 return (Val == INT32_MIN) || (Val > -4096 && Val < 4096);
1215 bool isAddrMode3() const {
1216 // If we have an immediate that's not a constant, treat it as a label
1217 // reference needing a fixup. If it is a constant, it's something else
1218 // and we reject it.
1219 if (isImm() && !isa<MCConstantExpr>(getImm()))
1221 if (!isMem() || Memory.Alignment != 0) return false;
1222 // No shifts are legal for AM3.
1223 if (Memory.ShiftType != ARM_AM::no_shift) return false;
1224 // Check for register offset.
1225 if (Memory.OffsetRegNum) return true;
1226 // Immediate offset in range [-255, 255].
1227 if (!Memory.OffsetImm) return true;
1228 int64_t Val = Memory.OffsetImm->getValue();
1229 // The #-0 offset is encoded as INT32_MIN, and we have to check
1231 return (Val > -256 && Val < 256) || Val == INT32_MIN;
1233 bool isAM3Offset() const {
1234 if (Kind != k_Immediate && Kind != k_PostIndexRegister)
1236 if (Kind == k_PostIndexRegister)
1237 return PostIdxReg.ShiftTy == ARM_AM::no_shift;
1238 // Immediate offset in range [-255, 255].
1239 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1240 if (!CE) return false;
1241 int64_t Val = CE->getValue();
1242 // Special case, #-0 is INT32_MIN.
1243 return (Val > -256 && Val < 256) || Val == INT32_MIN;
1245 bool isAddrMode5() const {
1246 // If we have an immediate that's not a constant, treat it as a label
1247 // reference needing a fixup. If it is a constant, it's something else
1248 // and we reject it.
1249 if (isImm() && !isa<MCConstantExpr>(getImm()))
1251 if (!isMem() || Memory.Alignment != 0) return false;
1252 // Check for register offset.
1253 if (Memory.OffsetRegNum) return false;
1254 // Immediate offset in range [-1020, 1020] and a multiple of 4.
1255 if (!Memory.OffsetImm) return true;
1256 int64_t Val = Memory.OffsetImm->getValue();
1257 return (Val >= -1020 && Val <= 1020 && ((Val & 3) == 0)) ||
1260 bool isMemTBB() const {
1261 if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1262 Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0)
1266 bool isMemTBH() const {
1267 if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1268 Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm != 1 ||
1269 Memory.Alignment != 0 )
1273 bool isMemRegOffset() const {
1274 if (!isMem() || !Memory.OffsetRegNum || Memory.Alignment != 0)
1278 bool isT2MemRegOffset() const {
1279 if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1280 Memory.Alignment != 0)
1282 // Only lsl #{0, 1, 2, 3} allowed.
1283 if (Memory.ShiftType == ARM_AM::no_shift)
1285 if (Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm > 3)
1289 bool isMemThumbRR() const {
1290 // Thumb reg+reg addressing is simple. Just two registers, a base and
1291 // an offset. No shifts, negations or any other complicating factors.
1292 if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1293 Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0)
1295 return isARMLowRegister(Memory.BaseRegNum) &&
1296 (!Memory.OffsetRegNum || isARMLowRegister(Memory.OffsetRegNum));
1298 bool isMemThumbRIs4() const {
1299 if (!isMem() || Memory.OffsetRegNum != 0 ||
1300 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
1302 // Immediate offset, multiple of 4 in range [0, 124].
1303 if (!Memory.OffsetImm) return true;
1304 int64_t Val = Memory.OffsetImm->getValue();
1305 return Val >= 0 && Val <= 124 && (Val % 4) == 0;
1307 bool isMemThumbRIs2() const {
1308 if (!isMem() || Memory.OffsetRegNum != 0 ||
1309 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
1311 // Immediate offset, multiple of 4 in range [0, 62].
1312 if (!Memory.OffsetImm) return true;
1313 int64_t Val = Memory.OffsetImm->getValue();
1314 return Val >= 0 && Val <= 62 && (Val % 2) == 0;
1316 bool isMemThumbRIs1() const {
1317 if (!isMem() || Memory.OffsetRegNum != 0 ||
1318 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
1320 // Immediate offset in range [0, 31].
1321 if (!Memory.OffsetImm) return true;
1322 int64_t Val = Memory.OffsetImm->getValue();
1323 return Val >= 0 && Val <= 31;
1325 bool isMemThumbSPI() const {
1326 if (!isMem() || Memory.OffsetRegNum != 0 ||
1327 Memory.BaseRegNum != ARM::SP || Memory.Alignment != 0)
1329 // Immediate offset, multiple of 4 in range [0, 1020].
1330 if (!Memory.OffsetImm) return true;
1331 int64_t Val = Memory.OffsetImm->getValue();
1332 return Val >= 0 && Val <= 1020 && (Val % 4) == 0;
1334 bool isMemImm8s4Offset() const {
1335 // If we have an immediate that's not a constant, treat it as a label
1336 // reference needing a fixup. If it is a constant, it's something else
1337 // and we reject it.
1338 if (isImm() && !isa<MCConstantExpr>(getImm()))
1340 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1342 // Immediate offset a multiple of 4 in range [-1020, 1020].
1343 if (!Memory.OffsetImm) return true;
1344 int64_t Val = Memory.OffsetImm->getValue();
1345 // Special case, #-0 is INT32_MIN.
1346 return (Val >= -1020 && Val <= 1020 && (Val & 3) == 0) || Val == INT32_MIN;
1348 bool isMemImm0_1020s4Offset() const {
1349 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1351 // Immediate offset a multiple of 4 in range [0, 1020].
1352 if (!Memory.OffsetImm) return true;
1353 int64_t Val = Memory.OffsetImm->getValue();
1354 return Val >= 0 && Val <= 1020 && (Val & 3) == 0;
1356 bool isMemImm8Offset() const {
1357 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1359 // Base reg of PC isn't allowed for these encodings.
1360 if (Memory.BaseRegNum == ARM::PC) return false;
1361 // Immediate offset in range [-255, 255].
1362 if (!Memory.OffsetImm) return true;
1363 int64_t Val = Memory.OffsetImm->getValue();
1364 return (Val == INT32_MIN) || (Val > -256 && Val < 256);
1366 bool isMemPosImm8Offset() const {
1367 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1369 // Immediate offset in range [0, 255].
1370 if (!Memory.OffsetImm) return true;
1371 int64_t Val = Memory.OffsetImm->getValue();
1372 return Val >= 0 && Val < 256;
1374 bool isMemNegImm8Offset() const {
1375 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1377 // Base reg of PC isn't allowed for these encodings.
1378 if (Memory.BaseRegNum == ARM::PC) return false;
1379 // Immediate offset in range [-255, -1].
1380 if (!Memory.OffsetImm) return false;
1381 int64_t Val = Memory.OffsetImm->getValue();
1382 return (Val == INT32_MIN) || (Val > -256 && Val < 0);
1384 bool isMemUImm12Offset() const {
1385 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1387 // Immediate offset in range [0, 4095].
1388 if (!Memory.OffsetImm) return true;
1389 int64_t Val = Memory.OffsetImm->getValue();
1390 return (Val >= 0 && Val < 4096);
1392 bool isMemImm12Offset() const {
1393 // If we have an immediate that's not a constant, treat it as a label
1394 // reference needing a fixup. If it is a constant, it's something else
1395 // and we reject it.
1396 if (isImm() && !isa<MCConstantExpr>(getImm()))
1399 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1401 // Immediate offset in range [-4095, 4095].
1402 if (!Memory.OffsetImm) return true;
1403 int64_t Val = Memory.OffsetImm->getValue();
1404 return (Val > -4096 && Val < 4096) || (Val == INT32_MIN);
1406 bool isPostIdxImm8() const {
1407 if (!isImm()) return false;
1408 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1409 if (!CE) return false;
1410 int64_t Val = CE->getValue();
1411 return (Val > -256 && Val < 256) || (Val == INT32_MIN);
1413 bool isPostIdxImm8s4() const {
1414 if (!isImm()) return false;
1415 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1416 if (!CE) return false;
1417 int64_t Val = CE->getValue();
1418 return ((Val & 3) == 0 && Val >= -1020 && Val <= 1020) ||
1422 bool isMSRMask() const { return Kind == k_MSRMask; }
1423 bool isBankedReg() const { return Kind == k_BankedReg; }
1424 bool isProcIFlags() const { return Kind == k_ProcIFlags; }
1427 bool isSingleSpacedVectorList() const {
1428 return Kind == k_VectorList && !VectorList.isDoubleSpaced;
1430 bool isDoubleSpacedVectorList() const {
1431 return Kind == k_VectorList && VectorList.isDoubleSpaced;
1433 bool isVecListOneD() const {
1434 if (!isSingleSpacedVectorList()) return false;
1435 return VectorList.Count == 1;
1438 bool isVecListDPair() const {
1439 if (!isSingleSpacedVectorList()) return false;
1440 return (ARMMCRegisterClasses[ARM::DPairRegClassID]
1441 .contains(VectorList.RegNum));
1444 bool isVecListThreeD() const {
1445 if (!isSingleSpacedVectorList()) return false;
1446 return VectorList.Count == 3;
1449 bool isVecListFourD() const {
1450 if (!isSingleSpacedVectorList()) return false;
1451 return VectorList.Count == 4;
1454 bool isVecListDPairSpaced() const {
1455 if (Kind != k_VectorList) return false;
1456 if (isSingleSpacedVectorList()) return false;
1457 return (ARMMCRegisterClasses[ARM::DPairSpcRegClassID]
1458 .contains(VectorList.RegNum));
1461 bool isVecListThreeQ() const {
1462 if (!isDoubleSpacedVectorList()) return false;
1463 return VectorList.Count == 3;
1466 bool isVecListFourQ() const {
1467 if (!isDoubleSpacedVectorList()) return false;
1468 return VectorList.Count == 4;
1471 bool isSingleSpacedVectorAllLanes() const {
1472 return Kind == k_VectorListAllLanes && !VectorList.isDoubleSpaced;
1474 bool isDoubleSpacedVectorAllLanes() const {
1475 return Kind == k_VectorListAllLanes && VectorList.isDoubleSpaced;
1477 bool isVecListOneDAllLanes() const {
1478 if (!isSingleSpacedVectorAllLanes()) return false;
1479 return VectorList.Count == 1;
1482 bool isVecListDPairAllLanes() const {
1483 if (!isSingleSpacedVectorAllLanes()) return false;
1484 return (ARMMCRegisterClasses[ARM::DPairRegClassID]
1485 .contains(VectorList.RegNum));
1488 bool isVecListDPairSpacedAllLanes() const {
1489 if (!isDoubleSpacedVectorAllLanes()) return false;
1490 return VectorList.Count == 2;
1493 bool isVecListThreeDAllLanes() const {
1494 if (!isSingleSpacedVectorAllLanes()) return false;
1495 return VectorList.Count == 3;
1498 bool isVecListThreeQAllLanes() const {
1499 if (!isDoubleSpacedVectorAllLanes()) return false;
1500 return VectorList.Count == 3;
1503 bool isVecListFourDAllLanes() const {
1504 if (!isSingleSpacedVectorAllLanes()) return false;
1505 return VectorList.Count == 4;
1508 bool isVecListFourQAllLanes() const {
1509 if (!isDoubleSpacedVectorAllLanes()) return false;
1510 return VectorList.Count == 4;
1513 bool isSingleSpacedVectorIndexed() const {
1514 return Kind == k_VectorListIndexed && !VectorList.isDoubleSpaced;
1516 bool isDoubleSpacedVectorIndexed() const {
1517 return Kind == k_VectorListIndexed && VectorList.isDoubleSpaced;
1519 bool isVecListOneDByteIndexed() const {
1520 if (!isSingleSpacedVectorIndexed()) return false;
1521 return VectorList.Count == 1 && VectorList.LaneIndex <= 7;
1524 bool isVecListOneDHWordIndexed() const {
1525 if (!isSingleSpacedVectorIndexed()) return false;
1526 return VectorList.Count == 1 && VectorList.LaneIndex <= 3;
1529 bool isVecListOneDWordIndexed() const {
1530 if (!isSingleSpacedVectorIndexed()) return false;
1531 return VectorList.Count == 1 && VectorList.LaneIndex <= 1;
1534 bool isVecListTwoDByteIndexed() const {
1535 if (!isSingleSpacedVectorIndexed()) return false;
1536 return VectorList.Count == 2 && VectorList.LaneIndex <= 7;
1539 bool isVecListTwoDHWordIndexed() const {
1540 if (!isSingleSpacedVectorIndexed()) return false;
1541 return VectorList.Count == 2 && VectorList.LaneIndex <= 3;
1544 bool isVecListTwoQWordIndexed() const {
1545 if (!isDoubleSpacedVectorIndexed()) return false;
1546 return VectorList.Count == 2 && VectorList.LaneIndex <= 1;
1549 bool isVecListTwoQHWordIndexed() const {
1550 if (!isDoubleSpacedVectorIndexed()) return false;
1551 return VectorList.Count == 2 && VectorList.LaneIndex <= 3;
1554 bool isVecListTwoDWordIndexed() const {
1555 if (!isSingleSpacedVectorIndexed()) return false;
1556 return VectorList.Count == 2 && VectorList.LaneIndex <= 1;
1559 bool isVecListThreeDByteIndexed() const {
1560 if (!isSingleSpacedVectorIndexed()) return false;
1561 return VectorList.Count == 3 && VectorList.LaneIndex <= 7;
1564 bool isVecListThreeDHWordIndexed() const {
1565 if (!isSingleSpacedVectorIndexed()) return false;
1566 return VectorList.Count == 3 && VectorList.LaneIndex <= 3;
1569 bool isVecListThreeQWordIndexed() const {
1570 if (!isDoubleSpacedVectorIndexed()) return false;
1571 return VectorList.Count == 3 && VectorList.LaneIndex <= 1;
1574 bool isVecListThreeQHWordIndexed() const {
1575 if (!isDoubleSpacedVectorIndexed()) return false;
1576 return VectorList.Count == 3 && VectorList.LaneIndex <= 3;
1579 bool isVecListThreeDWordIndexed() const {
1580 if (!isSingleSpacedVectorIndexed()) return false;
1581 return VectorList.Count == 3 && VectorList.LaneIndex <= 1;
1584 bool isVecListFourDByteIndexed() const {
1585 if (!isSingleSpacedVectorIndexed()) return false;
1586 return VectorList.Count == 4 && VectorList.LaneIndex <= 7;
1589 bool isVecListFourDHWordIndexed() const {
1590 if (!isSingleSpacedVectorIndexed()) return false;
1591 return VectorList.Count == 4 && VectorList.LaneIndex <= 3;
1594 bool isVecListFourQWordIndexed() const {
1595 if (!isDoubleSpacedVectorIndexed()) return false;
1596 return VectorList.Count == 4 && VectorList.LaneIndex <= 1;
1599 bool isVecListFourQHWordIndexed() const {
1600 if (!isDoubleSpacedVectorIndexed()) return false;
1601 return VectorList.Count == 4 && VectorList.LaneIndex <= 3;
1604 bool isVecListFourDWordIndexed() const {
1605 if (!isSingleSpacedVectorIndexed()) return false;
1606 return VectorList.Count == 4 && VectorList.LaneIndex <= 1;
1609 bool isVectorIndex8() const {
1610 if (Kind != k_VectorIndex) return false;
1611 return VectorIndex.Val < 8;
1613 bool isVectorIndex16() const {
1614 if (Kind != k_VectorIndex) return false;
1615 return VectorIndex.Val < 4;
1617 bool isVectorIndex32() const {
1618 if (Kind != k_VectorIndex) return false;
1619 return VectorIndex.Val < 2;
1622 bool isNEONi8splat() const {
1623 if (!isImm()) return false;
1624 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1625 // Must be a constant.
1626 if (!CE) return false;
1627 int64_t Value = CE->getValue();
1628 // i8 value splatted across 8 bytes. The immediate is just the 8 byte
1630 return Value >= 0 && Value < 256;
1633 bool isNEONi16splat() const {
1634 if (isNEONByteReplicate(2))
1635 return false; // Leave that for bytes replication and forbid by default.
1638 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1639 // Must be a constant.
1640 if (!CE) return false;
1641 unsigned Value = CE->getValue();
1642 return ARM_AM::isNEONi16splat(Value);
1645 bool isNEONi16splatNot() const {
1648 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1649 // Must be a constant.
1650 if (!CE) return false;
1651 unsigned Value = CE->getValue();
1652 return ARM_AM::isNEONi16splat(~Value & 0xffff);
1655 bool isNEONi32splat() const {
1656 if (isNEONByteReplicate(4))
1657 return false; // Leave that for bytes replication and forbid by default.
1660 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1661 // Must be a constant.
1662 if (!CE) return false;
1663 unsigned Value = CE->getValue();
1664 return ARM_AM::isNEONi32splat(Value);
1667 bool isNEONi32splatNot() const {
1670 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1671 // Must be a constant.
1672 if (!CE) return false;
1673 unsigned Value = CE->getValue();
1674 return ARM_AM::isNEONi32splat(~Value);
1677 bool isNEONByteReplicate(unsigned NumBytes) const {
1680 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1681 // Must be a constant.
1684 int64_t Value = CE->getValue();
1686 return false; // Don't bother with zero.
1688 unsigned char B = Value & 0xff;
1689 for (unsigned i = 1; i < NumBytes; ++i) {
1691 if ((Value & 0xff) != B)
1696 bool isNEONi16ByteReplicate() const { return isNEONByteReplicate(2); }
1697 bool isNEONi32ByteReplicate() const { return isNEONByteReplicate(4); }
1698 bool isNEONi32vmov() const {
1699 if (isNEONByteReplicate(4))
1700 return false; // Let it to be classified as byte-replicate case.
1703 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1704 // Must be a constant.
1707 int64_t Value = CE->getValue();
1708 // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X,
1709 // for VMOV/VMVN only, 00Xf or 0Xff are also accepted.
1710 // FIXME: This is probably wrong and a copy and paste from previous example
1711 return (Value >= 0 && Value < 256) ||
1712 (Value >= 0x0100 && Value <= 0xff00) ||
1713 (Value >= 0x010000 && Value <= 0xff0000) ||
1714 (Value >= 0x01000000 && Value <= 0xff000000) ||
1715 (Value >= 0x01ff && Value <= 0xffff && (Value & 0xff) == 0xff) ||
1716 (Value >= 0x01ffff && Value <= 0xffffff && (Value & 0xffff) == 0xffff);
1718 bool isNEONi32vmovNeg() const {
1719 if (!isImm()) return false;
1720 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1721 // Must be a constant.
1722 if (!CE) return false;
1723 int64_t Value = ~CE->getValue();
1724 // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X,
1725 // for VMOV/VMVN only, 00Xf or 0Xff are also accepted.
1726 // FIXME: This is probably wrong and a copy and paste from previous example
1727 return (Value >= 0 && Value < 256) ||
1728 (Value >= 0x0100 && Value <= 0xff00) ||
1729 (Value >= 0x010000 && Value <= 0xff0000) ||
1730 (Value >= 0x01000000 && Value <= 0xff000000) ||
1731 (Value >= 0x01ff && Value <= 0xffff && (Value & 0xff) == 0xff) ||
1732 (Value >= 0x01ffff && Value <= 0xffffff && (Value & 0xffff) == 0xffff);
1735 bool isNEONi64splat() const {
1736 if (!isImm()) return false;
1737 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1738 // Must be a constant.
1739 if (!CE) return false;
1740 uint64_t Value = CE->getValue();
1741 // i64 value with each byte being either 0 or 0xff.
1742 for (unsigned i = 0; i < 8; ++i)
1743 if ((Value & 0xff) != 0 && (Value & 0xff) != 0xff) return false;
1747 void addExpr(MCInst &Inst, const MCExpr *Expr) const {
1748 // Add as immediates when possible. Null MCExpr = 0.
1750 Inst.addOperand(MCOperand::CreateImm(0));
1751 else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
1752 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
1754 Inst.addOperand(MCOperand::CreateExpr(Expr));
1757 void addCondCodeOperands(MCInst &Inst, unsigned N) const {
1758 assert(N == 2 && "Invalid number of operands!");
1759 Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
1760 unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR;
1761 Inst.addOperand(MCOperand::CreateReg(RegNum));
1764 void addCoprocNumOperands(MCInst &Inst, unsigned N) const {
1765 assert(N == 1 && "Invalid number of operands!");
1766 Inst.addOperand(MCOperand::CreateImm(getCoproc()));
1769 void addCoprocRegOperands(MCInst &Inst, unsigned N) const {
1770 assert(N == 1 && "Invalid number of operands!");
1771 Inst.addOperand(MCOperand::CreateImm(getCoproc()));
1774 void addCoprocOptionOperands(MCInst &Inst, unsigned N) const {
1775 assert(N == 1 && "Invalid number of operands!");
1776 Inst.addOperand(MCOperand::CreateImm(CoprocOption.Val));
1779 void addITMaskOperands(MCInst &Inst, unsigned N) const {
1780 assert(N == 1 && "Invalid number of operands!");
1781 Inst.addOperand(MCOperand::CreateImm(ITMask.Mask));
1784 void addITCondCodeOperands(MCInst &Inst, unsigned N) const {
1785 assert(N == 1 && "Invalid number of operands!");
1786 Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
1789 void addCCOutOperands(MCInst &Inst, unsigned N) const {
1790 assert(N == 1 && "Invalid number of operands!");
1791 Inst.addOperand(MCOperand::CreateReg(getReg()));
1794 void addRegOperands(MCInst &Inst, unsigned N) const {
1795 assert(N == 1 && "Invalid number of operands!");
1796 Inst.addOperand(MCOperand::CreateReg(getReg()));
1799 void addRegShiftedRegOperands(MCInst &Inst, unsigned N) const {
1800 assert(N == 3 && "Invalid number of operands!");
1801 assert(isRegShiftedReg() &&
1802 "addRegShiftedRegOperands() on non-RegShiftedReg!");
1803 Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.SrcReg));
1804 Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.ShiftReg));
1805 Inst.addOperand(MCOperand::CreateImm(
1806 ARM_AM::getSORegOpc(RegShiftedReg.ShiftTy, RegShiftedReg.ShiftImm)));
1809 void addRegShiftedImmOperands(MCInst &Inst, unsigned N) const {
1810 assert(N == 2 && "Invalid number of operands!");
1811 assert(isRegShiftedImm() &&
1812 "addRegShiftedImmOperands() on non-RegShiftedImm!");
1813 Inst.addOperand(MCOperand::CreateReg(RegShiftedImm.SrcReg));
1814 // Shift of #32 is encoded as 0 where permitted
1815 unsigned Imm = (RegShiftedImm.ShiftImm == 32 ? 0 : RegShiftedImm.ShiftImm);
1816 Inst.addOperand(MCOperand::CreateImm(
1817 ARM_AM::getSORegOpc(RegShiftedImm.ShiftTy, Imm)));
1820 void addShifterImmOperands(MCInst &Inst, unsigned N) const {
1821 assert(N == 1 && "Invalid number of operands!");
1822 Inst.addOperand(MCOperand::CreateImm((ShifterImm.isASR << 5) |
1826 void addRegListOperands(MCInst &Inst, unsigned N) const {
1827 assert(N == 1 && "Invalid number of operands!");
1828 const SmallVectorImpl<unsigned> &RegList = getRegList();
1829 for (SmallVectorImpl<unsigned>::const_iterator
1830 I = RegList.begin(), E = RegList.end(); I != E; ++I)
1831 Inst.addOperand(MCOperand::CreateReg(*I));
1834 void addDPRRegListOperands(MCInst &Inst, unsigned N) const {
1835 addRegListOperands(Inst, N);
1838 void addSPRRegListOperands(MCInst &Inst, unsigned N) const {
1839 addRegListOperands(Inst, N);
1842 void addRotImmOperands(MCInst &Inst, unsigned N) const {
1843 assert(N == 1 && "Invalid number of operands!");
1844 // Encoded as val>>3. The printer handles display as 8, 16, 24.
1845 Inst.addOperand(MCOperand::CreateImm(RotImm.Imm >> 3));
1848 void addModImmOperands(MCInst &Inst, unsigned N) const {
1849 assert(N == 1 && "Invalid number of operands!");
1851 // Support for fixups (MCFixup)
1853 return addImmOperands(Inst, N);
1855 Inst.addOperand(MCOperand::CreateImm(ModImm.Bits | (ModImm.Rot << 7)));
1858 void addModImmNotOperands(MCInst &Inst, unsigned N) const {
1859 assert(N == 1 && "Invalid number of operands!");
1860 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1861 uint32_t Enc = ARM_AM::getSOImmVal(~CE->getValue());
1862 Inst.addOperand(MCOperand::CreateImm(Enc));
1865 void addModImmNegOperands(MCInst &Inst, unsigned N) const {
1866 assert(N == 1 && "Invalid number of operands!");
1867 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1868 uint32_t Enc = ARM_AM::getSOImmVal(-CE->getValue());
1869 Inst.addOperand(MCOperand::CreateImm(Enc));
1872 void addBitfieldOperands(MCInst &Inst, unsigned N) const {
1873 assert(N == 1 && "Invalid number of operands!");
1874 // Munge the lsb/width into a bitfield mask.
1875 unsigned lsb = Bitfield.LSB;
1876 unsigned width = Bitfield.Width;
1877 // Make a 32-bit mask w/ the referenced bits clear and all other bits set.
1878 uint32_t Mask = ~(((uint32_t)0xffffffff >> lsb) << (32 - width) >>
1879 (32 - (lsb + width)));
1880 Inst.addOperand(MCOperand::CreateImm(Mask));
1883 void addImmOperands(MCInst &Inst, unsigned N) const {
1884 assert(N == 1 && "Invalid number of operands!");
1885 addExpr(Inst, getImm());
1888 void addFBits16Operands(MCInst &Inst, unsigned N) const {
1889 assert(N == 1 && "Invalid number of operands!");
1890 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1891 Inst.addOperand(MCOperand::CreateImm(16 - CE->getValue()));
1894 void addFBits32Operands(MCInst &Inst, unsigned N) const {
1895 assert(N == 1 && "Invalid number of operands!");
1896 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1897 Inst.addOperand(MCOperand::CreateImm(32 - CE->getValue()));
1900 void addFPImmOperands(MCInst &Inst, unsigned N) const {
1901 assert(N == 1 && "Invalid number of operands!");
1902 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1903 int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue()));
1904 Inst.addOperand(MCOperand::CreateImm(Val));
1907 void addImm8s4Operands(MCInst &Inst, unsigned N) const {
1908 assert(N == 1 && "Invalid number of operands!");
1909 // FIXME: We really want to scale the value here, but the LDRD/STRD
1910 // instruction don't encode operands that way yet.
1911 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1912 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
1915 void addImm0_1020s4Operands(MCInst &Inst, unsigned N) const {
1916 assert(N == 1 && "Invalid number of operands!");
1917 // The immediate is scaled by four in the encoding and is stored
1918 // in the MCInst as such. Lop off the low two bits here.
1919 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1920 Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4));
1923 void addImm0_508s4NegOperands(MCInst &Inst, unsigned N) const {
1924 assert(N == 1 && "Invalid number of operands!");
1925 // The immediate is scaled by four in the encoding and is stored
1926 // in the MCInst as such. Lop off the low two bits here.
1927 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1928 Inst.addOperand(MCOperand::CreateImm(-(CE->getValue() / 4)));
1931 void addImm0_508s4Operands(MCInst &Inst, unsigned N) const {
1932 assert(N == 1 && "Invalid number of operands!");
1933 // The immediate is scaled by four in the encoding and is stored
1934 // in the MCInst as such. Lop off the low two bits here.
1935 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1936 Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4));
1939 void addImm1_16Operands(MCInst &Inst, unsigned N) const {
1940 assert(N == 1 && "Invalid number of operands!");
1941 // The constant encodes as the immediate-1, and we store in the instruction
1942 // the bits as encoded, so subtract off one here.
1943 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1944 Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
1947 void addImm1_32Operands(MCInst &Inst, unsigned N) const {
1948 assert(N == 1 && "Invalid number of operands!");
1949 // The constant encodes as the immediate-1, and we store in the instruction
1950 // the bits as encoded, so subtract off one here.
1951 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1952 Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
1955 void addImmThumbSROperands(MCInst &Inst, unsigned N) const {
1956 assert(N == 1 && "Invalid number of operands!");
1957 // The constant encodes as the immediate, except for 32, which encodes as
1959 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1960 unsigned Imm = CE->getValue();
1961 Inst.addOperand(MCOperand::CreateImm((Imm == 32 ? 0 : Imm)));
1964 void addPKHASRImmOperands(MCInst &Inst, unsigned N) const {
1965 assert(N == 1 && "Invalid number of operands!");
1966 // An ASR value of 32 encodes as 0, so that's how we want to add it to
1967 // the instruction as well.
1968 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1969 int Val = CE->getValue();
1970 Inst.addOperand(MCOperand::CreateImm(Val == 32 ? 0 : Val));
1973 void addT2SOImmNotOperands(MCInst &Inst, unsigned N) const {
1974 assert(N == 1 && "Invalid number of operands!");
1975 // The operand is actually a t2_so_imm, but we have its bitwise
1976 // negation in the assembly source, so twiddle it here.
1977 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1978 Inst.addOperand(MCOperand::CreateImm(~CE->getValue()));
1981 void addT2SOImmNegOperands(MCInst &Inst, unsigned N) const {
1982 assert(N == 1 && "Invalid number of operands!");
1983 // The operand is actually a t2_so_imm, but we have its
1984 // negation in the assembly source, so twiddle it here.
1985 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1986 Inst.addOperand(MCOperand::CreateImm(-CE->getValue()));
1989 void addImm0_4095NegOperands(MCInst &Inst, unsigned N) const {
1990 assert(N == 1 && "Invalid number of operands!");
1991 // The operand is actually an imm0_4095, but we have its
1992 // negation in the assembly source, so twiddle it here.
1993 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1994 Inst.addOperand(MCOperand::CreateImm(-CE->getValue()));
1997 void addUnsignedOffset_b8s2Operands(MCInst &Inst, unsigned N) const {
1998 if(const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm())) {
1999 Inst.addOperand(MCOperand::CreateImm(CE->getValue() >> 2));
2003 const MCSymbolRefExpr *SR = dyn_cast<MCSymbolRefExpr>(Imm.Val);
2004 assert(SR && "Unknown value type!");
2005 Inst.addOperand(MCOperand::CreateExpr(SR));
2008 void addThumbMemPCOperands(MCInst &Inst, unsigned N) const {
2009 assert(N == 1 && "Invalid number of operands!");
2011 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2013 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
2017 const MCSymbolRefExpr *SR = dyn_cast<MCSymbolRefExpr>(Imm.Val);
2018 assert(SR && "Unknown value type!");
2019 Inst.addOperand(MCOperand::CreateExpr(SR));
2023 assert(isMem() && "Unknown value type!");
2024 assert(isa<MCConstantExpr>(Memory.OffsetImm) && "Unknown value type!");
2025 Inst.addOperand(MCOperand::CreateImm(Memory.OffsetImm->getValue()));
2028 void addMemBarrierOptOperands(MCInst &Inst, unsigned N) const {
2029 assert(N == 1 && "Invalid number of operands!");
2030 Inst.addOperand(MCOperand::CreateImm(unsigned(getMemBarrierOpt())));
2033 void addInstSyncBarrierOptOperands(MCInst &Inst, unsigned N) const {
2034 assert(N == 1 && "Invalid number of operands!");
2035 Inst.addOperand(MCOperand::CreateImm(unsigned(getInstSyncBarrierOpt())));
2038 void addMemNoOffsetOperands(MCInst &Inst, unsigned N) const {
2039 assert(N == 1 && "Invalid number of operands!");
2040 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2043 void addMemPCRelImm12Operands(MCInst &Inst, unsigned N) const {
2044 assert(N == 1 && "Invalid number of operands!");
2045 int32_t Imm = Memory.OffsetImm->getValue();
2046 Inst.addOperand(MCOperand::CreateImm(Imm));
2049 void addAdrLabelOperands(MCInst &Inst, unsigned N) const {
2050 assert(N == 1 && "Invalid number of operands!");
2051 assert(isImm() && "Not an immediate!");
2053 // If we have an immediate that's not a constant, treat it as a label
2054 // reference needing a fixup.
2055 if (!isa<MCConstantExpr>(getImm())) {
2056 Inst.addOperand(MCOperand::CreateExpr(getImm()));
2060 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2061 int Val = CE->getValue();
2062 Inst.addOperand(MCOperand::CreateImm(Val));
2065 void addAlignedMemoryOperands(MCInst &Inst, unsigned N) const {
2066 assert(N == 2 && "Invalid number of operands!");
2067 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2068 Inst.addOperand(MCOperand::CreateImm(Memory.Alignment));
2071 void addDupAlignedMemoryNoneOperands(MCInst &Inst, unsigned N) const {
2072 addAlignedMemoryOperands(Inst, N);
2075 void addAlignedMemoryNoneOperands(MCInst &Inst, unsigned N) const {
2076 addAlignedMemoryOperands(Inst, N);
2079 void addAlignedMemory16Operands(MCInst &Inst, unsigned N) const {
2080 addAlignedMemoryOperands(Inst, N);
2083 void addDupAlignedMemory16Operands(MCInst &Inst, unsigned N) const {
2084 addAlignedMemoryOperands(Inst, N);
2087 void addAlignedMemory32Operands(MCInst &Inst, unsigned N) const {
2088 addAlignedMemoryOperands(Inst, N);
2091 void addDupAlignedMemory32Operands(MCInst &Inst, unsigned N) const {
2092 addAlignedMemoryOperands(Inst, N);
2095 void addAlignedMemory64Operands(MCInst &Inst, unsigned N) const {
2096 addAlignedMemoryOperands(Inst, N);
2099 void addDupAlignedMemory64Operands(MCInst &Inst, unsigned N) const {
2100 addAlignedMemoryOperands(Inst, N);
2103 void addAlignedMemory64or128Operands(MCInst &Inst, unsigned N) const {
2104 addAlignedMemoryOperands(Inst, N);
2107 void addDupAlignedMemory64or128Operands(MCInst &Inst, unsigned N) const {
2108 addAlignedMemoryOperands(Inst, N);
2111 void addAlignedMemory64or128or256Operands(MCInst &Inst, unsigned N) const {
2112 addAlignedMemoryOperands(Inst, N);
2115 void addAddrMode2Operands(MCInst &Inst, unsigned N) const {
2116 assert(N == 3 && "Invalid number of operands!");
2117 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2118 if (!Memory.OffsetRegNum) {
2119 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
2120 // Special case for #-0
2121 if (Val == INT32_MIN) Val = 0;
2122 if (Val < 0) Val = -Val;
2123 Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
2125 // For register offset, we encode the shift type and negation flag
2127 Val = ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add,
2128 Memory.ShiftImm, Memory.ShiftType);
2130 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2131 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
2132 Inst.addOperand(MCOperand::CreateImm(Val));
2135 void addAM2OffsetImmOperands(MCInst &Inst, unsigned N) const {
2136 assert(N == 2 && "Invalid number of operands!");
2137 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2138 assert(CE && "non-constant AM2OffsetImm operand!");
2139 int32_t Val = CE->getValue();
2140 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
2141 // Special case for #-0
2142 if (Val == INT32_MIN) Val = 0;
2143 if (Val < 0) Val = -Val;
2144 Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
2145 Inst.addOperand(MCOperand::CreateReg(0));
2146 Inst.addOperand(MCOperand::CreateImm(Val));
2149 void addAddrMode3Operands(MCInst &Inst, unsigned N) const {
2150 assert(N == 3 && "Invalid number of operands!");
2151 // If we have an immediate that's not a constant, treat it as a label
2152 // reference needing a fixup. If it is a constant, it's something else
2153 // and we reject it.
2155 Inst.addOperand(MCOperand::CreateExpr(getImm()));
2156 Inst.addOperand(MCOperand::CreateReg(0));
2157 Inst.addOperand(MCOperand::CreateImm(0));
2161 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2162 if (!Memory.OffsetRegNum) {
2163 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
2164 // Special case for #-0
2165 if (Val == INT32_MIN) Val = 0;
2166 if (Val < 0) Val = -Val;
2167 Val = ARM_AM::getAM3Opc(AddSub, Val);
2169 // For register offset, we encode the shift type and negation flag
2171 Val = ARM_AM::getAM3Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add, 0);
2173 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2174 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
2175 Inst.addOperand(MCOperand::CreateImm(Val));
2178 void addAM3OffsetOperands(MCInst &Inst, unsigned N) const {
2179 assert(N == 2 && "Invalid number of operands!");
2180 if (Kind == k_PostIndexRegister) {
2182 ARM_AM::getAM3Opc(PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub, 0);
2183 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
2184 Inst.addOperand(MCOperand::CreateImm(Val));
2189 const MCConstantExpr *CE = static_cast<const MCConstantExpr*>(getImm());
2190 int32_t Val = CE->getValue();
2191 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
2192 // Special case for #-0
2193 if (Val == INT32_MIN) Val = 0;
2194 if (Val < 0) Val = -Val;
2195 Val = ARM_AM::getAM3Opc(AddSub, Val);
2196 Inst.addOperand(MCOperand::CreateReg(0));
2197 Inst.addOperand(MCOperand::CreateImm(Val));
2200 void addAddrMode5Operands(MCInst &Inst, unsigned N) const {
2201 assert(N == 2 && "Invalid number of operands!");
2202 // If we have an immediate that's not a constant, treat it as a label
2203 // reference needing a fixup. If it is a constant, it's something else
2204 // and we reject it.
2206 Inst.addOperand(MCOperand::CreateExpr(getImm()));
2207 Inst.addOperand(MCOperand::CreateImm(0));
2211 // The lower two bits are always zero and as such are not encoded.
2212 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0;
2213 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
2214 // Special case for #-0
2215 if (Val == INT32_MIN) Val = 0;
2216 if (Val < 0) Val = -Val;
2217 Val = ARM_AM::getAM5Opc(AddSub, Val);
2218 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2219 Inst.addOperand(MCOperand::CreateImm(Val));
2222 void addMemImm8s4OffsetOperands(MCInst &Inst, unsigned N) const {
2223 assert(N == 2 && "Invalid number of operands!");
2224 // If we have an immediate that's not a constant, treat it as a label
2225 // reference needing a fixup. If it is a constant, it's something else
2226 // and we reject it.
2228 Inst.addOperand(MCOperand::CreateExpr(getImm()));
2229 Inst.addOperand(MCOperand::CreateImm(0));
2233 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2234 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2235 Inst.addOperand(MCOperand::CreateImm(Val));
2238 void addMemImm0_1020s4OffsetOperands(MCInst &Inst, unsigned N) const {
2239 assert(N == 2 && "Invalid number of operands!");
2240 // The lower two bits are always zero and as such are not encoded.
2241 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0;
2242 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2243 Inst.addOperand(MCOperand::CreateImm(Val));
2246 void addMemImm8OffsetOperands(MCInst &Inst, unsigned N) const {
2247 assert(N == 2 && "Invalid number of operands!");
2248 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2249 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2250 Inst.addOperand(MCOperand::CreateImm(Val));
2253 void addMemPosImm8OffsetOperands(MCInst &Inst, unsigned N) const {
2254 addMemImm8OffsetOperands(Inst, N);
2257 void addMemNegImm8OffsetOperands(MCInst &Inst, unsigned N) const {
2258 addMemImm8OffsetOperands(Inst, N);
2261 void addMemUImm12OffsetOperands(MCInst &Inst, unsigned N) const {
2262 assert(N == 2 && "Invalid number of operands!");
2263 // If this is an immediate, it's a label reference.
2265 addExpr(Inst, getImm());
2266 Inst.addOperand(MCOperand::CreateImm(0));
2270 // Otherwise, it's a normal memory reg+offset.
2271 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2272 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2273 Inst.addOperand(MCOperand::CreateImm(Val));
2276 void addMemImm12OffsetOperands(MCInst &Inst, unsigned N) const {
2277 assert(N == 2 && "Invalid number of operands!");
2278 // If this is an immediate, it's a label reference.
2280 addExpr(Inst, getImm());
2281 Inst.addOperand(MCOperand::CreateImm(0));
2285 // Otherwise, it's a normal memory reg+offset.
2286 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2287 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2288 Inst.addOperand(MCOperand::CreateImm(Val));
2291 void addMemTBBOperands(MCInst &Inst, unsigned N) const {
2292 assert(N == 2 && "Invalid number of operands!");
2293 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2294 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
2297 void addMemTBHOperands(MCInst &Inst, unsigned N) const {
2298 assert(N == 2 && "Invalid number of operands!");
2299 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2300 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
2303 void addMemRegOffsetOperands(MCInst &Inst, unsigned N) const {
2304 assert(N == 3 && "Invalid number of operands!");
2306 ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add,
2307 Memory.ShiftImm, Memory.ShiftType);
2308 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2309 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
2310 Inst.addOperand(MCOperand::CreateImm(Val));
2313 void addT2MemRegOffsetOperands(MCInst &Inst, unsigned N) const {
2314 assert(N == 3 && "Invalid number of operands!");
2315 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2316 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
2317 Inst.addOperand(MCOperand::CreateImm(Memory.ShiftImm));
2320 void addMemThumbRROperands(MCInst &Inst, unsigned N) const {
2321 assert(N == 2 && "Invalid number of operands!");
2322 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2323 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
2326 void addMemThumbRIs4Operands(MCInst &Inst, unsigned N) const {
2327 assert(N == 2 && "Invalid number of operands!");
2328 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0;
2329 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2330 Inst.addOperand(MCOperand::CreateImm(Val));
2333 void addMemThumbRIs2Operands(MCInst &Inst, unsigned N) const {
2334 assert(N == 2 && "Invalid number of operands!");
2335 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 2) : 0;
2336 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2337 Inst.addOperand(MCOperand::CreateImm(Val));
2340 void addMemThumbRIs1Operands(MCInst &Inst, unsigned N) const {
2341 assert(N == 2 && "Invalid number of operands!");
2342 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue()) : 0;
2343 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2344 Inst.addOperand(MCOperand::CreateImm(Val));
2347 void addMemThumbSPIOperands(MCInst &Inst, unsigned N) const {
2348 assert(N == 2 && "Invalid number of operands!");
2349 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0;
2350 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2351 Inst.addOperand(MCOperand::CreateImm(Val));
2354 void addPostIdxImm8Operands(MCInst &Inst, unsigned N) const {
2355 assert(N == 1 && "Invalid number of operands!");
2356 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2357 assert(CE && "non-constant post-idx-imm8 operand!");
2358 int Imm = CE->getValue();
2359 bool isAdd = Imm >= 0;
2360 if (Imm == INT32_MIN) Imm = 0;
2361 Imm = (Imm < 0 ? -Imm : Imm) | (int)isAdd << 8;
2362 Inst.addOperand(MCOperand::CreateImm(Imm));
2365 void addPostIdxImm8s4Operands(MCInst &Inst, unsigned N) const {
2366 assert(N == 1 && "Invalid number of operands!");
2367 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2368 assert(CE && "non-constant post-idx-imm8s4 operand!");
2369 int Imm = CE->getValue();
2370 bool isAdd = Imm >= 0;
2371 if (Imm == INT32_MIN) Imm = 0;
2372 // Immediate is scaled by 4.
2373 Imm = ((Imm < 0 ? -Imm : Imm) / 4) | (int)isAdd << 8;
2374 Inst.addOperand(MCOperand::CreateImm(Imm));
2377 void addPostIdxRegOperands(MCInst &Inst, unsigned N) const {
2378 assert(N == 2 && "Invalid number of operands!");
2379 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
2380 Inst.addOperand(MCOperand::CreateImm(PostIdxReg.isAdd));
2383 void addPostIdxRegShiftedOperands(MCInst &Inst, unsigned N) const {
2384 assert(N == 2 && "Invalid number of operands!");
2385 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
2386 // The sign, shift type, and shift amount are encoded in a single operand
2387 // using the AM2 encoding helpers.
2388 ARM_AM::AddrOpc opc = PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub;
2389 unsigned Imm = ARM_AM::getAM2Opc(opc, PostIdxReg.ShiftImm,
2390 PostIdxReg.ShiftTy);
2391 Inst.addOperand(MCOperand::CreateImm(Imm));
2394 void addMSRMaskOperands(MCInst &Inst, unsigned N) const {
2395 assert(N == 1 && "Invalid number of operands!");
2396 Inst.addOperand(MCOperand::CreateImm(unsigned(getMSRMask())));
2399 void addBankedRegOperands(MCInst &Inst, unsigned N) const {
2400 assert(N == 1 && "Invalid number of operands!");
2401 Inst.addOperand(MCOperand::CreateImm(unsigned(getBankedReg())));
2404 void addProcIFlagsOperands(MCInst &Inst, unsigned N) const {
2405 assert(N == 1 && "Invalid number of operands!");
2406 Inst.addOperand(MCOperand::CreateImm(unsigned(getProcIFlags())));
2409 void addVecListOperands(MCInst &Inst, unsigned N) const {
2410 assert(N == 1 && "Invalid number of operands!");
2411 Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum));
2414 void addVecListIndexedOperands(MCInst &Inst, unsigned N) const {
2415 assert(N == 2 && "Invalid number of operands!");
2416 Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum));
2417 Inst.addOperand(MCOperand::CreateImm(VectorList.LaneIndex));
2420 void addVectorIndex8Operands(MCInst &Inst, unsigned N) const {
2421 assert(N == 1 && "Invalid number of operands!");
2422 Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
2425 void addVectorIndex16Operands(MCInst &Inst, unsigned N) const {
2426 assert(N == 1 && "Invalid number of operands!");
2427 Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
2430 void addVectorIndex32Operands(MCInst &Inst, unsigned N) const {
2431 assert(N == 1 && "Invalid number of operands!");
2432 Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
2435 void addNEONi8splatOperands(MCInst &Inst, unsigned N) const {
2436 assert(N == 1 && "Invalid number of operands!");
2437 // The immediate encodes the type of constant as well as the value.
2438 // Mask in that this is an i8 splat.
2439 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2440 Inst.addOperand(MCOperand::CreateImm(CE->getValue() | 0xe00));
2443 void addNEONi16splatOperands(MCInst &Inst, unsigned N) const {
2444 assert(N == 1 && "Invalid number of operands!");
2445 // The immediate encodes the type of constant as well as the value.
2446 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2447 unsigned Value = CE->getValue();
2448 Value = ARM_AM::encodeNEONi16splat(Value);
2449 Inst.addOperand(MCOperand::CreateImm(Value));
2452 void addNEONi16splatNotOperands(MCInst &Inst, unsigned N) const {
2453 assert(N == 1 && "Invalid number of operands!");
2454 // The immediate encodes the type of constant as well as the value.
2455 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2456 unsigned Value = CE->getValue();
2457 Value = ARM_AM::encodeNEONi16splat(~Value & 0xffff);
2458 Inst.addOperand(MCOperand::CreateImm(Value));
2461 void addNEONi32splatOperands(MCInst &Inst, unsigned N) const {
2462 assert(N == 1 && "Invalid number of operands!");
2463 // The immediate encodes the type of constant as well as the value.
2464 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2465 unsigned Value = CE->getValue();
2466 Value = ARM_AM::encodeNEONi32splat(Value);
2467 Inst.addOperand(MCOperand::CreateImm(Value));
2470 void addNEONi32splatNotOperands(MCInst &Inst, unsigned N) const {
2471 assert(N == 1 && "Invalid number of operands!");
2472 // The immediate encodes the type of constant as well as the value.
2473 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2474 unsigned Value = CE->getValue();
2475 Value = ARM_AM::encodeNEONi32splat(~Value);
2476 Inst.addOperand(MCOperand::CreateImm(Value));
2479 void addNEONinvByteReplicateOperands(MCInst &Inst, unsigned N) const {
2480 assert(N == 1 && "Invalid number of operands!");
2481 // The immediate encodes the type of constant as well as the value.
2482 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2483 unsigned Value = CE->getValue();
2484 assert((Inst.getOpcode() == ARM::VMOVv8i8 ||
2485 Inst.getOpcode() == ARM::VMOVv16i8) &&
2486 "All vmvn instructions that wants to replicate non-zero byte "
2487 "always must be replaced with VMOVv8i8 or VMOVv16i8.");
2488 unsigned B = ((~Value) & 0xff);
2489 B |= 0xe00; // cmode = 0b1110
2490 Inst.addOperand(MCOperand::CreateImm(B));
2492 void addNEONi32vmovOperands(MCInst &Inst, unsigned N) const {
2493 assert(N == 1 && "Invalid number of operands!");
2494 // The immediate encodes the type of constant as well as the value.
2495 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2496 unsigned Value = CE->getValue();
2497 if (Value >= 256 && Value <= 0xffff)
2498 Value = (Value >> 8) | ((Value & 0xff) ? 0xc00 : 0x200);
2499 else if (Value > 0xffff && Value <= 0xffffff)
2500 Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400);
2501 else if (Value > 0xffffff)
2502 Value = (Value >> 24) | 0x600;
2503 Inst.addOperand(MCOperand::CreateImm(Value));
2506 void addNEONvmovByteReplicateOperands(MCInst &Inst, unsigned N) const {
2507 assert(N == 1 && "Invalid number of operands!");
2508 // The immediate encodes the type of constant as well as the value.
2509 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2510 unsigned Value = CE->getValue();
2511 assert((Inst.getOpcode() == ARM::VMOVv8i8 ||
2512 Inst.getOpcode() == ARM::VMOVv16i8) &&
2513 "All instructions that wants to replicate non-zero byte "
2514 "always must be replaced with VMOVv8i8 or VMOVv16i8.");
2515 unsigned B = Value & 0xff;
2516 B |= 0xe00; // cmode = 0b1110
2517 Inst.addOperand(MCOperand::CreateImm(B));
2519 void addNEONi32vmovNegOperands(MCInst &Inst, unsigned N) const {
2520 assert(N == 1 && "Invalid number of operands!");
2521 // The immediate encodes the type of constant as well as the value.
2522 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2523 unsigned Value = ~CE->getValue();
2524 if (Value >= 256 && Value <= 0xffff)
2525 Value = (Value >> 8) | ((Value & 0xff) ? 0xc00 : 0x200);
2526 else if (Value > 0xffff && Value <= 0xffffff)
2527 Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400);
2528 else if (Value > 0xffffff)
2529 Value = (Value >> 24) | 0x600;
2530 Inst.addOperand(MCOperand::CreateImm(Value));
2533 void addNEONi64splatOperands(MCInst &Inst, unsigned N) const {
2534 assert(N == 1 && "Invalid number of operands!");
2535 // The immediate encodes the type of constant as well as the value.
2536 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2537 uint64_t Value = CE->getValue();
2539 for (unsigned i = 0; i < 8; ++i, Value >>= 8) {
2540 Imm |= (Value & 1) << i;
2542 Inst.addOperand(MCOperand::CreateImm(Imm | 0x1e00));
2545 void print(raw_ostream &OS) const override;
2547 static std::unique_ptr<ARMOperand> CreateITMask(unsigned Mask, SMLoc S) {
2548 auto Op = make_unique<ARMOperand>(k_ITCondMask);
2549 Op->ITMask.Mask = Mask;
2555 static std::unique_ptr<ARMOperand> CreateCondCode(ARMCC::CondCodes CC,
2557 auto Op = make_unique<ARMOperand>(k_CondCode);
2564 static std::unique_ptr<ARMOperand> CreateCoprocNum(unsigned CopVal, SMLoc S) {
2565 auto Op = make_unique<ARMOperand>(k_CoprocNum);
2566 Op->Cop.Val = CopVal;
2572 static std::unique_ptr<ARMOperand> CreateCoprocReg(unsigned CopVal, SMLoc S) {
2573 auto Op = make_unique<ARMOperand>(k_CoprocReg);
2574 Op->Cop.Val = CopVal;
2580 static std::unique_ptr<ARMOperand> CreateCoprocOption(unsigned Val, SMLoc S,
2582 auto Op = make_unique<ARMOperand>(k_CoprocOption);
2589 static std::unique_ptr<ARMOperand> CreateCCOut(unsigned RegNum, SMLoc S) {
2590 auto Op = make_unique<ARMOperand>(k_CCOut);
2591 Op->Reg.RegNum = RegNum;
2597 static std::unique_ptr<ARMOperand> CreateToken(StringRef Str, SMLoc S) {
2598 auto Op = make_unique<ARMOperand>(k_Token);
2599 Op->Tok.Data = Str.data();
2600 Op->Tok.Length = Str.size();
2606 static std::unique_ptr<ARMOperand> CreateReg(unsigned RegNum, SMLoc S,
2608 auto Op = make_unique<ARMOperand>(k_Register);
2609 Op->Reg.RegNum = RegNum;
2615 static std::unique_ptr<ARMOperand>
2616 CreateShiftedRegister(ARM_AM::ShiftOpc ShTy, unsigned SrcReg,
2617 unsigned ShiftReg, unsigned ShiftImm, SMLoc S,
2619 auto Op = make_unique<ARMOperand>(k_ShiftedRegister);
2620 Op->RegShiftedReg.ShiftTy = ShTy;
2621 Op->RegShiftedReg.SrcReg = SrcReg;
2622 Op->RegShiftedReg.ShiftReg = ShiftReg;
2623 Op->RegShiftedReg.ShiftImm = ShiftImm;
2629 static std::unique_ptr<ARMOperand>
2630 CreateShiftedImmediate(ARM_AM::ShiftOpc ShTy, unsigned SrcReg,
2631 unsigned ShiftImm, SMLoc S, SMLoc E) {
2632 auto Op = make_unique<ARMOperand>(k_ShiftedImmediate);
2633 Op->RegShiftedImm.ShiftTy = ShTy;
2634 Op->RegShiftedImm.SrcReg = SrcReg;
2635 Op->RegShiftedImm.ShiftImm = ShiftImm;
2641 static std::unique_ptr<ARMOperand> CreateShifterImm(bool isASR, unsigned Imm,
2643 auto Op = make_unique<ARMOperand>(k_ShifterImmediate);
2644 Op->ShifterImm.isASR = isASR;
2645 Op->ShifterImm.Imm = Imm;
2651 static std::unique_ptr<ARMOperand> CreateRotImm(unsigned Imm, SMLoc S,
2653 auto Op = make_unique<ARMOperand>(k_RotateImmediate);
2654 Op->RotImm.Imm = Imm;
2660 static std::unique_ptr<ARMOperand> CreateModImm(unsigned Bits, unsigned Rot,
2662 auto Op = make_unique<ARMOperand>(k_ModifiedImmediate);
2663 Op->ModImm.Bits = Bits;
2664 Op->ModImm.Rot = Rot;
2670 static std::unique_ptr<ARMOperand>
2671 CreateBitfield(unsigned LSB, unsigned Width, SMLoc S, SMLoc E) {
2672 auto Op = make_unique<ARMOperand>(k_BitfieldDescriptor);
2673 Op->Bitfield.LSB = LSB;
2674 Op->Bitfield.Width = Width;
2680 static std::unique_ptr<ARMOperand>
2681 CreateRegList(SmallVectorImpl<std::pair<unsigned, unsigned>> &Regs,
2682 SMLoc StartLoc, SMLoc EndLoc) {
2683 assert (Regs.size() > 0 && "RegList contains no registers?");
2684 KindTy Kind = k_RegisterList;
2686 if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Regs.front().second))
2687 Kind = k_DPRRegisterList;
2688 else if (ARMMCRegisterClasses[ARM::SPRRegClassID].
2689 contains(Regs.front().second))
2690 Kind = k_SPRRegisterList;
2692 // Sort based on the register encoding values.
2693 array_pod_sort(Regs.begin(), Regs.end());
2695 auto Op = make_unique<ARMOperand>(Kind);
2696 for (SmallVectorImpl<std::pair<unsigned, unsigned> >::const_iterator
2697 I = Regs.begin(), E = Regs.end(); I != E; ++I)
2698 Op->Registers.push_back(I->second);
2699 Op->StartLoc = StartLoc;
2700 Op->EndLoc = EndLoc;
2704 static std::unique_ptr<ARMOperand> CreateVectorList(unsigned RegNum,
2706 bool isDoubleSpaced,
2708 auto Op = make_unique<ARMOperand>(k_VectorList);
2709 Op->VectorList.RegNum = RegNum;
2710 Op->VectorList.Count = Count;
2711 Op->VectorList.isDoubleSpaced = isDoubleSpaced;
2717 static std::unique_ptr<ARMOperand>
2718 CreateVectorListAllLanes(unsigned RegNum, unsigned Count, bool isDoubleSpaced,
2720 auto Op = make_unique<ARMOperand>(k_VectorListAllLanes);
2721 Op->VectorList.RegNum = RegNum;
2722 Op->VectorList.Count = Count;
2723 Op->VectorList.isDoubleSpaced = isDoubleSpaced;
2729 static std::unique_ptr<ARMOperand>
2730 CreateVectorListIndexed(unsigned RegNum, unsigned Count, unsigned Index,
2731 bool isDoubleSpaced, SMLoc S, SMLoc E) {
2732 auto Op = make_unique<ARMOperand>(k_VectorListIndexed);
2733 Op->VectorList.RegNum = RegNum;
2734 Op->VectorList.Count = Count;
2735 Op->VectorList.LaneIndex = Index;
2736 Op->VectorList.isDoubleSpaced = isDoubleSpaced;
2742 static std::unique_ptr<ARMOperand>
2743 CreateVectorIndex(unsigned Idx, SMLoc S, SMLoc E, MCContext &Ctx) {
2744 auto Op = make_unique<ARMOperand>(k_VectorIndex);
2745 Op->VectorIndex.Val = Idx;
2751 static std::unique_ptr<ARMOperand> CreateImm(const MCExpr *Val, SMLoc S,
2753 auto Op = make_unique<ARMOperand>(k_Immediate);
2760 static std::unique_ptr<ARMOperand>
2761 CreateMem(unsigned BaseRegNum, const MCConstantExpr *OffsetImm,
2762 unsigned OffsetRegNum, ARM_AM::ShiftOpc ShiftType,
2763 unsigned ShiftImm, unsigned Alignment, bool isNegative, SMLoc S,
2764 SMLoc E, SMLoc AlignmentLoc = SMLoc()) {
2765 auto Op = make_unique<ARMOperand>(k_Memory);
2766 Op->Memory.BaseRegNum = BaseRegNum;
2767 Op->Memory.OffsetImm = OffsetImm;
2768 Op->Memory.OffsetRegNum = OffsetRegNum;
2769 Op->Memory.ShiftType = ShiftType;
2770 Op->Memory.ShiftImm = ShiftImm;
2771 Op->Memory.Alignment = Alignment;
2772 Op->Memory.isNegative = isNegative;
2775 Op->AlignmentLoc = AlignmentLoc;
2779 static std::unique_ptr<ARMOperand>
2780 CreatePostIdxReg(unsigned RegNum, bool isAdd, ARM_AM::ShiftOpc ShiftTy,
2781 unsigned ShiftImm, SMLoc S, SMLoc E) {
2782 auto Op = make_unique<ARMOperand>(k_PostIndexRegister);
2783 Op->PostIdxReg.RegNum = RegNum;
2784 Op->PostIdxReg.isAdd = isAdd;
2785 Op->PostIdxReg.ShiftTy = ShiftTy;
2786 Op->PostIdxReg.ShiftImm = ShiftImm;
2792 static std::unique_ptr<ARMOperand> CreateMemBarrierOpt(ARM_MB::MemBOpt Opt,
2794 auto Op = make_unique<ARMOperand>(k_MemBarrierOpt);
2795 Op->MBOpt.Val = Opt;
2801 static std::unique_ptr<ARMOperand>
2802 CreateInstSyncBarrierOpt(ARM_ISB::InstSyncBOpt Opt, SMLoc S) {
2803 auto Op = make_unique<ARMOperand>(k_InstSyncBarrierOpt);
2804 Op->ISBOpt.Val = Opt;
2810 static std::unique_ptr<ARMOperand> CreateProcIFlags(ARM_PROC::IFlags IFlags,
2812 auto Op = make_unique<ARMOperand>(k_ProcIFlags);
2813 Op->IFlags.Val = IFlags;
2819 static std::unique_ptr<ARMOperand> CreateMSRMask(unsigned MMask, SMLoc S) {
2820 auto Op = make_unique<ARMOperand>(k_MSRMask);
2821 Op->MMask.Val = MMask;
2827 static std::unique_ptr<ARMOperand> CreateBankedReg(unsigned Reg, SMLoc S) {
2828 auto Op = make_unique<ARMOperand>(k_BankedReg);
2829 Op->BankedReg.Val = Reg;
2836 } // end anonymous namespace.
2838 void ARMOperand::print(raw_ostream &OS) const {
2841 OS << "<ARMCC::" << ARMCondCodeToString(getCondCode()) << ">";
2844 OS << "<ccout " << getReg() << ">";
2846 case k_ITCondMask: {
2847 static const char *const MaskStr[] = {
2848 "()", "(t)", "(e)", "(tt)", "(et)", "(te)", "(ee)", "(ttt)", "(ett)",
2849 "(tet)", "(eet)", "(tte)", "(ete)", "(tee)", "(eee)"
2851 assert((ITMask.Mask & 0xf) == ITMask.Mask);
2852 OS << "<it-mask " << MaskStr[ITMask.Mask] << ">";
2856 OS << "<coprocessor number: " << getCoproc() << ">";
2859 OS << "<coprocessor register: " << getCoproc() << ">";
2861 case k_CoprocOption:
2862 OS << "<coprocessor option: " << CoprocOption.Val << ">";
2865 OS << "<mask: " << getMSRMask() << ">";
2868 OS << "<banked reg: " << getBankedReg() << ">";
2871 getImm()->print(OS);
2873 case k_MemBarrierOpt:
2874 OS << "<ARM_MB::" << MemBOptToString(getMemBarrierOpt(), false) << ">";
2876 case k_InstSyncBarrierOpt:
2877 OS << "<ARM_ISB::" << InstSyncBOptToString(getInstSyncBarrierOpt()) << ">";
2881 << " base:" << Memory.BaseRegNum;
2884 case k_PostIndexRegister:
2885 OS << "post-idx register " << (PostIdxReg.isAdd ? "" : "-")
2886 << PostIdxReg.RegNum;
2887 if (PostIdxReg.ShiftTy != ARM_AM::no_shift)
2888 OS << ARM_AM::getShiftOpcStr(PostIdxReg.ShiftTy) << " "
2889 << PostIdxReg.ShiftImm;
2892 case k_ProcIFlags: {
2893 OS << "<ARM_PROC::";
2894 unsigned IFlags = getProcIFlags();
2895 for (int i=2; i >= 0; --i)
2896 if (IFlags & (1 << i))
2897 OS << ARM_PROC::IFlagsToString(1 << i);
2902 OS << "<register " << getReg() << ">";
2904 case k_ShifterImmediate:
2905 OS << "<shift " << (ShifterImm.isASR ? "asr" : "lsl")
2906 << " #" << ShifterImm.Imm << ">";
2908 case k_ShiftedRegister:
2909 OS << "<so_reg_reg "
2910 << RegShiftedReg.SrcReg << " "
2911 << ARM_AM::getShiftOpcStr(RegShiftedReg.ShiftTy)
2912 << " " << RegShiftedReg.ShiftReg << ">";
2914 case k_ShiftedImmediate:
2915 OS << "<so_reg_imm "
2916 << RegShiftedImm.SrcReg << " "
2917 << ARM_AM::getShiftOpcStr(RegShiftedImm.ShiftTy)
2918 << " #" << RegShiftedImm.ShiftImm << ">";
2920 case k_RotateImmediate:
2921 OS << "<ror " << " #" << (RotImm.Imm * 8) << ">";
2923 case k_ModifiedImmediate:
2924 OS << "<mod_imm #" << ModImm.Bits << ", #"
2925 << ModImm.Rot << ")>";
2927 case k_BitfieldDescriptor:
2928 OS << "<bitfield " << "lsb: " << Bitfield.LSB
2929 << ", width: " << Bitfield.Width << ">";
2931 case k_RegisterList:
2932 case k_DPRRegisterList:
2933 case k_SPRRegisterList: {
2934 OS << "<register_list ";
2936 const SmallVectorImpl<unsigned> &RegList = getRegList();
2937 for (SmallVectorImpl<unsigned>::const_iterator
2938 I = RegList.begin(), E = RegList.end(); I != E; ) {
2940 if (++I < E) OS << ", ";
2947 OS << "<vector_list " << VectorList.Count << " * "
2948 << VectorList.RegNum << ">";
2950 case k_VectorListAllLanes:
2951 OS << "<vector_list(all lanes) " << VectorList.Count << " * "
2952 << VectorList.RegNum << ">";
2954 case k_VectorListIndexed:
2955 OS << "<vector_list(lane " << VectorList.LaneIndex << ") "
2956 << VectorList.Count << " * " << VectorList.RegNum << ">";
2959 OS << "'" << getToken() << "'";
2962 OS << "<vectorindex " << getVectorIndex() << ">";
2967 /// @name Auto-generated Match Functions
2970 static unsigned MatchRegisterName(StringRef Name);
2974 bool ARMAsmParser::ParseRegister(unsigned &RegNo,
2975 SMLoc &StartLoc, SMLoc &EndLoc) {
2976 const AsmToken &Tok = getParser().getTok();
2977 StartLoc = Tok.getLoc();
2978 EndLoc = Tok.getEndLoc();
2979 RegNo = tryParseRegister();
2981 return (RegNo == (unsigned)-1);
2984 /// Try to parse a register name. The token must be an Identifier when called,
2985 /// and if it is a register name the token is eaten and the register number is
2986 /// returned. Otherwise return -1.
2988 int ARMAsmParser::tryParseRegister() {
2989 MCAsmParser &Parser = getParser();
2990 const AsmToken &Tok = Parser.getTok();
2991 if (Tok.isNot(AsmToken::Identifier)) return -1;
2993 std::string lowerCase = Tok.getString().lower();
2994 unsigned RegNum = MatchRegisterName(lowerCase);
2996 RegNum = StringSwitch<unsigned>(lowerCase)
2997 .Case("r13", ARM::SP)
2998 .Case("r14", ARM::LR)
2999 .Case("r15", ARM::PC)
3000 .Case("ip", ARM::R12)
3001 // Additional register name aliases for 'gas' compatibility.
3002 .Case("a1", ARM::R0)
3003 .Case("a2", ARM::R1)
3004 .Case("a3", ARM::R2)
3005 .Case("a4", ARM::R3)
3006 .Case("v1", ARM::R4)
3007 .Case("v2", ARM::R5)
3008 .Case("v3", ARM::R6)
3009 .Case("v4", ARM::R7)
3010 .Case("v5", ARM::R8)
3011 .Case("v6", ARM::R9)
3012 .Case("v7", ARM::R10)
3013 .Case("v8", ARM::R11)
3014 .Case("sb", ARM::R9)
3015 .Case("sl", ARM::R10)
3016 .Case("fp", ARM::R11)
3020 // Check for aliases registered via .req. Canonicalize to lower case.
3021 // That's more consistent since register names are case insensitive, and
3022 // it's how the original entry was passed in from MC/MCParser/AsmParser.
3023 StringMap<unsigned>::const_iterator Entry = RegisterReqs.find(lowerCase);
3024 // If no match, return failure.
3025 if (Entry == RegisterReqs.end())
3027 Parser.Lex(); // Eat identifier token.
3028 return Entry->getValue();
3031 // Some FPUs only have 16 D registers, so D16-D31 are invalid
3032 if (hasD16() && RegNum >= ARM::D16 && RegNum <= ARM::D31)
3035 Parser.Lex(); // Eat identifier token.
3040 // Try to parse a shifter (e.g., "lsl <amt>"). On success, return 0.
3041 // If a recoverable error occurs, return 1. If an irrecoverable error
3042 // occurs, return -1. An irrecoverable error is one where tokens have been
3043 // consumed in the process of trying to parse the shifter (i.e., when it is
3044 // indeed a shifter operand, but malformed).
3045 int ARMAsmParser::tryParseShiftRegister(OperandVector &Operands) {
3046 MCAsmParser &Parser = getParser();
3047 SMLoc S = Parser.getTok().getLoc();
3048 const AsmToken &Tok = Parser.getTok();
3049 if (Tok.isNot(AsmToken::Identifier))
3052 std::string lowerCase = Tok.getString().lower();
3053 ARM_AM::ShiftOpc ShiftTy = StringSwitch<ARM_AM::ShiftOpc>(lowerCase)
3054 .Case("asl", ARM_AM::lsl)
3055 .Case("lsl", ARM_AM::lsl)
3056 .Case("lsr", ARM_AM::lsr)
3057 .Case("asr", ARM_AM::asr)
3058 .Case("ror", ARM_AM::ror)
3059 .Case("rrx", ARM_AM::rrx)
3060 .Default(ARM_AM::no_shift);
3062 if (ShiftTy == ARM_AM::no_shift)
3065 Parser.Lex(); // Eat the operator.
3067 // The source register for the shift has already been added to the
3068 // operand list, so we need to pop it off and combine it into the shifted
3069 // register operand instead.
3070 std::unique_ptr<ARMOperand> PrevOp(
3071 (ARMOperand *)Operands.pop_back_val().release());
3072 if (!PrevOp->isReg())
3073 return Error(PrevOp->getStartLoc(), "shift must be of a register");
3074 int SrcReg = PrevOp->getReg();
3079 if (ShiftTy == ARM_AM::rrx) {
3080 // RRX Doesn't have an explicit shift amount. The encoder expects
3081 // the shift register to be the same as the source register. Seems odd,
3085 // Figure out if this is shifted by a constant or a register (for non-RRX).
3086 if (Parser.getTok().is(AsmToken::Hash) ||
3087 Parser.getTok().is(AsmToken::Dollar)) {
3088 Parser.Lex(); // Eat hash.
3089 SMLoc ImmLoc = Parser.getTok().getLoc();
3090 const MCExpr *ShiftExpr = nullptr;
3091 if (getParser().parseExpression(ShiftExpr, EndLoc)) {
3092 Error(ImmLoc, "invalid immediate shift value");
3095 // The expression must be evaluatable as an immediate.
3096 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftExpr);
3098 Error(ImmLoc, "invalid immediate shift value");
3101 // Range check the immediate.
3102 // lsl, ror: 0 <= imm <= 31
3103 // lsr, asr: 0 <= imm <= 32
3104 Imm = CE->getValue();
3106 ((ShiftTy == ARM_AM::lsl || ShiftTy == ARM_AM::ror) && Imm > 31) ||
3107 ((ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr) && Imm > 32)) {
3108 Error(ImmLoc, "immediate shift value out of range");
3111 // shift by zero is a nop. Always send it through as lsl.
3112 // ('as' compatibility)
3114 ShiftTy = ARM_AM::lsl;
3115 } else if (Parser.getTok().is(AsmToken::Identifier)) {
3116 SMLoc L = Parser.getTok().getLoc();
3117 EndLoc = Parser.getTok().getEndLoc();
3118 ShiftReg = tryParseRegister();
3119 if (ShiftReg == -1) {
3120 Error(L, "expected immediate or register in shift operand");
3124 Error(Parser.getTok().getLoc(),
3125 "expected immediate or register in shift operand");
3130 if (ShiftReg && ShiftTy != ARM_AM::rrx)
3131 Operands.push_back(ARMOperand::CreateShiftedRegister(ShiftTy, SrcReg,
3135 Operands.push_back(ARMOperand::CreateShiftedImmediate(ShiftTy, SrcReg, Imm,
3142 /// Try to parse a register name. The token must be an Identifier when called.
3143 /// If it's a register, an AsmOperand is created. Another AsmOperand is created
3144 /// if there is a "writeback". 'true' if it's not a register.
3146 /// TODO this is likely to change to allow different register types and or to
3147 /// parse for a specific register type.
3148 bool ARMAsmParser::tryParseRegisterWithWriteBack(OperandVector &Operands) {
3149 MCAsmParser &Parser = getParser();
3150 const AsmToken &RegTok = Parser.getTok();
3151 int RegNo = tryParseRegister();
3155 Operands.push_back(ARMOperand::CreateReg(RegNo, RegTok.getLoc(),
3156 RegTok.getEndLoc()));
3158 const AsmToken &ExclaimTok = Parser.getTok();
3159 if (ExclaimTok.is(AsmToken::Exclaim)) {
3160 Operands.push_back(ARMOperand::CreateToken(ExclaimTok.getString(),
3161 ExclaimTok.getLoc()));
3162 Parser.Lex(); // Eat exclaim token
3166 // Also check for an index operand. This is only legal for vector registers,
3167 // but that'll get caught OK in operand matching, so we don't need to
3168 // explicitly filter everything else out here.
3169 if (Parser.getTok().is(AsmToken::LBrac)) {
3170 SMLoc SIdx = Parser.getTok().getLoc();
3171 Parser.Lex(); // Eat left bracket token.
3173 const MCExpr *ImmVal;
3174 if (getParser().parseExpression(ImmVal))
3176 const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(ImmVal);
3178 return TokError("immediate value expected for vector index");
3180 if (Parser.getTok().isNot(AsmToken::RBrac))
3181 return Error(Parser.getTok().getLoc(), "']' expected");
3183 SMLoc E = Parser.getTok().getEndLoc();
3184 Parser.Lex(); // Eat right bracket token.
3186 Operands.push_back(ARMOperand::CreateVectorIndex(MCE->getValue(),
3194 /// MatchCoprocessorOperandName - Try to parse an coprocessor related
3195 /// instruction with a symbolic operand name.
3196 /// We accept "crN" syntax for GAS compatibility.
3197 /// <operand-name> ::= <prefix><number>
3198 /// If CoprocOp is 'c', then:
3199 /// <prefix> ::= c | cr
3200 /// If CoprocOp is 'p', then :
3202 /// <number> ::= integer in range [0, 15]
3203 static int MatchCoprocessorOperandName(StringRef Name, char CoprocOp) {
3204 // Use the same layout as the tablegen'erated register name matcher. Ugly,
3206 if (Name.size() < 2 || Name[0] != CoprocOp)
3208 Name = (Name[1] == 'r') ? Name.drop_front(2) : Name.drop_front();
3210 switch (Name.size()) {
3231 // CP10 and CP11 are VFP/NEON and so vector instructions should be used.
3232 // However, old cores (v5/v6) did use them in that way.
3233 case '0': return 10;
3234 case '1': return 11;
3235 case '2': return 12;
3236 case '3': return 13;
3237 case '4': return 14;
3238 case '5': return 15;
3243 /// parseITCondCode - Try to parse a condition code for an IT instruction.
3244 ARMAsmParser::OperandMatchResultTy
3245 ARMAsmParser::parseITCondCode(OperandVector &Operands) {
3246 MCAsmParser &Parser = getParser();
3247 SMLoc S = Parser.getTok().getLoc();
3248 const AsmToken &Tok = Parser.getTok();
3249 if (!Tok.is(AsmToken::Identifier))
3250 return MatchOperand_NoMatch;
3251 unsigned CC = StringSwitch<unsigned>(Tok.getString().lower())
3252 .Case("eq", ARMCC::EQ)
3253 .Case("ne", ARMCC::NE)
3254 .Case("hs", ARMCC::HS)
3255 .Case("cs", ARMCC::HS)
3256 .Case("lo", ARMCC::LO)
3257 .Case("cc", ARMCC::LO)
3258 .Case("mi", ARMCC::MI)
3259 .Case("pl", ARMCC::PL)
3260 .Case("vs", ARMCC::VS)
3261 .Case("vc", ARMCC::VC)
3262 .Case("hi", ARMCC::HI)
3263 .Case("ls", ARMCC::LS)
3264 .Case("ge", ARMCC::GE)
3265 .Case("lt", ARMCC::LT)
3266 .Case("gt", ARMCC::GT)
3267 .Case("le", ARMCC::LE)
3268 .Case("al", ARMCC::AL)
3271 return MatchOperand_NoMatch;
3272 Parser.Lex(); // Eat the token.
3274 Operands.push_back(ARMOperand::CreateCondCode(ARMCC::CondCodes(CC), S));
3276 return MatchOperand_Success;
3279 /// parseCoprocNumOperand - Try to parse an coprocessor number operand. The
3280 /// token must be an Identifier when called, and if it is a coprocessor
3281 /// number, the token is eaten and the operand is added to the operand list.
3282 ARMAsmParser::OperandMatchResultTy
3283 ARMAsmParser::parseCoprocNumOperand(OperandVector &Operands) {
3284 MCAsmParser &Parser = getParser();
3285 SMLoc S = Parser.getTok().getLoc();
3286 const AsmToken &Tok = Parser.getTok();
3287 if (Tok.isNot(AsmToken::Identifier))
3288 return MatchOperand_NoMatch;
3290 int Num = MatchCoprocessorOperandName(Tok.getString(), 'p');
3292 return MatchOperand_NoMatch;
3293 // ARMv7 and v8 don't allow cp10/cp11 due to VFP/NEON specific instructions
3294 if ((hasV7Ops() || hasV8Ops()) && (Num == 10 || Num == 11))
3295 return MatchOperand_NoMatch;
3297 Parser.Lex(); // Eat identifier token.
3298 Operands.push_back(ARMOperand::CreateCoprocNum(Num, S));
3299 return MatchOperand_Success;
3302 /// parseCoprocRegOperand - Try to parse an coprocessor register operand. The
3303 /// token must be an Identifier when called, and if it is a coprocessor
3304 /// number, the token is eaten and the operand is added to the operand list.
3305 ARMAsmParser::OperandMatchResultTy
3306 ARMAsmParser::parseCoprocRegOperand(OperandVector &Operands) {
3307 MCAsmParser &Parser = getParser();
3308 SMLoc S = Parser.getTok().getLoc();
3309 const AsmToken &Tok = Parser.getTok();
3310 if (Tok.isNot(AsmToken::Identifier))
3311 return MatchOperand_NoMatch;
3313 int Reg = MatchCoprocessorOperandName(Tok.getString(), 'c');
3315 return MatchOperand_NoMatch;
3317 Parser.Lex(); // Eat identifier token.
3318 Operands.push_back(ARMOperand::CreateCoprocReg(Reg, S));
3319 return MatchOperand_Success;
3322 /// parseCoprocOptionOperand - Try to parse an coprocessor option operand.
3323 /// coproc_option : '{' imm0_255 '}'
3324 ARMAsmParser::OperandMatchResultTy
3325 ARMAsmParser::parseCoprocOptionOperand(OperandVector &Operands) {
3326 MCAsmParser &Parser = getParser();
3327 SMLoc S = Parser.getTok().getLoc();
3329 // If this isn't a '{', this isn't a coprocessor immediate operand.
3330 if (Parser.getTok().isNot(AsmToken::LCurly))
3331 return MatchOperand_NoMatch;
3332 Parser.Lex(); // Eat the '{'
3335 SMLoc Loc = Parser.getTok().getLoc();
3336 if (getParser().parseExpression(Expr)) {
3337 Error(Loc, "illegal expression");
3338 return MatchOperand_ParseFail;
3340 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
3341 if (!CE || CE->getValue() < 0 || CE->getValue() > 255) {
3342 Error(Loc, "coprocessor option must be an immediate in range [0, 255]");
3343 return MatchOperand_ParseFail;
3345 int Val = CE->getValue();
3347 // Check for and consume the closing '}'
3348 if (Parser.getTok().isNot(AsmToken::RCurly))
3349 return MatchOperand_ParseFail;
3350 SMLoc E = Parser.getTok().getEndLoc();
3351 Parser.Lex(); // Eat the '}'
3353 Operands.push_back(ARMOperand::CreateCoprocOption(Val, S, E));
3354 return MatchOperand_Success;
3357 // For register list parsing, we need to map from raw GPR register numbering
3358 // to the enumeration values. The enumeration values aren't sorted by
3359 // register number due to our using "sp", "lr" and "pc" as canonical names.
3360 static unsigned getNextRegister(unsigned Reg) {
3361 // If this is a GPR, we need to do it manually, otherwise we can rely
3362 // on the sort ordering of the enumeration since the other reg-classes
3364 if (!ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
3367 default: llvm_unreachable("Invalid GPR number!");
3368 case ARM::R0: return ARM::R1; case ARM::R1: return ARM::R2;
3369 case ARM::R2: return ARM::R3; case ARM::R3: return ARM::R4;
3370 case ARM::R4: return ARM::R5; case ARM::R5: return ARM::R6;
3371 case ARM::R6: return ARM::R7; case ARM::R7: return ARM::R8;
3372 case ARM::R8: return ARM::R9; case ARM::R9: return ARM::R10;
3373 case ARM::R10: return ARM::R11; case ARM::R11: return ARM::R12;
3374 case ARM::R12: return ARM::SP; case ARM::SP: return ARM::LR;
3375 case ARM::LR: return ARM::PC; case ARM::PC: return ARM::R0;
3379 // Return the low-subreg of a given Q register.
3380 static unsigned getDRegFromQReg(unsigned QReg) {
3382 default: llvm_unreachable("expected a Q register!");
3383 case ARM::Q0: return ARM::D0;
3384 case ARM::Q1: return ARM::D2;
3385 case ARM::Q2: return ARM::D4;
3386 case ARM::Q3: return ARM::D6;
3387 case ARM::Q4: return ARM::D8;
3388 case ARM::Q5: return ARM::D10;
3389 case ARM::Q6: return ARM::D12;
3390 case ARM::Q7: return ARM::D14;
3391 case ARM::Q8: return ARM::D16;
3392 case ARM::Q9: return ARM::D18;
3393 case ARM::Q10: return ARM::D20;
3394 case ARM::Q11: return ARM::D22;
3395 case ARM::Q12: return ARM::D24;
3396 case ARM::Q13: return ARM::D26;
3397 case ARM::Q14: return ARM::D28;
3398 case ARM::Q15: return ARM::D30;
3402 /// Parse a register list.
3403 bool ARMAsmParser::parseRegisterList(OperandVector &Operands) {
3404 MCAsmParser &Parser = getParser();
3405 assert(Parser.getTok().is(AsmToken::LCurly) &&
3406 "Token is not a Left Curly Brace");
3407 SMLoc S = Parser.getTok().getLoc();
3408 Parser.Lex(); // Eat '{' token.
3409 SMLoc RegLoc = Parser.getTok().getLoc();
3411 // Check the first register in the list to see what register class
3412 // this is a list of.
3413 int Reg = tryParseRegister();
3415 return Error(RegLoc, "register expected");
3417 // The reglist instructions have at most 16 registers, so reserve
3418 // space for that many.
3420 SmallVector<std::pair<unsigned, unsigned>, 16> Registers;
3422 // Allow Q regs and just interpret them as the two D sub-registers.
3423 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3424 Reg = getDRegFromQReg(Reg);
3425 EReg = MRI->getEncodingValue(Reg);
3426 Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3429 const MCRegisterClass *RC;
3430 if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
3431 RC = &ARMMCRegisterClasses[ARM::GPRRegClassID];
3432 else if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg))
3433 RC = &ARMMCRegisterClasses[ARM::DPRRegClassID];
3434 else if (ARMMCRegisterClasses[ARM::SPRRegClassID].contains(Reg))
3435 RC = &ARMMCRegisterClasses[ARM::SPRRegClassID];
3437 return Error(RegLoc, "invalid register in register list");
3439 // Store the register.
3440 EReg = MRI->getEncodingValue(Reg);
3441 Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3443 // This starts immediately after the first register token in the list,
3444 // so we can see either a comma or a minus (range separator) as a legal
3446 while (Parser.getTok().is(AsmToken::Comma) ||
3447 Parser.getTok().is(AsmToken::Minus)) {
3448 if (Parser.getTok().is(AsmToken::Minus)) {
3449 Parser.Lex(); // Eat the minus.
3450 SMLoc AfterMinusLoc = Parser.getTok().getLoc();
3451 int EndReg = tryParseRegister();
3453 return Error(AfterMinusLoc, "register expected");
3454 // Allow Q regs and just interpret them as the two D sub-registers.
3455 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg))
3456 EndReg = getDRegFromQReg(EndReg) + 1;
3457 // If the register is the same as the start reg, there's nothing
3461 // The register must be in the same register class as the first.
3462 if (!RC->contains(EndReg))
3463 return Error(AfterMinusLoc, "invalid register in register list");
3464 // Ranges must go from low to high.
3465 if (MRI->getEncodingValue(Reg) > MRI->getEncodingValue(EndReg))
3466 return Error(AfterMinusLoc, "bad range in register list");
3468 // Add all the registers in the range to the register list.
3469 while (Reg != EndReg) {
3470 Reg = getNextRegister(Reg);
3471 EReg = MRI->getEncodingValue(Reg);
3472 Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3476 Parser.Lex(); // Eat the comma.
3477 RegLoc = Parser.getTok().getLoc();
3479 const AsmToken RegTok = Parser.getTok();
3480 Reg = tryParseRegister();
3482 return Error(RegLoc, "register expected");
3483 // Allow Q regs and just interpret them as the two D sub-registers.
3484 bool isQReg = false;
3485 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3486 Reg = getDRegFromQReg(Reg);
3489 // The register must be in the same register class as the first.
3490 if (!RC->contains(Reg))
3491 return Error(RegLoc, "invalid register in register list");
3492 // List must be monotonically increasing.
3493 if (MRI->getEncodingValue(Reg) < MRI->getEncodingValue(OldReg)) {
3494 if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
3495 Warning(RegLoc, "register list not in ascending order");
3497 return Error(RegLoc, "register list not in ascending order");
3499 if (MRI->getEncodingValue(Reg) == MRI->getEncodingValue(OldReg)) {
3500 Warning(RegLoc, "duplicated register (" + RegTok.getString() +
3501 ") in register list");
3504 // VFP register lists must also be contiguous.
3505 if (RC != &ARMMCRegisterClasses[ARM::GPRRegClassID] &&
3507 return Error(RegLoc, "non-contiguous register range");
3508 EReg = MRI->getEncodingValue(Reg);
3509 Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3511 EReg = MRI->getEncodingValue(++Reg);
3512 Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3516 if (Parser.getTok().isNot(AsmToken::RCurly))
3517 return Error(Parser.getTok().getLoc(), "'}' expected");
3518 SMLoc E = Parser.getTok().getEndLoc();
3519 Parser.Lex(); // Eat '}' token.
3521 // Push the register list operand.
3522 Operands.push_back(ARMOperand::CreateRegList(Registers, S, E));
3524 // The ARM system instruction variants for LDM/STM have a '^' token here.
3525 if (Parser.getTok().is(AsmToken::Caret)) {
3526 Operands.push_back(ARMOperand::CreateToken("^",Parser.getTok().getLoc()));
3527 Parser.Lex(); // Eat '^' token.
3533 // Helper function to parse the lane index for vector lists.
3534 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3535 parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index, SMLoc &EndLoc) {
3536 MCAsmParser &Parser = getParser();
3537 Index = 0; // Always return a defined index value.
3538 if (Parser.getTok().is(AsmToken::LBrac)) {
3539 Parser.Lex(); // Eat the '['.
3540 if (Parser.getTok().is(AsmToken::RBrac)) {
3541 // "Dn[]" is the 'all lanes' syntax.
3542 LaneKind = AllLanes;
3543 EndLoc = Parser.getTok().getEndLoc();
3544 Parser.Lex(); // Eat the ']'.
3545 return MatchOperand_Success;
3548 // There's an optional '#' token here. Normally there wouldn't be, but
3549 // inline assemble puts one in, and it's friendly to accept that.
3550 if (Parser.getTok().is(AsmToken::Hash))
3551 Parser.Lex(); // Eat '#' or '$'.
3553 const MCExpr *LaneIndex;
3554 SMLoc Loc = Parser.getTok().getLoc();
3555 if (getParser().parseExpression(LaneIndex)) {
3556 Error(Loc, "illegal expression");
3557 return MatchOperand_ParseFail;
3559 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LaneIndex);
3561 Error(Loc, "lane index must be empty or an integer");
3562 return MatchOperand_ParseFail;
3564 if (Parser.getTok().isNot(AsmToken::RBrac)) {
3565 Error(Parser.getTok().getLoc(), "']' expected");
3566 return MatchOperand_ParseFail;
3568 EndLoc = Parser.getTok().getEndLoc();
3569 Parser.Lex(); // Eat the ']'.
3570 int64_t Val = CE->getValue();
3572 // FIXME: Make this range check context sensitive for .8, .16, .32.
3573 if (Val < 0 || Val > 7) {
3574 Error(Parser.getTok().getLoc(), "lane index out of range");
3575 return MatchOperand_ParseFail;
3578 LaneKind = IndexedLane;
3579 return MatchOperand_Success;
3582 return MatchOperand_Success;
3585 // parse a vector register list
3586 ARMAsmParser::OperandMatchResultTy
3587 ARMAsmParser::parseVectorList(OperandVector &Operands) {
3588 MCAsmParser &Parser = getParser();
3589 VectorLaneTy LaneKind;
3591 SMLoc S = Parser.getTok().getLoc();
3592 // As an extension (to match gas), support a plain D register or Q register
3593 // (without encosing curly braces) as a single or double entry list,
3595 if (Parser.getTok().is(AsmToken::Identifier)) {
3596 SMLoc E = Parser.getTok().getEndLoc();
3597 int Reg = tryParseRegister();
3599 return MatchOperand_NoMatch;
3600 if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg)) {
3601 OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex, E);
3602 if (Res != MatchOperand_Success)
3606 Operands.push_back(ARMOperand::CreateVectorList(Reg, 1, false, S, E));
3609 Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 1, false,
3613 Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 1,
3618 return MatchOperand_Success;
3620 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3621 Reg = getDRegFromQReg(Reg);
3622 OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex, E);
3623 if (Res != MatchOperand_Success)
3627 Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0,
3628 &ARMMCRegisterClasses[ARM::DPairRegClassID]);
3629 Operands.push_back(ARMOperand::CreateVectorList(Reg, 2, false, S, E));
3632 Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0,
3633 &ARMMCRegisterClasses[ARM::DPairRegClassID]);
3634 Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 2, false,
3638 Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 2,
3643 return MatchOperand_Success;
3645 Error(S, "vector register expected");
3646 return MatchOperand_ParseFail;
3649 if (Parser.getTok().isNot(AsmToken::LCurly))
3650 return MatchOperand_NoMatch;
3652 Parser.Lex(); // Eat '{' token.
3653 SMLoc RegLoc = Parser.getTok().getLoc();
3655 int Reg = tryParseRegister();
3657 Error(RegLoc, "register expected");
3658 return MatchOperand_ParseFail;
3662 unsigned FirstReg = Reg;
3663 // The list is of D registers, but we also allow Q regs and just interpret
3664 // them as the two D sub-registers.
3665 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3666 FirstReg = Reg = getDRegFromQReg(Reg);
3667 Spacing = 1; // double-spacing requires explicit D registers, otherwise
3668 // it's ambiguous with four-register single spaced.
3674 if (parseVectorLane(LaneKind, LaneIndex, E) != MatchOperand_Success)
3675 return MatchOperand_ParseFail;
3677 while (Parser.getTok().is(AsmToken::Comma) ||
3678 Parser.getTok().is(AsmToken::Minus)) {
3679 if (Parser.getTok().is(AsmToken::Minus)) {
3681 Spacing = 1; // Register range implies a single spaced list.
3682 else if (Spacing == 2) {
3683 Error(Parser.getTok().getLoc(),
3684 "sequential registers in double spaced list");
3685 return MatchOperand_ParseFail;
3687 Parser.Lex(); // Eat the minus.
3688 SMLoc AfterMinusLoc = Parser.getTok().getLoc();
3689 int EndReg = tryParseRegister();
3691 Error(AfterMinusLoc, "register expected");
3692 return MatchOperand_ParseFail;
3694 // Allow Q regs and just interpret them as the two D sub-registers.
3695 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg))
3696 EndReg = getDRegFromQReg(EndReg) + 1;
3697 // If the register is the same as the start reg, there's nothing
3701 // The register must be in the same register class as the first.
3702 if (!ARMMCRegisterClasses[ARM::DPRRegClassID].contains(EndReg)) {
3703 Error(AfterMinusLoc, "invalid register in register list");
3704 return MatchOperand_ParseFail;
3706 // Ranges must go from low to high.
3708 Error(AfterMinusLoc, "bad range in register list");
3709 return MatchOperand_ParseFail;
3711 // Parse the lane specifier if present.
3712 VectorLaneTy NextLaneKind;
3713 unsigned NextLaneIndex;
3714 if (parseVectorLane(NextLaneKind, NextLaneIndex, E) !=
3715 MatchOperand_Success)
3716 return MatchOperand_ParseFail;
3717 if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
3718 Error(AfterMinusLoc, "mismatched lane index in register list");
3719 return MatchOperand_ParseFail;
3722 // Add all the registers in the range to the register list.
3723 Count += EndReg - Reg;
3727 Parser.Lex(); // Eat the comma.
3728 RegLoc = Parser.getTok().getLoc();
3730 Reg = tryParseRegister();
3732 Error(RegLoc, "register expected");
3733 return MatchOperand_ParseFail;
3735 // vector register lists must be contiguous.
3736 // It's OK to use the enumeration values directly here rather, as the
3737 // VFP register classes have the enum sorted properly.
3739 // The list is of D registers, but we also allow Q regs and just interpret
3740 // them as the two D sub-registers.
3741 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3743 Spacing = 1; // Register range implies a single spaced list.
3744 else if (Spacing == 2) {
3746 "invalid register in double-spaced list (must be 'D' register')");
3747 return MatchOperand_ParseFail;
3749 Reg = getDRegFromQReg(Reg);
3750 if (Reg != OldReg + 1) {
3751 Error(RegLoc, "non-contiguous register range");
3752 return MatchOperand_ParseFail;
3756 // Parse the lane specifier if present.
3757 VectorLaneTy NextLaneKind;
3758 unsigned NextLaneIndex;
3759 SMLoc LaneLoc = Parser.getTok().getLoc();
3760 if (parseVectorLane(NextLaneKind, NextLaneIndex, E) !=
3761 MatchOperand_Success)
3762 return MatchOperand_ParseFail;
3763 if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
3764 Error(LaneLoc, "mismatched lane index in register list");
3765 return MatchOperand_ParseFail;
3769 // Normal D register.
3770 // Figure out the register spacing (single or double) of the list if
3771 // we don't know it already.
3773 Spacing = 1 + (Reg == OldReg + 2);
3775 // Just check that it's contiguous and keep going.
3776 if (Reg != OldReg + Spacing) {
3777 Error(RegLoc, "non-contiguous register range");
3778 return MatchOperand_ParseFail;
3781 // Parse the lane specifier if present.
3782 VectorLaneTy NextLaneKind;
3783 unsigned NextLaneIndex;
3784 SMLoc EndLoc = Parser.getTok().getLoc();
3785 if (parseVectorLane(NextLaneKind, NextLaneIndex, E) != MatchOperand_Success)
3786 return MatchOperand_ParseFail;
3787 if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
3788 Error(EndLoc, "mismatched lane index in register list");
3789 return MatchOperand_ParseFail;
3793 if (Parser.getTok().isNot(AsmToken::RCurly)) {
3794 Error(Parser.getTok().getLoc(), "'}' expected");
3795 return MatchOperand_ParseFail;
3797 E = Parser.getTok().getEndLoc();
3798 Parser.Lex(); // Eat '}' token.
3802 // Two-register operands have been converted to the
3803 // composite register classes.
3805 const MCRegisterClass *RC = (Spacing == 1) ?
3806 &ARMMCRegisterClasses[ARM::DPairRegClassID] :
3807 &ARMMCRegisterClasses[ARM::DPairSpcRegClassID];
3808 FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC);
3811 Operands.push_back(ARMOperand::CreateVectorList(FirstReg, Count,
3812 (Spacing == 2), S, E));
3815 // Two-register operands have been converted to the
3816 // composite register classes.
3818 const MCRegisterClass *RC = (Spacing == 1) ?
3819 &ARMMCRegisterClasses[ARM::DPairRegClassID] :
3820 &ARMMCRegisterClasses[ARM::DPairSpcRegClassID];
3821 FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC);
3823 Operands.push_back(ARMOperand::CreateVectorListAllLanes(FirstReg, Count,
3828 Operands.push_back(ARMOperand::CreateVectorListIndexed(FirstReg, Count,
3834 return MatchOperand_Success;
3837 /// parseMemBarrierOptOperand - Try to parse DSB/DMB data barrier options.
3838 ARMAsmParser::OperandMatchResultTy
3839 ARMAsmParser::parseMemBarrierOptOperand(OperandVector &Operands) {
3840 MCAsmParser &Parser = getParser();
3841 SMLoc S = Parser.getTok().getLoc();
3842 const AsmToken &Tok = Parser.getTok();
3845 if (Tok.is(AsmToken::Identifier)) {
3846 StringRef OptStr = Tok.getString();
3848 Opt = StringSwitch<unsigned>(OptStr.slice(0, OptStr.size()).lower())
3849 .Case("sy", ARM_MB::SY)
3850 .Case("st", ARM_MB::ST)
3851 .Case("ld", ARM_MB::LD)
3852 .Case("sh", ARM_MB::ISH)
3853 .Case("ish", ARM_MB::ISH)
3854 .Case("shst", ARM_MB::ISHST)
3855 .Case("ishst", ARM_MB::ISHST)
3856 .Case("ishld", ARM_MB::ISHLD)
3857 .Case("nsh", ARM_MB::NSH)
3858 .Case("un", ARM_MB::NSH)
3859 .Case("nshst", ARM_MB::NSHST)
3860 .Case("nshld", ARM_MB::NSHLD)
3861 .Case("unst", ARM_MB::NSHST)
3862 .Case("osh", ARM_MB::OSH)
3863 .Case("oshst", ARM_MB::OSHST)
3864 .Case("oshld", ARM_MB::OSHLD)
3867 // ishld, oshld, nshld and ld are only available from ARMv8.
3868 if (!hasV8Ops() && (Opt == ARM_MB::ISHLD || Opt == ARM_MB::OSHLD ||
3869 Opt == ARM_MB::NSHLD || Opt == ARM_MB::LD))
3873 return MatchOperand_NoMatch;
3875 Parser.Lex(); // Eat identifier token.
3876 } else if (Tok.is(AsmToken::Hash) ||
3877 Tok.is(AsmToken::Dollar) ||
3878 Tok.is(AsmToken::Integer)) {
3879 if (Parser.getTok().isNot(AsmToken::Integer))
3880 Parser.Lex(); // Eat '#' or '$'.
3881 SMLoc Loc = Parser.getTok().getLoc();
3883 const MCExpr *MemBarrierID;
3884 if (getParser().parseExpression(MemBarrierID)) {
3885 Error(Loc, "illegal expression");
3886 return MatchOperand_ParseFail;
3889 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(MemBarrierID);
3891 Error(Loc, "constant expression expected");
3892 return MatchOperand_ParseFail;
3895 int Val = CE->getValue();
3897 Error(Loc, "immediate value out of range");
3898 return MatchOperand_ParseFail;
3901 Opt = ARM_MB::RESERVED_0 + Val;
3903 return MatchOperand_ParseFail;
3905 Operands.push_back(ARMOperand::CreateMemBarrierOpt((ARM_MB::MemBOpt)Opt, S));
3906 return MatchOperand_Success;
3909 /// parseInstSyncBarrierOptOperand - Try to parse ISB inst sync barrier options.
3910 ARMAsmParser::OperandMatchResultTy
3911 ARMAsmParser::parseInstSyncBarrierOptOperand(OperandVector &Operands) {
3912 MCAsmParser &Parser = getParser();
3913 SMLoc S = Parser.getTok().getLoc();
3914 const AsmToken &Tok = Parser.getTok();
3917 if (Tok.is(AsmToken::Identifier)) {
3918 StringRef OptStr = Tok.getString();
3920 if (OptStr.equals_lower("sy"))
3923 return MatchOperand_NoMatch;
3925 Parser.Lex(); // Eat identifier token.
3926 } else if (Tok.is(AsmToken::Hash) ||
3927 Tok.is(AsmToken::Dollar) ||
3928 Tok.is(AsmToken::Integer)) {
3929 if (Parser.getTok().isNot(AsmToken::Integer))
3930 Parser.Lex(); // Eat '#' or '$'.
3931 SMLoc Loc = Parser.getTok().getLoc();
3933 const MCExpr *ISBarrierID;
3934 if (getParser().parseExpression(ISBarrierID)) {
3935 Error(Loc, "illegal expression");
3936 return MatchOperand_ParseFail;
3939 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ISBarrierID);
3941 Error(Loc, "constant expression expected");
3942 return MatchOperand_ParseFail;
3945 int Val = CE->getValue();
3947 Error(Loc, "immediate value out of range");
3948 return MatchOperand_ParseFail;
3951 Opt = ARM_ISB::RESERVED_0 + Val;
3953 return MatchOperand_ParseFail;
3955 Operands.push_back(ARMOperand::CreateInstSyncBarrierOpt(
3956 (ARM_ISB::InstSyncBOpt)Opt, S));
3957 return MatchOperand_Success;
3961 /// parseProcIFlagsOperand - Try to parse iflags from CPS instruction.
3962 ARMAsmParser::OperandMatchResultTy
3963 ARMAsmParser::parseProcIFlagsOperand(OperandVector &Operands) {
3964 MCAsmParser &Parser = getParser();
3965 SMLoc S = Parser.getTok().getLoc();
3966 const AsmToken &Tok = Parser.getTok();
3967 if (!Tok.is(AsmToken::Identifier))
3968 return MatchOperand_NoMatch;
3969 StringRef IFlagsStr = Tok.getString();
3971 // An iflags string of "none" is interpreted to mean that none of the AIF
3972 // bits are set. Not a terribly useful instruction, but a valid encoding.
3973 unsigned IFlags = 0;
3974 if (IFlagsStr != "none") {
3975 for (int i = 0, e = IFlagsStr.size(); i != e; ++i) {
3976 unsigned Flag = StringSwitch<unsigned>(IFlagsStr.substr(i, 1))
3977 .Case("a", ARM_PROC::A)
3978 .Case("i", ARM_PROC::I)
3979 .Case("f", ARM_PROC::F)
3982 // If some specific iflag is already set, it means that some letter is
3983 // present more than once, this is not acceptable.
3984 if (Flag == ~0U || (IFlags & Flag))
3985 return MatchOperand_NoMatch;
3991 Parser.Lex(); // Eat identifier token.
3992 Operands.push_back(ARMOperand::CreateProcIFlags((ARM_PROC::IFlags)IFlags, S));
3993 return MatchOperand_Success;
3996 /// parseMSRMaskOperand - Try to parse mask flags from MSR instruction.
3997 ARMAsmParser::OperandMatchResultTy
3998 ARMAsmParser::parseMSRMaskOperand(OperandVector &Operands) {
3999 MCAsmParser &Parser = getParser();
4000 SMLoc S = Parser.getTok().getLoc();
4001 const AsmToken &Tok = Parser.getTok();
4002 if (!Tok.is(AsmToken::Identifier))
4003 return MatchOperand_NoMatch;
4004 StringRef Mask = Tok.getString();
4007 // See ARMv6-M 10.1.1
4008 std::string Name = Mask.lower();
4009 unsigned FlagsVal = StringSwitch<unsigned>(Name)
4010 // Note: in the documentation:
4011 // ARM deprecates using MSR APSR without a _<bits> qualifier as an alias
4012 // for MSR APSR_nzcvq.
4013 // but we do make it an alias here. This is so to get the "mask encoding"
4014 // bits correct on MSR APSR writes.
4016 // FIXME: Note the 0xc00 "mask encoding" bits version of the registers
4017 // should really only be allowed when writing a special register. Note
4018 // they get dropped in the MRS instruction reading a special register as
4019 // the SYSm field is only 8 bits.
4020 .Case("apsr", 0x800)
4021 .Case("apsr_nzcvq", 0x800)
4022 .Case("apsr_g", 0x400)
4023 .Case("apsr_nzcvqg", 0xc00)
4024 .Case("iapsr", 0x801)
4025 .Case("iapsr_nzcvq", 0x801)
4026 .Case("iapsr_g", 0x401)
4027 .Case("iapsr_nzcvqg", 0xc01)
4028 .Case("eapsr", 0x802)
4029 .Case("eapsr_nzcvq", 0x802)
4030 .Case("eapsr_g", 0x402)
4031 .Case("eapsr_nzcvqg", 0xc02)
4032 .Case("xpsr", 0x803)
4033 .Case("xpsr_nzcvq", 0x803)
4034 .Case("xpsr_g", 0x403)
4035 .Case("xpsr_nzcvqg", 0xc03)
4036 .Case("ipsr", 0x805)
4037 .Case("epsr", 0x806)
4038 .Case("iepsr", 0x807)
4041 .Case("primask", 0x810)
4042 .Case("basepri", 0x811)
4043 .Case("basepri_max", 0x812)
4044 .Case("faultmask", 0x813)
4045 .Case("control", 0x814)
4048 if (FlagsVal == ~0U)
4049 return MatchOperand_NoMatch;
4051 if (!hasThumb2DSP() && (FlagsVal & 0x400))
4052 // The _g and _nzcvqg versions are only valid if the DSP extension is
4054 return MatchOperand_NoMatch;
4056 if (!hasV7Ops() && FlagsVal >= 0x811 && FlagsVal <= 0x813)
4057 // basepri, basepri_max and faultmask only valid for V7m.
4058 return MatchOperand_NoMatch;
4060 Parser.Lex(); // Eat identifier token.
4061 Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S));
4062 return MatchOperand_Success;
4065 // Split spec_reg from flag, example: CPSR_sxf => "CPSR" and "sxf"
4066 size_t Start = 0, Next = Mask.find('_');
4067 StringRef Flags = "";
4068 std::string SpecReg = Mask.slice(Start, Next).lower();
4069 if (Next != StringRef::npos)
4070 Flags = Mask.slice(Next+1, Mask.size());
4072 // FlagsVal contains the complete mask:
4074 // 4: Special Reg (cpsr, apsr => 0; spsr => 1)
4075 unsigned FlagsVal = 0;
4077 if (SpecReg == "apsr") {
4078 FlagsVal = StringSwitch<unsigned>(Flags)
4079 .Case("nzcvq", 0x8) // same as CPSR_f
4080 .Case("g", 0x4) // same as CPSR_s
4081 .Case("nzcvqg", 0xc) // same as CPSR_fs
4084 if (FlagsVal == ~0U) {
4086 return MatchOperand_NoMatch;
4088 FlagsVal = 8; // No flag
4090 } else if (SpecReg == "cpsr" || SpecReg == "spsr") {
4091 // cpsr_all is an alias for cpsr_fc, as is plain cpsr.
4092 if (Flags == "all" || Flags == "")
4094 for (int i = 0, e = Flags.size(); i != e; ++i) {
4095 unsigned Flag = StringSwitch<unsigned>(Flags.substr(i, 1))
4102 // If some specific flag is already set, it means that some letter is
4103 // present more than once, this is not acceptable.
4104 if (FlagsVal == ~0U || (FlagsVal & Flag))
4105 return MatchOperand_NoMatch;
4108 } else // No match for special register.
4109 return MatchOperand_NoMatch;
4111 // Special register without flags is NOT equivalent to "fc" flags.
4112 // NOTE: This is a divergence from gas' behavior. Uncommenting the following
4113 // two lines would enable gas compatibility at the expense of breaking
4119 // Bit 4: Special Reg (cpsr, apsr => 0; spsr => 1)
4120 if (SpecReg == "spsr")
4123 Parser.Lex(); // Eat identifier token.
4124 Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S));
4125 return MatchOperand_Success;
4128 /// parseBankedRegOperand - Try to parse a banked register (e.g. "lr_irq") for
4129 /// use in the MRS/MSR instructions added to support virtualization.
4130 ARMAsmParser::OperandMatchResultTy
4131 ARMAsmParser::parseBankedRegOperand(OperandVector &Operands) {
4132 MCAsmParser &Parser = getParser();
4133 SMLoc S = Parser.getTok().getLoc();
4134 const AsmToken &Tok = Parser.getTok();
4135 if (!Tok.is(AsmToken::Identifier))
4136 return MatchOperand_NoMatch;
4137 StringRef RegName = Tok.getString();
4139 // The values here come from B9.2.3 of the ARM ARM, where bits 4-0 are SysM
4141 unsigned Encoding = StringSwitch<unsigned>(RegName.lower())
4142 .Case("r8_usr", 0x00)
4143 .Case("r9_usr", 0x01)
4144 .Case("r10_usr", 0x02)
4145 .Case("r11_usr", 0x03)
4146 .Case("r12_usr", 0x04)
4147 .Case("sp_usr", 0x05)
4148 .Case("lr_usr", 0x06)
4149 .Case("r8_fiq", 0x08)
4150 .Case("r9_fiq", 0x09)
4151 .Case("r10_fiq", 0x0a)
4152 .Case("r11_fiq", 0x0b)
4153 .Case("r12_fiq", 0x0c)
4154 .Case("sp_fiq", 0x0d)
4155 .Case("lr_fiq", 0x0e)
4156 .Case("lr_irq", 0x10)
4157 .Case("sp_irq", 0x11)
4158 .Case("lr_svc", 0x12)
4159 .Case("sp_svc", 0x13)
4160 .Case("lr_abt", 0x14)
4161 .Case("sp_abt", 0x15)
4162 .Case("lr_und", 0x16)
4163 .Case("sp_und", 0x17)
4164 .Case("lr_mon", 0x1c)
4165 .Case("sp_mon", 0x1d)
4166 .Case("elr_hyp", 0x1e)
4167 .Case("sp_hyp", 0x1f)
4168 .Case("spsr_fiq", 0x2e)
4169 .Case("spsr_irq", 0x30)
4170 .Case("spsr_svc", 0x32)
4171 .Case("spsr_abt", 0x34)
4172 .Case("spsr_und", 0x36)
4173 .Case("spsr_mon", 0x3c)
4174 .Case("spsr_hyp", 0x3e)
4177 if (Encoding == ~0U)
4178 return MatchOperand_NoMatch;
4180 Parser.Lex(); // Eat identifier token.
4181 Operands.push_back(ARMOperand::CreateBankedReg(Encoding, S));
4182 return MatchOperand_Success;
4185 ARMAsmParser::OperandMatchResultTy
4186 ARMAsmParser::parsePKHImm(OperandVector &Operands, StringRef Op, int Low,
4188 MCAsmParser &Parser = getParser();
4189 const AsmToken &Tok = Parser.getTok();
4190 if (Tok.isNot(AsmToken::Identifier)) {
4191 Error(Parser.getTok().getLoc(), Op + " operand expected.");
4192 return MatchOperand_ParseFail;
4194 StringRef ShiftName = Tok.getString();
4195 std::string LowerOp = Op.lower();
4196 std::string UpperOp = Op.upper();
4197 if (ShiftName != LowerOp && ShiftName != UpperOp) {
4198 Error(Parser.getTok().getLoc(), Op + " operand expected.");
4199 return MatchOperand_ParseFail;
4201 Parser.Lex(); // Eat shift type token.
4203 // There must be a '#' and a shift amount.
4204 if (Parser.getTok().isNot(AsmToken::Hash) &&
4205 Parser.getTok().isNot(AsmToken::Dollar)) {
4206 Error(Parser.getTok().getLoc(), "'#' expected");
4207 return MatchOperand_ParseFail;
4209 Parser.Lex(); // Eat hash token.
4211 const MCExpr *ShiftAmount;
4212 SMLoc Loc = Parser.getTok().getLoc();
4214 if (getParser().parseExpression(ShiftAmount, EndLoc)) {
4215 Error(Loc, "illegal expression");
4216 return MatchOperand_ParseFail;
4218 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
4220 Error(Loc, "constant expression expected");
4221 return MatchOperand_ParseFail;
4223 int Val = CE->getValue();
4224 if (Val < Low || Val > High) {
4225 Error(Loc, "immediate value out of range");
4226 return MatchOperand_ParseFail;
4229 Operands.push_back(ARMOperand::CreateImm(CE, Loc, EndLoc));
4231 return MatchOperand_Success;
4234 ARMAsmParser::OperandMatchResultTy
4235 ARMAsmParser::parseSetEndImm(OperandVector &Operands) {
4236 MCAsmParser &Parser = getParser();
4237 const AsmToken &Tok = Parser.getTok();
4238 SMLoc S = Tok.getLoc();
4239 if (Tok.isNot(AsmToken::Identifier)) {
4240 Error(S, "'be' or 'le' operand expected");
4241 return MatchOperand_ParseFail;
4243 int Val = StringSwitch<int>(Tok.getString().lower())
4247 Parser.Lex(); // Eat the token.
4250 Error(S, "'be' or 'le' operand expected");
4251 return MatchOperand_ParseFail;
4253 Operands.push_back(ARMOperand::CreateImm(MCConstantExpr::Create(Val,
4255 S, Tok.getEndLoc()));
4256 return MatchOperand_Success;
4259 /// parseShifterImm - Parse the shifter immediate operand for SSAT/USAT
4260 /// instructions. Legal values are:
4261 /// lsl #n 'n' in [0,31]
4262 /// asr #n 'n' in [1,32]
4263 /// n == 32 encoded as n == 0.
4264 ARMAsmParser::OperandMatchResultTy
4265 ARMAsmParser::parseShifterImm(OperandVector &Operands) {
4266 MCAsmParser &Parser = getParser();
4267 const AsmToken &Tok = Parser.getTok();
4268 SMLoc S = Tok.getLoc();
4269 if (Tok.isNot(AsmToken::Identifier)) {
4270 Error(S, "shift operator 'asr' or 'lsl' expected");
4271 return MatchOperand_ParseFail;
4273 StringRef ShiftName = Tok.getString();
4275 if (ShiftName == "lsl" || ShiftName == "LSL")
4277 else if (ShiftName == "asr" || ShiftName == "ASR")
4280 Error(S, "shift operator 'asr' or 'lsl' expected");
4281 return MatchOperand_ParseFail;
4283 Parser.Lex(); // Eat the operator.
4285 // A '#' and a shift amount.
4286 if (Parser.getTok().isNot(AsmToken::Hash) &&
4287 Parser.getTok().isNot(AsmToken::Dollar)) {
4288 Error(Parser.getTok().getLoc(), "'#' expected");
4289 return MatchOperand_ParseFail;
4291 Parser.Lex(); // Eat hash token.
4292 SMLoc ExLoc = Parser.getTok().getLoc();
4294 const MCExpr *ShiftAmount;
4296 if (getParser().parseExpression(ShiftAmount, EndLoc)) {
4297 Error(ExLoc, "malformed shift expression");
4298 return MatchOperand_ParseFail;
4300 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
4302 Error(ExLoc, "shift amount must be an immediate");
4303 return MatchOperand_ParseFail;
4306 int64_t Val = CE->getValue();
4308 // Shift amount must be in [1,32]
4309 if (Val < 1 || Val > 32) {
4310 Error(ExLoc, "'asr' shift amount must be in range [1,32]");
4311 return MatchOperand_ParseFail;
4313 // asr #32 encoded as asr #0, but is not allowed in Thumb2 mode.
4314 if (isThumb() && Val == 32) {
4315 Error(ExLoc, "'asr #32' shift amount not allowed in Thumb mode");
4316 return MatchOperand_ParseFail;
4318 if (Val == 32) Val = 0;
4320 // Shift amount must be in [1,32]
4321 if (Val < 0 || Val > 31) {
4322 Error(ExLoc, "'lsr' shift amount must be in range [0,31]");
4323 return MatchOperand_ParseFail;
4327 Operands.push_back(ARMOperand::CreateShifterImm(isASR, Val, S, EndLoc));
4329 return MatchOperand_Success;
4332 /// parseRotImm - Parse the shifter immediate operand for SXTB/UXTB family
4333 /// of instructions. Legal values are:
4334 /// ror #n 'n' in {0, 8, 16, 24}
4335 ARMAsmParser::OperandMatchResultTy
4336 ARMAsmParser::parseRotImm(OperandVector &Operands) {
4337 MCAsmParser &Parser = getParser();
4338 const AsmToken &Tok = Parser.getTok();
4339 SMLoc S = Tok.getLoc();
4340 if (Tok.isNot(AsmToken::Identifier))
4341 return MatchOperand_NoMatch;
4342 StringRef ShiftName = Tok.getString();
4343 if (ShiftName != "ror" && ShiftName != "ROR")
4344 return MatchOperand_NoMatch;
4345 Parser.Lex(); // Eat the operator.
4347 // A '#' and a rotate amount.
4348 if (Parser.getTok().isNot(AsmToken::Hash) &&
4349 Parser.getTok().isNot(AsmToken::Dollar)) {
4350 Error(Parser.getTok().getLoc(), "'#' expected");
4351 return MatchOperand_ParseFail;
4353 Parser.Lex(); // Eat hash token.
4354 SMLoc ExLoc = Parser.getTok().getLoc();
4356 const MCExpr *ShiftAmount;
4358 if (getParser().parseExpression(ShiftAmount, EndLoc)) {
4359 Error(ExLoc, "malformed rotate expression");
4360 return MatchOperand_ParseFail;
4362 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
4364 Error(ExLoc, "rotate amount must be an immediate");
4365 return MatchOperand_ParseFail;
4368 int64_t Val = CE->getValue();
4369 // Shift amount must be in {0, 8, 16, 24} (0 is undocumented extension)
4370 // normally, zero is represented in asm by omitting the rotate operand
4372 if (Val != 8 && Val != 16 && Val != 24 && Val != 0) {
4373 Error(ExLoc, "'ror' rotate amount must be 8, 16, or 24");
4374 return MatchOperand_ParseFail;
4377 Operands.push_back(ARMOperand::CreateRotImm(Val, S, EndLoc));
4379 return MatchOperand_Success;
4382 ARMAsmParser::OperandMatchResultTy
4383 ARMAsmParser::parseModImm(OperandVector &Operands) {
4384 MCAsmParser &Parser = getParser();
4385 MCAsmLexer &Lexer = getLexer();
4388 SMLoc S = Parser.getTok().getLoc();
4390 // 1) A mod_imm operand can appear in the place of a register name:
4392 // add r0, r0, #mod_imm
4393 // to correctly handle the latter, we bail out as soon as we see an
4396 // 2) Similarly, we do not want to parse into complex operands:
4398 // mov r0, :lower16:(_foo)
4399 if (Parser.getTok().is(AsmToken::Identifier) ||
4400 Parser.getTok().is(AsmToken::Colon))
4401 return MatchOperand_NoMatch;
4403 // Hash (dollar) is optional as per the ARMARM
4404 if (Parser.getTok().is(AsmToken::Hash) ||
4405 Parser.getTok().is(AsmToken::Dollar)) {
4406 // Avoid parsing into complex operands (#:)
4407 if (Lexer.peekTok().is(AsmToken::Colon))
4408 return MatchOperand_NoMatch;
4410 // Eat the hash (dollar)
4415 Sx1 = Parser.getTok().getLoc();
4416 const MCExpr *Imm1Exp;
4417 if (getParser().parseExpression(Imm1Exp, Ex1)) {
4418 Error(Sx1, "malformed expression");
4419 return MatchOperand_ParseFail;
4422 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm1Exp);
4425 // Immediate must fit within 32-bits
4426 Imm1 = CE->getValue();
4427 int Enc = ARM_AM::getSOImmVal(Imm1);
4428 if (Enc != -1 && Parser.getTok().is(AsmToken::EndOfStatement)) {
4430 Operands.push_back(ARMOperand::CreateModImm((Enc & 0xFF),
4433 return MatchOperand_Success;
4436 // We have parsed an immediate which is not for us, fallback to a plain
4437 // immediate. This can happen for instruction aliases. For an example,
4438 // ARMInstrInfo.td defines the alias [mov <-> mvn] which can transform
4439 // a mov (mvn) with a mod_imm_neg/mod_imm_not operand into the opposite
4440 // instruction with a mod_imm operand. The alias is defined such that the
4441 // parser method is shared, that's why we have to do this here.
4442 if (Parser.getTok().is(AsmToken::EndOfStatement)) {
4443 Operands.push_back(ARMOperand::CreateImm(Imm1Exp, Sx1, Ex1));
4444 return MatchOperand_Success;
4447 // Operands like #(l1 - l2) can only be evaluated at a later stage (via an
4448 // MCFixup). Fallback to a plain immediate.
4449 Operands.push_back(ARMOperand::CreateImm(Imm1Exp, Sx1, Ex1));
4450 return MatchOperand_Success;
4453 // From this point onward, we expect the input to be a (#bits, #rot) pair
4454 if (Parser.getTok().isNot(AsmToken::Comma)) {
4455 Error(Sx1, "expected modified immediate operand: #[0, 255], #even[0-30]");
4456 return MatchOperand_ParseFail;
4460 Error(Sx1, "immediate operand must a number in the range [0, 255]");
4461 return MatchOperand_ParseFail;
4469 Sx2 = Parser.getTok().getLoc();
4471 // Eat the optional hash (dollar)
4472 if (Parser.getTok().is(AsmToken::Hash) ||
4473 Parser.getTok().is(AsmToken::Dollar))
4476 const MCExpr *Imm2Exp;
4477 if (getParser().parseExpression(Imm2Exp, Ex2)) {
4478 Error(Sx2, "malformed expression");
4479 return MatchOperand_ParseFail;
4482 CE = dyn_cast<MCConstantExpr>(Imm2Exp);
4485 Imm2 = CE->getValue();
4486 if (!(Imm2 & ~0x1E)) {
4488 Operands.push_back(ARMOperand::CreateModImm(Imm1, Imm2, S, Ex2));
4489 return MatchOperand_Success;
4491 Error(Sx2, "immediate operand must an even number in the range [0, 30]");
4492 return MatchOperand_ParseFail;
4494 Error(Sx2, "constant expression expected");
4495 return MatchOperand_ParseFail;
4499 ARMAsmParser::OperandMatchResultTy
4500 ARMAsmParser::parseBitfield(OperandVector &Operands) {
4501 MCAsmParser &Parser = getParser();
4502 SMLoc S = Parser.getTok().getLoc();
4503 // The bitfield descriptor is really two operands, the LSB and the width.
4504 if (Parser.getTok().isNot(AsmToken::Hash) &&
4505 Parser.getTok().isNot(AsmToken::Dollar)) {
4506 Error(Parser.getTok().getLoc(), "'#' expected");
4507 return MatchOperand_ParseFail;
4509 Parser.Lex(); // Eat hash token.
4511 const MCExpr *LSBExpr;
4512 SMLoc E = Parser.getTok().getLoc();
4513 if (getParser().parseExpression(LSBExpr)) {
4514 Error(E, "malformed immediate expression");
4515 return MatchOperand_ParseFail;
4517 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LSBExpr);
4519 Error(E, "'lsb' operand must be an immediate");
4520 return MatchOperand_ParseFail;
4523 int64_t LSB = CE->getValue();
4524 // The LSB must be in the range [0,31]
4525 if (LSB < 0 || LSB > 31) {
4526 Error(E, "'lsb' operand must be in the range [0,31]");
4527 return MatchOperand_ParseFail;
4529 E = Parser.getTok().getLoc();
4531 // Expect another immediate operand.
4532 if (Parser.getTok().isNot(AsmToken::Comma)) {
4533 Error(Parser.getTok().getLoc(), "too few operands");
4534 return MatchOperand_ParseFail;
4536 Parser.Lex(); // Eat hash token.
4537 if (Parser.getTok().isNot(AsmToken::Hash) &&
4538 Parser.getTok().isNot(AsmToken::Dollar)) {
4539 Error(Parser.getTok().getLoc(), "'#' expected");
4540 return MatchOperand_ParseFail;
4542 Parser.Lex(); // Eat hash token.
4544 const MCExpr *WidthExpr;
4546 if (getParser().parseExpression(WidthExpr, EndLoc)) {
4547 Error(E, "malformed immediate expression");
4548 return MatchOperand_ParseFail;
4550 CE = dyn_cast<MCConstantExpr>(WidthExpr);
4552 Error(E, "'width' operand must be an immediate");
4553 return MatchOperand_ParseFail;
4556 int64_t Width = CE->getValue();
4557 // The LSB must be in the range [1,32-lsb]
4558 if (Width < 1 || Width > 32 - LSB) {
4559 Error(E, "'width' operand must be in the range [1,32-lsb]");
4560 return MatchOperand_ParseFail;
4563 Operands.push_back(ARMOperand::CreateBitfield(LSB, Width, S, EndLoc));
4565 return MatchOperand_Success;
4568 ARMAsmParser::OperandMatchResultTy
4569 ARMAsmParser::parsePostIdxReg(OperandVector &Operands) {
4570 // Check for a post-index addressing register operand. Specifically:
4571 // postidx_reg := '+' register {, shift}
4572 // | '-' register {, shift}
4573 // | register {, shift}
4575 // This method must return MatchOperand_NoMatch without consuming any tokens
4576 // in the case where there is no match, as other alternatives take other
4578 MCAsmParser &Parser = getParser();
4579 AsmToken Tok = Parser.getTok();
4580 SMLoc S = Tok.getLoc();
4581 bool haveEaten = false;
4583 if (Tok.is(AsmToken::Plus)) {
4584 Parser.Lex(); // Eat the '+' token.
4586 } else if (Tok.is(AsmToken::Minus)) {
4587 Parser.Lex(); // Eat the '-' token.
4592 SMLoc E = Parser.getTok().getEndLoc();
4593 int Reg = tryParseRegister();
4596 return MatchOperand_NoMatch;
4597 Error(Parser.getTok().getLoc(), "register expected");
4598 return MatchOperand_ParseFail;
4601 ARM_AM::ShiftOpc ShiftTy = ARM_AM::no_shift;
4602 unsigned ShiftImm = 0;
4603 if (Parser.getTok().is(AsmToken::Comma)) {
4604 Parser.Lex(); // Eat the ','.
4605 if (parseMemRegOffsetShift(ShiftTy, ShiftImm))
4606 return MatchOperand_ParseFail;
4608 // FIXME: Only approximates end...may include intervening whitespace.
4609 E = Parser.getTok().getLoc();
4612 Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ShiftTy,
4615 return MatchOperand_Success;
4618 ARMAsmParser::OperandMatchResultTy
4619 ARMAsmParser::parseAM3Offset(OperandVector &Operands) {
4620 // Check for a post-index addressing register operand. Specifically:
4621 // am3offset := '+' register
4628 // This method must return MatchOperand_NoMatch without consuming any tokens
4629 // in the case where there is no match, as other alternatives take other
4631 MCAsmParser &Parser = getParser();
4632 AsmToken Tok = Parser.getTok();
4633 SMLoc S = Tok.getLoc();
4635 // Do immediates first, as we always parse those if we have a '#'.
4636 if (Parser.getTok().is(AsmToken::Hash) ||
4637 Parser.getTok().is(AsmToken::Dollar)) {
4638 Parser.Lex(); // Eat '#' or '$'.
4639 // Explicitly look for a '-', as we need to encode negative zero
4641 bool isNegative = Parser.getTok().is(AsmToken::Minus);
4642 const MCExpr *Offset;
4644 if (getParser().parseExpression(Offset, E))
4645 return MatchOperand_ParseFail;
4646 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
4648 Error(S, "constant expression expected");
4649 return MatchOperand_ParseFail;
4651 // Negative zero is encoded as the flag value INT32_MIN.
4652 int32_t Val = CE->getValue();
4653 if (isNegative && Val == 0)
4657 ARMOperand::CreateImm(MCConstantExpr::Create(Val, getContext()), S, E));
4659 return MatchOperand_Success;
4663 bool haveEaten = false;
4665 if (Tok.is(AsmToken::Plus)) {
4666 Parser.Lex(); // Eat the '+' token.
4668 } else if (Tok.is(AsmToken::Minus)) {
4669 Parser.Lex(); // Eat the '-' token.
4674 Tok = Parser.getTok();
4675 int Reg = tryParseRegister();
4678 return MatchOperand_NoMatch;
4679 Error(Tok.getLoc(), "register expected");
4680 return MatchOperand_ParseFail;
4683 Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ARM_AM::no_shift,
4684 0, S, Tok.getEndLoc()));
4686 return MatchOperand_Success;
4689 /// Convert parsed operands to MCInst. Needed here because this instruction
4690 /// only has two register operands, but multiplication is commutative so
4691 /// assemblers should accept both "mul rD, rN, rD" and "mul rD, rD, rN".
4692 void ARMAsmParser::cvtThumbMultiply(MCInst &Inst,
4693 const OperandVector &Operands) {
4694 ((ARMOperand &)*Operands[3]).addRegOperands(Inst, 1);
4695 ((ARMOperand &)*Operands[1]).addCCOutOperands(Inst, 1);
4696 // If we have a three-operand form, make sure to set Rn to be the operand
4697 // that isn't the same as Rd.
4699 if (Operands.size() == 6 &&
4700 ((ARMOperand &)*Operands[4]).getReg() ==
4701 ((ARMOperand &)*Operands[3]).getReg())
4703 ((ARMOperand &)*Operands[RegOp]).addRegOperands(Inst, 1);
4704 Inst.addOperand(Inst.getOperand(0));
4705 ((ARMOperand &)*Operands[2]).addCondCodeOperands(Inst, 2);
4708 void ARMAsmParser::cvtThumbBranches(MCInst &Inst,
4709 const OperandVector &Operands) {
4710 int CondOp = -1, ImmOp = -1;
4711 switch(Inst.getOpcode()) {
4713 case ARM::tBcc: CondOp = 1; ImmOp = 2; break;
4716 case ARM::t2Bcc: CondOp = 1; ImmOp = 3; break;
4718 default: llvm_unreachable("Unexpected instruction in cvtThumbBranches");
4720 // first decide whether or not the branch should be conditional
4721 // by looking at it's location relative to an IT block
4723 // inside an IT block we cannot have any conditional branches. any
4724 // such instructions needs to be converted to unconditional form
4725 switch(Inst.getOpcode()) {
4726 case ARM::tBcc: Inst.setOpcode(ARM::tB); break;
4727 case ARM::t2Bcc: Inst.setOpcode(ARM::t2B); break;
4730 // outside IT blocks we can only have unconditional branches with AL
4731 // condition code or conditional branches with non-AL condition code
4732 unsigned Cond = static_cast<ARMOperand &>(*Operands[CondOp]).getCondCode();
4733 switch(Inst.getOpcode()) {
4736 Inst.setOpcode(Cond == ARMCC::AL ? ARM::tB : ARM::tBcc);
4740 Inst.setOpcode(Cond == ARMCC::AL ? ARM::t2B : ARM::t2Bcc);
4745 // now decide on encoding size based on branch target range
4746 switch(Inst.getOpcode()) {
4747 // classify tB as either t2B or t1B based on range of immediate operand
4749 ARMOperand &op = static_cast<ARMOperand &>(*Operands[ImmOp]);
4750 if (!op.isSignedOffset<11, 1>() && isThumbTwo())
4751 Inst.setOpcode(ARM::t2B);
4754 // classify tBcc as either t2Bcc or t1Bcc based on range of immediate operand
4756 ARMOperand &op = static_cast<ARMOperand &>(*Operands[ImmOp]);
4757 if (!op.isSignedOffset<8, 1>() && isThumbTwo())
4758 Inst.setOpcode(ARM::t2Bcc);
4762 ((ARMOperand &)*Operands[ImmOp]).addImmOperands(Inst, 1);
4763 ((ARMOperand &)*Operands[CondOp]).addCondCodeOperands(Inst, 2);
4766 /// Parse an ARM memory expression, return false if successful else return true
4767 /// or an error. The first token must be a '[' when called.
4768 bool ARMAsmParser::parseMemory(OperandVector &Operands) {
4769 MCAsmParser &Parser = getParser();
4771 assert(Parser.getTok().is(AsmToken::LBrac) &&
4772 "Token is not a Left Bracket");
4773 S = Parser.getTok().getLoc();
4774 Parser.Lex(); // Eat left bracket token.
4776 const AsmToken &BaseRegTok = Parser.getTok();
4777 int BaseRegNum = tryParseRegister();
4778 if (BaseRegNum == -1)
4779 return Error(BaseRegTok.getLoc(), "register expected");
4781 // The next token must either be a comma, a colon or a closing bracket.
4782 const AsmToken &Tok = Parser.getTok();
4783 if (!Tok.is(AsmToken::Colon) && !Tok.is(AsmToken::Comma) &&
4784 !Tok.is(AsmToken::RBrac))
4785 return Error(Tok.getLoc(), "malformed memory operand");
4787 if (Tok.is(AsmToken::RBrac)) {
4788 E = Tok.getEndLoc();
4789 Parser.Lex(); // Eat right bracket token.
4791 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, nullptr, 0,
4792 ARM_AM::no_shift, 0, 0, false,
4795 // If there's a pre-indexing writeback marker, '!', just add it as a token
4796 // operand. It's rather odd, but syntactically valid.
4797 if (Parser.getTok().is(AsmToken::Exclaim)) {
4798 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4799 Parser.Lex(); // Eat the '!'.
4805 assert((Tok.is(AsmToken::Colon) || Tok.is(AsmToken::Comma)) &&
4806 "Lost colon or comma in memory operand?!");
4807 if (Tok.is(AsmToken::Comma)) {
4808 Parser.Lex(); // Eat the comma.
4811 // If we have a ':', it's an alignment specifier.
4812 if (Parser.getTok().is(AsmToken::Colon)) {
4813 Parser.Lex(); // Eat the ':'.
4814 E = Parser.getTok().getLoc();
4815 SMLoc AlignmentLoc = Tok.getLoc();
4818 if (getParser().parseExpression(Expr))
4821 // The expression has to be a constant. Memory references with relocations
4822 // don't come through here, as they use the <label> forms of the relevant
4824 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
4826 return Error (E, "constant expression expected");
4829 switch (CE->getValue()) {
4832 "alignment specifier must be 16, 32, 64, 128, or 256 bits");
4833 case 16: Align = 2; break;
4834 case 32: Align = 4; break;
4835 case 64: Align = 8; break;
4836 case 128: Align = 16; break;
4837 case 256: Align = 32; break;
4840 // Now we should have the closing ']'
4841 if (Parser.getTok().isNot(AsmToken::RBrac))
4842 return Error(Parser.getTok().getLoc(), "']' expected");
4843 E = Parser.getTok().getEndLoc();
4844 Parser.Lex(); // Eat right bracket token.
4846 // Don't worry about range checking the value here. That's handled by
4847 // the is*() predicates.
4848 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, nullptr, 0,
4849 ARM_AM::no_shift, 0, Align,
4850 false, S, E, AlignmentLoc));
4852 // If there's a pre-indexing writeback marker, '!', just add it as a token
4854 if (Parser.getTok().is(AsmToken::Exclaim)) {
4855 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4856 Parser.Lex(); // Eat the '!'.
4862 // If we have a '#', it's an immediate offset, else assume it's a register
4863 // offset. Be friendly and also accept a plain integer (without a leading
4864 // hash) for gas compatibility.
4865 if (Parser.getTok().is(AsmToken::Hash) ||
4866 Parser.getTok().is(AsmToken::Dollar) ||
4867 Parser.getTok().is(AsmToken::Integer)) {
4868 if (Parser.getTok().isNot(AsmToken::Integer))
4869 Parser.Lex(); // Eat '#' or '$'.
4870 E = Parser.getTok().getLoc();
4872 bool isNegative = getParser().getTok().is(AsmToken::Minus);
4873 const MCExpr *Offset;
4874 if (getParser().parseExpression(Offset))
4877 // The expression has to be a constant. Memory references with relocations
4878 // don't come through here, as they use the <label> forms of the relevant
4880 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
4882 return Error (E, "constant expression expected");
4884 // If the constant was #-0, represent it as INT32_MIN.
4885 int32_t Val = CE->getValue();
4886 if (isNegative && Val == 0)
4887 CE = MCConstantExpr::Create(INT32_MIN, getContext());
4889 // Now we should have the closing ']'
4890 if (Parser.getTok().isNot(AsmToken::RBrac))
4891 return Error(Parser.getTok().getLoc(), "']' expected");
4892 E = Parser.getTok().getEndLoc();
4893 Parser.Lex(); // Eat right bracket token.
4895 // Don't worry about range checking the value here. That's handled by
4896 // the is*() predicates.
4897 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, CE, 0,
4898 ARM_AM::no_shift, 0, 0,
4901 // If there's a pre-indexing writeback marker, '!', just add it as a token
4903 if (Parser.getTok().is(AsmToken::Exclaim)) {
4904 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4905 Parser.Lex(); // Eat the '!'.
4911 // The register offset is optionally preceded by a '+' or '-'
4912 bool isNegative = false;
4913 if (Parser.getTok().is(AsmToken::Minus)) {
4915 Parser.Lex(); // Eat the '-'.
4916 } else if (Parser.getTok().is(AsmToken::Plus)) {
4918 Parser.Lex(); // Eat the '+'.
4921 E = Parser.getTok().getLoc();
4922 int OffsetRegNum = tryParseRegister();
4923 if (OffsetRegNum == -1)
4924 return Error(E, "register expected");
4926 // If there's a shift operator, handle it.
4927 ARM_AM::ShiftOpc ShiftType = ARM_AM::no_shift;
4928 unsigned ShiftImm = 0;
4929 if (Parser.getTok().is(AsmToken::Comma)) {
4930 Parser.Lex(); // Eat the ','.
4931 if (parseMemRegOffsetShift(ShiftType, ShiftImm))
4935 // Now we should have the closing ']'
4936 if (Parser.getTok().isNot(AsmToken::RBrac))
4937 return Error(Parser.getTok().getLoc(), "']' expected");
4938 E = Parser.getTok().getEndLoc();
4939 Parser.Lex(); // Eat right bracket token.
4941 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, nullptr, OffsetRegNum,
4942 ShiftType, ShiftImm, 0, isNegative,
4945 // If there's a pre-indexing writeback marker, '!', just add it as a token
4947 if (Parser.getTok().is(AsmToken::Exclaim)) {
4948 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4949 Parser.Lex(); // Eat the '!'.
4955 /// parseMemRegOffsetShift - one of these two:
4956 /// ( lsl | lsr | asr | ror ) , # shift_amount
4958 /// return true if it parses a shift otherwise it returns false.
4959 bool ARMAsmParser::parseMemRegOffsetShift(ARM_AM::ShiftOpc &St,
4961 MCAsmParser &Parser = getParser();
4962 SMLoc Loc = Parser.getTok().getLoc();
4963 const AsmToken &Tok = Parser.getTok();
4964 if (Tok.isNot(AsmToken::Identifier))
4966 StringRef ShiftName = Tok.getString();
4967 if (ShiftName == "lsl" || ShiftName == "LSL" ||
4968 ShiftName == "asl" || ShiftName == "ASL")
4970 else if (ShiftName == "lsr" || ShiftName == "LSR")
4972 else if (ShiftName == "asr" || ShiftName == "ASR")
4974 else if (ShiftName == "ror" || ShiftName == "ROR")
4976 else if (ShiftName == "rrx" || ShiftName == "RRX")
4979 return Error(Loc, "illegal shift operator");
4980 Parser.Lex(); // Eat shift type token.
4982 // rrx stands alone.
4984 if (St != ARM_AM::rrx) {
4985 Loc = Parser.getTok().getLoc();
4986 // A '#' and a shift amount.
4987 const AsmToken &HashTok = Parser.getTok();
4988 if (HashTok.isNot(AsmToken::Hash) &&
4989 HashTok.isNot(AsmToken::Dollar))
4990 return Error(HashTok.getLoc(), "'#' expected");
4991 Parser.Lex(); // Eat hash token.
4994 if (getParser().parseExpression(Expr))
4996 // Range check the immediate.
4997 // lsl, ror: 0 <= imm <= 31
4998 // lsr, asr: 0 <= imm <= 32
4999 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
5001 return Error(Loc, "shift amount must be an immediate");
5002 int64_t Imm = CE->getValue();
5004 ((St == ARM_AM::lsl || St == ARM_AM::ror) && Imm > 31) ||
5005 ((St == ARM_AM::lsr || St == ARM_AM::asr) && Imm > 32))
5006 return Error(Loc, "immediate shift value out of range");
5007 // If <ShiftTy> #0, turn it into a no_shift.
5010 // For consistency, treat lsr #32 and asr #32 as having immediate value 0.
5019 /// parseFPImm - A floating point immediate expression operand.
5020 ARMAsmParser::OperandMatchResultTy
5021 ARMAsmParser::parseFPImm(OperandVector &Operands) {
5022 MCAsmParser &Parser = getParser();
5023 // Anything that can accept a floating point constant as an operand
5024 // needs to go through here, as the regular parseExpression is
5027 // This routine still creates a generic Immediate operand, containing
5028 // a bitcast of the 64-bit floating point value. The various operands
5029 // that accept floats can check whether the value is valid for them
5030 // via the standard is*() predicates.
5032 SMLoc S = Parser.getTok().getLoc();
5034 if (Parser.getTok().isNot(AsmToken::Hash) &&
5035 Parser.getTok().isNot(AsmToken::Dollar))
5036 return MatchOperand_NoMatch;
5038 // Disambiguate the VMOV forms that can accept an FP immediate.
5039 // vmov.f32 <sreg>, #imm
5040 // vmov.f64 <dreg>, #imm
5041 // vmov.f32 <dreg>, #imm @ vector f32x2
5042 // vmov.f32 <qreg>, #imm @ vector f32x4
5044 // There are also the NEON VMOV instructions which expect an
5045 // integer constant. Make sure we don't try to parse an FPImm
5047 // vmov.i{8|16|32|64} <dreg|qreg>, #imm
5048 ARMOperand &TyOp = static_cast<ARMOperand &>(*Operands[2]);
5049 bool isVmovf = TyOp.isToken() &&
5050 (TyOp.getToken() == ".f32" || TyOp.getToken() == ".f64");
5051 ARMOperand &Mnemonic = static_cast<ARMOperand &>(*Operands[0]);
5052 bool isFconst = Mnemonic.isToken() && (Mnemonic.getToken() == "fconstd" ||
5053 Mnemonic.getToken() == "fconsts");
5054 if (!(isVmovf || isFconst))
5055 return MatchOperand_NoMatch;
5057 Parser.Lex(); // Eat '#' or '$'.
5059 // Handle negation, as that still comes through as a separate token.
5060 bool isNegative = false;
5061 if (Parser.getTok().is(AsmToken::Minus)) {
5065 const AsmToken &Tok = Parser.getTok();
5066 SMLoc Loc = Tok.getLoc();
5067 if (Tok.is(AsmToken::Real) && isVmovf) {
5068 APFloat RealVal(APFloat::IEEEsingle, Tok.getString());
5069 uint64_t IntVal = RealVal.bitcastToAPInt().getZExtValue();
5070 // If we had a '-' in front, toggle the sign bit.
5071 IntVal ^= (uint64_t)isNegative << 31;
5072 Parser.Lex(); // Eat the token.
5073 Operands.push_back(ARMOperand::CreateImm(
5074 MCConstantExpr::Create(IntVal, getContext()),
5075 S, Parser.getTok().getLoc()));
5076 return MatchOperand_Success;
5078 // Also handle plain integers. Instructions which allow floating point
5079 // immediates also allow a raw encoded 8-bit value.
5080 if (Tok.is(AsmToken::Integer) && isFconst) {
5081 int64_t Val = Tok.getIntVal();
5082 Parser.Lex(); // Eat the token.
5083 if (Val > 255 || Val < 0) {
5084 Error(Loc, "encoded floating point value out of range");
5085 return MatchOperand_ParseFail;
5087 float RealVal = ARM_AM::getFPImmFloat(Val);
5088 Val = APFloat(RealVal).bitcastToAPInt().getZExtValue();
5090 Operands.push_back(ARMOperand::CreateImm(
5091 MCConstantExpr::Create(Val, getContext()), S,
5092 Parser.getTok().getLoc()));
5093 return MatchOperand_Success;
5096 Error(Loc, "invalid floating point immediate");
5097 return MatchOperand_ParseFail;
5100 /// Parse a arm instruction operand. For now this parses the operand regardless
5101 /// of the mnemonic.
5102 bool ARMAsmParser::parseOperand(OperandVector &Operands, StringRef Mnemonic) {
5103 MCAsmParser &Parser = getParser();
5106 // Check if the current operand has a custom associated parser, if so, try to
5107 // custom parse the operand, or fallback to the general approach.
5108 OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
5109 if (ResTy == MatchOperand_Success)
5111 // If there wasn't a custom match, try the generic matcher below. Otherwise,
5112 // there was a match, but an error occurred, in which case, just return that
5113 // the operand parsing failed.
5114 if (ResTy == MatchOperand_ParseFail)
5117 switch (getLexer().getKind()) {
5119 Error(Parser.getTok().getLoc(), "unexpected token in operand");
5121 case AsmToken::Identifier: {
5122 // If we've seen a branch mnemonic, the next operand must be a label. This
5123 // is true even if the label is a register name. So "br r1" means branch to
5125 bool ExpectLabel = Mnemonic == "b" || Mnemonic == "bl";
5127 if (!tryParseRegisterWithWriteBack(Operands))
5129 int Res = tryParseShiftRegister(Operands);
5130 if (Res == 0) // success
5132 else if (Res == -1) // irrecoverable error
5134 // If this is VMRS, check for the apsr_nzcv operand.
5135 if (Mnemonic == "vmrs" &&
5136 Parser.getTok().getString().equals_lower("apsr_nzcv")) {
5137 S = Parser.getTok().getLoc();
5139 Operands.push_back(ARMOperand::CreateToken("APSR_nzcv", S));
5144 // Fall though for the Identifier case that is not a register or a
5147 case AsmToken::LParen: // parenthesized expressions like (_strcmp-4)
5148 case AsmToken::Integer: // things like 1f and 2b as a branch targets
5149 case AsmToken::String: // quoted label names.
5150 case AsmToken::Dot: { // . as a branch target
5151 // This was not a register so parse other operands that start with an
5152 // identifier (like labels) as expressions and create them as immediates.
5153 const MCExpr *IdVal;
5154 S = Parser.getTok().getLoc();
5155 if (getParser().parseExpression(IdVal))
5157 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
5158 Operands.push_back(ARMOperand::CreateImm(IdVal, S, E));
5161 case AsmToken::LBrac:
5162 return parseMemory(Operands);
5163 case AsmToken::LCurly:
5164 return parseRegisterList(Operands);
5165 case AsmToken::Dollar:
5166 case AsmToken::Hash: {
5167 // #42 -> immediate.
5168 S = Parser.getTok().getLoc();
5171 if (Parser.getTok().isNot(AsmToken::Colon)) {
5172 bool isNegative = Parser.getTok().is(AsmToken::Minus);
5173 const MCExpr *ImmVal;
5174 if (getParser().parseExpression(ImmVal))
5176 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ImmVal);
5178 int32_t Val = CE->getValue();
5179 if (isNegative && Val == 0)
5180 ImmVal = MCConstantExpr::Create(INT32_MIN, getContext());
5182 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
5183 Operands.push_back(ARMOperand::CreateImm(ImmVal, S, E));
5185 // There can be a trailing '!' on operands that we want as a separate
5186 // '!' Token operand. Handle that here. For example, the compatibility
5187 // alias for 'srsdb sp!, #imm' is 'srsdb #imm!'.
5188 if (Parser.getTok().is(AsmToken::Exclaim)) {
5189 Operands.push_back(ARMOperand::CreateToken(Parser.getTok().getString(),
5190 Parser.getTok().getLoc()));
5191 Parser.Lex(); // Eat exclaim token
5195 // w/ a ':' after the '#', it's just like a plain ':'.
5198 case AsmToken::Colon: {
5199 // ":lower16:" and ":upper16:" expression prefixes
5200 // FIXME: Check it's an expression prefix,
5201 // e.g. (FOO - :lower16:BAR) isn't legal.
5202 ARMMCExpr::VariantKind RefKind;
5203 if (parsePrefix(RefKind))
5206 const MCExpr *SubExprVal;
5207 if (getParser().parseExpression(SubExprVal))
5210 const MCExpr *ExprVal = ARMMCExpr::Create(RefKind, SubExprVal,
5212 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
5213 Operands.push_back(ARMOperand::CreateImm(ExprVal, S, E));
5216 case AsmToken::Equal: {
5217 if (Mnemonic != "ldr") // only parse for ldr pseudo (e.g. ldr r0, =val)
5218 return Error(Parser.getTok().getLoc(), "unexpected token in operand");
5220 Parser.Lex(); // Eat '='
5221 const MCExpr *SubExprVal;
5222 if (getParser().parseExpression(SubExprVal))
5224 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
5226 const MCExpr *CPLoc = getTargetStreamer().addConstantPoolEntry(SubExprVal);
5227 Operands.push_back(ARMOperand::CreateImm(CPLoc, S, E));
5233 // parsePrefix - Parse ARM 16-bit relocations expression prefix, i.e.
5234 // :lower16: and :upper16:.
5235 bool ARMAsmParser::parsePrefix(ARMMCExpr::VariantKind &RefKind) {
5236 MCAsmParser &Parser = getParser();
5237 RefKind = ARMMCExpr::VK_ARM_None;
5239 // consume an optional '#' (GNU compatibility)
5240 if (getLexer().is(AsmToken::Hash))
5243 // :lower16: and :upper16: modifiers
5244 assert(getLexer().is(AsmToken::Colon) && "expected a :");
5245 Parser.Lex(); // Eat ':'
5247 if (getLexer().isNot(AsmToken::Identifier)) {
5248 Error(Parser.getTok().getLoc(), "expected prefix identifier in operand");
5253 COFF = (1 << MCObjectFileInfo::IsCOFF),
5254 ELF = (1 << MCObjectFileInfo::IsELF),
5255 MACHO = (1 << MCObjectFileInfo::IsMachO)
5257 static const struct PrefixEntry {
5258 const char *Spelling;
5259 ARMMCExpr::VariantKind VariantKind;
5260 uint8_t SupportedFormats;
5261 } PrefixEntries[] = {
5262 { "lower16", ARMMCExpr::VK_ARM_LO16, COFF | ELF | MACHO },
5263 { "upper16", ARMMCExpr::VK_ARM_HI16, COFF | ELF | MACHO },
5266 StringRef IDVal = Parser.getTok().getIdentifier();
5268 const auto &Prefix =
5269 std::find_if(std::begin(PrefixEntries), std::end(PrefixEntries),
5270 [&IDVal](const PrefixEntry &PE) {
5271 return PE.Spelling == IDVal;
5273 if (Prefix == std::end(PrefixEntries)) {
5274 Error(Parser.getTok().getLoc(), "unexpected prefix in operand");
5278 uint8_t CurrentFormat;
5279 switch (getContext().getObjectFileInfo()->getObjectFileType()) {
5280 case MCObjectFileInfo::IsMachO:
5281 CurrentFormat = MACHO;
5283 case MCObjectFileInfo::IsELF:
5284 CurrentFormat = ELF;
5286 case MCObjectFileInfo::IsCOFF:
5287 CurrentFormat = COFF;
5291 if (~Prefix->SupportedFormats & CurrentFormat) {
5292 Error(Parser.getTok().getLoc(),
5293 "cannot represent relocation in the current file format");
5297 RefKind = Prefix->VariantKind;
5300 if (getLexer().isNot(AsmToken::Colon)) {
5301 Error(Parser.getTok().getLoc(), "unexpected token after prefix");
5304 Parser.Lex(); // Eat the last ':'
5309 /// \brief Given a mnemonic, split out possible predication code and carry
5310 /// setting letters to form a canonical mnemonic and flags.
5312 // FIXME: Would be nice to autogen this.
5313 // FIXME: This is a bit of a maze of special cases.
5314 StringRef ARMAsmParser::splitMnemonic(StringRef Mnemonic,
5315 unsigned &PredicationCode,
5317 unsigned &ProcessorIMod,
5318 StringRef &ITMask) {
5319 PredicationCode = ARMCC::AL;
5320 CarrySetting = false;
5323 // Ignore some mnemonics we know aren't predicated forms.
5325 // FIXME: Would be nice to autogen this.
5326 if ((Mnemonic == "movs" && isThumb()) ||
5327 Mnemonic == "teq" || Mnemonic == "vceq" || Mnemonic == "svc" ||
5328 Mnemonic == "mls" || Mnemonic == "smmls" || Mnemonic == "vcls" ||
5329 Mnemonic == "vmls" || Mnemonic == "vnmls" || Mnemonic == "vacge" ||
5330 Mnemonic == "vcge" || Mnemonic == "vclt" || Mnemonic == "vacgt" ||
5331 Mnemonic == "vaclt" || Mnemonic == "vacle" || Mnemonic == "hlt" ||
5332 Mnemonic == "vcgt" || Mnemonic == "vcle" || Mnemonic == "smlal" ||
5333 Mnemonic == "umaal" || Mnemonic == "umlal" || Mnemonic == "vabal" ||
5334 Mnemonic == "vmlal" || Mnemonic == "vpadal" || Mnemonic == "vqdmlal" ||
5335 Mnemonic == "fmuls" || Mnemonic == "vmaxnm" || Mnemonic == "vminnm" ||
5336 Mnemonic == "vcvta" || Mnemonic == "vcvtn" || Mnemonic == "vcvtp" ||
5337 Mnemonic == "vcvtm" || Mnemonic == "vrinta" || Mnemonic == "vrintn" ||
5338 Mnemonic == "vrintp" || Mnemonic == "vrintm" || Mnemonic == "hvc" ||
5339 Mnemonic.startswith("vsel"))
5342 // First, split out any predication code. Ignore mnemonics we know aren't
5343 // predicated but do have a carry-set and so weren't caught above.
5344 if (Mnemonic != "adcs" && Mnemonic != "bics" && Mnemonic != "movs" &&
5345 Mnemonic != "muls" && Mnemonic != "smlals" && Mnemonic != "smulls" &&
5346 Mnemonic != "umlals" && Mnemonic != "umulls" && Mnemonic != "lsls" &&
5347 Mnemonic != "sbcs" && Mnemonic != "rscs") {
5348 unsigned CC = StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2))
5349 .Case("eq", ARMCC::EQ)
5350 .Case("ne", ARMCC::NE)
5351 .Case("hs", ARMCC::HS)
5352 .Case("cs", ARMCC::HS)
5353 .Case("lo", ARMCC::LO)
5354 .Case("cc", ARMCC::LO)
5355 .Case("mi", ARMCC::MI)
5356 .Case("pl", ARMCC::PL)
5357 .Case("vs", ARMCC::VS)
5358 .Case("vc", ARMCC::VC)
5359 .Case("hi", ARMCC::HI)
5360 .Case("ls", ARMCC::LS)
5361 .Case("ge", ARMCC::GE)
5362 .Case("lt", ARMCC::LT)
5363 .Case("gt", ARMCC::GT)
5364 .Case("le", ARMCC::LE)
5365 .Case("al", ARMCC::AL)
5368 Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 2);
5369 PredicationCode = CC;
5373 // Next, determine if we have a carry setting bit. We explicitly ignore all
5374 // the instructions we know end in 's'.
5375 if (Mnemonic.endswith("s") &&
5376 !(Mnemonic == "cps" || Mnemonic == "mls" ||
5377 Mnemonic == "mrs" || Mnemonic == "smmls" || Mnemonic == "vabs" ||
5378 Mnemonic == "vcls" || Mnemonic == "vmls" || Mnemonic == "vmrs" ||
5379 Mnemonic == "vnmls" || Mnemonic == "vqabs" || Mnemonic == "vrecps" ||
5380 Mnemonic == "vrsqrts" || Mnemonic == "srs" || Mnemonic == "flds" ||
5381 Mnemonic == "fmrs" || Mnemonic == "fsqrts" || Mnemonic == "fsubs" ||
5382 Mnemonic == "fsts" || Mnemonic == "fcpys" || Mnemonic == "fdivs" ||
5383 Mnemonic == "fmuls" || Mnemonic == "fcmps" || Mnemonic == "fcmpzs" ||
5384 Mnemonic == "vfms" || Mnemonic == "vfnms" || Mnemonic == "fconsts" ||
5385 (Mnemonic == "movs" && isThumb()))) {
5386 Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 1);
5387 CarrySetting = true;
5390 // The "cps" instruction can have a interrupt mode operand which is glued into
5391 // the mnemonic. Check if this is the case, split it and parse the imod op
5392 if (Mnemonic.startswith("cps")) {
5393 // Split out any imod code.
5395 StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2, 2))
5396 .Case("ie", ARM_PROC::IE)
5397 .Case("id", ARM_PROC::ID)
5400 Mnemonic = Mnemonic.slice(0, Mnemonic.size()-2);
5401 ProcessorIMod = IMod;
5405 // The "it" instruction has the condition mask on the end of the mnemonic.
5406 if (Mnemonic.startswith("it")) {
5407 ITMask = Mnemonic.slice(2, Mnemonic.size());
5408 Mnemonic = Mnemonic.slice(0, 2);
5414 /// \brief Given a canonical mnemonic, determine if the instruction ever allows
5415 /// inclusion of carry set or predication code operands.
5417 // FIXME: It would be nice to autogen this.
5419 getMnemonicAcceptInfo(StringRef Mnemonic, StringRef FullInst,
5420 bool &CanAcceptCarrySet, bool &CanAcceptPredicationCode) {
5421 if (Mnemonic == "and" || Mnemonic == "lsl" || Mnemonic == "lsr" ||
5422 Mnemonic == "rrx" || Mnemonic == "ror" || Mnemonic == "sub" ||
5423 Mnemonic == "add" || Mnemonic == "adc" ||
5424 Mnemonic == "mul" || Mnemonic == "bic" || Mnemonic == "asr" ||
5425 Mnemonic == "orr" || Mnemonic == "mvn" ||
5426 Mnemonic == "rsb" || Mnemonic == "rsc" || Mnemonic == "orn" ||
5427 Mnemonic == "sbc" || Mnemonic == "eor" || Mnemonic == "neg" ||
5428 Mnemonic == "vfm" || Mnemonic == "vfnm" ||
5429 (!isThumb() && (Mnemonic == "smull" || Mnemonic == "mov" ||
5430 Mnemonic == "mla" || Mnemonic == "smlal" ||
5431 Mnemonic == "umlal" || Mnemonic == "umull"))) {
5432 CanAcceptCarrySet = true;
5434 CanAcceptCarrySet = false;
5436 if (Mnemonic == "bkpt" || Mnemonic == "cbnz" || Mnemonic == "setend" ||
5437 Mnemonic == "cps" || Mnemonic == "it" || Mnemonic == "cbz" ||
5438 Mnemonic == "trap" || Mnemonic == "hlt" || Mnemonic == "udf" ||
5439 Mnemonic.startswith("crc32") || Mnemonic.startswith("cps") ||
5440 Mnemonic.startswith("vsel") ||
5441 Mnemonic == "vmaxnm" || Mnemonic == "vminnm" || Mnemonic == "vcvta" ||
5442 Mnemonic == "vcvtn" || Mnemonic == "vcvtp" || Mnemonic == "vcvtm" ||
5443 Mnemonic == "vrinta" || Mnemonic == "vrintn" || Mnemonic == "vrintp" ||
5444 Mnemonic == "vrintm" || Mnemonic.startswith("aes") || Mnemonic == "hvc" ||
5445 Mnemonic.startswith("sha1") || Mnemonic.startswith("sha256") ||
5446 (FullInst.startswith("vmull") && FullInst.endswith(".p64"))) {
5447 // These mnemonics are never predicable
5448 CanAcceptPredicationCode = false;
5449 } else if (!isThumb()) {
5450 // Some instructions are only predicable in Thumb mode
5451 CanAcceptPredicationCode
5452 = Mnemonic != "cdp2" && Mnemonic != "clrex" && Mnemonic != "mcr2" &&
5453 Mnemonic != "mcrr2" && Mnemonic != "mrc2" && Mnemonic != "mrrc2" &&
5454 Mnemonic != "dmb" && Mnemonic != "dsb" && Mnemonic != "isb" &&
5455 Mnemonic != "pld" && Mnemonic != "pli" && Mnemonic != "pldw" &&
5456 Mnemonic != "ldc2" && Mnemonic != "ldc2l" &&
5457 Mnemonic != "stc2" && Mnemonic != "stc2l" &&
5458 !Mnemonic.startswith("rfe") && !Mnemonic.startswith("srs");
5459 } else if (isThumbOne()) {
5461 CanAcceptPredicationCode = Mnemonic != "movs";
5463 CanAcceptPredicationCode = Mnemonic != "nop" && Mnemonic != "movs";
5465 CanAcceptPredicationCode = true;
5468 bool ARMAsmParser::shouldOmitCCOutOperand(StringRef Mnemonic,
5469 OperandVector &Operands) {
5470 // FIXME: This is all horribly hacky. We really need a better way to deal
5471 // with optional operands like this in the matcher table.
5473 // The 'mov' mnemonic is special. One variant has a cc_out operand, while
5474 // another does not. Specifically, the MOVW instruction does not. So we
5475 // special case it here and remove the defaulted (non-setting) cc_out
5476 // operand if that's the instruction we're trying to match.
5478 // We do this as post-processing of the explicit operands rather than just
5479 // conditionally adding the cc_out in the first place because we need
5480 // to check the type of the parsed immediate operand.
5481 if (Mnemonic == "mov" && Operands.size() > 4 && !isThumb() &&
5482 !static_cast<ARMOperand &>(*Operands[4]).isModImm() &&
5483 static_cast<ARMOperand &>(*Operands[4]).isImm0_65535Expr() &&
5484 static_cast<ARMOperand &>(*Operands[1]).getReg() == 0)
5487 // Register-register 'add' for thumb does not have a cc_out operand
5488 // when there are only two register operands.
5489 if (isThumb() && Mnemonic == "add" && Operands.size() == 5 &&
5490 static_cast<ARMOperand &>(*Operands[3]).isReg() &&
5491 static_cast<ARMOperand &>(*Operands[4]).isReg() &&
5492 static_cast<ARMOperand &>(*Operands[1]).getReg() == 0)
5494 // Register-register 'add' for thumb does not have a cc_out operand
5495 // when it's an ADD Rdm, SP, {Rdm|#imm0_255} instruction. We do
5496 // have to check the immediate range here since Thumb2 has a variant
5497 // that can handle a different range and has a cc_out operand.
5498 if (((isThumb() && Mnemonic == "add") ||
5499 (isThumbTwo() && Mnemonic == "sub")) &&
5500 Operands.size() == 6 && static_cast<ARMOperand &>(*Operands[3]).isReg() &&
5501 static_cast<ARMOperand &>(*Operands[4]).isReg() &&
5502 static_cast<ARMOperand &>(*Operands[4]).getReg() == ARM::SP &&
5503 static_cast<ARMOperand &>(*Operands[1]).getReg() == 0 &&
5504 ((Mnemonic == "add" && static_cast<ARMOperand &>(*Operands[5]).isReg()) ||
5505 static_cast<ARMOperand &>(*Operands[5]).isImm0_1020s4()))
5507 // For Thumb2, add/sub immediate does not have a cc_out operand for the
5508 // imm0_4095 variant. That's the least-preferred variant when
5509 // selecting via the generic "add" mnemonic, so to know that we
5510 // should remove the cc_out operand, we have to explicitly check that
5511 // it's not one of the other variants. Ugh.
5512 if (isThumbTwo() && (Mnemonic == "add" || Mnemonic == "sub") &&
5513 Operands.size() == 6 && static_cast<ARMOperand &>(*Operands[3]).isReg() &&
5514 static_cast<ARMOperand &>(*Operands[4]).isReg() &&
5515 static_cast<ARMOperand &>(*Operands[5]).isImm()) {
5516 // Nest conditions rather than one big 'if' statement for readability.
5518 // If both registers are low, we're in an IT block, and the immediate is
5519 // in range, we should use encoding T1 instead, which has a cc_out.
5521 isARMLowRegister(static_cast<ARMOperand &>(*Operands[3]).getReg()) &&
5522 isARMLowRegister(static_cast<ARMOperand &>(*Operands[4]).getReg()) &&
5523 static_cast<ARMOperand &>(*Operands[5]).isImm0_7())
5525 // Check against T3. If the second register is the PC, this is an
5526 // alternate form of ADR, which uses encoding T4, so check for that too.
5527 if (static_cast<ARMOperand &>(*Operands[4]).getReg() != ARM::PC &&
5528 static_cast<ARMOperand &>(*Operands[5]).isT2SOImm())
5531 // Otherwise, we use encoding T4, which does not have a cc_out
5536 // The thumb2 multiply instruction doesn't have a CCOut register, so
5537 // if we have a "mul" mnemonic in Thumb mode, check if we'll be able to
5538 // use the 16-bit encoding or not.
5539 if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 6 &&
5540 static_cast<ARMOperand &>(*Operands[1]).getReg() == 0 &&
5541 static_cast<ARMOperand &>(*Operands[3]).isReg() &&
5542 static_cast<ARMOperand &>(*Operands[4]).isReg() &&
5543 static_cast<ARMOperand &>(*Operands[5]).isReg() &&
5544 // If the registers aren't low regs, the destination reg isn't the
5545 // same as one of the source regs, or the cc_out operand is zero
5546 // outside of an IT block, we have to use the 32-bit encoding, so
5547 // remove the cc_out operand.
5548 (!isARMLowRegister(static_cast<ARMOperand &>(*Operands[3]).getReg()) ||
5549 !isARMLowRegister(static_cast<ARMOperand &>(*Operands[4]).getReg()) ||
5550 !isARMLowRegister(static_cast<ARMOperand &>(*Operands[5]).getReg()) ||
5551 !inITBlock() || (static_cast<ARMOperand &>(*Operands[3]).getReg() !=
5552 static_cast<ARMOperand &>(*Operands[5]).getReg() &&
5553 static_cast<ARMOperand &>(*Operands[3]).getReg() !=
5554 static_cast<ARMOperand &>(*Operands[4]).getReg())))
5557 // Also check the 'mul' syntax variant that doesn't specify an explicit
5558 // destination register.
5559 if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 5 &&
5560 static_cast<ARMOperand &>(*Operands[1]).getReg() == 0 &&
5561 static_cast<ARMOperand &>(*Operands[3]).isReg() &&
5562 static_cast<ARMOperand &>(*Operands[4]).isReg() &&
5563 // If the registers aren't low regs or the cc_out operand is zero
5564 // outside of an IT block, we have to use the 32-bit encoding, so
5565 // remove the cc_out operand.
5566 (!isARMLowRegister(static_cast<ARMOperand &>(*Operands[3]).getReg()) ||
5567 !isARMLowRegister(static_cast<ARMOperand &>(*Operands[4]).getReg()) ||
5573 // Register-register 'add/sub' for thumb does not have a cc_out operand
5574 // when it's an ADD/SUB SP, #imm. Be lenient on count since there's also
5575 // the "add/sub SP, SP, #imm" version. If the follow-up operands aren't
5576 // right, this will result in better diagnostics (which operand is off)
5578 if (isThumb() && (Mnemonic == "add" || Mnemonic == "sub") &&
5579 (Operands.size() == 5 || Operands.size() == 6) &&
5580 static_cast<ARMOperand &>(*Operands[3]).isReg() &&
5581 static_cast<ARMOperand &>(*Operands[3]).getReg() == ARM::SP &&
5582 static_cast<ARMOperand &>(*Operands[1]).getReg() == 0 &&
5583 (static_cast<ARMOperand &>(*Operands[4]).isImm() ||
5584 (Operands.size() == 6 &&
5585 static_cast<ARMOperand &>(*Operands[5]).isImm())))
5591 bool ARMAsmParser::shouldOmitPredicateOperand(StringRef Mnemonic,
5592 OperandVector &Operands) {
5593 // VRINT{Z, R, X} have a predicate operand in VFP, but not in NEON
5594 unsigned RegIdx = 3;
5595 if ((Mnemonic == "vrintz" || Mnemonic == "vrintx" || Mnemonic == "vrintr") &&
5596 static_cast<ARMOperand &>(*Operands[2]).getToken() == ".f32") {
5597 if (static_cast<ARMOperand &>(*Operands[3]).isToken() &&
5598 static_cast<ARMOperand &>(*Operands[3]).getToken() == ".f32")
5601 if (static_cast<ARMOperand &>(*Operands[RegIdx]).isReg() &&
5602 (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(
5603 static_cast<ARMOperand &>(*Operands[RegIdx]).getReg()) ||
5604 ARMMCRegisterClasses[ARM::QPRRegClassID].contains(
5605 static_cast<ARMOperand &>(*Operands[RegIdx]).getReg())))
5611 static bool isDataTypeToken(StringRef Tok) {
5612 return Tok == ".8" || Tok == ".16" || Tok == ".32" || Tok == ".64" ||
5613 Tok == ".i8" || Tok == ".i16" || Tok == ".i32" || Tok == ".i64" ||
5614 Tok == ".u8" || Tok == ".u16" || Tok == ".u32" || Tok == ".u64" ||
5615 Tok == ".s8" || Tok == ".s16" || Tok == ".s32" || Tok == ".s64" ||
5616 Tok == ".p8" || Tok == ".p16" || Tok == ".f32" || Tok == ".f64" ||
5617 Tok == ".f" || Tok == ".d";
5620 // FIXME: This bit should probably be handled via an explicit match class
5621 // in the .td files that matches the suffix instead of having it be
5622 // a literal string token the way it is now.
5623 static bool doesIgnoreDataTypeSuffix(StringRef Mnemonic, StringRef DT) {
5624 return Mnemonic.startswith("vldm") || Mnemonic.startswith("vstm");
5626 static void applyMnemonicAliases(StringRef &Mnemonic, uint64_t Features,
5627 unsigned VariantID);
5629 static bool RequiresVFPRegListValidation(StringRef Inst,
5630 bool &AcceptSinglePrecisionOnly,
5631 bool &AcceptDoublePrecisionOnly) {
5632 if (Inst.size() < 7)
5635 if (Inst.startswith("fldm") || Inst.startswith("fstm")) {
5636 StringRef AddressingMode = Inst.substr(4, 2);
5637 if (AddressingMode == "ia" || AddressingMode == "db" ||
5638 AddressingMode == "ea" || AddressingMode == "fd") {
5639 AcceptSinglePrecisionOnly = Inst[6] == 's';
5640 AcceptDoublePrecisionOnly = Inst[6] == 'd' || Inst[6] == 'x';
5648 /// Parse an arm instruction mnemonic followed by its operands.
5649 bool ARMAsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
5650 SMLoc NameLoc, OperandVector &Operands) {
5651 MCAsmParser &Parser = getParser();
5652 // FIXME: Can this be done via tablegen in some fashion?
5653 bool RequireVFPRegisterListCheck;
5654 bool AcceptSinglePrecisionOnly;
5655 bool AcceptDoublePrecisionOnly;
5656 RequireVFPRegisterListCheck =
5657 RequiresVFPRegListValidation(Name, AcceptSinglePrecisionOnly,
5658 AcceptDoublePrecisionOnly);
5660 // Apply mnemonic aliases before doing anything else, as the destination
5661 // mnemonic may include suffices and we want to handle them normally.
5662 // The generic tblgen'erated code does this later, at the start of
5663 // MatchInstructionImpl(), but that's too late for aliases that include
5664 // any sort of suffix.
5665 uint64_t AvailableFeatures = getAvailableFeatures();
5666 unsigned AssemblerDialect = getParser().getAssemblerDialect();
5667 applyMnemonicAliases(Name, AvailableFeatures, AssemblerDialect);
5669 // First check for the ARM-specific .req directive.
5670 if (Parser.getTok().is(AsmToken::Identifier) &&
5671 Parser.getTok().getIdentifier() == ".req") {
5672 parseDirectiveReq(Name, NameLoc);
5673 // We always return 'error' for this, as we're done with this
5674 // statement and don't need to match the 'instruction."
5678 // Create the leading tokens for the mnemonic, split by '.' characters.
5679 size_t Start = 0, Next = Name.find('.');
5680 StringRef Mnemonic = Name.slice(Start, Next);
5682 // Split out the predication code and carry setting flag from the mnemonic.
5683 unsigned PredicationCode;
5684 unsigned ProcessorIMod;
5687 Mnemonic = splitMnemonic(Mnemonic, PredicationCode, CarrySetting,
5688 ProcessorIMod, ITMask);
5690 // In Thumb1, only the branch (B) instruction can be predicated.
5691 if (isThumbOne() && PredicationCode != ARMCC::AL && Mnemonic != "b") {
5692 Parser.eatToEndOfStatement();
5693 return Error(NameLoc, "conditional execution not supported in Thumb1");
5696 Operands.push_back(ARMOperand::CreateToken(Mnemonic, NameLoc));
5698 // Handle the IT instruction ITMask. Convert it to a bitmask. This
5699 // is the mask as it will be for the IT encoding if the conditional
5700 // encoding has a '1' as it's bit0 (i.e. 't' ==> '1'). In the case
5701 // where the conditional bit0 is zero, the instruction post-processing
5702 // will adjust the mask accordingly.
5703 if (Mnemonic == "it") {
5704 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + 2);
5705 if (ITMask.size() > 3) {
5706 Parser.eatToEndOfStatement();
5707 return Error(Loc, "too many conditions on IT instruction");
5710 for (unsigned i = ITMask.size(); i != 0; --i) {
5711 char pos = ITMask[i - 1];
5712 if (pos != 't' && pos != 'e') {
5713 Parser.eatToEndOfStatement();
5714 return Error(Loc, "illegal IT block condition mask '" + ITMask + "'");
5717 if (ITMask[i - 1] == 't')
5720 Operands.push_back(ARMOperand::CreateITMask(Mask, Loc));
5723 // FIXME: This is all a pretty gross hack. We should automatically handle
5724 // optional operands like this via tblgen.
5726 // Next, add the CCOut and ConditionCode operands, if needed.
5728 // For mnemonics which can ever incorporate a carry setting bit or predication
5729 // code, our matching model involves us always generating CCOut and
5730 // ConditionCode operands to match the mnemonic "as written" and then we let
5731 // the matcher deal with finding the right instruction or generating an
5732 // appropriate error.
5733 bool CanAcceptCarrySet, CanAcceptPredicationCode;
5734 getMnemonicAcceptInfo(Mnemonic, Name, CanAcceptCarrySet, CanAcceptPredicationCode);
5736 // If we had a carry-set on an instruction that can't do that, issue an
5738 if (!CanAcceptCarrySet && CarrySetting) {
5739 Parser.eatToEndOfStatement();
5740 return Error(NameLoc, "instruction '" + Mnemonic +
5741 "' can not set flags, but 's' suffix specified");
5743 // If we had a predication code on an instruction that can't do that, issue an
5745 if (!CanAcceptPredicationCode && PredicationCode != ARMCC::AL) {
5746 Parser.eatToEndOfStatement();
5747 return Error(NameLoc, "instruction '" + Mnemonic +
5748 "' is not predicable, but condition code specified");
5751 // Add the carry setting operand, if necessary.
5752 if (CanAcceptCarrySet) {
5753 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size());
5754 Operands.push_back(ARMOperand::CreateCCOut(CarrySetting ? ARM::CPSR : 0,
5758 // Add the predication code operand, if necessary.
5759 if (CanAcceptPredicationCode) {
5760 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size() +
5762 Operands.push_back(ARMOperand::CreateCondCode(
5763 ARMCC::CondCodes(PredicationCode), Loc));
5766 // Add the processor imod operand, if necessary.
5767 if (ProcessorIMod) {
5768 Operands.push_back(ARMOperand::CreateImm(
5769 MCConstantExpr::Create(ProcessorIMod, getContext()),
5771 } else if (Mnemonic == "cps" && isMClass()) {
5772 return Error(NameLoc, "instruction 'cps' requires effect for M-class");
5775 // Add the remaining tokens in the mnemonic.
5776 while (Next != StringRef::npos) {
5778 Next = Name.find('.', Start + 1);
5779 StringRef ExtraToken = Name.slice(Start, Next);
5781 // Some NEON instructions have an optional datatype suffix that is
5782 // completely ignored. Check for that.
5783 if (isDataTypeToken(ExtraToken) &&
5784 doesIgnoreDataTypeSuffix(Mnemonic, ExtraToken))
5787 // For for ARM mode generate an error if the .n qualifier is used.
5788 if (ExtraToken == ".n" && !isThumb()) {
5789 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Start);
5790 Parser.eatToEndOfStatement();
5791 return Error(Loc, "instruction with .n (narrow) qualifier not allowed in "
5795 // The .n qualifier is always discarded as that is what the tables
5796 // and matcher expect. In ARM mode the .w qualifier has no effect,
5797 // so discard it to avoid errors that can be caused by the matcher.
5798 if (ExtraToken != ".n" && (isThumb() || ExtraToken != ".w")) {
5799 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Start);
5800 Operands.push_back(ARMOperand::CreateToken(ExtraToken, Loc));
5804 // Read the remaining operands.
5805 if (getLexer().isNot(AsmToken::EndOfStatement)) {
5806 // Read the first operand.
5807 if (parseOperand(Operands, Mnemonic)) {
5808 Parser.eatToEndOfStatement();
5812 while (getLexer().is(AsmToken::Comma)) {
5813 Parser.Lex(); // Eat the comma.
5815 // Parse and remember the operand.
5816 if (parseOperand(Operands, Mnemonic)) {
5817 Parser.eatToEndOfStatement();
5823 if (getLexer().isNot(AsmToken::EndOfStatement)) {
5824 SMLoc Loc = getLexer().getLoc();
5825 Parser.eatToEndOfStatement();
5826 return Error(Loc, "unexpected token in argument list");
5829 Parser.Lex(); // Consume the EndOfStatement
5831 if (RequireVFPRegisterListCheck) {
5832 ARMOperand &Op = static_cast<ARMOperand &>(*Operands.back());
5833 if (AcceptSinglePrecisionOnly && !Op.isSPRRegList())
5834 return Error(Op.getStartLoc(),
5835 "VFP/Neon single precision register expected");
5836 if (AcceptDoublePrecisionOnly && !Op.isDPRRegList())
5837 return Error(Op.getStartLoc(),
5838 "VFP/Neon double precision register expected");
5841 // Some instructions, mostly Thumb, have forms for the same mnemonic that
5842 // do and don't have a cc_out optional-def operand. With some spot-checks
5843 // of the operand list, we can figure out which variant we're trying to
5844 // parse and adjust accordingly before actually matching. We shouldn't ever
5845 // try to remove a cc_out operand that was explicitly set on the the
5846 // mnemonic, of course (CarrySetting == true). Reason number #317 the
5847 // table driven matcher doesn't fit well with the ARM instruction set.
5848 if (!CarrySetting && shouldOmitCCOutOperand(Mnemonic, Operands))
5849 Operands.erase(Operands.begin() + 1);
5851 // Some instructions have the same mnemonic, but don't always
5852 // have a predicate. Distinguish them here and delete the
5853 // predicate if needed.
5854 if (shouldOmitPredicateOperand(Mnemonic, Operands))
5855 Operands.erase(Operands.begin() + 1);
5857 // ARM mode 'blx' need special handling, as the register operand version
5858 // is predicable, but the label operand version is not. So, we can't rely
5859 // on the Mnemonic based checking to correctly figure out when to put
5860 // a k_CondCode operand in the list. If we're trying to match the label
5861 // version, remove the k_CondCode operand here.
5862 if (!isThumb() && Mnemonic == "blx" && Operands.size() == 3 &&
5863 static_cast<ARMOperand &>(*Operands[2]).isImm())
5864 Operands.erase(Operands.begin() + 1);
5866 // Adjust operands of ldrexd/strexd to MCK_GPRPair.
5867 // ldrexd/strexd require even/odd GPR pair. To enforce this constraint,
5868 // a single GPRPair reg operand is used in the .td file to replace the two
5869 // GPRs. However, when parsing from asm, the two GRPs cannot be automatically
5870 // expressed as a GPRPair, so we have to manually merge them.
5871 // FIXME: We would really like to be able to tablegen'erate this.
5872 if (!isThumb() && Operands.size() > 4 &&
5873 (Mnemonic == "ldrexd" || Mnemonic == "strexd" || Mnemonic == "ldaexd" ||
5874 Mnemonic == "stlexd")) {
5875 bool isLoad = (Mnemonic == "ldrexd" || Mnemonic == "ldaexd");
5876 unsigned Idx = isLoad ? 2 : 3;
5877 ARMOperand &Op1 = static_cast<ARMOperand &>(*Operands[Idx]);
5878 ARMOperand &Op2 = static_cast<ARMOperand &>(*Operands[Idx + 1]);
5880 const MCRegisterClass& MRC = MRI->getRegClass(ARM::GPRRegClassID);
5881 // Adjust only if Op1 and Op2 are GPRs.
5882 if (Op1.isReg() && Op2.isReg() && MRC.contains(Op1.getReg()) &&
5883 MRC.contains(Op2.getReg())) {
5884 unsigned Reg1 = Op1.getReg();
5885 unsigned Reg2 = Op2.getReg();
5886 unsigned Rt = MRI->getEncodingValue(Reg1);
5887 unsigned Rt2 = MRI->getEncodingValue(Reg2);
5889 // Rt2 must be Rt + 1 and Rt must be even.
5890 if (Rt + 1 != Rt2 || (Rt & 1)) {
5891 Error(Op2.getStartLoc(), isLoad
5892 ? "destination operands must be sequential"
5893 : "source operands must be sequential");
5896 unsigned NewReg = MRI->getMatchingSuperReg(Reg1, ARM::gsub_0,
5897 &(MRI->getRegClass(ARM::GPRPairRegClassID)));
5899 ARMOperand::CreateReg(NewReg, Op1.getStartLoc(), Op2.getEndLoc());
5900 Operands.erase(Operands.begin() + Idx + 1);
5904 // If first 2 operands of a 3 operand instruction are the same
5905 // then transform to 2 operand version of the same instruction
5906 // e.g. 'adds r0, r0, #1' transforms to 'adds r0, #1'
5907 // FIXME: We would really like to be able to tablegen'erate this.
5908 if (isThumbOne() && Operands.size() == 6 &&
5909 (Mnemonic == "add" || Mnemonic == "sub" || Mnemonic == "and" ||
5910 Mnemonic == "eor" || Mnemonic == "lsl" || Mnemonic == "lsr" ||
5911 Mnemonic == "asr" || Mnemonic == "adc" || Mnemonic == "sbc" ||
5912 Mnemonic == "ror" || Mnemonic == "orr" || Mnemonic == "bic")) {
5913 ARMOperand &Op3 = static_cast<ARMOperand &>(*Operands[3]);
5914 ARMOperand &Op4 = static_cast<ARMOperand &>(*Operands[4]);
5915 ARMOperand &Op5 = static_cast<ARMOperand &>(*Operands[5]);
5917 // If both registers are the same then remove one of them from
5918 // the operand list.
5919 if (Op3.isReg() && Op4.isReg() && Op3.getReg() == Op4.getReg()) {
5920 // If 3rd operand (variable Op5) is a register and the instruction is adds/sub
5921 // then do not transform as the backend already handles this instruction
5923 if (!Op5.isReg() || !((Mnemonic == "add" && CarrySetting) || Mnemonic == "sub")) {
5924 Operands.erase(Operands.begin() + 3);
5925 if (Mnemonic == "add" && !CarrySetting) {
5926 // Special case for 'add' (not 'adds') instruction must
5927 // remove the CCOut operand as well.
5928 Operands.erase(Operands.begin() + 1);
5934 // If instruction is 'add' and first two register operands
5935 // use SP register, then remove one of the SP registers from
5937 // FIXME: We would really like to be able to tablegen'erate this.
5938 if (isThumbOne() && Operands.size() == 5 && Mnemonic == "add" && !CarrySetting) {
5939 ARMOperand &Op2 = static_cast<ARMOperand &>(*Operands[2]);
5940 ARMOperand &Op3 = static_cast<ARMOperand &>(*Operands[3]);
5941 if (Op2.isReg() && Op3.isReg() && Op2.getReg() == ARM::SP && Op3.getReg() == ARM::SP) {
5942 Operands.erase(Operands.begin() + 2);
5946 // GNU Assembler extension (compatibility)
5947 if ((Mnemonic == "ldrd" || Mnemonic == "strd")) {
5948 ARMOperand &Op2 = static_cast<ARMOperand &>(*Operands[2]);
5949 ARMOperand &Op3 = static_cast<ARMOperand &>(*Operands[3]);
5951 assert(Op2.isReg() && "expected register argument");
5953 unsigned SuperReg = MRI->getMatchingSuperReg(
5954 Op2.getReg(), ARM::gsub_0, &MRI->getRegClass(ARM::GPRPairRegClassID));
5956 assert(SuperReg && "expected register pair");
5958 unsigned PairedReg = MRI->getSubReg(SuperReg, ARM::gsub_1);
5961 Operands.begin() + 3,
5962 ARMOperand::CreateReg(PairedReg, Op2.getStartLoc(), Op2.getEndLoc()));
5966 // FIXME: As said above, this is all a pretty gross hack. This instruction
5967 // does not fit with other "subs" and tblgen.
5968 // Adjust operands of B9.3.19 SUBS PC, LR, #imm (Thumb2) system instruction
5969 // so the Mnemonic is the original name "subs" and delete the predicate
5970 // operand so it will match the table entry.
5971 if (isThumbTwo() && Mnemonic == "sub" && Operands.size() == 6 &&
5972 static_cast<ARMOperand &>(*Operands[3]).isReg() &&
5973 static_cast<ARMOperand &>(*Operands[3]).getReg() == ARM::PC &&
5974 static_cast<ARMOperand &>(*Operands[4]).isReg() &&
5975 static_cast<ARMOperand &>(*Operands[4]).getReg() == ARM::LR &&
5976 static_cast<ARMOperand &>(*Operands[5]).isImm()) {
5977 Operands.front() = ARMOperand::CreateToken(Name, NameLoc);
5978 Operands.erase(Operands.begin() + 1);
5983 // Validate context-sensitive operand constraints.
5985 // return 'true' if register list contains non-low GPR registers,
5986 // 'false' otherwise. If Reg is in the register list or is HiReg, set
5987 // 'containsReg' to true.
5988 static bool checkLowRegisterList(MCInst Inst, unsigned OpNo, unsigned Reg,
5989 unsigned HiReg, bool &containsReg) {
5990 containsReg = false;
5991 for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) {
5992 unsigned OpReg = Inst.getOperand(i).getReg();
5995 // Anything other than a low register isn't legal here.
5996 if (!isARMLowRegister(OpReg) && (!HiReg || OpReg != HiReg))
6002 // Check if the specified regisgter is in the register list of the inst,
6003 // starting at the indicated operand number.
6004 static bool listContainsReg(MCInst &Inst, unsigned OpNo, unsigned Reg) {
6005 for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) {
6006 unsigned OpReg = Inst.getOperand(i).getReg();
6013 // Return true if instruction has the interesting property of being
6014 // allowed in IT blocks, but not being predicable.
6015 static bool instIsBreakpoint(const MCInst &Inst) {
6016 return Inst.getOpcode() == ARM::tBKPT ||
6017 Inst.getOpcode() == ARM::BKPT ||
6018 Inst.getOpcode() == ARM::tHLT ||
6019 Inst.getOpcode() == ARM::HLT;
6023 bool ARMAsmParser::validatetLDMRegList(MCInst Inst,
6024 const OperandVector &Operands,
6025 unsigned ListNo, bool IsARPop) {
6026 const ARMOperand &Op = static_cast<const ARMOperand &>(*Operands[ListNo]);
6027 bool HasWritebackToken = Op.isToken() && Op.getToken() == "!";
6029 bool ListContainsSP = listContainsReg(Inst, ListNo, ARM::SP);
6030 bool ListContainsLR = listContainsReg(Inst, ListNo, ARM::LR);
6031 bool ListContainsPC = listContainsReg(Inst, ListNo, ARM::PC);
6033 if (!IsARPop && ListContainsSP)
6034 return Error(Operands[ListNo + HasWritebackToken]->getStartLoc(),
6035 "SP may not be in the register list");
6036 else if (ListContainsPC && ListContainsLR)
6037 return Error(Operands[ListNo + HasWritebackToken]->getStartLoc(),
6038 "PC and LR may not be in the register list simultaneously");
6039 else if (inITBlock() && !lastInITBlock() && ListContainsPC)
6040 return Error(Operands[ListNo + HasWritebackToken]->getStartLoc(),
6041 "instruction must be outside of IT block or the last "
6042 "instruction in an IT block");
6046 bool ARMAsmParser::validatetSTMRegList(MCInst Inst,
6047 const OperandVector &Operands,
6049 const ARMOperand &Op = static_cast<const ARMOperand &>(*Operands[ListNo]);
6050 bool HasWritebackToken = Op.isToken() && Op.getToken() == "!";
6052 bool ListContainsSP = listContainsReg(Inst, ListNo, ARM::SP);
6053 bool ListContainsPC = listContainsReg(Inst, ListNo, ARM::PC);
6055 if (ListContainsSP && ListContainsPC)
6056 return Error(Operands[ListNo + HasWritebackToken]->getStartLoc(),
6057 "SP and PC may not be in the register list");
6058 else if (ListContainsSP)
6059 return Error(Operands[ListNo + HasWritebackToken]->getStartLoc(),
6060 "SP may not be in the register list");
6061 else if (ListContainsPC)
6062 return Error(Operands[ListNo + HasWritebackToken]->getStartLoc(),
6063 "PC may not be in the register list");
6067 // FIXME: We would really like to be able to tablegen'erate this.
6068 bool ARMAsmParser::validateInstruction(MCInst &Inst,
6069 const OperandVector &Operands) {
6070 const MCInstrDesc &MCID = MII.get(Inst.getOpcode());
6071 SMLoc Loc = Operands[0]->getStartLoc();
6073 // Check the IT block state first.
6074 // NOTE: BKPT and HLT instructions have the interesting property of being
6075 // allowed in IT blocks, but not being predicable. They just always execute.
6076 if (inITBlock() && !instIsBreakpoint(Inst)) {
6078 if (ITState.FirstCond)
6079 ITState.FirstCond = false;
6081 Bit = (ITState.Mask >> (5 - ITState.CurPosition)) & 1;
6082 // The instruction must be predicable.
6083 if (!MCID.isPredicable())
6084 return Error(Loc, "instructions in IT block must be predicable");
6085 unsigned Cond = Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm();
6086 unsigned ITCond = Bit ? ITState.Cond :
6087 ARMCC::getOppositeCondition(ITState.Cond);
6088 if (Cond != ITCond) {
6089 // Find the condition code Operand to get its SMLoc information.
6091 for (unsigned I = 1; I < Operands.size(); ++I)
6092 if (static_cast<ARMOperand &>(*Operands[I]).isCondCode())
6093 CondLoc = Operands[I]->getStartLoc();
6094 return Error(CondLoc, "incorrect condition in IT block; got '" +
6095 StringRef(ARMCondCodeToString(ARMCC::CondCodes(Cond))) +
6096 "', but expected '" +
6097 ARMCondCodeToString(ARMCC::CondCodes(ITCond)) + "'");
6099 // Check for non-'al' condition codes outside of the IT block.
6100 } else if (isThumbTwo() && MCID.isPredicable() &&
6101 Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm() !=
6102 ARMCC::AL && Inst.getOpcode() != ARM::tBcc &&
6103 Inst.getOpcode() != ARM::t2Bcc)
6104 return Error(Loc, "predicated instructions must be in IT block");
6106 const unsigned Opcode = Inst.getOpcode();
6110 case ARM::LDRD_POST: {
6111 const unsigned RtReg = Inst.getOperand(0).getReg();
6114 if (RtReg == ARM::LR)
6115 return Error(Operands[3]->getStartLoc(),
6118 const unsigned Rt = MRI->getEncodingValue(RtReg);
6119 // Rt must be even-numbered.
6121 return Error(Operands[3]->getStartLoc(),
6122 "Rt must be even-numbered");
6124 // Rt2 must be Rt + 1.
6125 const unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg());
6127 return Error(Operands[3]->getStartLoc(),
6128 "destination operands must be sequential");
6130 if (Opcode == ARM::LDRD_PRE || Opcode == ARM::LDRD_POST) {
6131 const unsigned Rn = MRI->getEncodingValue(Inst.getOperand(3).getReg());
6132 // For addressing modes with writeback, the base register needs to be
6133 // different from the destination registers.
6134 if (Rn == Rt || Rn == Rt2)
6135 return Error(Operands[3]->getStartLoc(),
6136 "base register needs to be different from destination "
6143 case ARM::t2LDRD_PRE:
6144 case ARM::t2LDRD_POST: {
6145 // Rt2 must be different from Rt.
6146 unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg());
6147 unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg());
6149 return Error(Operands[3]->getStartLoc(),
6150 "destination operands can't be identical");
6154 // Rt2 must be Rt + 1.
6155 unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg());
6156 unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg());
6158 return Error(Operands[3]->getStartLoc(),
6159 "source operands must be sequential");
6163 case ARM::STRD_POST: {
6164 // Rt2 must be Rt + 1.
6165 unsigned Rt = MRI->getEncodingValue(Inst.getOperand(1).getReg());
6166 unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(2).getReg());
6168 return Error(Operands[3]->getStartLoc(),
6169 "source operands must be sequential");
6172 case ARM::STR_PRE_IMM:
6173 case ARM::STR_PRE_REG:
6174 case ARM::STR_POST_IMM:
6175 case ARM::STR_POST_REG:
6177 case ARM::STRH_POST:
6178 case ARM::STRB_PRE_IMM:
6179 case ARM::STRB_PRE_REG:
6180 case ARM::STRB_POST_IMM:
6181 case ARM::STRB_POST_REG: {
6182 // Rt must be different from Rn.
6183 const unsigned Rt = MRI->getEncodingValue(Inst.getOperand(1).getReg());
6184 const unsigned Rn = MRI->getEncodingValue(Inst.getOperand(2).getReg());
6187 return Error(Operands[3]->getStartLoc(),
6188 "source register and base register can't be identical");
6191 case ARM::LDR_PRE_IMM:
6192 case ARM::LDR_PRE_REG:
6193 case ARM::LDR_POST_IMM:
6194 case ARM::LDR_POST_REG:
6196 case ARM::LDRH_POST:
6197 case ARM::LDRSH_PRE:
6198 case ARM::LDRSH_POST:
6199 case ARM::LDRB_PRE_IMM:
6200 case ARM::LDRB_PRE_REG:
6201 case ARM::LDRB_POST_IMM:
6202 case ARM::LDRB_POST_REG:
6203 case ARM::LDRSB_PRE:
6204 case ARM::LDRSB_POST: {
6205 // Rt must be different from Rn.
6206 const unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg());
6207 const unsigned Rn = MRI->getEncodingValue(Inst.getOperand(2).getReg());
6210 return Error(Operands[3]->getStartLoc(),
6211 "destination register and base register can't be identical");
6216 // Width must be in range [1, 32-lsb].
6217 unsigned LSB = Inst.getOperand(2).getImm();
6218 unsigned Widthm1 = Inst.getOperand(3).getImm();
6219 if (Widthm1 >= 32 - LSB)
6220 return Error(Operands[5]->getStartLoc(),
6221 "bitfield width must be in range [1,32-lsb]");
6224 // Notionally handles ARM::tLDMIA_UPD too.
6226 // If we're parsing Thumb2, the .w variant is available and handles
6227 // most cases that are normally illegal for a Thumb1 LDM instruction.
6228 // We'll make the transformation in processInstruction() if necessary.
6230 // Thumb LDM instructions are writeback iff the base register is not
6231 // in the register list.
6232 unsigned Rn = Inst.getOperand(0).getReg();
6233 bool HasWritebackToken =
6234 (static_cast<ARMOperand &>(*Operands[3]).isToken() &&
6235 static_cast<ARMOperand &>(*Operands[3]).getToken() == "!");
6236 bool ListContainsBase;
6237 if (checkLowRegisterList(Inst, 3, Rn, 0, ListContainsBase) && !isThumbTwo())
6238 return Error(Operands[3 + HasWritebackToken]->getStartLoc(),
6239 "registers must be in range r0-r7");
6240 // If we should have writeback, then there should be a '!' token.
6241 if (!ListContainsBase && !HasWritebackToken && !isThumbTwo())
6242 return Error(Operands[2]->getStartLoc(),
6243 "writeback operator '!' expected");
6244 // If we should not have writeback, there must not be a '!'. This is
6245 // true even for the 32-bit wide encodings.
6246 if (ListContainsBase && HasWritebackToken)
6247 return Error(Operands[3]->getStartLoc(),
6248 "writeback operator '!' not allowed when base register "
6249 "in register list");
6251 if (validatetLDMRegList(Inst, Operands, 3))
6255 case ARM::LDMIA_UPD:
6256 case ARM::LDMDB_UPD:
6257 case ARM::LDMIB_UPD:
6258 case ARM::LDMDA_UPD:
6259 // ARM variants loading and updating the same register are only officially
6260 // UNPREDICTABLE on v7 upwards. Goodness knows what they did before.
6263 if (listContainsReg(Inst, 3, Inst.getOperand(0).getReg()))
6264 return Error(Operands.back()->getStartLoc(),
6265 "writeback register not allowed in register list");
6269 if (validatetLDMRegList(Inst, Operands, 3))
6274 if (validatetSTMRegList(Inst, Operands, 3))
6277 case ARM::t2LDMIA_UPD:
6278 case ARM::t2LDMDB_UPD:
6279 case ARM::t2STMIA_UPD:
6280 case ARM::t2STMDB_UPD: {
6281 if (listContainsReg(Inst, 3, Inst.getOperand(0).getReg()))
6282 return Error(Operands.back()->getStartLoc(),
6283 "writeback register not allowed in register list");
6285 if (Opcode == ARM::t2LDMIA_UPD || Opcode == ARM::t2LDMDB_UPD) {
6286 if (validatetLDMRegList(Inst, Operands, 3))
6289 if (validatetSTMRegList(Inst, Operands, 3))
6294 case ARM::sysLDMIA_UPD:
6295 case ARM::sysLDMDA_UPD:
6296 case ARM::sysLDMDB_UPD:
6297 case ARM::sysLDMIB_UPD:
6298 if (!listContainsReg(Inst, 3, ARM::PC))
6299 return Error(Operands[4]->getStartLoc(),
6300 "writeback register only allowed on system LDM "
6301 "if PC in register-list");
6303 case ARM::sysSTMIA_UPD:
6304 case ARM::sysSTMDA_UPD:
6305 case ARM::sysSTMDB_UPD:
6306 case ARM::sysSTMIB_UPD:
6307 return Error(Operands[2]->getStartLoc(),
6308 "system STM cannot have writeback register");
6310 // The second source operand must be the same register as the destination
6313 // In this case, we must directly check the parsed operands because the
6314 // cvtThumbMultiply() function is written in such a way that it guarantees
6315 // this first statement is always true for the new Inst. Essentially, the
6316 // destination is unconditionally copied into the second source operand
6317 // without checking to see if it matches what we actually parsed.
6318 if (Operands.size() == 6 && (((ARMOperand &)*Operands[3]).getReg() !=
6319 ((ARMOperand &)*Operands[5]).getReg()) &&
6320 (((ARMOperand &)*Operands[3]).getReg() !=
6321 ((ARMOperand &)*Operands[4]).getReg())) {
6322 return Error(Operands[3]->getStartLoc(),
6323 "destination register must match source register");
6327 // Like for ldm/stm, push and pop have hi-reg handling version in Thumb2,
6328 // so only issue a diagnostic for thumb1. The instructions will be
6329 // switched to the t2 encodings in processInstruction() if necessary.
6331 bool ListContainsBase;
6332 if (checkLowRegisterList(Inst, 2, 0, ARM::PC, ListContainsBase) &&
6334 return Error(Operands[2]->getStartLoc(),
6335 "registers must be in range r0-r7 or pc");
6336 if (validatetLDMRegList(Inst, Operands, 2, !isMClass()))
6341 bool ListContainsBase;
6342 if (checkLowRegisterList(Inst, 2, 0, ARM::LR, ListContainsBase) &&
6344 return Error(Operands[2]->getStartLoc(),
6345 "registers must be in range r0-r7 or lr");
6346 if (validatetSTMRegList(Inst, Operands, 2))
6350 case ARM::tSTMIA_UPD: {
6351 bool ListContainsBase, InvalidLowList;
6352 InvalidLowList = checkLowRegisterList(Inst, 4, Inst.getOperand(0).getReg(),
6353 0, ListContainsBase);
6354 if (InvalidLowList && !isThumbTwo())
6355 return Error(Operands[4]->getStartLoc(),
6356 "registers must be in range r0-r7");
6358 // This would be converted to a 32-bit stm, but that's not valid if the
6359 // writeback register is in the list.
6360 if (InvalidLowList && ListContainsBase)
6361 return Error(Operands[4]->getStartLoc(),
6362 "writeback operator '!' not allowed when base register "
6363 "in register list");
6365 if (validatetSTMRegList(Inst, Operands, 4))
6369 case ARM::tADDrSP: {
6370 // If the non-SP source operand and the destination operand are not the
6371 // same, we need thumb2 (for the wide encoding), or we have an error.
6372 if (!isThumbTwo() &&
6373 Inst.getOperand(0).getReg() != Inst.getOperand(2).getReg()) {
6374 return Error(Operands[4]->getStartLoc(),
6375 "source register must be the same as destination");
6379 // Final range checking for Thumb unconditional branch instructions.
6381 if (!(static_cast<ARMOperand &>(*Operands[2])).isSignedOffset<11, 1>())
6382 return Error(Operands[2]->getStartLoc(), "branch target out of range");
6385 int op = (Operands[2]->isImm()) ? 2 : 3;
6386 if (!static_cast<ARMOperand &>(*Operands[op]).isSignedOffset<24, 1>())
6387 return Error(Operands[op]->getStartLoc(), "branch target out of range");
6390 // Final range checking for Thumb conditional branch instructions.
6392 if (!static_cast<ARMOperand &>(*Operands[2]).isSignedOffset<8, 1>())
6393 return Error(Operands[2]->getStartLoc(), "branch target out of range");
6396 int Op = (Operands[2]->isImm()) ? 2 : 3;
6397 if (!static_cast<ARMOperand &>(*Operands[Op]).isSignedOffset<20, 1>())
6398 return Error(Operands[Op]->getStartLoc(), "branch target out of range");
6403 case ARM::t2MOVTi16:
6405 // We want to avoid misleadingly allowing something like "mov r0, <symbol>"
6406 // especially when we turn it into a movw and the expression <symbol> does
6407 // not have a :lower16: or :upper16 as part of the expression. We don't
6408 // want the behavior of silently truncating, which can be unexpected and
6409 // lead to bugs that are difficult to find since this is an easy mistake
6411 int i = (Operands[3]->isImm()) ? 3 : 4;
6412 ARMOperand &Op = static_cast<ARMOperand &>(*Operands[i]);
6413 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op.getImm());
6415 const MCExpr *E = dyn_cast<MCExpr>(Op.getImm());
6417 const ARMMCExpr *ARM16Expr = dyn_cast<ARMMCExpr>(E);
6418 if (!ARM16Expr || (ARM16Expr->getKind() != ARMMCExpr::VK_ARM_HI16 &&
6419 ARM16Expr->getKind() != ARMMCExpr::VK_ARM_LO16))
6422 "immediate expression for mov requires :lower16: or :upper16");
6430 static unsigned getRealVSTOpcode(unsigned Opc, unsigned &Spacing) {
6432 default: llvm_unreachable("unexpected opcode!");
6434 case ARM::VST1LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST1LNd8_UPD;
6435 case ARM::VST1LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST1LNd16_UPD;
6436 case ARM::VST1LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST1LNd32_UPD;
6437 case ARM::VST1LNdWB_register_Asm_8: Spacing = 1; return ARM::VST1LNd8_UPD;
6438 case ARM::VST1LNdWB_register_Asm_16: Spacing = 1; return ARM::VST1LNd16_UPD;
6439 case ARM::VST1LNdWB_register_Asm_32: Spacing = 1; return ARM::VST1LNd32_UPD;
6440 case ARM::VST1LNdAsm_8: Spacing = 1; return ARM::VST1LNd8;
6441 case ARM::VST1LNdAsm_16: Spacing = 1; return ARM::VST1LNd16;
6442 case ARM::VST1LNdAsm_32: Spacing = 1; return ARM::VST1LNd32;
6445 case ARM::VST2LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST2LNd8_UPD;
6446 case ARM::VST2LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST2LNd16_UPD;
6447 case ARM::VST2LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST2LNd32_UPD;
6448 case ARM::VST2LNqWB_fixed_Asm_16: Spacing = 2; return ARM::VST2LNq16_UPD;
6449 case ARM::VST2LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST2LNq32_UPD;
6451 case ARM::VST2LNdWB_register_Asm_8: Spacing = 1; return ARM::VST2LNd8_UPD;
6452 case ARM::VST2LNdWB_register_Asm_16: Spacing = 1; return ARM::VST2LNd16_UPD;
6453 case ARM::VST2LNdWB_register_Asm_32: Spacing = 1; return ARM::VST2LNd32_UPD;
6454 case ARM::VST2LNqWB_register_Asm_16: Spacing = 2; return ARM::VST2LNq16_UPD;
6455 case ARM::VST2LNqWB_register_Asm_32: Spacing = 2; return ARM::VST2LNq32_UPD;
6457 case ARM::VST2LNdAsm_8: Spacing = 1; return ARM::VST2LNd8;
6458 case ARM::VST2LNdAsm_16: Spacing = 1; return ARM::VST2LNd16;
6459 case ARM::VST2LNdAsm_32: Spacing = 1; return ARM::VST2LNd32;
6460 case ARM::VST2LNqAsm_16: Spacing = 2; return ARM::VST2LNq16;
6461 case ARM::VST2LNqAsm_32: Spacing = 2; return ARM::VST2LNq32;
6464 case ARM::VST3LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST3LNd8_UPD;
6465 case ARM::VST3LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST3LNd16_UPD;
6466 case ARM::VST3LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST3LNd32_UPD;
6467 case ARM::VST3LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VST3LNq16_UPD;
6468 case ARM::VST3LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST3LNq32_UPD;
6469 case ARM::VST3LNdWB_register_Asm_8: Spacing = 1; return ARM::VST3LNd8_UPD;
6470 case ARM::VST3LNdWB_register_Asm_16: Spacing = 1; return ARM::VST3LNd16_UPD;
6471 case ARM::VST3LNdWB_register_Asm_32: Spacing = 1; return ARM::VST3LNd32_UPD;
6472 case ARM::VST3LNqWB_register_Asm_16: Spacing = 2; return ARM::VST3LNq16_UPD;
6473 case ARM::VST3LNqWB_register_Asm_32: Spacing = 2; return ARM::VST3LNq32_UPD;
6474 case ARM::VST3LNdAsm_8: Spacing = 1; return ARM::VST3LNd8;
6475 case ARM::VST3LNdAsm_16: Spacing = 1; return ARM::VST3LNd16;
6476 case ARM::VST3LNdAsm_32: Spacing = 1; return ARM::VST3LNd32;
6477 case ARM::VST3LNqAsm_16: Spacing = 2; return ARM::VST3LNq16;
6478 case ARM::VST3LNqAsm_32: Spacing = 2; return ARM::VST3LNq32;
6481 case ARM::VST3dWB_fixed_Asm_8: Spacing = 1; return ARM::VST3d8_UPD;
6482 case ARM::VST3dWB_fixed_Asm_16: Spacing = 1; return ARM::VST3d16_UPD;
6483 case ARM::VST3dWB_fixed_Asm_32: Spacing = 1; return ARM::VST3d32_UPD;
6484 case ARM::VST3qWB_fixed_Asm_8: Spacing = 2; return ARM::VST3q8_UPD;
6485 case ARM::VST3qWB_fixed_Asm_16: Spacing = 2; return ARM::VST3q16_UPD;
6486 case ARM::VST3qWB_fixed_Asm_32: Spacing = 2; return ARM::VST3q32_UPD;
6487 case ARM::VST3dWB_register_Asm_8: Spacing = 1; return ARM::VST3d8_UPD;
6488 case ARM::VST3dWB_register_Asm_16: Spacing = 1; return ARM::VST3d16_UPD;
6489 case ARM::VST3dWB_register_Asm_32: Spacing = 1; return ARM::VST3d32_UPD;
6490 case ARM::VST3qWB_register_Asm_8: Spacing = 2; return ARM::VST3q8_UPD;
6491 case ARM::VST3qWB_register_Asm_16: Spacing = 2; return ARM::VST3q16_UPD;
6492 case ARM::VST3qWB_register_Asm_32: Spacing = 2; return ARM::VST3q32_UPD;
6493 case ARM::VST3dAsm_8: Spacing = 1; return ARM::VST3d8;
6494 case ARM::VST3dAsm_16: Spacing = 1; return ARM::VST3d16;
6495 case ARM::VST3dAsm_32: Spacing = 1; return ARM::VST3d32;
6496 case ARM::VST3qAsm_8: Spacing = 2; return ARM::VST3q8;
6497 case ARM::VST3qAsm_16: Spacing = 2; return ARM::VST3q16;
6498 case ARM::VST3qAsm_32: Spacing = 2; return ARM::VST3q32;
6501 case ARM::VST4LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST4LNd8_UPD;
6502 case ARM::VST4LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST4LNd16_UPD;
6503 case ARM::VST4LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST4LNd32_UPD;
6504 case ARM::VST4LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VST4LNq16_UPD;
6505 case ARM::VST4LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST4LNq32_UPD;
6506 case ARM::VST4LNdWB_register_Asm_8: Spacing = 1; return ARM::VST4LNd8_UPD;
6507 case ARM::VST4LNdWB_register_Asm_16: Spacing = 1; return ARM::VST4LNd16_UPD;
6508 case ARM::VST4LNdWB_register_Asm_32: Spacing = 1; return ARM::VST4LNd32_UPD;
6509 case ARM::VST4LNqWB_register_Asm_16: Spacing = 2; return ARM::VST4LNq16_UPD;
6510 case ARM::VST4LNqWB_register_Asm_32: Spacing = 2; return ARM::VST4LNq32_UPD;
6511 case ARM::VST4LNdAsm_8: Spacing = 1; return ARM::VST4LNd8;
6512 case ARM::VST4LNdAsm_16: Spacing = 1; return ARM::VST4LNd16;
6513 case ARM::VST4LNdAsm_32: Spacing = 1; return ARM::VST4LNd32;
6514 case ARM::VST4LNqAsm_16: Spacing = 2; return ARM::VST4LNq16;
6515 case ARM::VST4LNqAsm_32: Spacing = 2; return ARM::VST4LNq32;
6518 case ARM::VST4dWB_fixed_Asm_8: Spacing = 1; return ARM::VST4d8_UPD;
6519 case ARM::VST4dWB_fixed_Asm_16: Spacing = 1; return ARM::VST4d16_UPD;
6520 case ARM::VST4dWB_fixed_Asm_32: Spacing = 1; return ARM::VST4d32_UPD;
6521 case ARM::VST4qWB_fixed_Asm_8: Spacing = 2; return ARM::VST4q8_UPD;
6522 case ARM::VST4qWB_fixed_Asm_16: Spacing = 2; return ARM::VST4q16_UPD;
6523 case ARM::VST4qWB_fixed_Asm_32: Spacing = 2; return ARM::VST4q32_UPD;
6524 case ARM::VST4dWB_register_Asm_8: Spacing = 1; return ARM::VST4d8_UPD;
6525 case ARM::VST4dWB_register_Asm_16: Spacing = 1; return ARM::VST4d16_UPD;
6526 case ARM::VST4dWB_register_Asm_32: Spacing = 1; return ARM::VST4d32_UPD;
6527 case ARM::VST4qWB_register_Asm_8: Spacing = 2; return ARM::VST4q8_UPD;
6528 case ARM::VST4qWB_register_Asm_16: Spacing = 2; return ARM::VST4q16_UPD;
6529 case ARM::VST4qWB_register_Asm_32: Spacing = 2; return ARM::VST4q32_UPD;
6530 case ARM::VST4dAsm_8: Spacing = 1; return ARM::VST4d8;
6531 case ARM::VST4dAsm_16: Spacing = 1; return ARM::VST4d16;
6532 case ARM::VST4dAsm_32: Spacing = 1; return ARM::VST4d32;
6533 case ARM::VST4qAsm_8: Spacing = 2; return ARM::VST4q8;
6534 case ARM::VST4qAsm_16: Spacing = 2; return ARM::VST4q16;
6535 case ARM::VST4qAsm_32: Spacing = 2; return ARM::VST4q32;
6539 static unsigned getRealVLDOpcode(unsigned Opc, unsigned &Spacing) {
6541 default: llvm_unreachable("unexpected opcode!");
6543 case ARM::VLD1LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD1LNd8_UPD;
6544 case ARM::VLD1LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD1LNd16_UPD;
6545 case ARM::VLD1LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD1LNd32_UPD;
6546 case ARM::VLD1LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD1LNd8_UPD;
6547 case ARM::VLD1LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD1LNd16_UPD;
6548 case ARM::VLD1LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD1LNd32_UPD;
6549 case ARM::VLD1LNdAsm_8: Spacing = 1; return ARM::VLD1LNd8;
6550 case ARM::VLD1LNdAsm_16: Spacing = 1; return ARM::VLD1LNd16;
6551 case ARM::VLD1LNdAsm_32: Spacing = 1; return ARM::VLD1LNd32;
6554 case ARM::VLD2LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD2LNd8_UPD;
6555 case ARM::VLD2LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD2LNd16_UPD;
6556 case ARM::VLD2LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD2LNd32_UPD;
6557 case ARM::VLD2LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD2LNq16_UPD;
6558 case ARM::VLD2LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD2LNq32_UPD;
6559 case ARM::VLD2LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD2LNd8_UPD;
6560 case ARM::VLD2LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD2LNd16_UPD;
6561 case ARM::VLD2LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD2LNd32_UPD;
6562 case ARM::VLD2LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD2LNq16_UPD;
6563 case ARM::VLD2LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD2LNq32_UPD;
6564 case ARM::VLD2LNdAsm_8: Spacing = 1; return ARM::VLD2LNd8;
6565 case ARM::VLD2LNdAsm_16: Spacing = 1; return ARM::VLD2LNd16;
6566 case ARM::VLD2LNdAsm_32: Spacing = 1; return ARM::VLD2LNd32;
6567 case ARM::VLD2LNqAsm_16: Spacing = 2; return ARM::VLD2LNq16;
6568 case ARM::VLD2LNqAsm_32: Spacing = 2; return ARM::VLD2LNq32;
6571 case ARM::VLD3DUPdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3DUPd8_UPD;
6572 case ARM::VLD3DUPdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3DUPd16_UPD;
6573 case ARM::VLD3DUPdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3DUPd32_UPD;
6574 case ARM::VLD3DUPqWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3DUPq8_UPD;
6575 case ARM::VLD3DUPqWB_fixed_Asm_16: Spacing = 2; return ARM::VLD3DUPq16_UPD;
6576 case ARM::VLD3DUPqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3DUPq32_UPD;
6577 case ARM::VLD3DUPdWB_register_Asm_8: Spacing = 1; return ARM::VLD3DUPd8_UPD;
6578 case ARM::VLD3DUPdWB_register_Asm_16: Spacing = 1; return ARM::VLD3DUPd16_UPD;
6579 case ARM::VLD3DUPdWB_register_Asm_32: Spacing = 1; return ARM::VLD3DUPd32_UPD;
6580 case ARM::VLD3DUPqWB_register_Asm_8: Spacing = 2; return ARM::VLD3DUPq8_UPD;
6581 case ARM::VLD3DUPqWB_register_Asm_16: Spacing = 2; return ARM::VLD3DUPq16_UPD;
6582 case ARM::VLD3DUPqWB_register_Asm_32: Spacing = 2; return ARM::VLD3DUPq32_UPD;
6583 case ARM::VLD3DUPdAsm_8: Spacing = 1; return ARM::VLD3DUPd8;
6584 case ARM::VLD3DUPdAsm_16: Spacing = 1; return ARM::VLD3DUPd16;
6585 case ARM::VLD3DUPdAsm_32: Spacing = 1; return ARM::VLD3DUPd32;
6586 case ARM::VLD3DUPqAsm_8: Spacing = 2; return ARM::VLD3DUPq8;
6587 case ARM::VLD3DUPqAsm_16: Spacing = 2; return ARM::VLD3DUPq16;
6588 case ARM::VLD3DUPqAsm_32: Spacing = 2; return ARM::VLD3DUPq32;
6591 case ARM::VLD3LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3LNd8_UPD;
6592 case ARM::VLD3LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3LNd16_UPD;
6593 case ARM::VLD3LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3LNd32_UPD;
6594 case ARM::VLD3LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3LNq16_UPD;
6595 case ARM::VLD3LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3LNq32_UPD;
6596 case ARM::VLD3LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD3LNd8_UPD;
6597 case ARM::VLD3LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD3LNd16_UPD;
6598 case ARM::VLD3LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD3LNd32_UPD;
6599 case ARM::VLD3LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD3LNq16_UPD;
6600 case ARM::VLD3LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD3LNq32_UPD;
6601 case ARM::VLD3LNdAsm_8: Spacing = 1; return ARM::VLD3LNd8;
6602 case ARM::VLD3LNdAsm_16: Spacing = 1; return ARM::VLD3LNd16;
6603 case ARM::VLD3LNdAsm_32: Spacing = 1; return ARM::VLD3LNd32;
6604 case ARM::VLD3LNqAsm_16: Spacing = 2; return ARM::VLD3LNq16;
6605 case ARM::VLD3LNqAsm_32: Spacing = 2; return ARM::VLD3LNq32;
6608 case ARM::VLD3dWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3d8_UPD;
6609 case ARM::VLD3dWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3d16_UPD;
6610 case ARM::VLD3dWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3d32_UPD;
6611 case ARM::VLD3qWB_fixed_Asm_8: Spacing = 2; return ARM::VLD3q8_UPD;
6612 case ARM::VLD3qWB_fixed_Asm_16: Spacing = 2; return ARM::VLD3q16_UPD;
6613 case ARM::VLD3qWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3q32_UPD;
6614 case ARM::VLD3dWB_register_Asm_8: Spacing = 1; return ARM::VLD3d8_UPD;
6615 case ARM::VLD3dWB_register_Asm_16: Spacing = 1; return ARM::VLD3d16_UPD;
6616 case ARM::VLD3dWB_register_Asm_32: Spacing = 1; return ARM::VLD3d32_UPD;
6617 case ARM::VLD3qWB_register_Asm_8: Spacing = 2; return ARM::VLD3q8_UPD;
6618 case ARM::VLD3qWB_register_Asm_16: Spacing = 2; return ARM::VLD3q16_UPD;
6619 case ARM::VLD3qWB_register_Asm_32: Spacing = 2; return ARM::VLD3q32_UPD;
6620 case ARM::VLD3dAsm_8: Spacing = 1; return ARM::VLD3d8;
6621 case ARM::VLD3dAsm_16: Spacing = 1; return ARM::VLD3d16;
6622 case ARM::VLD3dAsm_32: Spacing = 1; return ARM::VLD3d32;
6623 case ARM::VLD3qAsm_8: Spacing = 2; return ARM::VLD3q8;
6624 case ARM::VLD3qAsm_16: Spacing = 2; return ARM::VLD3q16;
6625 case ARM::VLD3qAsm_32: Spacing = 2; return ARM::VLD3q32;
6628 case ARM::VLD4LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4LNd8_UPD;
6629 case ARM::VLD4LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4LNd16_UPD;
6630 case ARM::VLD4LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4LNd32_UPD;
6631 case ARM::VLD4LNqWB_fixed_Asm_16: Spacing = 2; return ARM::VLD4LNq16_UPD;
6632 case ARM::VLD4LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4LNq32_UPD;
6633 case ARM::VLD4LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD4LNd8_UPD;
6634 case ARM::VLD4LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD4LNd16_UPD;
6635 case ARM::VLD4LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD4LNd32_UPD;
6636 case ARM::VLD4LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD4LNq16_UPD;
6637 case ARM::VLD4LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD4LNq32_UPD;
6638 case ARM::VLD4LNdAsm_8: Spacing = 1; return ARM::VLD4LNd8;
6639 case ARM::VLD4LNdAsm_16: Spacing = 1; return ARM::VLD4LNd16;
6640 case ARM::VLD4LNdAsm_32: Spacing = 1; return ARM::VLD4LNd32;
6641 case ARM::VLD4LNqAsm_16: Spacing = 2; return ARM::VLD4LNq16;
6642 case ARM::VLD4LNqAsm_32: Spacing = 2; return ARM::VLD4LNq32;
6645 case ARM::VLD4DUPdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4DUPd8_UPD;
6646 case ARM::VLD4DUPdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4DUPd16_UPD;
6647 case ARM::VLD4DUPdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4DUPd32_UPD;
6648 case ARM::VLD4DUPqWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4DUPq8_UPD;
6649 case ARM::VLD4DUPqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4DUPq16_UPD;
6650 case ARM::VLD4DUPqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4DUPq32_UPD;
6651 case ARM::VLD4DUPdWB_register_Asm_8: Spacing = 1; return ARM::VLD4DUPd8_UPD;
6652 case ARM::VLD4DUPdWB_register_Asm_16: Spacing = 1; return ARM::VLD4DUPd16_UPD;
6653 case ARM::VLD4DUPdWB_register_Asm_32: Spacing = 1; return ARM::VLD4DUPd32_UPD;
6654 case ARM::VLD4DUPqWB_register_Asm_8: Spacing = 2; return ARM::VLD4DUPq8_UPD;
6655 case ARM::VLD4DUPqWB_register_Asm_16: Spacing = 2; return ARM::VLD4DUPq16_UPD;
6656 case ARM::VLD4DUPqWB_register_Asm_32: Spacing = 2; return ARM::VLD4DUPq32_UPD;
6657 case ARM::VLD4DUPdAsm_8: Spacing = 1; return ARM::VLD4DUPd8;
6658 case ARM::VLD4DUPdAsm_16: Spacing = 1; return ARM::VLD4DUPd16;
6659 case ARM::VLD4DUPdAsm_32: Spacing = 1; return ARM::VLD4DUPd32;
6660 case ARM::VLD4DUPqAsm_8: Spacing = 2; return ARM::VLD4DUPq8;
6661 case ARM::VLD4DUPqAsm_16: Spacing = 2; return ARM::VLD4DUPq16;
6662 case ARM::VLD4DUPqAsm_32: Spacing = 2; return ARM::VLD4DUPq32;
6665 case ARM::VLD4dWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4d8_UPD;
6666 case ARM::VLD4dWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4d16_UPD;
6667 case ARM::VLD4dWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4d32_UPD;
6668 case ARM::VLD4qWB_fixed_Asm_8: Spacing = 2; return ARM::VLD4q8_UPD;
6669 case ARM::VLD4qWB_fixed_Asm_16: Spacing = 2; return ARM::VLD4q16_UPD;
6670 case ARM::VLD4qWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4q32_UPD;
6671 case ARM::VLD4dWB_register_Asm_8: Spacing = 1; return ARM::VLD4d8_UPD;
6672 case ARM::VLD4dWB_register_Asm_16: Spacing = 1; return ARM::VLD4d16_UPD;
6673 case ARM::VLD4dWB_register_Asm_32: Spacing = 1; return ARM::VLD4d32_UPD;
6674 case ARM::VLD4qWB_register_Asm_8: Spacing = 2; return ARM::VLD4q8_UPD;
6675 case ARM::VLD4qWB_register_Asm_16: Spacing = 2; return ARM::VLD4q16_UPD;
6676 case ARM::VLD4qWB_register_Asm_32: Spacing = 2; return ARM::VLD4q32_UPD;
6677 case ARM::VLD4dAsm_8: Spacing = 1; return ARM::VLD4d8;
6678 case ARM::VLD4dAsm_16: Spacing = 1; return ARM::VLD4d16;
6679 case ARM::VLD4dAsm_32: Spacing = 1; return ARM::VLD4d32;
6680 case ARM::VLD4qAsm_8: Spacing = 2; return ARM::VLD4q8;
6681 case ARM::VLD4qAsm_16: Spacing = 2; return ARM::VLD4q16;
6682 case ARM::VLD4qAsm_32: Spacing = 2; return ARM::VLD4q32;
6686 bool ARMAsmParser::processInstruction(MCInst &Inst,
6687 const OperandVector &Operands,
6689 switch (Inst.getOpcode()) {
6690 // Alias for alternate form of 'ldr{,b}t Rt, [Rn], #imm' instruction.
6691 case ARM::LDRT_POST:
6692 case ARM::LDRBT_POST: {
6693 const unsigned Opcode =
6694 (Inst.getOpcode() == ARM::LDRT_POST) ? ARM::LDRT_POST_IMM
6695 : ARM::LDRBT_POST_IMM;
6697 TmpInst.setOpcode(Opcode);
6698 TmpInst.addOperand(Inst.getOperand(0));
6699 TmpInst.addOperand(Inst.getOperand(1));
6700 TmpInst.addOperand(Inst.getOperand(1));
6701 TmpInst.addOperand(MCOperand::CreateReg(0));
6702 TmpInst.addOperand(MCOperand::CreateImm(0));
6703 TmpInst.addOperand(Inst.getOperand(2));
6704 TmpInst.addOperand(Inst.getOperand(3));
6708 // Alias for alternate form of 'str{,b}t Rt, [Rn], #imm' instruction.
6709 case ARM::STRT_POST:
6710 case ARM::STRBT_POST: {
6711 const unsigned Opcode =
6712 (Inst.getOpcode() == ARM::STRT_POST) ? ARM::STRT_POST_IMM
6713 : ARM::STRBT_POST_IMM;
6715 TmpInst.setOpcode(Opcode);
6716 TmpInst.addOperand(Inst.getOperand(1));
6717 TmpInst.addOperand(Inst.getOperand(0));
6718 TmpInst.addOperand(Inst.getOperand(1));
6719 TmpInst.addOperand(MCOperand::CreateReg(0));
6720 TmpInst.addOperand(MCOperand::CreateImm(0));
6721 TmpInst.addOperand(Inst.getOperand(2));
6722 TmpInst.addOperand(Inst.getOperand(3));
6726 // Alias for alternate form of 'ADR Rd, #imm' instruction.
6728 if (Inst.getOperand(1).getReg() != ARM::PC ||
6729 Inst.getOperand(5).getReg() != 0 ||
6730 !(Inst.getOperand(2).isExpr() || Inst.getOperand(2).isImm()))
6733 TmpInst.setOpcode(ARM::ADR);
6734 TmpInst.addOperand(Inst.getOperand(0));
6735 if (Inst.getOperand(2).isImm()) {
6736 // Immediate (mod_imm) will be in its encoded form, we must unencode it
6737 // before passing it to the ADR instruction.
6738 unsigned Enc = Inst.getOperand(2).getImm();
6739 TmpInst.addOperand(MCOperand::CreateImm(
6740 ARM_AM::rotr32(Enc & 0xFF, (Enc & 0xF00) >> 7)));
6742 // Turn PC-relative expression into absolute expression.
6743 // Reading PC provides the start of the current instruction + 8 and
6744 // the transform to adr is biased by that.
6745 MCSymbol *Dot = getContext().CreateTempSymbol();
6747 const MCExpr *OpExpr = Inst.getOperand(2).getExpr();
6748 const MCExpr *InstPC = MCSymbolRefExpr::Create(Dot,
6749 MCSymbolRefExpr::VK_None,
6751 const MCExpr *Const8 = MCConstantExpr::Create(8, getContext());
6752 const MCExpr *ReadPC = MCBinaryExpr::CreateAdd(InstPC, Const8,
6754 const MCExpr *FixupAddr = MCBinaryExpr::CreateAdd(ReadPC, OpExpr,
6756 TmpInst.addOperand(MCOperand::CreateExpr(FixupAddr));
6758 TmpInst.addOperand(Inst.getOperand(3));
6759 TmpInst.addOperand(Inst.getOperand(4));
6763 // Aliases for alternate PC+imm syntax of LDR instructions.
6764 case ARM::t2LDRpcrel:
6765 // Select the narrow version if the immediate will fit.
6766 if (Inst.getOperand(1).getImm() > 0 &&
6767 Inst.getOperand(1).getImm() <= 0xff &&
6768 !(static_cast<ARMOperand &>(*Operands[2]).isToken() &&
6769 static_cast<ARMOperand &>(*Operands[2]).getToken() == ".w"))
6770 Inst.setOpcode(ARM::tLDRpci);
6772 Inst.setOpcode(ARM::t2LDRpci);
6774 case ARM::t2LDRBpcrel:
6775 Inst.setOpcode(ARM::t2LDRBpci);
6777 case ARM::t2LDRHpcrel:
6778 Inst.setOpcode(ARM::t2LDRHpci);
6780 case ARM::t2LDRSBpcrel:
6781 Inst.setOpcode(ARM::t2LDRSBpci);
6783 case ARM::t2LDRSHpcrel:
6784 Inst.setOpcode(ARM::t2LDRSHpci);
6786 // Handle NEON VST complex aliases.
6787 case ARM::VST1LNdWB_register_Asm_8:
6788 case ARM::VST1LNdWB_register_Asm_16:
6789 case ARM::VST1LNdWB_register_Asm_32: {
6791 // Shuffle the operands around so the lane index operand is in the
6794 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6795 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6796 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6797 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6798 TmpInst.addOperand(Inst.getOperand(4)); // Rm
6799 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6800 TmpInst.addOperand(Inst.getOperand(1)); // lane
6801 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6802 TmpInst.addOperand(Inst.getOperand(6));
6807 case ARM::VST2LNdWB_register_Asm_8:
6808 case ARM::VST2LNdWB_register_Asm_16:
6809 case ARM::VST2LNdWB_register_Asm_32:
6810 case ARM::VST2LNqWB_register_Asm_16:
6811 case ARM::VST2LNqWB_register_Asm_32: {
6813 // Shuffle the operands around so the lane index operand is in the
6816 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6817 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6818 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6819 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6820 TmpInst.addOperand(Inst.getOperand(4)); // Rm
6821 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6822 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6824 TmpInst.addOperand(Inst.getOperand(1)); // lane
6825 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6826 TmpInst.addOperand(Inst.getOperand(6));
6831 case ARM::VST3LNdWB_register_Asm_8:
6832 case ARM::VST3LNdWB_register_Asm_16:
6833 case ARM::VST3LNdWB_register_Asm_32:
6834 case ARM::VST3LNqWB_register_Asm_16:
6835 case ARM::VST3LNqWB_register_Asm_32: {
6837 // Shuffle the operands around so the lane index operand is in the
6840 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6841 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6842 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6843 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6844 TmpInst.addOperand(Inst.getOperand(4)); // Rm
6845 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6846 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6848 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6850 TmpInst.addOperand(Inst.getOperand(1)); // lane
6851 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6852 TmpInst.addOperand(Inst.getOperand(6));
6857 case ARM::VST4LNdWB_register_Asm_8:
6858 case ARM::VST4LNdWB_register_Asm_16:
6859 case ARM::VST4LNdWB_register_Asm_32:
6860 case ARM::VST4LNqWB_register_Asm_16:
6861 case ARM::VST4LNqWB_register_Asm_32: {
6863 // Shuffle the operands around so the lane index operand is in the
6866 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6867 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6868 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6869 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6870 TmpInst.addOperand(Inst.getOperand(4)); // Rm
6871 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6872 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6874 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6876 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6878 TmpInst.addOperand(Inst.getOperand(1)); // lane
6879 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6880 TmpInst.addOperand(Inst.getOperand(6));
6885 case ARM::VST1LNdWB_fixed_Asm_8:
6886 case ARM::VST1LNdWB_fixed_Asm_16:
6887 case ARM::VST1LNdWB_fixed_Asm_32: {
6889 // Shuffle the operands around so the lane index operand is in the
6892 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6893 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6894 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6895 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6896 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6897 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6898 TmpInst.addOperand(Inst.getOperand(1)); // lane
6899 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6900 TmpInst.addOperand(Inst.getOperand(5));
6905 case ARM::VST2LNdWB_fixed_Asm_8:
6906 case ARM::VST2LNdWB_fixed_Asm_16:
6907 case ARM::VST2LNdWB_fixed_Asm_32:
6908 case ARM::VST2LNqWB_fixed_Asm_16:
6909 case ARM::VST2LNqWB_fixed_Asm_32: {
6911 // Shuffle the operands around so the lane index operand is in the
6914 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6915 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6916 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6917 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6918 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6919 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6920 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6922 TmpInst.addOperand(Inst.getOperand(1)); // lane
6923 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6924 TmpInst.addOperand(Inst.getOperand(5));
6929 case ARM::VST3LNdWB_fixed_Asm_8:
6930 case ARM::VST3LNdWB_fixed_Asm_16:
6931 case ARM::VST3LNdWB_fixed_Asm_32:
6932 case ARM::VST3LNqWB_fixed_Asm_16:
6933 case ARM::VST3LNqWB_fixed_Asm_32: {
6935 // Shuffle the operands around so the lane index operand is in the
6938 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6939 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6940 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6941 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6942 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6943 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6944 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6946 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6948 TmpInst.addOperand(Inst.getOperand(1)); // lane
6949 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6950 TmpInst.addOperand(Inst.getOperand(5));
6955 case ARM::VST4LNdWB_fixed_Asm_8:
6956 case ARM::VST4LNdWB_fixed_Asm_16:
6957 case ARM::VST4LNdWB_fixed_Asm_32:
6958 case ARM::VST4LNqWB_fixed_Asm_16:
6959 case ARM::VST4LNqWB_fixed_Asm_32: {
6961 // Shuffle the operands around so the lane index operand is in the
6964 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6965 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6966 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6967 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6968 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6969 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6970 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6972 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6974 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6976 TmpInst.addOperand(Inst.getOperand(1)); // lane
6977 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6978 TmpInst.addOperand(Inst.getOperand(5));
6983 case ARM::VST1LNdAsm_8:
6984 case ARM::VST1LNdAsm_16:
6985 case ARM::VST1LNdAsm_32: {
6987 // Shuffle the operands around so the lane index operand is in the
6990 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6991 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6992 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6993 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6994 TmpInst.addOperand(Inst.getOperand(1)); // lane
6995 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6996 TmpInst.addOperand(Inst.getOperand(5));
7001 case ARM::VST2LNdAsm_8:
7002 case ARM::VST2LNdAsm_16:
7003 case ARM::VST2LNdAsm_32:
7004 case ARM::VST2LNqAsm_16:
7005 case ARM::VST2LNqAsm_32: {
7007 // Shuffle the operands around so the lane index operand is in the
7010 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7011 TmpInst.addOperand(Inst.getOperand(2)); // Rn
7012 TmpInst.addOperand(Inst.getOperand(3)); // alignment
7013 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7014 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7016 TmpInst.addOperand(Inst.getOperand(1)); // lane
7017 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7018 TmpInst.addOperand(Inst.getOperand(5));
7023 case ARM::VST3LNdAsm_8:
7024 case ARM::VST3LNdAsm_16:
7025 case ARM::VST3LNdAsm_32:
7026 case ARM::VST3LNqAsm_16:
7027 case ARM::VST3LNqAsm_32: {
7029 // Shuffle the operands around so the lane index operand is in the
7032 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7033 TmpInst.addOperand(Inst.getOperand(2)); // Rn
7034 TmpInst.addOperand(Inst.getOperand(3)); // alignment
7035 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7036 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7038 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7040 TmpInst.addOperand(Inst.getOperand(1)); // lane
7041 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7042 TmpInst.addOperand(Inst.getOperand(5));
7047 case ARM::VST4LNdAsm_8:
7048 case ARM::VST4LNdAsm_16:
7049 case ARM::VST4LNdAsm_32:
7050 case ARM::VST4LNqAsm_16:
7051 case ARM::VST4LNqAsm_32: {
7053 // Shuffle the operands around so the lane index operand is in the
7056 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7057 TmpInst.addOperand(Inst.getOperand(2)); // Rn
7058 TmpInst.addOperand(Inst.getOperand(3)); // alignment
7059 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7060 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7062 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7064 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7066 TmpInst.addOperand(Inst.getOperand(1)); // lane
7067 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7068 TmpInst.addOperand(Inst.getOperand(5));
7073 // Handle NEON VLD complex aliases.
7074 case ARM::VLD1LNdWB_register_Asm_8:
7075 case ARM::VLD1LNdWB_register_Asm_16:
7076 case ARM::VLD1LNdWB_register_Asm_32: {
7078 // Shuffle the operands around so the lane index operand is in the
7081 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7082 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7083 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
7084 TmpInst.addOperand(Inst.getOperand(2)); // Rn
7085 TmpInst.addOperand(Inst.getOperand(3)); // alignment
7086 TmpInst.addOperand(Inst.getOperand(4)); // Rm
7087 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
7088 TmpInst.addOperand(Inst.getOperand(1)); // lane
7089 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
7090 TmpInst.addOperand(Inst.getOperand(6));
7095 case ARM::VLD2LNdWB_register_Asm_8:
7096 case ARM::VLD2LNdWB_register_Asm_16:
7097 case ARM::VLD2LNdWB_register_Asm_32:
7098 case ARM::VLD2LNqWB_register_Asm_16:
7099 case ARM::VLD2LNqWB_register_Asm_32: {
7101 // Shuffle the operands around so the lane index operand is in the
7104 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7105 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7106 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7108 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
7109 TmpInst.addOperand(Inst.getOperand(2)); // Rn
7110 TmpInst.addOperand(Inst.getOperand(3)); // alignment
7111 TmpInst.addOperand(Inst.getOperand(4)); // Rm
7112 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
7113 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7115 TmpInst.addOperand(Inst.getOperand(1)); // lane
7116 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
7117 TmpInst.addOperand(Inst.getOperand(6));
7122 case ARM::VLD3LNdWB_register_Asm_8:
7123 case ARM::VLD3LNdWB_register_Asm_16:
7124 case ARM::VLD3LNdWB_register_Asm_32:
7125 case ARM::VLD3LNqWB_register_Asm_16:
7126 case ARM::VLD3LNqWB_register_Asm_32: {
7128 // Shuffle the operands around so the lane index operand is in the
7131 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7132 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7133 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7135 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7137 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
7138 TmpInst.addOperand(Inst.getOperand(2)); // Rn
7139 TmpInst.addOperand(Inst.getOperand(3)); // alignment
7140 TmpInst.addOperand(Inst.getOperand(4)); // Rm
7141 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
7142 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7144 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7146 TmpInst.addOperand(Inst.getOperand(1)); // lane
7147 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
7148 TmpInst.addOperand(Inst.getOperand(6));
7153 case ARM::VLD4LNdWB_register_Asm_8:
7154 case ARM::VLD4LNdWB_register_Asm_16:
7155 case ARM::VLD4LNdWB_register_Asm_32:
7156 case ARM::VLD4LNqWB_register_Asm_16:
7157 case ARM::VLD4LNqWB_register_Asm_32: {
7159 // Shuffle the operands around so the lane index operand is in the
7162 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7163 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7164 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7166 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7168 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7170 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
7171 TmpInst.addOperand(Inst.getOperand(2)); // Rn
7172 TmpInst.addOperand(Inst.getOperand(3)); // alignment
7173 TmpInst.addOperand(Inst.getOperand(4)); // Rm
7174 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
7175 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7177 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7179 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7181 TmpInst.addOperand(Inst.getOperand(1)); // lane
7182 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
7183 TmpInst.addOperand(Inst.getOperand(6));
7188 case ARM::VLD1LNdWB_fixed_Asm_8:
7189 case ARM::VLD1LNdWB_fixed_Asm_16:
7190 case ARM::VLD1LNdWB_fixed_Asm_32: {
7192 // Shuffle the operands around so the lane index operand is in the
7195 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7196 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7197 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
7198 TmpInst.addOperand(Inst.getOperand(2)); // Rn
7199 TmpInst.addOperand(Inst.getOperand(3)); // alignment
7200 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
7201 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
7202 TmpInst.addOperand(Inst.getOperand(1)); // lane
7203 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7204 TmpInst.addOperand(Inst.getOperand(5));
7209 case ARM::VLD2LNdWB_fixed_Asm_8:
7210 case ARM::VLD2LNdWB_fixed_Asm_16:
7211 case ARM::VLD2LNdWB_fixed_Asm_32:
7212 case ARM::VLD2LNqWB_fixed_Asm_16:
7213 case ARM::VLD2LNqWB_fixed_Asm_32: {
7215 // Shuffle the operands around so the lane index operand is in the
7218 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7219 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7220 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7222 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
7223 TmpInst.addOperand(Inst.getOperand(2)); // Rn
7224 TmpInst.addOperand(Inst.getOperand(3)); // alignment
7225 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
7226 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
7227 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7229 TmpInst.addOperand(Inst.getOperand(1)); // lane
7230 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7231 TmpInst.addOperand(Inst.getOperand(5));
7236 case ARM::VLD3LNdWB_fixed_Asm_8:
7237 case ARM::VLD3LNdWB_fixed_Asm_16:
7238 case ARM::VLD3LNdWB_fixed_Asm_32:
7239 case ARM::VLD3LNqWB_fixed_Asm_16:
7240 case ARM::VLD3LNqWB_fixed_Asm_32: {
7242 // Shuffle the operands around so the lane index operand is in the
7245 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7246 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7247 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7249 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7251 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
7252 TmpInst.addOperand(Inst.getOperand(2)); // Rn
7253 TmpInst.addOperand(Inst.getOperand(3)); // alignment
7254 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
7255 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
7256 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7258 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7260 TmpInst.addOperand(Inst.getOperand(1)); // lane
7261 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7262 TmpInst.addOperand(Inst.getOperand(5));
7267 case ARM::VLD4LNdWB_fixed_Asm_8:
7268 case ARM::VLD4LNdWB_fixed_Asm_16:
7269 case ARM::VLD4LNdWB_fixed_Asm_32:
7270 case ARM::VLD4LNqWB_fixed_Asm_16:
7271 case ARM::VLD4LNqWB_fixed_Asm_32: {
7273 // Shuffle the operands around so the lane index operand is in the
7276 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7277 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7278 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7280 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7282 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7284 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
7285 TmpInst.addOperand(Inst.getOperand(2)); // Rn
7286 TmpInst.addOperand(Inst.getOperand(3)); // alignment
7287 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
7288 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
7289 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7291 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7293 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7295 TmpInst.addOperand(Inst.getOperand(1)); // lane
7296 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7297 TmpInst.addOperand(Inst.getOperand(5));
7302 case ARM::VLD1LNdAsm_8:
7303 case ARM::VLD1LNdAsm_16:
7304 case ARM::VLD1LNdAsm_32: {
7306 // Shuffle the operands around so the lane index operand is in the
7309 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7310 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7311 TmpInst.addOperand(Inst.getOperand(2)); // Rn
7312 TmpInst.addOperand(Inst.getOperand(3)); // alignment
7313 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
7314 TmpInst.addOperand(Inst.getOperand(1)); // lane
7315 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7316 TmpInst.addOperand(Inst.getOperand(5));
7321 case ARM::VLD2LNdAsm_8:
7322 case ARM::VLD2LNdAsm_16:
7323 case ARM::VLD2LNdAsm_32:
7324 case ARM::VLD2LNqAsm_16:
7325 case ARM::VLD2LNqAsm_32: {
7327 // Shuffle the operands around so the lane index operand is in the
7330 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7331 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7332 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7334 TmpInst.addOperand(Inst.getOperand(2)); // Rn
7335 TmpInst.addOperand(Inst.getOperand(3)); // alignment
7336 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
7337 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7339 TmpInst.addOperand(Inst.getOperand(1)); // lane
7340 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7341 TmpInst.addOperand(Inst.getOperand(5));
7346 case ARM::VLD3LNdAsm_8:
7347 case ARM::VLD3LNdAsm_16:
7348 case ARM::VLD3LNdAsm_32:
7349 case ARM::VLD3LNqAsm_16:
7350 case ARM::VLD3LNqAsm_32: {
7352 // Shuffle the operands around so the lane index operand is in the
7355 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7356 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7357 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7359 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7361 TmpInst.addOperand(Inst.getOperand(2)); // Rn
7362 TmpInst.addOperand(Inst.getOperand(3)); // alignment
7363 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
7364 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7366 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7368 TmpInst.addOperand(Inst.getOperand(1)); // lane
7369 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7370 TmpInst.addOperand(Inst.getOperand(5));
7375 case ARM::VLD4LNdAsm_8:
7376 case ARM::VLD4LNdAsm_16:
7377 case ARM::VLD4LNdAsm_32:
7378 case ARM::VLD4LNqAsm_16:
7379 case ARM::VLD4LNqAsm_32: {
7381 // Shuffle the operands around so the lane index operand is in the
7384 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7385 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7386 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7388 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7390 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7392 TmpInst.addOperand(Inst.getOperand(2)); // Rn
7393 TmpInst.addOperand(Inst.getOperand(3)); // alignment
7394 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
7395 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7397 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7399 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7401 TmpInst.addOperand(Inst.getOperand(1)); // lane
7402 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7403 TmpInst.addOperand(Inst.getOperand(5));
7408 // VLD3DUP single 3-element structure to all lanes instructions.
7409 case ARM::VLD3DUPdAsm_8:
7410 case ARM::VLD3DUPdAsm_16:
7411 case ARM::VLD3DUPdAsm_32:
7412 case ARM::VLD3DUPqAsm_8:
7413 case ARM::VLD3DUPqAsm_16:
7414 case ARM::VLD3DUPqAsm_32: {
7417 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7418 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7419 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7421 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7423 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7424 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7425 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7426 TmpInst.addOperand(Inst.getOperand(4));
7431 case ARM::VLD3DUPdWB_fixed_Asm_8:
7432 case ARM::VLD3DUPdWB_fixed_Asm_16:
7433 case ARM::VLD3DUPdWB_fixed_Asm_32:
7434 case ARM::VLD3DUPqWB_fixed_Asm_8:
7435 case ARM::VLD3DUPqWB_fixed_Asm_16:
7436 case ARM::VLD3DUPqWB_fixed_Asm_32: {
7439 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7440 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7441 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7443 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7445 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7446 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7447 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7448 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
7449 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7450 TmpInst.addOperand(Inst.getOperand(4));
7455 case ARM::VLD3DUPdWB_register_Asm_8:
7456 case ARM::VLD3DUPdWB_register_Asm_16:
7457 case ARM::VLD3DUPdWB_register_Asm_32:
7458 case ARM::VLD3DUPqWB_register_Asm_8:
7459 case ARM::VLD3DUPqWB_register_Asm_16:
7460 case ARM::VLD3DUPqWB_register_Asm_32: {
7463 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7464 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7465 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7467 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7469 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7470 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7471 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7472 TmpInst.addOperand(Inst.getOperand(3)); // Rm
7473 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7474 TmpInst.addOperand(Inst.getOperand(5));
7479 // VLD3 multiple 3-element structure instructions.
7480 case ARM::VLD3dAsm_8:
7481 case ARM::VLD3dAsm_16:
7482 case ARM::VLD3dAsm_32:
7483 case ARM::VLD3qAsm_8:
7484 case ARM::VLD3qAsm_16:
7485 case ARM::VLD3qAsm_32: {
7488 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7489 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7490 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7492 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7494 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7495 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7496 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7497 TmpInst.addOperand(Inst.getOperand(4));
7502 case ARM::VLD3dWB_fixed_Asm_8:
7503 case ARM::VLD3dWB_fixed_Asm_16:
7504 case ARM::VLD3dWB_fixed_Asm_32:
7505 case ARM::VLD3qWB_fixed_Asm_8:
7506 case ARM::VLD3qWB_fixed_Asm_16:
7507 case ARM::VLD3qWB_fixed_Asm_32: {
7510 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7511 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7512 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7514 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7516 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7517 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7518 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7519 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
7520 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7521 TmpInst.addOperand(Inst.getOperand(4));
7526 case ARM::VLD3dWB_register_Asm_8:
7527 case ARM::VLD3dWB_register_Asm_16:
7528 case ARM::VLD3dWB_register_Asm_32:
7529 case ARM::VLD3qWB_register_Asm_8:
7530 case ARM::VLD3qWB_register_Asm_16:
7531 case ARM::VLD3qWB_register_Asm_32: {
7534 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7535 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7536 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7538 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7540 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7541 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7542 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7543 TmpInst.addOperand(Inst.getOperand(3)); // Rm
7544 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7545 TmpInst.addOperand(Inst.getOperand(5));
7550 // VLD4DUP single 3-element structure to all lanes instructions.
7551 case ARM::VLD4DUPdAsm_8:
7552 case ARM::VLD4DUPdAsm_16:
7553 case ARM::VLD4DUPdAsm_32:
7554 case ARM::VLD4DUPqAsm_8:
7555 case ARM::VLD4DUPqAsm_16:
7556 case ARM::VLD4DUPqAsm_32: {
7559 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7560 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7561 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7563 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7565 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7567 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7568 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7569 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7570 TmpInst.addOperand(Inst.getOperand(4));
7575 case ARM::VLD4DUPdWB_fixed_Asm_8:
7576 case ARM::VLD4DUPdWB_fixed_Asm_16:
7577 case ARM::VLD4DUPdWB_fixed_Asm_32:
7578 case ARM::VLD4DUPqWB_fixed_Asm_8:
7579 case ARM::VLD4DUPqWB_fixed_Asm_16:
7580 case ARM::VLD4DUPqWB_fixed_Asm_32: {
7583 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7584 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7585 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7587 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7589 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7591 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7592 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7593 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7594 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
7595 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7596 TmpInst.addOperand(Inst.getOperand(4));
7601 case ARM::VLD4DUPdWB_register_Asm_8:
7602 case ARM::VLD4DUPdWB_register_Asm_16:
7603 case ARM::VLD4DUPdWB_register_Asm_32:
7604 case ARM::VLD4DUPqWB_register_Asm_8:
7605 case ARM::VLD4DUPqWB_register_Asm_16:
7606 case ARM::VLD4DUPqWB_register_Asm_32: {
7609 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7610 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7611 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7613 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7615 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7617 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7618 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7619 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7620 TmpInst.addOperand(Inst.getOperand(3)); // Rm
7621 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7622 TmpInst.addOperand(Inst.getOperand(5));
7627 // VLD4 multiple 4-element structure instructions.
7628 case ARM::VLD4dAsm_8:
7629 case ARM::VLD4dAsm_16:
7630 case ARM::VLD4dAsm_32:
7631 case ARM::VLD4qAsm_8:
7632 case ARM::VLD4qAsm_16:
7633 case ARM::VLD4qAsm_32: {
7636 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7637 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7638 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7640 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7642 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7644 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7645 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7646 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7647 TmpInst.addOperand(Inst.getOperand(4));
7652 case ARM::VLD4dWB_fixed_Asm_8:
7653 case ARM::VLD4dWB_fixed_Asm_16:
7654 case ARM::VLD4dWB_fixed_Asm_32:
7655 case ARM::VLD4qWB_fixed_Asm_8:
7656 case ARM::VLD4qWB_fixed_Asm_16:
7657 case ARM::VLD4qWB_fixed_Asm_32: {
7660 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7661 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7662 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7664 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7666 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7668 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7669 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7670 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7671 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
7672 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7673 TmpInst.addOperand(Inst.getOperand(4));
7678 case ARM::VLD4dWB_register_Asm_8:
7679 case ARM::VLD4dWB_register_Asm_16:
7680 case ARM::VLD4dWB_register_Asm_32:
7681 case ARM::VLD4qWB_register_Asm_8:
7682 case ARM::VLD4qWB_register_Asm_16:
7683 case ARM::VLD4qWB_register_Asm_32: {
7686 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7687 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7688 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7690 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7692 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7694 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7695 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7696 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7697 TmpInst.addOperand(Inst.getOperand(3)); // Rm
7698 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7699 TmpInst.addOperand(Inst.getOperand(5));
7704 // VST3 multiple 3-element structure instructions.
7705 case ARM::VST3dAsm_8:
7706 case ARM::VST3dAsm_16:
7707 case ARM::VST3dAsm_32:
7708 case ARM::VST3qAsm_8:
7709 case ARM::VST3qAsm_16:
7710 case ARM::VST3qAsm_32: {
7713 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7714 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7715 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7716 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7717 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7719 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7721 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7722 TmpInst.addOperand(Inst.getOperand(4));
7727 case ARM::VST3dWB_fixed_Asm_8:
7728 case ARM::VST3dWB_fixed_Asm_16:
7729 case ARM::VST3dWB_fixed_Asm_32:
7730 case ARM::VST3qWB_fixed_Asm_8:
7731 case ARM::VST3qWB_fixed_Asm_16:
7732 case ARM::VST3qWB_fixed_Asm_32: {
7735 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7736 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7737 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7738 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7739 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
7740 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7741 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7743 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7745 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7746 TmpInst.addOperand(Inst.getOperand(4));
7751 case ARM::VST3dWB_register_Asm_8:
7752 case ARM::VST3dWB_register_Asm_16:
7753 case ARM::VST3dWB_register_Asm_32:
7754 case ARM::VST3qWB_register_Asm_8:
7755 case ARM::VST3qWB_register_Asm_16:
7756 case ARM::VST3qWB_register_Asm_32: {
7759 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7760 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7761 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7762 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7763 TmpInst.addOperand(Inst.getOperand(3)); // Rm
7764 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7765 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7767 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7769 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7770 TmpInst.addOperand(Inst.getOperand(5));
7775 // VST4 multiple 3-element structure instructions.
7776 case ARM::VST4dAsm_8:
7777 case ARM::VST4dAsm_16:
7778 case ARM::VST4dAsm_32:
7779 case ARM::VST4qAsm_8:
7780 case ARM::VST4qAsm_16:
7781 case ARM::VST4qAsm_32: {
7784 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7785 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7786 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7787 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7788 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7790 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7792 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7794 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7795 TmpInst.addOperand(Inst.getOperand(4));
7800 case ARM::VST4dWB_fixed_Asm_8:
7801 case ARM::VST4dWB_fixed_Asm_16:
7802 case ARM::VST4dWB_fixed_Asm_32:
7803 case ARM::VST4qWB_fixed_Asm_8:
7804 case ARM::VST4qWB_fixed_Asm_16:
7805 case ARM::VST4qWB_fixed_Asm_32: {
7808 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7809 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7810 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7811 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7812 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
7813 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7814 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7816 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7818 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7820 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7821 TmpInst.addOperand(Inst.getOperand(4));
7826 case ARM::VST4dWB_register_Asm_8:
7827 case ARM::VST4dWB_register_Asm_16:
7828 case ARM::VST4dWB_register_Asm_32:
7829 case ARM::VST4qWB_register_Asm_8:
7830 case ARM::VST4qWB_register_Asm_16:
7831 case ARM::VST4qWB_register_Asm_32: {
7834 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7835 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7836 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7837 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7838 TmpInst.addOperand(Inst.getOperand(3)); // Rm
7839 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7840 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7842 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7844 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7846 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7847 TmpInst.addOperand(Inst.getOperand(5));
7852 // Handle encoding choice for the shift-immediate instructions.
7855 case ARM::t2ASRri: {
7856 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7857 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
7858 Inst.getOperand(5).getReg() == (inITBlock() ? 0 : ARM::CPSR) &&
7859 !(static_cast<ARMOperand &>(*Operands[3]).isToken() &&
7860 static_cast<ARMOperand &>(*Operands[3]).getToken() == ".w")) {
7862 switch (Inst.getOpcode()) {
7863 default: llvm_unreachable("unexpected opcode");
7864 case ARM::t2LSLri: NewOpc = ARM::tLSLri; break;
7865 case ARM::t2LSRri: NewOpc = ARM::tLSRri; break;
7866 case ARM::t2ASRri: NewOpc = ARM::tASRri; break;
7868 // The Thumb1 operands aren't in the same order. Awesome, eh?
7870 TmpInst.setOpcode(NewOpc);
7871 TmpInst.addOperand(Inst.getOperand(0));
7872 TmpInst.addOperand(Inst.getOperand(5));
7873 TmpInst.addOperand(Inst.getOperand(1));
7874 TmpInst.addOperand(Inst.getOperand(2));
7875 TmpInst.addOperand(Inst.getOperand(3));
7876 TmpInst.addOperand(Inst.getOperand(4));
7883 // Handle the Thumb2 mode MOV complex aliases.
7885 case ARM::t2MOVSsr: {
7886 // Which instruction to expand to depends on the CCOut operand and
7887 // whether we're in an IT block if the register operands are low
7889 bool isNarrow = false;
7890 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7891 isARMLowRegister(Inst.getOperand(1).getReg()) &&
7892 isARMLowRegister(Inst.getOperand(2).getReg()) &&
7893 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
7894 inITBlock() == (Inst.getOpcode() == ARM::t2MOVsr))
7898 switch(ARM_AM::getSORegShOp(Inst.getOperand(3).getImm())) {
7899 default: llvm_unreachable("unexpected opcode!");
7900 case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRrr : ARM::t2ASRrr; break;
7901 case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRrr : ARM::t2LSRrr; break;
7902 case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLrr : ARM::t2LSLrr; break;
7903 case ARM_AM::ror: newOpc = isNarrow ? ARM::tROR : ARM::t2RORrr; break;
7905 TmpInst.setOpcode(newOpc);
7906 TmpInst.addOperand(Inst.getOperand(0)); // Rd
7908 TmpInst.addOperand(MCOperand::CreateReg(
7909 Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0));
7910 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7911 TmpInst.addOperand(Inst.getOperand(2)); // Rm
7912 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7913 TmpInst.addOperand(Inst.getOperand(5));
7915 TmpInst.addOperand(MCOperand::CreateReg(
7916 Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0));
7921 case ARM::t2MOVSsi: {
7922 // Which instruction to expand to depends on the CCOut operand and
7923 // whether we're in an IT block if the register operands are low
7925 bool isNarrow = false;
7926 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7927 isARMLowRegister(Inst.getOperand(1).getReg()) &&
7928 inITBlock() == (Inst.getOpcode() == ARM::t2MOVsi))
7932 switch(ARM_AM::getSORegShOp(Inst.getOperand(2).getImm())) {
7933 default: llvm_unreachable("unexpected opcode!");
7934 case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRri : ARM::t2ASRri; break;
7935 case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRri : ARM::t2LSRri; break;
7936 case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLri : ARM::t2LSLri; break;
7937 case ARM_AM::ror: newOpc = ARM::t2RORri; isNarrow = false; break;
7938 case ARM_AM::rrx: isNarrow = false; newOpc = ARM::t2RRX; break;
7940 unsigned Amount = ARM_AM::getSORegOffset(Inst.getOperand(2).getImm());
7941 if (Amount == 32) Amount = 0;
7942 TmpInst.setOpcode(newOpc);
7943 TmpInst.addOperand(Inst.getOperand(0)); // Rd
7945 TmpInst.addOperand(MCOperand::CreateReg(
7946 Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0));
7947 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7948 if (newOpc != ARM::t2RRX)
7949 TmpInst.addOperand(MCOperand::CreateImm(Amount));
7950 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7951 TmpInst.addOperand(Inst.getOperand(4));
7953 TmpInst.addOperand(MCOperand::CreateReg(
7954 Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0));
7958 // Handle the ARM mode MOV complex aliases.
7963 ARM_AM::ShiftOpc ShiftTy;
7964 switch(Inst.getOpcode()) {
7965 default: llvm_unreachable("unexpected opcode!");
7966 case ARM::ASRr: ShiftTy = ARM_AM::asr; break;
7967 case ARM::LSRr: ShiftTy = ARM_AM::lsr; break;
7968 case ARM::LSLr: ShiftTy = ARM_AM::lsl; break;
7969 case ARM::RORr: ShiftTy = ARM_AM::ror; break;
7971 unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, 0);
7973 TmpInst.setOpcode(ARM::MOVsr);
7974 TmpInst.addOperand(Inst.getOperand(0)); // Rd
7975 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7976 TmpInst.addOperand(Inst.getOperand(2)); // Rm
7977 TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty
7978 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7979 TmpInst.addOperand(Inst.getOperand(4));
7980 TmpInst.addOperand(Inst.getOperand(5)); // cc_out
7988 ARM_AM::ShiftOpc ShiftTy;
7989 switch(Inst.getOpcode()) {
7990 default: llvm_unreachable("unexpected opcode!");
7991 case ARM::ASRi: ShiftTy = ARM_AM::asr; break;
7992 case ARM::LSRi: ShiftTy = ARM_AM::lsr; break;
7993 case ARM::LSLi: ShiftTy = ARM_AM::lsl; break;
7994 case ARM::RORi: ShiftTy = ARM_AM::ror; break;
7996 // A shift by zero is a plain MOVr, not a MOVsi.
7997 unsigned Amt = Inst.getOperand(2).getImm();
7998 unsigned Opc = Amt == 0 ? ARM::MOVr : ARM::MOVsi;
7999 // A shift by 32 should be encoded as 0 when permitted
8000 if (Amt == 32 && (ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr))
8002 unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, Amt);
8004 TmpInst.setOpcode(Opc);
8005 TmpInst.addOperand(Inst.getOperand(0)); // Rd
8006 TmpInst.addOperand(Inst.getOperand(1)); // Rn
8007 if (Opc == ARM::MOVsi)
8008 TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty
8009 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
8010 TmpInst.addOperand(Inst.getOperand(4));
8011 TmpInst.addOperand(Inst.getOperand(5)); // cc_out
8016 unsigned Shifter = ARM_AM::getSORegOpc(ARM_AM::rrx, 0);
8018 TmpInst.setOpcode(ARM::MOVsi);
8019 TmpInst.addOperand(Inst.getOperand(0)); // Rd
8020 TmpInst.addOperand(Inst.getOperand(1)); // Rn
8021 TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty
8022 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
8023 TmpInst.addOperand(Inst.getOperand(3));
8024 TmpInst.addOperand(Inst.getOperand(4)); // cc_out
8028 case ARM::t2LDMIA_UPD: {
8029 // If this is a load of a single register, then we should use
8030 // a post-indexed LDR instruction instead, per the ARM ARM.
8031 if (Inst.getNumOperands() != 5)
8034 TmpInst.setOpcode(ARM::t2LDR_POST);
8035 TmpInst.addOperand(Inst.getOperand(4)); // Rt
8036 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
8037 TmpInst.addOperand(Inst.getOperand(1)); // Rn
8038 TmpInst.addOperand(MCOperand::CreateImm(4));
8039 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
8040 TmpInst.addOperand(Inst.getOperand(3));
8044 case ARM::t2STMDB_UPD: {
8045 // If this is a store of a single register, then we should use
8046 // a pre-indexed STR instruction instead, per the ARM ARM.
8047 if (Inst.getNumOperands() != 5)
8050 TmpInst.setOpcode(ARM::t2STR_PRE);
8051 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
8052 TmpInst.addOperand(Inst.getOperand(4)); // Rt
8053 TmpInst.addOperand(Inst.getOperand(1)); // Rn
8054 TmpInst.addOperand(MCOperand::CreateImm(-4));
8055 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
8056 TmpInst.addOperand(Inst.getOperand(3));
8060 case ARM::LDMIA_UPD:
8061 // If this is a load of a single register via a 'pop', then we should use
8062 // a post-indexed LDR instruction instead, per the ARM ARM.
8063 if (static_cast<ARMOperand &>(*Operands[0]).getToken() == "pop" &&
8064 Inst.getNumOperands() == 5) {
8066 TmpInst.setOpcode(ARM::LDR_POST_IMM);
8067 TmpInst.addOperand(Inst.getOperand(4)); // Rt
8068 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
8069 TmpInst.addOperand(Inst.getOperand(1)); // Rn
8070 TmpInst.addOperand(MCOperand::CreateReg(0)); // am2offset
8071 TmpInst.addOperand(MCOperand::CreateImm(4));
8072 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
8073 TmpInst.addOperand(Inst.getOperand(3));
8078 case ARM::STMDB_UPD:
8079 // If this is a store of a single register via a 'push', then we should use
8080 // a pre-indexed STR instruction instead, per the ARM ARM.
8081 if (static_cast<ARMOperand &>(*Operands[0]).getToken() == "push" &&
8082 Inst.getNumOperands() == 5) {
8084 TmpInst.setOpcode(ARM::STR_PRE_IMM);
8085 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
8086 TmpInst.addOperand(Inst.getOperand(4)); // Rt
8087 TmpInst.addOperand(Inst.getOperand(1)); // addrmode_imm12
8088 TmpInst.addOperand(MCOperand::CreateImm(-4));
8089 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
8090 TmpInst.addOperand(Inst.getOperand(3));
8094 case ARM::t2ADDri12:
8095 // If the immediate fits for encoding T3 (t2ADDri) and the generic "add"
8096 // mnemonic was used (not "addw"), encoding T3 is preferred.
8097 if (static_cast<ARMOperand &>(*Operands[0]).getToken() != "add" ||
8098 ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1)
8100 Inst.setOpcode(ARM::t2ADDri);
8101 Inst.addOperand(MCOperand::CreateReg(0)); // cc_out
8103 case ARM::t2SUBri12:
8104 // If the immediate fits for encoding T3 (t2SUBri) and the generic "sub"
8105 // mnemonic was used (not "subw"), encoding T3 is preferred.
8106 if (static_cast<ARMOperand &>(*Operands[0]).getToken() != "sub" ||
8107 ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1)
8109 Inst.setOpcode(ARM::t2SUBri);
8110 Inst.addOperand(MCOperand::CreateReg(0)); // cc_out
8113 // If the immediate is in the range 0-7, we want tADDi3 iff Rd was
8114 // explicitly specified. From the ARM ARM: "Encoding T1 is preferred
8115 // to encoding T2 if <Rd> is specified and encoding T2 is preferred
8116 // to encoding T1 if <Rd> is omitted."
8117 if ((unsigned)Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) {
8118 Inst.setOpcode(ARM::tADDi3);
8123 // If the immediate is in the range 0-7, we want tADDi3 iff Rd was
8124 // explicitly specified. From the ARM ARM: "Encoding T1 is preferred
8125 // to encoding T2 if <Rd> is specified and encoding T2 is preferred
8126 // to encoding T1 if <Rd> is omitted."
8127 if ((unsigned)Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) {
8128 Inst.setOpcode(ARM::tSUBi3);
8133 case ARM::t2SUBri: {
8134 // If the destination and first source operand are the same, and
8135 // the flags are compatible with the current IT status, use encoding T2
8136 // instead of T3. For compatibility with the system 'as'. Make sure the
8137 // wide encoding wasn't explicit.
8138 if (Inst.getOperand(0).getReg() != Inst.getOperand(1).getReg() ||
8139 !isARMLowRegister(Inst.getOperand(0).getReg()) ||
8140 (unsigned)Inst.getOperand(2).getImm() > 255 ||
8141 ((!inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR) ||
8142 (inITBlock() && Inst.getOperand(5).getReg() != 0)) ||
8143 (static_cast<ARMOperand &>(*Operands[3]).isToken() &&
8144 static_cast<ARMOperand &>(*Operands[3]).getToken() == ".w"))
8147 TmpInst.setOpcode(Inst.getOpcode() == ARM::t2ADDri ?
8148 ARM::tADDi8 : ARM::tSUBi8);
8149 TmpInst.addOperand(Inst.getOperand(0));
8150 TmpInst.addOperand(Inst.getOperand(5));
8151 TmpInst.addOperand(Inst.getOperand(0));
8152 TmpInst.addOperand(Inst.getOperand(2));
8153 TmpInst.addOperand(Inst.getOperand(3));
8154 TmpInst.addOperand(Inst.getOperand(4));
8158 case ARM::t2ADDrr: {
8159 // If the destination and first source operand are the same, and
8160 // there's no setting of the flags, use encoding T2 instead of T3.
8161 // Note that this is only for ADD, not SUB. This mirrors the system
8162 // 'as' behaviour. Make sure the wide encoding wasn't explicit.
8163 if (Inst.getOperand(0).getReg() != Inst.getOperand(1).getReg() ||
8164 Inst.getOperand(5).getReg() != 0 ||
8165 (static_cast<ARMOperand &>(*Operands[3]).isToken() &&
8166 static_cast<ARMOperand &>(*Operands[3]).getToken() == ".w"))
8169 TmpInst.setOpcode(ARM::tADDhirr);
8170 TmpInst.addOperand(Inst.getOperand(0));
8171 TmpInst.addOperand(Inst.getOperand(0));
8172 TmpInst.addOperand(Inst.getOperand(2));
8173 TmpInst.addOperand(Inst.getOperand(3));
8174 TmpInst.addOperand(Inst.getOperand(4));
8178 case ARM::tADDrSP: {
8179 // If the non-SP source operand and the destination operand are not the
8180 // same, we need to use the 32-bit encoding if it's available.
8181 if (Inst.getOperand(0).getReg() != Inst.getOperand(2).getReg()) {
8182 Inst.setOpcode(ARM::t2ADDrr);
8183 Inst.addOperand(MCOperand::CreateReg(0)); // cc_out
8189 // A Thumb conditional branch outside of an IT block is a tBcc.
8190 if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()) {
8191 Inst.setOpcode(ARM::tBcc);
8196 // A Thumb2 conditional branch outside of an IT block is a t2Bcc.
8197 if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()){
8198 Inst.setOpcode(ARM::t2Bcc);
8203 // If the conditional is AL or we're in an IT block, we really want t2B.
8204 if (Inst.getOperand(1).getImm() == ARMCC::AL || inITBlock()) {
8205 Inst.setOpcode(ARM::t2B);
8210 // If the conditional is AL, we really want tB.
8211 if (Inst.getOperand(1).getImm() == ARMCC::AL) {
8212 Inst.setOpcode(ARM::tB);
8217 // If the register list contains any high registers, or if the writeback
8218 // doesn't match what tLDMIA can do, we need to use the 32-bit encoding
8219 // instead if we're in Thumb2. Otherwise, this should have generated
8220 // an error in validateInstruction().
8221 unsigned Rn = Inst.getOperand(0).getReg();
8222 bool hasWritebackToken =
8223 (static_cast<ARMOperand &>(*Operands[3]).isToken() &&
8224 static_cast<ARMOperand &>(*Operands[3]).getToken() == "!");
8225 bool listContainsBase;
8226 if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase) ||
8227 (!listContainsBase && !hasWritebackToken) ||
8228 (listContainsBase && hasWritebackToken)) {
8229 // 16-bit encoding isn't sufficient. Switch to the 32-bit version.
8230 assert (isThumbTwo());
8231 Inst.setOpcode(hasWritebackToken ? ARM::t2LDMIA_UPD : ARM::t2LDMIA);
8232 // If we're switching to the updating version, we need to insert
8233 // the writeback tied operand.
8234 if (hasWritebackToken)
8235 Inst.insert(Inst.begin(),
8236 MCOperand::CreateReg(Inst.getOperand(0).getReg()));
8241 case ARM::tSTMIA_UPD: {
8242 // If the register list contains any high registers, we need to use
8243 // the 32-bit encoding instead if we're in Thumb2. Otherwise, this
8244 // should have generated an error in validateInstruction().
8245 unsigned Rn = Inst.getOperand(0).getReg();
8246 bool listContainsBase;
8247 if (checkLowRegisterList(Inst, 4, Rn, 0, listContainsBase)) {
8248 // 16-bit encoding isn't sufficient. Switch to the 32-bit version.
8249 assert (isThumbTwo());
8250 Inst.setOpcode(ARM::t2STMIA_UPD);
8256 bool listContainsBase;
8257 // If the register list contains any high registers, we need to use
8258 // the 32-bit encoding instead if we're in Thumb2. Otherwise, this
8259 // should have generated an error in validateInstruction().
8260 if (!checkLowRegisterList(Inst, 2, 0, ARM::PC, listContainsBase))
8262 assert (isThumbTwo());
8263 Inst.setOpcode(ARM::t2LDMIA_UPD);
8264 // Add the base register and writeback operands.
8265 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
8266 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
8270 bool listContainsBase;
8271 if (!checkLowRegisterList(Inst, 2, 0, ARM::LR, listContainsBase))
8273 assert (isThumbTwo());
8274 Inst.setOpcode(ARM::t2STMDB_UPD);
8275 // Add the base register and writeback operands.
8276 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
8277 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
8281 // If we can use the 16-bit encoding and the user didn't explicitly
8282 // request the 32-bit variant, transform it here.
8283 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
8284 (unsigned)Inst.getOperand(1).getImm() <= 255 &&
8285 ((!inITBlock() && Inst.getOperand(2).getImm() == ARMCC::AL &&
8286 Inst.getOperand(4).getReg() == ARM::CPSR) ||
8287 (inITBlock() && Inst.getOperand(4).getReg() == 0)) &&
8288 (!static_cast<ARMOperand &>(*Operands[2]).isToken() ||
8289 static_cast<ARMOperand &>(*Operands[2]).getToken() != ".w")) {
8290 // The operands aren't in the same order for tMOVi8...
8292 TmpInst.setOpcode(ARM::tMOVi8);
8293 TmpInst.addOperand(Inst.getOperand(0));
8294 TmpInst.addOperand(Inst.getOperand(4));
8295 TmpInst.addOperand(Inst.getOperand(1));
8296 TmpInst.addOperand(Inst.getOperand(2));
8297 TmpInst.addOperand(Inst.getOperand(3));
8304 // If we can use the 16-bit encoding and the user didn't explicitly
8305 // request the 32-bit variant, transform it here.
8306 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
8307 isARMLowRegister(Inst.getOperand(1).getReg()) &&
8308 Inst.getOperand(2).getImm() == ARMCC::AL &&
8309 Inst.getOperand(4).getReg() == ARM::CPSR &&
8310 (!static_cast<ARMOperand &>(*Operands[2]).isToken() ||
8311 static_cast<ARMOperand &>(*Operands[2]).getToken() != ".w")) {
8312 // The operands aren't the same for tMOV[S]r... (no cc_out)
8314 TmpInst.setOpcode(Inst.getOperand(4).getReg() ? ARM::tMOVSr : ARM::tMOVr);
8315 TmpInst.addOperand(Inst.getOperand(0));
8316 TmpInst.addOperand(Inst.getOperand(1));
8317 TmpInst.addOperand(Inst.getOperand(2));
8318 TmpInst.addOperand(Inst.getOperand(3));
8328 // If we can use the 16-bit encoding and the user didn't explicitly
8329 // request the 32-bit variant, transform it here.
8330 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
8331 isARMLowRegister(Inst.getOperand(1).getReg()) &&
8332 Inst.getOperand(2).getImm() == 0 &&
8333 (!static_cast<ARMOperand &>(*Operands[2]).isToken() ||
8334 static_cast<ARMOperand &>(*Operands[2]).getToken() != ".w")) {
8336 switch (Inst.getOpcode()) {
8337 default: llvm_unreachable("Illegal opcode!");
8338 case ARM::t2SXTH: NewOpc = ARM::tSXTH; break;
8339 case ARM::t2SXTB: NewOpc = ARM::tSXTB; break;
8340 case ARM::t2UXTH: NewOpc = ARM::tUXTH; break;
8341 case ARM::t2UXTB: NewOpc = ARM::tUXTB; break;
8343 // The operands aren't the same for thumb1 (no rotate operand).
8345 TmpInst.setOpcode(NewOpc);
8346 TmpInst.addOperand(Inst.getOperand(0));
8347 TmpInst.addOperand(Inst.getOperand(1));
8348 TmpInst.addOperand(Inst.getOperand(3));
8349 TmpInst.addOperand(Inst.getOperand(4));
8356 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(2).getImm());
8357 // rrx shifts and asr/lsr of #32 is encoded as 0
8358 if (SOpc == ARM_AM::rrx || SOpc == ARM_AM::asr || SOpc == ARM_AM::lsr)
8360 if (ARM_AM::getSORegOffset(Inst.getOperand(2).getImm()) == 0) {
8361 // Shifting by zero is accepted as a vanilla 'MOVr'
8363 TmpInst.setOpcode(ARM::MOVr);
8364 TmpInst.addOperand(Inst.getOperand(0));
8365 TmpInst.addOperand(Inst.getOperand(1));
8366 TmpInst.addOperand(Inst.getOperand(3));
8367 TmpInst.addOperand(Inst.getOperand(4));
8368 TmpInst.addOperand(Inst.getOperand(5));
8381 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(3).getImm());
8382 if (SOpc == ARM_AM::rrx) return false;
8383 switch (Inst.getOpcode()) {
8384 default: llvm_unreachable("unexpected opcode!");
8385 case ARM::ANDrsi: newOpc = ARM::ANDrr; break;
8386 case ARM::ORRrsi: newOpc = ARM::ORRrr; break;
8387 case ARM::EORrsi: newOpc = ARM::EORrr; break;
8388 case ARM::BICrsi: newOpc = ARM::BICrr; break;
8389 case ARM::SUBrsi: newOpc = ARM::SUBrr; break;
8390 case ARM::ADDrsi: newOpc = ARM::ADDrr; break;
8392 // If the shift is by zero, use the non-shifted instruction definition.
8393 // The exception is for right shifts, where 0 == 32
8394 if (ARM_AM::getSORegOffset(Inst.getOperand(3).getImm()) == 0 &&
8395 !(SOpc == ARM_AM::lsr || SOpc == ARM_AM::asr)) {
8397 TmpInst.setOpcode(newOpc);
8398 TmpInst.addOperand(Inst.getOperand(0));
8399 TmpInst.addOperand(Inst.getOperand(1));
8400 TmpInst.addOperand(Inst.getOperand(2));
8401 TmpInst.addOperand(Inst.getOperand(4));
8402 TmpInst.addOperand(Inst.getOperand(5));
8403 TmpInst.addOperand(Inst.getOperand(6));
8411 // The mask bits for all but the first condition are represented as
8412 // the low bit of the condition code value implies 't'. We currently
8413 // always have 1 implies 't', so XOR toggle the bits if the low bit
8414 // of the condition code is zero.
8415 MCOperand &MO = Inst.getOperand(1);
8416 unsigned Mask = MO.getImm();
8417 unsigned OrigMask = Mask;
8418 unsigned TZ = countTrailingZeros(Mask);
8419 if ((Inst.getOperand(0).getImm() & 1) == 0) {
8420 assert(Mask && TZ <= 3 && "illegal IT mask value!");
8421 Mask ^= (0xE << TZ) & 0xF;
8425 // Set up the IT block state according to the IT instruction we just
8427 assert(!inITBlock() && "nested IT blocks?!");
8428 ITState.Cond = ARMCC::CondCodes(Inst.getOperand(0).getImm());
8429 ITState.Mask = OrigMask; // Use the original mask, not the updated one.
8430 ITState.CurPosition = 0;
8431 ITState.FirstCond = true;
8441 // Assemblers should use the narrow encodings of these instructions when permissible.
8442 if ((isARMLowRegister(Inst.getOperand(1).getReg()) &&
8443 isARMLowRegister(Inst.getOperand(2).getReg())) &&
8444 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
8445 ((!inITBlock() && Inst.getOperand(5).getReg() == ARM::CPSR) ||
8446 (inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR)) &&
8447 (!static_cast<ARMOperand &>(*Operands[3]).isToken() ||
8448 !static_cast<ARMOperand &>(*Operands[3]).getToken().equals_lower(
8451 switch (Inst.getOpcode()) {
8452 default: llvm_unreachable("unexpected opcode");
8453 case ARM::t2LSLrr: NewOpc = ARM::tLSLrr; break;
8454 case ARM::t2LSRrr: NewOpc = ARM::tLSRrr; break;
8455 case ARM::t2ASRrr: NewOpc = ARM::tASRrr; break;
8456 case ARM::t2SBCrr: NewOpc = ARM::tSBC; break;
8457 case ARM::t2RORrr: NewOpc = ARM::tROR; break;
8458 case ARM::t2BICrr: NewOpc = ARM::tBIC; break;
8461 TmpInst.setOpcode(NewOpc);
8462 TmpInst.addOperand(Inst.getOperand(0));
8463 TmpInst.addOperand(Inst.getOperand(5));
8464 TmpInst.addOperand(Inst.getOperand(1));
8465 TmpInst.addOperand(Inst.getOperand(2));
8466 TmpInst.addOperand(Inst.getOperand(3));
8467 TmpInst.addOperand(Inst.getOperand(4));
8478 // Assemblers should use the narrow encodings of these instructions when permissible.
8479 // These instructions are special in that they are commutable, so shorter encodings
8480 // are available more often.
8481 if ((isARMLowRegister(Inst.getOperand(1).getReg()) &&
8482 isARMLowRegister(Inst.getOperand(2).getReg())) &&
8483 (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() ||
8484 Inst.getOperand(0).getReg() == Inst.getOperand(2).getReg()) &&
8485 ((!inITBlock() && Inst.getOperand(5).getReg() == ARM::CPSR) ||
8486 (inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR)) &&
8487 (!static_cast<ARMOperand &>(*Operands[3]).isToken() ||
8488 !static_cast<ARMOperand &>(*Operands[3]).getToken().equals_lower(
8491 switch (Inst.getOpcode()) {
8492 default: llvm_unreachable("unexpected opcode");
8493 case ARM::t2ADCrr: NewOpc = ARM::tADC; break;
8494 case ARM::t2ANDrr: NewOpc = ARM::tAND; break;
8495 case ARM::t2EORrr: NewOpc = ARM::tEOR; break;
8496 case ARM::t2ORRrr: NewOpc = ARM::tORR; break;
8499 TmpInst.setOpcode(NewOpc);
8500 TmpInst.addOperand(Inst.getOperand(0));
8501 TmpInst.addOperand(Inst.getOperand(5));
8502 if (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()) {
8503 TmpInst.addOperand(Inst.getOperand(1));
8504 TmpInst.addOperand(Inst.getOperand(2));
8506 TmpInst.addOperand(Inst.getOperand(2));
8507 TmpInst.addOperand(Inst.getOperand(1));
8509 TmpInst.addOperand(Inst.getOperand(3));
8510 TmpInst.addOperand(Inst.getOperand(4));
8520 unsigned ARMAsmParser::checkTargetMatchPredicate(MCInst &Inst) {
8521 // 16-bit thumb arithmetic instructions either require or preclude the 'S'
8522 // suffix depending on whether they're in an IT block or not.
8523 unsigned Opc = Inst.getOpcode();
8524 const MCInstrDesc &MCID = MII.get(Opc);
8525 if (MCID.TSFlags & ARMII::ThumbArithFlagSetting) {
8526 assert(MCID.hasOptionalDef() &&
8527 "optionally flag setting instruction missing optional def operand");
8528 assert(MCID.NumOperands == Inst.getNumOperands() &&
8529 "operand count mismatch!");
8530 // Find the optional-def operand (cc_out).
8533 !MCID.OpInfo[OpNo].isOptionalDef() && OpNo < MCID.NumOperands;
8536 // If we're parsing Thumb1, reject it completely.
8537 if (isThumbOne() && Inst.getOperand(OpNo).getReg() != ARM::CPSR)
8538 return Match_MnemonicFail;
8539 // If we're parsing Thumb2, which form is legal depends on whether we're
8541 if (isThumbTwo() && Inst.getOperand(OpNo).getReg() != ARM::CPSR &&
8543 return Match_RequiresITBlock;
8544 if (isThumbTwo() && Inst.getOperand(OpNo).getReg() == ARM::CPSR &&
8546 return Match_RequiresNotITBlock;
8548 // Some high-register supporting Thumb1 encodings only allow both registers
8549 // to be from r0-r7 when in Thumb2.
8550 else if (Opc == ARM::tADDhirr && isThumbOne() && !hasV6MOps() &&
8551 isARMLowRegister(Inst.getOperand(1).getReg()) &&
8552 isARMLowRegister(Inst.getOperand(2).getReg()))
8553 return Match_RequiresThumb2;
8554 // Others only require ARMv6 or later.
8555 else if (Opc == ARM::tMOVr && isThumbOne() && !hasV6Ops() &&
8556 isARMLowRegister(Inst.getOperand(0).getReg()) &&
8557 isARMLowRegister(Inst.getOperand(1).getReg()))
8558 return Match_RequiresV6;
8559 return Match_Success;
8563 template <> inline bool IsCPSRDead<MCInst>(MCInst *Instr) {
8564 return true; // In an assembly source, no need to second-guess
8568 static const char *getSubtargetFeatureName(uint64_t Val);
8569 bool ARMAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
8570 OperandVector &Operands,
8571 MCStreamer &Out, uint64_t &ErrorInfo,
8572 bool MatchingInlineAsm) {
8574 unsigned MatchResult;
8576 MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo,
8578 switch (MatchResult) {
8580 // Context sensitive operand constraints aren't handled by the matcher,
8581 // so check them here.
8582 if (validateInstruction(Inst, Operands)) {
8583 // Still progress the IT block, otherwise one wrong condition causes
8584 // nasty cascading errors.
8585 forwardITPosition();
8589 { // processInstruction() updates inITBlock state, we need to save it away
8590 bool wasInITBlock = inITBlock();
8592 // Some instructions need post-processing to, for example, tweak which
8593 // encoding is selected. Loop on it while changes happen so the
8594 // individual transformations can chain off each other. E.g.,
8595 // tPOP(r8)->t2LDMIA_UPD(sp,r8)->t2STR_POST(sp,r8)
8596 while (processInstruction(Inst, Operands, Out))
8599 // Only after the instruction is fully processed, we can validate it
8600 if (wasInITBlock && hasV8Ops() && isThumb() &&
8601 !isV8EligibleForIT(&Inst)) {
8602 Warning(IDLoc, "deprecated instruction in IT block");
8606 // Only move forward at the very end so that everything in validate
8607 // and process gets a consistent answer about whether we're in an IT
8609 forwardITPosition();
8611 // ITasm is an ARM mode pseudo-instruction that just sets the ITblock and
8612 // doesn't actually encode.
8613 if (Inst.getOpcode() == ARM::ITasm)
8617 Out.EmitInstruction(Inst, STI);
8619 case Match_MissingFeature: {
8620 assert(ErrorInfo && "Unknown missing feature!");
8621 // Special case the error message for the very common case where only
8622 // a single subtarget feature is missing (Thumb vs. ARM, e.g.).
8623 std::string Msg = "instruction requires:";
8625 for (unsigned i = 0; i < (sizeof(ErrorInfo)*8-1); ++i) {
8626 if (ErrorInfo & Mask) {
8628 Msg += getSubtargetFeatureName(ErrorInfo & Mask);
8632 return Error(IDLoc, Msg);
8634 case Match_InvalidOperand: {
8635 SMLoc ErrorLoc = IDLoc;
8636 if (ErrorInfo != ~0ULL) {
8637 if (ErrorInfo >= Operands.size())
8638 return Error(IDLoc, "too few operands for instruction");
8640 ErrorLoc = ((ARMOperand &)*Operands[ErrorInfo]).getStartLoc();
8641 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
8644 return Error(ErrorLoc, "invalid operand for instruction");
8646 case Match_MnemonicFail:
8647 return Error(IDLoc, "invalid instruction",
8648 ((ARMOperand &)*Operands[0]).getLocRange());
8649 case Match_RequiresNotITBlock:
8650 return Error(IDLoc, "flag setting instruction only valid outside IT block");
8651 case Match_RequiresITBlock:
8652 return Error(IDLoc, "instruction only valid inside IT block");
8653 case Match_RequiresV6:
8654 return Error(IDLoc, "instruction variant requires ARMv6 or later");
8655 case Match_RequiresThumb2:
8656 return Error(IDLoc, "instruction variant requires Thumb2");
8657 case Match_ImmRange0_15: {
8658 SMLoc ErrorLoc = ((ARMOperand &)*Operands[ErrorInfo]).getStartLoc();
8659 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
8660 return Error(ErrorLoc, "immediate operand must be in the range [0,15]");
8662 case Match_ImmRange0_239: {
8663 SMLoc ErrorLoc = ((ARMOperand &)*Operands[ErrorInfo]).getStartLoc();
8664 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
8665 return Error(ErrorLoc, "immediate operand must be in the range [0,239]");
8667 case Match_AlignedMemoryRequiresNone:
8668 case Match_DupAlignedMemoryRequiresNone:
8669 case Match_AlignedMemoryRequires16:
8670 case Match_DupAlignedMemoryRequires16:
8671 case Match_AlignedMemoryRequires32:
8672 case Match_DupAlignedMemoryRequires32:
8673 case Match_AlignedMemoryRequires64:
8674 case Match_DupAlignedMemoryRequires64:
8675 case Match_AlignedMemoryRequires64or128:
8676 case Match_DupAlignedMemoryRequires64or128:
8677 case Match_AlignedMemoryRequires64or128or256:
8679 SMLoc ErrorLoc = ((ARMOperand &)*Operands[ErrorInfo]).getAlignmentLoc();
8680 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
8681 switch (MatchResult) {
8683 llvm_unreachable("Missing Match_Aligned type");
8684 case Match_AlignedMemoryRequiresNone:
8685 case Match_DupAlignedMemoryRequiresNone:
8686 return Error(ErrorLoc, "alignment must be omitted");
8687 case Match_AlignedMemoryRequires16:
8688 case Match_DupAlignedMemoryRequires16:
8689 return Error(ErrorLoc, "alignment must be 16 or omitted");
8690 case Match_AlignedMemoryRequires32:
8691 case Match_DupAlignedMemoryRequires32:
8692 return Error(ErrorLoc, "alignment must be 32 or omitted");
8693 case Match_AlignedMemoryRequires64:
8694 case Match_DupAlignedMemoryRequires64:
8695 return Error(ErrorLoc, "alignment must be 64 or omitted");
8696 case Match_AlignedMemoryRequires64or128:
8697 case Match_DupAlignedMemoryRequires64or128:
8698 return Error(ErrorLoc, "alignment must be 64, 128 or omitted");
8699 case Match_AlignedMemoryRequires64or128or256:
8700 return Error(ErrorLoc, "alignment must be 64, 128, 256 or omitted");
8705 llvm_unreachable("Implement any new match types added!");
8708 /// parseDirective parses the arm specific directives
8709 bool ARMAsmParser::ParseDirective(AsmToken DirectiveID) {
8710 const MCObjectFileInfo::Environment Format =
8711 getContext().getObjectFileInfo()->getObjectFileType();
8712 bool IsMachO = Format == MCObjectFileInfo::IsMachO;
8713 bool IsCOFF = Format == MCObjectFileInfo::IsCOFF;
8715 StringRef IDVal = DirectiveID.getIdentifier();
8716 if (IDVal == ".word")
8717 return parseLiteralValues(4, DirectiveID.getLoc());
8718 else if (IDVal == ".short" || IDVal == ".hword")
8719 return parseLiteralValues(2, DirectiveID.getLoc());
8720 else if (IDVal == ".thumb")
8721 return parseDirectiveThumb(DirectiveID.getLoc());
8722 else if (IDVal == ".arm")
8723 return parseDirectiveARM(DirectiveID.getLoc());
8724 else if (IDVal == ".thumb_func")
8725 return parseDirectiveThumbFunc(DirectiveID.getLoc());
8726 else if (IDVal == ".code")
8727 return parseDirectiveCode(DirectiveID.getLoc());
8728 else if (IDVal == ".syntax")
8729 return parseDirectiveSyntax(DirectiveID.getLoc());
8730 else if (IDVal == ".unreq")
8731 return parseDirectiveUnreq(DirectiveID.getLoc());
8732 else if (IDVal == ".fnend")
8733 return parseDirectiveFnEnd(DirectiveID.getLoc());
8734 else if (IDVal == ".cantunwind")
8735 return parseDirectiveCantUnwind(DirectiveID.getLoc());
8736 else if (IDVal == ".personality")
8737 return parseDirectivePersonality(DirectiveID.getLoc());
8738 else if (IDVal == ".handlerdata")
8739 return parseDirectiveHandlerData(DirectiveID.getLoc());
8740 else if (IDVal == ".setfp")
8741 return parseDirectiveSetFP(DirectiveID.getLoc());
8742 else if (IDVal == ".pad")
8743 return parseDirectivePad(DirectiveID.getLoc());
8744 else if (IDVal == ".save")
8745 return parseDirectiveRegSave(DirectiveID.getLoc(), false);
8746 else if (IDVal == ".vsave")
8747 return parseDirectiveRegSave(DirectiveID.getLoc(), true);
8748 else if (IDVal == ".ltorg" || IDVal == ".pool")
8749 return parseDirectiveLtorg(DirectiveID.getLoc());
8750 else if (IDVal == ".even")
8751 return parseDirectiveEven(DirectiveID.getLoc());
8752 else if (IDVal == ".personalityindex")
8753 return parseDirectivePersonalityIndex(DirectiveID.getLoc());
8754 else if (IDVal == ".unwind_raw")
8755 return parseDirectiveUnwindRaw(DirectiveID.getLoc());
8756 else if (IDVal == ".movsp")
8757 return parseDirectiveMovSP(DirectiveID.getLoc());
8758 else if (IDVal == ".arch_extension")
8759 return parseDirectiveArchExtension(DirectiveID.getLoc());
8760 else if (IDVal == ".align")
8761 return parseDirectiveAlign(DirectiveID.getLoc());
8762 else if (IDVal == ".thumb_set")
8763 return parseDirectiveThumbSet(DirectiveID.getLoc());
8765 if (!IsMachO && !IsCOFF) {
8766 if (IDVal == ".arch")
8767 return parseDirectiveArch(DirectiveID.getLoc());
8768 else if (IDVal == ".cpu")
8769 return parseDirectiveCPU(DirectiveID.getLoc());
8770 else if (IDVal == ".eabi_attribute")
8771 return parseDirectiveEabiAttr(DirectiveID.getLoc());
8772 else if (IDVal == ".fpu")
8773 return parseDirectiveFPU(DirectiveID.getLoc());
8774 else if (IDVal == ".fnstart")
8775 return parseDirectiveFnStart(DirectiveID.getLoc());
8776 else if (IDVal == ".inst")
8777 return parseDirectiveInst(DirectiveID.getLoc());
8778 else if (IDVal == ".inst.n")
8779 return parseDirectiveInst(DirectiveID.getLoc(), 'n');
8780 else if (IDVal == ".inst.w")
8781 return parseDirectiveInst(DirectiveID.getLoc(), 'w');
8782 else if (IDVal == ".object_arch")
8783 return parseDirectiveObjectArch(DirectiveID.getLoc());
8784 else if (IDVal == ".tlsdescseq")
8785 return parseDirectiveTLSDescSeq(DirectiveID.getLoc());
8791 /// parseLiteralValues
8792 /// ::= .hword expression [, expression]*
8793 /// ::= .short expression [, expression]*
8794 /// ::= .word expression [, expression]*
8795 bool ARMAsmParser::parseLiteralValues(unsigned Size, SMLoc L) {
8796 MCAsmParser &Parser = getParser();
8797 if (getLexer().isNot(AsmToken::EndOfStatement)) {
8799 const MCExpr *Value;
8800 if (getParser().parseExpression(Value)) {
8801 Parser.eatToEndOfStatement();
8805 getParser().getStreamer().EmitValue(Value, Size);
8807 if (getLexer().is(AsmToken::EndOfStatement))
8810 // FIXME: Improve diagnostic.
8811 if (getLexer().isNot(AsmToken::Comma)) {
8812 Error(L, "unexpected token in directive");
8823 /// parseDirectiveThumb
8825 bool ARMAsmParser::parseDirectiveThumb(SMLoc L) {
8826 MCAsmParser &Parser = getParser();
8827 if (getLexer().isNot(AsmToken::EndOfStatement)) {
8828 Error(L, "unexpected token in directive");
8834 Error(L, "target does not support Thumb mode");
8841 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
8845 /// parseDirectiveARM
8847 bool ARMAsmParser::parseDirectiveARM(SMLoc L) {
8848 MCAsmParser &Parser = getParser();
8849 if (getLexer().isNot(AsmToken::EndOfStatement)) {
8850 Error(L, "unexpected token in directive");
8856 Error(L, "target does not support ARM mode");
8863 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
8867 void ARMAsmParser::onLabelParsed(MCSymbol *Symbol) {
8868 if (NextSymbolIsThumb) {
8869 getParser().getStreamer().EmitThumbFunc(Symbol);
8870 NextSymbolIsThumb = false;
8874 /// parseDirectiveThumbFunc
8875 /// ::= .thumbfunc symbol_name
8876 bool ARMAsmParser::parseDirectiveThumbFunc(SMLoc L) {
8877 MCAsmParser &Parser = getParser();
8878 const auto Format = getContext().getObjectFileInfo()->getObjectFileType();
8879 bool IsMachO = Format == MCObjectFileInfo::IsMachO;
8881 // Darwin asm has (optionally) function name after .thumb_func direction
8884 const AsmToken &Tok = Parser.getTok();
8885 if (Tok.isNot(AsmToken::EndOfStatement)) {
8886 if (Tok.isNot(AsmToken::Identifier) && Tok.isNot(AsmToken::String)) {
8887 Error(L, "unexpected token in .thumb_func directive");
8892 getParser().getContext().GetOrCreateSymbol(Tok.getIdentifier());
8893 getParser().getStreamer().EmitThumbFunc(Func);
8894 Parser.Lex(); // Consume the identifier token.
8899 if (getLexer().isNot(AsmToken::EndOfStatement)) {
8900 Error(Parser.getTok().getLoc(), "unexpected token in directive");
8901 Parser.eatToEndOfStatement();
8905 NextSymbolIsThumb = true;
8909 /// parseDirectiveSyntax
8910 /// ::= .syntax unified | divided
8911 bool ARMAsmParser::parseDirectiveSyntax(SMLoc L) {
8912 MCAsmParser &Parser = getParser();
8913 const AsmToken &Tok = Parser.getTok();
8914 if (Tok.isNot(AsmToken::Identifier)) {
8915 Error(L, "unexpected token in .syntax directive");
8919 StringRef Mode = Tok.getString();
8920 if (Mode == "unified" || Mode == "UNIFIED") {
8922 } else if (Mode == "divided" || Mode == "DIVIDED") {
8923 Error(L, "'.syntax divided' arm asssembly not supported");
8926 Error(L, "unrecognized syntax mode in .syntax directive");
8930 if (getLexer().isNot(AsmToken::EndOfStatement)) {
8931 Error(Parser.getTok().getLoc(), "unexpected token in directive");
8936 // TODO tell the MC streamer the mode
8937 // getParser().getStreamer().Emit???();
8941 /// parseDirectiveCode
8942 /// ::= .code 16 | 32
8943 bool ARMAsmParser::parseDirectiveCode(SMLoc L) {
8944 MCAsmParser &Parser = getParser();
8945 const AsmToken &Tok = Parser.getTok();
8946 if (Tok.isNot(AsmToken::Integer)) {
8947 Error(L, "unexpected token in .code directive");
8950 int64_t Val = Parser.getTok().getIntVal();
8951 if (Val != 16 && Val != 32) {
8952 Error(L, "invalid operand to .code directive");
8957 if (getLexer().isNot(AsmToken::EndOfStatement)) {
8958 Error(Parser.getTok().getLoc(), "unexpected token in directive");
8965 Error(L, "target does not support Thumb mode");
8971 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
8974 Error(L, "target does not support ARM mode");
8980 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
8986 /// parseDirectiveReq
8987 /// ::= name .req registername
8988 bool ARMAsmParser::parseDirectiveReq(StringRef Name, SMLoc L) {
8989 MCAsmParser &Parser = getParser();
8990 Parser.Lex(); // Eat the '.req' token.
8992 SMLoc SRegLoc, ERegLoc;
8993 if (ParseRegister(Reg, SRegLoc, ERegLoc)) {
8994 Parser.eatToEndOfStatement();
8995 Error(SRegLoc, "register name expected");
8999 // Shouldn't be anything else.
9000 if (Parser.getTok().isNot(AsmToken::EndOfStatement)) {
9001 Parser.eatToEndOfStatement();
9002 Error(Parser.getTok().getLoc(), "unexpected input in .req directive.");
9006 Parser.Lex(); // Consume the EndOfStatement
9008 if (RegisterReqs.insert(std::make_pair(Name, Reg)).first->second != Reg) {
9009 Error(SRegLoc, "redefinition of '" + Name + "' does not match original.");
9016 /// parseDirectiveUneq
9017 /// ::= .unreq registername
9018 bool ARMAsmParser::parseDirectiveUnreq(SMLoc L) {
9019 MCAsmParser &Parser = getParser();
9020 if (Parser.getTok().isNot(AsmToken::Identifier)) {
9021 Parser.eatToEndOfStatement();
9022 Error(L, "unexpected input in .unreq directive.");
9025 RegisterReqs.erase(Parser.getTok().getIdentifier().lower());
9026 Parser.Lex(); // Eat the identifier.
9030 /// parseDirectiveArch
9032 bool ARMAsmParser::parseDirectiveArch(SMLoc L) {
9033 StringRef Arch = getParser().parseStringToEndOfStatement().trim();
9035 unsigned ID = StringSwitch<unsigned>(Arch)
9036 #define ARM_ARCH_NAME(NAME, ID, DEFAULT_CPU_NAME, DEFAULT_CPU_ARCH) \
9037 .Case(NAME, ARM::ID)
9038 #define ARM_ARCH_ALIAS(NAME, ID) \
9039 .Case(NAME, ARM::ID)
9040 #include "MCTargetDesc/ARMArchName.def"
9041 .Default(ARM::INVALID_ARCH);
9043 if (ID == ARM::INVALID_ARCH) {
9044 Error(L, "Unknown arch name");
9048 getTargetStreamer().emitArch(ID);
9052 /// parseDirectiveEabiAttr
9053 /// ::= .eabi_attribute int, int [, "str"]
9054 /// ::= .eabi_attribute Tag_name, int [, "str"]
9055 bool ARMAsmParser::parseDirectiveEabiAttr(SMLoc L) {
9056 MCAsmParser &Parser = getParser();
9059 TagLoc = Parser.getTok().getLoc();
9060 if (Parser.getTok().is(AsmToken::Identifier)) {
9061 StringRef Name = Parser.getTok().getIdentifier();
9062 Tag = ARMBuildAttrs::AttrTypeFromString(Name);
9064 Error(TagLoc, "attribute name not recognised: " + Name);
9065 Parser.eatToEndOfStatement();
9070 const MCExpr *AttrExpr;
9072 TagLoc = Parser.getTok().getLoc();
9073 if (Parser.parseExpression(AttrExpr)) {
9074 Parser.eatToEndOfStatement();
9078 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(AttrExpr);
9080 Error(TagLoc, "expected numeric constant");
9081 Parser.eatToEndOfStatement();
9085 Tag = CE->getValue();
9088 if (Parser.getTok().isNot(AsmToken::Comma)) {
9089 Error(Parser.getTok().getLoc(), "comma expected");
9090 Parser.eatToEndOfStatement();
9093 Parser.Lex(); // skip comma
9095 StringRef StringValue = "";
9096 bool IsStringValue = false;
9098 int64_t IntegerValue = 0;
9099 bool IsIntegerValue = false;
9101 if (Tag == ARMBuildAttrs::CPU_raw_name || Tag == ARMBuildAttrs::CPU_name)
9102 IsStringValue = true;
9103 else if (Tag == ARMBuildAttrs::compatibility) {
9104 IsStringValue = true;
9105 IsIntegerValue = true;
9106 } else if (Tag < 32 || Tag % 2 == 0)
9107 IsIntegerValue = true;
9108 else if (Tag % 2 == 1)
9109 IsStringValue = true;
9111 llvm_unreachable("invalid tag type");
9113 if (IsIntegerValue) {
9114 const MCExpr *ValueExpr;
9115 SMLoc ValueExprLoc = Parser.getTok().getLoc();
9116 if (Parser.parseExpression(ValueExpr)) {
9117 Parser.eatToEndOfStatement();
9121 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ValueExpr);
9123 Error(ValueExprLoc, "expected numeric constant");
9124 Parser.eatToEndOfStatement();
9128 IntegerValue = CE->getValue();
9131 if (Tag == ARMBuildAttrs::compatibility) {
9132 if (Parser.getTok().isNot(AsmToken::Comma))
9133 IsStringValue = false;
9134 if (Parser.getTok().isNot(AsmToken::Comma)) {
9135 Error(Parser.getTok().getLoc(), "comma expected");
9136 Parser.eatToEndOfStatement();
9143 if (IsStringValue) {
9144 if (Parser.getTok().isNot(AsmToken::String)) {
9145 Error(Parser.getTok().getLoc(), "bad string constant");
9146 Parser.eatToEndOfStatement();
9150 StringValue = Parser.getTok().getStringContents();
9154 if (IsIntegerValue && IsStringValue) {
9155 assert(Tag == ARMBuildAttrs::compatibility);
9156 getTargetStreamer().emitIntTextAttribute(Tag, IntegerValue, StringValue);
9157 } else if (IsIntegerValue)
9158 getTargetStreamer().emitAttribute(Tag, IntegerValue);
9159 else if (IsStringValue)
9160 getTargetStreamer().emitTextAttribute(Tag, StringValue);
9164 /// parseDirectiveCPU
9166 bool ARMAsmParser::parseDirectiveCPU(SMLoc L) {
9167 StringRef CPU = getParser().parseStringToEndOfStatement().trim();
9168 getTargetStreamer().emitTextAttribute(ARMBuildAttrs::CPU_name, CPU);
9170 if (!STI.isCPUStringValid(CPU)) {
9171 Error(L, "Unknown CPU name");
9175 // FIXME: This switches the CPU features globally, therefore it might
9176 // happen that code you would not expect to assemble will. For details
9177 // see: http://llvm.org/bugs/show_bug.cgi?id=20757
9178 STI.InitMCProcessorInfo(CPU, "");
9179 STI.InitCPUSchedModel(CPU);
9180 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
9185 // FIXME: This is duplicated in getARMFPUFeatures() in
9186 // tools/clang/lib/Driver/Tools.cpp
9187 static const struct {
9189 const uint64_t Enabled;
9190 const uint64_t Disabled;
9193 /* Enabled */ ARM::FeatureVFP2,
9194 /* Disabled */ ARM::FeatureNEON},
9195 {/* ID */ ARM::VFPV2,
9196 /* Enabled */ ARM::FeatureVFP2,
9197 /* Disabled */ ARM::FeatureNEON},
9198 {/* ID */ ARM::VFPV3,
9199 /* Enabled */ ARM::FeatureVFP2 | ARM::FeatureVFP3,
9200 /* Disabled */ ARM::FeatureNEON | ARM::FeatureD16},
9201 {/* ID */ ARM::VFPV3_D16,
9202 /* Enable */ ARM::FeatureVFP2 | ARM::FeatureVFP3 | ARM::FeatureD16,
9203 /* Disabled */ ARM::FeatureNEON},
9204 {/* ID */ ARM::VFPV4,
9205 /* Enabled */ ARM::FeatureVFP2 | ARM::FeatureVFP3 | ARM::FeatureVFP4,
9206 /* Disabled */ ARM::FeatureNEON | ARM::FeatureD16},
9207 {/* ID */ ARM::VFPV4_D16,
9208 /* Enabled */ ARM::FeatureVFP2 | ARM::FeatureVFP3 | ARM::FeatureVFP4 |
9210 /* Disabled */ ARM::FeatureNEON},
9211 {/* ID */ ARM::FPV5_D16,
9212 /* Enabled */ ARM::FeatureVFP2 | ARM::FeatureVFP3 | ARM::FeatureVFP4 |
9213 ARM::FeatureFPARMv8 | ARM::FeatureD16,
9214 /* Disabled */ ARM::FeatureNEON | ARM::FeatureCrypto},
9215 {/* ID */ ARM::FP_ARMV8,
9216 /* Enabled */ ARM::FeatureVFP2 | ARM::FeatureVFP3 | ARM::FeatureVFP4 |
9217 ARM::FeatureFPARMv8,
9218 /* Disabled */ ARM::FeatureNEON | ARM::FeatureCrypto | ARM::FeatureD16},
9219 {/* ID */ ARM::NEON,
9220 /* Enabled */ ARM::FeatureVFP2 | ARM::FeatureVFP3 | ARM::FeatureNEON,
9221 /* Disabled */ ARM::FeatureD16},
9222 {/* ID */ ARM::NEON_VFPV4,
9223 /* Enabled */ ARM::FeatureVFP2 | ARM::FeatureVFP3 | ARM::FeatureVFP4 |
9225 /* Disabled */ ARM::FeatureD16},
9226 {/* ID */ ARM::NEON_FP_ARMV8,
9227 /* Enabled */ ARM::FeatureVFP2 | ARM::FeatureVFP3 | ARM::FeatureVFP4 |
9228 ARM::FeatureFPARMv8 | ARM::FeatureNEON,
9229 /* Disabled */ ARM::FeatureCrypto | ARM::FeatureD16},
9230 {/* ID */ ARM::CRYPTO_NEON_FP_ARMV8,
9231 /* Enabled */ ARM::FeatureVFP2 | ARM::FeatureVFP3 | ARM::FeatureVFP4 |
9232 ARM::FeatureFPARMv8 | ARM::FeatureNEON | ARM::FeatureCrypto,
9233 /* Disabled */ ARM::FeatureD16},
9234 {ARM::SOFTVFP, 0, 0},
9237 /// parseDirectiveFPU
9239 bool ARMAsmParser::parseDirectiveFPU(SMLoc L) {
9240 SMLoc FPUNameLoc = getTok().getLoc();
9241 StringRef FPU = getParser().parseStringToEndOfStatement().trim();
9243 unsigned ID = StringSwitch<unsigned>(FPU)
9244 #define ARM_FPU_NAME(NAME, ID) .Case(NAME, ARM::ID)
9245 #include "ARMFPUName.def"
9246 .Default(ARM::INVALID_FPU);
9248 if (ID == ARM::INVALID_FPU) {
9249 Error(FPUNameLoc, "Unknown FPU name");
9253 for (const auto &Entry : FPUs) {
9257 // Need to toggle features that should be on but are off and that
9258 // should off but are on.
9259 uint64_t Toggle = (Entry.Enabled & ~STI.getFeatureBits()) |
9260 (Entry.Disabled & STI.getFeatureBits());
9261 setAvailableFeatures(ComputeAvailableFeatures(STI.ToggleFeature(Toggle)));
9265 getTargetStreamer().emitFPU(ID);
9269 /// parseDirectiveFnStart
9271 bool ARMAsmParser::parseDirectiveFnStart(SMLoc L) {
9272 if (UC.hasFnStart()) {
9273 Error(L, ".fnstart starts before the end of previous one");
9274 UC.emitFnStartLocNotes();
9278 // Reset the unwind directives parser state
9281 getTargetStreamer().emitFnStart();
9283 UC.recordFnStart(L);
9287 /// parseDirectiveFnEnd
9289 bool ARMAsmParser::parseDirectiveFnEnd(SMLoc L) {
9290 // Check the ordering of unwind directives
9291 if (!UC.hasFnStart()) {
9292 Error(L, ".fnstart must precede .fnend directive");
9296 // Reset the unwind directives parser state
9297 getTargetStreamer().emitFnEnd();
9303 /// parseDirectiveCantUnwind
9305 bool ARMAsmParser::parseDirectiveCantUnwind(SMLoc L) {
9306 UC.recordCantUnwind(L);
9308 // Check the ordering of unwind directives
9309 if (!UC.hasFnStart()) {
9310 Error(L, ".fnstart must precede .cantunwind directive");
9313 if (UC.hasHandlerData()) {
9314 Error(L, ".cantunwind can't be used with .handlerdata directive");
9315 UC.emitHandlerDataLocNotes();
9318 if (UC.hasPersonality()) {
9319 Error(L, ".cantunwind can't be used with .personality directive");
9320 UC.emitPersonalityLocNotes();
9324 getTargetStreamer().emitCantUnwind();
9328 /// parseDirectivePersonality
9329 /// ::= .personality name
9330 bool ARMAsmParser::parseDirectivePersonality(SMLoc L) {
9331 MCAsmParser &Parser = getParser();
9332 bool HasExistingPersonality = UC.hasPersonality();
9334 UC.recordPersonality(L);
9336 // Check the ordering of unwind directives
9337 if (!UC.hasFnStart()) {
9338 Error(L, ".fnstart must precede .personality directive");
9341 if (UC.cantUnwind()) {
9342 Error(L, ".personality can't be used with .cantunwind directive");
9343 UC.emitCantUnwindLocNotes();
9346 if (UC.hasHandlerData()) {
9347 Error(L, ".personality must precede .handlerdata directive");
9348 UC.emitHandlerDataLocNotes();
9351 if (HasExistingPersonality) {
9352 Parser.eatToEndOfStatement();
9353 Error(L, "multiple personality directives");
9354 UC.emitPersonalityLocNotes();
9358 // Parse the name of the personality routine
9359 if (Parser.getTok().isNot(AsmToken::Identifier)) {
9360 Parser.eatToEndOfStatement();
9361 Error(L, "unexpected input in .personality directive.");
9364 StringRef Name(Parser.getTok().getIdentifier());
9367 MCSymbol *PR = getParser().getContext().GetOrCreateSymbol(Name);
9368 getTargetStreamer().emitPersonality(PR);
9372 /// parseDirectiveHandlerData
9373 /// ::= .handlerdata
9374 bool ARMAsmParser::parseDirectiveHandlerData(SMLoc L) {
9375 UC.recordHandlerData(L);
9377 // Check the ordering of unwind directives
9378 if (!UC.hasFnStart()) {
9379 Error(L, ".fnstart must precede .personality directive");
9382 if (UC.cantUnwind()) {
9383 Error(L, ".handlerdata can't be used with .cantunwind directive");
9384 UC.emitCantUnwindLocNotes();
9388 getTargetStreamer().emitHandlerData();
9392 /// parseDirectiveSetFP
9393 /// ::= .setfp fpreg, spreg [, offset]
9394 bool ARMAsmParser::parseDirectiveSetFP(SMLoc L) {
9395 MCAsmParser &Parser = getParser();
9396 // Check the ordering of unwind directives
9397 if (!UC.hasFnStart()) {
9398 Error(L, ".fnstart must precede .setfp directive");
9401 if (UC.hasHandlerData()) {
9402 Error(L, ".setfp must precede .handlerdata directive");
9407 SMLoc FPRegLoc = Parser.getTok().getLoc();
9408 int FPReg = tryParseRegister();
9410 Error(FPRegLoc, "frame pointer register expected");
9415 if (Parser.getTok().isNot(AsmToken::Comma)) {
9416 Error(Parser.getTok().getLoc(), "comma expected");
9419 Parser.Lex(); // skip comma
9422 SMLoc SPRegLoc = Parser.getTok().getLoc();
9423 int SPReg = tryParseRegister();
9425 Error(SPRegLoc, "stack pointer register expected");
9429 if (SPReg != ARM::SP && SPReg != UC.getFPReg()) {
9430 Error(SPRegLoc, "register should be either $sp or the latest fp register");
9434 // Update the frame pointer register
9435 UC.saveFPReg(FPReg);
9439 if (Parser.getTok().is(AsmToken::Comma)) {
9440 Parser.Lex(); // skip comma
9442 if (Parser.getTok().isNot(AsmToken::Hash) &&
9443 Parser.getTok().isNot(AsmToken::Dollar)) {
9444 Error(Parser.getTok().getLoc(), "'#' expected");
9447 Parser.Lex(); // skip hash token.
9449 const MCExpr *OffsetExpr;
9450 SMLoc ExLoc = Parser.getTok().getLoc();
9452 if (getParser().parseExpression(OffsetExpr, EndLoc)) {
9453 Error(ExLoc, "malformed setfp offset");
9456 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr);
9458 Error(ExLoc, "setfp offset must be an immediate");
9462 Offset = CE->getValue();
9465 getTargetStreamer().emitSetFP(static_cast<unsigned>(FPReg),
9466 static_cast<unsigned>(SPReg), Offset);
9472 bool ARMAsmParser::parseDirectivePad(SMLoc L) {
9473 MCAsmParser &Parser = getParser();
9474 // Check the ordering of unwind directives
9475 if (!UC.hasFnStart()) {
9476 Error(L, ".fnstart must precede .pad directive");
9479 if (UC.hasHandlerData()) {
9480 Error(L, ".pad must precede .handlerdata directive");
9485 if (Parser.getTok().isNot(AsmToken::Hash) &&
9486 Parser.getTok().isNot(AsmToken::Dollar)) {
9487 Error(Parser.getTok().getLoc(), "'#' expected");
9490 Parser.Lex(); // skip hash token.
9492 const MCExpr *OffsetExpr;
9493 SMLoc ExLoc = Parser.getTok().getLoc();
9495 if (getParser().parseExpression(OffsetExpr, EndLoc)) {
9496 Error(ExLoc, "malformed pad offset");
9499 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr);
9501 Error(ExLoc, "pad offset must be an immediate");
9505 getTargetStreamer().emitPad(CE->getValue());
9509 /// parseDirectiveRegSave
9510 /// ::= .save { registers }
9511 /// ::= .vsave { registers }
9512 bool ARMAsmParser::parseDirectiveRegSave(SMLoc L, bool IsVector) {
9513 // Check the ordering of unwind directives
9514 if (!UC.hasFnStart()) {
9515 Error(L, ".fnstart must precede .save or .vsave directives");
9518 if (UC.hasHandlerData()) {
9519 Error(L, ".save or .vsave must precede .handlerdata directive");
9523 // RAII object to make sure parsed operands are deleted.
9524 SmallVector<std::unique_ptr<MCParsedAsmOperand>, 1> Operands;
9526 // Parse the register list
9527 if (parseRegisterList(Operands))
9529 ARMOperand &Op = (ARMOperand &)*Operands[0];
9530 if (!IsVector && !Op.isRegList()) {
9531 Error(L, ".save expects GPR registers");
9534 if (IsVector && !Op.isDPRRegList()) {
9535 Error(L, ".vsave expects DPR registers");
9539 getTargetStreamer().emitRegSave(Op.getRegList(), IsVector);
9543 /// parseDirectiveInst
9544 /// ::= .inst opcode [, ...]
9545 /// ::= .inst.n opcode [, ...]
9546 /// ::= .inst.w opcode [, ...]
9547 bool ARMAsmParser::parseDirectiveInst(SMLoc Loc, char Suffix) {
9548 MCAsmParser &Parser = getParser();
9560 Parser.eatToEndOfStatement();
9561 Error(Loc, "cannot determine Thumb instruction size, "
9562 "use inst.n/inst.w instead");
9567 Parser.eatToEndOfStatement();
9568 Error(Loc, "width suffixes are invalid in ARM mode");
9574 if (getLexer().is(AsmToken::EndOfStatement)) {
9575 Parser.eatToEndOfStatement();
9576 Error(Loc, "expected expression following directive");
9583 if (getParser().parseExpression(Expr)) {
9584 Error(Loc, "expected expression");
9588 const MCConstantExpr *Value = dyn_cast_or_null<MCConstantExpr>(Expr);
9590 Error(Loc, "expected constant expression");
9596 if (Value->getValue() > 0xffff) {
9597 Error(Loc, "inst.n operand is too big, use inst.w instead");
9602 if (Value->getValue() > 0xffffffff) {
9604 StringRef(Suffix ? "inst.w" : "inst") + " operand is too big");
9609 llvm_unreachable("only supported widths are 2 and 4");
9612 getTargetStreamer().emitInst(Value->getValue(), Suffix);
9614 if (getLexer().is(AsmToken::EndOfStatement))
9617 if (getLexer().isNot(AsmToken::Comma)) {
9618 Error(Loc, "unexpected token in directive");
9629 /// parseDirectiveLtorg
9630 /// ::= .ltorg | .pool
9631 bool ARMAsmParser::parseDirectiveLtorg(SMLoc L) {
9632 getTargetStreamer().emitCurrentConstantPool();
9636 bool ARMAsmParser::parseDirectiveEven(SMLoc L) {
9637 const MCSection *Section = getStreamer().getCurrentSection().first;
9639 if (getLexer().isNot(AsmToken::EndOfStatement)) {
9640 TokError("unexpected token in directive");
9645 getStreamer().InitSections(false);
9646 Section = getStreamer().getCurrentSection().first;
9649 assert(Section && "must have section to emit alignment");
9650 if (Section->UseCodeAlign())
9651 getStreamer().EmitCodeAlignment(2);
9653 getStreamer().EmitValueToAlignment(2);
9658 /// parseDirectivePersonalityIndex
9659 /// ::= .personalityindex index
9660 bool ARMAsmParser::parseDirectivePersonalityIndex(SMLoc L) {
9661 MCAsmParser &Parser = getParser();
9662 bool HasExistingPersonality = UC.hasPersonality();
9664 UC.recordPersonalityIndex(L);
9666 if (!UC.hasFnStart()) {
9667 Parser.eatToEndOfStatement();
9668 Error(L, ".fnstart must precede .personalityindex directive");
9671 if (UC.cantUnwind()) {
9672 Parser.eatToEndOfStatement();
9673 Error(L, ".personalityindex cannot be used with .cantunwind");
9674 UC.emitCantUnwindLocNotes();
9677 if (UC.hasHandlerData()) {
9678 Parser.eatToEndOfStatement();
9679 Error(L, ".personalityindex must precede .handlerdata directive");
9680 UC.emitHandlerDataLocNotes();
9683 if (HasExistingPersonality) {
9684 Parser.eatToEndOfStatement();
9685 Error(L, "multiple personality directives");
9686 UC.emitPersonalityLocNotes();
9690 const MCExpr *IndexExpression;
9691 SMLoc IndexLoc = Parser.getTok().getLoc();
9692 if (Parser.parseExpression(IndexExpression)) {
9693 Parser.eatToEndOfStatement();
9697 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(IndexExpression);
9699 Parser.eatToEndOfStatement();
9700 Error(IndexLoc, "index must be a constant number");
9703 if (CE->getValue() < 0 ||
9704 CE->getValue() >= ARM::EHABI::NUM_PERSONALITY_INDEX) {
9705 Parser.eatToEndOfStatement();
9706 Error(IndexLoc, "personality routine index should be in range [0-3]");
9710 getTargetStreamer().emitPersonalityIndex(CE->getValue());
9714 /// parseDirectiveUnwindRaw
9715 /// ::= .unwind_raw offset, opcode [, opcode...]
9716 bool ARMAsmParser::parseDirectiveUnwindRaw(SMLoc L) {
9717 MCAsmParser &Parser = getParser();
9718 if (!UC.hasFnStart()) {
9719 Parser.eatToEndOfStatement();
9720 Error(L, ".fnstart must precede .unwind_raw directives");
9724 int64_t StackOffset;
9726 const MCExpr *OffsetExpr;
9727 SMLoc OffsetLoc = getLexer().getLoc();
9728 if (getLexer().is(AsmToken::EndOfStatement) ||
9729 getParser().parseExpression(OffsetExpr)) {
9730 Error(OffsetLoc, "expected expression");
9731 Parser.eatToEndOfStatement();
9735 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr);
9737 Error(OffsetLoc, "offset must be a constant");
9738 Parser.eatToEndOfStatement();
9742 StackOffset = CE->getValue();
9744 if (getLexer().isNot(AsmToken::Comma)) {
9745 Error(getLexer().getLoc(), "expected comma");
9746 Parser.eatToEndOfStatement();
9751 SmallVector<uint8_t, 16> Opcodes;
9755 SMLoc OpcodeLoc = getLexer().getLoc();
9756 if (getLexer().is(AsmToken::EndOfStatement) || Parser.parseExpression(OE)) {
9757 Error(OpcodeLoc, "expected opcode expression");
9758 Parser.eatToEndOfStatement();
9762 const MCConstantExpr *OC = dyn_cast<MCConstantExpr>(OE);
9764 Error(OpcodeLoc, "opcode value must be a constant");
9765 Parser.eatToEndOfStatement();
9769 const int64_t Opcode = OC->getValue();
9770 if (Opcode & ~0xff) {
9771 Error(OpcodeLoc, "invalid opcode");
9772 Parser.eatToEndOfStatement();
9776 Opcodes.push_back(uint8_t(Opcode));
9778 if (getLexer().is(AsmToken::EndOfStatement))
9781 if (getLexer().isNot(AsmToken::Comma)) {
9782 Error(getLexer().getLoc(), "unexpected token in directive");
9783 Parser.eatToEndOfStatement();
9790 getTargetStreamer().emitUnwindRaw(StackOffset, Opcodes);
9796 /// parseDirectiveTLSDescSeq
9797 /// ::= .tlsdescseq tls-variable
9798 bool ARMAsmParser::parseDirectiveTLSDescSeq(SMLoc L) {
9799 MCAsmParser &Parser = getParser();
9801 if (getLexer().isNot(AsmToken::Identifier)) {
9802 TokError("expected variable after '.tlsdescseq' directive");
9803 Parser.eatToEndOfStatement();
9807 const MCSymbolRefExpr *SRE =
9808 MCSymbolRefExpr::Create(Parser.getTok().getIdentifier(),
9809 MCSymbolRefExpr::VK_ARM_TLSDESCSEQ, getContext());
9812 if (getLexer().isNot(AsmToken::EndOfStatement)) {
9813 Error(Parser.getTok().getLoc(), "unexpected token");
9814 Parser.eatToEndOfStatement();
9818 getTargetStreamer().AnnotateTLSDescriptorSequence(SRE);
9822 /// parseDirectiveMovSP
9823 /// ::= .movsp reg [, #offset]
9824 bool ARMAsmParser::parseDirectiveMovSP(SMLoc L) {
9825 MCAsmParser &Parser = getParser();
9826 if (!UC.hasFnStart()) {
9827 Parser.eatToEndOfStatement();
9828 Error(L, ".fnstart must precede .movsp directives");
9831 if (UC.getFPReg() != ARM::SP) {
9832 Parser.eatToEndOfStatement();
9833 Error(L, "unexpected .movsp directive");
9837 SMLoc SPRegLoc = Parser.getTok().getLoc();
9838 int SPReg = tryParseRegister();
9840 Parser.eatToEndOfStatement();
9841 Error(SPRegLoc, "register expected");
9845 if (SPReg == ARM::SP || SPReg == ARM::PC) {
9846 Parser.eatToEndOfStatement();
9847 Error(SPRegLoc, "sp and pc are not permitted in .movsp directive");
9852 if (Parser.getTok().is(AsmToken::Comma)) {
9855 if (Parser.getTok().isNot(AsmToken::Hash)) {
9856 Error(Parser.getTok().getLoc(), "expected #constant");
9857 Parser.eatToEndOfStatement();
9862 const MCExpr *OffsetExpr;
9863 SMLoc OffsetLoc = Parser.getTok().getLoc();
9864 if (Parser.parseExpression(OffsetExpr)) {
9865 Parser.eatToEndOfStatement();
9866 Error(OffsetLoc, "malformed offset expression");
9870 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr);
9872 Parser.eatToEndOfStatement();
9873 Error(OffsetLoc, "offset must be an immediate constant");
9877 Offset = CE->getValue();
9880 getTargetStreamer().emitMovSP(SPReg, Offset);
9881 UC.saveFPReg(SPReg);
9886 /// parseDirectiveObjectArch
9887 /// ::= .object_arch name
9888 bool ARMAsmParser::parseDirectiveObjectArch(SMLoc L) {
9889 MCAsmParser &Parser = getParser();
9890 if (getLexer().isNot(AsmToken::Identifier)) {
9891 Error(getLexer().getLoc(), "unexpected token");
9892 Parser.eatToEndOfStatement();
9896 StringRef Arch = Parser.getTok().getString();
9897 SMLoc ArchLoc = Parser.getTok().getLoc();
9900 unsigned ID = StringSwitch<unsigned>(Arch)
9901 #define ARM_ARCH_NAME(NAME, ID, DEFAULT_CPU_NAME, DEFAULT_CPU_ARCH) \
9902 .Case(NAME, ARM::ID)
9903 #define ARM_ARCH_ALIAS(NAME, ID) \
9904 .Case(NAME, ARM::ID)
9905 #include "MCTargetDesc/ARMArchName.def"
9906 #undef ARM_ARCH_NAME
9907 #undef ARM_ARCH_ALIAS
9908 .Default(ARM::INVALID_ARCH);
9910 if (ID == ARM::INVALID_ARCH) {
9911 Error(ArchLoc, "unknown architecture '" + Arch + "'");
9912 Parser.eatToEndOfStatement();
9916 getTargetStreamer().emitObjectArch(ID);
9918 if (getLexer().isNot(AsmToken::EndOfStatement)) {
9919 Error(getLexer().getLoc(), "unexpected token");
9920 Parser.eatToEndOfStatement();
9926 /// parseDirectiveAlign
9928 bool ARMAsmParser::parseDirectiveAlign(SMLoc L) {
9929 // NOTE: if this is not the end of the statement, fall back to the target
9930 // agnostic handling for this directive which will correctly handle this.
9931 if (getLexer().isNot(AsmToken::EndOfStatement))
9934 // '.align' is target specifically handled to mean 2**2 byte alignment.
9935 if (getStreamer().getCurrentSection().first->UseCodeAlign())
9936 getStreamer().EmitCodeAlignment(4, 0);
9938 getStreamer().EmitValueToAlignment(4, 0, 1, 0);
9943 /// parseDirectiveThumbSet
9944 /// ::= .thumb_set name, value
9945 bool ARMAsmParser::parseDirectiveThumbSet(SMLoc L) {
9946 MCAsmParser &Parser = getParser();
9949 if (Parser.parseIdentifier(Name)) {
9950 TokError("expected identifier after '.thumb_set'");
9951 Parser.eatToEndOfStatement();
9955 if (getLexer().isNot(AsmToken::Comma)) {
9956 TokError("expected comma after name '" + Name + "'");
9957 Parser.eatToEndOfStatement();
9962 const MCExpr *Value;
9963 if (Parser.parseExpression(Value)) {
9964 TokError("missing expression");
9965 Parser.eatToEndOfStatement();
9969 if (getLexer().isNot(AsmToken::EndOfStatement)) {
9970 TokError("unexpected token");
9971 Parser.eatToEndOfStatement();
9976 MCSymbol *Alias = getContext().GetOrCreateSymbol(Name);
9977 getTargetStreamer().emitThumbSet(Alias, Value);
9981 /// Force static initialization.
9982 extern "C" void LLVMInitializeARMAsmParser() {
9983 RegisterMCAsmParser<ARMAsmParser> X(TheARMLETarget);
9984 RegisterMCAsmParser<ARMAsmParser> Y(TheARMBETarget);
9985 RegisterMCAsmParser<ARMAsmParser> A(TheThumbLETarget);
9986 RegisterMCAsmParser<ARMAsmParser> B(TheThumbBETarget);
9989 #define GET_REGISTER_MATCHER
9990 #define GET_SUBTARGET_FEATURE_NAME
9991 #define GET_MATCHER_IMPLEMENTATION
9992 #include "ARMGenAsmMatcher.inc"
9994 static const struct {
9996 const unsigned ArchCheck;
9997 const uint64_t Features;
9999 { "crc", Feature_HasV8, ARM::FeatureCRC },
10000 { "crypto", Feature_HasV8,
10001 ARM::FeatureCrypto | ARM::FeatureNEON | ARM::FeatureFPARMv8 },
10002 { "fp", Feature_HasV8, ARM::FeatureFPARMv8 },
10003 { "idiv", Feature_HasV7 | Feature_IsNotMClass,
10004 ARM::FeatureHWDiv | ARM::FeatureHWDivARM },
10005 // FIXME: iWMMXT not supported
10006 { "iwmmxt", Feature_None, 0 },
10007 // FIXME: iWMMXT2 not supported
10008 { "iwmmxt2", Feature_None, 0 },
10009 // FIXME: Maverick not supported
10010 { "maverick", Feature_None, 0 },
10011 { "mp", Feature_HasV7 | Feature_IsNotMClass, ARM::FeatureMP },
10012 // FIXME: ARMv6-m OS Extensions feature not checked
10013 { "os", Feature_None, 0 },
10014 // FIXME: Also available in ARMv6-K
10015 { "sec", Feature_HasV7, ARM::FeatureTrustZone },
10016 { "simd", Feature_HasV8, ARM::FeatureNEON | ARM::FeatureFPARMv8 },
10017 // FIXME: Only available in A-class, isel not predicated
10018 { "virt", Feature_HasV7, ARM::FeatureVirtualization },
10019 // FIXME: xscale not supported
10020 { "xscale", Feature_None, 0 },
10023 /// parseDirectiveArchExtension
10024 /// ::= .arch_extension [no]feature
10025 bool ARMAsmParser::parseDirectiveArchExtension(SMLoc L) {
10026 MCAsmParser &Parser = getParser();
10028 if (getLexer().isNot(AsmToken::Identifier)) {
10029 Error(getLexer().getLoc(), "unexpected token");
10030 Parser.eatToEndOfStatement();
10034 StringRef Name = Parser.getTok().getString();
10035 SMLoc ExtLoc = Parser.getTok().getLoc();
10038 bool EnableFeature = true;
10039 if (Name.startswith_lower("no")) {
10040 EnableFeature = false;
10041 Name = Name.substr(2);
10044 for (const auto &Extension : Extensions) {
10045 if (Extension.Name != Name)
10048 if (!Extension.Features)
10049 report_fatal_error("unsupported architectural extension: " + Name);
10051 if ((getAvailableFeatures() & Extension.ArchCheck) != Extension.ArchCheck) {
10052 Error(ExtLoc, "architectural extension '" + Name + "' is not "
10053 "allowed for the current base architecture");
10057 uint64_t ToggleFeatures = EnableFeature
10058 ? (~STI.getFeatureBits() & Extension.Features)
10059 : ( STI.getFeatureBits() & Extension.Features);
10060 uint64_t Features =
10061 ComputeAvailableFeatures(STI.ToggleFeature(ToggleFeatures));
10062 setAvailableFeatures(Features);
10066 Error(ExtLoc, "unknown architectural extension: " + Name);
10067 Parser.eatToEndOfStatement();
10071 // Define this matcher function after the auto-generated include so we
10072 // have the match class enum definitions.
10073 unsigned ARMAsmParser::validateTargetOperandClass(MCParsedAsmOperand &AsmOp,
10075 ARMOperand &Op = static_cast<ARMOperand &>(AsmOp);
10076 // If the kind is a token for a literal immediate, check if our asm
10077 // operand matches. This is for InstAliases which have a fixed-value
10078 // immediate in the syntax.
10083 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op.getImm()))
10084 if (CE->getValue() == 0)
10085 return Match_Success;
10089 const MCExpr *SOExpr = Op.getImm();
10091 if (!SOExpr->EvaluateAsAbsolute(Value))
10092 return Match_Success;
10093 assert((Value >= INT32_MIN && Value <= UINT32_MAX) &&
10094 "expression value must be representable in 32 bits");
10099 MRI->getRegClass(ARM::GPRRegClassID).contains(Op.getReg()))
10100 return Match_Success;
10103 return Match_InvalidOperand;