1 //===-- ARMAsmParser.cpp - Parse ARM assembly to MCInst instructions ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "ARMFPUName.h"
11 #include "ARMFeatures.h"
12 #include "MCTargetDesc/ARMAddressingModes.h"
13 #include "MCTargetDesc/ARMArchName.h"
14 #include "MCTargetDesc/ARMBaseInfo.h"
15 #include "MCTargetDesc/ARMMCExpr.h"
16 #include "llvm/ADT/STLExtras.h"
17 #include "llvm/ADT/SmallVector.h"
18 #include "llvm/ADT/StringExtras.h"
19 #include "llvm/ADT/StringSwitch.h"
20 #include "llvm/ADT/Twine.h"
21 #include "llvm/MC/MCAsmInfo.h"
22 #include "llvm/MC/MCAssembler.h"
23 #include "llvm/MC/MCContext.h"
24 #include "llvm/MC/MCDisassembler.h"
25 #include "llvm/MC/MCELFStreamer.h"
26 #include "llvm/MC/MCExpr.h"
27 #include "llvm/MC/MCInst.h"
28 #include "llvm/MC/MCInstrDesc.h"
29 #include "llvm/MC/MCInstrInfo.h"
30 #include "llvm/MC/MCObjectFileInfo.h"
31 #include "llvm/MC/MCParser/MCAsmLexer.h"
32 #include "llvm/MC/MCParser/MCAsmParser.h"
33 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
34 #include "llvm/MC/MCRegisterInfo.h"
35 #include "llvm/MC/MCSection.h"
36 #include "llvm/MC/MCStreamer.h"
37 #include "llvm/MC/MCSubtargetInfo.h"
38 #include "llvm/MC/MCSymbol.h"
39 #include "llvm/MC/MCTargetAsmParser.h"
40 #include "llvm/Support/ARMBuildAttributes.h"
41 #include "llvm/Support/ARMEHABI.h"
42 #include "llvm/Support/COFF.h"
43 #include "llvm/Support/Debug.h"
44 #include "llvm/Support/ELF.h"
45 #include "llvm/Support/MathExtras.h"
46 #include "llvm/Support/SourceMgr.h"
47 #include "llvm/Support/TargetRegistry.h"
48 #include "llvm/Support/raw_ostream.h"
56 enum VectorLaneTy { NoLanes, AllLanes, IndexedLane };
61 typedef SmallVector<SMLoc, 4> Locs;
66 Locs PersonalityIndexLocs;
71 UnwindContext(MCAsmParser &P) : Parser(P), FPReg(ARM::SP) {}
73 bool hasFnStart() const { return !FnStartLocs.empty(); }
74 bool cantUnwind() const { return !CantUnwindLocs.empty(); }
75 bool hasHandlerData() const { return !HandlerDataLocs.empty(); }
76 bool hasPersonality() const {
77 return !(PersonalityLocs.empty() && PersonalityIndexLocs.empty());
80 void recordFnStart(SMLoc L) { FnStartLocs.push_back(L); }
81 void recordCantUnwind(SMLoc L) { CantUnwindLocs.push_back(L); }
82 void recordPersonality(SMLoc L) { PersonalityLocs.push_back(L); }
83 void recordHandlerData(SMLoc L) { HandlerDataLocs.push_back(L); }
84 void recordPersonalityIndex(SMLoc L) { PersonalityIndexLocs.push_back(L); }
86 void saveFPReg(int Reg) { FPReg = Reg; }
87 int getFPReg() const { return FPReg; }
89 void emitFnStartLocNotes() const {
90 for (Locs::const_iterator FI = FnStartLocs.begin(), FE = FnStartLocs.end();
92 Parser.Note(*FI, ".fnstart was specified here");
94 void emitCantUnwindLocNotes() const {
95 for (Locs::const_iterator UI = CantUnwindLocs.begin(),
96 UE = CantUnwindLocs.end(); UI != UE; ++UI)
97 Parser.Note(*UI, ".cantunwind was specified here");
99 void emitHandlerDataLocNotes() const {
100 for (Locs::const_iterator HI = HandlerDataLocs.begin(),
101 HE = HandlerDataLocs.end(); HI != HE; ++HI)
102 Parser.Note(*HI, ".handlerdata was specified here");
104 void emitPersonalityLocNotes() const {
105 for (Locs::const_iterator PI = PersonalityLocs.begin(),
106 PE = PersonalityLocs.end(),
107 PII = PersonalityIndexLocs.begin(),
108 PIE = PersonalityIndexLocs.end();
109 PI != PE || PII != PIE;) {
110 if (PI != PE && (PII == PIE || PI->getPointer() < PII->getPointer()))
111 Parser.Note(*PI++, ".personality was specified here");
112 else if (PII != PIE && (PI == PE || PII->getPointer() < PI->getPointer()))
113 Parser.Note(*PII++, ".personalityindex was specified here");
115 llvm_unreachable(".personality and .personalityindex cannot be "
116 "at the same location");
121 FnStartLocs = Locs();
122 CantUnwindLocs = Locs();
123 PersonalityLocs = Locs();
124 HandlerDataLocs = Locs();
125 PersonalityIndexLocs = Locs();
130 class ARMAsmParser : public MCTargetAsmParser {
131 MCSubtargetInfo &STI;
133 const MCInstrInfo &MII;
134 const MCRegisterInfo *MRI;
137 ARMTargetStreamer &getTargetStreamer() {
138 assert(getParser().getStreamer().getTargetStreamer() &&
139 "do not have a target streamer");
140 MCTargetStreamer &TS = *getParser().getStreamer().getTargetStreamer();
141 return static_cast<ARMTargetStreamer &>(TS);
144 // Map of register aliases registers via the .req directive.
145 StringMap<unsigned> RegisterReqs;
147 bool NextSymbolIsThumb;
150 ARMCC::CondCodes Cond; // Condition for IT block.
151 unsigned Mask:4; // Condition mask for instructions.
152 // Starting at first 1 (from lsb).
153 // '1' condition as indicated in IT.
154 // '0' inverse of condition (else).
155 // Count of instructions in IT block is
156 // 4 - trailingzeroes(mask)
158 bool FirstCond; // Explicit flag for when we're parsing the
159 // First instruction in the IT block. It's
160 // implied in the mask, so needs special
163 unsigned CurPosition; // Current position in parsing of IT
164 // block. In range [0,3]. Initialized
165 // according to count of instructions in block.
166 // ~0U if no active IT block.
168 bool inITBlock() { return ITState.CurPosition != ~0U;}
169 void forwardITPosition() {
170 if (!inITBlock()) return;
171 // Move to the next instruction in the IT block, if there is one. If not,
172 // mark the block as done.
173 unsigned TZ = countTrailingZeros(ITState.Mask);
174 if (++ITState.CurPosition == 5 - TZ)
175 ITState.CurPosition = ~0U; // Done with the IT block after this.
179 MCAsmParser &getParser() const { return Parser; }
180 MCAsmLexer &getLexer() const { return Parser.getLexer(); }
182 void Note(SMLoc L, const Twine &Msg, ArrayRef<SMRange> Ranges = None) {
183 return Parser.Note(L, Msg, Ranges);
185 bool Warning(SMLoc L, const Twine &Msg,
186 ArrayRef<SMRange> Ranges = None) {
187 return Parser.Warning(L, Msg, Ranges);
189 bool Error(SMLoc L, const Twine &Msg,
190 ArrayRef<SMRange> Ranges = None) {
191 return Parser.Error(L, Msg, Ranges);
194 int tryParseRegister();
195 bool tryParseRegisterWithWriteBack(OperandVector &);
196 int tryParseShiftRegister(OperandVector &);
197 bool parseRegisterList(OperandVector &);
198 bool parseMemory(OperandVector &);
199 bool parseOperand(OperandVector &, StringRef Mnemonic);
200 bool parsePrefix(ARMMCExpr::VariantKind &RefKind);
201 bool parseMemRegOffsetShift(ARM_AM::ShiftOpc &ShiftType,
202 unsigned &ShiftAmount);
203 bool parseLiteralValues(unsigned Size, SMLoc L);
204 bool parseDirectiveThumb(SMLoc L);
205 bool parseDirectiveARM(SMLoc L);
206 bool parseDirectiveThumbFunc(SMLoc L);
207 bool parseDirectiveCode(SMLoc L);
208 bool parseDirectiveSyntax(SMLoc L);
209 bool parseDirectiveReq(StringRef Name, SMLoc L);
210 bool parseDirectiveUnreq(SMLoc L);
211 bool parseDirectiveArch(SMLoc L);
212 bool parseDirectiveEabiAttr(SMLoc L);
213 bool parseDirectiveCPU(SMLoc L);
214 bool parseDirectiveFPU(SMLoc L);
215 bool parseDirectiveFnStart(SMLoc L);
216 bool parseDirectiveFnEnd(SMLoc L);
217 bool parseDirectiveCantUnwind(SMLoc L);
218 bool parseDirectivePersonality(SMLoc L);
219 bool parseDirectiveHandlerData(SMLoc L);
220 bool parseDirectiveSetFP(SMLoc L);
221 bool parseDirectivePad(SMLoc L);
222 bool parseDirectiveRegSave(SMLoc L, bool IsVector);
223 bool parseDirectiveInst(SMLoc L, char Suffix = '\0');
224 bool parseDirectiveLtorg(SMLoc L);
225 bool parseDirectiveEven(SMLoc L);
226 bool parseDirectivePersonalityIndex(SMLoc L);
227 bool parseDirectiveUnwindRaw(SMLoc L);
228 bool parseDirectiveTLSDescSeq(SMLoc L);
229 bool parseDirectiveMovSP(SMLoc L);
230 bool parseDirectiveObjectArch(SMLoc L);
231 bool parseDirectiveArchExtension(SMLoc L);
232 bool parseDirectiveAlign(SMLoc L);
233 bool parseDirectiveThumbSet(SMLoc L);
235 StringRef splitMnemonic(StringRef Mnemonic, unsigned &PredicationCode,
236 bool &CarrySetting, unsigned &ProcessorIMod,
238 void getMnemonicAcceptInfo(StringRef Mnemonic, StringRef FullInst,
239 bool &CanAcceptCarrySet,
240 bool &CanAcceptPredicationCode);
242 bool isThumb() const {
243 // FIXME: Can tablegen auto-generate this?
244 return (STI.getFeatureBits() & ARM::ModeThumb) != 0;
246 bool isThumbOne() const {
247 return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2) == 0;
249 bool isThumbTwo() const {
250 return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2);
252 bool hasThumb() const {
253 return STI.getFeatureBits() & ARM::HasV4TOps;
255 bool hasV6Ops() const {
256 return STI.getFeatureBits() & ARM::HasV6Ops;
258 bool hasV6MOps() const {
259 return STI.getFeatureBits() & ARM::HasV6MOps;
261 bool hasV7Ops() const {
262 return STI.getFeatureBits() & ARM::HasV7Ops;
264 bool hasV8Ops() const {
265 return STI.getFeatureBits() & ARM::HasV8Ops;
267 bool hasARM() const {
268 return !(STI.getFeatureBits() & ARM::FeatureNoARM);
270 bool hasThumb2DSP() const {
271 return STI.getFeatureBits() & ARM::FeatureDSPThumb2;
275 uint64_t FB = ComputeAvailableFeatures(STI.ToggleFeature(ARM::ModeThumb));
276 setAvailableFeatures(FB);
278 bool isMClass() const {
279 return STI.getFeatureBits() & ARM::FeatureMClass;
282 /// @name Auto-generated Match Functions
285 #define GET_ASSEMBLER_HEADER
286 #include "ARMGenAsmMatcher.inc"
290 OperandMatchResultTy parseITCondCode(OperandVector &);
291 OperandMatchResultTy parseCoprocNumOperand(OperandVector &);
292 OperandMatchResultTy parseCoprocRegOperand(OperandVector &);
293 OperandMatchResultTy parseCoprocOptionOperand(OperandVector &);
294 OperandMatchResultTy parseMemBarrierOptOperand(OperandVector &);
295 OperandMatchResultTy parseInstSyncBarrierOptOperand(OperandVector &);
296 OperandMatchResultTy parseProcIFlagsOperand(OperandVector &);
297 OperandMatchResultTy parseMSRMaskOperand(OperandVector &);
298 OperandMatchResultTy parseBankedRegOperand(OperandVector &);
299 OperandMatchResultTy parsePKHImm(OperandVector &O, StringRef Op, int Low,
301 OperandMatchResultTy parsePKHLSLImm(OperandVector &O) {
302 return parsePKHImm(O, "lsl", 0, 31);
304 OperandMatchResultTy parsePKHASRImm(OperandVector &O) {
305 return parsePKHImm(O, "asr", 1, 32);
307 OperandMatchResultTy parseSetEndImm(OperandVector &);
308 OperandMatchResultTy parseShifterImm(OperandVector &);
309 OperandMatchResultTy parseRotImm(OperandVector &);
310 OperandMatchResultTy parseBitfield(OperandVector &);
311 OperandMatchResultTy parsePostIdxReg(OperandVector &);
312 OperandMatchResultTy parseAM3Offset(OperandVector &);
313 OperandMatchResultTy parseFPImm(OperandVector &);
314 OperandMatchResultTy parseVectorList(OperandVector &);
315 OperandMatchResultTy parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index,
318 // Asm Match Converter Methods
319 void cvtThumbMultiply(MCInst &Inst, const OperandVector &);
320 void cvtThumbBranches(MCInst &Inst, const OperandVector &);
322 bool validateInstruction(MCInst &Inst, const OperandVector &Ops);
323 bool processInstruction(MCInst &Inst, const OperandVector &Ops);
324 bool shouldOmitCCOutOperand(StringRef Mnemonic, OperandVector &Operands);
325 bool shouldOmitPredicateOperand(StringRef Mnemonic, OperandVector &Operands);
328 enum ARMMatchResultTy {
329 Match_RequiresITBlock = FIRST_TARGET_MATCH_RESULT_TY,
330 Match_RequiresNotITBlock,
332 Match_RequiresThumb2,
333 #define GET_OPERAND_DIAGNOSTIC_TYPES
334 #include "ARMGenAsmMatcher.inc"
338 ARMAsmParser(MCSubtargetInfo &_STI, MCAsmParser &_Parser,
339 const MCInstrInfo &MII,
340 const MCTargetOptions &Options)
341 : MCTargetAsmParser(), STI(_STI), Parser(_Parser), MII(MII), UC(_Parser) {
342 MCAsmParserExtension::Initialize(_Parser);
344 // Cache the MCRegisterInfo.
345 MRI = getContext().getRegisterInfo();
347 // Initialize the set of available features.
348 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
350 // Not in an ITBlock to start with.
351 ITState.CurPosition = ~0U;
353 NextSymbolIsThumb = false;
356 // Implementation of the MCTargetAsmParser interface:
357 bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
358 bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
359 SMLoc NameLoc, OperandVector &Operands) override;
360 bool ParseDirective(AsmToken DirectiveID) override;
362 unsigned validateTargetOperandClass(MCParsedAsmOperand &Op,
363 unsigned Kind) override;
364 unsigned checkTargetMatchPredicate(MCInst &Inst) override;
366 bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
367 OperandVector &Operands, MCStreamer &Out,
369 bool MatchingInlineAsm) override;
370 void onLabelParsed(MCSymbol *Symbol) override;
372 } // end anonymous namespace
376 /// ARMOperand - Instances of this class represent a parsed ARM machine
378 class ARMOperand : public MCParsedAsmOperand {
388 k_InstSyncBarrierOpt,
400 k_VectorListAllLanes,
406 k_BitfieldDescriptor,
410 SMLoc StartLoc, EndLoc, AlignmentLoc;
411 SmallVector<unsigned, 8> Registers;
414 ARMCC::CondCodes Val;
421 struct CoprocOptionOp {
434 ARM_ISB::InstSyncBOpt Val;
438 ARM_PROC::IFlags Val;
458 // A vector register list is a sequential list of 1 to 4 registers.
459 struct VectorListOp {
466 struct VectorIndexOp {
474 /// Combined record for all forms of ARM address expressions.
477 // Offset is in OffsetReg or OffsetImm. If both are zero, no offset
479 const MCConstantExpr *OffsetImm; // Offset immediate value
480 unsigned OffsetRegNum; // Offset register num, when OffsetImm == NULL
481 ARM_AM::ShiftOpc ShiftType; // Shift type for OffsetReg
482 unsigned ShiftImm; // shift for OffsetReg.
483 unsigned Alignment; // 0 = no alignment specified
484 // n = alignment in bytes (2, 4, 8, 16, or 32)
485 unsigned isNegative : 1; // Negated OffsetReg? (~'U' bit)
488 struct PostIdxRegOp {
491 ARM_AM::ShiftOpc ShiftTy;
495 struct ShifterImmOp {
500 struct RegShiftedRegOp {
501 ARM_AM::ShiftOpc ShiftTy;
507 struct RegShiftedImmOp {
508 ARM_AM::ShiftOpc ShiftTy;
525 struct CoprocOptionOp CoprocOption;
526 struct MBOptOp MBOpt;
527 struct ISBOptOp ISBOpt;
528 struct ITMaskOp ITMask;
529 struct IFlagsOp IFlags;
530 struct MMaskOp MMask;
531 struct BankedRegOp BankedReg;
534 struct VectorListOp VectorList;
535 struct VectorIndexOp VectorIndex;
537 struct MemoryOp Memory;
538 struct PostIdxRegOp PostIdxReg;
539 struct ShifterImmOp ShifterImm;
540 struct RegShiftedRegOp RegShiftedReg;
541 struct RegShiftedImmOp RegShiftedImm;
542 struct RotImmOp RotImm;
543 struct BitfieldOp Bitfield;
547 ARMOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
548 ARMOperand(const ARMOperand &o) : MCParsedAsmOperand() {
550 StartLoc = o.StartLoc;
567 case k_DPRRegisterList:
568 case k_SPRRegisterList:
569 Registers = o.Registers;
572 case k_VectorListAllLanes:
573 case k_VectorListIndexed:
574 VectorList = o.VectorList;
581 CoprocOption = o.CoprocOption;
586 case k_MemBarrierOpt:
589 case k_InstSyncBarrierOpt:
594 case k_PostIndexRegister:
595 PostIdxReg = o.PostIdxReg;
601 BankedReg = o.BankedReg;
606 case k_ShifterImmediate:
607 ShifterImm = o.ShifterImm;
609 case k_ShiftedRegister:
610 RegShiftedReg = o.RegShiftedReg;
612 case k_ShiftedImmediate:
613 RegShiftedImm = o.RegShiftedImm;
615 case k_RotateImmediate:
618 case k_BitfieldDescriptor:
619 Bitfield = o.Bitfield;
622 VectorIndex = o.VectorIndex;
627 /// getStartLoc - Get the location of the first token of this operand.
628 SMLoc getStartLoc() const override { return StartLoc; }
629 /// getEndLoc - Get the location of the last token of this operand.
630 SMLoc getEndLoc() const override { return EndLoc; }
631 /// getLocRange - Get the range between the first and last token of this
633 SMRange getLocRange() const { return SMRange(StartLoc, EndLoc); }
635 /// getAlignmentLoc - Get the location of the Alignment token of this operand.
636 SMLoc getAlignmentLoc() const {
637 assert(Kind == k_Memory && "Invalid access!");
641 ARMCC::CondCodes getCondCode() const {
642 assert(Kind == k_CondCode && "Invalid access!");
646 unsigned getCoproc() const {
647 assert((Kind == k_CoprocNum || Kind == k_CoprocReg) && "Invalid access!");
651 StringRef getToken() const {
652 assert(Kind == k_Token && "Invalid access!");
653 return StringRef(Tok.Data, Tok.Length);
656 unsigned getReg() const override {
657 assert((Kind == k_Register || Kind == k_CCOut) && "Invalid access!");
661 const SmallVectorImpl<unsigned> &getRegList() const {
662 assert((Kind == k_RegisterList || Kind == k_DPRRegisterList ||
663 Kind == k_SPRRegisterList) && "Invalid access!");
667 const MCExpr *getImm() const {
668 assert(isImm() && "Invalid access!");
672 unsigned getVectorIndex() const {
673 assert(Kind == k_VectorIndex && "Invalid access!");
674 return VectorIndex.Val;
677 ARM_MB::MemBOpt getMemBarrierOpt() const {
678 assert(Kind == k_MemBarrierOpt && "Invalid access!");
682 ARM_ISB::InstSyncBOpt getInstSyncBarrierOpt() const {
683 assert(Kind == k_InstSyncBarrierOpt && "Invalid access!");
687 ARM_PROC::IFlags getProcIFlags() const {
688 assert(Kind == k_ProcIFlags && "Invalid access!");
692 unsigned getMSRMask() const {
693 assert(Kind == k_MSRMask && "Invalid access!");
697 unsigned getBankedReg() const {
698 assert(Kind == k_BankedReg && "Invalid access!");
699 return BankedReg.Val;
702 bool isCoprocNum() const { return Kind == k_CoprocNum; }
703 bool isCoprocReg() const { return Kind == k_CoprocReg; }
704 bool isCoprocOption() const { return Kind == k_CoprocOption; }
705 bool isCondCode() const { return Kind == k_CondCode; }
706 bool isCCOut() const { return Kind == k_CCOut; }
707 bool isITMask() const { return Kind == k_ITCondMask; }
708 bool isITCondCode() const { return Kind == k_CondCode; }
709 bool isImm() const override { return Kind == k_Immediate; }
710 // checks whether this operand is an unsigned offset which fits is a field
711 // of specified width and scaled by a specific number of bits
712 template<unsigned width, unsigned scale>
713 bool isUnsignedOffset() const {
714 if (!isImm()) return false;
715 if (isa<MCSymbolRefExpr>(Imm.Val)) return true;
716 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val)) {
717 int64_t Val = CE->getValue();
718 int64_t Align = 1LL << scale;
719 int64_t Max = Align * ((1LL << width) - 1);
720 return ((Val % Align) == 0) && (Val >= 0) && (Val <= Max);
724 // checks whether this operand is an signed offset which fits is a field
725 // of specified width and scaled by a specific number of bits
726 template<unsigned width, unsigned scale>
727 bool isSignedOffset() const {
728 if (!isImm()) return false;
729 if (isa<MCSymbolRefExpr>(Imm.Val)) return true;
730 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val)) {
731 int64_t Val = CE->getValue();
732 int64_t Align = 1LL << scale;
733 int64_t Max = Align * ((1LL << (width-1)) - 1);
734 int64_t Min = -Align * (1LL << (width-1));
735 return ((Val % Align) == 0) && (Val >= Min) && (Val <= Max);
740 // checks whether this operand is a memory operand computed as an offset
741 // applied to PC. the offset may have 8 bits of magnitude and is represented
742 // with two bits of shift. textually it may be either [pc, #imm], #imm or
743 // relocable expression...
744 bool isThumbMemPC() const {
747 if (isa<MCSymbolRefExpr>(Imm.Val)) return true;
748 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val);
749 if (!CE) return false;
750 Val = CE->getValue();
753 if(!Memory.OffsetImm || Memory.OffsetRegNum) return false;
754 if(Memory.BaseRegNum != ARM::PC) return false;
755 Val = Memory.OffsetImm->getValue();
758 return ((Val % 4) == 0) && (Val >= 0) && (Val <= 1020);
760 bool isFPImm() const {
761 if (!isImm()) return false;
762 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
763 if (!CE) return false;
764 int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue()));
767 bool isFBits16() const {
768 if (!isImm()) return false;
769 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
770 if (!CE) return false;
771 int64_t Value = CE->getValue();
772 return Value >= 0 && Value <= 16;
774 bool isFBits32() const {
775 if (!isImm()) return false;
776 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
777 if (!CE) return false;
778 int64_t Value = CE->getValue();
779 return Value >= 1 && Value <= 32;
781 bool isImm8s4() const {
782 if (!isImm()) return false;
783 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
784 if (!CE) return false;
785 int64_t Value = CE->getValue();
786 return ((Value & 3) == 0) && Value >= -1020 && Value <= 1020;
788 bool isImm0_1020s4() const {
789 if (!isImm()) return false;
790 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
791 if (!CE) return false;
792 int64_t Value = CE->getValue();
793 return ((Value & 3) == 0) && Value >= 0 && Value <= 1020;
795 bool isImm0_508s4() const {
796 if (!isImm()) return false;
797 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
798 if (!CE) return false;
799 int64_t Value = CE->getValue();
800 return ((Value & 3) == 0) && Value >= 0 && Value <= 508;
802 bool isImm0_508s4Neg() const {
803 if (!isImm()) return false;
804 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
805 if (!CE) return false;
806 int64_t Value = -CE->getValue();
807 // explicitly exclude zero. we want that to use the normal 0_508 version.
808 return ((Value & 3) == 0) && Value > 0 && Value <= 508;
810 bool isImm0_239() const {
811 if (!isImm()) return false;
812 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
813 if (!CE) return false;
814 int64_t Value = CE->getValue();
815 return Value >= 0 && Value < 240;
817 bool isImm0_255() const {
818 if (!isImm()) return false;
819 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
820 if (!CE) return false;
821 int64_t Value = CE->getValue();
822 return Value >= 0 && Value < 256;
824 bool isImm0_4095() const {
825 if (!isImm()) return false;
826 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
827 if (!CE) return false;
828 int64_t Value = CE->getValue();
829 return Value >= 0 && Value < 4096;
831 bool isImm0_4095Neg() const {
832 if (!isImm()) return false;
833 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
834 if (!CE) return false;
835 int64_t Value = -CE->getValue();
836 return Value > 0 && Value < 4096;
838 bool isImm0_1() const {
839 if (!isImm()) return false;
840 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
841 if (!CE) return false;
842 int64_t Value = CE->getValue();
843 return Value >= 0 && Value < 2;
845 bool isImm0_3() const {
846 if (!isImm()) return false;
847 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
848 if (!CE) return false;
849 int64_t Value = CE->getValue();
850 return Value >= 0 && Value < 4;
852 bool isImm0_7() const {
853 if (!isImm()) return false;
854 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
855 if (!CE) return false;
856 int64_t Value = CE->getValue();
857 return Value >= 0 && Value < 8;
859 bool isImm0_15() const {
860 if (!isImm()) return false;
861 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
862 if (!CE) return false;
863 int64_t Value = CE->getValue();
864 return Value >= 0 && Value < 16;
866 bool isImm0_31() const {
867 if (!isImm()) return false;
868 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
869 if (!CE) return false;
870 int64_t Value = CE->getValue();
871 return Value >= 0 && Value < 32;
873 bool isImm0_63() const {
874 if (!isImm()) return false;
875 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
876 if (!CE) return false;
877 int64_t Value = CE->getValue();
878 return Value >= 0 && Value < 64;
880 bool isImm8() const {
881 if (!isImm()) return false;
882 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
883 if (!CE) return false;
884 int64_t Value = CE->getValue();
887 bool isImm16() const {
888 if (!isImm()) return false;
889 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
890 if (!CE) return false;
891 int64_t Value = CE->getValue();
894 bool isImm32() const {
895 if (!isImm()) return false;
896 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
897 if (!CE) return false;
898 int64_t Value = CE->getValue();
901 bool isShrImm8() const {
902 if (!isImm()) return false;
903 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
904 if (!CE) return false;
905 int64_t Value = CE->getValue();
906 return Value > 0 && Value <= 8;
908 bool isShrImm16() const {
909 if (!isImm()) return false;
910 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
911 if (!CE) return false;
912 int64_t Value = CE->getValue();
913 return Value > 0 && Value <= 16;
915 bool isShrImm32() const {
916 if (!isImm()) return false;
917 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
918 if (!CE) return false;
919 int64_t Value = CE->getValue();
920 return Value > 0 && Value <= 32;
922 bool isShrImm64() const {
923 if (!isImm()) return false;
924 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
925 if (!CE) return false;
926 int64_t Value = CE->getValue();
927 return Value > 0 && Value <= 64;
929 bool isImm1_7() const {
930 if (!isImm()) return false;
931 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
932 if (!CE) return false;
933 int64_t Value = CE->getValue();
934 return Value > 0 && Value < 8;
936 bool isImm1_15() const {
937 if (!isImm()) return false;
938 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
939 if (!CE) return false;
940 int64_t Value = CE->getValue();
941 return Value > 0 && Value < 16;
943 bool isImm1_31() const {
944 if (!isImm()) return false;
945 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
946 if (!CE) return false;
947 int64_t Value = CE->getValue();
948 return Value > 0 && Value < 32;
950 bool isImm1_16() const {
951 if (!isImm()) return false;
952 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
953 if (!CE) return false;
954 int64_t Value = CE->getValue();
955 return Value > 0 && Value < 17;
957 bool isImm1_32() const {
958 if (!isImm()) return false;
959 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
960 if (!CE) return false;
961 int64_t Value = CE->getValue();
962 return Value > 0 && Value < 33;
964 bool isImm0_32() const {
965 if (!isImm()) return false;
966 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
967 if (!CE) return false;
968 int64_t Value = CE->getValue();
969 return Value >= 0 && Value < 33;
971 bool isImm0_65535() const {
972 if (!isImm()) return false;
973 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
974 if (!CE) return false;
975 int64_t Value = CE->getValue();
976 return Value >= 0 && Value < 65536;
978 bool isImm256_65535Expr() const {
979 if (!isImm()) return false;
980 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
981 // If it's not a constant expression, it'll generate a fixup and be
983 if (!CE) return true;
984 int64_t Value = CE->getValue();
985 return Value >= 256 && Value < 65536;
987 bool isImm0_65535Expr() const {
988 if (!isImm()) return false;
989 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
990 // If it's not a constant expression, it'll generate a fixup and be
992 if (!CE) return true;
993 int64_t Value = CE->getValue();
994 return Value >= 0 && Value < 65536;
996 bool isImm24bit() const {
997 if (!isImm()) return false;
998 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
999 if (!CE) return false;
1000 int64_t Value = CE->getValue();
1001 return Value >= 0 && Value <= 0xffffff;
1003 bool isImmThumbSR() const {
1004 if (!isImm()) return false;
1005 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1006 if (!CE) return false;
1007 int64_t Value = CE->getValue();
1008 return Value > 0 && Value < 33;
1010 bool isPKHLSLImm() const {
1011 if (!isImm()) return false;
1012 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1013 if (!CE) return false;
1014 int64_t Value = CE->getValue();
1015 return Value >= 0 && Value < 32;
1017 bool isPKHASRImm() const {
1018 if (!isImm()) return false;
1019 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1020 if (!CE) return false;
1021 int64_t Value = CE->getValue();
1022 return Value > 0 && Value <= 32;
1024 bool isAdrLabel() const {
1025 // If we have an immediate that's not a constant, treat it as a label
1026 // reference needing a fixup. If it is a constant, but it can't fit
1027 // into shift immediate encoding, we reject it.
1028 if (isImm() && !isa<MCConstantExpr>(getImm())) return true;
1029 else return (isARMSOImm() || isARMSOImmNeg());
1031 bool isARMSOImm() const {
1032 if (!isImm()) return false;
1033 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1034 if (!CE) return false;
1035 int64_t Value = CE->getValue();
1036 return ARM_AM::getSOImmVal(Value) != -1;
1038 bool isARMSOImmNot() const {
1039 if (!isImm()) return false;
1040 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1041 if (!CE) return false;
1042 int64_t Value = CE->getValue();
1043 return ARM_AM::getSOImmVal(~Value) != -1;
1045 bool isARMSOImmNeg() const {
1046 if (!isImm()) return false;
1047 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1048 if (!CE) return false;
1049 int64_t Value = CE->getValue();
1050 // Only use this when not representable as a plain so_imm.
1051 return ARM_AM::getSOImmVal(Value) == -1 &&
1052 ARM_AM::getSOImmVal(-Value) != -1;
1054 bool isT2SOImm() const {
1055 if (!isImm()) return false;
1056 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1057 if (!CE) return false;
1058 int64_t Value = CE->getValue();
1059 return ARM_AM::getT2SOImmVal(Value) != -1;
1061 bool isT2SOImmNot() const {
1062 if (!isImm()) return false;
1063 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1064 if (!CE) return false;
1065 int64_t Value = CE->getValue();
1066 return ARM_AM::getT2SOImmVal(Value) == -1 &&
1067 ARM_AM::getT2SOImmVal(~Value) != -1;
1069 bool isT2SOImmNeg() const {
1070 if (!isImm()) return false;
1071 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1072 if (!CE) return false;
1073 int64_t Value = CE->getValue();
1074 // Only use this when not representable as a plain so_imm.
1075 return ARM_AM::getT2SOImmVal(Value) == -1 &&
1076 ARM_AM::getT2SOImmVal(-Value) != -1;
1078 bool isSetEndImm() const {
1079 if (!isImm()) return false;
1080 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1081 if (!CE) return false;
1082 int64_t Value = CE->getValue();
1083 return Value == 1 || Value == 0;
1085 bool isReg() const override { return Kind == k_Register; }
1086 bool isRegList() const { return Kind == k_RegisterList; }
1087 bool isDPRRegList() const { return Kind == k_DPRRegisterList; }
1088 bool isSPRRegList() const { return Kind == k_SPRRegisterList; }
1089 bool isToken() const override { return Kind == k_Token; }
1090 bool isMemBarrierOpt() const { return Kind == k_MemBarrierOpt; }
1091 bool isInstSyncBarrierOpt() const { return Kind == k_InstSyncBarrierOpt; }
1092 bool isMem() const override { return Kind == k_Memory; }
1093 bool isShifterImm() const { return Kind == k_ShifterImmediate; }
1094 bool isRegShiftedReg() const { return Kind == k_ShiftedRegister; }
1095 bool isRegShiftedImm() const { return Kind == k_ShiftedImmediate; }
1096 bool isRotImm() const { return Kind == k_RotateImmediate; }
1097 bool isBitfield() const { return Kind == k_BitfieldDescriptor; }
1098 bool isPostIdxRegShifted() const { return Kind == k_PostIndexRegister; }
1099 bool isPostIdxReg() const {
1100 return Kind == k_PostIndexRegister && PostIdxReg.ShiftTy ==ARM_AM::no_shift;
1102 bool isMemNoOffset(bool alignOK = false, unsigned Alignment = 0) const {
1105 // No offset of any kind.
1106 return Memory.OffsetRegNum == 0 && Memory.OffsetImm == nullptr &&
1107 (alignOK || Memory.Alignment == Alignment);
1109 bool isMemPCRelImm12() const {
1110 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1112 // Base register must be PC.
1113 if (Memory.BaseRegNum != ARM::PC)
1115 // Immediate offset in range [-4095, 4095].
1116 if (!Memory.OffsetImm) return true;
1117 int64_t Val = Memory.OffsetImm->getValue();
1118 return (Val > -4096 && Val < 4096) || (Val == INT32_MIN);
1120 bool isAlignedMemory() const {
1121 return isMemNoOffset(true);
1123 bool isAlignedMemoryNone() const {
1124 return isMemNoOffset(false, 0);
1126 bool isDupAlignedMemoryNone() const {
1127 return isMemNoOffset(false, 0);
1129 bool isAlignedMemory16() const {
1130 if (isMemNoOffset(false, 2)) // alignment in bytes for 16-bits is 2.
1132 return isMemNoOffset(false, 0);
1134 bool isDupAlignedMemory16() const {
1135 if (isMemNoOffset(false, 2)) // alignment in bytes for 16-bits is 2.
1137 return isMemNoOffset(false, 0);
1139 bool isAlignedMemory32() const {
1140 if (isMemNoOffset(false, 4)) // alignment in bytes for 32-bits is 4.
1142 return isMemNoOffset(false, 0);
1144 bool isDupAlignedMemory32() const {
1145 if (isMemNoOffset(false, 4)) // alignment in bytes for 32-bits is 4.
1147 return isMemNoOffset(false, 0);
1149 bool isAlignedMemory64() const {
1150 if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8.
1152 return isMemNoOffset(false, 0);
1154 bool isDupAlignedMemory64() const {
1155 if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8.
1157 return isMemNoOffset(false, 0);
1159 bool isAlignedMemory64or128() const {
1160 if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8.
1162 if (isMemNoOffset(false, 16)) // alignment in bytes for 128-bits is 16.
1164 return isMemNoOffset(false, 0);
1166 bool isDupAlignedMemory64or128() const {
1167 if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8.
1169 if (isMemNoOffset(false, 16)) // alignment in bytes for 128-bits is 16.
1171 return isMemNoOffset(false, 0);
1173 bool isAlignedMemory64or128or256() const {
1174 if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8.
1176 if (isMemNoOffset(false, 16)) // alignment in bytes for 128-bits is 16.
1178 if (isMemNoOffset(false, 32)) // alignment in bytes for 256-bits is 32.
1180 return isMemNoOffset(false, 0);
1182 bool isAddrMode2() const {
1183 if (!isMem() || Memory.Alignment != 0) return false;
1184 // Check for register offset.
1185 if (Memory.OffsetRegNum) return true;
1186 // Immediate offset in range [-4095, 4095].
1187 if (!Memory.OffsetImm) return true;
1188 int64_t Val = Memory.OffsetImm->getValue();
1189 return Val > -4096 && Val < 4096;
1191 bool isAM2OffsetImm() const {
1192 if (!isImm()) return false;
1193 // Immediate offset in range [-4095, 4095].
1194 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1195 if (!CE) return false;
1196 int64_t Val = CE->getValue();
1197 return (Val == INT32_MIN) || (Val > -4096 && Val < 4096);
1199 bool isAddrMode3() const {
1200 // If we have an immediate that's not a constant, treat it as a label
1201 // reference needing a fixup. If it is a constant, it's something else
1202 // and we reject it.
1203 if (isImm() && !isa<MCConstantExpr>(getImm()))
1205 if (!isMem() || Memory.Alignment != 0) return false;
1206 // No shifts are legal for AM3.
1207 if (Memory.ShiftType != ARM_AM::no_shift) return false;
1208 // Check for register offset.
1209 if (Memory.OffsetRegNum) return true;
1210 // Immediate offset in range [-255, 255].
1211 if (!Memory.OffsetImm) return true;
1212 int64_t Val = Memory.OffsetImm->getValue();
1213 // The #-0 offset is encoded as INT32_MIN, and we have to check
1215 return (Val > -256 && Val < 256) || Val == INT32_MIN;
1217 bool isAM3Offset() const {
1218 if (Kind != k_Immediate && Kind != k_PostIndexRegister)
1220 if (Kind == k_PostIndexRegister)
1221 return PostIdxReg.ShiftTy == ARM_AM::no_shift;
1222 // Immediate offset in range [-255, 255].
1223 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1224 if (!CE) return false;
1225 int64_t Val = CE->getValue();
1226 // Special case, #-0 is INT32_MIN.
1227 return (Val > -256 && Val < 256) || Val == INT32_MIN;
1229 bool isAddrMode5() const {
1230 // If we have an immediate that's not a constant, treat it as a label
1231 // reference needing a fixup. If it is a constant, it's something else
1232 // and we reject it.
1233 if (isImm() && !isa<MCConstantExpr>(getImm()))
1235 if (!isMem() || Memory.Alignment != 0) return false;
1236 // Check for register offset.
1237 if (Memory.OffsetRegNum) return false;
1238 // Immediate offset in range [-1020, 1020] and a multiple of 4.
1239 if (!Memory.OffsetImm) return true;
1240 int64_t Val = Memory.OffsetImm->getValue();
1241 return (Val >= -1020 && Val <= 1020 && ((Val & 3) == 0)) ||
1244 bool isMemTBB() const {
1245 if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1246 Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0)
1250 bool isMemTBH() const {
1251 if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1252 Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm != 1 ||
1253 Memory.Alignment != 0 )
1257 bool isMemRegOffset() const {
1258 if (!isMem() || !Memory.OffsetRegNum || Memory.Alignment != 0)
1262 bool isT2MemRegOffset() const {
1263 if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1264 Memory.Alignment != 0)
1266 // Only lsl #{0, 1, 2, 3} allowed.
1267 if (Memory.ShiftType == ARM_AM::no_shift)
1269 if (Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm > 3)
1273 bool isMemThumbRR() const {
1274 // Thumb reg+reg addressing is simple. Just two registers, a base and
1275 // an offset. No shifts, negations or any other complicating factors.
1276 if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1277 Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0)
1279 return isARMLowRegister(Memory.BaseRegNum) &&
1280 (!Memory.OffsetRegNum || isARMLowRegister(Memory.OffsetRegNum));
1282 bool isMemThumbRIs4() const {
1283 if (!isMem() || Memory.OffsetRegNum != 0 ||
1284 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
1286 // Immediate offset, multiple of 4 in range [0, 124].
1287 if (!Memory.OffsetImm) return true;
1288 int64_t Val = Memory.OffsetImm->getValue();
1289 return Val >= 0 && Val <= 124 && (Val % 4) == 0;
1291 bool isMemThumbRIs2() const {
1292 if (!isMem() || Memory.OffsetRegNum != 0 ||
1293 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
1295 // Immediate offset, multiple of 4 in range [0, 62].
1296 if (!Memory.OffsetImm) return true;
1297 int64_t Val = Memory.OffsetImm->getValue();
1298 return Val >= 0 && Val <= 62 && (Val % 2) == 0;
1300 bool isMemThumbRIs1() const {
1301 if (!isMem() || Memory.OffsetRegNum != 0 ||
1302 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
1304 // Immediate offset in range [0, 31].
1305 if (!Memory.OffsetImm) return true;
1306 int64_t Val = Memory.OffsetImm->getValue();
1307 return Val >= 0 && Val <= 31;
1309 bool isMemThumbSPI() const {
1310 if (!isMem() || Memory.OffsetRegNum != 0 ||
1311 Memory.BaseRegNum != ARM::SP || Memory.Alignment != 0)
1313 // Immediate offset, multiple of 4 in range [0, 1020].
1314 if (!Memory.OffsetImm) return true;
1315 int64_t Val = Memory.OffsetImm->getValue();
1316 return Val >= 0 && Val <= 1020 && (Val % 4) == 0;
1318 bool isMemImm8s4Offset() const {
1319 // If we have an immediate that's not a constant, treat it as a label
1320 // reference needing a fixup. If it is a constant, it's something else
1321 // and we reject it.
1322 if (isImm() && !isa<MCConstantExpr>(getImm()))
1324 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1326 // Immediate offset a multiple of 4 in range [-1020, 1020].
1327 if (!Memory.OffsetImm) return true;
1328 int64_t Val = Memory.OffsetImm->getValue();
1329 // Special case, #-0 is INT32_MIN.
1330 return (Val >= -1020 && Val <= 1020 && (Val & 3) == 0) || Val == INT32_MIN;
1332 bool isMemImm0_1020s4Offset() const {
1333 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1335 // Immediate offset a multiple of 4 in range [0, 1020].
1336 if (!Memory.OffsetImm) return true;
1337 int64_t Val = Memory.OffsetImm->getValue();
1338 return Val >= 0 && Val <= 1020 && (Val & 3) == 0;
1340 bool isMemImm8Offset() const {
1341 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1343 // Base reg of PC isn't allowed for these encodings.
1344 if (Memory.BaseRegNum == ARM::PC) return false;
1345 // Immediate offset in range [-255, 255].
1346 if (!Memory.OffsetImm) return true;
1347 int64_t Val = Memory.OffsetImm->getValue();
1348 return (Val == INT32_MIN) || (Val > -256 && Val < 256);
1350 bool isMemPosImm8Offset() const {
1351 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1353 // Immediate offset in range [0, 255].
1354 if (!Memory.OffsetImm) return true;
1355 int64_t Val = Memory.OffsetImm->getValue();
1356 return Val >= 0 && Val < 256;
1358 bool isMemNegImm8Offset() const {
1359 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1361 // Base reg of PC isn't allowed for these encodings.
1362 if (Memory.BaseRegNum == ARM::PC) return false;
1363 // Immediate offset in range [-255, -1].
1364 if (!Memory.OffsetImm) return false;
1365 int64_t Val = Memory.OffsetImm->getValue();
1366 return (Val == INT32_MIN) || (Val > -256 && Val < 0);
1368 bool isMemUImm12Offset() const {
1369 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1371 // Immediate offset in range [0, 4095].
1372 if (!Memory.OffsetImm) return true;
1373 int64_t Val = Memory.OffsetImm->getValue();
1374 return (Val >= 0 && Val < 4096);
1376 bool isMemImm12Offset() const {
1377 // If we have an immediate that's not a constant, treat it as a label
1378 // reference needing a fixup. If it is a constant, it's something else
1379 // and we reject it.
1380 if (isImm() && !isa<MCConstantExpr>(getImm()))
1383 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1385 // Immediate offset in range [-4095, 4095].
1386 if (!Memory.OffsetImm) return true;
1387 int64_t Val = Memory.OffsetImm->getValue();
1388 return (Val > -4096 && Val < 4096) || (Val == INT32_MIN);
1390 bool isPostIdxImm8() const {
1391 if (!isImm()) return false;
1392 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1393 if (!CE) return false;
1394 int64_t Val = CE->getValue();
1395 return (Val > -256 && Val < 256) || (Val == INT32_MIN);
1397 bool isPostIdxImm8s4() const {
1398 if (!isImm()) return false;
1399 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1400 if (!CE) return false;
1401 int64_t Val = CE->getValue();
1402 return ((Val & 3) == 0 && Val >= -1020 && Val <= 1020) ||
1406 bool isMSRMask() const { return Kind == k_MSRMask; }
1407 bool isBankedReg() const { return Kind == k_BankedReg; }
1408 bool isProcIFlags() const { return Kind == k_ProcIFlags; }
1411 bool isSingleSpacedVectorList() const {
1412 return Kind == k_VectorList && !VectorList.isDoubleSpaced;
1414 bool isDoubleSpacedVectorList() const {
1415 return Kind == k_VectorList && VectorList.isDoubleSpaced;
1417 bool isVecListOneD() const {
1418 if (!isSingleSpacedVectorList()) return false;
1419 return VectorList.Count == 1;
1422 bool isVecListDPair() const {
1423 if (!isSingleSpacedVectorList()) return false;
1424 return (ARMMCRegisterClasses[ARM::DPairRegClassID]
1425 .contains(VectorList.RegNum));
1428 bool isVecListThreeD() const {
1429 if (!isSingleSpacedVectorList()) return false;
1430 return VectorList.Count == 3;
1433 bool isVecListFourD() const {
1434 if (!isSingleSpacedVectorList()) return false;
1435 return VectorList.Count == 4;
1438 bool isVecListDPairSpaced() const {
1439 if (Kind != k_VectorList) return false;
1440 if (isSingleSpacedVectorList()) return false;
1441 return (ARMMCRegisterClasses[ARM::DPairSpcRegClassID]
1442 .contains(VectorList.RegNum));
1445 bool isVecListThreeQ() const {
1446 if (!isDoubleSpacedVectorList()) return false;
1447 return VectorList.Count == 3;
1450 bool isVecListFourQ() const {
1451 if (!isDoubleSpacedVectorList()) return false;
1452 return VectorList.Count == 4;
1455 bool isSingleSpacedVectorAllLanes() const {
1456 return Kind == k_VectorListAllLanes && !VectorList.isDoubleSpaced;
1458 bool isDoubleSpacedVectorAllLanes() const {
1459 return Kind == k_VectorListAllLanes && VectorList.isDoubleSpaced;
1461 bool isVecListOneDAllLanes() const {
1462 if (!isSingleSpacedVectorAllLanes()) return false;
1463 return VectorList.Count == 1;
1466 bool isVecListDPairAllLanes() const {
1467 if (!isSingleSpacedVectorAllLanes()) return false;
1468 return (ARMMCRegisterClasses[ARM::DPairRegClassID]
1469 .contains(VectorList.RegNum));
1472 bool isVecListDPairSpacedAllLanes() const {
1473 if (!isDoubleSpacedVectorAllLanes()) return false;
1474 return VectorList.Count == 2;
1477 bool isVecListThreeDAllLanes() const {
1478 if (!isSingleSpacedVectorAllLanes()) return false;
1479 return VectorList.Count == 3;
1482 bool isVecListThreeQAllLanes() const {
1483 if (!isDoubleSpacedVectorAllLanes()) return false;
1484 return VectorList.Count == 3;
1487 bool isVecListFourDAllLanes() const {
1488 if (!isSingleSpacedVectorAllLanes()) return false;
1489 return VectorList.Count == 4;
1492 bool isVecListFourQAllLanes() const {
1493 if (!isDoubleSpacedVectorAllLanes()) return false;
1494 return VectorList.Count == 4;
1497 bool isSingleSpacedVectorIndexed() const {
1498 return Kind == k_VectorListIndexed && !VectorList.isDoubleSpaced;
1500 bool isDoubleSpacedVectorIndexed() const {
1501 return Kind == k_VectorListIndexed && VectorList.isDoubleSpaced;
1503 bool isVecListOneDByteIndexed() const {
1504 if (!isSingleSpacedVectorIndexed()) return false;
1505 return VectorList.Count == 1 && VectorList.LaneIndex <= 7;
1508 bool isVecListOneDHWordIndexed() const {
1509 if (!isSingleSpacedVectorIndexed()) return false;
1510 return VectorList.Count == 1 && VectorList.LaneIndex <= 3;
1513 bool isVecListOneDWordIndexed() const {
1514 if (!isSingleSpacedVectorIndexed()) return false;
1515 return VectorList.Count == 1 && VectorList.LaneIndex <= 1;
1518 bool isVecListTwoDByteIndexed() const {
1519 if (!isSingleSpacedVectorIndexed()) return false;
1520 return VectorList.Count == 2 && VectorList.LaneIndex <= 7;
1523 bool isVecListTwoDHWordIndexed() const {
1524 if (!isSingleSpacedVectorIndexed()) return false;
1525 return VectorList.Count == 2 && VectorList.LaneIndex <= 3;
1528 bool isVecListTwoQWordIndexed() const {
1529 if (!isDoubleSpacedVectorIndexed()) return false;
1530 return VectorList.Count == 2 && VectorList.LaneIndex <= 1;
1533 bool isVecListTwoQHWordIndexed() const {
1534 if (!isDoubleSpacedVectorIndexed()) return false;
1535 return VectorList.Count == 2 && VectorList.LaneIndex <= 3;
1538 bool isVecListTwoDWordIndexed() const {
1539 if (!isSingleSpacedVectorIndexed()) return false;
1540 return VectorList.Count == 2 && VectorList.LaneIndex <= 1;
1543 bool isVecListThreeDByteIndexed() const {
1544 if (!isSingleSpacedVectorIndexed()) return false;
1545 return VectorList.Count == 3 && VectorList.LaneIndex <= 7;
1548 bool isVecListThreeDHWordIndexed() const {
1549 if (!isSingleSpacedVectorIndexed()) return false;
1550 return VectorList.Count == 3 && VectorList.LaneIndex <= 3;
1553 bool isVecListThreeQWordIndexed() const {
1554 if (!isDoubleSpacedVectorIndexed()) return false;
1555 return VectorList.Count == 3 && VectorList.LaneIndex <= 1;
1558 bool isVecListThreeQHWordIndexed() const {
1559 if (!isDoubleSpacedVectorIndexed()) return false;
1560 return VectorList.Count == 3 && VectorList.LaneIndex <= 3;
1563 bool isVecListThreeDWordIndexed() const {
1564 if (!isSingleSpacedVectorIndexed()) return false;
1565 return VectorList.Count == 3 && VectorList.LaneIndex <= 1;
1568 bool isVecListFourDByteIndexed() const {
1569 if (!isSingleSpacedVectorIndexed()) return false;
1570 return VectorList.Count == 4 && VectorList.LaneIndex <= 7;
1573 bool isVecListFourDHWordIndexed() const {
1574 if (!isSingleSpacedVectorIndexed()) return false;
1575 return VectorList.Count == 4 && VectorList.LaneIndex <= 3;
1578 bool isVecListFourQWordIndexed() const {
1579 if (!isDoubleSpacedVectorIndexed()) return false;
1580 return VectorList.Count == 4 && VectorList.LaneIndex <= 1;
1583 bool isVecListFourQHWordIndexed() const {
1584 if (!isDoubleSpacedVectorIndexed()) return false;
1585 return VectorList.Count == 4 && VectorList.LaneIndex <= 3;
1588 bool isVecListFourDWordIndexed() const {
1589 if (!isSingleSpacedVectorIndexed()) return false;
1590 return VectorList.Count == 4 && VectorList.LaneIndex <= 1;
1593 bool isVectorIndex8() const {
1594 if (Kind != k_VectorIndex) return false;
1595 return VectorIndex.Val < 8;
1597 bool isVectorIndex16() const {
1598 if (Kind != k_VectorIndex) return false;
1599 return VectorIndex.Val < 4;
1601 bool isVectorIndex32() const {
1602 if (Kind != k_VectorIndex) return false;
1603 return VectorIndex.Val < 2;
1606 bool isNEONi8splat() const {
1607 if (!isImm()) return false;
1608 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1609 // Must be a constant.
1610 if (!CE) return false;
1611 int64_t Value = CE->getValue();
1612 // i8 value splatted across 8 bytes. The immediate is just the 8 byte
1614 return Value >= 0 && Value < 256;
1617 bool isNEONi16splat() const {
1618 if (isNEONByteReplicate(2))
1619 return false; // Leave that for bytes replication and forbid by default.
1622 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1623 // Must be a constant.
1624 if (!CE) return false;
1625 unsigned Value = CE->getValue();
1626 return ARM_AM::isNEONi16splat(Value);
1629 bool isNEONi16splatNot() const {
1632 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1633 // Must be a constant.
1634 if (!CE) return false;
1635 unsigned Value = CE->getValue();
1636 return ARM_AM::isNEONi16splat(~Value & 0xffff);
1639 bool isNEONi32splat() const {
1640 if (isNEONByteReplicate(4))
1641 return false; // Leave that for bytes replication and forbid by default.
1644 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1645 // Must be a constant.
1646 if (!CE) return false;
1647 unsigned Value = CE->getValue();
1648 return ARM_AM::isNEONi32splat(Value);
1651 bool isNEONi32splatNot() const {
1654 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1655 // Must be a constant.
1656 if (!CE) return false;
1657 unsigned Value = CE->getValue();
1658 return ARM_AM::isNEONi32splat(~Value);
1661 bool isNEONByteReplicate(unsigned NumBytes) const {
1664 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1665 // Must be a constant.
1668 int64_t Value = CE->getValue();
1670 return false; // Don't bother with zero.
1672 unsigned char B = Value & 0xff;
1673 for (unsigned i = 1; i < NumBytes; ++i) {
1675 if ((Value & 0xff) != B)
1680 bool isNEONi16ByteReplicate() const { return isNEONByteReplicate(2); }
1681 bool isNEONi32ByteReplicate() const { return isNEONByteReplicate(4); }
1682 bool isNEONi32vmov() const {
1683 if (isNEONByteReplicate(4))
1684 return false; // Let it to be classified as byte-replicate case.
1687 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1688 // Must be a constant.
1691 int64_t Value = CE->getValue();
1692 // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X,
1693 // for VMOV/VMVN only, 00Xf or 0Xff are also accepted.
1694 // FIXME: This is probably wrong and a copy and paste from previous example
1695 return (Value >= 0 && Value < 256) ||
1696 (Value >= 0x0100 && Value <= 0xff00) ||
1697 (Value >= 0x010000 && Value <= 0xff0000) ||
1698 (Value >= 0x01000000 && Value <= 0xff000000) ||
1699 (Value >= 0x01ff && Value <= 0xffff && (Value & 0xff) == 0xff) ||
1700 (Value >= 0x01ffff && Value <= 0xffffff && (Value & 0xffff) == 0xffff);
1702 bool isNEONi32vmovNeg() const {
1703 if (!isImm()) return false;
1704 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1705 // Must be a constant.
1706 if (!CE) return false;
1707 int64_t Value = ~CE->getValue();
1708 // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X,
1709 // for VMOV/VMVN only, 00Xf or 0Xff are also accepted.
1710 // FIXME: This is probably wrong and a copy and paste from previous example
1711 return (Value >= 0 && Value < 256) ||
1712 (Value >= 0x0100 && Value <= 0xff00) ||
1713 (Value >= 0x010000 && Value <= 0xff0000) ||
1714 (Value >= 0x01000000 && Value <= 0xff000000) ||
1715 (Value >= 0x01ff && Value <= 0xffff && (Value & 0xff) == 0xff) ||
1716 (Value >= 0x01ffff && Value <= 0xffffff && (Value & 0xffff) == 0xffff);
1719 bool isNEONi64splat() const {
1720 if (!isImm()) return false;
1721 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1722 // Must be a constant.
1723 if (!CE) return false;
1724 uint64_t Value = CE->getValue();
1725 // i64 value with each byte being either 0 or 0xff.
1726 for (unsigned i = 0; i < 8; ++i)
1727 if ((Value & 0xff) != 0 && (Value & 0xff) != 0xff) return false;
1731 void addExpr(MCInst &Inst, const MCExpr *Expr) const {
1732 // Add as immediates when possible. Null MCExpr = 0.
1734 Inst.addOperand(MCOperand::CreateImm(0));
1735 else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
1736 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
1738 Inst.addOperand(MCOperand::CreateExpr(Expr));
1741 void addCondCodeOperands(MCInst &Inst, unsigned N) const {
1742 assert(N == 2 && "Invalid number of operands!");
1743 Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
1744 unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR;
1745 Inst.addOperand(MCOperand::CreateReg(RegNum));
1748 void addCoprocNumOperands(MCInst &Inst, unsigned N) const {
1749 assert(N == 1 && "Invalid number of operands!");
1750 Inst.addOperand(MCOperand::CreateImm(getCoproc()));
1753 void addCoprocRegOperands(MCInst &Inst, unsigned N) const {
1754 assert(N == 1 && "Invalid number of operands!");
1755 Inst.addOperand(MCOperand::CreateImm(getCoproc()));
1758 void addCoprocOptionOperands(MCInst &Inst, unsigned N) const {
1759 assert(N == 1 && "Invalid number of operands!");
1760 Inst.addOperand(MCOperand::CreateImm(CoprocOption.Val));
1763 void addITMaskOperands(MCInst &Inst, unsigned N) const {
1764 assert(N == 1 && "Invalid number of operands!");
1765 Inst.addOperand(MCOperand::CreateImm(ITMask.Mask));
1768 void addITCondCodeOperands(MCInst &Inst, unsigned N) const {
1769 assert(N == 1 && "Invalid number of operands!");
1770 Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
1773 void addCCOutOperands(MCInst &Inst, unsigned N) const {
1774 assert(N == 1 && "Invalid number of operands!");
1775 Inst.addOperand(MCOperand::CreateReg(getReg()));
1778 void addRegOperands(MCInst &Inst, unsigned N) const {
1779 assert(N == 1 && "Invalid number of operands!");
1780 Inst.addOperand(MCOperand::CreateReg(getReg()));
1783 void addRegShiftedRegOperands(MCInst &Inst, unsigned N) const {
1784 assert(N == 3 && "Invalid number of operands!");
1785 assert(isRegShiftedReg() &&
1786 "addRegShiftedRegOperands() on non-RegShiftedReg!");
1787 Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.SrcReg));
1788 Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.ShiftReg));
1789 Inst.addOperand(MCOperand::CreateImm(
1790 ARM_AM::getSORegOpc(RegShiftedReg.ShiftTy, RegShiftedReg.ShiftImm)));
1793 void addRegShiftedImmOperands(MCInst &Inst, unsigned N) const {
1794 assert(N == 2 && "Invalid number of operands!");
1795 assert(isRegShiftedImm() &&
1796 "addRegShiftedImmOperands() on non-RegShiftedImm!");
1797 Inst.addOperand(MCOperand::CreateReg(RegShiftedImm.SrcReg));
1798 // Shift of #32 is encoded as 0 where permitted
1799 unsigned Imm = (RegShiftedImm.ShiftImm == 32 ? 0 : RegShiftedImm.ShiftImm);
1800 Inst.addOperand(MCOperand::CreateImm(
1801 ARM_AM::getSORegOpc(RegShiftedImm.ShiftTy, Imm)));
1804 void addShifterImmOperands(MCInst &Inst, unsigned N) const {
1805 assert(N == 1 && "Invalid number of operands!");
1806 Inst.addOperand(MCOperand::CreateImm((ShifterImm.isASR << 5) |
1810 void addRegListOperands(MCInst &Inst, unsigned N) const {
1811 assert(N == 1 && "Invalid number of operands!");
1812 const SmallVectorImpl<unsigned> &RegList = getRegList();
1813 for (SmallVectorImpl<unsigned>::const_iterator
1814 I = RegList.begin(), E = RegList.end(); I != E; ++I)
1815 Inst.addOperand(MCOperand::CreateReg(*I));
1818 void addDPRRegListOperands(MCInst &Inst, unsigned N) const {
1819 addRegListOperands(Inst, N);
1822 void addSPRRegListOperands(MCInst &Inst, unsigned N) const {
1823 addRegListOperands(Inst, N);
1826 void addRotImmOperands(MCInst &Inst, unsigned N) const {
1827 assert(N == 1 && "Invalid number of operands!");
1828 // Encoded as val>>3. The printer handles display as 8, 16, 24.
1829 Inst.addOperand(MCOperand::CreateImm(RotImm.Imm >> 3));
1832 void addBitfieldOperands(MCInst &Inst, unsigned N) const {
1833 assert(N == 1 && "Invalid number of operands!");
1834 // Munge the lsb/width into a bitfield mask.
1835 unsigned lsb = Bitfield.LSB;
1836 unsigned width = Bitfield.Width;
1837 // Make a 32-bit mask w/ the referenced bits clear and all other bits set.
1838 uint32_t Mask = ~(((uint32_t)0xffffffff >> lsb) << (32 - width) >>
1839 (32 - (lsb + width)));
1840 Inst.addOperand(MCOperand::CreateImm(Mask));
1843 void addImmOperands(MCInst &Inst, unsigned N) const {
1844 assert(N == 1 && "Invalid number of operands!");
1845 addExpr(Inst, getImm());
1848 void addFBits16Operands(MCInst &Inst, unsigned N) const {
1849 assert(N == 1 && "Invalid number of operands!");
1850 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1851 Inst.addOperand(MCOperand::CreateImm(16 - CE->getValue()));
1854 void addFBits32Operands(MCInst &Inst, unsigned N) const {
1855 assert(N == 1 && "Invalid number of operands!");
1856 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1857 Inst.addOperand(MCOperand::CreateImm(32 - CE->getValue()));
1860 void addFPImmOperands(MCInst &Inst, unsigned N) const {
1861 assert(N == 1 && "Invalid number of operands!");
1862 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1863 int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue()));
1864 Inst.addOperand(MCOperand::CreateImm(Val));
1867 void addImm8s4Operands(MCInst &Inst, unsigned N) const {
1868 assert(N == 1 && "Invalid number of operands!");
1869 // FIXME: We really want to scale the value here, but the LDRD/STRD
1870 // instruction don't encode operands that way yet.
1871 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1872 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
1875 void addImm0_1020s4Operands(MCInst &Inst, unsigned N) const {
1876 assert(N == 1 && "Invalid number of operands!");
1877 // The immediate is scaled by four in the encoding and is stored
1878 // in the MCInst as such. Lop off the low two bits here.
1879 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1880 Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4));
1883 void addImm0_508s4NegOperands(MCInst &Inst, unsigned N) const {
1884 assert(N == 1 && "Invalid number of operands!");
1885 // The immediate is scaled by four in the encoding and is stored
1886 // in the MCInst as such. Lop off the low two bits here.
1887 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1888 Inst.addOperand(MCOperand::CreateImm(-(CE->getValue() / 4)));
1891 void addImm0_508s4Operands(MCInst &Inst, unsigned N) const {
1892 assert(N == 1 && "Invalid number of operands!");
1893 // The immediate is scaled by four in the encoding and is stored
1894 // in the MCInst as such. Lop off the low two bits here.
1895 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1896 Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4));
1899 void addImm1_16Operands(MCInst &Inst, unsigned N) const {
1900 assert(N == 1 && "Invalid number of operands!");
1901 // The constant encodes as the immediate-1, and we store in the instruction
1902 // the bits as encoded, so subtract off one here.
1903 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1904 Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
1907 void addImm1_32Operands(MCInst &Inst, unsigned N) const {
1908 assert(N == 1 && "Invalid number of operands!");
1909 // The constant encodes as the immediate-1, and we store in the instruction
1910 // the bits as encoded, so subtract off one here.
1911 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1912 Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
1915 void addImmThumbSROperands(MCInst &Inst, unsigned N) const {
1916 assert(N == 1 && "Invalid number of operands!");
1917 // The constant encodes as the immediate, except for 32, which encodes as
1919 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1920 unsigned Imm = CE->getValue();
1921 Inst.addOperand(MCOperand::CreateImm((Imm == 32 ? 0 : Imm)));
1924 void addPKHASRImmOperands(MCInst &Inst, unsigned N) const {
1925 assert(N == 1 && "Invalid number of operands!");
1926 // An ASR value of 32 encodes as 0, so that's how we want to add it to
1927 // the instruction as well.
1928 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1929 int Val = CE->getValue();
1930 Inst.addOperand(MCOperand::CreateImm(Val == 32 ? 0 : Val));
1933 void addT2SOImmNotOperands(MCInst &Inst, unsigned N) const {
1934 assert(N == 1 && "Invalid number of operands!");
1935 // The operand is actually a t2_so_imm, but we have its bitwise
1936 // negation in the assembly source, so twiddle it here.
1937 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1938 Inst.addOperand(MCOperand::CreateImm(~CE->getValue()));
1941 void addT2SOImmNegOperands(MCInst &Inst, unsigned N) const {
1942 assert(N == 1 && "Invalid number of operands!");
1943 // The operand is actually a t2_so_imm, but we have its
1944 // negation in the assembly source, so twiddle it here.
1945 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1946 Inst.addOperand(MCOperand::CreateImm(-CE->getValue()));
1949 void addImm0_4095NegOperands(MCInst &Inst, unsigned N) const {
1950 assert(N == 1 && "Invalid number of operands!");
1951 // The operand is actually an imm0_4095, but we have its
1952 // negation in the assembly source, so twiddle it here.
1953 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1954 Inst.addOperand(MCOperand::CreateImm(-CE->getValue()));
1957 void addUnsignedOffset_b8s2Operands(MCInst &Inst, unsigned N) const {
1958 if(const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm())) {
1959 Inst.addOperand(MCOperand::CreateImm(CE->getValue() >> 2));
1963 const MCSymbolRefExpr *SR = dyn_cast<MCSymbolRefExpr>(Imm.Val);
1964 assert(SR && "Unknown value type!");
1965 Inst.addOperand(MCOperand::CreateExpr(SR));
1968 void addThumbMemPCOperands(MCInst &Inst, unsigned N) const {
1969 assert(N == 1 && "Invalid number of operands!");
1971 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1973 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
1977 const MCSymbolRefExpr *SR = dyn_cast<MCSymbolRefExpr>(Imm.Val);
1978 assert(SR && "Unknown value type!");
1979 Inst.addOperand(MCOperand::CreateExpr(SR));
1983 assert(isMem() && "Unknown value type!");
1984 assert(isa<MCConstantExpr>(Memory.OffsetImm) && "Unknown value type!");
1985 Inst.addOperand(MCOperand::CreateImm(Memory.OffsetImm->getValue()));
1988 void addARMSOImmNotOperands(MCInst &Inst, unsigned N) const {
1989 assert(N == 1 && "Invalid number of operands!");
1990 // The operand is actually a so_imm, but we have its bitwise
1991 // negation in the assembly source, so twiddle it here.
1992 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1993 Inst.addOperand(MCOperand::CreateImm(~CE->getValue()));
1996 void addARMSOImmNegOperands(MCInst &Inst, unsigned N) const {
1997 assert(N == 1 && "Invalid number of operands!");
1998 // The operand is actually a so_imm, but we have its
1999 // negation in the assembly source, so twiddle it here.
2000 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2001 Inst.addOperand(MCOperand::CreateImm(-CE->getValue()));
2004 void addMemBarrierOptOperands(MCInst &Inst, unsigned N) const {
2005 assert(N == 1 && "Invalid number of operands!");
2006 Inst.addOperand(MCOperand::CreateImm(unsigned(getMemBarrierOpt())));
2009 void addInstSyncBarrierOptOperands(MCInst &Inst, unsigned N) const {
2010 assert(N == 1 && "Invalid number of operands!");
2011 Inst.addOperand(MCOperand::CreateImm(unsigned(getInstSyncBarrierOpt())));
2014 void addMemNoOffsetOperands(MCInst &Inst, unsigned N) const {
2015 assert(N == 1 && "Invalid number of operands!");
2016 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2019 void addMemPCRelImm12Operands(MCInst &Inst, unsigned N) const {
2020 assert(N == 1 && "Invalid number of operands!");
2021 int32_t Imm = Memory.OffsetImm->getValue();
2022 Inst.addOperand(MCOperand::CreateImm(Imm));
2025 void addAdrLabelOperands(MCInst &Inst, unsigned N) const {
2026 assert(N == 1 && "Invalid number of operands!");
2027 assert(isImm() && "Not an immediate!");
2029 // If we have an immediate that's not a constant, treat it as a label
2030 // reference needing a fixup.
2031 if (!isa<MCConstantExpr>(getImm())) {
2032 Inst.addOperand(MCOperand::CreateExpr(getImm()));
2036 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2037 int Val = CE->getValue();
2038 Inst.addOperand(MCOperand::CreateImm(Val));
2041 void addAlignedMemoryOperands(MCInst &Inst, unsigned N) const {
2042 assert(N == 2 && "Invalid number of operands!");
2043 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2044 Inst.addOperand(MCOperand::CreateImm(Memory.Alignment));
2047 void addDupAlignedMemoryNoneOperands(MCInst &Inst, unsigned N) const {
2048 addAlignedMemoryOperands(Inst, N);
2051 void addAlignedMemoryNoneOperands(MCInst &Inst, unsigned N) const {
2052 addAlignedMemoryOperands(Inst, N);
2055 void addAlignedMemory16Operands(MCInst &Inst, unsigned N) const {
2056 addAlignedMemoryOperands(Inst, N);
2059 void addDupAlignedMemory16Operands(MCInst &Inst, unsigned N) const {
2060 addAlignedMemoryOperands(Inst, N);
2063 void addAlignedMemory32Operands(MCInst &Inst, unsigned N) const {
2064 addAlignedMemoryOperands(Inst, N);
2067 void addDupAlignedMemory32Operands(MCInst &Inst, unsigned N) const {
2068 addAlignedMemoryOperands(Inst, N);
2071 void addAlignedMemory64Operands(MCInst &Inst, unsigned N) const {
2072 addAlignedMemoryOperands(Inst, N);
2075 void addDupAlignedMemory64Operands(MCInst &Inst, unsigned N) const {
2076 addAlignedMemoryOperands(Inst, N);
2079 void addAlignedMemory64or128Operands(MCInst &Inst, unsigned N) const {
2080 addAlignedMemoryOperands(Inst, N);
2083 void addDupAlignedMemory64or128Operands(MCInst &Inst, unsigned N) const {
2084 addAlignedMemoryOperands(Inst, N);
2087 void addAlignedMemory64or128or256Operands(MCInst &Inst, unsigned N) const {
2088 addAlignedMemoryOperands(Inst, N);
2091 void addAddrMode2Operands(MCInst &Inst, unsigned N) const {
2092 assert(N == 3 && "Invalid number of operands!");
2093 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2094 if (!Memory.OffsetRegNum) {
2095 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
2096 // Special case for #-0
2097 if (Val == INT32_MIN) Val = 0;
2098 if (Val < 0) Val = -Val;
2099 Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
2101 // For register offset, we encode the shift type and negation flag
2103 Val = ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add,
2104 Memory.ShiftImm, Memory.ShiftType);
2106 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2107 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
2108 Inst.addOperand(MCOperand::CreateImm(Val));
2111 void addAM2OffsetImmOperands(MCInst &Inst, unsigned N) const {
2112 assert(N == 2 && "Invalid number of operands!");
2113 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2114 assert(CE && "non-constant AM2OffsetImm operand!");
2115 int32_t Val = CE->getValue();
2116 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
2117 // Special case for #-0
2118 if (Val == INT32_MIN) Val = 0;
2119 if (Val < 0) Val = -Val;
2120 Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
2121 Inst.addOperand(MCOperand::CreateReg(0));
2122 Inst.addOperand(MCOperand::CreateImm(Val));
2125 void addAddrMode3Operands(MCInst &Inst, unsigned N) const {
2126 assert(N == 3 && "Invalid number of operands!");
2127 // If we have an immediate that's not a constant, treat it as a label
2128 // reference needing a fixup. If it is a constant, it's something else
2129 // and we reject it.
2131 Inst.addOperand(MCOperand::CreateExpr(getImm()));
2132 Inst.addOperand(MCOperand::CreateReg(0));
2133 Inst.addOperand(MCOperand::CreateImm(0));
2137 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2138 if (!Memory.OffsetRegNum) {
2139 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
2140 // Special case for #-0
2141 if (Val == INT32_MIN) Val = 0;
2142 if (Val < 0) Val = -Val;
2143 Val = ARM_AM::getAM3Opc(AddSub, Val);
2145 // For register offset, we encode the shift type and negation flag
2147 Val = ARM_AM::getAM3Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add, 0);
2149 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2150 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
2151 Inst.addOperand(MCOperand::CreateImm(Val));
2154 void addAM3OffsetOperands(MCInst &Inst, unsigned N) const {
2155 assert(N == 2 && "Invalid number of operands!");
2156 if (Kind == k_PostIndexRegister) {
2158 ARM_AM::getAM3Opc(PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub, 0);
2159 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
2160 Inst.addOperand(MCOperand::CreateImm(Val));
2165 const MCConstantExpr *CE = static_cast<const MCConstantExpr*>(getImm());
2166 int32_t Val = CE->getValue();
2167 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
2168 // Special case for #-0
2169 if (Val == INT32_MIN) Val = 0;
2170 if (Val < 0) Val = -Val;
2171 Val = ARM_AM::getAM3Opc(AddSub, Val);
2172 Inst.addOperand(MCOperand::CreateReg(0));
2173 Inst.addOperand(MCOperand::CreateImm(Val));
2176 void addAddrMode5Operands(MCInst &Inst, unsigned N) const {
2177 assert(N == 2 && "Invalid number of operands!");
2178 // If we have an immediate that's not a constant, treat it as a label
2179 // reference needing a fixup. If it is a constant, it's something else
2180 // and we reject it.
2182 Inst.addOperand(MCOperand::CreateExpr(getImm()));
2183 Inst.addOperand(MCOperand::CreateImm(0));
2187 // The lower two bits are always zero and as such are not encoded.
2188 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0;
2189 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
2190 // Special case for #-0
2191 if (Val == INT32_MIN) Val = 0;
2192 if (Val < 0) Val = -Val;
2193 Val = ARM_AM::getAM5Opc(AddSub, Val);
2194 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2195 Inst.addOperand(MCOperand::CreateImm(Val));
2198 void addMemImm8s4OffsetOperands(MCInst &Inst, unsigned N) const {
2199 assert(N == 2 && "Invalid number of operands!");
2200 // If we have an immediate that's not a constant, treat it as a label
2201 // reference needing a fixup. If it is a constant, it's something else
2202 // and we reject it.
2204 Inst.addOperand(MCOperand::CreateExpr(getImm()));
2205 Inst.addOperand(MCOperand::CreateImm(0));
2209 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2210 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2211 Inst.addOperand(MCOperand::CreateImm(Val));
2214 void addMemImm0_1020s4OffsetOperands(MCInst &Inst, unsigned N) const {
2215 assert(N == 2 && "Invalid number of operands!");
2216 // The lower two bits are always zero and as such are not encoded.
2217 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0;
2218 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2219 Inst.addOperand(MCOperand::CreateImm(Val));
2222 void addMemImm8OffsetOperands(MCInst &Inst, unsigned N) const {
2223 assert(N == 2 && "Invalid number of operands!");
2224 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2225 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2226 Inst.addOperand(MCOperand::CreateImm(Val));
2229 void addMemPosImm8OffsetOperands(MCInst &Inst, unsigned N) const {
2230 addMemImm8OffsetOperands(Inst, N);
2233 void addMemNegImm8OffsetOperands(MCInst &Inst, unsigned N) const {
2234 addMemImm8OffsetOperands(Inst, N);
2237 void addMemUImm12OffsetOperands(MCInst &Inst, unsigned N) const {
2238 assert(N == 2 && "Invalid number of operands!");
2239 // If this is an immediate, it's a label reference.
2241 addExpr(Inst, getImm());
2242 Inst.addOperand(MCOperand::CreateImm(0));
2246 // Otherwise, it's a normal memory reg+offset.
2247 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2248 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2249 Inst.addOperand(MCOperand::CreateImm(Val));
2252 void addMemImm12OffsetOperands(MCInst &Inst, unsigned N) const {
2253 assert(N == 2 && "Invalid number of operands!");
2254 // If this is an immediate, it's a label reference.
2256 addExpr(Inst, getImm());
2257 Inst.addOperand(MCOperand::CreateImm(0));
2261 // Otherwise, it's a normal memory reg+offset.
2262 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2263 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2264 Inst.addOperand(MCOperand::CreateImm(Val));
2267 void addMemTBBOperands(MCInst &Inst, unsigned N) const {
2268 assert(N == 2 && "Invalid number of operands!");
2269 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2270 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
2273 void addMemTBHOperands(MCInst &Inst, unsigned N) const {
2274 assert(N == 2 && "Invalid number of operands!");
2275 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2276 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
2279 void addMemRegOffsetOperands(MCInst &Inst, unsigned N) const {
2280 assert(N == 3 && "Invalid number of operands!");
2282 ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add,
2283 Memory.ShiftImm, Memory.ShiftType);
2284 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2285 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
2286 Inst.addOperand(MCOperand::CreateImm(Val));
2289 void addT2MemRegOffsetOperands(MCInst &Inst, unsigned N) const {
2290 assert(N == 3 && "Invalid number of operands!");
2291 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2292 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
2293 Inst.addOperand(MCOperand::CreateImm(Memory.ShiftImm));
2296 void addMemThumbRROperands(MCInst &Inst, unsigned N) const {
2297 assert(N == 2 && "Invalid number of operands!");
2298 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2299 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
2302 void addMemThumbRIs4Operands(MCInst &Inst, unsigned N) const {
2303 assert(N == 2 && "Invalid number of operands!");
2304 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0;
2305 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2306 Inst.addOperand(MCOperand::CreateImm(Val));
2309 void addMemThumbRIs2Operands(MCInst &Inst, unsigned N) const {
2310 assert(N == 2 && "Invalid number of operands!");
2311 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 2) : 0;
2312 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2313 Inst.addOperand(MCOperand::CreateImm(Val));
2316 void addMemThumbRIs1Operands(MCInst &Inst, unsigned N) const {
2317 assert(N == 2 && "Invalid number of operands!");
2318 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue()) : 0;
2319 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2320 Inst.addOperand(MCOperand::CreateImm(Val));
2323 void addMemThumbSPIOperands(MCInst &Inst, unsigned N) const {
2324 assert(N == 2 && "Invalid number of operands!");
2325 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0;
2326 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2327 Inst.addOperand(MCOperand::CreateImm(Val));
2330 void addPostIdxImm8Operands(MCInst &Inst, unsigned N) const {
2331 assert(N == 1 && "Invalid number of operands!");
2332 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2333 assert(CE && "non-constant post-idx-imm8 operand!");
2334 int Imm = CE->getValue();
2335 bool isAdd = Imm >= 0;
2336 if (Imm == INT32_MIN) Imm = 0;
2337 Imm = (Imm < 0 ? -Imm : Imm) | (int)isAdd << 8;
2338 Inst.addOperand(MCOperand::CreateImm(Imm));
2341 void addPostIdxImm8s4Operands(MCInst &Inst, unsigned N) const {
2342 assert(N == 1 && "Invalid number of operands!");
2343 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2344 assert(CE && "non-constant post-idx-imm8s4 operand!");
2345 int Imm = CE->getValue();
2346 bool isAdd = Imm >= 0;
2347 if (Imm == INT32_MIN) Imm = 0;
2348 // Immediate is scaled by 4.
2349 Imm = ((Imm < 0 ? -Imm : Imm) / 4) | (int)isAdd << 8;
2350 Inst.addOperand(MCOperand::CreateImm(Imm));
2353 void addPostIdxRegOperands(MCInst &Inst, unsigned N) const {
2354 assert(N == 2 && "Invalid number of operands!");
2355 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
2356 Inst.addOperand(MCOperand::CreateImm(PostIdxReg.isAdd));
2359 void addPostIdxRegShiftedOperands(MCInst &Inst, unsigned N) const {
2360 assert(N == 2 && "Invalid number of operands!");
2361 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
2362 // The sign, shift type, and shift amount are encoded in a single operand
2363 // using the AM2 encoding helpers.
2364 ARM_AM::AddrOpc opc = PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub;
2365 unsigned Imm = ARM_AM::getAM2Opc(opc, PostIdxReg.ShiftImm,
2366 PostIdxReg.ShiftTy);
2367 Inst.addOperand(MCOperand::CreateImm(Imm));
2370 void addMSRMaskOperands(MCInst &Inst, unsigned N) const {
2371 assert(N == 1 && "Invalid number of operands!");
2372 Inst.addOperand(MCOperand::CreateImm(unsigned(getMSRMask())));
2375 void addBankedRegOperands(MCInst &Inst, unsigned N) const {
2376 assert(N == 1 && "Invalid number of operands!");
2377 Inst.addOperand(MCOperand::CreateImm(unsigned(getBankedReg())));
2380 void addProcIFlagsOperands(MCInst &Inst, unsigned N) const {
2381 assert(N == 1 && "Invalid number of operands!");
2382 Inst.addOperand(MCOperand::CreateImm(unsigned(getProcIFlags())));
2385 void addVecListOperands(MCInst &Inst, unsigned N) const {
2386 assert(N == 1 && "Invalid number of operands!");
2387 Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum));
2390 void addVecListIndexedOperands(MCInst &Inst, unsigned N) const {
2391 assert(N == 2 && "Invalid number of operands!");
2392 Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum));
2393 Inst.addOperand(MCOperand::CreateImm(VectorList.LaneIndex));
2396 void addVectorIndex8Operands(MCInst &Inst, unsigned N) const {
2397 assert(N == 1 && "Invalid number of operands!");
2398 Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
2401 void addVectorIndex16Operands(MCInst &Inst, unsigned N) const {
2402 assert(N == 1 && "Invalid number of operands!");
2403 Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
2406 void addVectorIndex32Operands(MCInst &Inst, unsigned N) const {
2407 assert(N == 1 && "Invalid number of operands!");
2408 Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
2411 void addNEONi8splatOperands(MCInst &Inst, unsigned N) const {
2412 assert(N == 1 && "Invalid number of operands!");
2413 // The immediate encodes the type of constant as well as the value.
2414 // Mask in that this is an i8 splat.
2415 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2416 Inst.addOperand(MCOperand::CreateImm(CE->getValue() | 0xe00));
2419 void addNEONi16splatOperands(MCInst &Inst, unsigned N) const {
2420 assert(N == 1 && "Invalid number of operands!");
2421 // The immediate encodes the type of constant as well as the value.
2422 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2423 unsigned Value = CE->getValue();
2424 Value = ARM_AM::encodeNEONi16splat(Value);
2425 Inst.addOperand(MCOperand::CreateImm(Value));
2428 void addNEONi16splatNotOperands(MCInst &Inst, unsigned N) const {
2429 assert(N == 1 && "Invalid number of operands!");
2430 // The immediate encodes the type of constant as well as the value.
2431 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2432 unsigned Value = CE->getValue();
2433 Value = ARM_AM::encodeNEONi16splat(~Value & 0xffff);
2434 Inst.addOperand(MCOperand::CreateImm(Value));
2437 void addNEONi32splatOperands(MCInst &Inst, unsigned N) const {
2438 assert(N == 1 && "Invalid number of operands!");
2439 // The immediate encodes the type of constant as well as the value.
2440 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2441 unsigned Value = CE->getValue();
2442 Value = ARM_AM::encodeNEONi32splat(Value);
2443 Inst.addOperand(MCOperand::CreateImm(Value));
2446 void addNEONi32splatNotOperands(MCInst &Inst, unsigned N) const {
2447 assert(N == 1 && "Invalid number of operands!");
2448 // The immediate encodes the type of constant as well as the value.
2449 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2450 unsigned Value = CE->getValue();
2451 Value = ARM_AM::encodeNEONi32splat(~Value);
2452 Inst.addOperand(MCOperand::CreateImm(Value));
2455 void addNEONinvByteReplicateOperands(MCInst &Inst, unsigned N) const {
2456 assert(N == 1 && "Invalid number of operands!");
2457 // The immediate encodes the type of constant as well as the value.
2458 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2459 unsigned Value = CE->getValue();
2460 assert((Inst.getOpcode() == ARM::VMOVv8i8 ||
2461 Inst.getOpcode() == ARM::VMOVv16i8) &&
2462 "All vmvn instructions that wants to replicate non-zero byte "
2463 "always must be replaced with VMOVv8i8 or VMOVv16i8.");
2464 unsigned B = ((~Value) & 0xff);
2465 B |= 0xe00; // cmode = 0b1110
2466 Inst.addOperand(MCOperand::CreateImm(B));
2468 void addNEONi32vmovOperands(MCInst &Inst, unsigned N) const {
2469 assert(N == 1 && "Invalid number of operands!");
2470 // The immediate encodes the type of constant as well as the value.
2471 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2472 unsigned Value = CE->getValue();
2473 if (Value >= 256 && Value <= 0xffff)
2474 Value = (Value >> 8) | ((Value & 0xff) ? 0xc00 : 0x200);
2475 else if (Value > 0xffff && Value <= 0xffffff)
2476 Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400);
2477 else if (Value > 0xffffff)
2478 Value = (Value >> 24) | 0x600;
2479 Inst.addOperand(MCOperand::CreateImm(Value));
2482 void addNEONvmovByteReplicateOperands(MCInst &Inst, unsigned N) const {
2483 assert(N == 1 && "Invalid number of operands!");
2484 // The immediate encodes the type of constant as well as the value.
2485 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2486 unsigned Value = CE->getValue();
2487 assert((Inst.getOpcode() == ARM::VMOVv8i8 ||
2488 Inst.getOpcode() == ARM::VMOVv16i8) &&
2489 "All instructions that wants to replicate non-zero byte "
2490 "always must be replaced with VMOVv8i8 or VMOVv16i8.");
2491 unsigned B = Value & 0xff;
2492 B |= 0xe00; // cmode = 0b1110
2493 Inst.addOperand(MCOperand::CreateImm(B));
2495 void addNEONi32vmovNegOperands(MCInst &Inst, unsigned N) const {
2496 assert(N == 1 && "Invalid number of operands!");
2497 // The immediate encodes the type of constant as well as the value.
2498 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2499 unsigned Value = ~CE->getValue();
2500 if (Value >= 256 && Value <= 0xffff)
2501 Value = (Value >> 8) | ((Value & 0xff) ? 0xc00 : 0x200);
2502 else if (Value > 0xffff && Value <= 0xffffff)
2503 Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400);
2504 else if (Value > 0xffffff)
2505 Value = (Value >> 24) | 0x600;
2506 Inst.addOperand(MCOperand::CreateImm(Value));
2509 void addNEONi64splatOperands(MCInst &Inst, unsigned N) const {
2510 assert(N == 1 && "Invalid number of operands!");
2511 // The immediate encodes the type of constant as well as the value.
2512 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2513 uint64_t Value = CE->getValue();
2515 for (unsigned i = 0; i < 8; ++i, Value >>= 8) {
2516 Imm |= (Value & 1) << i;
2518 Inst.addOperand(MCOperand::CreateImm(Imm | 0x1e00));
2521 void print(raw_ostream &OS) const override;
2523 static std::unique_ptr<ARMOperand> CreateITMask(unsigned Mask, SMLoc S) {
2524 auto Op = make_unique<ARMOperand>(k_ITCondMask);
2525 Op->ITMask.Mask = Mask;
2531 static std::unique_ptr<ARMOperand> CreateCondCode(ARMCC::CondCodes CC,
2533 auto Op = make_unique<ARMOperand>(k_CondCode);
2540 static std::unique_ptr<ARMOperand> CreateCoprocNum(unsigned CopVal, SMLoc S) {
2541 auto Op = make_unique<ARMOperand>(k_CoprocNum);
2542 Op->Cop.Val = CopVal;
2548 static std::unique_ptr<ARMOperand> CreateCoprocReg(unsigned CopVal, SMLoc S) {
2549 auto Op = make_unique<ARMOperand>(k_CoprocReg);
2550 Op->Cop.Val = CopVal;
2556 static std::unique_ptr<ARMOperand> CreateCoprocOption(unsigned Val, SMLoc S,
2558 auto Op = make_unique<ARMOperand>(k_CoprocOption);
2565 static std::unique_ptr<ARMOperand> CreateCCOut(unsigned RegNum, SMLoc S) {
2566 auto Op = make_unique<ARMOperand>(k_CCOut);
2567 Op->Reg.RegNum = RegNum;
2573 static std::unique_ptr<ARMOperand> CreateToken(StringRef Str, SMLoc S) {
2574 auto Op = make_unique<ARMOperand>(k_Token);
2575 Op->Tok.Data = Str.data();
2576 Op->Tok.Length = Str.size();
2582 static std::unique_ptr<ARMOperand> CreateReg(unsigned RegNum, SMLoc S,
2584 auto Op = make_unique<ARMOperand>(k_Register);
2585 Op->Reg.RegNum = RegNum;
2591 static std::unique_ptr<ARMOperand>
2592 CreateShiftedRegister(ARM_AM::ShiftOpc ShTy, unsigned SrcReg,
2593 unsigned ShiftReg, unsigned ShiftImm, SMLoc S,
2595 auto Op = make_unique<ARMOperand>(k_ShiftedRegister);
2596 Op->RegShiftedReg.ShiftTy = ShTy;
2597 Op->RegShiftedReg.SrcReg = SrcReg;
2598 Op->RegShiftedReg.ShiftReg = ShiftReg;
2599 Op->RegShiftedReg.ShiftImm = ShiftImm;
2605 static std::unique_ptr<ARMOperand>
2606 CreateShiftedImmediate(ARM_AM::ShiftOpc ShTy, unsigned SrcReg,
2607 unsigned ShiftImm, SMLoc S, SMLoc E) {
2608 auto Op = make_unique<ARMOperand>(k_ShiftedImmediate);
2609 Op->RegShiftedImm.ShiftTy = ShTy;
2610 Op->RegShiftedImm.SrcReg = SrcReg;
2611 Op->RegShiftedImm.ShiftImm = ShiftImm;
2617 static std::unique_ptr<ARMOperand> CreateShifterImm(bool isASR, unsigned Imm,
2619 auto Op = make_unique<ARMOperand>(k_ShifterImmediate);
2620 Op->ShifterImm.isASR = isASR;
2621 Op->ShifterImm.Imm = Imm;
2627 static std::unique_ptr<ARMOperand> CreateRotImm(unsigned Imm, SMLoc S,
2629 auto Op = make_unique<ARMOperand>(k_RotateImmediate);
2630 Op->RotImm.Imm = Imm;
2636 static std::unique_ptr<ARMOperand>
2637 CreateBitfield(unsigned LSB, unsigned Width, SMLoc S, SMLoc E) {
2638 auto Op = make_unique<ARMOperand>(k_BitfieldDescriptor);
2639 Op->Bitfield.LSB = LSB;
2640 Op->Bitfield.Width = Width;
2646 static std::unique_ptr<ARMOperand>
2647 CreateRegList(SmallVectorImpl<std::pair<unsigned, unsigned>> &Regs,
2648 SMLoc StartLoc, SMLoc EndLoc) {
2649 assert (Regs.size() > 0 && "RegList contains no registers?");
2650 KindTy Kind = k_RegisterList;
2652 if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Regs.front().second))
2653 Kind = k_DPRRegisterList;
2654 else if (ARMMCRegisterClasses[ARM::SPRRegClassID].
2655 contains(Regs.front().second))
2656 Kind = k_SPRRegisterList;
2658 // Sort based on the register encoding values.
2659 array_pod_sort(Regs.begin(), Regs.end());
2661 auto Op = make_unique<ARMOperand>(Kind);
2662 for (SmallVectorImpl<std::pair<unsigned, unsigned> >::const_iterator
2663 I = Regs.begin(), E = Regs.end(); I != E; ++I)
2664 Op->Registers.push_back(I->second);
2665 Op->StartLoc = StartLoc;
2666 Op->EndLoc = EndLoc;
2670 static std::unique_ptr<ARMOperand> CreateVectorList(unsigned RegNum,
2672 bool isDoubleSpaced,
2674 auto Op = make_unique<ARMOperand>(k_VectorList);
2675 Op->VectorList.RegNum = RegNum;
2676 Op->VectorList.Count = Count;
2677 Op->VectorList.isDoubleSpaced = isDoubleSpaced;
2683 static std::unique_ptr<ARMOperand>
2684 CreateVectorListAllLanes(unsigned RegNum, unsigned Count, bool isDoubleSpaced,
2686 auto Op = make_unique<ARMOperand>(k_VectorListAllLanes);
2687 Op->VectorList.RegNum = RegNum;
2688 Op->VectorList.Count = Count;
2689 Op->VectorList.isDoubleSpaced = isDoubleSpaced;
2695 static std::unique_ptr<ARMOperand>
2696 CreateVectorListIndexed(unsigned RegNum, unsigned Count, unsigned Index,
2697 bool isDoubleSpaced, SMLoc S, SMLoc E) {
2698 auto Op = make_unique<ARMOperand>(k_VectorListIndexed);
2699 Op->VectorList.RegNum = RegNum;
2700 Op->VectorList.Count = Count;
2701 Op->VectorList.LaneIndex = Index;
2702 Op->VectorList.isDoubleSpaced = isDoubleSpaced;
2708 static std::unique_ptr<ARMOperand>
2709 CreateVectorIndex(unsigned Idx, SMLoc S, SMLoc E, MCContext &Ctx) {
2710 auto Op = make_unique<ARMOperand>(k_VectorIndex);
2711 Op->VectorIndex.Val = Idx;
2717 static std::unique_ptr<ARMOperand> CreateImm(const MCExpr *Val, SMLoc S,
2719 auto Op = make_unique<ARMOperand>(k_Immediate);
2726 static std::unique_ptr<ARMOperand>
2727 CreateMem(unsigned BaseRegNum, const MCConstantExpr *OffsetImm,
2728 unsigned OffsetRegNum, ARM_AM::ShiftOpc ShiftType,
2729 unsigned ShiftImm, unsigned Alignment, bool isNegative, SMLoc S,
2730 SMLoc E, SMLoc AlignmentLoc = SMLoc()) {
2731 auto Op = make_unique<ARMOperand>(k_Memory);
2732 Op->Memory.BaseRegNum = BaseRegNum;
2733 Op->Memory.OffsetImm = OffsetImm;
2734 Op->Memory.OffsetRegNum = OffsetRegNum;
2735 Op->Memory.ShiftType = ShiftType;
2736 Op->Memory.ShiftImm = ShiftImm;
2737 Op->Memory.Alignment = Alignment;
2738 Op->Memory.isNegative = isNegative;
2741 Op->AlignmentLoc = AlignmentLoc;
2745 static std::unique_ptr<ARMOperand>
2746 CreatePostIdxReg(unsigned RegNum, bool isAdd, ARM_AM::ShiftOpc ShiftTy,
2747 unsigned ShiftImm, SMLoc S, SMLoc E) {
2748 auto Op = make_unique<ARMOperand>(k_PostIndexRegister);
2749 Op->PostIdxReg.RegNum = RegNum;
2750 Op->PostIdxReg.isAdd = isAdd;
2751 Op->PostIdxReg.ShiftTy = ShiftTy;
2752 Op->PostIdxReg.ShiftImm = ShiftImm;
2758 static std::unique_ptr<ARMOperand> CreateMemBarrierOpt(ARM_MB::MemBOpt Opt,
2760 auto Op = make_unique<ARMOperand>(k_MemBarrierOpt);
2761 Op->MBOpt.Val = Opt;
2767 static std::unique_ptr<ARMOperand>
2768 CreateInstSyncBarrierOpt(ARM_ISB::InstSyncBOpt Opt, SMLoc S) {
2769 auto Op = make_unique<ARMOperand>(k_InstSyncBarrierOpt);
2770 Op->ISBOpt.Val = Opt;
2776 static std::unique_ptr<ARMOperand> CreateProcIFlags(ARM_PROC::IFlags IFlags,
2778 auto Op = make_unique<ARMOperand>(k_ProcIFlags);
2779 Op->IFlags.Val = IFlags;
2785 static std::unique_ptr<ARMOperand> CreateMSRMask(unsigned MMask, SMLoc S) {
2786 auto Op = make_unique<ARMOperand>(k_MSRMask);
2787 Op->MMask.Val = MMask;
2793 static std::unique_ptr<ARMOperand> CreateBankedReg(unsigned Reg, SMLoc S) {
2794 auto Op = make_unique<ARMOperand>(k_BankedReg);
2795 Op->BankedReg.Val = Reg;
2802 } // end anonymous namespace.
2804 void ARMOperand::print(raw_ostream &OS) const {
2807 OS << "<ARMCC::" << ARMCondCodeToString(getCondCode()) << ">";
2810 OS << "<ccout " << getReg() << ">";
2812 case k_ITCondMask: {
2813 static const char *const MaskStr[] = {
2814 "()", "(t)", "(e)", "(tt)", "(et)", "(te)", "(ee)", "(ttt)", "(ett)",
2815 "(tet)", "(eet)", "(tte)", "(ete)", "(tee)", "(eee)"
2817 assert((ITMask.Mask & 0xf) == ITMask.Mask);
2818 OS << "<it-mask " << MaskStr[ITMask.Mask] << ">";
2822 OS << "<coprocessor number: " << getCoproc() << ">";
2825 OS << "<coprocessor register: " << getCoproc() << ">";
2827 case k_CoprocOption:
2828 OS << "<coprocessor option: " << CoprocOption.Val << ">";
2831 OS << "<mask: " << getMSRMask() << ">";
2834 OS << "<banked reg: " << getBankedReg() << ">";
2837 getImm()->print(OS);
2839 case k_MemBarrierOpt:
2840 OS << "<ARM_MB::" << MemBOptToString(getMemBarrierOpt(), false) << ">";
2842 case k_InstSyncBarrierOpt:
2843 OS << "<ARM_ISB::" << InstSyncBOptToString(getInstSyncBarrierOpt()) << ">";
2847 << " base:" << Memory.BaseRegNum;
2850 case k_PostIndexRegister:
2851 OS << "post-idx register " << (PostIdxReg.isAdd ? "" : "-")
2852 << PostIdxReg.RegNum;
2853 if (PostIdxReg.ShiftTy != ARM_AM::no_shift)
2854 OS << ARM_AM::getShiftOpcStr(PostIdxReg.ShiftTy) << " "
2855 << PostIdxReg.ShiftImm;
2858 case k_ProcIFlags: {
2859 OS << "<ARM_PROC::";
2860 unsigned IFlags = getProcIFlags();
2861 for (int i=2; i >= 0; --i)
2862 if (IFlags & (1 << i))
2863 OS << ARM_PROC::IFlagsToString(1 << i);
2868 OS << "<register " << getReg() << ">";
2870 case k_ShifterImmediate:
2871 OS << "<shift " << (ShifterImm.isASR ? "asr" : "lsl")
2872 << " #" << ShifterImm.Imm << ">";
2874 case k_ShiftedRegister:
2875 OS << "<so_reg_reg "
2876 << RegShiftedReg.SrcReg << " "
2877 << ARM_AM::getShiftOpcStr(RegShiftedReg.ShiftTy)
2878 << " " << RegShiftedReg.ShiftReg << ">";
2880 case k_ShiftedImmediate:
2881 OS << "<so_reg_imm "
2882 << RegShiftedImm.SrcReg << " "
2883 << ARM_AM::getShiftOpcStr(RegShiftedImm.ShiftTy)
2884 << " #" << RegShiftedImm.ShiftImm << ">";
2886 case k_RotateImmediate:
2887 OS << "<ror " << " #" << (RotImm.Imm * 8) << ">";
2889 case k_BitfieldDescriptor:
2890 OS << "<bitfield " << "lsb: " << Bitfield.LSB
2891 << ", width: " << Bitfield.Width << ">";
2893 case k_RegisterList:
2894 case k_DPRRegisterList:
2895 case k_SPRRegisterList: {
2896 OS << "<register_list ";
2898 const SmallVectorImpl<unsigned> &RegList = getRegList();
2899 for (SmallVectorImpl<unsigned>::const_iterator
2900 I = RegList.begin(), E = RegList.end(); I != E; ) {
2902 if (++I < E) OS << ", ";
2909 OS << "<vector_list " << VectorList.Count << " * "
2910 << VectorList.RegNum << ">";
2912 case k_VectorListAllLanes:
2913 OS << "<vector_list(all lanes) " << VectorList.Count << " * "
2914 << VectorList.RegNum << ">";
2916 case k_VectorListIndexed:
2917 OS << "<vector_list(lane " << VectorList.LaneIndex << ") "
2918 << VectorList.Count << " * " << VectorList.RegNum << ">";
2921 OS << "'" << getToken() << "'";
2924 OS << "<vectorindex " << getVectorIndex() << ">";
2929 /// @name Auto-generated Match Functions
2932 static unsigned MatchRegisterName(StringRef Name);
2936 bool ARMAsmParser::ParseRegister(unsigned &RegNo,
2937 SMLoc &StartLoc, SMLoc &EndLoc) {
2938 StartLoc = Parser.getTok().getLoc();
2939 EndLoc = Parser.getTok().getEndLoc();
2940 RegNo = tryParseRegister();
2942 return (RegNo == (unsigned)-1);
2945 /// Try to parse a register name. The token must be an Identifier when called,
2946 /// and if it is a register name the token is eaten and the register number is
2947 /// returned. Otherwise return -1.
2949 int ARMAsmParser::tryParseRegister() {
2950 const AsmToken &Tok = Parser.getTok();
2951 if (Tok.isNot(AsmToken::Identifier)) return -1;
2953 std::string lowerCase = Tok.getString().lower();
2954 unsigned RegNum = MatchRegisterName(lowerCase);
2956 RegNum = StringSwitch<unsigned>(lowerCase)
2957 .Case("r13", ARM::SP)
2958 .Case("r14", ARM::LR)
2959 .Case("r15", ARM::PC)
2960 .Case("ip", ARM::R12)
2961 // Additional register name aliases for 'gas' compatibility.
2962 .Case("a1", ARM::R0)
2963 .Case("a2", ARM::R1)
2964 .Case("a3", ARM::R2)
2965 .Case("a4", ARM::R3)
2966 .Case("v1", ARM::R4)
2967 .Case("v2", ARM::R5)
2968 .Case("v3", ARM::R6)
2969 .Case("v4", ARM::R7)
2970 .Case("v5", ARM::R8)
2971 .Case("v6", ARM::R9)
2972 .Case("v7", ARM::R10)
2973 .Case("v8", ARM::R11)
2974 .Case("sb", ARM::R9)
2975 .Case("sl", ARM::R10)
2976 .Case("fp", ARM::R11)
2980 // Check for aliases registered via .req. Canonicalize to lower case.
2981 // That's more consistent since register names are case insensitive, and
2982 // it's how the original entry was passed in from MC/MCParser/AsmParser.
2983 StringMap<unsigned>::const_iterator Entry = RegisterReqs.find(lowerCase);
2984 // If no match, return failure.
2985 if (Entry == RegisterReqs.end())
2987 Parser.Lex(); // Eat identifier token.
2988 return Entry->getValue();
2991 Parser.Lex(); // Eat identifier token.
2996 // Try to parse a shifter (e.g., "lsl <amt>"). On success, return 0.
2997 // If a recoverable error occurs, return 1. If an irrecoverable error
2998 // occurs, return -1. An irrecoverable error is one where tokens have been
2999 // consumed in the process of trying to parse the shifter (i.e., when it is
3000 // indeed a shifter operand, but malformed).
3001 int ARMAsmParser::tryParseShiftRegister(OperandVector &Operands) {
3002 SMLoc S = Parser.getTok().getLoc();
3003 const AsmToken &Tok = Parser.getTok();
3004 if (Tok.isNot(AsmToken::Identifier))
3007 std::string lowerCase = Tok.getString().lower();
3008 ARM_AM::ShiftOpc ShiftTy = StringSwitch<ARM_AM::ShiftOpc>(lowerCase)
3009 .Case("asl", ARM_AM::lsl)
3010 .Case("lsl", ARM_AM::lsl)
3011 .Case("lsr", ARM_AM::lsr)
3012 .Case("asr", ARM_AM::asr)
3013 .Case("ror", ARM_AM::ror)
3014 .Case("rrx", ARM_AM::rrx)
3015 .Default(ARM_AM::no_shift);
3017 if (ShiftTy == ARM_AM::no_shift)
3020 Parser.Lex(); // Eat the operator.
3022 // The source register for the shift has already been added to the
3023 // operand list, so we need to pop it off and combine it into the shifted
3024 // register operand instead.
3025 std::unique_ptr<ARMOperand> PrevOp(
3026 (ARMOperand *)Operands.pop_back_val().release());
3027 if (!PrevOp->isReg())
3028 return Error(PrevOp->getStartLoc(), "shift must be of a register");
3029 int SrcReg = PrevOp->getReg();
3034 if (ShiftTy == ARM_AM::rrx) {
3035 // RRX Doesn't have an explicit shift amount. The encoder expects
3036 // the shift register to be the same as the source register. Seems odd,
3040 // Figure out if this is shifted by a constant or a register (for non-RRX).
3041 if (Parser.getTok().is(AsmToken::Hash) ||
3042 Parser.getTok().is(AsmToken::Dollar)) {
3043 Parser.Lex(); // Eat hash.
3044 SMLoc ImmLoc = Parser.getTok().getLoc();
3045 const MCExpr *ShiftExpr = nullptr;
3046 if (getParser().parseExpression(ShiftExpr, EndLoc)) {
3047 Error(ImmLoc, "invalid immediate shift value");
3050 // The expression must be evaluatable as an immediate.
3051 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftExpr);
3053 Error(ImmLoc, "invalid immediate shift value");
3056 // Range check the immediate.
3057 // lsl, ror: 0 <= imm <= 31
3058 // lsr, asr: 0 <= imm <= 32
3059 Imm = CE->getValue();
3061 ((ShiftTy == ARM_AM::lsl || ShiftTy == ARM_AM::ror) && Imm > 31) ||
3062 ((ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr) && Imm > 32)) {
3063 Error(ImmLoc, "immediate shift value out of range");
3066 // shift by zero is a nop. Always send it through as lsl.
3067 // ('as' compatibility)
3069 ShiftTy = ARM_AM::lsl;
3070 } else if (Parser.getTok().is(AsmToken::Identifier)) {
3071 SMLoc L = Parser.getTok().getLoc();
3072 EndLoc = Parser.getTok().getEndLoc();
3073 ShiftReg = tryParseRegister();
3074 if (ShiftReg == -1) {
3075 Error(L, "expected immediate or register in shift operand");
3079 Error(Parser.getTok().getLoc(),
3080 "expected immediate or register in shift operand");
3085 if (ShiftReg && ShiftTy != ARM_AM::rrx)
3086 Operands.push_back(ARMOperand::CreateShiftedRegister(ShiftTy, SrcReg,
3090 Operands.push_back(ARMOperand::CreateShiftedImmediate(ShiftTy, SrcReg, Imm,
3097 /// Try to parse a register name. The token must be an Identifier when called.
3098 /// If it's a register, an AsmOperand is created. Another AsmOperand is created
3099 /// if there is a "writeback". 'true' if it's not a register.
3101 /// TODO this is likely to change to allow different register types and or to
3102 /// parse for a specific register type.
3103 bool ARMAsmParser::tryParseRegisterWithWriteBack(OperandVector &Operands) {
3104 const AsmToken &RegTok = Parser.getTok();
3105 int RegNo = tryParseRegister();
3109 Operands.push_back(ARMOperand::CreateReg(RegNo, RegTok.getLoc(),
3110 RegTok.getEndLoc()));
3112 const AsmToken &ExclaimTok = Parser.getTok();
3113 if (ExclaimTok.is(AsmToken::Exclaim)) {
3114 Operands.push_back(ARMOperand::CreateToken(ExclaimTok.getString(),
3115 ExclaimTok.getLoc()));
3116 Parser.Lex(); // Eat exclaim token
3120 // Also check for an index operand. This is only legal for vector registers,
3121 // but that'll get caught OK in operand matching, so we don't need to
3122 // explicitly filter everything else out here.
3123 if (Parser.getTok().is(AsmToken::LBrac)) {
3124 SMLoc SIdx = Parser.getTok().getLoc();
3125 Parser.Lex(); // Eat left bracket token.
3127 const MCExpr *ImmVal;
3128 if (getParser().parseExpression(ImmVal))
3130 const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(ImmVal);
3132 return TokError("immediate value expected for vector index");
3134 if (Parser.getTok().isNot(AsmToken::RBrac))
3135 return Error(Parser.getTok().getLoc(), "']' expected");
3137 SMLoc E = Parser.getTok().getEndLoc();
3138 Parser.Lex(); // Eat right bracket token.
3140 Operands.push_back(ARMOperand::CreateVectorIndex(MCE->getValue(),
3148 /// MatchCoprocessorOperandName - Try to parse an coprocessor related
3149 /// instruction with a symbolic operand name.
3150 /// We accept "crN" syntax for GAS compatibility.
3151 /// <operand-name> ::= <prefix><number>
3152 /// If CoprocOp is 'c', then:
3153 /// <prefix> ::= c | cr
3154 /// If CoprocOp is 'p', then :
3156 /// <number> ::= integer in range [0, 15]
3157 static int MatchCoprocessorOperandName(StringRef Name, char CoprocOp) {
3158 // Use the same layout as the tablegen'erated register name matcher. Ugly,
3160 if (Name.size() < 2 || Name[0] != CoprocOp)
3162 Name = (Name[1] == 'r') ? Name.drop_front(2) : Name.drop_front();
3164 switch (Name.size()) {
3185 // CP10 and CP11 are VFP/NEON and so vector instructions should be used.
3186 // However, old cores (v5/v6) did use them in that way.
3187 case '0': return 10;
3188 case '1': return 11;
3189 case '2': return 12;
3190 case '3': return 13;
3191 case '4': return 14;
3192 case '5': return 15;
3197 /// parseITCondCode - Try to parse a condition code for an IT instruction.
3198 ARMAsmParser::OperandMatchResultTy
3199 ARMAsmParser::parseITCondCode(OperandVector &Operands) {
3200 SMLoc S = Parser.getTok().getLoc();
3201 const AsmToken &Tok = Parser.getTok();
3202 if (!Tok.is(AsmToken::Identifier))
3203 return MatchOperand_NoMatch;
3204 unsigned CC = StringSwitch<unsigned>(Tok.getString().lower())
3205 .Case("eq", ARMCC::EQ)
3206 .Case("ne", ARMCC::NE)
3207 .Case("hs", ARMCC::HS)
3208 .Case("cs", ARMCC::HS)
3209 .Case("lo", ARMCC::LO)
3210 .Case("cc", ARMCC::LO)
3211 .Case("mi", ARMCC::MI)
3212 .Case("pl", ARMCC::PL)
3213 .Case("vs", ARMCC::VS)
3214 .Case("vc", ARMCC::VC)
3215 .Case("hi", ARMCC::HI)
3216 .Case("ls", ARMCC::LS)
3217 .Case("ge", ARMCC::GE)
3218 .Case("lt", ARMCC::LT)
3219 .Case("gt", ARMCC::GT)
3220 .Case("le", ARMCC::LE)
3221 .Case("al", ARMCC::AL)
3224 return MatchOperand_NoMatch;
3225 Parser.Lex(); // Eat the token.
3227 Operands.push_back(ARMOperand::CreateCondCode(ARMCC::CondCodes(CC), S));
3229 return MatchOperand_Success;
3232 /// parseCoprocNumOperand - Try to parse an coprocessor number operand. The
3233 /// token must be an Identifier when called, and if it is a coprocessor
3234 /// number, the token is eaten and the operand is added to the operand list.
3235 ARMAsmParser::OperandMatchResultTy
3236 ARMAsmParser::parseCoprocNumOperand(OperandVector &Operands) {
3237 SMLoc S = Parser.getTok().getLoc();
3238 const AsmToken &Tok = Parser.getTok();
3239 if (Tok.isNot(AsmToken::Identifier))
3240 return MatchOperand_NoMatch;
3242 int Num = MatchCoprocessorOperandName(Tok.getString(), 'p');
3244 return MatchOperand_NoMatch;
3245 // ARMv7 and v8 don't allow cp10/cp11 due to VFP/NEON specific instructions
3246 if ((hasV7Ops() || hasV8Ops()) && (Num == 10 || Num == 11))
3247 return MatchOperand_NoMatch;
3249 Parser.Lex(); // Eat identifier token.
3250 Operands.push_back(ARMOperand::CreateCoprocNum(Num, S));
3251 return MatchOperand_Success;
3254 /// parseCoprocRegOperand - Try to parse an coprocessor register operand. The
3255 /// token must be an Identifier when called, and if it is a coprocessor
3256 /// number, the token is eaten and the operand is added to the operand list.
3257 ARMAsmParser::OperandMatchResultTy
3258 ARMAsmParser::parseCoprocRegOperand(OperandVector &Operands) {
3259 SMLoc S = Parser.getTok().getLoc();
3260 const AsmToken &Tok = Parser.getTok();
3261 if (Tok.isNot(AsmToken::Identifier))
3262 return MatchOperand_NoMatch;
3264 int Reg = MatchCoprocessorOperandName(Tok.getString(), 'c');
3266 return MatchOperand_NoMatch;
3268 Parser.Lex(); // Eat identifier token.
3269 Operands.push_back(ARMOperand::CreateCoprocReg(Reg, S));
3270 return MatchOperand_Success;
3273 /// parseCoprocOptionOperand - Try to parse an coprocessor option operand.
3274 /// coproc_option : '{' imm0_255 '}'
3275 ARMAsmParser::OperandMatchResultTy
3276 ARMAsmParser::parseCoprocOptionOperand(OperandVector &Operands) {
3277 SMLoc S = Parser.getTok().getLoc();
3279 // If this isn't a '{', this isn't a coprocessor immediate operand.
3280 if (Parser.getTok().isNot(AsmToken::LCurly))
3281 return MatchOperand_NoMatch;
3282 Parser.Lex(); // Eat the '{'
3285 SMLoc Loc = Parser.getTok().getLoc();
3286 if (getParser().parseExpression(Expr)) {
3287 Error(Loc, "illegal expression");
3288 return MatchOperand_ParseFail;
3290 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
3291 if (!CE || CE->getValue() < 0 || CE->getValue() > 255) {
3292 Error(Loc, "coprocessor option must be an immediate in range [0, 255]");
3293 return MatchOperand_ParseFail;
3295 int Val = CE->getValue();
3297 // Check for and consume the closing '}'
3298 if (Parser.getTok().isNot(AsmToken::RCurly))
3299 return MatchOperand_ParseFail;
3300 SMLoc E = Parser.getTok().getEndLoc();
3301 Parser.Lex(); // Eat the '}'
3303 Operands.push_back(ARMOperand::CreateCoprocOption(Val, S, E));
3304 return MatchOperand_Success;
3307 // For register list parsing, we need to map from raw GPR register numbering
3308 // to the enumeration values. The enumeration values aren't sorted by
3309 // register number due to our using "sp", "lr" and "pc" as canonical names.
3310 static unsigned getNextRegister(unsigned Reg) {
3311 // If this is a GPR, we need to do it manually, otherwise we can rely
3312 // on the sort ordering of the enumeration since the other reg-classes
3314 if (!ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
3317 default: llvm_unreachable("Invalid GPR number!");
3318 case ARM::R0: return ARM::R1; case ARM::R1: return ARM::R2;
3319 case ARM::R2: return ARM::R3; case ARM::R3: return ARM::R4;
3320 case ARM::R4: return ARM::R5; case ARM::R5: return ARM::R6;
3321 case ARM::R6: return ARM::R7; case ARM::R7: return ARM::R8;
3322 case ARM::R8: return ARM::R9; case ARM::R9: return ARM::R10;
3323 case ARM::R10: return ARM::R11; case ARM::R11: return ARM::R12;
3324 case ARM::R12: return ARM::SP; case ARM::SP: return ARM::LR;
3325 case ARM::LR: return ARM::PC; case ARM::PC: return ARM::R0;
3329 // Return the low-subreg of a given Q register.
3330 static unsigned getDRegFromQReg(unsigned QReg) {
3332 default: llvm_unreachable("expected a Q register!");
3333 case ARM::Q0: return ARM::D0;
3334 case ARM::Q1: return ARM::D2;
3335 case ARM::Q2: return ARM::D4;
3336 case ARM::Q3: return ARM::D6;
3337 case ARM::Q4: return ARM::D8;
3338 case ARM::Q5: return ARM::D10;
3339 case ARM::Q6: return ARM::D12;
3340 case ARM::Q7: return ARM::D14;
3341 case ARM::Q8: return ARM::D16;
3342 case ARM::Q9: return ARM::D18;
3343 case ARM::Q10: return ARM::D20;
3344 case ARM::Q11: return ARM::D22;
3345 case ARM::Q12: return ARM::D24;
3346 case ARM::Q13: return ARM::D26;
3347 case ARM::Q14: return ARM::D28;
3348 case ARM::Q15: return ARM::D30;
3352 /// Parse a register list.
3353 bool ARMAsmParser::parseRegisterList(OperandVector &Operands) {
3354 assert(Parser.getTok().is(AsmToken::LCurly) &&
3355 "Token is not a Left Curly Brace");
3356 SMLoc S = Parser.getTok().getLoc();
3357 Parser.Lex(); // Eat '{' token.
3358 SMLoc RegLoc = Parser.getTok().getLoc();
3360 // Check the first register in the list to see what register class
3361 // this is a list of.
3362 int Reg = tryParseRegister();
3364 return Error(RegLoc, "register expected");
3366 // The reglist instructions have at most 16 registers, so reserve
3367 // space for that many.
3369 SmallVector<std::pair<unsigned, unsigned>, 16> Registers;
3371 // Allow Q regs and just interpret them as the two D sub-registers.
3372 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3373 Reg = getDRegFromQReg(Reg);
3374 EReg = MRI->getEncodingValue(Reg);
3375 Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3378 const MCRegisterClass *RC;
3379 if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
3380 RC = &ARMMCRegisterClasses[ARM::GPRRegClassID];
3381 else if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg))
3382 RC = &ARMMCRegisterClasses[ARM::DPRRegClassID];
3383 else if (ARMMCRegisterClasses[ARM::SPRRegClassID].contains(Reg))
3384 RC = &ARMMCRegisterClasses[ARM::SPRRegClassID];
3386 return Error(RegLoc, "invalid register in register list");
3388 // Store the register.
3389 EReg = MRI->getEncodingValue(Reg);
3390 Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3392 // This starts immediately after the first register token in the list,
3393 // so we can see either a comma or a minus (range separator) as a legal
3395 while (Parser.getTok().is(AsmToken::Comma) ||
3396 Parser.getTok().is(AsmToken::Minus)) {
3397 if (Parser.getTok().is(AsmToken::Minus)) {
3398 Parser.Lex(); // Eat the minus.
3399 SMLoc AfterMinusLoc = Parser.getTok().getLoc();
3400 int EndReg = tryParseRegister();
3402 return Error(AfterMinusLoc, "register expected");
3403 // Allow Q regs and just interpret them as the two D sub-registers.
3404 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg))
3405 EndReg = getDRegFromQReg(EndReg) + 1;
3406 // If the register is the same as the start reg, there's nothing
3410 // The register must be in the same register class as the first.
3411 if (!RC->contains(EndReg))
3412 return Error(AfterMinusLoc, "invalid register in register list");
3413 // Ranges must go from low to high.
3414 if (MRI->getEncodingValue(Reg) > MRI->getEncodingValue(EndReg))
3415 return Error(AfterMinusLoc, "bad range in register list");
3417 // Add all the registers in the range to the register list.
3418 while (Reg != EndReg) {
3419 Reg = getNextRegister(Reg);
3420 EReg = MRI->getEncodingValue(Reg);
3421 Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3425 Parser.Lex(); // Eat the comma.
3426 RegLoc = Parser.getTok().getLoc();
3428 const AsmToken RegTok = Parser.getTok();
3429 Reg = tryParseRegister();
3431 return Error(RegLoc, "register expected");
3432 // Allow Q regs and just interpret them as the two D sub-registers.
3433 bool isQReg = false;
3434 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3435 Reg = getDRegFromQReg(Reg);
3438 // The register must be in the same register class as the first.
3439 if (!RC->contains(Reg))
3440 return Error(RegLoc, "invalid register in register list");
3441 // List must be monotonically increasing.
3442 if (MRI->getEncodingValue(Reg) < MRI->getEncodingValue(OldReg)) {
3443 if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
3444 Warning(RegLoc, "register list not in ascending order");
3446 return Error(RegLoc, "register list not in ascending order");
3448 if (MRI->getEncodingValue(Reg) == MRI->getEncodingValue(OldReg)) {
3449 Warning(RegLoc, "duplicated register (" + RegTok.getString() +
3450 ") in register list");
3453 // VFP register lists must also be contiguous.
3454 if (RC != &ARMMCRegisterClasses[ARM::GPRRegClassID] &&
3456 return Error(RegLoc, "non-contiguous register range");
3457 EReg = MRI->getEncodingValue(Reg);
3458 Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3460 EReg = MRI->getEncodingValue(++Reg);
3461 Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3465 if (Parser.getTok().isNot(AsmToken::RCurly))
3466 return Error(Parser.getTok().getLoc(), "'}' expected");
3467 SMLoc E = Parser.getTok().getEndLoc();
3468 Parser.Lex(); // Eat '}' token.
3470 // Push the register list operand.
3471 Operands.push_back(ARMOperand::CreateRegList(Registers, S, E));
3473 // The ARM system instruction variants for LDM/STM have a '^' token here.
3474 if (Parser.getTok().is(AsmToken::Caret)) {
3475 Operands.push_back(ARMOperand::CreateToken("^",Parser.getTok().getLoc()));
3476 Parser.Lex(); // Eat '^' token.
3482 // Helper function to parse the lane index for vector lists.
3483 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3484 parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index, SMLoc &EndLoc) {
3485 Index = 0; // Always return a defined index value.
3486 if (Parser.getTok().is(AsmToken::LBrac)) {
3487 Parser.Lex(); // Eat the '['.
3488 if (Parser.getTok().is(AsmToken::RBrac)) {
3489 // "Dn[]" is the 'all lanes' syntax.
3490 LaneKind = AllLanes;
3491 EndLoc = Parser.getTok().getEndLoc();
3492 Parser.Lex(); // Eat the ']'.
3493 return MatchOperand_Success;
3496 // There's an optional '#' token here. Normally there wouldn't be, but
3497 // inline assemble puts one in, and it's friendly to accept that.
3498 if (Parser.getTok().is(AsmToken::Hash))
3499 Parser.Lex(); // Eat '#' or '$'.
3501 const MCExpr *LaneIndex;
3502 SMLoc Loc = Parser.getTok().getLoc();
3503 if (getParser().parseExpression(LaneIndex)) {
3504 Error(Loc, "illegal expression");
3505 return MatchOperand_ParseFail;
3507 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LaneIndex);
3509 Error(Loc, "lane index must be empty or an integer");
3510 return MatchOperand_ParseFail;
3512 if (Parser.getTok().isNot(AsmToken::RBrac)) {
3513 Error(Parser.getTok().getLoc(), "']' expected");
3514 return MatchOperand_ParseFail;
3516 EndLoc = Parser.getTok().getEndLoc();
3517 Parser.Lex(); // Eat the ']'.
3518 int64_t Val = CE->getValue();
3520 // FIXME: Make this range check context sensitive for .8, .16, .32.
3521 if (Val < 0 || Val > 7) {
3522 Error(Parser.getTok().getLoc(), "lane index out of range");
3523 return MatchOperand_ParseFail;
3526 LaneKind = IndexedLane;
3527 return MatchOperand_Success;
3530 return MatchOperand_Success;
3533 // parse a vector register list
3534 ARMAsmParser::OperandMatchResultTy
3535 ARMAsmParser::parseVectorList(OperandVector &Operands) {
3536 VectorLaneTy LaneKind;
3538 SMLoc S = Parser.getTok().getLoc();
3539 // As an extension (to match gas), support a plain D register or Q register
3540 // (without encosing curly braces) as a single or double entry list,
3542 if (Parser.getTok().is(AsmToken::Identifier)) {
3543 SMLoc E = Parser.getTok().getEndLoc();
3544 int Reg = tryParseRegister();
3546 return MatchOperand_NoMatch;
3547 if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg)) {
3548 OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex, E);
3549 if (Res != MatchOperand_Success)
3553 Operands.push_back(ARMOperand::CreateVectorList(Reg, 1, false, S, E));
3556 Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 1, false,
3560 Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 1,
3565 return MatchOperand_Success;
3567 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3568 Reg = getDRegFromQReg(Reg);
3569 OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex, E);
3570 if (Res != MatchOperand_Success)
3574 Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0,
3575 &ARMMCRegisterClasses[ARM::DPairRegClassID]);
3576 Operands.push_back(ARMOperand::CreateVectorList(Reg, 2, false, S, E));
3579 Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0,
3580 &ARMMCRegisterClasses[ARM::DPairRegClassID]);
3581 Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 2, false,
3585 Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 2,
3590 return MatchOperand_Success;
3592 Error(S, "vector register expected");
3593 return MatchOperand_ParseFail;
3596 if (Parser.getTok().isNot(AsmToken::LCurly))
3597 return MatchOperand_NoMatch;
3599 Parser.Lex(); // Eat '{' token.
3600 SMLoc RegLoc = Parser.getTok().getLoc();
3602 int Reg = tryParseRegister();
3604 Error(RegLoc, "register expected");
3605 return MatchOperand_ParseFail;
3609 unsigned FirstReg = Reg;
3610 // The list is of D registers, but we also allow Q regs and just interpret
3611 // them as the two D sub-registers.
3612 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3613 FirstReg = Reg = getDRegFromQReg(Reg);
3614 Spacing = 1; // double-spacing requires explicit D registers, otherwise
3615 // it's ambiguous with four-register single spaced.
3621 if (parseVectorLane(LaneKind, LaneIndex, E) != MatchOperand_Success)
3622 return MatchOperand_ParseFail;
3624 while (Parser.getTok().is(AsmToken::Comma) ||
3625 Parser.getTok().is(AsmToken::Minus)) {
3626 if (Parser.getTok().is(AsmToken::Minus)) {
3628 Spacing = 1; // Register range implies a single spaced list.
3629 else if (Spacing == 2) {
3630 Error(Parser.getTok().getLoc(),
3631 "sequential registers in double spaced list");
3632 return MatchOperand_ParseFail;
3634 Parser.Lex(); // Eat the minus.
3635 SMLoc AfterMinusLoc = Parser.getTok().getLoc();
3636 int EndReg = tryParseRegister();
3638 Error(AfterMinusLoc, "register expected");
3639 return MatchOperand_ParseFail;
3641 // Allow Q regs and just interpret them as the two D sub-registers.
3642 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg))
3643 EndReg = getDRegFromQReg(EndReg) + 1;
3644 // If the register is the same as the start reg, there's nothing
3648 // The register must be in the same register class as the first.
3649 if (!ARMMCRegisterClasses[ARM::DPRRegClassID].contains(EndReg)) {
3650 Error(AfterMinusLoc, "invalid register in register list");
3651 return MatchOperand_ParseFail;
3653 // Ranges must go from low to high.
3655 Error(AfterMinusLoc, "bad range in register list");
3656 return MatchOperand_ParseFail;
3658 // Parse the lane specifier if present.
3659 VectorLaneTy NextLaneKind;
3660 unsigned NextLaneIndex;
3661 if (parseVectorLane(NextLaneKind, NextLaneIndex, E) !=
3662 MatchOperand_Success)
3663 return MatchOperand_ParseFail;
3664 if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
3665 Error(AfterMinusLoc, "mismatched lane index in register list");
3666 return MatchOperand_ParseFail;
3669 // Add all the registers in the range to the register list.
3670 Count += EndReg - Reg;
3674 Parser.Lex(); // Eat the comma.
3675 RegLoc = Parser.getTok().getLoc();
3677 Reg = tryParseRegister();
3679 Error(RegLoc, "register expected");
3680 return MatchOperand_ParseFail;
3682 // vector register lists must be contiguous.
3683 // It's OK to use the enumeration values directly here rather, as the
3684 // VFP register classes have the enum sorted properly.
3686 // The list is of D registers, but we also allow Q regs and just interpret
3687 // them as the two D sub-registers.
3688 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3690 Spacing = 1; // Register range implies a single spaced list.
3691 else if (Spacing == 2) {
3693 "invalid register in double-spaced list (must be 'D' register')");
3694 return MatchOperand_ParseFail;
3696 Reg = getDRegFromQReg(Reg);
3697 if (Reg != OldReg + 1) {
3698 Error(RegLoc, "non-contiguous register range");
3699 return MatchOperand_ParseFail;
3703 // Parse the lane specifier if present.
3704 VectorLaneTy NextLaneKind;
3705 unsigned NextLaneIndex;
3706 SMLoc LaneLoc = Parser.getTok().getLoc();
3707 if (parseVectorLane(NextLaneKind, NextLaneIndex, E) !=
3708 MatchOperand_Success)
3709 return MatchOperand_ParseFail;
3710 if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
3711 Error(LaneLoc, "mismatched lane index in register list");
3712 return MatchOperand_ParseFail;
3716 // Normal D register.
3717 // Figure out the register spacing (single or double) of the list if
3718 // we don't know it already.
3720 Spacing = 1 + (Reg == OldReg + 2);
3722 // Just check that it's contiguous and keep going.
3723 if (Reg != OldReg + Spacing) {
3724 Error(RegLoc, "non-contiguous register range");
3725 return MatchOperand_ParseFail;
3728 // Parse the lane specifier if present.
3729 VectorLaneTy NextLaneKind;
3730 unsigned NextLaneIndex;
3731 SMLoc EndLoc = Parser.getTok().getLoc();
3732 if (parseVectorLane(NextLaneKind, NextLaneIndex, E) != MatchOperand_Success)
3733 return MatchOperand_ParseFail;
3734 if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
3735 Error(EndLoc, "mismatched lane index in register list");
3736 return MatchOperand_ParseFail;
3740 if (Parser.getTok().isNot(AsmToken::RCurly)) {
3741 Error(Parser.getTok().getLoc(), "'}' expected");
3742 return MatchOperand_ParseFail;
3744 E = Parser.getTok().getEndLoc();
3745 Parser.Lex(); // Eat '}' token.
3749 // Two-register operands have been converted to the
3750 // composite register classes.
3752 const MCRegisterClass *RC = (Spacing == 1) ?
3753 &ARMMCRegisterClasses[ARM::DPairRegClassID] :
3754 &ARMMCRegisterClasses[ARM::DPairSpcRegClassID];
3755 FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC);
3758 Operands.push_back(ARMOperand::CreateVectorList(FirstReg, Count,
3759 (Spacing == 2), S, E));
3762 // Two-register operands have been converted to the
3763 // composite register classes.
3765 const MCRegisterClass *RC = (Spacing == 1) ?
3766 &ARMMCRegisterClasses[ARM::DPairRegClassID] :
3767 &ARMMCRegisterClasses[ARM::DPairSpcRegClassID];
3768 FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC);
3770 Operands.push_back(ARMOperand::CreateVectorListAllLanes(FirstReg, Count,
3775 Operands.push_back(ARMOperand::CreateVectorListIndexed(FirstReg, Count,
3781 return MatchOperand_Success;
3784 /// parseMemBarrierOptOperand - Try to parse DSB/DMB data barrier options.
3785 ARMAsmParser::OperandMatchResultTy
3786 ARMAsmParser::parseMemBarrierOptOperand(OperandVector &Operands) {
3787 SMLoc S = Parser.getTok().getLoc();
3788 const AsmToken &Tok = Parser.getTok();
3791 if (Tok.is(AsmToken::Identifier)) {
3792 StringRef OptStr = Tok.getString();
3794 Opt = StringSwitch<unsigned>(OptStr.slice(0, OptStr.size()).lower())
3795 .Case("sy", ARM_MB::SY)
3796 .Case("st", ARM_MB::ST)
3797 .Case("ld", ARM_MB::LD)
3798 .Case("sh", ARM_MB::ISH)
3799 .Case("ish", ARM_MB::ISH)
3800 .Case("shst", ARM_MB::ISHST)
3801 .Case("ishst", ARM_MB::ISHST)
3802 .Case("ishld", ARM_MB::ISHLD)
3803 .Case("nsh", ARM_MB::NSH)
3804 .Case("un", ARM_MB::NSH)
3805 .Case("nshst", ARM_MB::NSHST)
3806 .Case("nshld", ARM_MB::NSHLD)
3807 .Case("unst", ARM_MB::NSHST)
3808 .Case("osh", ARM_MB::OSH)
3809 .Case("oshst", ARM_MB::OSHST)
3810 .Case("oshld", ARM_MB::OSHLD)
3813 // ishld, oshld, nshld and ld are only available from ARMv8.
3814 if (!hasV8Ops() && (Opt == ARM_MB::ISHLD || Opt == ARM_MB::OSHLD ||
3815 Opt == ARM_MB::NSHLD || Opt == ARM_MB::LD))
3819 return MatchOperand_NoMatch;
3821 Parser.Lex(); // Eat identifier token.
3822 } else if (Tok.is(AsmToken::Hash) ||
3823 Tok.is(AsmToken::Dollar) ||
3824 Tok.is(AsmToken::Integer)) {
3825 if (Parser.getTok().isNot(AsmToken::Integer))
3826 Parser.Lex(); // Eat '#' or '$'.
3827 SMLoc Loc = Parser.getTok().getLoc();
3829 const MCExpr *MemBarrierID;
3830 if (getParser().parseExpression(MemBarrierID)) {
3831 Error(Loc, "illegal expression");
3832 return MatchOperand_ParseFail;
3835 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(MemBarrierID);
3837 Error(Loc, "constant expression expected");
3838 return MatchOperand_ParseFail;
3841 int Val = CE->getValue();
3843 Error(Loc, "immediate value out of range");
3844 return MatchOperand_ParseFail;
3847 Opt = ARM_MB::RESERVED_0 + Val;
3849 return MatchOperand_ParseFail;
3851 Operands.push_back(ARMOperand::CreateMemBarrierOpt((ARM_MB::MemBOpt)Opt, S));
3852 return MatchOperand_Success;
3855 /// parseInstSyncBarrierOptOperand - Try to parse ISB inst sync barrier options.
3856 ARMAsmParser::OperandMatchResultTy
3857 ARMAsmParser::parseInstSyncBarrierOptOperand(OperandVector &Operands) {
3858 SMLoc S = Parser.getTok().getLoc();
3859 const AsmToken &Tok = Parser.getTok();
3862 if (Tok.is(AsmToken::Identifier)) {
3863 StringRef OptStr = Tok.getString();
3865 if (OptStr.equals_lower("sy"))
3868 return MatchOperand_NoMatch;
3870 Parser.Lex(); // Eat identifier token.
3871 } else if (Tok.is(AsmToken::Hash) ||
3872 Tok.is(AsmToken::Dollar) ||
3873 Tok.is(AsmToken::Integer)) {
3874 if (Parser.getTok().isNot(AsmToken::Integer))
3875 Parser.Lex(); // Eat '#' or '$'.
3876 SMLoc Loc = Parser.getTok().getLoc();
3878 const MCExpr *ISBarrierID;
3879 if (getParser().parseExpression(ISBarrierID)) {
3880 Error(Loc, "illegal expression");
3881 return MatchOperand_ParseFail;
3884 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ISBarrierID);
3886 Error(Loc, "constant expression expected");
3887 return MatchOperand_ParseFail;
3890 int Val = CE->getValue();
3892 Error(Loc, "immediate value out of range");
3893 return MatchOperand_ParseFail;
3896 Opt = ARM_ISB::RESERVED_0 + Val;
3898 return MatchOperand_ParseFail;
3900 Operands.push_back(ARMOperand::CreateInstSyncBarrierOpt(
3901 (ARM_ISB::InstSyncBOpt)Opt, S));
3902 return MatchOperand_Success;
3906 /// parseProcIFlagsOperand - Try to parse iflags from CPS instruction.
3907 ARMAsmParser::OperandMatchResultTy
3908 ARMAsmParser::parseProcIFlagsOperand(OperandVector &Operands) {
3909 SMLoc S = Parser.getTok().getLoc();
3910 const AsmToken &Tok = Parser.getTok();
3911 if (!Tok.is(AsmToken::Identifier))
3912 return MatchOperand_NoMatch;
3913 StringRef IFlagsStr = Tok.getString();
3915 // An iflags string of "none" is interpreted to mean that none of the AIF
3916 // bits are set. Not a terribly useful instruction, but a valid encoding.
3917 unsigned IFlags = 0;
3918 if (IFlagsStr != "none") {
3919 for (int i = 0, e = IFlagsStr.size(); i != e; ++i) {
3920 unsigned Flag = StringSwitch<unsigned>(IFlagsStr.substr(i, 1))
3921 .Case("a", ARM_PROC::A)
3922 .Case("i", ARM_PROC::I)
3923 .Case("f", ARM_PROC::F)
3926 // If some specific iflag is already set, it means that some letter is
3927 // present more than once, this is not acceptable.
3928 if (Flag == ~0U || (IFlags & Flag))
3929 return MatchOperand_NoMatch;
3935 Parser.Lex(); // Eat identifier token.
3936 Operands.push_back(ARMOperand::CreateProcIFlags((ARM_PROC::IFlags)IFlags, S));
3937 return MatchOperand_Success;
3940 /// parseMSRMaskOperand - Try to parse mask flags from MSR instruction.
3941 ARMAsmParser::OperandMatchResultTy
3942 ARMAsmParser::parseMSRMaskOperand(OperandVector &Operands) {
3943 SMLoc S = Parser.getTok().getLoc();
3944 const AsmToken &Tok = Parser.getTok();
3945 if (!Tok.is(AsmToken::Identifier))
3946 return MatchOperand_NoMatch;
3947 StringRef Mask = Tok.getString();
3950 // See ARMv6-M 10.1.1
3951 std::string Name = Mask.lower();
3952 unsigned FlagsVal = StringSwitch<unsigned>(Name)
3953 // Note: in the documentation:
3954 // ARM deprecates using MSR APSR without a _<bits> qualifier as an alias
3955 // for MSR APSR_nzcvq.
3956 // but we do make it an alias here. This is so to get the "mask encoding"
3957 // bits correct on MSR APSR writes.
3959 // FIXME: Note the 0xc00 "mask encoding" bits version of the registers
3960 // should really only be allowed when writing a special register. Note
3961 // they get dropped in the MRS instruction reading a special register as
3962 // the SYSm field is only 8 bits.
3963 .Case("apsr", 0x800)
3964 .Case("apsr_nzcvq", 0x800)
3965 .Case("apsr_g", 0x400)
3966 .Case("apsr_nzcvqg", 0xc00)
3967 .Case("iapsr", 0x801)
3968 .Case("iapsr_nzcvq", 0x801)
3969 .Case("iapsr_g", 0x401)
3970 .Case("iapsr_nzcvqg", 0xc01)
3971 .Case("eapsr", 0x802)
3972 .Case("eapsr_nzcvq", 0x802)
3973 .Case("eapsr_g", 0x402)
3974 .Case("eapsr_nzcvqg", 0xc02)
3975 .Case("xpsr", 0x803)
3976 .Case("xpsr_nzcvq", 0x803)
3977 .Case("xpsr_g", 0x403)
3978 .Case("xpsr_nzcvqg", 0xc03)
3979 .Case("ipsr", 0x805)
3980 .Case("epsr", 0x806)
3981 .Case("iepsr", 0x807)
3984 .Case("primask", 0x810)
3985 .Case("basepri", 0x811)
3986 .Case("basepri_max", 0x812)
3987 .Case("faultmask", 0x813)
3988 .Case("control", 0x814)
3991 if (FlagsVal == ~0U)
3992 return MatchOperand_NoMatch;
3994 if (!hasThumb2DSP() && (FlagsVal & 0x400))
3995 // The _g and _nzcvqg versions are only valid if the DSP extension is
3997 return MatchOperand_NoMatch;
3999 if (!hasV7Ops() && FlagsVal >= 0x811 && FlagsVal <= 0x813)
4000 // basepri, basepri_max and faultmask only valid for V7m.
4001 return MatchOperand_NoMatch;
4003 Parser.Lex(); // Eat identifier token.
4004 Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S));
4005 return MatchOperand_Success;
4008 // Split spec_reg from flag, example: CPSR_sxf => "CPSR" and "sxf"
4009 size_t Start = 0, Next = Mask.find('_');
4010 StringRef Flags = "";
4011 std::string SpecReg = Mask.slice(Start, Next).lower();
4012 if (Next != StringRef::npos)
4013 Flags = Mask.slice(Next+1, Mask.size());
4015 // FlagsVal contains the complete mask:
4017 // 4: Special Reg (cpsr, apsr => 0; spsr => 1)
4018 unsigned FlagsVal = 0;
4020 if (SpecReg == "apsr") {
4021 FlagsVal = StringSwitch<unsigned>(Flags)
4022 .Case("nzcvq", 0x8) // same as CPSR_f
4023 .Case("g", 0x4) // same as CPSR_s
4024 .Case("nzcvqg", 0xc) // same as CPSR_fs
4027 if (FlagsVal == ~0U) {
4029 return MatchOperand_NoMatch;
4031 FlagsVal = 8; // No flag
4033 } else if (SpecReg == "cpsr" || SpecReg == "spsr") {
4034 // cpsr_all is an alias for cpsr_fc, as is plain cpsr.
4035 if (Flags == "all" || Flags == "")
4037 for (int i = 0, e = Flags.size(); i != e; ++i) {
4038 unsigned Flag = StringSwitch<unsigned>(Flags.substr(i, 1))
4045 // If some specific flag is already set, it means that some letter is
4046 // present more than once, this is not acceptable.
4047 if (FlagsVal == ~0U || (FlagsVal & Flag))
4048 return MatchOperand_NoMatch;
4051 } else // No match for special register.
4052 return MatchOperand_NoMatch;
4054 // Special register without flags is NOT equivalent to "fc" flags.
4055 // NOTE: This is a divergence from gas' behavior. Uncommenting the following
4056 // two lines would enable gas compatibility at the expense of breaking
4062 // Bit 4: Special Reg (cpsr, apsr => 0; spsr => 1)
4063 if (SpecReg == "spsr")
4066 Parser.Lex(); // Eat identifier token.
4067 Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S));
4068 return MatchOperand_Success;
4071 /// parseBankedRegOperand - Try to parse a banked register (e.g. "lr_irq") for
4072 /// use in the MRS/MSR instructions added to support virtualization.
4073 ARMAsmParser::OperandMatchResultTy
4074 ARMAsmParser::parseBankedRegOperand(OperandVector &Operands) {
4075 SMLoc S = Parser.getTok().getLoc();
4076 const AsmToken &Tok = Parser.getTok();
4077 if (!Tok.is(AsmToken::Identifier))
4078 return MatchOperand_NoMatch;
4079 StringRef RegName = Tok.getString();
4081 // The values here come from B9.2.3 of the ARM ARM, where bits 4-0 are SysM
4083 unsigned Encoding = StringSwitch<unsigned>(RegName.lower())
4084 .Case("r8_usr", 0x00)
4085 .Case("r9_usr", 0x01)
4086 .Case("r10_usr", 0x02)
4087 .Case("r11_usr", 0x03)
4088 .Case("r12_usr", 0x04)
4089 .Case("sp_usr", 0x05)
4090 .Case("lr_usr", 0x06)
4091 .Case("r8_fiq", 0x08)
4092 .Case("r9_fiq", 0x09)
4093 .Case("r10_fiq", 0x0a)
4094 .Case("r11_fiq", 0x0b)
4095 .Case("r12_fiq", 0x0c)
4096 .Case("sp_fiq", 0x0d)
4097 .Case("lr_fiq", 0x0e)
4098 .Case("lr_irq", 0x10)
4099 .Case("sp_irq", 0x11)
4100 .Case("lr_svc", 0x12)
4101 .Case("sp_svc", 0x13)
4102 .Case("lr_abt", 0x14)
4103 .Case("sp_abt", 0x15)
4104 .Case("lr_und", 0x16)
4105 .Case("sp_und", 0x17)
4106 .Case("lr_mon", 0x1c)
4107 .Case("sp_mon", 0x1d)
4108 .Case("elr_hyp", 0x1e)
4109 .Case("sp_hyp", 0x1f)
4110 .Case("spsr_fiq", 0x2e)
4111 .Case("spsr_irq", 0x30)
4112 .Case("spsr_svc", 0x32)
4113 .Case("spsr_abt", 0x34)
4114 .Case("spsr_und", 0x36)
4115 .Case("spsr_mon", 0x3c)
4116 .Case("spsr_hyp", 0x3e)
4119 if (Encoding == ~0U)
4120 return MatchOperand_NoMatch;
4122 Parser.Lex(); // Eat identifier token.
4123 Operands.push_back(ARMOperand::CreateBankedReg(Encoding, S));
4124 return MatchOperand_Success;
4127 ARMAsmParser::OperandMatchResultTy
4128 ARMAsmParser::parsePKHImm(OperandVector &Operands, StringRef Op, int Low,
4130 const AsmToken &Tok = Parser.getTok();
4131 if (Tok.isNot(AsmToken::Identifier)) {
4132 Error(Parser.getTok().getLoc(), Op + " operand expected.");
4133 return MatchOperand_ParseFail;
4135 StringRef ShiftName = Tok.getString();
4136 std::string LowerOp = Op.lower();
4137 std::string UpperOp = Op.upper();
4138 if (ShiftName != LowerOp && ShiftName != UpperOp) {
4139 Error(Parser.getTok().getLoc(), Op + " operand expected.");
4140 return MatchOperand_ParseFail;
4142 Parser.Lex(); // Eat shift type token.
4144 // There must be a '#' and a shift amount.
4145 if (Parser.getTok().isNot(AsmToken::Hash) &&
4146 Parser.getTok().isNot(AsmToken::Dollar)) {
4147 Error(Parser.getTok().getLoc(), "'#' expected");
4148 return MatchOperand_ParseFail;
4150 Parser.Lex(); // Eat hash token.
4152 const MCExpr *ShiftAmount;
4153 SMLoc Loc = Parser.getTok().getLoc();
4155 if (getParser().parseExpression(ShiftAmount, EndLoc)) {
4156 Error(Loc, "illegal expression");
4157 return MatchOperand_ParseFail;
4159 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
4161 Error(Loc, "constant expression expected");
4162 return MatchOperand_ParseFail;
4164 int Val = CE->getValue();
4165 if (Val < Low || Val > High) {
4166 Error(Loc, "immediate value out of range");
4167 return MatchOperand_ParseFail;
4170 Operands.push_back(ARMOperand::CreateImm(CE, Loc, EndLoc));
4172 return MatchOperand_Success;
4175 ARMAsmParser::OperandMatchResultTy
4176 ARMAsmParser::parseSetEndImm(OperandVector &Operands) {
4177 const AsmToken &Tok = Parser.getTok();
4178 SMLoc S = Tok.getLoc();
4179 if (Tok.isNot(AsmToken::Identifier)) {
4180 Error(S, "'be' or 'le' operand expected");
4181 return MatchOperand_ParseFail;
4183 int Val = StringSwitch<int>(Tok.getString().lower())
4187 Parser.Lex(); // Eat the token.
4190 Error(S, "'be' or 'le' operand expected");
4191 return MatchOperand_ParseFail;
4193 Operands.push_back(ARMOperand::CreateImm(MCConstantExpr::Create(Val,
4195 S, Tok.getEndLoc()));
4196 return MatchOperand_Success;
4199 /// parseShifterImm - Parse the shifter immediate operand for SSAT/USAT
4200 /// instructions. Legal values are:
4201 /// lsl #n 'n' in [0,31]
4202 /// asr #n 'n' in [1,32]
4203 /// n == 32 encoded as n == 0.
4204 ARMAsmParser::OperandMatchResultTy
4205 ARMAsmParser::parseShifterImm(OperandVector &Operands) {
4206 const AsmToken &Tok = Parser.getTok();
4207 SMLoc S = Tok.getLoc();
4208 if (Tok.isNot(AsmToken::Identifier)) {
4209 Error(S, "shift operator 'asr' or 'lsl' expected");
4210 return MatchOperand_ParseFail;
4212 StringRef ShiftName = Tok.getString();
4214 if (ShiftName == "lsl" || ShiftName == "LSL")
4216 else if (ShiftName == "asr" || ShiftName == "ASR")
4219 Error(S, "shift operator 'asr' or 'lsl' expected");
4220 return MatchOperand_ParseFail;
4222 Parser.Lex(); // Eat the operator.
4224 // A '#' and a shift amount.
4225 if (Parser.getTok().isNot(AsmToken::Hash) &&
4226 Parser.getTok().isNot(AsmToken::Dollar)) {
4227 Error(Parser.getTok().getLoc(), "'#' expected");
4228 return MatchOperand_ParseFail;
4230 Parser.Lex(); // Eat hash token.
4231 SMLoc ExLoc = Parser.getTok().getLoc();
4233 const MCExpr *ShiftAmount;
4235 if (getParser().parseExpression(ShiftAmount, EndLoc)) {
4236 Error(ExLoc, "malformed shift expression");
4237 return MatchOperand_ParseFail;
4239 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
4241 Error(ExLoc, "shift amount must be an immediate");
4242 return MatchOperand_ParseFail;
4245 int64_t Val = CE->getValue();
4247 // Shift amount must be in [1,32]
4248 if (Val < 1 || Val > 32) {
4249 Error(ExLoc, "'asr' shift amount must be in range [1,32]");
4250 return MatchOperand_ParseFail;
4252 // asr #32 encoded as asr #0, but is not allowed in Thumb2 mode.
4253 if (isThumb() && Val == 32) {
4254 Error(ExLoc, "'asr #32' shift amount not allowed in Thumb mode");
4255 return MatchOperand_ParseFail;
4257 if (Val == 32) Val = 0;
4259 // Shift amount must be in [1,32]
4260 if (Val < 0 || Val > 31) {
4261 Error(ExLoc, "'lsr' shift amount must be in range [0,31]");
4262 return MatchOperand_ParseFail;
4266 Operands.push_back(ARMOperand::CreateShifterImm(isASR, Val, S, EndLoc));
4268 return MatchOperand_Success;
4271 /// parseRotImm - Parse the shifter immediate operand for SXTB/UXTB family
4272 /// of instructions. Legal values are:
4273 /// ror #n 'n' in {0, 8, 16, 24}
4274 ARMAsmParser::OperandMatchResultTy
4275 ARMAsmParser::parseRotImm(OperandVector &Operands) {
4276 const AsmToken &Tok = Parser.getTok();
4277 SMLoc S = Tok.getLoc();
4278 if (Tok.isNot(AsmToken::Identifier))
4279 return MatchOperand_NoMatch;
4280 StringRef ShiftName = Tok.getString();
4281 if (ShiftName != "ror" && ShiftName != "ROR")
4282 return MatchOperand_NoMatch;
4283 Parser.Lex(); // Eat the operator.
4285 // A '#' and a rotate amount.
4286 if (Parser.getTok().isNot(AsmToken::Hash) &&
4287 Parser.getTok().isNot(AsmToken::Dollar)) {
4288 Error(Parser.getTok().getLoc(), "'#' expected");
4289 return MatchOperand_ParseFail;
4291 Parser.Lex(); // Eat hash token.
4292 SMLoc ExLoc = Parser.getTok().getLoc();
4294 const MCExpr *ShiftAmount;
4296 if (getParser().parseExpression(ShiftAmount, EndLoc)) {
4297 Error(ExLoc, "malformed rotate expression");
4298 return MatchOperand_ParseFail;
4300 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
4302 Error(ExLoc, "rotate amount must be an immediate");
4303 return MatchOperand_ParseFail;
4306 int64_t Val = CE->getValue();
4307 // Shift amount must be in {0, 8, 16, 24} (0 is undocumented extension)
4308 // normally, zero is represented in asm by omitting the rotate operand
4310 if (Val != 8 && Val != 16 && Val != 24 && Val != 0) {
4311 Error(ExLoc, "'ror' rotate amount must be 8, 16, or 24");
4312 return MatchOperand_ParseFail;
4315 Operands.push_back(ARMOperand::CreateRotImm(Val, S, EndLoc));
4317 return MatchOperand_Success;
4320 ARMAsmParser::OperandMatchResultTy
4321 ARMAsmParser::parseBitfield(OperandVector &Operands) {
4322 SMLoc S = Parser.getTok().getLoc();
4323 // The bitfield descriptor is really two operands, the LSB and the width.
4324 if (Parser.getTok().isNot(AsmToken::Hash) &&
4325 Parser.getTok().isNot(AsmToken::Dollar)) {
4326 Error(Parser.getTok().getLoc(), "'#' expected");
4327 return MatchOperand_ParseFail;
4329 Parser.Lex(); // Eat hash token.
4331 const MCExpr *LSBExpr;
4332 SMLoc E = Parser.getTok().getLoc();
4333 if (getParser().parseExpression(LSBExpr)) {
4334 Error(E, "malformed immediate expression");
4335 return MatchOperand_ParseFail;
4337 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LSBExpr);
4339 Error(E, "'lsb' operand must be an immediate");
4340 return MatchOperand_ParseFail;
4343 int64_t LSB = CE->getValue();
4344 // The LSB must be in the range [0,31]
4345 if (LSB < 0 || LSB > 31) {
4346 Error(E, "'lsb' operand must be in the range [0,31]");
4347 return MatchOperand_ParseFail;
4349 E = Parser.getTok().getLoc();
4351 // Expect another immediate operand.
4352 if (Parser.getTok().isNot(AsmToken::Comma)) {
4353 Error(Parser.getTok().getLoc(), "too few operands");
4354 return MatchOperand_ParseFail;
4356 Parser.Lex(); // Eat hash token.
4357 if (Parser.getTok().isNot(AsmToken::Hash) &&
4358 Parser.getTok().isNot(AsmToken::Dollar)) {
4359 Error(Parser.getTok().getLoc(), "'#' expected");
4360 return MatchOperand_ParseFail;
4362 Parser.Lex(); // Eat hash token.
4364 const MCExpr *WidthExpr;
4366 if (getParser().parseExpression(WidthExpr, EndLoc)) {
4367 Error(E, "malformed immediate expression");
4368 return MatchOperand_ParseFail;
4370 CE = dyn_cast<MCConstantExpr>(WidthExpr);
4372 Error(E, "'width' operand must be an immediate");
4373 return MatchOperand_ParseFail;
4376 int64_t Width = CE->getValue();
4377 // The LSB must be in the range [1,32-lsb]
4378 if (Width < 1 || Width > 32 - LSB) {
4379 Error(E, "'width' operand must be in the range [1,32-lsb]");
4380 return MatchOperand_ParseFail;
4383 Operands.push_back(ARMOperand::CreateBitfield(LSB, Width, S, EndLoc));
4385 return MatchOperand_Success;
4388 ARMAsmParser::OperandMatchResultTy
4389 ARMAsmParser::parsePostIdxReg(OperandVector &Operands) {
4390 // Check for a post-index addressing register operand. Specifically:
4391 // postidx_reg := '+' register {, shift}
4392 // | '-' register {, shift}
4393 // | register {, shift}
4395 // This method must return MatchOperand_NoMatch without consuming any tokens
4396 // in the case where there is no match, as other alternatives take other
4398 AsmToken Tok = Parser.getTok();
4399 SMLoc S = Tok.getLoc();
4400 bool haveEaten = false;
4402 if (Tok.is(AsmToken::Plus)) {
4403 Parser.Lex(); // Eat the '+' token.
4405 } else if (Tok.is(AsmToken::Minus)) {
4406 Parser.Lex(); // Eat the '-' token.
4411 SMLoc E = Parser.getTok().getEndLoc();
4412 int Reg = tryParseRegister();
4415 return MatchOperand_NoMatch;
4416 Error(Parser.getTok().getLoc(), "register expected");
4417 return MatchOperand_ParseFail;
4420 ARM_AM::ShiftOpc ShiftTy = ARM_AM::no_shift;
4421 unsigned ShiftImm = 0;
4422 if (Parser.getTok().is(AsmToken::Comma)) {
4423 Parser.Lex(); // Eat the ','.
4424 if (parseMemRegOffsetShift(ShiftTy, ShiftImm))
4425 return MatchOperand_ParseFail;
4427 // FIXME: Only approximates end...may include intervening whitespace.
4428 E = Parser.getTok().getLoc();
4431 Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ShiftTy,
4434 return MatchOperand_Success;
4437 ARMAsmParser::OperandMatchResultTy
4438 ARMAsmParser::parseAM3Offset(OperandVector &Operands) {
4439 // Check for a post-index addressing register operand. Specifically:
4440 // am3offset := '+' register
4447 // This method must return MatchOperand_NoMatch without consuming any tokens
4448 // in the case where there is no match, as other alternatives take other
4450 AsmToken Tok = Parser.getTok();
4451 SMLoc S = Tok.getLoc();
4453 // Do immediates first, as we always parse those if we have a '#'.
4454 if (Parser.getTok().is(AsmToken::Hash) ||
4455 Parser.getTok().is(AsmToken::Dollar)) {
4456 Parser.Lex(); // Eat '#' or '$'.
4457 // Explicitly look for a '-', as we need to encode negative zero
4459 bool isNegative = Parser.getTok().is(AsmToken::Minus);
4460 const MCExpr *Offset;
4462 if (getParser().parseExpression(Offset, E))
4463 return MatchOperand_ParseFail;
4464 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
4466 Error(S, "constant expression expected");
4467 return MatchOperand_ParseFail;
4469 // Negative zero is encoded as the flag value INT32_MIN.
4470 int32_t Val = CE->getValue();
4471 if (isNegative && Val == 0)
4475 ARMOperand::CreateImm(MCConstantExpr::Create(Val, getContext()), S, E));
4477 return MatchOperand_Success;
4481 bool haveEaten = false;
4483 if (Tok.is(AsmToken::Plus)) {
4484 Parser.Lex(); // Eat the '+' token.
4486 } else if (Tok.is(AsmToken::Minus)) {
4487 Parser.Lex(); // Eat the '-' token.
4492 Tok = Parser.getTok();
4493 int Reg = tryParseRegister();
4496 return MatchOperand_NoMatch;
4497 Error(Tok.getLoc(), "register expected");
4498 return MatchOperand_ParseFail;
4501 Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ARM_AM::no_shift,
4502 0, S, Tok.getEndLoc()));
4504 return MatchOperand_Success;
4507 /// Convert parsed operands to MCInst. Needed here because this instruction
4508 /// only has two register operands, but multiplication is commutative so
4509 /// assemblers should accept both "mul rD, rN, rD" and "mul rD, rD, rN".
4510 void ARMAsmParser::cvtThumbMultiply(MCInst &Inst,
4511 const OperandVector &Operands) {
4512 ((ARMOperand &)*Operands[3]).addRegOperands(Inst, 1);
4513 ((ARMOperand &)*Operands[1]).addCCOutOperands(Inst, 1);
4514 // If we have a three-operand form, make sure to set Rn to be the operand
4515 // that isn't the same as Rd.
4517 if (Operands.size() == 6 &&
4518 ((ARMOperand &)*Operands[4]).getReg() ==
4519 ((ARMOperand &)*Operands[3]).getReg())
4521 ((ARMOperand &)*Operands[RegOp]).addRegOperands(Inst, 1);
4522 Inst.addOperand(Inst.getOperand(0));
4523 ((ARMOperand &)*Operands[2]).addCondCodeOperands(Inst, 2);
4526 void ARMAsmParser::cvtThumbBranches(MCInst &Inst,
4527 const OperandVector &Operands) {
4528 int CondOp = -1, ImmOp = -1;
4529 switch(Inst.getOpcode()) {
4531 case ARM::tBcc: CondOp = 1; ImmOp = 2; break;
4534 case ARM::t2Bcc: CondOp = 1; ImmOp = 3; break;
4536 default: llvm_unreachable("Unexpected instruction in cvtThumbBranches");
4538 // first decide whether or not the branch should be conditional
4539 // by looking at it's location relative to an IT block
4541 // inside an IT block we cannot have any conditional branches. any
4542 // such instructions needs to be converted to unconditional form
4543 switch(Inst.getOpcode()) {
4544 case ARM::tBcc: Inst.setOpcode(ARM::tB); break;
4545 case ARM::t2Bcc: Inst.setOpcode(ARM::t2B); break;
4548 // outside IT blocks we can only have unconditional branches with AL
4549 // condition code or conditional branches with non-AL condition code
4550 unsigned Cond = static_cast<ARMOperand &>(*Operands[CondOp]).getCondCode();
4551 switch(Inst.getOpcode()) {
4554 Inst.setOpcode(Cond == ARMCC::AL ? ARM::tB : ARM::tBcc);
4558 Inst.setOpcode(Cond == ARMCC::AL ? ARM::t2B : ARM::t2Bcc);
4563 // now decide on encoding size based on branch target range
4564 switch(Inst.getOpcode()) {
4565 // classify tB as either t2B or t1B based on range of immediate operand
4567 ARMOperand &op = static_cast<ARMOperand &>(*Operands[ImmOp]);
4568 if (!op.isSignedOffset<11, 1>() && isThumbTwo())
4569 Inst.setOpcode(ARM::t2B);
4572 // classify tBcc as either t2Bcc or t1Bcc based on range of immediate operand
4574 ARMOperand &op = static_cast<ARMOperand &>(*Operands[ImmOp]);
4575 if (!op.isSignedOffset<8, 1>() && isThumbTwo())
4576 Inst.setOpcode(ARM::t2Bcc);
4580 ((ARMOperand &)*Operands[ImmOp]).addImmOperands(Inst, 1);
4581 ((ARMOperand &)*Operands[CondOp]).addCondCodeOperands(Inst, 2);
4584 /// Parse an ARM memory expression, return false if successful else return true
4585 /// or an error. The first token must be a '[' when called.
4586 bool ARMAsmParser::parseMemory(OperandVector &Operands) {
4588 assert(Parser.getTok().is(AsmToken::LBrac) &&
4589 "Token is not a Left Bracket");
4590 S = Parser.getTok().getLoc();
4591 Parser.Lex(); // Eat left bracket token.
4593 const AsmToken &BaseRegTok = Parser.getTok();
4594 int BaseRegNum = tryParseRegister();
4595 if (BaseRegNum == -1)
4596 return Error(BaseRegTok.getLoc(), "register expected");
4598 // The next token must either be a comma, a colon or a closing bracket.
4599 const AsmToken &Tok = Parser.getTok();
4600 if (!Tok.is(AsmToken::Colon) && !Tok.is(AsmToken::Comma) &&
4601 !Tok.is(AsmToken::RBrac))
4602 return Error(Tok.getLoc(), "malformed memory operand");
4604 if (Tok.is(AsmToken::RBrac)) {
4605 E = Tok.getEndLoc();
4606 Parser.Lex(); // Eat right bracket token.
4608 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, nullptr, 0,
4609 ARM_AM::no_shift, 0, 0, false,
4612 // If there's a pre-indexing writeback marker, '!', just add it as a token
4613 // operand. It's rather odd, but syntactically valid.
4614 if (Parser.getTok().is(AsmToken::Exclaim)) {
4615 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4616 Parser.Lex(); // Eat the '!'.
4622 assert((Tok.is(AsmToken::Colon) || Tok.is(AsmToken::Comma)) &&
4623 "Lost colon or comma in memory operand?!");
4624 if (Tok.is(AsmToken::Comma)) {
4625 Parser.Lex(); // Eat the comma.
4628 // If we have a ':', it's an alignment specifier.
4629 if (Parser.getTok().is(AsmToken::Colon)) {
4630 Parser.Lex(); // Eat the ':'.
4631 E = Parser.getTok().getLoc();
4632 SMLoc AlignmentLoc = Tok.getLoc();
4635 if (getParser().parseExpression(Expr))
4638 // The expression has to be a constant. Memory references with relocations
4639 // don't come through here, as they use the <label> forms of the relevant
4641 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
4643 return Error (E, "constant expression expected");
4646 switch (CE->getValue()) {
4649 "alignment specifier must be 16, 32, 64, 128, or 256 bits");
4650 case 16: Align = 2; break;
4651 case 32: Align = 4; break;
4652 case 64: Align = 8; break;
4653 case 128: Align = 16; break;
4654 case 256: Align = 32; break;
4657 // Now we should have the closing ']'
4658 if (Parser.getTok().isNot(AsmToken::RBrac))
4659 return Error(Parser.getTok().getLoc(), "']' expected");
4660 E = Parser.getTok().getEndLoc();
4661 Parser.Lex(); // Eat right bracket token.
4663 // Don't worry about range checking the value here. That's handled by
4664 // the is*() predicates.
4665 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, nullptr, 0,
4666 ARM_AM::no_shift, 0, Align,
4667 false, S, E, AlignmentLoc));
4669 // If there's a pre-indexing writeback marker, '!', just add it as a token
4671 if (Parser.getTok().is(AsmToken::Exclaim)) {
4672 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4673 Parser.Lex(); // Eat the '!'.
4679 // If we have a '#', it's an immediate offset, else assume it's a register
4680 // offset. Be friendly and also accept a plain integer (without a leading
4681 // hash) for gas compatibility.
4682 if (Parser.getTok().is(AsmToken::Hash) ||
4683 Parser.getTok().is(AsmToken::Dollar) ||
4684 Parser.getTok().is(AsmToken::Integer)) {
4685 if (Parser.getTok().isNot(AsmToken::Integer))
4686 Parser.Lex(); // Eat '#' or '$'.
4687 E = Parser.getTok().getLoc();
4689 bool isNegative = getParser().getTok().is(AsmToken::Minus);
4690 const MCExpr *Offset;
4691 if (getParser().parseExpression(Offset))
4694 // The expression has to be a constant. Memory references with relocations
4695 // don't come through here, as they use the <label> forms of the relevant
4697 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
4699 return Error (E, "constant expression expected");
4701 // If the constant was #-0, represent it as INT32_MIN.
4702 int32_t Val = CE->getValue();
4703 if (isNegative && Val == 0)
4704 CE = MCConstantExpr::Create(INT32_MIN, getContext());
4706 // Now we should have the closing ']'
4707 if (Parser.getTok().isNot(AsmToken::RBrac))
4708 return Error(Parser.getTok().getLoc(), "']' expected");
4709 E = Parser.getTok().getEndLoc();
4710 Parser.Lex(); // Eat right bracket token.
4712 // Don't worry about range checking the value here. That's handled by
4713 // the is*() predicates.
4714 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, CE, 0,
4715 ARM_AM::no_shift, 0, 0,
4718 // If there's a pre-indexing writeback marker, '!', just add it as a token
4720 if (Parser.getTok().is(AsmToken::Exclaim)) {
4721 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4722 Parser.Lex(); // Eat the '!'.
4728 // The register offset is optionally preceded by a '+' or '-'
4729 bool isNegative = false;
4730 if (Parser.getTok().is(AsmToken::Minus)) {
4732 Parser.Lex(); // Eat the '-'.
4733 } else if (Parser.getTok().is(AsmToken::Plus)) {
4735 Parser.Lex(); // Eat the '+'.
4738 E = Parser.getTok().getLoc();
4739 int OffsetRegNum = tryParseRegister();
4740 if (OffsetRegNum == -1)
4741 return Error(E, "register expected");
4743 // If there's a shift operator, handle it.
4744 ARM_AM::ShiftOpc ShiftType = ARM_AM::no_shift;
4745 unsigned ShiftImm = 0;
4746 if (Parser.getTok().is(AsmToken::Comma)) {
4747 Parser.Lex(); // Eat the ','.
4748 if (parseMemRegOffsetShift(ShiftType, ShiftImm))
4752 // Now we should have the closing ']'
4753 if (Parser.getTok().isNot(AsmToken::RBrac))
4754 return Error(Parser.getTok().getLoc(), "']' expected");
4755 E = Parser.getTok().getEndLoc();
4756 Parser.Lex(); // Eat right bracket token.
4758 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, nullptr, OffsetRegNum,
4759 ShiftType, ShiftImm, 0, isNegative,
4762 // If there's a pre-indexing writeback marker, '!', just add it as a token
4764 if (Parser.getTok().is(AsmToken::Exclaim)) {
4765 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4766 Parser.Lex(); // Eat the '!'.
4772 /// parseMemRegOffsetShift - one of these two:
4773 /// ( lsl | lsr | asr | ror ) , # shift_amount
4775 /// return true if it parses a shift otherwise it returns false.
4776 bool ARMAsmParser::parseMemRegOffsetShift(ARM_AM::ShiftOpc &St,
4778 SMLoc Loc = Parser.getTok().getLoc();
4779 const AsmToken &Tok = Parser.getTok();
4780 if (Tok.isNot(AsmToken::Identifier))
4782 StringRef ShiftName = Tok.getString();
4783 if (ShiftName == "lsl" || ShiftName == "LSL" ||
4784 ShiftName == "asl" || ShiftName == "ASL")
4786 else if (ShiftName == "lsr" || ShiftName == "LSR")
4788 else if (ShiftName == "asr" || ShiftName == "ASR")
4790 else if (ShiftName == "ror" || ShiftName == "ROR")
4792 else if (ShiftName == "rrx" || ShiftName == "RRX")
4795 return Error(Loc, "illegal shift operator");
4796 Parser.Lex(); // Eat shift type token.
4798 // rrx stands alone.
4800 if (St != ARM_AM::rrx) {
4801 Loc = Parser.getTok().getLoc();
4802 // A '#' and a shift amount.
4803 const AsmToken &HashTok = Parser.getTok();
4804 if (HashTok.isNot(AsmToken::Hash) &&
4805 HashTok.isNot(AsmToken::Dollar))
4806 return Error(HashTok.getLoc(), "'#' expected");
4807 Parser.Lex(); // Eat hash token.
4810 if (getParser().parseExpression(Expr))
4812 // Range check the immediate.
4813 // lsl, ror: 0 <= imm <= 31
4814 // lsr, asr: 0 <= imm <= 32
4815 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
4817 return Error(Loc, "shift amount must be an immediate");
4818 int64_t Imm = CE->getValue();
4820 ((St == ARM_AM::lsl || St == ARM_AM::ror) && Imm > 31) ||
4821 ((St == ARM_AM::lsr || St == ARM_AM::asr) && Imm > 32))
4822 return Error(Loc, "immediate shift value out of range");
4823 // If <ShiftTy> #0, turn it into a no_shift.
4826 // For consistency, treat lsr #32 and asr #32 as having immediate value 0.
4835 /// parseFPImm - A floating point immediate expression operand.
4836 ARMAsmParser::OperandMatchResultTy
4837 ARMAsmParser::parseFPImm(OperandVector &Operands) {
4838 // Anything that can accept a floating point constant as an operand
4839 // needs to go through here, as the regular parseExpression is
4842 // This routine still creates a generic Immediate operand, containing
4843 // a bitcast of the 64-bit floating point value. The various operands
4844 // that accept floats can check whether the value is valid for them
4845 // via the standard is*() predicates.
4847 SMLoc S = Parser.getTok().getLoc();
4849 if (Parser.getTok().isNot(AsmToken::Hash) &&
4850 Parser.getTok().isNot(AsmToken::Dollar))
4851 return MatchOperand_NoMatch;
4853 // Disambiguate the VMOV forms that can accept an FP immediate.
4854 // vmov.f32 <sreg>, #imm
4855 // vmov.f64 <dreg>, #imm
4856 // vmov.f32 <dreg>, #imm @ vector f32x2
4857 // vmov.f32 <qreg>, #imm @ vector f32x4
4859 // There are also the NEON VMOV instructions which expect an
4860 // integer constant. Make sure we don't try to parse an FPImm
4862 // vmov.i{8|16|32|64} <dreg|qreg>, #imm
4863 ARMOperand &TyOp = static_cast<ARMOperand &>(*Operands[2]);
4864 bool isVmovf = TyOp.isToken() &&
4865 (TyOp.getToken() == ".f32" || TyOp.getToken() == ".f64");
4866 ARMOperand &Mnemonic = static_cast<ARMOperand &>(*Operands[0]);
4867 bool isFconst = Mnemonic.isToken() && (Mnemonic.getToken() == "fconstd" ||
4868 Mnemonic.getToken() == "fconsts");
4869 if (!(isVmovf || isFconst))
4870 return MatchOperand_NoMatch;
4872 Parser.Lex(); // Eat '#' or '$'.
4874 // Handle negation, as that still comes through as a separate token.
4875 bool isNegative = false;
4876 if (Parser.getTok().is(AsmToken::Minus)) {
4880 const AsmToken &Tok = Parser.getTok();
4881 SMLoc Loc = Tok.getLoc();
4882 if (Tok.is(AsmToken::Real) && isVmovf) {
4883 APFloat RealVal(APFloat::IEEEsingle, Tok.getString());
4884 uint64_t IntVal = RealVal.bitcastToAPInt().getZExtValue();
4885 // If we had a '-' in front, toggle the sign bit.
4886 IntVal ^= (uint64_t)isNegative << 31;
4887 Parser.Lex(); // Eat the token.
4888 Operands.push_back(ARMOperand::CreateImm(
4889 MCConstantExpr::Create(IntVal, getContext()),
4890 S, Parser.getTok().getLoc()));
4891 return MatchOperand_Success;
4893 // Also handle plain integers. Instructions which allow floating point
4894 // immediates also allow a raw encoded 8-bit value.
4895 if (Tok.is(AsmToken::Integer) && isFconst) {
4896 int64_t Val = Tok.getIntVal();
4897 Parser.Lex(); // Eat the token.
4898 if (Val > 255 || Val < 0) {
4899 Error(Loc, "encoded floating point value out of range");
4900 return MatchOperand_ParseFail;
4902 float RealVal = ARM_AM::getFPImmFloat(Val);
4903 Val = APFloat(RealVal).bitcastToAPInt().getZExtValue();
4905 Operands.push_back(ARMOperand::CreateImm(
4906 MCConstantExpr::Create(Val, getContext()), S,
4907 Parser.getTok().getLoc()));
4908 return MatchOperand_Success;
4911 Error(Loc, "invalid floating point immediate");
4912 return MatchOperand_ParseFail;
4915 /// Parse a arm instruction operand. For now this parses the operand regardless
4916 /// of the mnemonic.
4917 bool ARMAsmParser::parseOperand(OperandVector &Operands, StringRef Mnemonic) {
4920 // Check if the current operand has a custom associated parser, if so, try to
4921 // custom parse the operand, or fallback to the general approach.
4922 OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
4923 if (ResTy == MatchOperand_Success)
4925 // If there wasn't a custom match, try the generic matcher below. Otherwise,
4926 // there was a match, but an error occurred, in which case, just return that
4927 // the operand parsing failed.
4928 if (ResTy == MatchOperand_ParseFail)
4931 switch (getLexer().getKind()) {
4933 Error(Parser.getTok().getLoc(), "unexpected token in operand");
4935 case AsmToken::Identifier: {
4936 // If we've seen a branch mnemonic, the next operand must be a label. This
4937 // is true even if the label is a register name. So "br r1" means branch to
4939 bool ExpectLabel = Mnemonic == "b" || Mnemonic == "bl";
4941 if (!tryParseRegisterWithWriteBack(Operands))
4943 int Res = tryParseShiftRegister(Operands);
4944 if (Res == 0) // success
4946 else if (Res == -1) // irrecoverable error
4948 // If this is VMRS, check for the apsr_nzcv operand.
4949 if (Mnemonic == "vmrs" &&
4950 Parser.getTok().getString().equals_lower("apsr_nzcv")) {
4951 S = Parser.getTok().getLoc();
4953 Operands.push_back(ARMOperand::CreateToken("APSR_nzcv", S));
4958 // Fall though for the Identifier case that is not a register or a
4961 case AsmToken::LParen: // parenthesized expressions like (_strcmp-4)
4962 case AsmToken::Integer: // things like 1f and 2b as a branch targets
4963 case AsmToken::String: // quoted label names.
4964 case AsmToken::Dot: { // . as a branch target
4965 // This was not a register so parse other operands that start with an
4966 // identifier (like labels) as expressions and create them as immediates.
4967 const MCExpr *IdVal;
4968 S = Parser.getTok().getLoc();
4969 if (getParser().parseExpression(IdVal))
4971 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
4972 Operands.push_back(ARMOperand::CreateImm(IdVal, S, E));
4975 case AsmToken::LBrac:
4976 return parseMemory(Operands);
4977 case AsmToken::LCurly:
4978 return parseRegisterList(Operands);
4979 case AsmToken::Dollar:
4980 case AsmToken::Hash: {
4981 // #42 -> immediate.
4982 S = Parser.getTok().getLoc();
4985 if (Parser.getTok().isNot(AsmToken::Colon)) {
4986 bool isNegative = Parser.getTok().is(AsmToken::Minus);
4987 const MCExpr *ImmVal;
4988 if (getParser().parseExpression(ImmVal))
4990 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ImmVal);
4992 int32_t Val = CE->getValue();
4993 if (isNegative && Val == 0)
4994 ImmVal = MCConstantExpr::Create(INT32_MIN, getContext());
4996 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
4997 Operands.push_back(ARMOperand::CreateImm(ImmVal, S, E));
4999 // There can be a trailing '!' on operands that we want as a separate
5000 // '!' Token operand. Handle that here. For example, the compatibility
5001 // alias for 'srsdb sp!, #imm' is 'srsdb #imm!'.
5002 if (Parser.getTok().is(AsmToken::Exclaim)) {
5003 Operands.push_back(ARMOperand::CreateToken(Parser.getTok().getString(),
5004 Parser.getTok().getLoc()));
5005 Parser.Lex(); // Eat exclaim token
5009 // w/ a ':' after the '#', it's just like a plain ':'.
5012 case AsmToken::Colon: {
5013 // ":lower16:" and ":upper16:" expression prefixes
5014 // FIXME: Check it's an expression prefix,
5015 // e.g. (FOO - :lower16:BAR) isn't legal.
5016 ARMMCExpr::VariantKind RefKind;
5017 if (parsePrefix(RefKind))
5020 const MCExpr *SubExprVal;
5021 if (getParser().parseExpression(SubExprVal))
5024 const MCExpr *ExprVal = ARMMCExpr::Create(RefKind, SubExprVal,
5026 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
5027 Operands.push_back(ARMOperand::CreateImm(ExprVal, S, E));
5030 case AsmToken::Equal: {
5031 if (Mnemonic != "ldr") // only parse for ldr pseudo (e.g. ldr r0, =val)
5032 return Error(Parser.getTok().getLoc(), "unexpected token in operand");
5034 Parser.Lex(); // Eat '='
5035 const MCExpr *SubExprVal;
5036 if (getParser().parseExpression(SubExprVal))
5038 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
5040 const MCExpr *CPLoc = getTargetStreamer().addConstantPoolEntry(SubExprVal);
5041 Operands.push_back(ARMOperand::CreateImm(CPLoc, S, E));
5047 // parsePrefix - Parse ARM 16-bit relocations expression prefix, i.e.
5048 // :lower16: and :upper16:.
5049 bool ARMAsmParser::parsePrefix(ARMMCExpr::VariantKind &RefKind) {
5050 RefKind = ARMMCExpr::VK_ARM_None;
5052 // consume an optional '#' (GNU compatibility)
5053 if (getLexer().is(AsmToken::Hash))
5056 // :lower16: and :upper16: modifiers
5057 assert(getLexer().is(AsmToken::Colon) && "expected a :");
5058 Parser.Lex(); // Eat ':'
5060 if (getLexer().isNot(AsmToken::Identifier)) {
5061 Error(Parser.getTok().getLoc(), "expected prefix identifier in operand");
5065 StringRef IDVal = Parser.getTok().getIdentifier();
5066 if (IDVal == "lower16") {
5067 RefKind = ARMMCExpr::VK_ARM_LO16;
5068 } else if (IDVal == "upper16") {
5069 RefKind = ARMMCExpr::VK_ARM_HI16;
5071 Error(Parser.getTok().getLoc(), "unexpected prefix in operand");
5076 if (getLexer().isNot(AsmToken::Colon)) {
5077 Error(Parser.getTok().getLoc(), "unexpected token after prefix");
5080 Parser.Lex(); // Eat the last ':'
5084 /// \brief Given a mnemonic, split out possible predication code and carry
5085 /// setting letters to form a canonical mnemonic and flags.
5087 // FIXME: Would be nice to autogen this.
5088 // FIXME: This is a bit of a maze of special cases.
5089 StringRef ARMAsmParser::splitMnemonic(StringRef Mnemonic,
5090 unsigned &PredicationCode,
5092 unsigned &ProcessorIMod,
5093 StringRef &ITMask) {
5094 PredicationCode = ARMCC::AL;
5095 CarrySetting = false;
5098 // Ignore some mnemonics we know aren't predicated forms.
5100 // FIXME: Would be nice to autogen this.
5101 if ((Mnemonic == "movs" && isThumb()) ||
5102 Mnemonic == "teq" || Mnemonic == "vceq" || Mnemonic == "svc" ||
5103 Mnemonic == "mls" || Mnemonic == "smmls" || Mnemonic == "vcls" ||
5104 Mnemonic == "vmls" || Mnemonic == "vnmls" || Mnemonic == "vacge" ||
5105 Mnemonic == "vcge" || Mnemonic == "vclt" || Mnemonic == "vacgt" ||
5106 Mnemonic == "vaclt" || Mnemonic == "vacle" || Mnemonic == "hlt" ||
5107 Mnemonic == "vcgt" || Mnemonic == "vcle" || Mnemonic == "smlal" ||
5108 Mnemonic == "umaal" || Mnemonic == "umlal" || Mnemonic == "vabal" ||
5109 Mnemonic == "vmlal" || Mnemonic == "vpadal" || Mnemonic == "vqdmlal" ||
5110 Mnemonic == "fmuls" || Mnemonic == "vmaxnm" || Mnemonic == "vminnm" ||
5111 Mnemonic == "vcvta" || Mnemonic == "vcvtn" || Mnemonic == "vcvtp" ||
5112 Mnemonic == "vcvtm" || Mnemonic == "vrinta" || Mnemonic == "vrintn" ||
5113 Mnemonic == "vrintp" || Mnemonic == "vrintm" || Mnemonic.startswith("vsel"))
5116 // First, split out any predication code. Ignore mnemonics we know aren't
5117 // predicated but do have a carry-set and so weren't caught above.
5118 if (Mnemonic != "adcs" && Mnemonic != "bics" && Mnemonic != "movs" &&
5119 Mnemonic != "muls" && Mnemonic != "smlals" && Mnemonic != "smulls" &&
5120 Mnemonic != "umlals" && Mnemonic != "umulls" && Mnemonic != "lsls" &&
5121 Mnemonic != "sbcs" && Mnemonic != "rscs") {
5122 unsigned CC = StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2))
5123 .Case("eq", ARMCC::EQ)
5124 .Case("ne", ARMCC::NE)
5125 .Case("hs", ARMCC::HS)
5126 .Case("cs", ARMCC::HS)
5127 .Case("lo", ARMCC::LO)
5128 .Case("cc", ARMCC::LO)
5129 .Case("mi", ARMCC::MI)
5130 .Case("pl", ARMCC::PL)
5131 .Case("vs", ARMCC::VS)
5132 .Case("vc", ARMCC::VC)
5133 .Case("hi", ARMCC::HI)
5134 .Case("ls", ARMCC::LS)
5135 .Case("ge", ARMCC::GE)
5136 .Case("lt", ARMCC::LT)
5137 .Case("gt", ARMCC::GT)
5138 .Case("le", ARMCC::LE)
5139 .Case("al", ARMCC::AL)
5142 Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 2);
5143 PredicationCode = CC;
5147 // Next, determine if we have a carry setting bit. We explicitly ignore all
5148 // the instructions we know end in 's'.
5149 if (Mnemonic.endswith("s") &&
5150 !(Mnemonic == "cps" || Mnemonic == "mls" ||
5151 Mnemonic == "mrs" || Mnemonic == "smmls" || Mnemonic == "vabs" ||
5152 Mnemonic == "vcls" || Mnemonic == "vmls" || Mnemonic == "vmrs" ||
5153 Mnemonic == "vnmls" || Mnemonic == "vqabs" || Mnemonic == "vrecps" ||
5154 Mnemonic == "vrsqrts" || Mnemonic == "srs" || Mnemonic == "flds" ||
5155 Mnemonic == "fmrs" || Mnemonic == "fsqrts" || Mnemonic == "fsubs" ||
5156 Mnemonic == "fsts" || Mnemonic == "fcpys" || Mnemonic == "fdivs" ||
5157 Mnemonic == "fmuls" || Mnemonic == "fcmps" || Mnemonic == "fcmpzs" ||
5158 Mnemonic == "vfms" || Mnemonic == "vfnms" || Mnemonic == "fconsts" ||
5159 (Mnemonic == "movs" && isThumb()))) {
5160 Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 1);
5161 CarrySetting = true;
5164 // The "cps" instruction can have a interrupt mode operand which is glued into
5165 // the mnemonic. Check if this is the case, split it and parse the imod op
5166 if (Mnemonic.startswith("cps")) {
5167 // Split out any imod code.
5169 StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2, 2))
5170 .Case("ie", ARM_PROC::IE)
5171 .Case("id", ARM_PROC::ID)
5174 Mnemonic = Mnemonic.slice(0, Mnemonic.size()-2);
5175 ProcessorIMod = IMod;
5179 // The "it" instruction has the condition mask on the end of the mnemonic.
5180 if (Mnemonic.startswith("it")) {
5181 ITMask = Mnemonic.slice(2, Mnemonic.size());
5182 Mnemonic = Mnemonic.slice(0, 2);
5188 /// \brief Given a canonical mnemonic, determine if the instruction ever allows
5189 /// inclusion of carry set or predication code operands.
5191 // FIXME: It would be nice to autogen this.
5193 getMnemonicAcceptInfo(StringRef Mnemonic, StringRef FullInst,
5194 bool &CanAcceptCarrySet, bool &CanAcceptPredicationCode) {
5195 if (Mnemonic == "and" || Mnemonic == "lsl" || Mnemonic == "lsr" ||
5196 Mnemonic == "rrx" || Mnemonic == "ror" || Mnemonic == "sub" ||
5197 Mnemonic == "add" || Mnemonic == "adc" ||
5198 Mnemonic == "mul" || Mnemonic == "bic" || Mnemonic == "asr" ||
5199 Mnemonic == "orr" || Mnemonic == "mvn" ||
5200 Mnemonic == "rsb" || Mnemonic == "rsc" || Mnemonic == "orn" ||
5201 Mnemonic == "sbc" || Mnemonic == "eor" || Mnemonic == "neg" ||
5202 Mnemonic == "vfm" || Mnemonic == "vfnm" ||
5203 (!isThumb() && (Mnemonic == "smull" || Mnemonic == "mov" ||
5204 Mnemonic == "mla" || Mnemonic == "smlal" ||
5205 Mnemonic == "umlal" || Mnemonic == "umull"))) {
5206 CanAcceptCarrySet = true;
5208 CanAcceptCarrySet = false;
5210 if (Mnemonic == "bkpt" || Mnemonic == "cbnz" || Mnemonic == "setend" ||
5211 Mnemonic == "cps" || Mnemonic == "it" || Mnemonic == "cbz" ||
5212 Mnemonic == "trap" || Mnemonic == "hlt" || Mnemonic == "udf" ||
5213 Mnemonic.startswith("crc32") || Mnemonic.startswith("cps") ||
5214 Mnemonic.startswith("vsel") ||
5215 Mnemonic == "vmaxnm" || Mnemonic == "vminnm" || Mnemonic == "vcvta" ||
5216 Mnemonic == "vcvtn" || Mnemonic == "vcvtp" || Mnemonic == "vcvtm" ||
5217 Mnemonic == "vrinta" || Mnemonic == "vrintn" || Mnemonic == "vrintp" ||
5218 Mnemonic == "vrintm" || Mnemonic.startswith("aes") ||
5219 Mnemonic.startswith("sha1") || Mnemonic.startswith("sha256") ||
5220 (FullInst.startswith("vmull") && FullInst.endswith(".p64"))) {
5221 // These mnemonics are never predicable
5222 CanAcceptPredicationCode = false;
5223 } else if (!isThumb()) {
5224 // Some instructions are only predicable in Thumb mode
5225 CanAcceptPredicationCode
5226 = Mnemonic != "cdp2" && Mnemonic != "clrex" && Mnemonic != "mcr2" &&
5227 Mnemonic != "mcrr2" && Mnemonic != "mrc2" && Mnemonic != "mrrc2" &&
5228 Mnemonic != "dmb" && Mnemonic != "dsb" && Mnemonic != "isb" &&
5229 Mnemonic != "pld" && Mnemonic != "pli" && Mnemonic != "pldw" &&
5230 Mnemonic != "ldc2" && Mnemonic != "ldc2l" &&
5231 Mnemonic != "stc2" && Mnemonic != "stc2l" &&
5232 !Mnemonic.startswith("rfe") && !Mnemonic.startswith("srs");
5233 } else if (isThumbOne()) {
5235 CanAcceptPredicationCode = Mnemonic != "movs";
5237 CanAcceptPredicationCode = Mnemonic != "nop" && Mnemonic != "movs";
5239 CanAcceptPredicationCode = true;
5242 bool ARMAsmParser::shouldOmitCCOutOperand(StringRef Mnemonic,
5243 OperandVector &Operands) {
5244 // FIXME: This is all horribly hacky. We really need a better way to deal
5245 // with optional operands like this in the matcher table.
5247 // The 'mov' mnemonic is special. One variant has a cc_out operand, while
5248 // another does not. Specifically, the MOVW instruction does not. So we
5249 // special case it here and remove the defaulted (non-setting) cc_out
5250 // operand if that's the instruction we're trying to match.
5252 // We do this as post-processing of the explicit operands rather than just
5253 // conditionally adding the cc_out in the first place because we need
5254 // to check the type of the parsed immediate operand.
5255 if (Mnemonic == "mov" && Operands.size() > 4 && !isThumb() &&
5256 !static_cast<ARMOperand &>(*Operands[4]).isARMSOImm() &&
5257 static_cast<ARMOperand &>(*Operands[4]).isImm0_65535Expr() &&
5258 static_cast<ARMOperand &>(*Operands[1]).getReg() == 0)
5261 // Register-register 'add' for thumb does not have a cc_out operand
5262 // when there are only two register operands.
5263 if (isThumb() && Mnemonic == "add" && Operands.size() == 5 &&
5264 static_cast<ARMOperand &>(*Operands[3]).isReg() &&
5265 static_cast<ARMOperand &>(*Operands[4]).isReg() &&
5266 static_cast<ARMOperand &>(*Operands[1]).getReg() == 0)
5268 // Register-register 'add' for thumb does not have a cc_out operand
5269 // when it's an ADD Rdm, SP, {Rdm|#imm0_255} instruction. We do
5270 // have to check the immediate range here since Thumb2 has a variant
5271 // that can handle a different range and has a cc_out operand.
5272 if (((isThumb() && Mnemonic == "add") ||
5273 (isThumbTwo() && Mnemonic == "sub")) &&
5274 Operands.size() == 6 && static_cast<ARMOperand &>(*Operands[3]).isReg() &&
5275 static_cast<ARMOperand &>(*Operands[4]).isReg() &&
5276 static_cast<ARMOperand &>(*Operands[4]).getReg() == ARM::SP &&
5277 static_cast<ARMOperand &>(*Operands[1]).getReg() == 0 &&
5278 ((Mnemonic == "add" && static_cast<ARMOperand &>(*Operands[5]).isReg()) ||
5279 static_cast<ARMOperand &>(*Operands[5]).isImm0_1020s4()))
5281 // For Thumb2, add/sub immediate does not have a cc_out operand for the
5282 // imm0_4095 variant. That's the least-preferred variant when
5283 // selecting via the generic "add" mnemonic, so to know that we
5284 // should remove the cc_out operand, we have to explicitly check that
5285 // it's not one of the other variants. Ugh.
5286 if (isThumbTwo() && (Mnemonic == "add" || Mnemonic == "sub") &&
5287 Operands.size() == 6 && static_cast<ARMOperand &>(*Operands[3]).isReg() &&
5288 static_cast<ARMOperand &>(*Operands[4]).isReg() &&
5289 static_cast<ARMOperand &>(*Operands[5]).isImm()) {
5290 // Nest conditions rather than one big 'if' statement for readability.
5292 // If both registers are low, we're in an IT block, and the immediate is
5293 // in range, we should use encoding T1 instead, which has a cc_out.
5295 isARMLowRegister(static_cast<ARMOperand &>(*Operands[3]).getReg()) &&
5296 isARMLowRegister(static_cast<ARMOperand &>(*Operands[4]).getReg()) &&
5297 static_cast<ARMOperand &>(*Operands[5]).isImm0_7())
5299 // Check against T3. If the second register is the PC, this is an
5300 // alternate form of ADR, which uses encoding T4, so check for that too.
5301 if (static_cast<ARMOperand &>(*Operands[4]).getReg() != ARM::PC &&
5302 static_cast<ARMOperand &>(*Operands[5]).isT2SOImm())
5305 // Otherwise, we use encoding T4, which does not have a cc_out
5310 // The thumb2 multiply instruction doesn't have a CCOut register, so
5311 // if we have a "mul" mnemonic in Thumb mode, check if we'll be able to
5312 // use the 16-bit encoding or not.
5313 if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 6 &&
5314 static_cast<ARMOperand &>(*Operands[1]).getReg() == 0 &&
5315 static_cast<ARMOperand &>(*Operands[3]).isReg() &&
5316 static_cast<ARMOperand &>(*Operands[4]).isReg() &&
5317 static_cast<ARMOperand &>(*Operands[5]).isReg() &&
5318 // If the registers aren't low regs, the destination reg isn't the
5319 // same as one of the source regs, or the cc_out operand is zero
5320 // outside of an IT block, we have to use the 32-bit encoding, so
5321 // remove the cc_out operand.
5322 (!isARMLowRegister(static_cast<ARMOperand &>(*Operands[3]).getReg()) ||
5323 !isARMLowRegister(static_cast<ARMOperand &>(*Operands[4]).getReg()) ||
5324 !isARMLowRegister(static_cast<ARMOperand &>(*Operands[5]).getReg()) ||
5325 !inITBlock() || (static_cast<ARMOperand &>(*Operands[3]).getReg() !=
5326 static_cast<ARMOperand &>(*Operands[5]).getReg() &&
5327 static_cast<ARMOperand &>(*Operands[3]).getReg() !=
5328 static_cast<ARMOperand &>(*Operands[4]).getReg())))
5331 // Also check the 'mul' syntax variant that doesn't specify an explicit
5332 // destination register.
5333 if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 5 &&
5334 static_cast<ARMOperand &>(*Operands[1]).getReg() == 0 &&
5335 static_cast<ARMOperand &>(*Operands[3]).isReg() &&
5336 static_cast<ARMOperand &>(*Operands[4]).isReg() &&
5337 // If the registers aren't low regs or the cc_out operand is zero
5338 // outside of an IT block, we have to use the 32-bit encoding, so
5339 // remove the cc_out operand.
5340 (!isARMLowRegister(static_cast<ARMOperand &>(*Operands[3]).getReg()) ||
5341 !isARMLowRegister(static_cast<ARMOperand &>(*Operands[4]).getReg()) ||
5347 // Register-register 'add/sub' for thumb does not have a cc_out operand
5348 // when it's an ADD/SUB SP, #imm. Be lenient on count since there's also
5349 // the "add/sub SP, SP, #imm" version. If the follow-up operands aren't
5350 // right, this will result in better diagnostics (which operand is off)
5352 if (isThumb() && (Mnemonic == "add" || Mnemonic == "sub") &&
5353 (Operands.size() == 5 || Operands.size() == 6) &&
5354 static_cast<ARMOperand &>(*Operands[3]).isReg() &&
5355 static_cast<ARMOperand &>(*Operands[3]).getReg() == ARM::SP &&
5356 static_cast<ARMOperand &>(*Operands[1]).getReg() == 0 &&
5357 (static_cast<ARMOperand &>(*Operands[4]).isImm() ||
5358 (Operands.size() == 6 &&
5359 static_cast<ARMOperand &>(*Operands[5]).isImm())))
5365 bool ARMAsmParser::shouldOmitPredicateOperand(StringRef Mnemonic,
5366 OperandVector &Operands) {
5367 // VRINT{Z, R, X} have a predicate operand in VFP, but not in NEON
5368 unsigned RegIdx = 3;
5369 if ((Mnemonic == "vrintz" || Mnemonic == "vrintx" || Mnemonic == "vrintr") &&
5370 static_cast<ARMOperand &>(*Operands[2]).getToken() == ".f32") {
5371 if (static_cast<ARMOperand &>(*Operands[3]).isToken() &&
5372 static_cast<ARMOperand &>(*Operands[3]).getToken() == ".f32")
5375 if (static_cast<ARMOperand &>(*Operands[RegIdx]).isReg() &&
5376 (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(
5377 static_cast<ARMOperand &>(*Operands[RegIdx]).getReg()) ||
5378 ARMMCRegisterClasses[ARM::QPRRegClassID].contains(
5379 static_cast<ARMOperand &>(*Operands[RegIdx]).getReg())))
5385 static bool isDataTypeToken(StringRef Tok) {
5386 return Tok == ".8" || Tok == ".16" || Tok == ".32" || Tok == ".64" ||
5387 Tok == ".i8" || Tok == ".i16" || Tok == ".i32" || Tok == ".i64" ||
5388 Tok == ".u8" || Tok == ".u16" || Tok == ".u32" || Tok == ".u64" ||
5389 Tok == ".s8" || Tok == ".s16" || Tok == ".s32" || Tok == ".s64" ||
5390 Tok == ".p8" || Tok == ".p16" || Tok == ".f32" || Tok == ".f64" ||
5391 Tok == ".f" || Tok == ".d";
5394 // FIXME: This bit should probably be handled via an explicit match class
5395 // in the .td files that matches the suffix instead of having it be
5396 // a literal string token the way it is now.
5397 static bool doesIgnoreDataTypeSuffix(StringRef Mnemonic, StringRef DT) {
5398 return Mnemonic.startswith("vldm") || Mnemonic.startswith("vstm");
5400 static void applyMnemonicAliases(StringRef &Mnemonic, uint64_t Features,
5401 unsigned VariantID);
5403 static bool RequiresVFPRegListValidation(StringRef Inst,
5404 bool &AcceptSinglePrecisionOnly,
5405 bool &AcceptDoublePrecisionOnly) {
5406 if (Inst.size() < 7)
5409 if (Inst.startswith("fldm") || Inst.startswith("fstm")) {
5410 StringRef AddressingMode = Inst.substr(4, 2);
5411 if (AddressingMode == "ia" || AddressingMode == "db" ||
5412 AddressingMode == "ea" || AddressingMode == "fd") {
5413 AcceptSinglePrecisionOnly = Inst[6] == 's';
5414 AcceptDoublePrecisionOnly = Inst[6] == 'd' || Inst[6] == 'x';
5422 /// Parse an arm instruction mnemonic followed by its operands.
5423 bool ARMAsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
5424 SMLoc NameLoc, OperandVector &Operands) {
5425 // FIXME: Can this be done via tablegen in some fashion?
5426 bool RequireVFPRegisterListCheck;
5427 bool AcceptSinglePrecisionOnly;
5428 bool AcceptDoublePrecisionOnly;
5429 RequireVFPRegisterListCheck =
5430 RequiresVFPRegListValidation(Name, AcceptSinglePrecisionOnly,
5431 AcceptDoublePrecisionOnly);
5433 // Apply mnemonic aliases before doing anything else, as the destination
5434 // mnemonic may include suffices and we want to handle them normally.
5435 // The generic tblgen'erated code does this later, at the start of
5436 // MatchInstructionImpl(), but that's too late for aliases that include
5437 // any sort of suffix.
5438 uint64_t AvailableFeatures = getAvailableFeatures();
5439 unsigned AssemblerDialect = getParser().getAssemblerDialect();
5440 applyMnemonicAliases(Name, AvailableFeatures, AssemblerDialect);
5442 // First check for the ARM-specific .req directive.
5443 if (Parser.getTok().is(AsmToken::Identifier) &&
5444 Parser.getTok().getIdentifier() == ".req") {
5445 parseDirectiveReq(Name, NameLoc);
5446 // We always return 'error' for this, as we're done with this
5447 // statement and don't need to match the 'instruction."
5451 // Create the leading tokens for the mnemonic, split by '.' characters.
5452 size_t Start = 0, Next = Name.find('.');
5453 StringRef Mnemonic = Name.slice(Start, Next);
5455 // Split out the predication code and carry setting flag from the mnemonic.
5456 unsigned PredicationCode;
5457 unsigned ProcessorIMod;
5460 Mnemonic = splitMnemonic(Mnemonic, PredicationCode, CarrySetting,
5461 ProcessorIMod, ITMask);
5463 // In Thumb1, only the branch (B) instruction can be predicated.
5464 if (isThumbOne() && PredicationCode != ARMCC::AL && Mnemonic != "b") {
5465 Parser.eatToEndOfStatement();
5466 return Error(NameLoc, "conditional execution not supported in Thumb1");
5469 Operands.push_back(ARMOperand::CreateToken(Mnemonic, NameLoc));
5471 // Handle the IT instruction ITMask. Convert it to a bitmask. This
5472 // is the mask as it will be for the IT encoding if the conditional
5473 // encoding has a '1' as it's bit0 (i.e. 't' ==> '1'). In the case
5474 // where the conditional bit0 is zero, the instruction post-processing
5475 // will adjust the mask accordingly.
5476 if (Mnemonic == "it") {
5477 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + 2);
5478 if (ITMask.size() > 3) {
5479 Parser.eatToEndOfStatement();
5480 return Error(Loc, "too many conditions on IT instruction");
5483 for (unsigned i = ITMask.size(); i != 0; --i) {
5484 char pos = ITMask[i - 1];
5485 if (pos != 't' && pos != 'e') {
5486 Parser.eatToEndOfStatement();
5487 return Error(Loc, "illegal IT block condition mask '" + ITMask + "'");
5490 if (ITMask[i - 1] == 't')
5493 Operands.push_back(ARMOperand::CreateITMask(Mask, Loc));
5496 // FIXME: This is all a pretty gross hack. We should automatically handle
5497 // optional operands like this via tblgen.
5499 // Next, add the CCOut and ConditionCode operands, if needed.
5501 // For mnemonics which can ever incorporate a carry setting bit or predication
5502 // code, our matching model involves us always generating CCOut and
5503 // ConditionCode operands to match the mnemonic "as written" and then we let
5504 // the matcher deal with finding the right instruction or generating an
5505 // appropriate error.
5506 bool CanAcceptCarrySet, CanAcceptPredicationCode;
5507 getMnemonicAcceptInfo(Mnemonic, Name, CanAcceptCarrySet, CanAcceptPredicationCode);
5509 // If we had a carry-set on an instruction that can't do that, issue an
5511 if (!CanAcceptCarrySet && CarrySetting) {
5512 Parser.eatToEndOfStatement();
5513 return Error(NameLoc, "instruction '" + Mnemonic +
5514 "' can not set flags, but 's' suffix specified");
5516 // If we had a predication code on an instruction that can't do that, issue an
5518 if (!CanAcceptPredicationCode && PredicationCode != ARMCC::AL) {
5519 Parser.eatToEndOfStatement();
5520 return Error(NameLoc, "instruction '" + Mnemonic +
5521 "' is not predicable, but condition code specified");
5524 // Add the carry setting operand, if necessary.
5525 if (CanAcceptCarrySet) {
5526 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size());
5527 Operands.push_back(ARMOperand::CreateCCOut(CarrySetting ? ARM::CPSR : 0,
5531 // Add the predication code operand, if necessary.
5532 if (CanAcceptPredicationCode) {
5533 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size() +
5535 Operands.push_back(ARMOperand::CreateCondCode(
5536 ARMCC::CondCodes(PredicationCode), Loc));
5539 // Add the processor imod operand, if necessary.
5540 if (ProcessorIMod) {
5541 Operands.push_back(ARMOperand::CreateImm(
5542 MCConstantExpr::Create(ProcessorIMod, getContext()),
5544 } else if (Mnemonic == "cps" && isMClass()) {
5545 return Error(NameLoc, "instruction 'cps' requires effect for M-class");
5548 // Add the remaining tokens in the mnemonic.
5549 while (Next != StringRef::npos) {
5551 Next = Name.find('.', Start + 1);
5552 StringRef ExtraToken = Name.slice(Start, Next);
5554 // Some NEON instructions have an optional datatype suffix that is
5555 // completely ignored. Check for that.
5556 if (isDataTypeToken(ExtraToken) &&
5557 doesIgnoreDataTypeSuffix(Mnemonic, ExtraToken))
5560 // For for ARM mode generate an error if the .n qualifier is used.
5561 if (ExtraToken == ".n" && !isThumb()) {
5562 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Start);
5563 Parser.eatToEndOfStatement();
5564 return Error(Loc, "instruction with .n (narrow) qualifier not allowed in "
5568 // The .n qualifier is always discarded as that is what the tables
5569 // and matcher expect. In ARM mode the .w qualifier has no effect,
5570 // so discard it to avoid errors that can be caused by the matcher.
5571 if (ExtraToken != ".n" && (isThumb() || ExtraToken != ".w")) {
5572 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Start);
5573 Operands.push_back(ARMOperand::CreateToken(ExtraToken, Loc));
5577 // Read the remaining operands.
5578 if (getLexer().isNot(AsmToken::EndOfStatement)) {
5579 // Read the first operand.
5580 if (parseOperand(Operands, Mnemonic)) {
5581 Parser.eatToEndOfStatement();
5585 while (getLexer().is(AsmToken::Comma)) {
5586 Parser.Lex(); // Eat the comma.
5588 // Parse and remember the operand.
5589 if (parseOperand(Operands, Mnemonic)) {
5590 Parser.eatToEndOfStatement();
5596 if (getLexer().isNot(AsmToken::EndOfStatement)) {
5597 SMLoc Loc = getLexer().getLoc();
5598 Parser.eatToEndOfStatement();
5599 return Error(Loc, "unexpected token in argument list");
5602 Parser.Lex(); // Consume the EndOfStatement
5604 if (RequireVFPRegisterListCheck) {
5605 ARMOperand &Op = static_cast<ARMOperand &>(*Operands.back());
5606 if (AcceptSinglePrecisionOnly && !Op.isSPRRegList())
5607 return Error(Op.getStartLoc(),
5608 "VFP/Neon single precision register expected");
5609 if (AcceptDoublePrecisionOnly && !Op.isDPRRegList())
5610 return Error(Op.getStartLoc(),
5611 "VFP/Neon double precision register expected");
5614 // Some instructions, mostly Thumb, have forms for the same mnemonic that
5615 // do and don't have a cc_out optional-def operand. With some spot-checks
5616 // of the operand list, we can figure out which variant we're trying to
5617 // parse and adjust accordingly before actually matching. We shouldn't ever
5618 // try to remove a cc_out operand that was explicitly set on the the
5619 // mnemonic, of course (CarrySetting == true). Reason number #317 the
5620 // table driven matcher doesn't fit well with the ARM instruction set.
5621 if (!CarrySetting && shouldOmitCCOutOperand(Mnemonic, Operands))
5622 Operands.erase(Operands.begin() + 1);
5624 // Some instructions have the same mnemonic, but don't always
5625 // have a predicate. Distinguish them here and delete the
5626 // predicate if needed.
5627 if (shouldOmitPredicateOperand(Mnemonic, Operands))
5628 Operands.erase(Operands.begin() + 1);
5630 // ARM mode 'blx' need special handling, as the register operand version
5631 // is predicable, but the label operand version is not. So, we can't rely
5632 // on the Mnemonic based checking to correctly figure out when to put
5633 // a k_CondCode operand in the list. If we're trying to match the label
5634 // version, remove the k_CondCode operand here.
5635 if (!isThumb() && Mnemonic == "blx" && Operands.size() == 3 &&
5636 static_cast<ARMOperand &>(*Operands[2]).isImm())
5637 Operands.erase(Operands.begin() + 1);
5639 // Adjust operands of ldrexd/strexd to MCK_GPRPair.
5640 // ldrexd/strexd require even/odd GPR pair. To enforce this constraint,
5641 // a single GPRPair reg operand is used in the .td file to replace the two
5642 // GPRs. However, when parsing from asm, the two GRPs cannot be automatically
5643 // expressed as a GPRPair, so we have to manually merge them.
5644 // FIXME: We would really like to be able to tablegen'erate this.
5645 if (!isThumb() && Operands.size() > 4 &&
5646 (Mnemonic == "ldrexd" || Mnemonic == "strexd" || Mnemonic == "ldaexd" ||
5647 Mnemonic == "stlexd")) {
5648 bool isLoad = (Mnemonic == "ldrexd" || Mnemonic == "ldaexd");
5649 unsigned Idx = isLoad ? 2 : 3;
5650 ARMOperand &Op1 = static_cast<ARMOperand &>(*Operands[Idx]);
5651 ARMOperand &Op2 = static_cast<ARMOperand &>(*Operands[Idx + 1]);
5653 const MCRegisterClass& MRC = MRI->getRegClass(ARM::GPRRegClassID);
5654 // Adjust only if Op1 and Op2 are GPRs.
5655 if (Op1.isReg() && Op2.isReg() && MRC.contains(Op1.getReg()) &&
5656 MRC.contains(Op2.getReg())) {
5657 unsigned Reg1 = Op1.getReg();
5658 unsigned Reg2 = Op2.getReg();
5659 unsigned Rt = MRI->getEncodingValue(Reg1);
5660 unsigned Rt2 = MRI->getEncodingValue(Reg2);
5662 // Rt2 must be Rt + 1 and Rt must be even.
5663 if (Rt + 1 != Rt2 || (Rt & 1)) {
5664 Error(Op2.getStartLoc(), isLoad
5665 ? "destination operands must be sequential"
5666 : "source operands must be sequential");
5669 unsigned NewReg = MRI->getMatchingSuperReg(Reg1, ARM::gsub_0,
5670 &(MRI->getRegClass(ARM::GPRPairRegClassID)));
5672 ARMOperand::CreateReg(NewReg, Op1.getStartLoc(), Op2.getEndLoc());
5673 Operands.erase(Operands.begin() + Idx + 1);
5677 // If first 2 operands of a 3 operand instruction are the same
5678 // then transform to 2 operand version of the same instruction
5679 // e.g. 'adds r0, r0, #1' transforms to 'adds r0, #1'
5680 // FIXME: We would really like to be able to tablegen'erate this.
5681 if (isThumbOne() && Operands.size() == 6 &&
5682 (Mnemonic == "add" || Mnemonic == "sub" || Mnemonic == "and" ||
5683 Mnemonic == "eor" || Mnemonic == "lsl" || Mnemonic == "lsr" ||
5684 Mnemonic == "asr" || Mnemonic == "adc" || Mnemonic == "sbc" ||
5685 Mnemonic == "ror" || Mnemonic == "orr" || Mnemonic == "bic")) {
5686 ARMOperand &Op3 = static_cast<ARMOperand &>(*Operands[3]);
5687 ARMOperand &Op4 = static_cast<ARMOperand &>(*Operands[4]);
5688 ARMOperand &Op5 = static_cast<ARMOperand &>(*Operands[5]);
5690 // If both registers are the same then remove one of them from
5691 // the operand list.
5692 if (Op3.isReg() && Op4.isReg() && Op3.getReg() == Op4.getReg()) {
5693 // If 3rd operand (variable Op5) is a register and the instruction is adds/sub
5694 // then do not transform as the backend already handles this instruction
5696 if (!Op5.isReg() || !((Mnemonic == "add" && CarrySetting) || Mnemonic == "sub")) {
5697 Operands.erase(Operands.begin() + 3);
5698 if (Mnemonic == "add" && !CarrySetting) {
5699 // Special case for 'add' (not 'adds') instruction must
5700 // remove the CCOut operand as well.
5701 Operands.erase(Operands.begin() + 1);
5707 // If instruction is 'add' and first two register operands
5708 // use SP register, then remove one of the SP registers from
5710 // FIXME: We would really like to be able to tablegen'erate this.
5711 if (isThumbOne() && Operands.size() == 5 && Mnemonic == "add" && !CarrySetting) {
5712 ARMOperand &Op2 = static_cast<ARMOperand &>(*Operands[2]);
5713 ARMOperand &Op3 = static_cast<ARMOperand &>(*Operands[3]);
5714 if (Op2.isReg() && Op3.isReg() && Op2.getReg() == ARM::SP && Op3.getReg() == ARM::SP) {
5715 Operands.erase(Operands.begin() + 2);
5719 // GNU Assembler extension (compatibility)
5720 if ((Mnemonic == "ldrd" || Mnemonic == "strd")) {
5721 ARMOperand &Op2 = static_cast<ARMOperand &>(*Operands[2]);
5722 ARMOperand &Op3 = static_cast<ARMOperand &>(*Operands[3]);
5724 assert(Op2.isReg() && "expected register argument");
5726 unsigned SuperReg = MRI->getMatchingSuperReg(
5727 Op2.getReg(), ARM::gsub_0, &MRI->getRegClass(ARM::GPRPairRegClassID));
5729 assert(SuperReg && "expected register pair");
5731 unsigned PairedReg = MRI->getSubReg(SuperReg, ARM::gsub_1);
5734 Operands.begin() + 3,
5735 ARMOperand::CreateReg(PairedReg, Op2.getStartLoc(), Op2.getEndLoc()));
5739 // FIXME: As said above, this is all a pretty gross hack. This instruction
5740 // does not fit with other "subs" and tblgen.
5741 // Adjust operands of B9.3.19 SUBS PC, LR, #imm (Thumb2) system instruction
5742 // so the Mnemonic is the original name "subs" and delete the predicate
5743 // operand so it will match the table entry.
5744 if (isThumbTwo() && Mnemonic == "sub" && Operands.size() == 6 &&
5745 static_cast<ARMOperand &>(*Operands[3]).isReg() &&
5746 static_cast<ARMOperand &>(*Operands[3]).getReg() == ARM::PC &&
5747 static_cast<ARMOperand &>(*Operands[4]).isReg() &&
5748 static_cast<ARMOperand &>(*Operands[4]).getReg() == ARM::LR &&
5749 static_cast<ARMOperand &>(*Operands[5]).isImm()) {
5750 Operands.front() = ARMOperand::CreateToken(Name, NameLoc);
5751 Operands.erase(Operands.begin() + 1);
5756 // Validate context-sensitive operand constraints.
5758 // return 'true' if register list contains non-low GPR registers,
5759 // 'false' otherwise. If Reg is in the register list or is HiReg, set
5760 // 'containsReg' to true.
5761 static bool checkLowRegisterList(MCInst Inst, unsigned OpNo, unsigned Reg,
5762 unsigned HiReg, bool &containsReg) {
5763 containsReg = false;
5764 for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) {
5765 unsigned OpReg = Inst.getOperand(i).getReg();
5768 // Anything other than a low register isn't legal here.
5769 if (!isARMLowRegister(OpReg) && (!HiReg || OpReg != HiReg))
5775 // Check if the specified regisgter is in the register list of the inst,
5776 // starting at the indicated operand number.
5777 static bool listContainsReg(MCInst &Inst, unsigned OpNo, unsigned Reg) {
5778 for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) {
5779 unsigned OpReg = Inst.getOperand(i).getReg();
5786 // Return true if instruction has the interesting property of being
5787 // allowed in IT blocks, but not being predicable.
5788 static bool instIsBreakpoint(const MCInst &Inst) {
5789 return Inst.getOpcode() == ARM::tBKPT ||
5790 Inst.getOpcode() == ARM::BKPT ||
5791 Inst.getOpcode() == ARM::tHLT ||
5792 Inst.getOpcode() == ARM::HLT;
5796 // FIXME: We would really like to be able to tablegen'erate this.
5797 bool ARMAsmParser::validateInstruction(MCInst &Inst,
5798 const OperandVector &Operands) {
5799 const MCInstrDesc &MCID = MII.get(Inst.getOpcode());
5800 SMLoc Loc = Operands[0]->getStartLoc();
5802 // Check the IT block state first.
5803 // NOTE: BKPT and HLT instructions have the interesting property of being
5804 // allowed in IT blocks, but not being predicable. They just always execute.
5805 if (inITBlock() && !instIsBreakpoint(Inst)) {
5807 if (ITState.FirstCond)
5808 ITState.FirstCond = false;
5810 Bit = (ITState.Mask >> (5 - ITState.CurPosition)) & 1;
5811 // The instruction must be predicable.
5812 if (!MCID.isPredicable())
5813 return Error(Loc, "instructions in IT block must be predicable");
5814 unsigned Cond = Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm();
5815 unsigned ITCond = Bit ? ITState.Cond :
5816 ARMCC::getOppositeCondition(ITState.Cond);
5817 if (Cond != ITCond) {
5818 // Find the condition code Operand to get its SMLoc information.
5820 for (unsigned I = 1; I < Operands.size(); ++I)
5821 if (static_cast<ARMOperand &>(*Operands[I]).isCondCode())
5822 CondLoc = Operands[I]->getStartLoc();
5823 return Error(CondLoc, "incorrect condition in IT block; got '" +
5824 StringRef(ARMCondCodeToString(ARMCC::CondCodes(Cond))) +
5825 "', but expected '" +
5826 ARMCondCodeToString(ARMCC::CondCodes(ITCond)) + "'");
5828 // Check for non-'al' condition codes outside of the IT block.
5829 } else if (isThumbTwo() && MCID.isPredicable() &&
5830 Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm() !=
5831 ARMCC::AL && Inst.getOpcode() != ARM::tBcc &&
5832 Inst.getOpcode() != ARM::t2Bcc)
5833 return Error(Loc, "predicated instructions must be in IT block");
5835 const unsigned Opcode = Inst.getOpcode();
5839 case ARM::LDRD_POST: {
5840 const unsigned RtReg = Inst.getOperand(0).getReg();
5843 if (RtReg == ARM::LR)
5844 return Error(Operands[3]->getStartLoc(),
5847 const unsigned Rt = MRI->getEncodingValue(RtReg);
5848 // Rt must be even-numbered.
5850 return Error(Operands[3]->getStartLoc(),
5851 "Rt must be even-numbered");
5853 // Rt2 must be Rt + 1.
5854 const unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg());
5856 return Error(Operands[3]->getStartLoc(),
5857 "destination operands must be sequential");
5859 if (Opcode == ARM::LDRD_PRE || Opcode == ARM::LDRD_POST) {
5860 const unsigned Rn = MRI->getEncodingValue(Inst.getOperand(3).getReg());
5861 // For addressing modes with writeback, the base register needs to be
5862 // different from the destination registers.
5863 if (Rn == Rt || Rn == Rt2)
5864 return Error(Operands[3]->getStartLoc(),
5865 "base register needs to be different from destination "
5872 case ARM::t2LDRD_PRE:
5873 case ARM::t2LDRD_POST: {
5874 // Rt2 must be different from Rt.
5875 unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg());
5876 unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg());
5878 return Error(Operands[3]->getStartLoc(),
5879 "destination operands can't be identical");
5883 // Rt2 must be Rt + 1.
5884 unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg());
5885 unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg());
5887 return Error(Operands[3]->getStartLoc(),
5888 "source operands must be sequential");
5892 case ARM::STRD_POST: {
5893 // Rt2 must be Rt + 1.
5894 unsigned Rt = MRI->getEncodingValue(Inst.getOperand(1).getReg());
5895 unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(2).getReg());
5897 return Error(Operands[3]->getStartLoc(),
5898 "source operands must be sequential");
5901 case ARM::STR_PRE_IMM:
5902 case ARM::STR_PRE_REG:
5903 case ARM::STR_POST_IMM:
5904 case ARM::STR_POST_REG:
5906 case ARM::STRH_POST:
5907 case ARM::STRB_PRE_IMM:
5908 case ARM::STRB_PRE_REG:
5909 case ARM::STRB_POST_IMM:
5910 case ARM::STRB_POST_REG: {
5911 // Rt must be different from Rn.
5912 const unsigned Rt = MRI->getEncodingValue(Inst.getOperand(1).getReg());
5913 const unsigned Rn = MRI->getEncodingValue(Inst.getOperand(2).getReg());
5916 return Error(Operands[3]->getStartLoc(),
5917 "source register and base register can't be identical");
5920 case ARM::LDR_PRE_IMM:
5921 case ARM::LDR_PRE_REG:
5922 case ARM::LDR_POST_IMM:
5923 case ARM::LDR_POST_REG:
5925 case ARM::LDRH_POST:
5926 case ARM::LDRSH_PRE:
5927 case ARM::LDRSH_POST:
5928 case ARM::LDRB_PRE_IMM:
5929 case ARM::LDRB_PRE_REG:
5930 case ARM::LDRB_POST_IMM:
5931 case ARM::LDRB_POST_REG:
5932 case ARM::LDRSB_PRE:
5933 case ARM::LDRSB_POST: {
5934 // Rt must be different from Rn.
5935 const unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg());
5936 const unsigned Rn = MRI->getEncodingValue(Inst.getOperand(2).getReg());
5939 return Error(Operands[3]->getStartLoc(),
5940 "destination register and base register can't be identical");
5945 // Width must be in range [1, 32-lsb].
5946 unsigned LSB = Inst.getOperand(2).getImm();
5947 unsigned Widthm1 = Inst.getOperand(3).getImm();
5948 if (Widthm1 >= 32 - LSB)
5949 return Error(Operands[5]->getStartLoc(),
5950 "bitfield width must be in range [1,32-lsb]");
5953 // Notionally handles ARM::tLDMIA_UPD too.
5955 // If we're parsing Thumb2, the .w variant is available and handles
5956 // most cases that are normally illegal for a Thumb1 LDM instruction.
5957 // We'll make the transformation in processInstruction() if necessary.
5959 // Thumb LDM instructions are writeback iff the base register is not
5960 // in the register list.
5961 unsigned Rn = Inst.getOperand(0).getReg();
5962 bool HasWritebackToken =
5963 (static_cast<ARMOperand &>(*Operands[3]).isToken() &&
5964 static_cast<ARMOperand &>(*Operands[3]).getToken() == "!");
5965 bool ListContainsBase;
5966 if (checkLowRegisterList(Inst, 3, Rn, 0, ListContainsBase) && !isThumbTwo())
5967 return Error(Operands[3 + HasWritebackToken]->getStartLoc(),
5968 "registers must be in range r0-r7");
5969 // If we should have writeback, then there should be a '!' token.
5970 if (!ListContainsBase && !HasWritebackToken && !isThumbTwo())
5971 return Error(Operands[2]->getStartLoc(),
5972 "writeback operator '!' expected");
5973 // If we should not have writeback, there must not be a '!'. This is
5974 // true even for the 32-bit wide encodings.
5975 if (ListContainsBase && HasWritebackToken)
5976 return Error(Operands[3]->getStartLoc(),
5977 "writeback operator '!' not allowed when base register "
5978 "in register list");
5979 if (listContainsReg(Inst, 3 + HasWritebackToken, ARM::SP))
5980 return Error(Operands[3 + HasWritebackToken]->getStartLoc(),
5981 "SP not allowed in register list");
5984 case ARM::LDMIA_UPD:
5985 case ARM::LDMDB_UPD:
5986 case ARM::LDMIB_UPD:
5987 case ARM::LDMDA_UPD:
5988 // ARM variants loading and updating the same register are only officially
5989 // UNPREDICTABLE on v7 upwards. Goodness knows what they did before.
5992 if (listContainsReg(Inst, 3, Inst.getOperand(0).getReg()))
5993 return Error(Operands.back()->getStartLoc(),
5994 "writeback register not allowed in register list");
5999 case ARM::t2STMDB: {
6000 if (listContainsReg(Inst, 3, ARM::SP))
6001 return Error(Operands.back()->getStartLoc(),
6002 "SP not allowed in register list");
6005 case ARM::t2LDMIA_UPD:
6006 case ARM::t2LDMDB_UPD:
6007 case ARM::t2STMIA_UPD:
6008 case ARM::t2STMDB_UPD: {
6009 if (listContainsReg(Inst, 3, Inst.getOperand(0).getReg()))
6010 return Error(Operands.back()->getStartLoc(),
6011 "writeback register not allowed in register list");
6013 if (listContainsReg(Inst, 4, ARM::SP))
6014 return Error(Operands.back()->getStartLoc(),
6015 "SP not allowed in register list");
6018 case ARM::sysLDMIA_UPD:
6019 case ARM::sysLDMDA_UPD:
6020 case ARM::sysLDMDB_UPD:
6021 case ARM::sysLDMIB_UPD:
6022 if (!listContainsReg(Inst, 3, ARM::PC))
6023 return Error(Operands[4]->getStartLoc(),
6024 "writeback register only allowed on system LDM "
6025 "if PC in register-list");
6027 case ARM::sysSTMIA_UPD:
6028 case ARM::sysSTMDA_UPD:
6029 case ARM::sysSTMDB_UPD:
6030 case ARM::sysSTMIB_UPD:
6031 return Error(Operands[2]->getStartLoc(),
6032 "system STM cannot have writeback register");
6034 // The second source operand must be the same register as the destination
6037 // In this case, we must directly check the parsed operands because the
6038 // cvtThumbMultiply() function is written in such a way that it guarantees
6039 // this first statement is always true for the new Inst. Essentially, the
6040 // destination is unconditionally copied into the second source operand
6041 // without checking to see if it matches what we actually parsed.
6042 if (Operands.size() == 6 && (((ARMOperand &)*Operands[3]).getReg() !=
6043 ((ARMOperand &)*Operands[5]).getReg()) &&
6044 (((ARMOperand &)*Operands[3]).getReg() !=
6045 ((ARMOperand &)*Operands[4]).getReg())) {
6046 return Error(Operands[3]->getStartLoc(),
6047 "destination register must match source register");
6051 // Like for ldm/stm, push and pop have hi-reg handling version in Thumb2,
6052 // so only issue a diagnostic for thumb1. The instructions will be
6053 // switched to the t2 encodings in processInstruction() if necessary.
6055 bool ListContainsBase;
6056 if (checkLowRegisterList(Inst, 2, 0, ARM::PC, ListContainsBase) &&
6058 return Error(Operands[2]->getStartLoc(),
6059 "registers must be in range r0-r7 or pc");
6063 bool ListContainsBase;
6064 if (checkLowRegisterList(Inst, 2, 0, ARM::LR, ListContainsBase) &&
6066 return Error(Operands[2]->getStartLoc(),
6067 "registers must be in range r0-r7 or lr");
6070 case ARM::tSTMIA_UPD: {
6071 bool ListContainsBase, InvalidLowList;
6072 InvalidLowList = checkLowRegisterList(Inst, 4, Inst.getOperand(0).getReg(),
6073 0, ListContainsBase);
6074 if (InvalidLowList && !isThumbTwo())
6075 return Error(Operands[4]->getStartLoc(),
6076 "registers must be in range r0-r7");
6078 // This would be converted to a 32-bit stm, but that's not valid if the
6079 // writeback register is in the list.
6080 if (InvalidLowList && ListContainsBase)
6081 return Error(Operands[4]->getStartLoc(),
6082 "writeback operator '!' not allowed when base register "
6083 "in register list");
6084 if (listContainsReg(Inst, 4, ARM::SP) && !inITBlock())
6085 return Error(Operands.back()->getStartLoc(),
6086 "SP not allowed in register list");
6089 case ARM::tADDrSP: {
6090 // If the non-SP source operand and the destination operand are not the
6091 // same, we need thumb2 (for the wide encoding), or we have an error.
6092 if (!isThumbTwo() &&
6093 Inst.getOperand(0).getReg() != Inst.getOperand(2).getReg()) {
6094 return Error(Operands[4]->getStartLoc(),
6095 "source register must be the same as destination");
6099 // Final range checking for Thumb unconditional branch instructions.
6101 if (!(static_cast<ARMOperand &>(*Operands[2])).isSignedOffset<11, 1>())
6102 return Error(Operands[2]->getStartLoc(), "branch target out of range");
6105 int op = (Operands[2]->isImm()) ? 2 : 3;
6106 if (!static_cast<ARMOperand &>(*Operands[op]).isSignedOffset<24, 1>())
6107 return Error(Operands[op]->getStartLoc(), "branch target out of range");
6110 // Final range checking for Thumb conditional branch instructions.
6112 if (!static_cast<ARMOperand &>(*Operands[2]).isSignedOffset<8, 1>())
6113 return Error(Operands[2]->getStartLoc(), "branch target out of range");
6116 int Op = (Operands[2]->isImm()) ? 2 : 3;
6117 if (!static_cast<ARMOperand &>(*Operands[Op]).isSignedOffset<20, 1>())
6118 return Error(Operands[Op]->getStartLoc(), "branch target out of range");
6123 case ARM::t2MOVTi16:
6125 // We want to avoid misleadingly allowing something like "mov r0, <symbol>"
6126 // especially when we turn it into a movw and the expression <symbol> does
6127 // not have a :lower16: or :upper16 as part of the expression. We don't
6128 // want the behavior of silently truncating, which can be unexpected and
6129 // lead to bugs that are difficult to find since this is an easy mistake
6131 int i = (Operands[3]->isImm()) ? 3 : 4;
6132 ARMOperand &Op = static_cast<ARMOperand &>(*Operands[i]);
6133 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op.getImm());
6135 const MCExpr *E = dyn_cast<MCExpr>(Op.getImm());
6137 const ARMMCExpr *ARM16Expr = dyn_cast<ARMMCExpr>(E);
6138 if (!ARM16Expr || (ARM16Expr->getKind() != ARMMCExpr::VK_ARM_HI16 &&
6139 ARM16Expr->getKind() != ARMMCExpr::VK_ARM_LO16))
6142 "immediate expression for mov requires :lower16: or :upper16");
6150 static unsigned getRealVSTOpcode(unsigned Opc, unsigned &Spacing) {
6152 default: llvm_unreachable("unexpected opcode!");
6154 case ARM::VST1LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST1LNd8_UPD;
6155 case ARM::VST1LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST1LNd16_UPD;
6156 case ARM::VST1LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST1LNd32_UPD;
6157 case ARM::VST1LNdWB_register_Asm_8: Spacing = 1; return ARM::VST1LNd8_UPD;
6158 case ARM::VST1LNdWB_register_Asm_16: Spacing = 1; return ARM::VST1LNd16_UPD;
6159 case ARM::VST1LNdWB_register_Asm_32: Spacing = 1; return ARM::VST1LNd32_UPD;
6160 case ARM::VST1LNdAsm_8: Spacing = 1; return ARM::VST1LNd8;
6161 case ARM::VST1LNdAsm_16: Spacing = 1; return ARM::VST1LNd16;
6162 case ARM::VST1LNdAsm_32: Spacing = 1; return ARM::VST1LNd32;
6165 case ARM::VST2LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST2LNd8_UPD;
6166 case ARM::VST2LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST2LNd16_UPD;
6167 case ARM::VST2LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST2LNd32_UPD;
6168 case ARM::VST2LNqWB_fixed_Asm_16: Spacing = 2; return ARM::VST2LNq16_UPD;
6169 case ARM::VST2LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST2LNq32_UPD;
6171 case ARM::VST2LNdWB_register_Asm_8: Spacing = 1; return ARM::VST2LNd8_UPD;
6172 case ARM::VST2LNdWB_register_Asm_16: Spacing = 1; return ARM::VST2LNd16_UPD;
6173 case ARM::VST2LNdWB_register_Asm_32: Spacing = 1; return ARM::VST2LNd32_UPD;
6174 case ARM::VST2LNqWB_register_Asm_16: Spacing = 2; return ARM::VST2LNq16_UPD;
6175 case ARM::VST2LNqWB_register_Asm_32: Spacing = 2; return ARM::VST2LNq32_UPD;
6177 case ARM::VST2LNdAsm_8: Spacing = 1; return ARM::VST2LNd8;
6178 case ARM::VST2LNdAsm_16: Spacing = 1; return ARM::VST2LNd16;
6179 case ARM::VST2LNdAsm_32: Spacing = 1; return ARM::VST2LNd32;
6180 case ARM::VST2LNqAsm_16: Spacing = 2; return ARM::VST2LNq16;
6181 case ARM::VST2LNqAsm_32: Spacing = 2; return ARM::VST2LNq32;
6184 case ARM::VST3LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST3LNd8_UPD;
6185 case ARM::VST3LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST3LNd16_UPD;
6186 case ARM::VST3LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST3LNd32_UPD;
6187 case ARM::VST3LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VST3LNq16_UPD;
6188 case ARM::VST3LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST3LNq32_UPD;
6189 case ARM::VST3LNdWB_register_Asm_8: Spacing = 1; return ARM::VST3LNd8_UPD;
6190 case ARM::VST3LNdWB_register_Asm_16: Spacing = 1; return ARM::VST3LNd16_UPD;
6191 case ARM::VST3LNdWB_register_Asm_32: Spacing = 1; return ARM::VST3LNd32_UPD;
6192 case ARM::VST3LNqWB_register_Asm_16: Spacing = 2; return ARM::VST3LNq16_UPD;
6193 case ARM::VST3LNqWB_register_Asm_32: Spacing = 2; return ARM::VST3LNq32_UPD;
6194 case ARM::VST3LNdAsm_8: Spacing = 1; return ARM::VST3LNd8;
6195 case ARM::VST3LNdAsm_16: Spacing = 1; return ARM::VST3LNd16;
6196 case ARM::VST3LNdAsm_32: Spacing = 1; return ARM::VST3LNd32;
6197 case ARM::VST3LNqAsm_16: Spacing = 2; return ARM::VST3LNq16;
6198 case ARM::VST3LNqAsm_32: Spacing = 2; return ARM::VST3LNq32;
6201 case ARM::VST3dWB_fixed_Asm_8: Spacing = 1; return ARM::VST3d8_UPD;
6202 case ARM::VST3dWB_fixed_Asm_16: Spacing = 1; return ARM::VST3d16_UPD;
6203 case ARM::VST3dWB_fixed_Asm_32: Spacing = 1; return ARM::VST3d32_UPD;
6204 case ARM::VST3qWB_fixed_Asm_8: Spacing = 2; return ARM::VST3q8_UPD;
6205 case ARM::VST3qWB_fixed_Asm_16: Spacing = 2; return ARM::VST3q16_UPD;
6206 case ARM::VST3qWB_fixed_Asm_32: Spacing = 2; return ARM::VST3q32_UPD;
6207 case ARM::VST3dWB_register_Asm_8: Spacing = 1; return ARM::VST3d8_UPD;
6208 case ARM::VST3dWB_register_Asm_16: Spacing = 1; return ARM::VST3d16_UPD;
6209 case ARM::VST3dWB_register_Asm_32: Spacing = 1; return ARM::VST3d32_UPD;
6210 case ARM::VST3qWB_register_Asm_8: Spacing = 2; return ARM::VST3q8_UPD;
6211 case ARM::VST3qWB_register_Asm_16: Spacing = 2; return ARM::VST3q16_UPD;
6212 case ARM::VST3qWB_register_Asm_32: Spacing = 2; return ARM::VST3q32_UPD;
6213 case ARM::VST3dAsm_8: Spacing = 1; return ARM::VST3d8;
6214 case ARM::VST3dAsm_16: Spacing = 1; return ARM::VST3d16;
6215 case ARM::VST3dAsm_32: Spacing = 1; return ARM::VST3d32;
6216 case ARM::VST3qAsm_8: Spacing = 2; return ARM::VST3q8;
6217 case ARM::VST3qAsm_16: Spacing = 2; return ARM::VST3q16;
6218 case ARM::VST3qAsm_32: Spacing = 2; return ARM::VST3q32;
6221 case ARM::VST4LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST4LNd8_UPD;
6222 case ARM::VST4LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST4LNd16_UPD;
6223 case ARM::VST4LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST4LNd32_UPD;
6224 case ARM::VST4LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VST4LNq16_UPD;
6225 case ARM::VST4LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST4LNq32_UPD;
6226 case ARM::VST4LNdWB_register_Asm_8: Spacing = 1; return ARM::VST4LNd8_UPD;
6227 case ARM::VST4LNdWB_register_Asm_16: Spacing = 1; return ARM::VST4LNd16_UPD;
6228 case ARM::VST4LNdWB_register_Asm_32: Spacing = 1; return ARM::VST4LNd32_UPD;
6229 case ARM::VST4LNqWB_register_Asm_16: Spacing = 2; return ARM::VST4LNq16_UPD;
6230 case ARM::VST4LNqWB_register_Asm_32: Spacing = 2; return ARM::VST4LNq32_UPD;
6231 case ARM::VST4LNdAsm_8: Spacing = 1; return ARM::VST4LNd8;
6232 case ARM::VST4LNdAsm_16: Spacing = 1; return ARM::VST4LNd16;
6233 case ARM::VST4LNdAsm_32: Spacing = 1; return ARM::VST4LNd32;
6234 case ARM::VST4LNqAsm_16: Spacing = 2; return ARM::VST4LNq16;
6235 case ARM::VST4LNqAsm_32: Spacing = 2; return ARM::VST4LNq32;
6238 case ARM::VST4dWB_fixed_Asm_8: Spacing = 1; return ARM::VST4d8_UPD;
6239 case ARM::VST4dWB_fixed_Asm_16: Spacing = 1; return ARM::VST4d16_UPD;
6240 case ARM::VST4dWB_fixed_Asm_32: Spacing = 1; return ARM::VST4d32_UPD;
6241 case ARM::VST4qWB_fixed_Asm_8: Spacing = 2; return ARM::VST4q8_UPD;
6242 case ARM::VST4qWB_fixed_Asm_16: Spacing = 2; return ARM::VST4q16_UPD;
6243 case ARM::VST4qWB_fixed_Asm_32: Spacing = 2; return ARM::VST4q32_UPD;
6244 case ARM::VST4dWB_register_Asm_8: Spacing = 1; return ARM::VST4d8_UPD;
6245 case ARM::VST4dWB_register_Asm_16: Spacing = 1; return ARM::VST4d16_UPD;
6246 case ARM::VST4dWB_register_Asm_32: Spacing = 1; return ARM::VST4d32_UPD;
6247 case ARM::VST4qWB_register_Asm_8: Spacing = 2; return ARM::VST4q8_UPD;
6248 case ARM::VST4qWB_register_Asm_16: Spacing = 2; return ARM::VST4q16_UPD;
6249 case ARM::VST4qWB_register_Asm_32: Spacing = 2; return ARM::VST4q32_UPD;
6250 case ARM::VST4dAsm_8: Spacing = 1; return ARM::VST4d8;
6251 case ARM::VST4dAsm_16: Spacing = 1; return ARM::VST4d16;
6252 case ARM::VST4dAsm_32: Spacing = 1; return ARM::VST4d32;
6253 case ARM::VST4qAsm_8: Spacing = 2; return ARM::VST4q8;
6254 case ARM::VST4qAsm_16: Spacing = 2; return ARM::VST4q16;
6255 case ARM::VST4qAsm_32: Spacing = 2; return ARM::VST4q32;
6259 static unsigned getRealVLDOpcode(unsigned Opc, unsigned &Spacing) {
6261 default: llvm_unreachable("unexpected opcode!");
6263 case ARM::VLD1LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD1LNd8_UPD;
6264 case ARM::VLD1LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD1LNd16_UPD;
6265 case ARM::VLD1LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD1LNd32_UPD;
6266 case ARM::VLD1LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD1LNd8_UPD;
6267 case ARM::VLD1LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD1LNd16_UPD;
6268 case ARM::VLD1LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD1LNd32_UPD;
6269 case ARM::VLD1LNdAsm_8: Spacing = 1; return ARM::VLD1LNd8;
6270 case ARM::VLD1LNdAsm_16: Spacing = 1; return ARM::VLD1LNd16;
6271 case ARM::VLD1LNdAsm_32: Spacing = 1; return ARM::VLD1LNd32;
6274 case ARM::VLD2LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD2LNd8_UPD;
6275 case ARM::VLD2LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD2LNd16_UPD;
6276 case ARM::VLD2LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD2LNd32_UPD;
6277 case ARM::VLD2LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD2LNq16_UPD;
6278 case ARM::VLD2LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD2LNq32_UPD;
6279 case ARM::VLD2LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD2LNd8_UPD;
6280 case ARM::VLD2LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD2LNd16_UPD;
6281 case ARM::VLD2LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD2LNd32_UPD;
6282 case ARM::VLD2LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD2LNq16_UPD;
6283 case ARM::VLD2LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD2LNq32_UPD;
6284 case ARM::VLD2LNdAsm_8: Spacing = 1; return ARM::VLD2LNd8;
6285 case ARM::VLD2LNdAsm_16: Spacing = 1; return ARM::VLD2LNd16;
6286 case ARM::VLD2LNdAsm_32: Spacing = 1; return ARM::VLD2LNd32;
6287 case ARM::VLD2LNqAsm_16: Spacing = 2; return ARM::VLD2LNq16;
6288 case ARM::VLD2LNqAsm_32: Spacing = 2; return ARM::VLD2LNq32;
6291 case ARM::VLD3DUPdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3DUPd8_UPD;
6292 case ARM::VLD3DUPdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3DUPd16_UPD;
6293 case ARM::VLD3DUPdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3DUPd32_UPD;
6294 case ARM::VLD3DUPqWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3DUPq8_UPD;
6295 case ARM::VLD3DUPqWB_fixed_Asm_16: Spacing = 2; return ARM::VLD3DUPq16_UPD;
6296 case ARM::VLD3DUPqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3DUPq32_UPD;
6297 case ARM::VLD3DUPdWB_register_Asm_8: Spacing = 1; return ARM::VLD3DUPd8_UPD;
6298 case ARM::VLD3DUPdWB_register_Asm_16: Spacing = 1; return ARM::VLD3DUPd16_UPD;
6299 case ARM::VLD3DUPdWB_register_Asm_32: Spacing = 1; return ARM::VLD3DUPd32_UPD;
6300 case ARM::VLD3DUPqWB_register_Asm_8: Spacing = 2; return ARM::VLD3DUPq8_UPD;
6301 case ARM::VLD3DUPqWB_register_Asm_16: Spacing = 2; return ARM::VLD3DUPq16_UPD;
6302 case ARM::VLD3DUPqWB_register_Asm_32: Spacing = 2; return ARM::VLD3DUPq32_UPD;
6303 case ARM::VLD3DUPdAsm_8: Spacing = 1; return ARM::VLD3DUPd8;
6304 case ARM::VLD3DUPdAsm_16: Spacing = 1; return ARM::VLD3DUPd16;
6305 case ARM::VLD3DUPdAsm_32: Spacing = 1; return ARM::VLD3DUPd32;
6306 case ARM::VLD3DUPqAsm_8: Spacing = 2; return ARM::VLD3DUPq8;
6307 case ARM::VLD3DUPqAsm_16: Spacing = 2; return ARM::VLD3DUPq16;
6308 case ARM::VLD3DUPqAsm_32: Spacing = 2; return ARM::VLD3DUPq32;
6311 case ARM::VLD3LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3LNd8_UPD;
6312 case ARM::VLD3LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3LNd16_UPD;
6313 case ARM::VLD3LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3LNd32_UPD;
6314 case ARM::VLD3LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3LNq16_UPD;
6315 case ARM::VLD3LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3LNq32_UPD;
6316 case ARM::VLD3LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD3LNd8_UPD;
6317 case ARM::VLD3LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD3LNd16_UPD;
6318 case ARM::VLD3LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD3LNd32_UPD;
6319 case ARM::VLD3LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD3LNq16_UPD;
6320 case ARM::VLD3LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD3LNq32_UPD;
6321 case ARM::VLD3LNdAsm_8: Spacing = 1; return ARM::VLD3LNd8;
6322 case ARM::VLD3LNdAsm_16: Spacing = 1; return ARM::VLD3LNd16;
6323 case ARM::VLD3LNdAsm_32: Spacing = 1; return ARM::VLD3LNd32;
6324 case ARM::VLD3LNqAsm_16: Spacing = 2; return ARM::VLD3LNq16;
6325 case ARM::VLD3LNqAsm_32: Spacing = 2; return ARM::VLD3LNq32;
6328 case ARM::VLD3dWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3d8_UPD;
6329 case ARM::VLD3dWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3d16_UPD;
6330 case ARM::VLD3dWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3d32_UPD;
6331 case ARM::VLD3qWB_fixed_Asm_8: Spacing = 2; return ARM::VLD3q8_UPD;
6332 case ARM::VLD3qWB_fixed_Asm_16: Spacing = 2; return ARM::VLD3q16_UPD;
6333 case ARM::VLD3qWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3q32_UPD;
6334 case ARM::VLD3dWB_register_Asm_8: Spacing = 1; return ARM::VLD3d8_UPD;
6335 case ARM::VLD3dWB_register_Asm_16: Spacing = 1; return ARM::VLD3d16_UPD;
6336 case ARM::VLD3dWB_register_Asm_32: Spacing = 1; return ARM::VLD3d32_UPD;
6337 case ARM::VLD3qWB_register_Asm_8: Spacing = 2; return ARM::VLD3q8_UPD;
6338 case ARM::VLD3qWB_register_Asm_16: Spacing = 2; return ARM::VLD3q16_UPD;
6339 case ARM::VLD3qWB_register_Asm_32: Spacing = 2; return ARM::VLD3q32_UPD;
6340 case ARM::VLD3dAsm_8: Spacing = 1; return ARM::VLD3d8;
6341 case ARM::VLD3dAsm_16: Spacing = 1; return ARM::VLD3d16;
6342 case ARM::VLD3dAsm_32: Spacing = 1; return ARM::VLD3d32;
6343 case ARM::VLD3qAsm_8: Spacing = 2; return ARM::VLD3q8;
6344 case ARM::VLD3qAsm_16: Spacing = 2; return ARM::VLD3q16;
6345 case ARM::VLD3qAsm_32: Spacing = 2; return ARM::VLD3q32;
6348 case ARM::VLD4LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4LNd8_UPD;
6349 case ARM::VLD4LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4LNd16_UPD;
6350 case ARM::VLD4LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4LNd32_UPD;
6351 case ARM::VLD4LNqWB_fixed_Asm_16: Spacing = 2; return ARM::VLD4LNq16_UPD;
6352 case ARM::VLD4LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4LNq32_UPD;
6353 case ARM::VLD4LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD4LNd8_UPD;
6354 case ARM::VLD4LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD4LNd16_UPD;
6355 case ARM::VLD4LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD4LNd32_UPD;
6356 case ARM::VLD4LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD4LNq16_UPD;
6357 case ARM::VLD4LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD4LNq32_UPD;
6358 case ARM::VLD4LNdAsm_8: Spacing = 1; return ARM::VLD4LNd8;
6359 case ARM::VLD4LNdAsm_16: Spacing = 1; return ARM::VLD4LNd16;
6360 case ARM::VLD4LNdAsm_32: Spacing = 1; return ARM::VLD4LNd32;
6361 case ARM::VLD4LNqAsm_16: Spacing = 2; return ARM::VLD4LNq16;
6362 case ARM::VLD4LNqAsm_32: Spacing = 2; return ARM::VLD4LNq32;
6365 case ARM::VLD4DUPdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4DUPd8_UPD;
6366 case ARM::VLD4DUPdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4DUPd16_UPD;
6367 case ARM::VLD4DUPdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4DUPd32_UPD;
6368 case ARM::VLD4DUPqWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4DUPq8_UPD;
6369 case ARM::VLD4DUPqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4DUPq16_UPD;
6370 case ARM::VLD4DUPqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4DUPq32_UPD;
6371 case ARM::VLD4DUPdWB_register_Asm_8: Spacing = 1; return ARM::VLD4DUPd8_UPD;
6372 case ARM::VLD4DUPdWB_register_Asm_16: Spacing = 1; return ARM::VLD4DUPd16_UPD;
6373 case ARM::VLD4DUPdWB_register_Asm_32: Spacing = 1; return ARM::VLD4DUPd32_UPD;
6374 case ARM::VLD4DUPqWB_register_Asm_8: Spacing = 2; return ARM::VLD4DUPq8_UPD;
6375 case ARM::VLD4DUPqWB_register_Asm_16: Spacing = 2; return ARM::VLD4DUPq16_UPD;
6376 case ARM::VLD4DUPqWB_register_Asm_32: Spacing = 2; return ARM::VLD4DUPq32_UPD;
6377 case ARM::VLD4DUPdAsm_8: Spacing = 1; return ARM::VLD4DUPd8;
6378 case ARM::VLD4DUPdAsm_16: Spacing = 1; return ARM::VLD4DUPd16;
6379 case ARM::VLD4DUPdAsm_32: Spacing = 1; return ARM::VLD4DUPd32;
6380 case ARM::VLD4DUPqAsm_8: Spacing = 2; return ARM::VLD4DUPq8;
6381 case ARM::VLD4DUPqAsm_16: Spacing = 2; return ARM::VLD4DUPq16;
6382 case ARM::VLD4DUPqAsm_32: Spacing = 2; return ARM::VLD4DUPq32;
6385 case ARM::VLD4dWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4d8_UPD;
6386 case ARM::VLD4dWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4d16_UPD;
6387 case ARM::VLD4dWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4d32_UPD;
6388 case ARM::VLD4qWB_fixed_Asm_8: Spacing = 2; return ARM::VLD4q8_UPD;
6389 case ARM::VLD4qWB_fixed_Asm_16: Spacing = 2; return ARM::VLD4q16_UPD;
6390 case ARM::VLD4qWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4q32_UPD;
6391 case ARM::VLD4dWB_register_Asm_8: Spacing = 1; return ARM::VLD4d8_UPD;
6392 case ARM::VLD4dWB_register_Asm_16: Spacing = 1; return ARM::VLD4d16_UPD;
6393 case ARM::VLD4dWB_register_Asm_32: Spacing = 1; return ARM::VLD4d32_UPD;
6394 case ARM::VLD4qWB_register_Asm_8: Spacing = 2; return ARM::VLD4q8_UPD;
6395 case ARM::VLD4qWB_register_Asm_16: Spacing = 2; return ARM::VLD4q16_UPD;
6396 case ARM::VLD4qWB_register_Asm_32: Spacing = 2; return ARM::VLD4q32_UPD;
6397 case ARM::VLD4dAsm_8: Spacing = 1; return ARM::VLD4d8;
6398 case ARM::VLD4dAsm_16: Spacing = 1; return ARM::VLD4d16;
6399 case ARM::VLD4dAsm_32: Spacing = 1; return ARM::VLD4d32;
6400 case ARM::VLD4qAsm_8: Spacing = 2; return ARM::VLD4q8;
6401 case ARM::VLD4qAsm_16: Spacing = 2; return ARM::VLD4q16;
6402 case ARM::VLD4qAsm_32: Spacing = 2; return ARM::VLD4q32;
6406 bool ARMAsmParser::processInstruction(MCInst &Inst,
6407 const OperandVector &Operands) {
6408 switch (Inst.getOpcode()) {
6409 // Alias for alternate form of 'ldr{,b}t Rt, [Rn], #imm' instruction.
6410 case ARM::LDRT_POST:
6411 case ARM::LDRBT_POST: {
6412 const unsigned Opcode =
6413 (Inst.getOpcode() == ARM::LDRT_POST) ? ARM::LDRT_POST_IMM
6414 : ARM::LDRBT_POST_IMM;
6416 TmpInst.setOpcode(Opcode);
6417 TmpInst.addOperand(Inst.getOperand(0));
6418 TmpInst.addOperand(Inst.getOperand(1));
6419 TmpInst.addOperand(Inst.getOperand(1));
6420 TmpInst.addOperand(MCOperand::CreateReg(0));
6421 TmpInst.addOperand(MCOperand::CreateImm(0));
6422 TmpInst.addOperand(Inst.getOperand(2));
6423 TmpInst.addOperand(Inst.getOperand(3));
6427 // Alias for alternate form of 'str{,b}t Rt, [Rn], #imm' instruction.
6428 case ARM::STRT_POST:
6429 case ARM::STRBT_POST: {
6430 const unsigned Opcode =
6431 (Inst.getOpcode() == ARM::STRT_POST) ? ARM::STRT_POST_IMM
6432 : ARM::STRBT_POST_IMM;
6434 TmpInst.setOpcode(Opcode);
6435 TmpInst.addOperand(Inst.getOperand(1));
6436 TmpInst.addOperand(Inst.getOperand(0));
6437 TmpInst.addOperand(Inst.getOperand(1));
6438 TmpInst.addOperand(MCOperand::CreateReg(0));
6439 TmpInst.addOperand(MCOperand::CreateImm(0));
6440 TmpInst.addOperand(Inst.getOperand(2));
6441 TmpInst.addOperand(Inst.getOperand(3));
6445 // Alias for alternate form of 'ADR Rd, #imm' instruction.
6447 if (Inst.getOperand(1).getReg() != ARM::PC ||
6448 Inst.getOperand(5).getReg() != 0)
6451 TmpInst.setOpcode(ARM::ADR);
6452 TmpInst.addOperand(Inst.getOperand(0));
6453 TmpInst.addOperand(Inst.getOperand(2));
6454 TmpInst.addOperand(Inst.getOperand(3));
6455 TmpInst.addOperand(Inst.getOperand(4));
6459 // Aliases for alternate PC+imm syntax of LDR instructions.
6460 case ARM::t2LDRpcrel:
6461 // Select the narrow version if the immediate will fit.
6462 if (Inst.getOperand(1).getImm() > 0 &&
6463 Inst.getOperand(1).getImm() <= 0xff &&
6464 !(static_cast<ARMOperand &>(*Operands[2]).isToken() &&
6465 static_cast<ARMOperand &>(*Operands[2]).getToken() == ".w"))
6466 Inst.setOpcode(ARM::tLDRpci);
6468 Inst.setOpcode(ARM::t2LDRpci);
6470 case ARM::t2LDRBpcrel:
6471 Inst.setOpcode(ARM::t2LDRBpci);
6473 case ARM::t2LDRHpcrel:
6474 Inst.setOpcode(ARM::t2LDRHpci);
6476 case ARM::t2LDRSBpcrel:
6477 Inst.setOpcode(ARM::t2LDRSBpci);
6479 case ARM::t2LDRSHpcrel:
6480 Inst.setOpcode(ARM::t2LDRSHpci);
6482 // Handle NEON VST complex aliases.
6483 case ARM::VST1LNdWB_register_Asm_8:
6484 case ARM::VST1LNdWB_register_Asm_16:
6485 case ARM::VST1LNdWB_register_Asm_32: {
6487 // Shuffle the operands around so the lane index operand is in the
6490 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6491 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6492 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6493 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6494 TmpInst.addOperand(Inst.getOperand(4)); // Rm
6495 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6496 TmpInst.addOperand(Inst.getOperand(1)); // lane
6497 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6498 TmpInst.addOperand(Inst.getOperand(6));
6503 case ARM::VST2LNdWB_register_Asm_8:
6504 case ARM::VST2LNdWB_register_Asm_16:
6505 case ARM::VST2LNdWB_register_Asm_32:
6506 case ARM::VST2LNqWB_register_Asm_16:
6507 case ARM::VST2LNqWB_register_Asm_32: {
6509 // Shuffle the operands around so the lane index operand is in the
6512 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6513 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6514 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6515 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6516 TmpInst.addOperand(Inst.getOperand(4)); // Rm
6517 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6518 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6520 TmpInst.addOperand(Inst.getOperand(1)); // lane
6521 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6522 TmpInst.addOperand(Inst.getOperand(6));
6527 case ARM::VST3LNdWB_register_Asm_8:
6528 case ARM::VST3LNdWB_register_Asm_16:
6529 case ARM::VST3LNdWB_register_Asm_32:
6530 case ARM::VST3LNqWB_register_Asm_16:
6531 case ARM::VST3LNqWB_register_Asm_32: {
6533 // Shuffle the operands around so the lane index operand is in the
6536 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6537 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6538 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6539 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6540 TmpInst.addOperand(Inst.getOperand(4)); // Rm
6541 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6542 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6544 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6546 TmpInst.addOperand(Inst.getOperand(1)); // lane
6547 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6548 TmpInst.addOperand(Inst.getOperand(6));
6553 case ARM::VST4LNdWB_register_Asm_8:
6554 case ARM::VST4LNdWB_register_Asm_16:
6555 case ARM::VST4LNdWB_register_Asm_32:
6556 case ARM::VST4LNqWB_register_Asm_16:
6557 case ARM::VST4LNqWB_register_Asm_32: {
6559 // Shuffle the operands around so the lane index operand is in the
6562 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6563 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6564 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6565 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6566 TmpInst.addOperand(Inst.getOperand(4)); // Rm
6567 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6568 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6570 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6572 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6574 TmpInst.addOperand(Inst.getOperand(1)); // lane
6575 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6576 TmpInst.addOperand(Inst.getOperand(6));
6581 case ARM::VST1LNdWB_fixed_Asm_8:
6582 case ARM::VST1LNdWB_fixed_Asm_16:
6583 case ARM::VST1LNdWB_fixed_Asm_32: {
6585 // Shuffle the operands around so the lane index operand is in the
6588 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6589 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6590 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6591 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6592 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6593 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6594 TmpInst.addOperand(Inst.getOperand(1)); // lane
6595 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6596 TmpInst.addOperand(Inst.getOperand(5));
6601 case ARM::VST2LNdWB_fixed_Asm_8:
6602 case ARM::VST2LNdWB_fixed_Asm_16:
6603 case ARM::VST2LNdWB_fixed_Asm_32:
6604 case ARM::VST2LNqWB_fixed_Asm_16:
6605 case ARM::VST2LNqWB_fixed_Asm_32: {
6607 // Shuffle the operands around so the lane index operand is in the
6610 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6611 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6612 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6613 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6614 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6615 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6616 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6618 TmpInst.addOperand(Inst.getOperand(1)); // lane
6619 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6620 TmpInst.addOperand(Inst.getOperand(5));
6625 case ARM::VST3LNdWB_fixed_Asm_8:
6626 case ARM::VST3LNdWB_fixed_Asm_16:
6627 case ARM::VST3LNdWB_fixed_Asm_32:
6628 case ARM::VST3LNqWB_fixed_Asm_16:
6629 case ARM::VST3LNqWB_fixed_Asm_32: {
6631 // Shuffle the operands around so the lane index operand is in the
6634 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6635 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6636 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6637 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6638 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6639 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6640 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6642 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6644 TmpInst.addOperand(Inst.getOperand(1)); // lane
6645 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6646 TmpInst.addOperand(Inst.getOperand(5));
6651 case ARM::VST4LNdWB_fixed_Asm_8:
6652 case ARM::VST4LNdWB_fixed_Asm_16:
6653 case ARM::VST4LNdWB_fixed_Asm_32:
6654 case ARM::VST4LNqWB_fixed_Asm_16:
6655 case ARM::VST4LNqWB_fixed_Asm_32: {
6657 // Shuffle the operands around so the lane index operand is in the
6660 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6661 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6662 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6663 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6664 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6665 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6666 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6668 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6670 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6672 TmpInst.addOperand(Inst.getOperand(1)); // lane
6673 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6674 TmpInst.addOperand(Inst.getOperand(5));
6679 case ARM::VST1LNdAsm_8:
6680 case ARM::VST1LNdAsm_16:
6681 case ARM::VST1LNdAsm_32: {
6683 // Shuffle the operands around so the lane index operand is in the
6686 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6687 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6688 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6689 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6690 TmpInst.addOperand(Inst.getOperand(1)); // lane
6691 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6692 TmpInst.addOperand(Inst.getOperand(5));
6697 case ARM::VST2LNdAsm_8:
6698 case ARM::VST2LNdAsm_16:
6699 case ARM::VST2LNdAsm_32:
6700 case ARM::VST2LNqAsm_16:
6701 case ARM::VST2LNqAsm_32: {
6703 // Shuffle the operands around so the lane index operand is in the
6706 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6707 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6708 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6709 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6710 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6712 TmpInst.addOperand(Inst.getOperand(1)); // lane
6713 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6714 TmpInst.addOperand(Inst.getOperand(5));
6719 case ARM::VST3LNdAsm_8:
6720 case ARM::VST3LNdAsm_16:
6721 case ARM::VST3LNdAsm_32:
6722 case ARM::VST3LNqAsm_16:
6723 case ARM::VST3LNqAsm_32: {
6725 // Shuffle the operands around so the lane index operand is in the
6728 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6729 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6730 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6731 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6732 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6734 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6736 TmpInst.addOperand(Inst.getOperand(1)); // lane
6737 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6738 TmpInst.addOperand(Inst.getOperand(5));
6743 case ARM::VST4LNdAsm_8:
6744 case ARM::VST4LNdAsm_16:
6745 case ARM::VST4LNdAsm_32:
6746 case ARM::VST4LNqAsm_16:
6747 case ARM::VST4LNqAsm_32: {
6749 // Shuffle the operands around so the lane index operand is in the
6752 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6753 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6754 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6755 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6756 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6758 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6760 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6762 TmpInst.addOperand(Inst.getOperand(1)); // lane
6763 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6764 TmpInst.addOperand(Inst.getOperand(5));
6769 // Handle NEON VLD complex aliases.
6770 case ARM::VLD1LNdWB_register_Asm_8:
6771 case ARM::VLD1LNdWB_register_Asm_16:
6772 case ARM::VLD1LNdWB_register_Asm_32: {
6774 // Shuffle the operands around so the lane index operand is in the
6777 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6778 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6779 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6780 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6781 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6782 TmpInst.addOperand(Inst.getOperand(4)); // Rm
6783 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6784 TmpInst.addOperand(Inst.getOperand(1)); // lane
6785 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6786 TmpInst.addOperand(Inst.getOperand(6));
6791 case ARM::VLD2LNdWB_register_Asm_8:
6792 case ARM::VLD2LNdWB_register_Asm_16:
6793 case ARM::VLD2LNdWB_register_Asm_32:
6794 case ARM::VLD2LNqWB_register_Asm_16:
6795 case ARM::VLD2LNqWB_register_Asm_32: {
6797 // Shuffle the operands around so the lane index operand is in the
6800 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6801 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6802 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6804 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6805 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6806 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6807 TmpInst.addOperand(Inst.getOperand(4)); // Rm
6808 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6809 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6811 TmpInst.addOperand(Inst.getOperand(1)); // lane
6812 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6813 TmpInst.addOperand(Inst.getOperand(6));
6818 case ARM::VLD3LNdWB_register_Asm_8:
6819 case ARM::VLD3LNdWB_register_Asm_16:
6820 case ARM::VLD3LNdWB_register_Asm_32:
6821 case ARM::VLD3LNqWB_register_Asm_16:
6822 case ARM::VLD3LNqWB_register_Asm_32: {
6824 // Shuffle the operands around so the lane index operand is in the
6827 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6828 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6829 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6831 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6833 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6834 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6835 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6836 TmpInst.addOperand(Inst.getOperand(4)); // Rm
6837 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6838 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6840 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6842 TmpInst.addOperand(Inst.getOperand(1)); // lane
6843 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6844 TmpInst.addOperand(Inst.getOperand(6));
6849 case ARM::VLD4LNdWB_register_Asm_8:
6850 case ARM::VLD4LNdWB_register_Asm_16:
6851 case ARM::VLD4LNdWB_register_Asm_32:
6852 case ARM::VLD4LNqWB_register_Asm_16:
6853 case ARM::VLD4LNqWB_register_Asm_32: {
6855 // Shuffle the operands around so the lane index operand is in the
6858 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6859 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6860 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6862 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6864 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6866 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6867 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6868 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6869 TmpInst.addOperand(Inst.getOperand(4)); // Rm
6870 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6871 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6873 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6875 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6877 TmpInst.addOperand(Inst.getOperand(1)); // lane
6878 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6879 TmpInst.addOperand(Inst.getOperand(6));
6884 case ARM::VLD1LNdWB_fixed_Asm_8:
6885 case ARM::VLD1LNdWB_fixed_Asm_16:
6886 case ARM::VLD1LNdWB_fixed_Asm_32: {
6888 // Shuffle the operands around so the lane index operand is in the
6891 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6892 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6893 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6894 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6895 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6896 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6897 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6898 TmpInst.addOperand(Inst.getOperand(1)); // lane
6899 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6900 TmpInst.addOperand(Inst.getOperand(5));
6905 case ARM::VLD2LNdWB_fixed_Asm_8:
6906 case ARM::VLD2LNdWB_fixed_Asm_16:
6907 case ARM::VLD2LNdWB_fixed_Asm_32:
6908 case ARM::VLD2LNqWB_fixed_Asm_16:
6909 case ARM::VLD2LNqWB_fixed_Asm_32: {
6911 // Shuffle the operands around so the lane index operand is in the
6914 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6915 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6916 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6918 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6919 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6920 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6921 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6922 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6923 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6925 TmpInst.addOperand(Inst.getOperand(1)); // lane
6926 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6927 TmpInst.addOperand(Inst.getOperand(5));
6932 case ARM::VLD3LNdWB_fixed_Asm_8:
6933 case ARM::VLD3LNdWB_fixed_Asm_16:
6934 case ARM::VLD3LNdWB_fixed_Asm_32:
6935 case ARM::VLD3LNqWB_fixed_Asm_16:
6936 case ARM::VLD3LNqWB_fixed_Asm_32: {
6938 // Shuffle the operands around so the lane index operand is in the
6941 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6942 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6943 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6945 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6947 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6948 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6949 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6950 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6951 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6952 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6954 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6956 TmpInst.addOperand(Inst.getOperand(1)); // lane
6957 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6958 TmpInst.addOperand(Inst.getOperand(5));
6963 case ARM::VLD4LNdWB_fixed_Asm_8:
6964 case ARM::VLD4LNdWB_fixed_Asm_16:
6965 case ARM::VLD4LNdWB_fixed_Asm_32:
6966 case ARM::VLD4LNqWB_fixed_Asm_16:
6967 case ARM::VLD4LNqWB_fixed_Asm_32: {
6969 // Shuffle the operands around so the lane index operand is in the
6972 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6973 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6974 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6976 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6978 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6980 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6981 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6982 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6983 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6984 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6985 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6987 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6989 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6991 TmpInst.addOperand(Inst.getOperand(1)); // lane
6992 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6993 TmpInst.addOperand(Inst.getOperand(5));
6998 case ARM::VLD1LNdAsm_8:
6999 case ARM::VLD1LNdAsm_16:
7000 case ARM::VLD1LNdAsm_32: {
7002 // Shuffle the operands around so the lane index operand is in the
7005 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7006 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7007 TmpInst.addOperand(Inst.getOperand(2)); // Rn
7008 TmpInst.addOperand(Inst.getOperand(3)); // alignment
7009 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
7010 TmpInst.addOperand(Inst.getOperand(1)); // lane
7011 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7012 TmpInst.addOperand(Inst.getOperand(5));
7017 case ARM::VLD2LNdAsm_8:
7018 case ARM::VLD2LNdAsm_16:
7019 case ARM::VLD2LNdAsm_32:
7020 case ARM::VLD2LNqAsm_16:
7021 case ARM::VLD2LNqAsm_32: {
7023 // Shuffle the operands around so the lane index operand is in the
7026 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7027 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7028 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7030 TmpInst.addOperand(Inst.getOperand(2)); // Rn
7031 TmpInst.addOperand(Inst.getOperand(3)); // alignment
7032 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
7033 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7035 TmpInst.addOperand(Inst.getOperand(1)); // lane
7036 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7037 TmpInst.addOperand(Inst.getOperand(5));
7042 case ARM::VLD3LNdAsm_8:
7043 case ARM::VLD3LNdAsm_16:
7044 case ARM::VLD3LNdAsm_32:
7045 case ARM::VLD3LNqAsm_16:
7046 case ARM::VLD3LNqAsm_32: {
7048 // Shuffle the operands around so the lane index operand is in the
7051 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7052 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7053 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7055 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7057 TmpInst.addOperand(Inst.getOperand(2)); // Rn
7058 TmpInst.addOperand(Inst.getOperand(3)); // alignment
7059 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
7060 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7062 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7064 TmpInst.addOperand(Inst.getOperand(1)); // lane
7065 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7066 TmpInst.addOperand(Inst.getOperand(5));
7071 case ARM::VLD4LNdAsm_8:
7072 case ARM::VLD4LNdAsm_16:
7073 case ARM::VLD4LNdAsm_32:
7074 case ARM::VLD4LNqAsm_16:
7075 case ARM::VLD4LNqAsm_32: {
7077 // Shuffle the operands around so the lane index operand is in the
7080 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7081 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7082 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7084 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7086 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7088 TmpInst.addOperand(Inst.getOperand(2)); // Rn
7089 TmpInst.addOperand(Inst.getOperand(3)); // alignment
7090 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
7091 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7093 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7095 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7097 TmpInst.addOperand(Inst.getOperand(1)); // lane
7098 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7099 TmpInst.addOperand(Inst.getOperand(5));
7104 // VLD3DUP single 3-element structure to all lanes instructions.
7105 case ARM::VLD3DUPdAsm_8:
7106 case ARM::VLD3DUPdAsm_16:
7107 case ARM::VLD3DUPdAsm_32:
7108 case ARM::VLD3DUPqAsm_8:
7109 case ARM::VLD3DUPqAsm_16:
7110 case ARM::VLD3DUPqAsm_32: {
7113 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7114 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7115 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7117 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7119 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7120 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7121 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7122 TmpInst.addOperand(Inst.getOperand(4));
7127 case ARM::VLD3DUPdWB_fixed_Asm_8:
7128 case ARM::VLD3DUPdWB_fixed_Asm_16:
7129 case ARM::VLD3DUPdWB_fixed_Asm_32:
7130 case ARM::VLD3DUPqWB_fixed_Asm_8:
7131 case ARM::VLD3DUPqWB_fixed_Asm_16:
7132 case ARM::VLD3DUPqWB_fixed_Asm_32: {
7135 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7136 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7137 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7139 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7141 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7142 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7143 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7144 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
7145 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7146 TmpInst.addOperand(Inst.getOperand(4));
7151 case ARM::VLD3DUPdWB_register_Asm_8:
7152 case ARM::VLD3DUPdWB_register_Asm_16:
7153 case ARM::VLD3DUPdWB_register_Asm_32:
7154 case ARM::VLD3DUPqWB_register_Asm_8:
7155 case ARM::VLD3DUPqWB_register_Asm_16:
7156 case ARM::VLD3DUPqWB_register_Asm_32: {
7159 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7160 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7161 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7163 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7165 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7166 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7167 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7168 TmpInst.addOperand(Inst.getOperand(3)); // Rm
7169 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7170 TmpInst.addOperand(Inst.getOperand(5));
7175 // VLD3 multiple 3-element structure instructions.
7176 case ARM::VLD3dAsm_8:
7177 case ARM::VLD3dAsm_16:
7178 case ARM::VLD3dAsm_32:
7179 case ARM::VLD3qAsm_8:
7180 case ARM::VLD3qAsm_16:
7181 case ARM::VLD3qAsm_32: {
7184 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7185 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7186 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7188 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7190 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7191 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7192 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7193 TmpInst.addOperand(Inst.getOperand(4));
7198 case ARM::VLD3dWB_fixed_Asm_8:
7199 case ARM::VLD3dWB_fixed_Asm_16:
7200 case ARM::VLD3dWB_fixed_Asm_32:
7201 case ARM::VLD3qWB_fixed_Asm_8:
7202 case ARM::VLD3qWB_fixed_Asm_16:
7203 case ARM::VLD3qWB_fixed_Asm_32: {
7206 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7207 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7208 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7210 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7212 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7213 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7214 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7215 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
7216 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7217 TmpInst.addOperand(Inst.getOperand(4));
7222 case ARM::VLD3dWB_register_Asm_8:
7223 case ARM::VLD3dWB_register_Asm_16:
7224 case ARM::VLD3dWB_register_Asm_32:
7225 case ARM::VLD3qWB_register_Asm_8:
7226 case ARM::VLD3qWB_register_Asm_16:
7227 case ARM::VLD3qWB_register_Asm_32: {
7230 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7231 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7232 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7234 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7236 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7237 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7238 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7239 TmpInst.addOperand(Inst.getOperand(3)); // Rm
7240 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7241 TmpInst.addOperand(Inst.getOperand(5));
7246 // VLD4DUP single 3-element structure to all lanes instructions.
7247 case ARM::VLD4DUPdAsm_8:
7248 case ARM::VLD4DUPdAsm_16:
7249 case ARM::VLD4DUPdAsm_32:
7250 case ARM::VLD4DUPqAsm_8:
7251 case ARM::VLD4DUPqAsm_16:
7252 case ARM::VLD4DUPqAsm_32: {
7255 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7256 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7257 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7259 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7261 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7263 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7264 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7265 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7266 TmpInst.addOperand(Inst.getOperand(4));
7271 case ARM::VLD4DUPdWB_fixed_Asm_8:
7272 case ARM::VLD4DUPdWB_fixed_Asm_16:
7273 case ARM::VLD4DUPdWB_fixed_Asm_32:
7274 case ARM::VLD4DUPqWB_fixed_Asm_8:
7275 case ARM::VLD4DUPqWB_fixed_Asm_16:
7276 case ARM::VLD4DUPqWB_fixed_Asm_32: {
7279 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7280 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7281 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7283 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7285 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7287 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7288 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7289 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7290 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
7291 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7292 TmpInst.addOperand(Inst.getOperand(4));
7297 case ARM::VLD4DUPdWB_register_Asm_8:
7298 case ARM::VLD4DUPdWB_register_Asm_16:
7299 case ARM::VLD4DUPdWB_register_Asm_32:
7300 case ARM::VLD4DUPqWB_register_Asm_8:
7301 case ARM::VLD4DUPqWB_register_Asm_16:
7302 case ARM::VLD4DUPqWB_register_Asm_32: {
7305 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7306 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7307 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7309 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7311 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7313 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7314 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7315 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7316 TmpInst.addOperand(Inst.getOperand(3)); // Rm
7317 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7318 TmpInst.addOperand(Inst.getOperand(5));
7323 // VLD4 multiple 4-element structure instructions.
7324 case ARM::VLD4dAsm_8:
7325 case ARM::VLD4dAsm_16:
7326 case ARM::VLD4dAsm_32:
7327 case ARM::VLD4qAsm_8:
7328 case ARM::VLD4qAsm_16:
7329 case ARM::VLD4qAsm_32: {
7332 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7333 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7334 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7336 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7338 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7340 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7341 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7342 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7343 TmpInst.addOperand(Inst.getOperand(4));
7348 case ARM::VLD4dWB_fixed_Asm_8:
7349 case ARM::VLD4dWB_fixed_Asm_16:
7350 case ARM::VLD4dWB_fixed_Asm_32:
7351 case ARM::VLD4qWB_fixed_Asm_8:
7352 case ARM::VLD4qWB_fixed_Asm_16:
7353 case ARM::VLD4qWB_fixed_Asm_32: {
7356 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7357 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7358 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7360 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7362 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7364 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7365 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7366 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7367 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
7368 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7369 TmpInst.addOperand(Inst.getOperand(4));
7374 case ARM::VLD4dWB_register_Asm_8:
7375 case ARM::VLD4dWB_register_Asm_16:
7376 case ARM::VLD4dWB_register_Asm_32:
7377 case ARM::VLD4qWB_register_Asm_8:
7378 case ARM::VLD4qWB_register_Asm_16:
7379 case ARM::VLD4qWB_register_Asm_32: {
7382 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7383 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7384 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7386 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7388 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7390 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7391 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7392 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7393 TmpInst.addOperand(Inst.getOperand(3)); // Rm
7394 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7395 TmpInst.addOperand(Inst.getOperand(5));
7400 // VST3 multiple 3-element structure instructions.
7401 case ARM::VST3dAsm_8:
7402 case ARM::VST3dAsm_16:
7403 case ARM::VST3dAsm_32:
7404 case ARM::VST3qAsm_8:
7405 case ARM::VST3qAsm_16:
7406 case ARM::VST3qAsm_32: {
7409 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7410 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7411 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7412 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7413 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7415 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7417 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7418 TmpInst.addOperand(Inst.getOperand(4));
7423 case ARM::VST3dWB_fixed_Asm_8:
7424 case ARM::VST3dWB_fixed_Asm_16:
7425 case ARM::VST3dWB_fixed_Asm_32:
7426 case ARM::VST3qWB_fixed_Asm_8:
7427 case ARM::VST3qWB_fixed_Asm_16:
7428 case ARM::VST3qWB_fixed_Asm_32: {
7431 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7432 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7433 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7434 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7435 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
7436 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7437 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7439 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7441 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7442 TmpInst.addOperand(Inst.getOperand(4));
7447 case ARM::VST3dWB_register_Asm_8:
7448 case ARM::VST3dWB_register_Asm_16:
7449 case ARM::VST3dWB_register_Asm_32:
7450 case ARM::VST3qWB_register_Asm_8:
7451 case ARM::VST3qWB_register_Asm_16:
7452 case ARM::VST3qWB_register_Asm_32: {
7455 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7456 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7457 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7458 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7459 TmpInst.addOperand(Inst.getOperand(3)); // Rm
7460 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7461 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7463 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7465 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7466 TmpInst.addOperand(Inst.getOperand(5));
7471 // VST4 multiple 3-element structure instructions.
7472 case ARM::VST4dAsm_8:
7473 case ARM::VST4dAsm_16:
7474 case ARM::VST4dAsm_32:
7475 case ARM::VST4qAsm_8:
7476 case ARM::VST4qAsm_16:
7477 case ARM::VST4qAsm_32: {
7480 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7481 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7482 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7483 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7484 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7486 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7488 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7490 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7491 TmpInst.addOperand(Inst.getOperand(4));
7496 case ARM::VST4dWB_fixed_Asm_8:
7497 case ARM::VST4dWB_fixed_Asm_16:
7498 case ARM::VST4dWB_fixed_Asm_32:
7499 case ARM::VST4qWB_fixed_Asm_8:
7500 case ARM::VST4qWB_fixed_Asm_16:
7501 case ARM::VST4qWB_fixed_Asm_32: {
7504 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7505 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7506 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7507 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7508 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
7509 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7510 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7512 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7514 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7516 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7517 TmpInst.addOperand(Inst.getOperand(4));
7522 case ARM::VST4dWB_register_Asm_8:
7523 case ARM::VST4dWB_register_Asm_16:
7524 case ARM::VST4dWB_register_Asm_32:
7525 case ARM::VST4qWB_register_Asm_8:
7526 case ARM::VST4qWB_register_Asm_16:
7527 case ARM::VST4qWB_register_Asm_32: {
7530 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7531 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7532 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7533 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7534 TmpInst.addOperand(Inst.getOperand(3)); // Rm
7535 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7536 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7538 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7540 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7542 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7543 TmpInst.addOperand(Inst.getOperand(5));
7548 // Handle encoding choice for the shift-immediate instructions.
7551 case ARM::t2ASRri: {
7552 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7553 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
7554 Inst.getOperand(5).getReg() == (inITBlock() ? 0 : ARM::CPSR) &&
7555 !(static_cast<ARMOperand &>(*Operands[3]).isToken() &&
7556 static_cast<ARMOperand &>(*Operands[3]).getToken() == ".w")) {
7558 switch (Inst.getOpcode()) {
7559 default: llvm_unreachable("unexpected opcode");
7560 case ARM::t2LSLri: NewOpc = ARM::tLSLri; break;
7561 case ARM::t2LSRri: NewOpc = ARM::tLSRri; break;
7562 case ARM::t2ASRri: NewOpc = ARM::tASRri; break;
7564 // The Thumb1 operands aren't in the same order. Awesome, eh?
7566 TmpInst.setOpcode(NewOpc);
7567 TmpInst.addOperand(Inst.getOperand(0));
7568 TmpInst.addOperand(Inst.getOperand(5));
7569 TmpInst.addOperand(Inst.getOperand(1));
7570 TmpInst.addOperand(Inst.getOperand(2));
7571 TmpInst.addOperand(Inst.getOperand(3));
7572 TmpInst.addOperand(Inst.getOperand(4));
7579 // Handle the Thumb2 mode MOV complex aliases.
7581 case ARM::t2MOVSsr: {
7582 // Which instruction to expand to depends on the CCOut operand and
7583 // whether we're in an IT block if the register operands are low
7585 bool isNarrow = false;
7586 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7587 isARMLowRegister(Inst.getOperand(1).getReg()) &&
7588 isARMLowRegister(Inst.getOperand(2).getReg()) &&
7589 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
7590 inITBlock() == (Inst.getOpcode() == ARM::t2MOVsr))
7594 switch(ARM_AM::getSORegShOp(Inst.getOperand(3).getImm())) {
7595 default: llvm_unreachable("unexpected opcode!");
7596 case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRrr : ARM::t2ASRrr; break;
7597 case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRrr : ARM::t2LSRrr; break;
7598 case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLrr : ARM::t2LSLrr; break;
7599 case ARM_AM::ror: newOpc = isNarrow ? ARM::tROR : ARM::t2RORrr; break;
7601 TmpInst.setOpcode(newOpc);
7602 TmpInst.addOperand(Inst.getOperand(0)); // Rd
7604 TmpInst.addOperand(MCOperand::CreateReg(
7605 Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0));
7606 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7607 TmpInst.addOperand(Inst.getOperand(2)); // Rm
7608 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7609 TmpInst.addOperand(Inst.getOperand(5));
7611 TmpInst.addOperand(MCOperand::CreateReg(
7612 Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0));
7617 case ARM::t2MOVSsi: {
7618 // Which instruction to expand to depends on the CCOut operand and
7619 // whether we're in an IT block if the register operands are low
7621 bool isNarrow = false;
7622 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7623 isARMLowRegister(Inst.getOperand(1).getReg()) &&
7624 inITBlock() == (Inst.getOpcode() == ARM::t2MOVsi))
7628 switch(ARM_AM::getSORegShOp(Inst.getOperand(2).getImm())) {
7629 default: llvm_unreachable("unexpected opcode!");
7630 case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRri : ARM::t2ASRri; break;
7631 case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRri : ARM::t2LSRri; break;
7632 case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLri : ARM::t2LSLri; break;
7633 case ARM_AM::ror: newOpc = ARM::t2RORri; isNarrow = false; break;
7634 case ARM_AM::rrx: isNarrow = false; newOpc = ARM::t2RRX; break;
7636 unsigned Amount = ARM_AM::getSORegOffset(Inst.getOperand(2).getImm());
7637 if (Amount == 32) Amount = 0;
7638 TmpInst.setOpcode(newOpc);
7639 TmpInst.addOperand(Inst.getOperand(0)); // Rd
7641 TmpInst.addOperand(MCOperand::CreateReg(
7642 Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0));
7643 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7644 if (newOpc != ARM::t2RRX)
7645 TmpInst.addOperand(MCOperand::CreateImm(Amount));
7646 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7647 TmpInst.addOperand(Inst.getOperand(4));
7649 TmpInst.addOperand(MCOperand::CreateReg(
7650 Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0));
7654 // Handle the ARM mode MOV complex aliases.
7659 ARM_AM::ShiftOpc ShiftTy;
7660 switch(Inst.getOpcode()) {
7661 default: llvm_unreachable("unexpected opcode!");
7662 case ARM::ASRr: ShiftTy = ARM_AM::asr; break;
7663 case ARM::LSRr: ShiftTy = ARM_AM::lsr; break;
7664 case ARM::LSLr: ShiftTy = ARM_AM::lsl; break;
7665 case ARM::RORr: ShiftTy = ARM_AM::ror; break;
7667 unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, 0);
7669 TmpInst.setOpcode(ARM::MOVsr);
7670 TmpInst.addOperand(Inst.getOperand(0)); // Rd
7671 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7672 TmpInst.addOperand(Inst.getOperand(2)); // Rm
7673 TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty
7674 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7675 TmpInst.addOperand(Inst.getOperand(4));
7676 TmpInst.addOperand(Inst.getOperand(5)); // cc_out
7684 ARM_AM::ShiftOpc ShiftTy;
7685 switch(Inst.getOpcode()) {
7686 default: llvm_unreachable("unexpected opcode!");
7687 case ARM::ASRi: ShiftTy = ARM_AM::asr; break;
7688 case ARM::LSRi: ShiftTy = ARM_AM::lsr; break;
7689 case ARM::LSLi: ShiftTy = ARM_AM::lsl; break;
7690 case ARM::RORi: ShiftTy = ARM_AM::ror; break;
7692 // A shift by zero is a plain MOVr, not a MOVsi.
7693 unsigned Amt = Inst.getOperand(2).getImm();
7694 unsigned Opc = Amt == 0 ? ARM::MOVr : ARM::MOVsi;
7695 // A shift by 32 should be encoded as 0 when permitted
7696 if (Amt == 32 && (ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr))
7698 unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, Amt);
7700 TmpInst.setOpcode(Opc);
7701 TmpInst.addOperand(Inst.getOperand(0)); // Rd
7702 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7703 if (Opc == ARM::MOVsi)
7704 TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty
7705 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7706 TmpInst.addOperand(Inst.getOperand(4));
7707 TmpInst.addOperand(Inst.getOperand(5)); // cc_out
7712 unsigned Shifter = ARM_AM::getSORegOpc(ARM_AM::rrx, 0);
7714 TmpInst.setOpcode(ARM::MOVsi);
7715 TmpInst.addOperand(Inst.getOperand(0)); // Rd
7716 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7717 TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty
7718 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
7719 TmpInst.addOperand(Inst.getOperand(3));
7720 TmpInst.addOperand(Inst.getOperand(4)); // cc_out
7724 case ARM::t2LDMIA_UPD: {
7725 // If this is a load of a single register, then we should use
7726 // a post-indexed LDR instruction instead, per the ARM ARM.
7727 if (Inst.getNumOperands() != 5)
7730 TmpInst.setOpcode(ARM::t2LDR_POST);
7731 TmpInst.addOperand(Inst.getOperand(4)); // Rt
7732 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
7733 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7734 TmpInst.addOperand(MCOperand::CreateImm(4));
7735 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
7736 TmpInst.addOperand(Inst.getOperand(3));
7740 case ARM::t2STMDB_UPD: {
7741 // If this is a store of a single register, then we should use
7742 // a pre-indexed STR instruction instead, per the ARM ARM.
7743 if (Inst.getNumOperands() != 5)
7746 TmpInst.setOpcode(ARM::t2STR_PRE);
7747 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
7748 TmpInst.addOperand(Inst.getOperand(4)); // Rt
7749 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7750 TmpInst.addOperand(MCOperand::CreateImm(-4));
7751 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
7752 TmpInst.addOperand(Inst.getOperand(3));
7756 case ARM::LDMIA_UPD:
7757 // If this is a load of a single register via a 'pop', then we should use
7758 // a post-indexed LDR instruction instead, per the ARM ARM.
7759 if (static_cast<ARMOperand &>(*Operands[0]).getToken() == "pop" &&
7760 Inst.getNumOperands() == 5) {
7762 TmpInst.setOpcode(ARM::LDR_POST_IMM);
7763 TmpInst.addOperand(Inst.getOperand(4)); // Rt
7764 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
7765 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7766 TmpInst.addOperand(MCOperand::CreateReg(0)); // am2offset
7767 TmpInst.addOperand(MCOperand::CreateImm(4));
7768 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
7769 TmpInst.addOperand(Inst.getOperand(3));
7774 case ARM::STMDB_UPD:
7775 // If this is a store of a single register via a 'push', then we should use
7776 // a pre-indexed STR instruction instead, per the ARM ARM.
7777 if (static_cast<ARMOperand &>(*Operands[0]).getToken() == "push" &&
7778 Inst.getNumOperands() == 5) {
7780 TmpInst.setOpcode(ARM::STR_PRE_IMM);
7781 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
7782 TmpInst.addOperand(Inst.getOperand(4)); // Rt
7783 TmpInst.addOperand(Inst.getOperand(1)); // addrmode_imm12
7784 TmpInst.addOperand(MCOperand::CreateImm(-4));
7785 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
7786 TmpInst.addOperand(Inst.getOperand(3));
7790 case ARM::t2ADDri12:
7791 // If the immediate fits for encoding T3 (t2ADDri) and the generic "add"
7792 // mnemonic was used (not "addw"), encoding T3 is preferred.
7793 if (static_cast<ARMOperand &>(*Operands[0]).getToken() != "add" ||
7794 ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1)
7796 Inst.setOpcode(ARM::t2ADDri);
7797 Inst.addOperand(MCOperand::CreateReg(0)); // cc_out
7799 case ARM::t2SUBri12:
7800 // If the immediate fits for encoding T3 (t2SUBri) and the generic "sub"
7801 // mnemonic was used (not "subw"), encoding T3 is preferred.
7802 if (static_cast<ARMOperand &>(*Operands[0]).getToken() != "sub" ||
7803 ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1)
7805 Inst.setOpcode(ARM::t2SUBri);
7806 Inst.addOperand(MCOperand::CreateReg(0)); // cc_out
7809 // If the immediate is in the range 0-7, we want tADDi3 iff Rd was
7810 // explicitly specified. From the ARM ARM: "Encoding T1 is preferred
7811 // to encoding T2 if <Rd> is specified and encoding T2 is preferred
7812 // to encoding T1 if <Rd> is omitted."
7813 if ((unsigned)Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) {
7814 Inst.setOpcode(ARM::tADDi3);
7819 // If the immediate is in the range 0-7, we want tADDi3 iff Rd was
7820 // explicitly specified. From the ARM ARM: "Encoding T1 is preferred
7821 // to encoding T2 if <Rd> is specified and encoding T2 is preferred
7822 // to encoding T1 if <Rd> is omitted."
7823 if ((unsigned)Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) {
7824 Inst.setOpcode(ARM::tSUBi3);
7829 case ARM::t2SUBri: {
7830 // If the destination and first source operand are the same, and
7831 // the flags are compatible with the current IT status, use encoding T2
7832 // instead of T3. For compatibility with the system 'as'. Make sure the
7833 // wide encoding wasn't explicit.
7834 if (Inst.getOperand(0).getReg() != Inst.getOperand(1).getReg() ||
7835 !isARMLowRegister(Inst.getOperand(0).getReg()) ||
7836 (unsigned)Inst.getOperand(2).getImm() > 255 ||
7837 ((!inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR) ||
7838 (inITBlock() && Inst.getOperand(5).getReg() != 0)) ||
7839 (static_cast<ARMOperand &>(*Operands[3]).isToken() &&
7840 static_cast<ARMOperand &>(*Operands[3]).getToken() == ".w"))
7843 TmpInst.setOpcode(Inst.getOpcode() == ARM::t2ADDri ?
7844 ARM::tADDi8 : ARM::tSUBi8);
7845 TmpInst.addOperand(Inst.getOperand(0));
7846 TmpInst.addOperand(Inst.getOperand(5));
7847 TmpInst.addOperand(Inst.getOperand(0));
7848 TmpInst.addOperand(Inst.getOperand(2));
7849 TmpInst.addOperand(Inst.getOperand(3));
7850 TmpInst.addOperand(Inst.getOperand(4));
7854 case ARM::t2ADDrr: {
7855 // If the destination and first source operand are the same, and
7856 // there's no setting of the flags, use encoding T2 instead of T3.
7857 // Note that this is only for ADD, not SUB. This mirrors the system
7858 // 'as' behaviour. Make sure the wide encoding wasn't explicit.
7859 if (Inst.getOperand(0).getReg() != Inst.getOperand(1).getReg() ||
7860 Inst.getOperand(5).getReg() != 0 ||
7861 (static_cast<ARMOperand &>(*Operands[3]).isToken() &&
7862 static_cast<ARMOperand &>(*Operands[3]).getToken() == ".w"))
7865 TmpInst.setOpcode(ARM::tADDhirr);
7866 TmpInst.addOperand(Inst.getOperand(0));
7867 TmpInst.addOperand(Inst.getOperand(0));
7868 TmpInst.addOperand(Inst.getOperand(2));
7869 TmpInst.addOperand(Inst.getOperand(3));
7870 TmpInst.addOperand(Inst.getOperand(4));
7874 case ARM::tADDrSP: {
7875 // If the non-SP source operand and the destination operand are not the
7876 // same, we need to use the 32-bit encoding if it's available.
7877 if (Inst.getOperand(0).getReg() != Inst.getOperand(2).getReg()) {
7878 Inst.setOpcode(ARM::t2ADDrr);
7879 Inst.addOperand(MCOperand::CreateReg(0)); // cc_out
7885 // A Thumb conditional branch outside of an IT block is a tBcc.
7886 if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()) {
7887 Inst.setOpcode(ARM::tBcc);
7892 // A Thumb2 conditional branch outside of an IT block is a t2Bcc.
7893 if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()){
7894 Inst.setOpcode(ARM::t2Bcc);
7899 // If the conditional is AL or we're in an IT block, we really want t2B.
7900 if (Inst.getOperand(1).getImm() == ARMCC::AL || inITBlock()) {
7901 Inst.setOpcode(ARM::t2B);
7906 // If the conditional is AL, we really want tB.
7907 if (Inst.getOperand(1).getImm() == ARMCC::AL) {
7908 Inst.setOpcode(ARM::tB);
7913 // If the register list contains any high registers, or if the writeback
7914 // doesn't match what tLDMIA can do, we need to use the 32-bit encoding
7915 // instead if we're in Thumb2. Otherwise, this should have generated
7916 // an error in validateInstruction().
7917 unsigned Rn = Inst.getOperand(0).getReg();
7918 bool hasWritebackToken =
7919 (static_cast<ARMOperand &>(*Operands[3]).isToken() &&
7920 static_cast<ARMOperand &>(*Operands[3]).getToken() == "!");
7921 bool listContainsBase;
7922 if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase) ||
7923 (!listContainsBase && !hasWritebackToken) ||
7924 (listContainsBase && hasWritebackToken)) {
7925 // 16-bit encoding isn't sufficient. Switch to the 32-bit version.
7926 assert (isThumbTwo());
7927 Inst.setOpcode(hasWritebackToken ? ARM::t2LDMIA_UPD : ARM::t2LDMIA);
7928 // If we're switching to the updating version, we need to insert
7929 // the writeback tied operand.
7930 if (hasWritebackToken)
7931 Inst.insert(Inst.begin(),
7932 MCOperand::CreateReg(Inst.getOperand(0).getReg()));
7937 case ARM::tSTMIA_UPD: {
7938 // If the register list contains any high registers, we need to use
7939 // the 32-bit encoding instead if we're in Thumb2. Otherwise, this
7940 // should have generated an error in validateInstruction().
7941 unsigned Rn = Inst.getOperand(0).getReg();
7942 bool listContainsBase;
7943 if (checkLowRegisterList(Inst, 4, Rn, 0, listContainsBase)) {
7944 // 16-bit encoding isn't sufficient. Switch to the 32-bit version.
7945 assert (isThumbTwo());
7946 Inst.setOpcode(ARM::t2STMIA_UPD);
7952 bool listContainsBase;
7953 // If the register list contains any high registers, we need to use
7954 // the 32-bit encoding instead if we're in Thumb2. Otherwise, this
7955 // should have generated an error in validateInstruction().
7956 if (!checkLowRegisterList(Inst, 2, 0, ARM::PC, listContainsBase))
7958 assert (isThumbTwo());
7959 Inst.setOpcode(ARM::t2LDMIA_UPD);
7960 // Add the base register and writeback operands.
7961 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
7962 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
7966 bool listContainsBase;
7967 if (!checkLowRegisterList(Inst, 2, 0, ARM::LR, listContainsBase))
7969 assert (isThumbTwo());
7970 Inst.setOpcode(ARM::t2STMDB_UPD);
7971 // Add the base register and writeback operands.
7972 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
7973 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
7977 // If we can use the 16-bit encoding and the user didn't explicitly
7978 // request the 32-bit variant, transform it here.
7979 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7980 (unsigned)Inst.getOperand(1).getImm() <= 255 &&
7981 ((!inITBlock() && Inst.getOperand(2).getImm() == ARMCC::AL &&
7982 Inst.getOperand(4).getReg() == ARM::CPSR) ||
7983 (inITBlock() && Inst.getOperand(4).getReg() == 0)) &&
7984 (!static_cast<ARMOperand &>(*Operands[2]).isToken() ||
7985 static_cast<ARMOperand &>(*Operands[2]).getToken() != ".w")) {
7986 // The operands aren't in the same order for tMOVi8...
7988 TmpInst.setOpcode(ARM::tMOVi8);
7989 TmpInst.addOperand(Inst.getOperand(0));
7990 TmpInst.addOperand(Inst.getOperand(4));
7991 TmpInst.addOperand(Inst.getOperand(1));
7992 TmpInst.addOperand(Inst.getOperand(2));
7993 TmpInst.addOperand(Inst.getOperand(3));
8000 // If we can use the 16-bit encoding and the user didn't explicitly
8001 // request the 32-bit variant, transform it here.
8002 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
8003 isARMLowRegister(Inst.getOperand(1).getReg()) &&
8004 Inst.getOperand(2).getImm() == ARMCC::AL &&
8005 Inst.getOperand(4).getReg() == ARM::CPSR &&
8006 (!static_cast<ARMOperand &>(*Operands[2]).isToken() ||
8007 static_cast<ARMOperand &>(*Operands[2]).getToken() != ".w")) {
8008 // The operands aren't the same for tMOV[S]r... (no cc_out)
8010 TmpInst.setOpcode(Inst.getOperand(4).getReg() ? ARM::tMOVSr : ARM::tMOVr);
8011 TmpInst.addOperand(Inst.getOperand(0));
8012 TmpInst.addOperand(Inst.getOperand(1));
8013 TmpInst.addOperand(Inst.getOperand(2));
8014 TmpInst.addOperand(Inst.getOperand(3));
8024 // If we can use the 16-bit encoding and the user didn't explicitly
8025 // request the 32-bit variant, transform it here.
8026 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
8027 isARMLowRegister(Inst.getOperand(1).getReg()) &&
8028 Inst.getOperand(2).getImm() == 0 &&
8029 (!static_cast<ARMOperand &>(*Operands[2]).isToken() ||
8030 static_cast<ARMOperand &>(*Operands[2]).getToken() != ".w")) {
8032 switch (Inst.getOpcode()) {
8033 default: llvm_unreachable("Illegal opcode!");
8034 case ARM::t2SXTH: NewOpc = ARM::tSXTH; break;
8035 case ARM::t2SXTB: NewOpc = ARM::tSXTB; break;
8036 case ARM::t2UXTH: NewOpc = ARM::tUXTH; break;
8037 case ARM::t2UXTB: NewOpc = ARM::tUXTB; break;
8039 // The operands aren't the same for thumb1 (no rotate operand).
8041 TmpInst.setOpcode(NewOpc);
8042 TmpInst.addOperand(Inst.getOperand(0));
8043 TmpInst.addOperand(Inst.getOperand(1));
8044 TmpInst.addOperand(Inst.getOperand(3));
8045 TmpInst.addOperand(Inst.getOperand(4));
8052 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(2).getImm());
8053 // rrx shifts and asr/lsr of #32 is encoded as 0
8054 if (SOpc == ARM_AM::rrx || SOpc == ARM_AM::asr || SOpc == ARM_AM::lsr)
8056 if (ARM_AM::getSORegOffset(Inst.getOperand(2).getImm()) == 0) {
8057 // Shifting by zero is accepted as a vanilla 'MOVr'
8059 TmpInst.setOpcode(ARM::MOVr);
8060 TmpInst.addOperand(Inst.getOperand(0));
8061 TmpInst.addOperand(Inst.getOperand(1));
8062 TmpInst.addOperand(Inst.getOperand(3));
8063 TmpInst.addOperand(Inst.getOperand(4));
8064 TmpInst.addOperand(Inst.getOperand(5));
8077 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(3).getImm());
8078 if (SOpc == ARM_AM::rrx) return false;
8079 switch (Inst.getOpcode()) {
8080 default: llvm_unreachable("unexpected opcode!");
8081 case ARM::ANDrsi: newOpc = ARM::ANDrr; break;
8082 case ARM::ORRrsi: newOpc = ARM::ORRrr; break;
8083 case ARM::EORrsi: newOpc = ARM::EORrr; break;
8084 case ARM::BICrsi: newOpc = ARM::BICrr; break;
8085 case ARM::SUBrsi: newOpc = ARM::SUBrr; break;
8086 case ARM::ADDrsi: newOpc = ARM::ADDrr; break;
8088 // If the shift is by zero, use the non-shifted instruction definition.
8089 // The exception is for right shifts, where 0 == 32
8090 if (ARM_AM::getSORegOffset(Inst.getOperand(3).getImm()) == 0 &&
8091 !(SOpc == ARM_AM::lsr || SOpc == ARM_AM::asr)) {
8093 TmpInst.setOpcode(newOpc);
8094 TmpInst.addOperand(Inst.getOperand(0));
8095 TmpInst.addOperand(Inst.getOperand(1));
8096 TmpInst.addOperand(Inst.getOperand(2));
8097 TmpInst.addOperand(Inst.getOperand(4));
8098 TmpInst.addOperand(Inst.getOperand(5));
8099 TmpInst.addOperand(Inst.getOperand(6));
8107 // The mask bits for all but the first condition are represented as
8108 // the low bit of the condition code value implies 't'. We currently
8109 // always have 1 implies 't', so XOR toggle the bits if the low bit
8110 // of the condition code is zero.
8111 MCOperand &MO = Inst.getOperand(1);
8112 unsigned Mask = MO.getImm();
8113 unsigned OrigMask = Mask;
8114 unsigned TZ = countTrailingZeros(Mask);
8115 if ((Inst.getOperand(0).getImm() & 1) == 0) {
8116 assert(Mask && TZ <= 3 && "illegal IT mask value!");
8117 Mask ^= (0xE << TZ) & 0xF;
8121 // Set up the IT block state according to the IT instruction we just
8123 assert(!inITBlock() && "nested IT blocks?!");
8124 ITState.Cond = ARMCC::CondCodes(Inst.getOperand(0).getImm());
8125 ITState.Mask = OrigMask; // Use the original mask, not the updated one.
8126 ITState.CurPosition = 0;
8127 ITState.FirstCond = true;
8137 // Assemblers should use the narrow encodings of these instructions when permissible.
8138 if ((isARMLowRegister(Inst.getOperand(1).getReg()) &&
8139 isARMLowRegister(Inst.getOperand(2).getReg())) &&
8140 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
8141 ((!inITBlock() && Inst.getOperand(5).getReg() == ARM::CPSR) ||
8142 (inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR)) &&
8143 (!static_cast<ARMOperand &>(*Operands[3]).isToken() ||
8144 !static_cast<ARMOperand &>(*Operands[3]).getToken().equals_lower(
8147 switch (Inst.getOpcode()) {
8148 default: llvm_unreachable("unexpected opcode");
8149 case ARM::t2LSLrr: NewOpc = ARM::tLSLrr; break;
8150 case ARM::t2LSRrr: NewOpc = ARM::tLSRrr; break;
8151 case ARM::t2ASRrr: NewOpc = ARM::tASRrr; break;
8152 case ARM::t2SBCrr: NewOpc = ARM::tSBC; break;
8153 case ARM::t2RORrr: NewOpc = ARM::tROR; break;
8154 case ARM::t2BICrr: NewOpc = ARM::tBIC; break;
8157 TmpInst.setOpcode(NewOpc);
8158 TmpInst.addOperand(Inst.getOperand(0));
8159 TmpInst.addOperand(Inst.getOperand(5));
8160 TmpInst.addOperand(Inst.getOperand(1));
8161 TmpInst.addOperand(Inst.getOperand(2));
8162 TmpInst.addOperand(Inst.getOperand(3));
8163 TmpInst.addOperand(Inst.getOperand(4));
8174 // Assemblers should use the narrow encodings of these instructions when permissible.
8175 // These instructions are special in that they are commutable, so shorter encodings
8176 // are available more often.
8177 if ((isARMLowRegister(Inst.getOperand(1).getReg()) &&
8178 isARMLowRegister(Inst.getOperand(2).getReg())) &&
8179 (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() ||
8180 Inst.getOperand(0).getReg() == Inst.getOperand(2).getReg()) &&
8181 ((!inITBlock() && Inst.getOperand(5).getReg() == ARM::CPSR) ||
8182 (inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR)) &&
8183 (!static_cast<ARMOperand &>(*Operands[3]).isToken() ||
8184 !static_cast<ARMOperand &>(*Operands[3]).getToken().equals_lower(
8187 switch (Inst.getOpcode()) {
8188 default: llvm_unreachable("unexpected opcode");
8189 case ARM::t2ADCrr: NewOpc = ARM::tADC; break;
8190 case ARM::t2ANDrr: NewOpc = ARM::tAND; break;
8191 case ARM::t2EORrr: NewOpc = ARM::tEOR; break;
8192 case ARM::t2ORRrr: NewOpc = ARM::tORR; break;
8195 TmpInst.setOpcode(NewOpc);
8196 TmpInst.addOperand(Inst.getOperand(0));
8197 TmpInst.addOperand(Inst.getOperand(5));
8198 if (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()) {
8199 TmpInst.addOperand(Inst.getOperand(1));
8200 TmpInst.addOperand(Inst.getOperand(2));
8202 TmpInst.addOperand(Inst.getOperand(2));
8203 TmpInst.addOperand(Inst.getOperand(1));
8205 TmpInst.addOperand(Inst.getOperand(3));
8206 TmpInst.addOperand(Inst.getOperand(4));
8216 unsigned ARMAsmParser::checkTargetMatchPredicate(MCInst &Inst) {
8217 // 16-bit thumb arithmetic instructions either require or preclude the 'S'
8218 // suffix depending on whether they're in an IT block or not.
8219 unsigned Opc = Inst.getOpcode();
8220 const MCInstrDesc &MCID = MII.get(Opc);
8221 if (MCID.TSFlags & ARMII::ThumbArithFlagSetting) {
8222 assert(MCID.hasOptionalDef() &&
8223 "optionally flag setting instruction missing optional def operand");
8224 assert(MCID.NumOperands == Inst.getNumOperands() &&
8225 "operand count mismatch!");
8226 // Find the optional-def operand (cc_out).
8229 !MCID.OpInfo[OpNo].isOptionalDef() && OpNo < MCID.NumOperands;
8232 // If we're parsing Thumb1, reject it completely.
8233 if (isThumbOne() && Inst.getOperand(OpNo).getReg() != ARM::CPSR)
8234 return Match_MnemonicFail;
8235 // If we're parsing Thumb2, which form is legal depends on whether we're
8237 if (isThumbTwo() && Inst.getOperand(OpNo).getReg() != ARM::CPSR &&
8239 return Match_RequiresITBlock;
8240 if (isThumbTwo() && Inst.getOperand(OpNo).getReg() == ARM::CPSR &&
8242 return Match_RequiresNotITBlock;
8244 // Some high-register supporting Thumb1 encodings only allow both registers
8245 // to be from r0-r7 when in Thumb2.
8246 else if (Opc == ARM::tADDhirr && isThumbOne() && !hasV6MOps() &&
8247 isARMLowRegister(Inst.getOperand(1).getReg()) &&
8248 isARMLowRegister(Inst.getOperand(2).getReg()))
8249 return Match_RequiresThumb2;
8250 // Others only require ARMv6 or later.
8251 else if (Opc == ARM::tMOVr && isThumbOne() && !hasV6Ops() &&
8252 isARMLowRegister(Inst.getOperand(0).getReg()) &&
8253 isARMLowRegister(Inst.getOperand(1).getReg()))
8254 return Match_RequiresV6;
8255 return Match_Success;
8259 template <> inline bool IsCPSRDead<MCInst>(MCInst *Instr) {
8260 return true; // In an assembly source, no need to second-guess
8264 static const char *getSubtargetFeatureName(uint64_t Val);
8265 bool ARMAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
8266 OperandVector &Operands,
8267 MCStreamer &Out, uint64_t &ErrorInfo,
8268 bool MatchingInlineAsm) {
8270 unsigned MatchResult;
8272 MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo,
8274 switch (MatchResult) {
8277 // Context sensitive operand constraints aren't handled by the matcher,
8278 // so check them here.
8279 if (validateInstruction(Inst, Operands)) {
8280 // Still progress the IT block, otherwise one wrong condition causes
8281 // nasty cascading errors.
8282 forwardITPosition();
8286 { // processInstruction() updates inITBlock state, we need to save it away
8287 bool wasInITBlock = inITBlock();
8289 // Some instructions need post-processing to, for example, tweak which
8290 // encoding is selected. Loop on it while changes happen so the
8291 // individual transformations can chain off each other. E.g.,
8292 // tPOP(r8)->t2LDMIA_UPD(sp,r8)->t2STR_POST(sp,r8)
8293 while (processInstruction(Inst, Operands))
8296 // Only after the instruction is fully processed, we can validate it
8297 if (wasInITBlock && hasV8Ops() && isThumb() &&
8298 !isV8EligibleForIT(&Inst)) {
8299 Warning(IDLoc, "deprecated instruction in IT block");
8303 // Only move forward at the very end so that everything in validate
8304 // and process gets a consistent answer about whether we're in an IT
8306 forwardITPosition();
8308 // ITasm is an ARM mode pseudo-instruction that just sets the ITblock and
8309 // doesn't actually encode.
8310 if (Inst.getOpcode() == ARM::ITasm)
8314 Out.EmitInstruction(Inst, STI);
8316 case Match_MissingFeature: {
8317 assert(ErrorInfo && "Unknown missing feature!");
8318 // Special case the error message for the very common case where only
8319 // a single subtarget feature is missing (Thumb vs. ARM, e.g.).
8320 std::string Msg = "instruction requires:";
8322 for (unsigned i = 0; i < (sizeof(ErrorInfo)*8-1); ++i) {
8323 if (ErrorInfo & Mask) {
8325 Msg += getSubtargetFeatureName(ErrorInfo & Mask);
8329 return Error(IDLoc, Msg);
8331 case Match_InvalidOperand: {
8332 SMLoc ErrorLoc = IDLoc;
8333 if (ErrorInfo != ~0ULL) {
8334 if (ErrorInfo >= Operands.size())
8335 return Error(IDLoc, "too few operands for instruction");
8337 ErrorLoc = ((ARMOperand &)*Operands[ErrorInfo]).getStartLoc();
8338 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
8341 return Error(ErrorLoc, "invalid operand for instruction");
8343 case Match_MnemonicFail:
8344 return Error(IDLoc, "invalid instruction",
8345 ((ARMOperand &)*Operands[0]).getLocRange());
8346 case Match_RequiresNotITBlock:
8347 return Error(IDLoc, "flag setting instruction only valid outside IT block");
8348 case Match_RequiresITBlock:
8349 return Error(IDLoc, "instruction only valid inside IT block");
8350 case Match_RequiresV6:
8351 return Error(IDLoc, "instruction variant requires ARMv6 or later");
8352 case Match_RequiresThumb2:
8353 return Error(IDLoc, "instruction variant requires Thumb2");
8354 case Match_ImmRange0_15: {
8355 SMLoc ErrorLoc = ((ARMOperand &)*Operands[ErrorInfo]).getStartLoc();
8356 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
8357 return Error(ErrorLoc, "immediate operand must be in the range [0,15]");
8359 case Match_ImmRange0_239: {
8360 SMLoc ErrorLoc = ((ARMOperand &)*Operands[ErrorInfo]).getStartLoc();
8361 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
8362 return Error(ErrorLoc, "immediate operand must be in the range [0,239]");
8364 case Match_AlignedMemoryRequiresNone:
8365 case Match_DupAlignedMemoryRequiresNone:
8366 case Match_AlignedMemoryRequires16:
8367 case Match_DupAlignedMemoryRequires16:
8368 case Match_AlignedMemoryRequires32:
8369 case Match_DupAlignedMemoryRequires32:
8370 case Match_AlignedMemoryRequires64:
8371 case Match_DupAlignedMemoryRequires64:
8372 case Match_AlignedMemoryRequires64or128:
8373 case Match_DupAlignedMemoryRequires64or128:
8374 case Match_AlignedMemoryRequires64or128or256:
8376 SMLoc ErrorLoc = ((ARMOperand &)*Operands[ErrorInfo]).getAlignmentLoc();
8377 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
8378 switch (MatchResult) {
8380 llvm_unreachable("Missing Match_Aligned type");
8381 case Match_AlignedMemoryRequiresNone:
8382 case Match_DupAlignedMemoryRequiresNone:
8383 return Error(ErrorLoc, "alignment must be omitted");
8384 case Match_AlignedMemoryRequires16:
8385 case Match_DupAlignedMemoryRequires16:
8386 return Error(ErrorLoc, "alignment must be 16 or omitted");
8387 case Match_AlignedMemoryRequires32:
8388 case Match_DupAlignedMemoryRequires32:
8389 return Error(ErrorLoc, "alignment must be 32 or omitted");
8390 case Match_AlignedMemoryRequires64:
8391 case Match_DupAlignedMemoryRequires64:
8392 return Error(ErrorLoc, "alignment must be 64 or omitted");
8393 case Match_AlignedMemoryRequires64or128:
8394 case Match_DupAlignedMemoryRequires64or128:
8395 return Error(ErrorLoc, "alignment must be 64, 128 or omitted");
8396 case Match_AlignedMemoryRequires64or128or256:
8397 return Error(ErrorLoc, "alignment must be 64, 128, 256 or omitted");
8402 llvm_unreachable("Implement any new match types added!");
8405 /// parseDirective parses the arm specific directives
8406 bool ARMAsmParser::ParseDirective(AsmToken DirectiveID) {
8407 const MCObjectFileInfo::Environment Format =
8408 getContext().getObjectFileInfo()->getObjectFileType();
8409 bool IsMachO = Format == MCObjectFileInfo::IsMachO;
8410 bool IsCOFF = Format == MCObjectFileInfo::IsCOFF;
8412 StringRef IDVal = DirectiveID.getIdentifier();
8413 if (IDVal == ".word")
8414 return parseLiteralValues(4, DirectiveID.getLoc());
8415 else if (IDVal == ".short" || IDVal == ".hword")
8416 return parseLiteralValues(2, DirectiveID.getLoc());
8417 else if (IDVal == ".thumb")
8418 return parseDirectiveThumb(DirectiveID.getLoc());
8419 else if (IDVal == ".arm")
8420 return parseDirectiveARM(DirectiveID.getLoc());
8421 else if (IDVal == ".thumb_func")
8422 return parseDirectiveThumbFunc(DirectiveID.getLoc());
8423 else if (IDVal == ".code")
8424 return parseDirectiveCode(DirectiveID.getLoc());
8425 else if (IDVal == ".syntax")
8426 return parseDirectiveSyntax(DirectiveID.getLoc());
8427 else if (IDVal == ".unreq")
8428 return parseDirectiveUnreq(DirectiveID.getLoc());
8429 else if (IDVal == ".fnend")
8430 return parseDirectiveFnEnd(DirectiveID.getLoc());
8431 else if (IDVal == ".cantunwind")
8432 return parseDirectiveCantUnwind(DirectiveID.getLoc());
8433 else if (IDVal == ".personality")
8434 return parseDirectivePersonality(DirectiveID.getLoc());
8435 else if (IDVal == ".handlerdata")
8436 return parseDirectiveHandlerData(DirectiveID.getLoc());
8437 else if (IDVal == ".setfp")
8438 return parseDirectiveSetFP(DirectiveID.getLoc());
8439 else if (IDVal == ".pad")
8440 return parseDirectivePad(DirectiveID.getLoc());
8441 else if (IDVal == ".save")
8442 return parseDirectiveRegSave(DirectiveID.getLoc(), false);
8443 else if (IDVal == ".vsave")
8444 return parseDirectiveRegSave(DirectiveID.getLoc(), true);
8445 else if (IDVal == ".ltorg" || IDVal == ".pool")
8446 return parseDirectiveLtorg(DirectiveID.getLoc());
8447 else if (IDVal == ".even")
8448 return parseDirectiveEven(DirectiveID.getLoc());
8449 else if (IDVal == ".personalityindex")
8450 return parseDirectivePersonalityIndex(DirectiveID.getLoc());
8451 else if (IDVal == ".unwind_raw")
8452 return parseDirectiveUnwindRaw(DirectiveID.getLoc());
8453 else if (IDVal == ".movsp")
8454 return parseDirectiveMovSP(DirectiveID.getLoc());
8455 else if (IDVal == ".arch_extension")
8456 return parseDirectiveArchExtension(DirectiveID.getLoc());
8457 else if (IDVal == ".align")
8458 return parseDirectiveAlign(DirectiveID.getLoc());
8459 else if (IDVal == ".thumb_set")
8460 return parseDirectiveThumbSet(DirectiveID.getLoc());
8462 if (!IsMachO && !IsCOFF) {
8463 if (IDVal == ".arch")
8464 return parseDirectiveArch(DirectiveID.getLoc());
8465 else if (IDVal == ".cpu")
8466 return parseDirectiveCPU(DirectiveID.getLoc());
8467 else if (IDVal == ".eabi_attribute")
8468 return parseDirectiveEabiAttr(DirectiveID.getLoc());
8469 else if (IDVal == ".fpu")
8470 return parseDirectiveFPU(DirectiveID.getLoc());
8471 else if (IDVal == ".fnstart")
8472 return parseDirectiveFnStart(DirectiveID.getLoc());
8473 else if (IDVal == ".inst")
8474 return parseDirectiveInst(DirectiveID.getLoc());
8475 else if (IDVal == ".inst.n")
8476 return parseDirectiveInst(DirectiveID.getLoc(), 'n');
8477 else if (IDVal == ".inst.w")
8478 return parseDirectiveInst(DirectiveID.getLoc(), 'w');
8479 else if (IDVal == ".object_arch")
8480 return parseDirectiveObjectArch(DirectiveID.getLoc());
8481 else if (IDVal == ".tlsdescseq")
8482 return parseDirectiveTLSDescSeq(DirectiveID.getLoc());
8488 /// parseLiteralValues
8489 /// ::= .hword expression [, expression]*
8490 /// ::= .short expression [, expression]*
8491 /// ::= .word expression [, expression]*
8492 bool ARMAsmParser::parseLiteralValues(unsigned Size, SMLoc L) {
8493 if (getLexer().isNot(AsmToken::EndOfStatement)) {
8495 const MCExpr *Value;
8496 if (getParser().parseExpression(Value)) {
8497 Parser.eatToEndOfStatement();
8501 getParser().getStreamer().EmitValue(Value, Size);
8503 if (getLexer().is(AsmToken::EndOfStatement))
8506 // FIXME: Improve diagnostic.
8507 if (getLexer().isNot(AsmToken::Comma)) {
8508 Error(L, "unexpected token in directive");
8519 /// parseDirectiveThumb
8521 bool ARMAsmParser::parseDirectiveThumb(SMLoc L) {
8522 if (getLexer().isNot(AsmToken::EndOfStatement)) {
8523 Error(L, "unexpected token in directive");
8529 Error(L, "target does not support Thumb mode");
8536 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
8540 /// parseDirectiveARM
8542 bool ARMAsmParser::parseDirectiveARM(SMLoc L) {
8543 if (getLexer().isNot(AsmToken::EndOfStatement)) {
8544 Error(L, "unexpected token in directive");
8550 Error(L, "target does not support ARM mode");
8557 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
8561 void ARMAsmParser::onLabelParsed(MCSymbol *Symbol) {
8562 if (NextSymbolIsThumb) {
8563 getParser().getStreamer().EmitThumbFunc(Symbol);
8564 NextSymbolIsThumb = false;
8568 /// parseDirectiveThumbFunc
8569 /// ::= .thumbfunc symbol_name
8570 bool ARMAsmParser::parseDirectiveThumbFunc(SMLoc L) {
8571 const auto Format = getContext().getObjectFileInfo()->getObjectFileType();
8572 bool IsMachO = Format == MCObjectFileInfo::IsMachO;
8574 // Darwin asm has (optionally) function name after .thumb_func direction
8577 const AsmToken &Tok = Parser.getTok();
8578 if (Tok.isNot(AsmToken::EndOfStatement)) {
8579 if (Tok.isNot(AsmToken::Identifier) && Tok.isNot(AsmToken::String)) {
8580 Error(L, "unexpected token in .thumb_func directive");
8585 getParser().getContext().GetOrCreateSymbol(Tok.getIdentifier());
8586 getParser().getStreamer().EmitThumbFunc(Func);
8587 Parser.Lex(); // Consume the identifier token.
8592 if (getLexer().isNot(AsmToken::EndOfStatement)) {
8593 Error(Parser.getTok().getLoc(), "unexpected token in directive");
8594 Parser.eatToEndOfStatement();
8598 NextSymbolIsThumb = true;
8602 /// parseDirectiveSyntax
8603 /// ::= .syntax unified | divided
8604 bool ARMAsmParser::parseDirectiveSyntax(SMLoc L) {
8605 const AsmToken &Tok = Parser.getTok();
8606 if (Tok.isNot(AsmToken::Identifier)) {
8607 Error(L, "unexpected token in .syntax directive");
8611 StringRef Mode = Tok.getString();
8612 if (Mode == "unified" || Mode == "UNIFIED") {
8614 } else if (Mode == "divided" || Mode == "DIVIDED") {
8615 Error(L, "'.syntax divided' arm asssembly not supported");
8618 Error(L, "unrecognized syntax mode in .syntax directive");
8622 if (getLexer().isNot(AsmToken::EndOfStatement)) {
8623 Error(Parser.getTok().getLoc(), "unexpected token in directive");
8628 // TODO tell the MC streamer the mode
8629 // getParser().getStreamer().Emit???();
8633 /// parseDirectiveCode
8634 /// ::= .code 16 | 32
8635 bool ARMAsmParser::parseDirectiveCode(SMLoc L) {
8636 const AsmToken &Tok = Parser.getTok();
8637 if (Tok.isNot(AsmToken::Integer)) {
8638 Error(L, "unexpected token in .code directive");
8641 int64_t Val = Parser.getTok().getIntVal();
8642 if (Val != 16 && Val != 32) {
8643 Error(L, "invalid operand to .code directive");
8648 if (getLexer().isNot(AsmToken::EndOfStatement)) {
8649 Error(Parser.getTok().getLoc(), "unexpected token in directive");
8656 Error(L, "target does not support Thumb mode");
8662 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
8665 Error(L, "target does not support ARM mode");
8671 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
8677 /// parseDirectiveReq
8678 /// ::= name .req registername
8679 bool ARMAsmParser::parseDirectiveReq(StringRef Name, SMLoc L) {
8680 Parser.Lex(); // Eat the '.req' token.
8682 SMLoc SRegLoc, ERegLoc;
8683 if (ParseRegister(Reg, SRegLoc, ERegLoc)) {
8684 Parser.eatToEndOfStatement();
8685 Error(SRegLoc, "register name expected");
8689 // Shouldn't be anything else.
8690 if (Parser.getTok().isNot(AsmToken::EndOfStatement)) {
8691 Parser.eatToEndOfStatement();
8692 Error(Parser.getTok().getLoc(), "unexpected input in .req directive.");
8696 Parser.Lex(); // Consume the EndOfStatement
8698 if (RegisterReqs.GetOrCreateValue(Name, Reg).getValue() != Reg) {
8699 Error(SRegLoc, "redefinition of '" + Name + "' does not match original.");
8706 /// parseDirectiveUneq
8707 /// ::= .unreq registername
8708 bool ARMAsmParser::parseDirectiveUnreq(SMLoc L) {
8709 if (Parser.getTok().isNot(AsmToken::Identifier)) {
8710 Parser.eatToEndOfStatement();
8711 Error(L, "unexpected input in .unreq directive.");
8714 RegisterReqs.erase(Parser.getTok().getIdentifier().lower());
8715 Parser.Lex(); // Eat the identifier.
8719 /// parseDirectiveArch
8721 bool ARMAsmParser::parseDirectiveArch(SMLoc L) {
8722 StringRef Arch = getParser().parseStringToEndOfStatement().trim();
8724 unsigned ID = StringSwitch<unsigned>(Arch)
8725 #define ARM_ARCH_NAME(NAME, ID, DEFAULT_CPU_NAME, DEFAULT_CPU_ARCH) \
8726 .Case(NAME, ARM::ID)
8727 #define ARM_ARCH_ALIAS(NAME, ID) \
8728 .Case(NAME, ARM::ID)
8729 #include "MCTargetDesc/ARMArchName.def"
8730 .Default(ARM::INVALID_ARCH);
8732 if (ID == ARM::INVALID_ARCH) {
8733 Error(L, "Unknown arch name");
8737 getTargetStreamer().emitArch(ID);
8741 /// parseDirectiveEabiAttr
8742 /// ::= .eabi_attribute int, int [, "str"]
8743 /// ::= .eabi_attribute Tag_name, int [, "str"]
8744 bool ARMAsmParser::parseDirectiveEabiAttr(SMLoc L) {
8747 TagLoc = Parser.getTok().getLoc();
8748 if (Parser.getTok().is(AsmToken::Identifier)) {
8749 StringRef Name = Parser.getTok().getIdentifier();
8750 Tag = ARMBuildAttrs::AttrTypeFromString(Name);
8752 Error(TagLoc, "attribute name not recognised: " + Name);
8753 Parser.eatToEndOfStatement();
8758 const MCExpr *AttrExpr;
8760 TagLoc = Parser.getTok().getLoc();
8761 if (Parser.parseExpression(AttrExpr)) {
8762 Parser.eatToEndOfStatement();
8766 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(AttrExpr);
8768 Error(TagLoc, "expected numeric constant");
8769 Parser.eatToEndOfStatement();
8773 Tag = CE->getValue();
8776 if (Parser.getTok().isNot(AsmToken::Comma)) {
8777 Error(Parser.getTok().getLoc(), "comma expected");
8778 Parser.eatToEndOfStatement();
8781 Parser.Lex(); // skip comma
8783 StringRef StringValue = "";
8784 bool IsStringValue = false;
8786 int64_t IntegerValue = 0;
8787 bool IsIntegerValue = false;
8789 if (Tag == ARMBuildAttrs::CPU_raw_name || Tag == ARMBuildAttrs::CPU_name)
8790 IsStringValue = true;
8791 else if (Tag == ARMBuildAttrs::compatibility) {
8792 IsStringValue = true;
8793 IsIntegerValue = true;
8794 } else if (Tag < 32 || Tag % 2 == 0)
8795 IsIntegerValue = true;
8796 else if (Tag % 2 == 1)
8797 IsStringValue = true;
8799 llvm_unreachable("invalid tag type");
8801 if (IsIntegerValue) {
8802 const MCExpr *ValueExpr;
8803 SMLoc ValueExprLoc = Parser.getTok().getLoc();
8804 if (Parser.parseExpression(ValueExpr)) {
8805 Parser.eatToEndOfStatement();
8809 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ValueExpr);
8811 Error(ValueExprLoc, "expected numeric constant");
8812 Parser.eatToEndOfStatement();
8816 IntegerValue = CE->getValue();
8819 if (Tag == ARMBuildAttrs::compatibility) {
8820 if (Parser.getTok().isNot(AsmToken::Comma))
8821 IsStringValue = false;
8826 if (IsStringValue) {
8827 if (Parser.getTok().isNot(AsmToken::String)) {
8828 Error(Parser.getTok().getLoc(), "bad string constant");
8829 Parser.eatToEndOfStatement();
8833 StringValue = Parser.getTok().getStringContents();
8837 if (IsIntegerValue && IsStringValue) {
8838 assert(Tag == ARMBuildAttrs::compatibility);
8839 getTargetStreamer().emitIntTextAttribute(Tag, IntegerValue, StringValue);
8840 } else if (IsIntegerValue)
8841 getTargetStreamer().emitAttribute(Tag, IntegerValue);
8842 else if (IsStringValue)
8843 getTargetStreamer().emitTextAttribute(Tag, StringValue);
8847 /// parseDirectiveCPU
8849 bool ARMAsmParser::parseDirectiveCPU(SMLoc L) {
8850 StringRef CPU = getParser().parseStringToEndOfStatement().trim();
8851 getTargetStreamer().emitTextAttribute(ARMBuildAttrs::CPU_name, CPU);
8855 // FIXME: This is duplicated in getARMFPUFeatures() in
8856 // tools/clang/lib/Driver/Tools.cpp
8857 static const struct {
8859 const uint64_t Enabled;
8860 const uint64_t Disabled;
8862 {ARM::VFP, ARM::FeatureVFP2, ARM::FeatureNEON},
8863 {ARM::VFPV2, ARM::FeatureVFP2, ARM::FeatureNEON},
8864 {ARM::VFPV3, ARM::FeatureVFP3, ARM::FeatureNEON},
8865 {ARM::VFPV3_D16, ARM::FeatureVFP3 | ARM::FeatureD16, ARM::FeatureNEON},
8866 {ARM::VFPV4, ARM::FeatureVFP4, ARM::FeatureNEON},
8867 {ARM::VFPV4_D16, ARM::FeatureVFP4 | ARM::FeatureD16, ARM::FeatureNEON},
8868 {ARM::FPV5_D16, ARM::FeatureFPARMv8 | ARM::FeatureD16,
8869 ARM::FeatureNEON | ARM::FeatureCrypto},
8870 {ARM::FP_ARMV8, ARM::FeatureFPARMv8,
8871 ARM::FeatureNEON | ARM::FeatureCrypto},
8872 {ARM::NEON, ARM::FeatureNEON, 0},
8873 {ARM::NEON_VFPV4, ARM::FeatureVFP4 | ARM::FeatureNEON, 0},
8874 {ARM::NEON_FP_ARMV8, ARM::FeatureFPARMv8 | ARM::FeatureNEON,
8875 ARM::FeatureCrypto},
8876 {ARM::CRYPTO_NEON_FP_ARMV8,
8877 ARM::FeatureFPARMv8 | ARM::FeatureNEON | ARM::FeatureCrypto, 0},
8878 {ARM::SOFTVFP, 0, 0},
8881 /// parseDirectiveFPU
8883 bool ARMAsmParser::parseDirectiveFPU(SMLoc L) {
8884 StringRef FPU = getParser().parseStringToEndOfStatement().trim();
8886 unsigned ID = StringSwitch<unsigned>(FPU)
8887 #define ARM_FPU_NAME(NAME, ID) .Case(NAME, ARM::ID)
8888 #include "ARMFPUName.def"
8889 .Default(ARM::INVALID_FPU);
8891 if (ID == ARM::INVALID_FPU) {
8892 Error(L, "Unknown FPU name");
8896 for (const auto &Fpu : Fpus) {
8900 // Need to toggle features that should be on but are off and that
8901 // should off but are on.
8902 uint64_t Toggle = (Fpu.Enabled & ~STI.getFeatureBits()) |
8903 (Fpu.Disabled & STI.getFeatureBits());
8904 setAvailableFeatures(ComputeAvailableFeatures(STI.ToggleFeature(Toggle)));
8908 getTargetStreamer().emitFPU(ID);
8912 /// parseDirectiveFnStart
8914 bool ARMAsmParser::parseDirectiveFnStart(SMLoc L) {
8915 if (UC.hasFnStart()) {
8916 Error(L, ".fnstart starts before the end of previous one");
8917 UC.emitFnStartLocNotes();
8921 // Reset the unwind directives parser state
8924 getTargetStreamer().emitFnStart();
8926 UC.recordFnStart(L);
8930 /// parseDirectiveFnEnd
8932 bool ARMAsmParser::parseDirectiveFnEnd(SMLoc L) {
8933 // Check the ordering of unwind directives
8934 if (!UC.hasFnStart()) {
8935 Error(L, ".fnstart must precede .fnend directive");
8939 // Reset the unwind directives parser state
8940 getTargetStreamer().emitFnEnd();
8946 /// parseDirectiveCantUnwind
8948 bool ARMAsmParser::parseDirectiveCantUnwind(SMLoc L) {
8949 UC.recordCantUnwind(L);
8951 // Check the ordering of unwind directives
8952 if (!UC.hasFnStart()) {
8953 Error(L, ".fnstart must precede .cantunwind directive");
8956 if (UC.hasHandlerData()) {
8957 Error(L, ".cantunwind can't be used with .handlerdata directive");
8958 UC.emitHandlerDataLocNotes();
8961 if (UC.hasPersonality()) {
8962 Error(L, ".cantunwind can't be used with .personality directive");
8963 UC.emitPersonalityLocNotes();
8967 getTargetStreamer().emitCantUnwind();
8971 /// parseDirectivePersonality
8972 /// ::= .personality name
8973 bool ARMAsmParser::parseDirectivePersonality(SMLoc L) {
8974 bool HasExistingPersonality = UC.hasPersonality();
8976 UC.recordPersonality(L);
8978 // Check the ordering of unwind directives
8979 if (!UC.hasFnStart()) {
8980 Error(L, ".fnstart must precede .personality directive");
8983 if (UC.cantUnwind()) {
8984 Error(L, ".personality can't be used with .cantunwind directive");
8985 UC.emitCantUnwindLocNotes();
8988 if (UC.hasHandlerData()) {
8989 Error(L, ".personality must precede .handlerdata directive");
8990 UC.emitHandlerDataLocNotes();
8993 if (HasExistingPersonality) {
8994 Parser.eatToEndOfStatement();
8995 Error(L, "multiple personality directives");
8996 UC.emitPersonalityLocNotes();
9000 // Parse the name of the personality routine
9001 if (Parser.getTok().isNot(AsmToken::Identifier)) {
9002 Parser.eatToEndOfStatement();
9003 Error(L, "unexpected input in .personality directive.");
9006 StringRef Name(Parser.getTok().getIdentifier());
9009 MCSymbol *PR = getParser().getContext().GetOrCreateSymbol(Name);
9010 getTargetStreamer().emitPersonality(PR);
9014 /// parseDirectiveHandlerData
9015 /// ::= .handlerdata
9016 bool ARMAsmParser::parseDirectiveHandlerData(SMLoc L) {
9017 UC.recordHandlerData(L);
9019 // Check the ordering of unwind directives
9020 if (!UC.hasFnStart()) {
9021 Error(L, ".fnstart must precede .personality directive");
9024 if (UC.cantUnwind()) {
9025 Error(L, ".handlerdata can't be used with .cantunwind directive");
9026 UC.emitCantUnwindLocNotes();
9030 getTargetStreamer().emitHandlerData();
9034 /// parseDirectiveSetFP
9035 /// ::= .setfp fpreg, spreg [, offset]
9036 bool ARMAsmParser::parseDirectiveSetFP(SMLoc L) {
9037 // Check the ordering of unwind directives
9038 if (!UC.hasFnStart()) {
9039 Error(L, ".fnstart must precede .setfp directive");
9042 if (UC.hasHandlerData()) {
9043 Error(L, ".setfp must precede .handlerdata directive");
9048 SMLoc FPRegLoc = Parser.getTok().getLoc();
9049 int FPReg = tryParseRegister();
9051 Error(FPRegLoc, "frame pointer register expected");
9056 if (Parser.getTok().isNot(AsmToken::Comma)) {
9057 Error(Parser.getTok().getLoc(), "comma expected");
9060 Parser.Lex(); // skip comma
9063 SMLoc SPRegLoc = Parser.getTok().getLoc();
9064 int SPReg = tryParseRegister();
9066 Error(SPRegLoc, "stack pointer register expected");
9070 if (SPReg != ARM::SP && SPReg != UC.getFPReg()) {
9071 Error(SPRegLoc, "register should be either $sp or the latest fp register");
9075 // Update the frame pointer register
9076 UC.saveFPReg(FPReg);
9080 if (Parser.getTok().is(AsmToken::Comma)) {
9081 Parser.Lex(); // skip comma
9083 if (Parser.getTok().isNot(AsmToken::Hash) &&
9084 Parser.getTok().isNot(AsmToken::Dollar)) {
9085 Error(Parser.getTok().getLoc(), "'#' expected");
9088 Parser.Lex(); // skip hash token.
9090 const MCExpr *OffsetExpr;
9091 SMLoc ExLoc = Parser.getTok().getLoc();
9093 if (getParser().parseExpression(OffsetExpr, EndLoc)) {
9094 Error(ExLoc, "malformed setfp offset");
9097 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr);
9099 Error(ExLoc, "setfp offset must be an immediate");
9103 Offset = CE->getValue();
9106 getTargetStreamer().emitSetFP(static_cast<unsigned>(FPReg),
9107 static_cast<unsigned>(SPReg), Offset);
9113 bool ARMAsmParser::parseDirectivePad(SMLoc L) {
9114 // Check the ordering of unwind directives
9115 if (!UC.hasFnStart()) {
9116 Error(L, ".fnstart must precede .pad directive");
9119 if (UC.hasHandlerData()) {
9120 Error(L, ".pad must precede .handlerdata directive");
9125 if (Parser.getTok().isNot(AsmToken::Hash) &&
9126 Parser.getTok().isNot(AsmToken::Dollar)) {
9127 Error(Parser.getTok().getLoc(), "'#' expected");
9130 Parser.Lex(); // skip hash token.
9132 const MCExpr *OffsetExpr;
9133 SMLoc ExLoc = Parser.getTok().getLoc();
9135 if (getParser().parseExpression(OffsetExpr, EndLoc)) {
9136 Error(ExLoc, "malformed pad offset");
9139 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr);
9141 Error(ExLoc, "pad offset must be an immediate");
9145 getTargetStreamer().emitPad(CE->getValue());
9149 /// parseDirectiveRegSave
9150 /// ::= .save { registers }
9151 /// ::= .vsave { registers }
9152 bool ARMAsmParser::parseDirectiveRegSave(SMLoc L, bool IsVector) {
9153 // Check the ordering of unwind directives
9154 if (!UC.hasFnStart()) {
9155 Error(L, ".fnstart must precede .save or .vsave directives");
9158 if (UC.hasHandlerData()) {
9159 Error(L, ".save or .vsave must precede .handlerdata directive");
9163 // RAII object to make sure parsed operands are deleted.
9164 SmallVector<std::unique_ptr<MCParsedAsmOperand>, 1> Operands;
9166 // Parse the register list
9167 if (parseRegisterList(Operands))
9169 ARMOperand &Op = (ARMOperand &)*Operands[0];
9170 if (!IsVector && !Op.isRegList()) {
9171 Error(L, ".save expects GPR registers");
9174 if (IsVector && !Op.isDPRRegList()) {
9175 Error(L, ".vsave expects DPR registers");
9179 getTargetStreamer().emitRegSave(Op.getRegList(), IsVector);
9183 /// parseDirectiveInst
9184 /// ::= .inst opcode [, ...]
9185 /// ::= .inst.n opcode [, ...]
9186 /// ::= .inst.w opcode [, ...]
9187 bool ARMAsmParser::parseDirectiveInst(SMLoc Loc, char Suffix) {
9199 Parser.eatToEndOfStatement();
9200 Error(Loc, "cannot determine Thumb instruction size, "
9201 "use inst.n/inst.w instead");
9206 Parser.eatToEndOfStatement();
9207 Error(Loc, "width suffixes are invalid in ARM mode");
9213 if (getLexer().is(AsmToken::EndOfStatement)) {
9214 Parser.eatToEndOfStatement();
9215 Error(Loc, "expected expression following directive");
9222 if (getParser().parseExpression(Expr)) {
9223 Error(Loc, "expected expression");
9227 const MCConstantExpr *Value = dyn_cast_or_null<MCConstantExpr>(Expr);
9229 Error(Loc, "expected constant expression");
9235 if (Value->getValue() > 0xffff) {
9236 Error(Loc, "inst.n operand is too big, use inst.w instead");
9241 if (Value->getValue() > 0xffffffff) {
9243 StringRef(Suffix ? "inst.w" : "inst") + " operand is too big");
9248 llvm_unreachable("only supported widths are 2 and 4");
9251 getTargetStreamer().emitInst(Value->getValue(), Suffix);
9253 if (getLexer().is(AsmToken::EndOfStatement))
9256 if (getLexer().isNot(AsmToken::Comma)) {
9257 Error(Loc, "unexpected token in directive");
9268 /// parseDirectiveLtorg
9269 /// ::= .ltorg | .pool
9270 bool ARMAsmParser::parseDirectiveLtorg(SMLoc L) {
9271 getTargetStreamer().emitCurrentConstantPool();
9275 bool ARMAsmParser::parseDirectiveEven(SMLoc L) {
9276 const MCSection *Section = getStreamer().getCurrentSection().first;
9278 if (getLexer().isNot(AsmToken::EndOfStatement)) {
9279 TokError("unexpected token in directive");
9284 getStreamer().InitSections(false);
9285 Section = getStreamer().getCurrentSection().first;
9288 assert(Section && "must have section to emit alignment");
9289 if (Section->UseCodeAlign())
9290 getStreamer().EmitCodeAlignment(2);
9292 getStreamer().EmitValueToAlignment(2);
9297 /// parseDirectivePersonalityIndex
9298 /// ::= .personalityindex index
9299 bool ARMAsmParser::parseDirectivePersonalityIndex(SMLoc L) {
9300 bool HasExistingPersonality = UC.hasPersonality();
9302 UC.recordPersonalityIndex(L);
9304 if (!UC.hasFnStart()) {
9305 Parser.eatToEndOfStatement();
9306 Error(L, ".fnstart must precede .personalityindex directive");
9309 if (UC.cantUnwind()) {
9310 Parser.eatToEndOfStatement();
9311 Error(L, ".personalityindex cannot be used with .cantunwind");
9312 UC.emitCantUnwindLocNotes();
9315 if (UC.hasHandlerData()) {
9316 Parser.eatToEndOfStatement();
9317 Error(L, ".personalityindex must precede .handlerdata directive");
9318 UC.emitHandlerDataLocNotes();
9321 if (HasExistingPersonality) {
9322 Parser.eatToEndOfStatement();
9323 Error(L, "multiple personality directives");
9324 UC.emitPersonalityLocNotes();
9328 const MCExpr *IndexExpression;
9329 SMLoc IndexLoc = Parser.getTok().getLoc();
9330 if (Parser.parseExpression(IndexExpression)) {
9331 Parser.eatToEndOfStatement();
9335 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(IndexExpression);
9337 Parser.eatToEndOfStatement();
9338 Error(IndexLoc, "index must be a constant number");
9341 if (CE->getValue() < 0 ||
9342 CE->getValue() >= ARM::EHABI::NUM_PERSONALITY_INDEX) {
9343 Parser.eatToEndOfStatement();
9344 Error(IndexLoc, "personality routine index should be in range [0-3]");
9348 getTargetStreamer().emitPersonalityIndex(CE->getValue());
9352 /// parseDirectiveUnwindRaw
9353 /// ::= .unwind_raw offset, opcode [, opcode...]
9354 bool ARMAsmParser::parseDirectiveUnwindRaw(SMLoc L) {
9355 if (!UC.hasFnStart()) {
9356 Parser.eatToEndOfStatement();
9357 Error(L, ".fnstart must precede .unwind_raw directives");
9361 int64_t StackOffset;
9363 const MCExpr *OffsetExpr;
9364 SMLoc OffsetLoc = getLexer().getLoc();
9365 if (getLexer().is(AsmToken::EndOfStatement) ||
9366 getParser().parseExpression(OffsetExpr)) {
9367 Error(OffsetLoc, "expected expression");
9368 Parser.eatToEndOfStatement();
9372 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr);
9374 Error(OffsetLoc, "offset must be a constant");
9375 Parser.eatToEndOfStatement();
9379 StackOffset = CE->getValue();
9381 if (getLexer().isNot(AsmToken::Comma)) {
9382 Error(getLexer().getLoc(), "expected comma");
9383 Parser.eatToEndOfStatement();
9388 SmallVector<uint8_t, 16> Opcodes;
9392 SMLoc OpcodeLoc = getLexer().getLoc();
9393 if (getLexer().is(AsmToken::EndOfStatement) || Parser.parseExpression(OE)) {
9394 Error(OpcodeLoc, "expected opcode expression");
9395 Parser.eatToEndOfStatement();
9399 const MCConstantExpr *OC = dyn_cast<MCConstantExpr>(OE);
9401 Error(OpcodeLoc, "opcode value must be a constant");
9402 Parser.eatToEndOfStatement();
9406 const int64_t Opcode = OC->getValue();
9407 if (Opcode & ~0xff) {
9408 Error(OpcodeLoc, "invalid opcode");
9409 Parser.eatToEndOfStatement();
9413 Opcodes.push_back(uint8_t(Opcode));
9415 if (getLexer().is(AsmToken::EndOfStatement))
9418 if (getLexer().isNot(AsmToken::Comma)) {
9419 Error(getLexer().getLoc(), "unexpected token in directive");
9420 Parser.eatToEndOfStatement();
9427 getTargetStreamer().emitUnwindRaw(StackOffset, Opcodes);
9433 /// parseDirectiveTLSDescSeq
9434 /// ::= .tlsdescseq tls-variable
9435 bool ARMAsmParser::parseDirectiveTLSDescSeq(SMLoc L) {
9436 if (getLexer().isNot(AsmToken::Identifier)) {
9437 TokError("expected variable after '.tlsdescseq' directive");
9438 Parser.eatToEndOfStatement();
9442 const MCSymbolRefExpr *SRE =
9443 MCSymbolRefExpr::Create(Parser.getTok().getIdentifier(),
9444 MCSymbolRefExpr::VK_ARM_TLSDESCSEQ, getContext());
9447 if (getLexer().isNot(AsmToken::EndOfStatement)) {
9448 Error(Parser.getTok().getLoc(), "unexpected token");
9449 Parser.eatToEndOfStatement();
9453 getTargetStreamer().AnnotateTLSDescriptorSequence(SRE);
9457 /// parseDirectiveMovSP
9458 /// ::= .movsp reg [, #offset]
9459 bool ARMAsmParser::parseDirectiveMovSP(SMLoc L) {
9460 if (!UC.hasFnStart()) {
9461 Parser.eatToEndOfStatement();
9462 Error(L, ".fnstart must precede .movsp directives");
9465 if (UC.getFPReg() != ARM::SP) {
9466 Parser.eatToEndOfStatement();
9467 Error(L, "unexpected .movsp directive");
9471 SMLoc SPRegLoc = Parser.getTok().getLoc();
9472 int SPReg = tryParseRegister();
9474 Parser.eatToEndOfStatement();
9475 Error(SPRegLoc, "register expected");
9479 if (SPReg == ARM::SP || SPReg == ARM::PC) {
9480 Parser.eatToEndOfStatement();
9481 Error(SPRegLoc, "sp and pc are not permitted in .movsp directive");
9486 if (Parser.getTok().is(AsmToken::Comma)) {
9489 if (Parser.getTok().isNot(AsmToken::Hash)) {
9490 Error(Parser.getTok().getLoc(), "expected #constant");
9491 Parser.eatToEndOfStatement();
9496 const MCExpr *OffsetExpr;
9497 SMLoc OffsetLoc = Parser.getTok().getLoc();
9498 if (Parser.parseExpression(OffsetExpr)) {
9499 Parser.eatToEndOfStatement();
9500 Error(OffsetLoc, "malformed offset expression");
9504 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr);
9506 Parser.eatToEndOfStatement();
9507 Error(OffsetLoc, "offset must be an immediate constant");
9511 Offset = CE->getValue();
9514 getTargetStreamer().emitMovSP(SPReg, Offset);
9515 UC.saveFPReg(SPReg);
9520 /// parseDirectiveObjectArch
9521 /// ::= .object_arch name
9522 bool ARMAsmParser::parseDirectiveObjectArch(SMLoc L) {
9523 if (getLexer().isNot(AsmToken::Identifier)) {
9524 Error(getLexer().getLoc(), "unexpected token");
9525 Parser.eatToEndOfStatement();
9529 StringRef Arch = Parser.getTok().getString();
9530 SMLoc ArchLoc = Parser.getTok().getLoc();
9533 unsigned ID = StringSwitch<unsigned>(Arch)
9534 #define ARM_ARCH_NAME(NAME, ID, DEFAULT_CPU_NAME, DEFAULT_CPU_ARCH) \
9535 .Case(NAME, ARM::ID)
9536 #define ARM_ARCH_ALIAS(NAME, ID) \
9537 .Case(NAME, ARM::ID)
9538 #include "MCTargetDesc/ARMArchName.def"
9539 #undef ARM_ARCH_NAME
9540 #undef ARM_ARCH_ALIAS
9541 .Default(ARM::INVALID_ARCH);
9543 if (ID == ARM::INVALID_ARCH) {
9544 Error(ArchLoc, "unknown architecture '" + Arch + "'");
9545 Parser.eatToEndOfStatement();
9549 getTargetStreamer().emitObjectArch(ID);
9551 if (getLexer().isNot(AsmToken::EndOfStatement)) {
9552 Error(getLexer().getLoc(), "unexpected token");
9553 Parser.eatToEndOfStatement();
9559 /// parseDirectiveAlign
9561 bool ARMAsmParser::parseDirectiveAlign(SMLoc L) {
9562 // NOTE: if this is not the end of the statement, fall back to the target
9563 // agnostic handling for this directive which will correctly handle this.
9564 if (getLexer().isNot(AsmToken::EndOfStatement))
9567 // '.align' is target specifically handled to mean 2**2 byte alignment.
9568 if (getStreamer().getCurrentSection().first->UseCodeAlign())
9569 getStreamer().EmitCodeAlignment(4, 0);
9571 getStreamer().EmitValueToAlignment(4, 0, 1, 0);
9576 /// parseDirectiveThumbSet
9577 /// ::= .thumb_set name, value
9578 bool ARMAsmParser::parseDirectiveThumbSet(SMLoc L) {
9580 if (Parser.parseIdentifier(Name)) {
9581 TokError("expected identifier after '.thumb_set'");
9582 Parser.eatToEndOfStatement();
9586 if (getLexer().isNot(AsmToken::Comma)) {
9587 TokError("expected comma after name '" + Name + "'");
9588 Parser.eatToEndOfStatement();
9593 const MCExpr *Value;
9594 if (Parser.parseExpression(Value)) {
9595 TokError("missing expression");
9596 Parser.eatToEndOfStatement();
9600 if (getLexer().isNot(AsmToken::EndOfStatement)) {
9601 TokError("unexpected token");
9602 Parser.eatToEndOfStatement();
9607 MCSymbol *Alias = getContext().GetOrCreateSymbol(Name);
9608 getTargetStreamer().emitThumbSet(Alias, Value);
9612 /// Force static initialization.
9613 extern "C" void LLVMInitializeARMAsmParser() {
9614 RegisterMCAsmParser<ARMAsmParser> X(TheARMLETarget);
9615 RegisterMCAsmParser<ARMAsmParser> Y(TheARMBETarget);
9616 RegisterMCAsmParser<ARMAsmParser> A(TheThumbLETarget);
9617 RegisterMCAsmParser<ARMAsmParser> B(TheThumbBETarget);
9620 #define GET_REGISTER_MATCHER
9621 #define GET_SUBTARGET_FEATURE_NAME
9622 #define GET_MATCHER_IMPLEMENTATION
9623 #include "ARMGenAsmMatcher.inc"
9625 static const struct {
9627 const unsigned ArchCheck;
9628 const uint64_t Features;
9630 { "crc", Feature_HasV8, ARM::FeatureCRC },
9631 { "crypto", Feature_HasV8,
9632 ARM::FeatureCrypto | ARM::FeatureNEON | ARM::FeatureFPARMv8 },
9633 { "fp", Feature_HasV8, ARM::FeatureFPARMv8 },
9634 { "idiv", Feature_HasV7 | Feature_IsNotMClass,
9635 ARM::FeatureHWDiv | ARM::FeatureHWDivARM },
9636 // FIXME: iWMMXT not supported
9637 { "iwmmxt", Feature_None, 0 },
9638 // FIXME: iWMMXT2 not supported
9639 { "iwmmxt2", Feature_None, 0 },
9640 // FIXME: Maverick not supported
9641 { "maverick", Feature_None, 0 },
9642 { "mp", Feature_HasV7 | Feature_IsNotMClass, ARM::FeatureMP },
9643 // FIXME: ARMv6-m OS Extensions feature not checked
9644 { "os", Feature_None, 0 },
9645 // FIXME: Also available in ARMv6-K
9646 { "sec", Feature_HasV7, ARM::FeatureTrustZone },
9647 { "simd", Feature_HasV8, ARM::FeatureNEON | ARM::FeatureFPARMv8 },
9648 // FIXME: Only available in A-class, isel not predicated
9649 { "virt", Feature_HasV7, ARM::FeatureVirtualization },
9650 // FIXME: xscale not supported
9651 { "xscale", Feature_None, 0 },
9654 /// parseDirectiveArchExtension
9655 /// ::= .arch_extension [no]feature
9656 bool ARMAsmParser::parseDirectiveArchExtension(SMLoc L) {
9657 if (getLexer().isNot(AsmToken::Identifier)) {
9658 Error(getLexer().getLoc(), "unexpected token");
9659 Parser.eatToEndOfStatement();
9663 StringRef Name = Parser.getTok().getString();
9664 SMLoc ExtLoc = Parser.getTok().getLoc();
9667 bool EnableFeature = true;
9668 if (Name.startswith_lower("no")) {
9669 EnableFeature = false;
9670 Name = Name.substr(2);
9673 for (const auto &Extension : Extensions) {
9674 if (Extension.Name != Name)
9677 if (!Extension.Features)
9678 report_fatal_error("unsupported architectural extension: " + Name);
9680 if ((getAvailableFeatures() & Extension.ArchCheck) != Extension.ArchCheck) {
9681 Error(ExtLoc, "architectural extension '" + Name + "' is not "
9682 "allowed for the current base architecture");
9686 uint64_t ToggleFeatures = EnableFeature
9687 ? (~STI.getFeatureBits() & Extension.Features)
9688 : ( STI.getFeatureBits() & Extension.Features);
9690 ComputeAvailableFeatures(STI.ToggleFeature(ToggleFeatures));
9691 setAvailableFeatures(Features);
9695 Error(ExtLoc, "unknown architectural extension: " + Name);
9696 Parser.eatToEndOfStatement();
9700 // Define this matcher function after the auto-generated include so we
9701 // have the match class enum definitions.
9702 unsigned ARMAsmParser::validateTargetOperandClass(MCParsedAsmOperand &AsmOp,
9704 ARMOperand &Op = static_cast<ARMOperand &>(AsmOp);
9705 // If the kind is a token for a literal immediate, check if our asm
9706 // operand matches. This is for InstAliases which have a fixed-value
9707 // immediate in the syntax.
9712 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op.getImm()))
9713 if (CE->getValue() == 0)
9714 return Match_Success;
9718 const MCExpr *SOExpr = Op.getImm();
9720 if (!SOExpr->EvaluateAsAbsolute(Value))
9721 return Match_Success;
9722 assert((Value >= INT32_MIN && Value <= UINT32_MAX) &&
9723 "expression value must be representable in 32 bits");
9728 MRI->getRegClass(ARM::GPRRegClassID).contains(Op.getReg()))
9729 return Match_Success;
9732 return Match_InvalidOperand;