1 //===-- ARMAsmParser.cpp - Parse ARM assembly to MCInst instructions ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "ARMBuildAttrs.h"
11 #include "ARMFPUName.h"
12 #include "ARMFeatures.h"
13 #include "llvm/MC/MCTargetAsmParser.h"
14 #include "MCTargetDesc/ARMAddressingModes.h"
15 #include "MCTargetDesc/ARMArchName.h"
16 #include "MCTargetDesc/ARMBaseInfo.h"
17 #include "MCTargetDesc/ARMMCExpr.h"
18 #include "llvm/ADT/BitVector.h"
19 #include "llvm/ADT/OwningPtr.h"
20 #include "llvm/ADT/STLExtras.h"
21 #include "llvm/ADT/SmallVector.h"
22 #include "llvm/ADT/StringSwitch.h"
23 #include "llvm/ADT/Twine.h"
24 #include "llvm/MC/MCAsmInfo.h"
25 #include "llvm/MC/MCAssembler.h"
26 #include "llvm/MC/MCContext.h"
27 #include "llvm/MC/MCELFStreamer.h"
28 #include "llvm/MC/MCExpr.h"
29 #include "llvm/MC/MCInst.h"
30 #include "llvm/MC/MCInstrDesc.h"
31 #include "llvm/MC/MCInstrInfo.h"
32 #include "llvm/MC/MCParser/MCAsmLexer.h"
33 #include "llvm/MC/MCParser/MCAsmParser.h"
34 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
35 #include "llvm/MC/MCRegisterInfo.h"
36 #include "llvm/MC/MCStreamer.h"
37 #include "llvm/MC/MCSubtargetInfo.h"
38 #include "llvm/Support/ELF.h"
39 #include "llvm/Support/MathExtras.h"
40 #include "llvm/Support/SourceMgr.h"
41 #include "llvm/Support/TargetRegistry.h"
42 #include "llvm/Support/raw_ostream.h"
50 enum VectorLaneTy { NoLanes, AllLanes, IndexedLane };
52 class ARMAsmParser : public MCTargetAsmParser {
55 const MCInstrInfo &MII;
56 const MCRegisterInfo *MRI;
58 ARMTargetStreamer &getTargetStreamer() {
59 MCTargetStreamer &TS = getParser().getStreamer().getTargetStreamer();
60 return static_cast<ARMTargetStreamer &>(TS);
63 // Unwind directives state
69 void resetUnwindDirectiveParserState() {
71 CantUnwindLoc = SMLoc();
72 PersonalityLoc = SMLoc();
73 HandlerDataLoc = SMLoc();
77 // Map of register aliases registers via the .req directive.
78 StringMap<unsigned> RegisterReqs;
80 bool NextSymbolIsThumb;
83 ARMCC::CondCodes Cond; // Condition for IT block.
84 unsigned Mask:4; // Condition mask for instructions.
85 // Starting at first 1 (from lsb).
86 // '1' condition as indicated in IT.
87 // '0' inverse of condition (else).
88 // Count of instructions in IT block is
89 // 4 - trailingzeroes(mask)
91 bool FirstCond; // Explicit flag for when we're parsing the
92 // First instruction in the IT block. It's
93 // implied in the mask, so needs special
96 unsigned CurPosition; // Current position in parsing of IT
97 // block. In range [0,3]. Initialized
98 // according to count of instructions in block.
99 // ~0U if no active IT block.
101 bool inITBlock() { return ITState.CurPosition != ~0U;}
102 void forwardITPosition() {
103 if (!inITBlock()) return;
104 // Move to the next instruction in the IT block, if there is one. If not,
105 // mark the block as done.
106 unsigned TZ = countTrailingZeros(ITState.Mask);
107 if (++ITState.CurPosition == 5 - TZ)
108 ITState.CurPosition = ~0U; // Done with the IT block after this.
112 MCAsmParser &getParser() const { return Parser; }
113 MCAsmLexer &getLexer() const { return Parser.getLexer(); }
115 bool Warning(SMLoc L, const Twine &Msg,
116 ArrayRef<SMRange> Ranges = None) {
117 return Parser.Warning(L, Msg, Ranges);
119 bool Error(SMLoc L, const Twine &Msg,
120 ArrayRef<SMRange> Ranges = None) {
121 return Parser.Error(L, Msg, Ranges);
124 int tryParseRegister();
125 bool tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &);
126 int tryParseShiftRegister(SmallVectorImpl<MCParsedAsmOperand*> &);
127 bool parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &);
128 bool parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &);
129 bool parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &, StringRef Mnemonic);
130 bool parsePrefix(ARMMCExpr::VariantKind &RefKind);
131 bool parseMemRegOffsetShift(ARM_AM::ShiftOpc &ShiftType,
132 unsigned &ShiftAmount);
133 bool parseDirectiveWord(unsigned Size, SMLoc L);
134 bool parseDirectiveThumb(SMLoc L);
135 bool parseDirectiveARM(SMLoc L);
136 bool parseDirectiveThumbFunc(SMLoc L);
137 bool parseDirectiveCode(SMLoc L);
138 bool parseDirectiveSyntax(SMLoc L);
139 bool parseDirectiveReq(StringRef Name, SMLoc L);
140 bool parseDirectiveUnreq(SMLoc L);
141 bool parseDirectiveArch(SMLoc L);
142 bool parseDirectiveEabiAttr(SMLoc L);
143 bool parseDirectiveCPU(SMLoc L);
144 bool parseDirectiveFPU(SMLoc L);
145 bool parseDirectiveFnStart(SMLoc L);
146 bool parseDirectiveFnEnd(SMLoc L);
147 bool parseDirectiveCantUnwind(SMLoc L);
148 bool parseDirectivePersonality(SMLoc L);
149 bool parseDirectiveHandlerData(SMLoc L);
150 bool parseDirectiveSetFP(SMLoc L);
151 bool parseDirectivePad(SMLoc L);
152 bool parseDirectiveRegSave(SMLoc L, bool IsVector);
154 StringRef splitMnemonic(StringRef Mnemonic, unsigned &PredicationCode,
155 bool &CarrySetting, unsigned &ProcessorIMod,
157 void getMnemonicAcceptInfo(StringRef Mnemonic, StringRef FullInst,
158 bool &CanAcceptCarrySet,
159 bool &CanAcceptPredicationCode);
161 bool isThumb() const {
162 // FIXME: Can tablegen auto-generate this?
163 return (STI.getFeatureBits() & ARM::ModeThumb) != 0;
165 bool isThumbOne() const {
166 return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2) == 0;
168 bool isThumbTwo() const {
169 return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2);
171 bool hasThumb() const {
172 return STI.getFeatureBits() & ARM::HasV4TOps;
174 bool hasV6Ops() const {
175 return STI.getFeatureBits() & ARM::HasV6Ops;
177 bool hasV6MOps() const {
178 return STI.getFeatureBits() & ARM::HasV6MOps;
180 bool hasV7Ops() const {
181 return STI.getFeatureBits() & ARM::HasV7Ops;
183 bool hasV8Ops() const {
184 return STI.getFeatureBits() & ARM::HasV8Ops;
186 bool hasARM() const {
187 return !(STI.getFeatureBits() & ARM::FeatureNoARM);
191 unsigned FB = ComputeAvailableFeatures(STI.ToggleFeature(ARM::ModeThumb));
192 setAvailableFeatures(FB);
194 bool isMClass() const {
195 return STI.getFeatureBits() & ARM::FeatureMClass;
198 /// @name Auto-generated Match Functions
201 #define GET_ASSEMBLER_HEADER
202 #include "ARMGenAsmMatcher.inc"
206 OperandMatchResultTy parseITCondCode(SmallVectorImpl<MCParsedAsmOperand*>&);
207 OperandMatchResultTy parseCoprocNumOperand(
208 SmallVectorImpl<MCParsedAsmOperand*>&);
209 OperandMatchResultTy parseCoprocRegOperand(
210 SmallVectorImpl<MCParsedAsmOperand*>&);
211 OperandMatchResultTy parseCoprocOptionOperand(
212 SmallVectorImpl<MCParsedAsmOperand*>&);
213 OperandMatchResultTy parseMemBarrierOptOperand(
214 SmallVectorImpl<MCParsedAsmOperand*>&);
215 OperandMatchResultTy parseInstSyncBarrierOptOperand(
216 SmallVectorImpl<MCParsedAsmOperand*>&);
217 OperandMatchResultTy parseProcIFlagsOperand(
218 SmallVectorImpl<MCParsedAsmOperand*>&);
219 OperandMatchResultTy parseMSRMaskOperand(
220 SmallVectorImpl<MCParsedAsmOperand*>&);
221 OperandMatchResultTy parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &O,
222 StringRef Op, int Low, int High);
223 OperandMatchResultTy parsePKHLSLImm(SmallVectorImpl<MCParsedAsmOperand*> &O) {
224 return parsePKHImm(O, "lsl", 0, 31);
226 OperandMatchResultTy parsePKHASRImm(SmallVectorImpl<MCParsedAsmOperand*> &O) {
227 return parsePKHImm(O, "asr", 1, 32);
229 OperandMatchResultTy parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*>&);
230 OperandMatchResultTy parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*>&);
231 OperandMatchResultTy parseRotImm(SmallVectorImpl<MCParsedAsmOperand*>&);
232 OperandMatchResultTy parseBitfield(SmallVectorImpl<MCParsedAsmOperand*>&);
233 OperandMatchResultTy parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*>&);
234 OperandMatchResultTy parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*>&);
235 OperandMatchResultTy parseFPImm(SmallVectorImpl<MCParsedAsmOperand*>&);
236 OperandMatchResultTy parseVectorList(SmallVectorImpl<MCParsedAsmOperand*>&);
237 OperandMatchResultTy parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index,
240 // Asm Match Converter Methods
241 void cvtThumbMultiply(MCInst &Inst,
242 const SmallVectorImpl<MCParsedAsmOperand*> &);
243 void cvtThumbBranches(MCInst &Inst,
244 const SmallVectorImpl<MCParsedAsmOperand*> &);
246 bool validateInstruction(MCInst &Inst,
247 const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
248 bool processInstruction(MCInst &Inst,
249 const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
250 bool shouldOmitCCOutOperand(StringRef Mnemonic,
251 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
252 bool shouldOmitPredicateOperand(StringRef Mnemonic,
253 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
255 enum ARMMatchResultTy {
256 Match_RequiresITBlock = FIRST_TARGET_MATCH_RESULT_TY,
257 Match_RequiresNotITBlock,
259 Match_RequiresThumb2,
260 #define GET_OPERAND_DIAGNOSTIC_TYPES
261 #include "ARMGenAsmMatcher.inc"
265 ARMAsmParser(MCSubtargetInfo &_STI, MCAsmParser &_Parser,
266 const MCInstrInfo &MII)
267 : MCTargetAsmParser(), STI(_STI), Parser(_Parser), MII(MII), FPReg(-1) {
268 MCAsmParserExtension::Initialize(_Parser);
270 // Cache the MCRegisterInfo.
271 MRI = getContext().getRegisterInfo();
273 // Initialize the set of available features.
274 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
276 // Not in an ITBlock to start with.
277 ITState.CurPosition = ~0U;
279 NextSymbolIsThumb = false;
282 // Implementation of the MCTargetAsmParser interface:
283 bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc);
284 bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
286 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
287 bool ParseDirective(AsmToken DirectiveID);
289 unsigned validateTargetOperandClass(MCParsedAsmOperand *Op, unsigned Kind);
290 unsigned checkTargetMatchPredicate(MCInst &Inst);
292 bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
293 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
294 MCStreamer &Out, unsigned &ErrorInfo,
295 bool MatchingInlineAsm);
296 void onLabelParsed(MCSymbol *Symbol);
299 } // end anonymous namespace
303 /// ARMOperand - Instances of this class represent a parsed ARM machine
305 class ARMOperand : public MCParsedAsmOperand {
315 k_InstSyncBarrierOpt,
326 k_VectorListAllLanes,
332 k_BitfieldDescriptor,
336 SMLoc StartLoc, EndLoc;
337 SmallVector<unsigned, 8> Registers;
340 ARMCC::CondCodes Val;
347 struct CoprocOptionOp {
360 ARM_ISB::InstSyncBOpt Val;
364 ARM_PROC::IFlags Val;
380 // A vector register list is a sequential list of 1 to 4 registers.
381 struct VectorListOp {
388 struct VectorIndexOp {
396 /// Combined record for all forms of ARM address expressions.
399 // Offset is in OffsetReg or OffsetImm. If both are zero, no offset
401 const MCConstantExpr *OffsetImm; // Offset immediate value
402 unsigned OffsetRegNum; // Offset register num, when OffsetImm == NULL
403 ARM_AM::ShiftOpc ShiftType; // Shift type for OffsetReg
404 unsigned ShiftImm; // shift for OffsetReg.
405 unsigned Alignment; // 0 = no alignment specified
406 // n = alignment in bytes (2, 4, 8, 16, or 32)
407 unsigned isNegative : 1; // Negated OffsetReg? (~'U' bit)
410 struct PostIdxRegOp {
413 ARM_AM::ShiftOpc ShiftTy;
417 struct ShifterImmOp {
422 struct RegShiftedRegOp {
423 ARM_AM::ShiftOpc ShiftTy;
429 struct RegShiftedImmOp {
430 ARM_AM::ShiftOpc ShiftTy;
447 struct CoprocOptionOp CoprocOption;
448 struct MBOptOp MBOpt;
449 struct ISBOptOp ISBOpt;
450 struct ITMaskOp ITMask;
451 struct IFlagsOp IFlags;
452 struct MMaskOp MMask;
455 struct VectorListOp VectorList;
456 struct VectorIndexOp VectorIndex;
458 struct MemoryOp Memory;
459 struct PostIdxRegOp PostIdxReg;
460 struct ShifterImmOp ShifterImm;
461 struct RegShiftedRegOp RegShiftedReg;
462 struct RegShiftedImmOp RegShiftedImm;
463 struct RotImmOp RotImm;
464 struct BitfieldOp Bitfield;
467 ARMOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
469 ARMOperand(const ARMOperand &o) : MCParsedAsmOperand() {
471 StartLoc = o.StartLoc;
488 case k_DPRRegisterList:
489 case k_SPRRegisterList:
490 Registers = o.Registers;
493 case k_VectorListAllLanes:
494 case k_VectorListIndexed:
495 VectorList = o.VectorList;
502 CoprocOption = o.CoprocOption;
507 case k_MemBarrierOpt:
510 case k_InstSyncBarrierOpt:
515 case k_PostIndexRegister:
516 PostIdxReg = o.PostIdxReg;
524 case k_ShifterImmediate:
525 ShifterImm = o.ShifterImm;
527 case k_ShiftedRegister:
528 RegShiftedReg = o.RegShiftedReg;
530 case k_ShiftedImmediate:
531 RegShiftedImm = o.RegShiftedImm;
533 case k_RotateImmediate:
536 case k_BitfieldDescriptor:
537 Bitfield = o.Bitfield;
540 VectorIndex = o.VectorIndex;
545 /// getStartLoc - Get the location of the first token of this operand.
546 SMLoc getStartLoc() const { return StartLoc; }
547 /// getEndLoc - Get the location of the last token of this operand.
548 SMLoc getEndLoc() const { return EndLoc; }
549 /// getLocRange - Get the range between the first and last token of this
551 SMRange getLocRange() const { return SMRange(StartLoc, EndLoc); }
553 ARMCC::CondCodes getCondCode() const {
554 assert(Kind == k_CondCode && "Invalid access!");
558 unsigned getCoproc() const {
559 assert((Kind == k_CoprocNum || Kind == k_CoprocReg) && "Invalid access!");
563 StringRef getToken() const {
564 assert(Kind == k_Token && "Invalid access!");
565 return StringRef(Tok.Data, Tok.Length);
568 unsigned getReg() const {
569 assert((Kind == k_Register || Kind == k_CCOut) && "Invalid access!");
573 const SmallVectorImpl<unsigned> &getRegList() const {
574 assert((Kind == k_RegisterList || Kind == k_DPRRegisterList ||
575 Kind == k_SPRRegisterList) && "Invalid access!");
579 const MCExpr *getImm() const {
580 assert(isImm() && "Invalid access!");
584 unsigned getVectorIndex() const {
585 assert(Kind == k_VectorIndex && "Invalid access!");
586 return VectorIndex.Val;
589 ARM_MB::MemBOpt getMemBarrierOpt() const {
590 assert(Kind == k_MemBarrierOpt && "Invalid access!");
594 ARM_ISB::InstSyncBOpt getInstSyncBarrierOpt() const {
595 assert(Kind == k_InstSyncBarrierOpt && "Invalid access!");
599 ARM_PROC::IFlags getProcIFlags() const {
600 assert(Kind == k_ProcIFlags && "Invalid access!");
604 unsigned getMSRMask() const {
605 assert(Kind == k_MSRMask && "Invalid access!");
609 bool isCoprocNum() const { return Kind == k_CoprocNum; }
610 bool isCoprocReg() const { return Kind == k_CoprocReg; }
611 bool isCoprocOption() const { return Kind == k_CoprocOption; }
612 bool isCondCode() const { return Kind == k_CondCode; }
613 bool isCCOut() const { return Kind == k_CCOut; }
614 bool isITMask() const { return Kind == k_ITCondMask; }
615 bool isITCondCode() const { return Kind == k_CondCode; }
616 bool isImm() const { return Kind == k_Immediate; }
617 // checks whether this operand is an unsigned offset which fits is a field
618 // of specified width and scaled by a specific number of bits
619 template<unsigned width, unsigned scale>
620 bool isUnsignedOffset() const {
621 if (!isImm()) return false;
622 if (isa<MCSymbolRefExpr>(Imm.Val)) return true;
623 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val)) {
624 int64_t Val = CE->getValue();
625 int64_t Align = 1LL << scale;
626 int64_t Max = Align * ((1LL << width) - 1);
627 return ((Val % Align) == 0) && (Val >= 0) && (Val <= Max);
631 // checks whether this operand is an signed offset which fits is a field
632 // of specified width and scaled by a specific number of bits
633 template<unsigned width, unsigned scale>
634 bool isSignedOffset() const {
635 if (!isImm()) return false;
636 if (isa<MCSymbolRefExpr>(Imm.Val)) return true;
637 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val)) {
638 int64_t Val = CE->getValue();
639 int64_t Align = 1LL << scale;
640 int64_t Max = Align * ((1LL << (width-1)) - 1);
641 int64_t Min = -Align * (1LL << (width-1));
642 return ((Val % Align) == 0) && (Val >= Min) && (Val <= Max);
647 // checks whether this operand is a memory operand computed as an offset
648 // applied to PC. the offset may have 8 bits of magnitude and is represented
649 // with two bits of shift. textually it may be either [pc, #imm], #imm or
650 // relocable expression...
651 bool isThumbMemPC() const {
654 if (isa<MCSymbolRefExpr>(Imm.Val)) return true;
655 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val);
656 if (!CE) return false;
657 Val = CE->getValue();
660 if(!Memory.OffsetImm || Memory.OffsetRegNum) return false;
661 if(Memory.BaseRegNum != ARM::PC) return false;
662 Val = Memory.OffsetImm->getValue();
665 return ((Val % 4) == 0) && (Val >= 0) && (Val <= 1020);
667 bool isFPImm() const {
668 if (!isImm()) return false;
669 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
670 if (!CE) return false;
671 int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue()));
674 bool isFBits16() const {
675 if (!isImm()) return false;
676 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
677 if (!CE) return false;
678 int64_t Value = CE->getValue();
679 return Value >= 0 && Value <= 16;
681 bool isFBits32() const {
682 if (!isImm()) return false;
683 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
684 if (!CE) return false;
685 int64_t Value = CE->getValue();
686 return Value >= 1 && Value <= 32;
688 bool isImm8s4() const {
689 if (!isImm()) return false;
690 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
691 if (!CE) return false;
692 int64_t Value = CE->getValue();
693 return ((Value & 3) == 0) && Value >= -1020 && Value <= 1020;
695 bool isImm0_1020s4() const {
696 if (!isImm()) return false;
697 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
698 if (!CE) return false;
699 int64_t Value = CE->getValue();
700 return ((Value & 3) == 0) && Value >= 0 && Value <= 1020;
702 bool isImm0_508s4() const {
703 if (!isImm()) return false;
704 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
705 if (!CE) return false;
706 int64_t Value = CE->getValue();
707 return ((Value & 3) == 0) && Value >= 0 && Value <= 508;
709 bool isImm0_508s4Neg() const {
710 if (!isImm()) return false;
711 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
712 if (!CE) return false;
713 int64_t Value = -CE->getValue();
714 // explicitly exclude zero. we want that to use the normal 0_508 version.
715 return ((Value & 3) == 0) && Value > 0 && Value <= 508;
717 bool isImm0_239() const {
718 if (!isImm()) return false;
719 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
720 if (!CE) return false;
721 int64_t Value = CE->getValue();
722 return Value >= 0 && Value < 240;
724 bool isImm0_255() const {
725 if (!isImm()) return false;
726 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
727 if (!CE) return false;
728 int64_t Value = CE->getValue();
729 return Value >= 0 && Value < 256;
731 bool isImm0_4095() const {
732 if (!isImm()) return false;
733 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
734 if (!CE) return false;
735 int64_t Value = CE->getValue();
736 return Value >= 0 && Value < 4096;
738 bool isImm0_4095Neg() const {
739 if (!isImm()) return false;
740 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
741 if (!CE) return false;
742 int64_t Value = -CE->getValue();
743 return Value > 0 && Value < 4096;
745 bool isImm0_1() const {
746 if (!isImm()) return false;
747 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
748 if (!CE) return false;
749 int64_t Value = CE->getValue();
750 return Value >= 0 && Value < 2;
752 bool isImm0_3() const {
753 if (!isImm()) return false;
754 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
755 if (!CE) return false;
756 int64_t Value = CE->getValue();
757 return Value >= 0 && Value < 4;
759 bool isImm0_7() const {
760 if (!isImm()) return false;
761 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
762 if (!CE) return false;
763 int64_t Value = CE->getValue();
764 return Value >= 0 && Value < 8;
766 bool isImm0_15() const {
767 if (!isImm()) return false;
768 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
769 if (!CE) return false;
770 int64_t Value = CE->getValue();
771 return Value >= 0 && Value < 16;
773 bool isImm0_31() const {
774 if (!isImm()) return false;
775 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
776 if (!CE) return false;
777 int64_t Value = CE->getValue();
778 return Value >= 0 && Value < 32;
780 bool isImm0_63() const {
781 if (!isImm()) return false;
782 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
783 if (!CE) return false;
784 int64_t Value = CE->getValue();
785 return Value >= 0 && Value < 64;
787 bool isImm8() const {
788 if (!isImm()) return false;
789 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
790 if (!CE) return false;
791 int64_t Value = CE->getValue();
794 bool isImm16() const {
795 if (!isImm()) return false;
796 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
797 if (!CE) return false;
798 int64_t Value = CE->getValue();
801 bool isImm32() const {
802 if (!isImm()) return false;
803 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
804 if (!CE) return false;
805 int64_t Value = CE->getValue();
808 bool isShrImm8() const {
809 if (!isImm()) return false;
810 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
811 if (!CE) return false;
812 int64_t Value = CE->getValue();
813 return Value > 0 && Value <= 8;
815 bool isShrImm16() const {
816 if (!isImm()) return false;
817 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
818 if (!CE) return false;
819 int64_t Value = CE->getValue();
820 return Value > 0 && Value <= 16;
822 bool isShrImm32() const {
823 if (!isImm()) return false;
824 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
825 if (!CE) return false;
826 int64_t Value = CE->getValue();
827 return Value > 0 && Value <= 32;
829 bool isShrImm64() const {
830 if (!isImm()) return false;
831 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
832 if (!CE) return false;
833 int64_t Value = CE->getValue();
834 return Value > 0 && Value <= 64;
836 bool isImm1_7() const {
837 if (!isImm()) return false;
838 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
839 if (!CE) return false;
840 int64_t Value = CE->getValue();
841 return Value > 0 && Value < 8;
843 bool isImm1_15() const {
844 if (!isImm()) return false;
845 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
846 if (!CE) return false;
847 int64_t Value = CE->getValue();
848 return Value > 0 && Value < 16;
850 bool isImm1_31() const {
851 if (!isImm()) return false;
852 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
853 if (!CE) return false;
854 int64_t Value = CE->getValue();
855 return Value > 0 && Value < 32;
857 bool isImm1_16() const {
858 if (!isImm()) return false;
859 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
860 if (!CE) return false;
861 int64_t Value = CE->getValue();
862 return Value > 0 && Value < 17;
864 bool isImm1_32() const {
865 if (!isImm()) return false;
866 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
867 if (!CE) return false;
868 int64_t Value = CE->getValue();
869 return Value > 0 && Value < 33;
871 bool isImm0_32() const {
872 if (!isImm()) return false;
873 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
874 if (!CE) return false;
875 int64_t Value = CE->getValue();
876 return Value >= 0 && Value < 33;
878 bool isImm0_65535() const {
879 if (!isImm()) return false;
880 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
881 if (!CE) return false;
882 int64_t Value = CE->getValue();
883 return Value >= 0 && Value < 65536;
885 bool isImm256_65535Expr() const {
886 if (!isImm()) return false;
887 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
888 // If it's not a constant expression, it'll generate a fixup and be
890 if (!CE) return true;
891 int64_t Value = CE->getValue();
892 return Value >= 256 && Value < 65536;
894 bool isImm0_65535Expr() const {
895 if (!isImm()) return false;
896 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
897 // If it's not a constant expression, it'll generate a fixup and be
899 if (!CE) return true;
900 int64_t Value = CE->getValue();
901 return Value >= 0 && Value < 65536;
903 bool isImm24bit() const {
904 if (!isImm()) return false;
905 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
906 if (!CE) return false;
907 int64_t Value = CE->getValue();
908 return Value >= 0 && Value <= 0xffffff;
910 bool isImmThumbSR() const {
911 if (!isImm()) return false;
912 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
913 if (!CE) return false;
914 int64_t Value = CE->getValue();
915 return Value > 0 && Value < 33;
917 bool isPKHLSLImm() const {
918 if (!isImm()) return false;
919 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
920 if (!CE) return false;
921 int64_t Value = CE->getValue();
922 return Value >= 0 && Value < 32;
924 bool isPKHASRImm() const {
925 if (!isImm()) return false;
926 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
927 if (!CE) return false;
928 int64_t Value = CE->getValue();
929 return Value > 0 && Value <= 32;
931 bool isAdrLabel() const {
932 // If we have an immediate that's not a constant, treat it as a label
933 // reference needing a fixup. If it is a constant, but it can't fit
934 // into shift immediate encoding, we reject it.
935 if (isImm() && !isa<MCConstantExpr>(getImm())) return true;
936 else return (isARMSOImm() || isARMSOImmNeg());
938 bool isARMSOImm() const {
939 if (!isImm()) return false;
940 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
941 if (!CE) return false;
942 int64_t Value = CE->getValue();
943 return ARM_AM::getSOImmVal(Value) != -1;
945 bool isARMSOImmNot() const {
946 if (!isImm()) return false;
947 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
948 if (!CE) return false;
949 int64_t Value = CE->getValue();
950 return ARM_AM::getSOImmVal(~Value) != -1;
952 bool isARMSOImmNeg() const {
953 if (!isImm()) return false;
954 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
955 if (!CE) return false;
956 int64_t Value = CE->getValue();
957 // Only use this when not representable as a plain so_imm.
958 return ARM_AM::getSOImmVal(Value) == -1 &&
959 ARM_AM::getSOImmVal(-Value) != -1;
961 bool isT2SOImm() const {
962 if (!isImm()) return false;
963 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
964 if (!CE) return false;
965 int64_t Value = CE->getValue();
966 return ARM_AM::getT2SOImmVal(Value) != -1;
968 bool isT2SOImmNot() const {
969 if (!isImm()) return false;
970 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
971 if (!CE) return false;
972 int64_t Value = CE->getValue();
973 return ARM_AM::getT2SOImmVal(Value) == -1 &&
974 ARM_AM::getT2SOImmVal(~Value) != -1;
976 bool isT2SOImmNeg() const {
977 if (!isImm()) return false;
978 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
979 if (!CE) return false;
980 int64_t Value = CE->getValue();
981 // Only use this when not representable as a plain so_imm.
982 return ARM_AM::getT2SOImmVal(Value) == -1 &&
983 ARM_AM::getT2SOImmVal(-Value) != -1;
985 bool isSetEndImm() const {
986 if (!isImm()) return false;
987 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
988 if (!CE) return false;
989 int64_t Value = CE->getValue();
990 return Value == 1 || Value == 0;
992 bool isReg() const { return Kind == k_Register; }
993 bool isRegList() const { return Kind == k_RegisterList; }
994 bool isDPRRegList() const { return Kind == k_DPRRegisterList; }
995 bool isSPRRegList() const { return Kind == k_SPRRegisterList; }
996 bool isToken() const { return Kind == k_Token; }
997 bool isMemBarrierOpt() const { return Kind == k_MemBarrierOpt; }
998 bool isInstSyncBarrierOpt() const { return Kind == k_InstSyncBarrierOpt; }
999 bool isMem() const { return Kind == k_Memory; }
1000 bool isShifterImm() const { return Kind == k_ShifterImmediate; }
1001 bool isRegShiftedReg() const { return Kind == k_ShiftedRegister; }
1002 bool isRegShiftedImm() const { return Kind == k_ShiftedImmediate; }
1003 bool isRotImm() const { return Kind == k_RotateImmediate; }
1004 bool isBitfield() const { return Kind == k_BitfieldDescriptor; }
1005 bool isPostIdxRegShifted() const { return Kind == k_PostIndexRegister; }
1006 bool isPostIdxReg() const {
1007 return Kind == k_PostIndexRegister && PostIdxReg.ShiftTy ==ARM_AM::no_shift;
1009 bool isMemNoOffset(bool alignOK = false) const {
1012 // No offset of any kind.
1013 return Memory.OffsetRegNum == 0 && Memory.OffsetImm == 0 &&
1014 (alignOK || Memory.Alignment == 0);
1016 bool isMemPCRelImm12() const {
1017 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1019 // Base register must be PC.
1020 if (Memory.BaseRegNum != ARM::PC)
1022 // Immediate offset in range [-4095, 4095].
1023 if (!Memory.OffsetImm) return true;
1024 int64_t Val = Memory.OffsetImm->getValue();
1025 return (Val > -4096 && Val < 4096) || (Val == INT32_MIN);
1027 bool isAlignedMemory() const {
1028 return isMemNoOffset(true);
1030 bool isAddrMode2() const {
1031 if (!isMem() || Memory.Alignment != 0) return false;
1032 // Check for register offset.
1033 if (Memory.OffsetRegNum) return true;
1034 // Immediate offset in range [-4095, 4095].
1035 if (!Memory.OffsetImm) return true;
1036 int64_t Val = Memory.OffsetImm->getValue();
1037 return Val > -4096 && Val < 4096;
1039 bool isAM2OffsetImm() const {
1040 if (!isImm()) return false;
1041 // Immediate offset in range [-4095, 4095].
1042 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1043 if (!CE) return false;
1044 int64_t Val = CE->getValue();
1045 return (Val == INT32_MIN) || (Val > -4096 && Val < 4096);
1047 bool isAddrMode3() const {
1048 // If we have an immediate that's not a constant, treat it as a label
1049 // reference needing a fixup. If it is a constant, it's something else
1050 // and we reject it.
1051 if (isImm() && !isa<MCConstantExpr>(getImm()))
1053 if (!isMem() || Memory.Alignment != 0) return false;
1054 // No shifts are legal for AM3.
1055 if (Memory.ShiftType != ARM_AM::no_shift) return false;
1056 // Check for register offset.
1057 if (Memory.OffsetRegNum) return true;
1058 // Immediate offset in range [-255, 255].
1059 if (!Memory.OffsetImm) return true;
1060 int64_t Val = Memory.OffsetImm->getValue();
1061 // The #-0 offset is encoded as INT32_MIN, and we have to check
1063 return (Val > -256 && Val < 256) || Val == INT32_MIN;
1065 bool isAM3Offset() const {
1066 if (Kind != k_Immediate && Kind != k_PostIndexRegister)
1068 if (Kind == k_PostIndexRegister)
1069 return PostIdxReg.ShiftTy == ARM_AM::no_shift;
1070 // Immediate offset in range [-255, 255].
1071 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1072 if (!CE) return false;
1073 int64_t Val = CE->getValue();
1074 // Special case, #-0 is INT32_MIN.
1075 return (Val > -256 && Val < 256) || Val == INT32_MIN;
1077 bool isAddrMode5() const {
1078 // If we have an immediate that's not a constant, treat it as a label
1079 // reference needing a fixup. If it is a constant, it's something else
1080 // and we reject it.
1081 if (isImm() && !isa<MCConstantExpr>(getImm()))
1083 if (!isMem() || Memory.Alignment != 0) return false;
1084 // Check for register offset.
1085 if (Memory.OffsetRegNum) return false;
1086 // Immediate offset in range [-1020, 1020] and a multiple of 4.
1087 if (!Memory.OffsetImm) return true;
1088 int64_t Val = Memory.OffsetImm->getValue();
1089 return (Val >= -1020 && Val <= 1020 && ((Val & 3) == 0)) ||
1092 bool isMemTBB() const {
1093 if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1094 Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0)
1098 bool isMemTBH() const {
1099 if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1100 Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm != 1 ||
1101 Memory.Alignment != 0 )
1105 bool isMemRegOffset() const {
1106 if (!isMem() || !Memory.OffsetRegNum || Memory.Alignment != 0)
1110 bool isT2MemRegOffset() const {
1111 if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1112 Memory.Alignment != 0)
1114 // Only lsl #{0, 1, 2, 3} allowed.
1115 if (Memory.ShiftType == ARM_AM::no_shift)
1117 if (Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm > 3)
1121 bool isMemThumbRR() const {
1122 // Thumb reg+reg addressing is simple. Just two registers, a base and
1123 // an offset. No shifts, negations or any other complicating factors.
1124 if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1125 Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0)
1127 return isARMLowRegister(Memory.BaseRegNum) &&
1128 (!Memory.OffsetRegNum || isARMLowRegister(Memory.OffsetRegNum));
1130 bool isMemThumbRIs4() const {
1131 if (!isMem() || Memory.OffsetRegNum != 0 ||
1132 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
1134 // Immediate offset, multiple of 4 in range [0, 124].
1135 if (!Memory.OffsetImm) return true;
1136 int64_t Val = Memory.OffsetImm->getValue();
1137 return Val >= 0 && Val <= 124 && (Val % 4) == 0;
1139 bool isMemThumbRIs2() const {
1140 if (!isMem() || Memory.OffsetRegNum != 0 ||
1141 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
1143 // Immediate offset, multiple of 4 in range [0, 62].
1144 if (!Memory.OffsetImm) return true;
1145 int64_t Val = Memory.OffsetImm->getValue();
1146 return Val >= 0 && Val <= 62 && (Val % 2) == 0;
1148 bool isMemThumbRIs1() const {
1149 if (!isMem() || Memory.OffsetRegNum != 0 ||
1150 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
1152 // Immediate offset in range [0, 31].
1153 if (!Memory.OffsetImm) return true;
1154 int64_t Val = Memory.OffsetImm->getValue();
1155 return Val >= 0 && Val <= 31;
1157 bool isMemThumbSPI() const {
1158 if (!isMem() || Memory.OffsetRegNum != 0 ||
1159 Memory.BaseRegNum != ARM::SP || Memory.Alignment != 0)
1161 // Immediate offset, multiple of 4 in range [0, 1020].
1162 if (!Memory.OffsetImm) return true;
1163 int64_t Val = Memory.OffsetImm->getValue();
1164 return Val >= 0 && Val <= 1020 && (Val % 4) == 0;
1166 bool isMemImm8s4Offset() const {
1167 // If we have an immediate that's not a constant, treat it as a label
1168 // reference needing a fixup. If it is a constant, it's something else
1169 // and we reject it.
1170 if (isImm() && !isa<MCConstantExpr>(getImm()))
1172 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1174 // Immediate offset a multiple of 4 in range [-1020, 1020].
1175 if (!Memory.OffsetImm) return true;
1176 int64_t Val = Memory.OffsetImm->getValue();
1177 // Special case, #-0 is INT32_MIN.
1178 return (Val >= -1020 && Val <= 1020 && (Val & 3) == 0) || Val == INT32_MIN;
1180 bool isMemImm0_1020s4Offset() const {
1181 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1183 // Immediate offset a multiple of 4 in range [0, 1020].
1184 if (!Memory.OffsetImm) return true;
1185 int64_t Val = Memory.OffsetImm->getValue();
1186 return Val >= 0 && Val <= 1020 && (Val & 3) == 0;
1188 bool isMemImm8Offset() const {
1189 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1191 // Base reg of PC isn't allowed for these encodings.
1192 if (Memory.BaseRegNum == ARM::PC) return false;
1193 // Immediate offset in range [-255, 255].
1194 if (!Memory.OffsetImm) return true;
1195 int64_t Val = Memory.OffsetImm->getValue();
1196 return (Val == INT32_MIN) || (Val > -256 && Val < 256);
1198 bool isMemPosImm8Offset() const {
1199 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1201 // Immediate offset in range [0, 255].
1202 if (!Memory.OffsetImm) return true;
1203 int64_t Val = Memory.OffsetImm->getValue();
1204 return Val >= 0 && Val < 256;
1206 bool isMemNegImm8Offset() const {
1207 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1209 // Base reg of PC isn't allowed for these encodings.
1210 if (Memory.BaseRegNum == ARM::PC) return false;
1211 // Immediate offset in range [-255, -1].
1212 if (!Memory.OffsetImm) return false;
1213 int64_t Val = Memory.OffsetImm->getValue();
1214 return (Val == INT32_MIN) || (Val > -256 && Val < 0);
1216 bool isMemUImm12Offset() const {
1217 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1219 // Immediate offset in range [0, 4095].
1220 if (!Memory.OffsetImm) return true;
1221 int64_t Val = Memory.OffsetImm->getValue();
1222 return (Val >= 0 && Val < 4096);
1224 bool isMemImm12Offset() const {
1225 // If we have an immediate that's not a constant, treat it as a label
1226 // reference needing a fixup. If it is a constant, it's something else
1227 // and we reject it.
1228 if (isImm() && !isa<MCConstantExpr>(getImm()))
1231 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1233 // Immediate offset in range [-4095, 4095].
1234 if (!Memory.OffsetImm) return true;
1235 int64_t Val = Memory.OffsetImm->getValue();
1236 return (Val > -4096 && Val < 4096) || (Val == INT32_MIN);
1238 bool isPostIdxImm8() const {
1239 if (!isImm()) return false;
1240 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1241 if (!CE) return false;
1242 int64_t Val = CE->getValue();
1243 return (Val > -256 && Val < 256) || (Val == INT32_MIN);
1245 bool isPostIdxImm8s4() const {
1246 if (!isImm()) return false;
1247 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1248 if (!CE) return false;
1249 int64_t Val = CE->getValue();
1250 return ((Val & 3) == 0 && Val >= -1020 && Val <= 1020) ||
1254 bool isMSRMask() const { return Kind == k_MSRMask; }
1255 bool isProcIFlags() const { return Kind == k_ProcIFlags; }
1258 bool isSingleSpacedVectorList() const {
1259 return Kind == k_VectorList && !VectorList.isDoubleSpaced;
1261 bool isDoubleSpacedVectorList() const {
1262 return Kind == k_VectorList && VectorList.isDoubleSpaced;
1264 bool isVecListOneD() const {
1265 if (!isSingleSpacedVectorList()) return false;
1266 return VectorList.Count == 1;
1269 bool isVecListDPair() const {
1270 if (!isSingleSpacedVectorList()) return false;
1271 return (ARMMCRegisterClasses[ARM::DPairRegClassID]
1272 .contains(VectorList.RegNum));
1275 bool isVecListThreeD() const {
1276 if (!isSingleSpacedVectorList()) return false;
1277 return VectorList.Count == 3;
1280 bool isVecListFourD() const {
1281 if (!isSingleSpacedVectorList()) return false;
1282 return VectorList.Count == 4;
1285 bool isVecListDPairSpaced() const {
1286 if (isSingleSpacedVectorList()) return false;
1287 return (ARMMCRegisterClasses[ARM::DPairSpcRegClassID]
1288 .contains(VectorList.RegNum));
1291 bool isVecListThreeQ() const {
1292 if (!isDoubleSpacedVectorList()) return false;
1293 return VectorList.Count == 3;
1296 bool isVecListFourQ() const {
1297 if (!isDoubleSpacedVectorList()) return false;
1298 return VectorList.Count == 4;
1301 bool isSingleSpacedVectorAllLanes() const {
1302 return Kind == k_VectorListAllLanes && !VectorList.isDoubleSpaced;
1304 bool isDoubleSpacedVectorAllLanes() const {
1305 return Kind == k_VectorListAllLanes && VectorList.isDoubleSpaced;
1307 bool isVecListOneDAllLanes() const {
1308 if (!isSingleSpacedVectorAllLanes()) return false;
1309 return VectorList.Count == 1;
1312 bool isVecListDPairAllLanes() const {
1313 if (!isSingleSpacedVectorAllLanes()) return false;
1314 return (ARMMCRegisterClasses[ARM::DPairRegClassID]
1315 .contains(VectorList.RegNum));
1318 bool isVecListDPairSpacedAllLanes() const {
1319 if (!isDoubleSpacedVectorAllLanes()) return false;
1320 return VectorList.Count == 2;
1323 bool isVecListThreeDAllLanes() const {
1324 if (!isSingleSpacedVectorAllLanes()) return false;
1325 return VectorList.Count == 3;
1328 bool isVecListThreeQAllLanes() const {
1329 if (!isDoubleSpacedVectorAllLanes()) return false;
1330 return VectorList.Count == 3;
1333 bool isVecListFourDAllLanes() const {
1334 if (!isSingleSpacedVectorAllLanes()) return false;
1335 return VectorList.Count == 4;
1338 bool isVecListFourQAllLanes() const {
1339 if (!isDoubleSpacedVectorAllLanes()) return false;
1340 return VectorList.Count == 4;
1343 bool isSingleSpacedVectorIndexed() const {
1344 return Kind == k_VectorListIndexed && !VectorList.isDoubleSpaced;
1346 bool isDoubleSpacedVectorIndexed() const {
1347 return Kind == k_VectorListIndexed && VectorList.isDoubleSpaced;
1349 bool isVecListOneDByteIndexed() const {
1350 if (!isSingleSpacedVectorIndexed()) return false;
1351 return VectorList.Count == 1 && VectorList.LaneIndex <= 7;
1354 bool isVecListOneDHWordIndexed() const {
1355 if (!isSingleSpacedVectorIndexed()) return false;
1356 return VectorList.Count == 1 && VectorList.LaneIndex <= 3;
1359 bool isVecListOneDWordIndexed() const {
1360 if (!isSingleSpacedVectorIndexed()) return false;
1361 return VectorList.Count == 1 && VectorList.LaneIndex <= 1;
1364 bool isVecListTwoDByteIndexed() const {
1365 if (!isSingleSpacedVectorIndexed()) return false;
1366 return VectorList.Count == 2 && VectorList.LaneIndex <= 7;
1369 bool isVecListTwoDHWordIndexed() const {
1370 if (!isSingleSpacedVectorIndexed()) return false;
1371 return VectorList.Count == 2 && VectorList.LaneIndex <= 3;
1374 bool isVecListTwoQWordIndexed() const {
1375 if (!isDoubleSpacedVectorIndexed()) return false;
1376 return VectorList.Count == 2 && VectorList.LaneIndex <= 1;
1379 bool isVecListTwoQHWordIndexed() const {
1380 if (!isDoubleSpacedVectorIndexed()) return false;
1381 return VectorList.Count == 2 && VectorList.LaneIndex <= 3;
1384 bool isVecListTwoDWordIndexed() const {
1385 if (!isSingleSpacedVectorIndexed()) return false;
1386 return VectorList.Count == 2 && VectorList.LaneIndex <= 1;
1389 bool isVecListThreeDByteIndexed() const {
1390 if (!isSingleSpacedVectorIndexed()) return false;
1391 return VectorList.Count == 3 && VectorList.LaneIndex <= 7;
1394 bool isVecListThreeDHWordIndexed() const {
1395 if (!isSingleSpacedVectorIndexed()) return false;
1396 return VectorList.Count == 3 && VectorList.LaneIndex <= 3;
1399 bool isVecListThreeQWordIndexed() const {
1400 if (!isDoubleSpacedVectorIndexed()) return false;
1401 return VectorList.Count == 3 && VectorList.LaneIndex <= 1;
1404 bool isVecListThreeQHWordIndexed() const {
1405 if (!isDoubleSpacedVectorIndexed()) return false;
1406 return VectorList.Count == 3 && VectorList.LaneIndex <= 3;
1409 bool isVecListThreeDWordIndexed() const {
1410 if (!isSingleSpacedVectorIndexed()) return false;
1411 return VectorList.Count == 3 && VectorList.LaneIndex <= 1;
1414 bool isVecListFourDByteIndexed() const {
1415 if (!isSingleSpacedVectorIndexed()) return false;
1416 return VectorList.Count == 4 && VectorList.LaneIndex <= 7;
1419 bool isVecListFourDHWordIndexed() const {
1420 if (!isSingleSpacedVectorIndexed()) return false;
1421 return VectorList.Count == 4 && VectorList.LaneIndex <= 3;
1424 bool isVecListFourQWordIndexed() const {
1425 if (!isDoubleSpacedVectorIndexed()) return false;
1426 return VectorList.Count == 4 && VectorList.LaneIndex <= 1;
1429 bool isVecListFourQHWordIndexed() const {
1430 if (!isDoubleSpacedVectorIndexed()) return false;
1431 return VectorList.Count == 4 && VectorList.LaneIndex <= 3;
1434 bool isVecListFourDWordIndexed() const {
1435 if (!isSingleSpacedVectorIndexed()) return false;
1436 return VectorList.Count == 4 && VectorList.LaneIndex <= 1;
1439 bool isVectorIndex8() const {
1440 if (Kind != k_VectorIndex) return false;
1441 return VectorIndex.Val < 8;
1443 bool isVectorIndex16() const {
1444 if (Kind != k_VectorIndex) return false;
1445 return VectorIndex.Val < 4;
1447 bool isVectorIndex32() const {
1448 if (Kind != k_VectorIndex) return false;
1449 return VectorIndex.Val < 2;
1452 bool isNEONi8splat() const {
1453 if (!isImm()) return false;
1454 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1455 // Must be a constant.
1456 if (!CE) return false;
1457 int64_t Value = CE->getValue();
1458 // i8 value splatted across 8 bytes. The immediate is just the 8 byte
1460 return Value >= 0 && Value < 256;
1463 bool isNEONi16splat() const {
1464 if (!isImm()) return false;
1465 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1466 // Must be a constant.
1467 if (!CE) return false;
1468 int64_t Value = CE->getValue();
1469 // i16 value in the range [0,255] or [0x0100, 0xff00]
1470 return (Value >= 0 && Value < 256) || (Value >= 0x0100 && Value <= 0xff00);
1473 bool isNEONi32splat() const {
1474 if (!isImm()) return false;
1475 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1476 // Must be a constant.
1477 if (!CE) return false;
1478 int64_t Value = CE->getValue();
1479 // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X.
1480 return (Value >= 0 && Value < 256) ||
1481 (Value >= 0x0100 && Value <= 0xff00) ||
1482 (Value >= 0x010000 && Value <= 0xff0000) ||
1483 (Value >= 0x01000000 && Value <= 0xff000000);
1486 bool isNEONi32vmov() const {
1487 if (!isImm()) return false;
1488 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1489 // Must be a constant.
1490 if (!CE) return false;
1491 int64_t Value = CE->getValue();
1492 // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X,
1493 // for VMOV/VMVN only, 00Xf or 0Xff are also accepted.
1494 return (Value >= 0 && Value < 256) ||
1495 (Value >= 0x0100 && Value <= 0xff00) ||
1496 (Value >= 0x010000 && Value <= 0xff0000) ||
1497 (Value >= 0x01000000 && Value <= 0xff000000) ||
1498 (Value >= 0x01ff && Value <= 0xffff && (Value & 0xff) == 0xff) ||
1499 (Value >= 0x01ffff && Value <= 0xffffff && (Value & 0xffff) == 0xffff);
1501 bool isNEONi32vmovNeg() const {
1502 if (!isImm()) return false;
1503 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1504 // Must be a constant.
1505 if (!CE) return false;
1506 int64_t Value = ~CE->getValue();
1507 // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X,
1508 // for VMOV/VMVN only, 00Xf or 0Xff are also accepted.
1509 return (Value >= 0 && Value < 256) ||
1510 (Value >= 0x0100 && Value <= 0xff00) ||
1511 (Value >= 0x010000 && Value <= 0xff0000) ||
1512 (Value >= 0x01000000 && Value <= 0xff000000) ||
1513 (Value >= 0x01ff && Value <= 0xffff && (Value & 0xff) == 0xff) ||
1514 (Value >= 0x01ffff && Value <= 0xffffff && (Value & 0xffff) == 0xffff);
1517 bool isNEONi64splat() const {
1518 if (!isImm()) return false;
1519 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1520 // Must be a constant.
1521 if (!CE) return false;
1522 uint64_t Value = CE->getValue();
1523 // i64 value with each byte being either 0 or 0xff.
1524 for (unsigned i = 0; i < 8; ++i)
1525 if ((Value & 0xff) != 0 && (Value & 0xff) != 0xff) return false;
1529 void addExpr(MCInst &Inst, const MCExpr *Expr) const {
1530 // Add as immediates when possible. Null MCExpr = 0.
1532 Inst.addOperand(MCOperand::CreateImm(0));
1533 else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
1534 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
1536 Inst.addOperand(MCOperand::CreateExpr(Expr));
1539 void addCondCodeOperands(MCInst &Inst, unsigned N) const {
1540 assert(N == 2 && "Invalid number of operands!");
1541 Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
1542 unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR;
1543 Inst.addOperand(MCOperand::CreateReg(RegNum));
1546 void addCoprocNumOperands(MCInst &Inst, unsigned N) const {
1547 assert(N == 1 && "Invalid number of operands!");
1548 Inst.addOperand(MCOperand::CreateImm(getCoproc()));
1551 void addCoprocRegOperands(MCInst &Inst, unsigned N) const {
1552 assert(N == 1 && "Invalid number of operands!");
1553 Inst.addOperand(MCOperand::CreateImm(getCoproc()));
1556 void addCoprocOptionOperands(MCInst &Inst, unsigned N) const {
1557 assert(N == 1 && "Invalid number of operands!");
1558 Inst.addOperand(MCOperand::CreateImm(CoprocOption.Val));
1561 void addITMaskOperands(MCInst &Inst, unsigned N) const {
1562 assert(N == 1 && "Invalid number of operands!");
1563 Inst.addOperand(MCOperand::CreateImm(ITMask.Mask));
1566 void addITCondCodeOperands(MCInst &Inst, unsigned N) const {
1567 assert(N == 1 && "Invalid number of operands!");
1568 Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
1571 void addCCOutOperands(MCInst &Inst, unsigned N) const {
1572 assert(N == 1 && "Invalid number of operands!");
1573 Inst.addOperand(MCOperand::CreateReg(getReg()));
1576 void addRegOperands(MCInst &Inst, unsigned N) const {
1577 assert(N == 1 && "Invalid number of operands!");
1578 Inst.addOperand(MCOperand::CreateReg(getReg()));
1581 void addRegShiftedRegOperands(MCInst &Inst, unsigned N) const {
1582 assert(N == 3 && "Invalid number of operands!");
1583 assert(isRegShiftedReg() &&
1584 "addRegShiftedRegOperands() on non-RegShiftedReg!");
1585 Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.SrcReg));
1586 Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.ShiftReg));
1587 Inst.addOperand(MCOperand::CreateImm(
1588 ARM_AM::getSORegOpc(RegShiftedReg.ShiftTy, RegShiftedReg.ShiftImm)));
1591 void addRegShiftedImmOperands(MCInst &Inst, unsigned N) const {
1592 assert(N == 2 && "Invalid number of operands!");
1593 assert(isRegShiftedImm() &&
1594 "addRegShiftedImmOperands() on non-RegShiftedImm!");
1595 Inst.addOperand(MCOperand::CreateReg(RegShiftedImm.SrcReg));
1596 // Shift of #32 is encoded as 0 where permitted
1597 unsigned Imm = (RegShiftedImm.ShiftImm == 32 ? 0 : RegShiftedImm.ShiftImm);
1598 Inst.addOperand(MCOperand::CreateImm(
1599 ARM_AM::getSORegOpc(RegShiftedImm.ShiftTy, Imm)));
1602 void addShifterImmOperands(MCInst &Inst, unsigned N) const {
1603 assert(N == 1 && "Invalid number of operands!");
1604 Inst.addOperand(MCOperand::CreateImm((ShifterImm.isASR << 5) |
1608 void addRegListOperands(MCInst &Inst, unsigned N) const {
1609 assert(N == 1 && "Invalid number of operands!");
1610 const SmallVectorImpl<unsigned> &RegList = getRegList();
1611 for (SmallVectorImpl<unsigned>::const_iterator
1612 I = RegList.begin(), E = RegList.end(); I != E; ++I)
1613 Inst.addOperand(MCOperand::CreateReg(*I));
1616 void addDPRRegListOperands(MCInst &Inst, unsigned N) const {
1617 addRegListOperands(Inst, N);
1620 void addSPRRegListOperands(MCInst &Inst, unsigned N) const {
1621 addRegListOperands(Inst, N);
1624 void addRotImmOperands(MCInst &Inst, unsigned N) const {
1625 assert(N == 1 && "Invalid number of operands!");
1626 // Encoded as val>>3. The printer handles display as 8, 16, 24.
1627 Inst.addOperand(MCOperand::CreateImm(RotImm.Imm >> 3));
1630 void addBitfieldOperands(MCInst &Inst, unsigned N) const {
1631 assert(N == 1 && "Invalid number of operands!");
1632 // Munge the lsb/width into a bitfield mask.
1633 unsigned lsb = Bitfield.LSB;
1634 unsigned width = Bitfield.Width;
1635 // Make a 32-bit mask w/ the referenced bits clear and all other bits set.
1636 uint32_t Mask = ~(((uint32_t)0xffffffff >> lsb) << (32 - width) >>
1637 (32 - (lsb + width)));
1638 Inst.addOperand(MCOperand::CreateImm(Mask));
1641 void addImmOperands(MCInst &Inst, unsigned N) const {
1642 assert(N == 1 && "Invalid number of operands!");
1643 addExpr(Inst, getImm());
1646 void addFBits16Operands(MCInst &Inst, unsigned N) const {
1647 assert(N == 1 && "Invalid number of operands!");
1648 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1649 Inst.addOperand(MCOperand::CreateImm(16 - CE->getValue()));
1652 void addFBits32Operands(MCInst &Inst, unsigned N) const {
1653 assert(N == 1 && "Invalid number of operands!");
1654 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1655 Inst.addOperand(MCOperand::CreateImm(32 - CE->getValue()));
1658 void addFPImmOperands(MCInst &Inst, unsigned N) const {
1659 assert(N == 1 && "Invalid number of operands!");
1660 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1661 int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue()));
1662 Inst.addOperand(MCOperand::CreateImm(Val));
1665 void addImm8s4Operands(MCInst &Inst, unsigned N) const {
1666 assert(N == 1 && "Invalid number of operands!");
1667 // FIXME: We really want to scale the value here, but the LDRD/STRD
1668 // instruction don't encode operands that way yet.
1669 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1670 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
1673 void addImm0_1020s4Operands(MCInst &Inst, unsigned N) const {
1674 assert(N == 1 && "Invalid number of operands!");
1675 // The immediate is scaled by four in the encoding and is stored
1676 // in the MCInst as such. Lop off the low two bits here.
1677 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1678 Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4));
1681 void addImm0_508s4NegOperands(MCInst &Inst, unsigned N) const {
1682 assert(N == 1 && "Invalid number of operands!");
1683 // The immediate is scaled by four in the encoding and is stored
1684 // in the MCInst as such. Lop off the low two bits here.
1685 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1686 Inst.addOperand(MCOperand::CreateImm(-(CE->getValue() / 4)));
1689 void addImm0_508s4Operands(MCInst &Inst, unsigned N) const {
1690 assert(N == 1 && "Invalid number of operands!");
1691 // The immediate is scaled by four in the encoding and is stored
1692 // in the MCInst as such. Lop off the low two bits here.
1693 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1694 Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4));
1697 void addImm1_16Operands(MCInst &Inst, unsigned N) const {
1698 assert(N == 1 && "Invalid number of operands!");
1699 // The constant encodes as the immediate-1, and we store in the instruction
1700 // the bits as encoded, so subtract off one here.
1701 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1702 Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
1705 void addImm1_32Operands(MCInst &Inst, unsigned N) const {
1706 assert(N == 1 && "Invalid number of operands!");
1707 // The constant encodes as the immediate-1, and we store in the instruction
1708 // the bits as encoded, so subtract off one here.
1709 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1710 Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
1713 void addImmThumbSROperands(MCInst &Inst, unsigned N) const {
1714 assert(N == 1 && "Invalid number of operands!");
1715 // The constant encodes as the immediate, except for 32, which encodes as
1717 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1718 unsigned Imm = CE->getValue();
1719 Inst.addOperand(MCOperand::CreateImm((Imm == 32 ? 0 : Imm)));
1722 void addPKHASRImmOperands(MCInst &Inst, unsigned N) const {
1723 assert(N == 1 && "Invalid number of operands!");
1724 // An ASR value of 32 encodes as 0, so that's how we want to add it to
1725 // the instruction as well.
1726 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1727 int Val = CE->getValue();
1728 Inst.addOperand(MCOperand::CreateImm(Val == 32 ? 0 : Val));
1731 void addT2SOImmNotOperands(MCInst &Inst, unsigned N) const {
1732 assert(N == 1 && "Invalid number of operands!");
1733 // The operand is actually a t2_so_imm, but we have its bitwise
1734 // negation in the assembly source, so twiddle it here.
1735 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1736 Inst.addOperand(MCOperand::CreateImm(~CE->getValue()));
1739 void addT2SOImmNegOperands(MCInst &Inst, unsigned N) const {
1740 assert(N == 1 && "Invalid number of operands!");
1741 // The operand is actually a t2_so_imm, but we have its
1742 // negation in the assembly source, so twiddle it here.
1743 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1744 Inst.addOperand(MCOperand::CreateImm(-CE->getValue()));
1747 void addImm0_4095NegOperands(MCInst &Inst, unsigned N) const {
1748 assert(N == 1 && "Invalid number of operands!");
1749 // The operand is actually an imm0_4095, but we have its
1750 // negation in the assembly source, so twiddle it here.
1751 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1752 Inst.addOperand(MCOperand::CreateImm(-CE->getValue()));
1755 void addUnsignedOffset_b8s2Operands(MCInst &Inst, unsigned N) const {
1756 if(const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm())) {
1757 Inst.addOperand(MCOperand::CreateImm(CE->getValue() >> 2));
1761 const MCSymbolRefExpr *SR = dyn_cast<MCSymbolRefExpr>(Imm.Val);
1762 assert(SR && "Unknown value type!");
1763 Inst.addOperand(MCOperand::CreateExpr(SR));
1766 void addThumbMemPCOperands(MCInst &Inst, unsigned N) const {
1767 assert(N == 1 && "Invalid number of operands!");
1769 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1771 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
1775 const MCSymbolRefExpr *SR = dyn_cast<MCSymbolRefExpr>(Imm.Val);
1776 assert(SR && "Unknown value type!");
1777 Inst.addOperand(MCOperand::CreateExpr(SR));
1781 assert(isMem() && "Unknown value type!");
1782 assert(isa<MCConstantExpr>(Memory.OffsetImm) && "Unknown value type!");
1783 Inst.addOperand(MCOperand::CreateImm(Memory.OffsetImm->getValue()));
1786 void addARMSOImmNotOperands(MCInst &Inst, unsigned N) const {
1787 assert(N == 1 && "Invalid number of operands!");
1788 // The operand is actually a so_imm, but we have its bitwise
1789 // negation in the assembly source, so twiddle it here.
1790 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1791 Inst.addOperand(MCOperand::CreateImm(~CE->getValue()));
1794 void addARMSOImmNegOperands(MCInst &Inst, unsigned N) const {
1795 assert(N == 1 && "Invalid number of operands!");
1796 // The operand is actually a so_imm, but we have its
1797 // negation in the assembly source, so twiddle it here.
1798 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1799 Inst.addOperand(MCOperand::CreateImm(-CE->getValue()));
1802 void addMemBarrierOptOperands(MCInst &Inst, unsigned N) const {
1803 assert(N == 1 && "Invalid number of operands!");
1804 Inst.addOperand(MCOperand::CreateImm(unsigned(getMemBarrierOpt())));
1807 void addInstSyncBarrierOptOperands(MCInst &Inst, unsigned N) const {
1808 assert(N == 1 && "Invalid number of operands!");
1809 Inst.addOperand(MCOperand::CreateImm(unsigned(getInstSyncBarrierOpt())));
1812 void addMemNoOffsetOperands(MCInst &Inst, unsigned N) const {
1813 assert(N == 1 && "Invalid number of operands!");
1814 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1817 void addMemPCRelImm12Operands(MCInst &Inst, unsigned N) const {
1818 assert(N == 1 && "Invalid number of operands!");
1819 int32_t Imm = Memory.OffsetImm->getValue();
1820 Inst.addOperand(MCOperand::CreateImm(Imm));
1823 void addAdrLabelOperands(MCInst &Inst, unsigned N) const {
1824 assert(N == 1 && "Invalid number of operands!");
1825 assert(isImm() && "Not an immediate!");
1827 // If we have an immediate that's not a constant, treat it as a label
1828 // reference needing a fixup.
1829 if (!isa<MCConstantExpr>(getImm())) {
1830 Inst.addOperand(MCOperand::CreateExpr(getImm()));
1834 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1835 int Val = CE->getValue();
1836 Inst.addOperand(MCOperand::CreateImm(Val));
1839 void addAlignedMemoryOperands(MCInst &Inst, unsigned N) const {
1840 assert(N == 2 && "Invalid number of operands!");
1841 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1842 Inst.addOperand(MCOperand::CreateImm(Memory.Alignment));
1845 void addAddrMode2Operands(MCInst &Inst, unsigned N) const {
1846 assert(N == 3 && "Invalid number of operands!");
1847 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1848 if (!Memory.OffsetRegNum) {
1849 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1850 // Special case for #-0
1851 if (Val == INT32_MIN) Val = 0;
1852 if (Val < 0) Val = -Val;
1853 Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
1855 // For register offset, we encode the shift type and negation flag
1857 Val = ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add,
1858 Memory.ShiftImm, Memory.ShiftType);
1860 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1861 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1862 Inst.addOperand(MCOperand::CreateImm(Val));
1865 void addAM2OffsetImmOperands(MCInst &Inst, unsigned N) const {
1866 assert(N == 2 && "Invalid number of operands!");
1867 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1868 assert(CE && "non-constant AM2OffsetImm operand!");
1869 int32_t Val = CE->getValue();
1870 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1871 // Special case for #-0
1872 if (Val == INT32_MIN) Val = 0;
1873 if (Val < 0) Val = -Val;
1874 Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
1875 Inst.addOperand(MCOperand::CreateReg(0));
1876 Inst.addOperand(MCOperand::CreateImm(Val));
1879 void addAddrMode3Operands(MCInst &Inst, unsigned N) const {
1880 assert(N == 3 && "Invalid number of operands!");
1881 // If we have an immediate that's not a constant, treat it as a label
1882 // reference needing a fixup. If it is a constant, it's something else
1883 // and we reject it.
1885 Inst.addOperand(MCOperand::CreateExpr(getImm()));
1886 Inst.addOperand(MCOperand::CreateReg(0));
1887 Inst.addOperand(MCOperand::CreateImm(0));
1891 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1892 if (!Memory.OffsetRegNum) {
1893 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1894 // Special case for #-0
1895 if (Val == INT32_MIN) Val = 0;
1896 if (Val < 0) Val = -Val;
1897 Val = ARM_AM::getAM3Opc(AddSub, Val);
1899 // For register offset, we encode the shift type and negation flag
1901 Val = ARM_AM::getAM3Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add, 0);
1903 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1904 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1905 Inst.addOperand(MCOperand::CreateImm(Val));
1908 void addAM3OffsetOperands(MCInst &Inst, unsigned N) const {
1909 assert(N == 2 && "Invalid number of operands!");
1910 if (Kind == k_PostIndexRegister) {
1912 ARM_AM::getAM3Opc(PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub, 0);
1913 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
1914 Inst.addOperand(MCOperand::CreateImm(Val));
1919 const MCConstantExpr *CE = static_cast<const MCConstantExpr*>(getImm());
1920 int32_t Val = CE->getValue();
1921 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1922 // Special case for #-0
1923 if (Val == INT32_MIN) Val = 0;
1924 if (Val < 0) Val = -Val;
1925 Val = ARM_AM::getAM3Opc(AddSub, Val);
1926 Inst.addOperand(MCOperand::CreateReg(0));
1927 Inst.addOperand(MCOperand::CreateImm(Val));
1930 void addAddrMode5Operands(MCInst &Inst, unsigned N) const {
1931 assert(N == 2 && "Invalid number of operands!");
1932 // If we have an immediate that's not a constant, treat it as a label
1933 // reference needing a fixup. If it is a constant, it's something else
1934 // and we reject it.
1936 Inst.addOperand(MCOperand::CreateExpr(getImm()));
1937 Inst.addOperand(MCOperand::CreateImm(0));
1941 // The lower two bits are always zero and as such are not encoded.
1942 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0;
1943 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1944 // Special case for #-0
1945 if (Val == INT32_MIN) Val = 0;
1946 if (Val < 0) Val = -Val;
1947 Val = ARM_AM::getAM5Opc(AddSub, Val);
1948 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1949 Inst.addOperand(MCOperand::CreateImm(Val));
1952 void addMemImm8s4OffsetOperands(MCInst &Inst, unsigned N) const {
1953 assert(N == 2 && "Invalid number of operands!");
1954 // If we have an immediate that's not a constant, treat it as a label
1955 // reference needing a fixup. If it is a constant, it's something else
1956 // and we reject it.
1958 Inst.addOperand(MCOperand::CreateExpr(getImm()));
1959 Inst.addOperand(MCOperand::CreateImm(0));
1963 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1964 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1965 Inst.addOperand(MCOperand::CreateImm(Val));
1968 void addMemImm0_1020s4OffsetOperands(MCInst &Inst, unsigned N) const {
1969 assert(N == 2 && "Invalid number of operands!");
1970 // The lower two bits are always zero and as such are not encoded.
1971 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0;
1972 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1973 Inst.addOperand(MCOperand::CreateImm(Val));
1976 void addMemImm8OffsetOperands(MCInst &Inst, unsigned N) const {
1977 assert(N == 2 && "Invalid number of operands!");
1978 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1979 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1980 Inst.addOperand(MCOperand::CreateImm(Val));
1983 void addMemPosImm8OffsetOperands(MCInst &Inst, unsigned N) const {
1984 addMemImm8OffsetOperands(Inst, N);
1987 void addMemNegImm8OffsetOperands(MCInst &Inst, unsigned N) const {
1988 addMemImm8OffsetOperands(Inst, N);
1991 void addMemUImm12OffsetOperands(MCInst &Inst, unsigned N) const {
1992 assert(N == 2 && "Invalid number of operands!");
1993 // If this is an immediate, it's a label reference.
1995 addExpr(Inst, getImm());
1996 Inst.addOperand(MCOperand::CreateImm(0));
2000 // Otherwise, it's a normal memory reg+offset.
2001 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2002 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2003 Inst.addOperand(MCOperand::CreateImm(Val));
2006 void addMemImm12OffsetOperands(MCInst &Inst, unsigned N) const {
2007 assert(N == 2 && "Invalid number of operands!");
2008 // If this is an immediate, it's a label reference.
2010 addExpr(Inst, getImm());
2011 Inst.addOperand(MCOperand::CreateImm(0));
2015 // Otherwise, it's a normal memory reg+offset.
2016 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2017 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2018 Inst.addOperand(MCOperand::CreateImm(Val));
2021 void addMemTBBOperands(MCInst &Inst, unsigned N) const {
2022 assert(N == 2 && "Invalid number of operands!");
2023 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2024 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
2027 void addMemTBHOperands(MCInst &Inst, unsigned N) const {
2028 assert(N == 2 && "Invalid number of operands!");
2029 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2030 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
2033 void addMemRegOffsetOperands(MCInst &Inst, unsigned N) const {
2034 assert(N == 3 && "Invalid number of operands!");
2036 ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add,
2037 Memory.ShiftImm, Memory.ShiftType);
2038 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2039 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
2040 Inst.addOperand(MCOperand::CreateImm(Val));
2043 void addT2MemRegOffsetOperands(MCInst &Inst, unsigned N) const {
2044 assert(N == 3 && "Invalid number of operands!");
2045 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2046 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
2047 Inst.addOperand(MCOperand::CreateImm(Memory.ShiftImm));
2050 void addMemThumbRROperands(MCInst &Inst, unsigned N) const {
2051 assert(N == 2 && "Invalid number of operands!");
2052 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2053 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
2056 void addMemThumbRIs4Operands(MCInst &Inst, unsigned N) const {
2057 assert(N == 2 && "Invalid number of operands!");
2058 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0;
2059 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2060 Inst.addOperand(MCOperand::CreateImm(Val));
2063 void addMemThumbRIs2Operands(MCInst &Inst, unsigned N) const {
2064 assert(N == 2 && "Invalid number of operands!");
2065 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 2) : 0;
2066 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2067 Inst.addOperand(MCOperand::CreateImm(Val));
2070 void addMemThumbRIs1Operands(MCInst &Inst, unsigned N) const {
2071 assert(N == 2 && "Invalid number of operands!");
2072 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue()) : 0;
2073 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2074 Inst.addOperand(MCOperand::CreateImm(Val));
2077 void addMemThumbSPIOperands(MCInst &Inst, unsigned N) const {
2078 assert(N == 2 && "Invalid number of operands!");
2079 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0;
2080 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2081 Inst.addOperand(MCOperand::CreateImm(Val));
2084 void addPostIdxImm8Operands(MCInst &Inst, unsigned N) const {
2085 assert(N == 1 && "Invalid number of operands!");
2086 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2087 assert(CE && "non-constant post-idx-imm8 operand!");
2088 int Imm = CE->getValue();
2089 bool isAdd = Imm >= 0;
2090 if (Imm == INT32_MIN) Imm = 0;
2091 Imm = (Imm < 0 ? -Imm : Imm) | (int)isAdd << 8;
2092 Inst.addOperand(MCOperand::CreateImm(Imm));
2095 void addPostIdxImm8s4Operands(MCInst &Inst, unsigned N) const {
2096 assert(N == 1 && "Invalid number of operands!");
2097 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2098 assert(CE && "non-constant post-idx-imm8s4 operand!");
2099 int Imm = CE->getValue();
2100 bool isAdd = Imm >= 0;
2101 if (Imm == INT32_MIN) Imm = 0;
2102 // Immediate is scaled by 4.
2103 Imm = ((Imm < 0 ? -Imm : Imm) / 4) | (int)isAdd << 8;
2104 Inst.addOperand(MCOperand::CreateImm(Imm));
2107 void addPostIdxRegOperands(MCInst &Inst, unsigned N) const {
2108 assert(N == 2 && "Invalid number of operands!");
2109 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
2110 Inst.addOperand(MCOperand::CreateImm(PostIdxReg.isAdd));
2113 void addPostIdxRegShiftedOperands(MCInst &Inst, unsigned N) const {
2114 assert(N == 2 && "Invalid number of operands!");
2115 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
2116 // The sign, shift type, and shift amount are encoded in a single operand
2117 // using the AM2 encoding helpers.
2118 ARM_AM::AddrOpc opc = PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub;
2119 unsigned Imm = ARM_AM::getAM2Opc(opc, PostIdxReg.ShiftImm,
2120 PostIdxReg.ShiftTy);
2121 Inst.addOperand(MCOperand::CreateImm(Imm));
2124 void addMSRMaskOperands(MCInst &Inst, unsigned N) const {
2125 assert(N == 1 && "Invalid number of operands!");
2126 Inst.addOperand(MCOperand::CreateImm(unsigned(getMSRMask())));
2129 void addProcIFlagsOperands(MCInst &Inst, unsigned N) const {
2130 assert(N == 1 && "Invalid number of operands!");
2131 Inst.addOperand(MCOperand::CreateImm(unsigned(getProcIFlags())));
2134 void addVecListOperands(MCInst &Inst, unsigned N) const {
2135 assert(N == 1 && "Invalid number of operands!");
2136 Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum));
2139 void addVecListIndexedOperands(MCInst &Inst, unsigned N) const {
2140 assert(N == 2 && "Invalid number of operands!");
2141 Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum));
2142 Inst.addOperand(MCOperand::CreateImm(VectorList.LaneIndex));
2145 void addVectorIndex8Operands(MCInst &Inst, unsigned N) const {
2146 assert(N == 1 && "Invalid number of operands!");
2147 Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
2150 void addVectorIndex16Operands(MCInst &Inst, unsigned N) const {
2151 assert(N == 1 && "Invalid number of operands!");
2152 Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
2155 void addVectorIndex32Operands(MCInst &Inst, unsigned N) const {
2156 assert(N == 1 && "Invalid number of operands!");
2157 Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
2160 void addNEONi8splatOperands(MCInst &Inst, unsigned N) const {
2161 assert(N == 1 && "Invalid number of operands!");
2162 // The immediate encodes the type of constant as well as the value.
2163 // Mask in that this is an i8 splat.
2164 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2165 Inst.addOperand(MCOperand::CreateImm(CE->getValue() | 0xe00));
2168 void addNEONi16splatOperands(MCInst &Inst, unsigned N) const {
2169 assert(N == 1 && "Invalid number of operands!");
2170 // The immediate encodes the type of constant as well as the value.
2171 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2172 unsigned Value = CE->getValue();
2174 Value = (Value >> 8) | 0xa00;
2177 Inst.addOperand(MCOperand::CreateImm(Value));
2180 void addNEONi32splatOperands(MCInst &Inst, unsigned N) const {
2181 assert(N == 1 && "Invalid number of operands!");
2182 // The immediate encodes the type of constant as well as the value.
2183 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2184 unsigned Value = CE->getValue();
2185 if (Value >= 256 && Value <= 0xff00)
2186 Value = (Value >> 8) | 0x200;
2187 else if (Value > 0xffff && Value <= 0xff0000)
2188 Value = (Value >> 16) | 0x400;
2189 else if (Value > 0xffffff)
2190 Value = (Value >> 24) | 0x600;
2191 Inst.addOperand(MCOperand::CreateImm(Value));
2194 void addNEONi32vmovOperands(MCInst &Inst, unsigned N) const {
2195 assert(N == 1 && "Invalid number of operands!");
2196 // The immediate encodes the type of constant as well as the value.
2197 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2198 unsigned Value = CE->getValue();
2199 if (Value >= 256 && Value <= 0xffff)
2200 Value = (Value >> 8) | ((Value & 0xff) ? 0xc00 : 0x200);
2201 else if (Value > 0xffff && Value <= 0xffffff)
2202 Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400);
2203 else if (Value > 0xffffff)
2204 Value = (Value >> 24) | 0x600;
2205 Inst.addOperand(MCOperand::CreateImm(Value));
2208 void addNEONi32vmovNegOperands(MCInst &Inst, unsigned N) const {
2209 assert(N == 1 && "Invalid number of operands!");
2210 // The immediate encodes the type of constant as well as the value.
2211 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2212 unsigned Value = ~CE->getValue();
2213 if (Value >= 256 && Value <= 0xffff)
2214 Value = (Value >> 8) | ((Value & 0xff) ? 0xc00 : 0x200);
2215 else if (Value > 0xffff && Value <= 0xffffff)
2216 Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400);
2217 else if (Value > 0xffffff)
2218 Value = (Value >> 24) | 0x600;
2219 Inst.addOperand(MCOperand::CreateImm(Value));
2222 void addNEONi64splatOperands(MCInst &Inst, unsigned N) const {
2223 assert(N == 1 && "Invalid number of operands!");
2224 // The immediate encodes the type of constant as well as the value.
2225 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2226 uint64_t Value = CE->getValue();
2228 for (unsigned i = 0; i < 8; ++i, Value >>= 8) {
2229 Imm |= (Value & 1) << i;
2231 Inst.addOperand(MCOperand::CreateImm(Imm | 0x1e00));
2234 virtual void print(raw_ostream &OS) const;
2236 static ARMOperand *CreateITMask(unsigned Mask, SMLoc S) {
2237 ARMOperand *Op = new ARMOperand(k_ITCondMask);
2238 Op->ITMask.Mask = Mask;
2244 static ARMOperand *CreateCondCode(ARMCC::CondCodes CC, SMLoc S) {
2245 ARMOperand *Op = new ARMOperand(k_CondCode);
2252 static ARMOperand *CreateCoprocNum(unsigned CopVal, SMLoc S) {
2253 ARMOperand *Op = new ARMOperand(k_CoprocNum);
2254 Op->Cop.Val = CopVal;
2260 static ARMOperand *CreateCoprocReg(unsigned CopVal, SMLoc S) {
2261 ARMOperand *Op = new ARMOperand(k_CoprocReg);
2262 Op->Cop.Val = CopVal;
2268 static ARMOperand *CreateCoprocOption(unsigned Val, SMLoc S, SMLoc E) {
2269 ARMOperand *Op = new ARMOperand(k_CoprocOption);
2276 static ARMOperand *CreateCCOut(unsigned RegNum, SMLoc S) {
2277 ARMOperand *Op = new ARMOperand(k_CCOut);
2278 Op->Reg.RegNum = RegNum;
2284 static ARMOperand *CreateToken(StringRef Str, SMLoc S) {
2285 ARMOperand *Op = new ARMOperand(k_Token);
2286 Op->Tok.Data = Str.data();
2287 Op->Tok.Length = Str.size();
2293 static ARMOperand *CreateReg(unsigned RegNum, SMLoc S, SMLoc E) {
2294 ARMOperand *Op = new ARMOperand(k_Register);
2295 Op->Reg.RegNum = RegNum;
2301 static ARMOperand *CreateShiftedRegister(ARM_AM::ShiftOpc ShTy,
2306 ARMOperand *Op = new ARMOperand(k_ShiftedRegister);
2307 Op->RegShiftedReg.ShiftTy = ShTy;
2308 Op->RegShiftedReg.SrcReg = SrcReg;
2309 Op->RegShiftedReg.ShiftReg = ShiftReg;
2310 Op->RegShiftedReg.ShiftImm = ShiftImm;
2316 static ARMOperand *CreateShiftedImmediate(ARM_AM::ShiftOpc ShTy,
2320 ARMOperand *Op = new ARMOperand(k_ShiftedImmediate);
2321 Op->RegShiftedImm.ShiftTy = ShTy;
2322 Op->RegShiftedImm.SrcReg = SrcReg;
2323 Op->RegShiftedImm.ShiftImm = ShiftImm;
2329 static ARMOperand *CreateShifterImm(bool isASR, unsigned Imm,
2331 ARMOperand *Op = new ARMOperand(k_ShifterImmediate);
2332 Op->ShifterImm.isASR = isASR;
2333 Op->ShifterImm.Imm = Imm;
2339 static ARMOperand *CreateRotImm(unsigned Imm, SMLoc S, SMLoc E) {
2340 ARMOperand *Op = new ARMOperand(k_RotateImmediate);
2341 Op->RotImm.Imm = Imm;
2347 static ARMOperand *CreateBitfield(unsigned LSB, unsigned Width,
2349 ARMOperand *Op = new ARMOperand(k_BitfieldDescriptor);
2350 Op->Bitfield.LSB = LSB;
2351 Op->Bitfield.Width = Width;
2358 CreateRegList(SmallVectorImpl<std::pair<unsigned, unsigned> > &Regs,
2359 SMLoc StartLoc, SMLoc EndLoc) {
2360 assert (Regs.size() > 0 && "RegList contains no registers?");
2361 KindTy Kind = k_RegisterList;
2363 if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Regs.front().second))
2364 Kind = k_DPRRegisterList;
2365 else if (ARMMCRegisterClasses[ARM::SPRRegClassID].
2366 contains(Regs.front().second))
2367 Kind = k_SPRRegisterList;
2369 // Sort based on the register encoding values.
2370 array_pod_sort(Regs.begin(), Regs.end());
2372 ARMOperand *Op = new ARMOperand(Kind);
2373 for (SmallVectorImpl<std::pair<unsigned, unsigned> >::const_iterator
2374 I = Regs.begin(), E = Regs.end(); I != E; ++I)
2375 Op->Registers.push_back(I->second);
2376 Op->StartLoc = StartLoc;
2377 Op->EndLoc = EndLoc;
2381 static ARMOperand *CreateVectorList(unsigned RegNum, unsigned Count,
2382 bool isDoubleSpaced, SMLoc S, SMLoc E) {
2383 ARMOperand *Op = new ARMOperand(k_VectorList);
2384 Op->VectorList.RegNum = RegNum;
2385 Op->VectorList.Count = Count;
2386 Op->VectorList.isDoubleSpaced = isDoubleSpaced;
2392 static ARMOperand *CreateVectorListAllLanes(unsigned RegNum, unsigned Count,
2393 bool isDoubleSpaced,
2395 ARMOperand *Op = new ARMOperand(k_VectorListAllLanes);
2396 Op->VectorList.RegNum = RegNum;
2397 Op->VectorList.Count = Count;
2398 Op->VectorList.isDoubleSpaced = isDoubleSpaced;
2404 static ARMOperand *CreateVectorListIndexed(unsigned RegNum, unsigned Count,
2406 bool isDoubleSpaced,
2408 ARMOperand *Op = new ARMOperand(k_VectorListIndexed);
2409 Op->VectorList.RegNum = RegNum;
2410 Op->VectorList.Count = Count;
2411 Op->VectorList.LaneIndex = Index;
2412 Op->VectorList.isDoubleSpaced = isDoubleSpaced;
2418 static ARMOperand *CreateVectorIndex(unsigned Idx, SMLoc S, SMLoc E,
2420 ARMOperand *Op = new ARMOperand(k_VectorIndex);
2421 Op->VectorIndex.Val = Idx;
2427 static ARMOperand *CreateImm(const MCExpr *Val, SMLoc S, SMLoc E) {
2428 ARMOperand *Op = new ARMOperand(k_Immediate);
2435 static ARMOperand *CreateMem(unsigned BaseRegNum,
2436 const MCConstantExpr *OffsetImm,
2437 unsigned OffsetRegNum,
2438 ARM_AM::ShiftOpc ShiftType,
2443 ARMOperand *Op = new ARMOperand(k_Memory);
2444 Op->Memory.BaseRegNum = BaseRegNum;
2445 Op->Memory.OffsetImm = OffsetImm;
2446 Op->Memory.OffsetRegNum = OffsetRegNum;
2447 Op->Memory.ShiftType = ShiftType;
2448 Op->Memory.ShiftImm = ShiftImm;
2449 Op->Memory.Alignment = Alignment;
2450 Op->Memory.isNegative = isNegative;
2456 static ARMOperand *CreatePostIdxReg(unsigned RegNum, bool isAdd,
2457 ARM_AM::ShiftOpc ShiftTy,
2460 ARMOperand *Op = new ARMOperand(k_PostIndexRegister);
2461 Op->PostIdxReg.RegNum = RegNum;
2462 Op->PostIdxReg.isAdd = isAdd;
2463 Op->PostIdxReg.ShiftTy = ShiftTy;
2464 Op->PostIdxReg.ShiftImm = ShiftImm;
2470 static ARMOperand *CreateMemBarrierOpt(ARM_MB::MemBOpt Opt, SMLoc S) {
2471 ARMOperand *Op = new ARMOperand(k_MemBarrierOpt);
2472 Op->MBOpt.Val = Opt;
2478 static ARMOperand *CreateInstSyncBarrierOpt(ARM_ISB::InstSyncBOpt Opt,
2480 ARMOperand *Op = new ARMOperand(k_InstSyncBarrierOpt);
2481 Op->ISBOpt.Val = Opt;
2487 static ARMOperand *CreateProcIFlags(ARM_PROC::IFlags IFlags, SMLoc S) {
2488 ARMOperand *Op = new ARMOperand(k_ProcIFlags);
2489 Op->IFlags.Val = IFlags;
2495 static ARMOperand *CreateMSRMask(unsigned MMask, SMLoc S) {
2496 ARMOperand *Op = new ARMOperand(k_MSRMask);
2497 Op->MMask.Val = MMask;
2504 } // end anonymous namespace.
2506 void ARMOperand::print(raw_ostream &OS) const {
2509 OS << "<ARMCC::" << ARMCondCodeToString(getCondCode()) << ">";
2512 OS << "<ccout " << getReg() << ">";
2514 case k_ITCondMask: {
2515 static const char *const MaskStr[] = {
2516 "()", "(t)", "(e)", "(tt)", "(et)", "(te)", "(ee)", "(ttt)", "(ett)",
2517 "(tet)", "(eet)", "(tte)", "(ete)", "(tee)", "(eee)"
2519 assert((ITMask.Mask & 0xf) == ITMask.Mask);
2520 OS << "<it-mask " << MaskStr[ITMask.Mask] << ">";
2524 OS << "<coprocessor number: " << getCoproc() << ">";
2527 OS << "<coprocessor register: " << getCoproc() << ">";
2529 case k_CoprocOption:
2530 OS << "<coprocessor option: " << CoprocOption.Val << ">";
2533 OS << "<mask: " << getMSRMask() << ">";
2536 getImm()->print(OS);
2538 case k_MemBarrierOpt:
2539 OS << "<ARM_MB::" << MemBOptToString(getMemBarrierOpt(), false) << ">";
2541 case k_InstSyncBarrierOpt:
2542 OS << "<ARM_ISB::" << InstSyncBOptToString(getInstSyncBarrierOpt()) << ">";
2546 << " base:" << Memory.BaseRegNum;
2549 case k_PostIndexRegister:
2550 OS << "post-idx register " << (PostIdxReg.isAdd ? "" : "-")
2551 << PostIdxReg.RegNum;
2552 if (PostIdxReg.ShiftTy != ARM_AM::no_shift)
2553 OS << ARM_AM::getShiftOpcStr(PostIdxReg.ShiftTy) << " "
2554 << PostIdxReg.ShiftImm;
2557 case k_ProcIFlags: {
2558 OS << "<ARM_PROC::";
2559 unsigned IFlags = getProcIFlags();
2560 for (int i=2; i >= 0; --i)
2561 if (IFlags & (1 << i))
2562 OS << ARM_PROC::IFlagsToString(1 << i);
2567 OS << "<register " << getReg() << ">";
2569 case k_ShifterImmediate:
2570 OS << "<shift " << (ShifterImm.isASR ? "asr" : "lsl")
2571 << " #" << ShifterImm.Imm << ">";
2573 case k_ShiftedRegister:
2574 OS << "<so_reg_reg "
2575 << RegShiftedReg.SrcReg << " "
2576 << ARM_AM::getShiftOpcStr(RegShiftedReg.ShiftTy)
2577 << " " << RegShiftedReg.ShiftReg << ">";
2579 case k_ShiftedImmediate:
2580 OS << "<so_reg_imm "
2581 << RegShiftedImm.SrcReg << " "
2582 << ARM_AM::getShiftOpcStr(RegShiftedImm.ShiftTy)
2583 << " #" << RegShiftedImm.ShiftImm << ">";
2585 case k_RotateImmediate:
2586 OS << "<ror " << " #" << (RotImm.Imm * 8) << ">";
2588 case k_BitfieldDescriptor:
2589 OS << "<bitfield " << "lsb: " << Bitfield.LSB
2590 << ", width: " << Bitfield.Width << ">";
2592 case k_RegisterList:
2593 case k_DPRRegisterList:
2594 case k_SPRRegisterList: {
2595 OS << "<register_list ";
2597 const SmallVectorImpl<unsigned> &RegList = getRegList();
2598 for (SmallVectorImpl<unsigned>::const_iterator
2599 I = RegList.begin(), E = RegList.end(); I != E; ) {
2601 if (++I < E) OS << ", ";
2608 OS << "<vector_list " << VectorList.Count << " * "
2609 << VectorList.RegNum << ">";
2611 case k_VectorListAllLanes:
2612 OS << "<vector_list(all lanes) " << VectorList.Count << " * "
2613 << VectorList.RegNum << ">";
2615 case k_VectorListIndexed:
2616 OS << "<vector_list(lane " << VectorList.LaneIndex << ") "
2617 << VectorList.Count << " * " << VectorList.RegNum << ">";
2620 OS << "'" << getToken() << "'";
2623 OS << "<vectorindex " << getVectorIndex() << ">";
2628 /// @name Auto-generated Match Functions
2631 static unsigned MatchRegisterName(StringRef Name);
2635 bool ARMAsmParser::ParseRegister(unsigned &RegNo,
2636 SMLoc &StartLoc, SMLoc &EndLoc) {
2637 StartLoc = Parser.getTok().getLoc();
2638 EndLoc = Parser.getTok().getEndLoc();
2639 RegNo = tryParseRegister();
2641 return (RegNo == (unsigned)-1);
2644 /// Try to parse a register name. The token must be an Identifier when called,
2645 /// and if it is a register name the token is eaten and the register number is
2646 /// returned. Otherwise return -1.
2648 int ARMAsmParser::tryParseRegister() {
2649 const AsmToken &Tok = Parser.getTok();
2650 if (Tok.isNot(AsmToken::Identifier)) return -1;
2652 std::string lowerCase = Tok.getString().lower();
2653 unsigned RegNum = MatchRegisterName(lowerCase);
2655 RegNum = StringSwitch<unsigned>(lowerCase)
2656 .Case("r13", ARM::SP)
2657 .Case("r14", ARM::LR)
2658 .Case("r15", ARM::PC)
2659 .Case("ip", ARM::R12)
2660 // Additional register name aliases for 'gas' compatibility.
2661 .Case("a1", ARM::R0)
2662 .Case("a2", ARM::R1)
2663 .Case("a3", ARM::R2)
2664 .Case("a4", ARM::R3)
2665 .Case("v1", ARM::R4)
2666 .Case("v2", ARM::R5)
2667 .Case("v3", ARM::R6)
2668 .Case("v4", ARM::R7)
2669 .Case("v5", ARM::R8)
2670 .Case("v6", ARM::R9)
2671 .Case("v7", ARM::R10)
2672 .Case("v8", ARM::R11)
2673 .Case("sb", ARM::R9)
2674 .Case("sl", ARM::R10)
2675 .Case("fp", ARM::R11)
2679 // Check for aliases registered via .req. Canonicalize to lower case.
2680 // That's more consistent since register names are case insensitive, and
2681 // it's how the original entry was passed in from MC/MCParser/AsmParser.
2682 StringMap<unsigned>::const_iterator Entry = RegisterReqs.find(lowerCase);
2683 // If no match, return failure.
2684 if (Entry == RegisterReqs.end())
2686 Parser.Lex(); // Eat identifier token.
2687 return Entry->getValue();
2690 Parser.Lex(); // Eat identifier token.
2695 // Try to parse a shifter (e.g., "lsl <amt>"). On success, return 0.
2696 // If a recoverable error occurs, return 1. If an irrecoverable error
2697 // occurs, return -1. An irrecoverable error is one where tokens have been
2698 // consumed in the process of trying to parse the shifter (i.e., when it is
2699 // indeed a shifter operand, but malformed).
2700 int ARMAsmParser::tryParseShiftRegister(
2701 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2702 SMLoc S = Parser.getTok().getLoc();
2703 const AsmToken &Tok = Parser.getTok();
2704 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
2706 std::string lowerCase = Tok.getString().lower();
2707 ARM_AM::ShiftOpc ShiftTy = StringSwitch<ARM_AM::ShiftOpc>(lowerCase)
2708 .Case("asl", ARM_AM::lsl)
2709 .Case("lsl", ARM_AM::lsl)
2710 .Case("lsr", ARM_AM::lsr)
2711 .Case("asr", ARM_AM::asr)
2712 .Case("ror", ARM_AM::ror)
2713 .Case("rrx", ARM_AM::rrx)
2714 .Default(ARM_AM::no_shift);
2716 if (ShiftTy == ARM_AM::no_shift)
2719 Parser.Lex(); // Eat the operator.
2721 // The source register for the shift has already been added to the
2722 // operand list, so we need to pop it off and combine it into the shifted
2723 // register operand instead.
2724 OwningPtr<ARMOperand> PrevOp((ARMOperand*)Operands.pop_back_val());
2725 if (!PrevOp->isReg())
2726 return Error(PrevOp->getStartLoc(), "shift must be of a register");
2727 int SrcReg = PrevOp->getReg();
2732 if (ShiftTy == ARM_AM::rrx) {
2733 // RRX Doesn't have an explicit shift amount. The encoder expects
2734 // the shift register to be the same as the source register. Seems odd,
2738 // Figure out if this is shifted by a constant or a register (for non-RRX).
2739 if (Parser.getTok().is(AsmToken::Hash) ||
2740 Parser.getTok().is(AsmToken::Dollar)) {
2741 Parser.Lex(); // Eat hash.
2742 SMLoc ImmLoc = Parser.getTok().getLoc();
2743 const MCExpr *ShiftExpr = 0;
2744 if (getParser().parseExpression(ShiftExpr, EndLoc)) {
2745 Error(ImmLoc, "invalid immediate shift value");
2748 // The expression must be evaluatable as an immediate.
2749 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftExpr);
2751 Error(ImmLoc, "invalid immediate shift value");
2754 // Range check the immediate.
2755 // lsl, ror: 0 <= imm <= 31
2756 // lsr, asr: 0 <= imm <= 32
2757 Imm = CE->getValue();
2759 ((ShiftTy == ARM_AM::lsl || ShiftTy == ARM_AM::ror) && Imm > 31) ||
2760 ((ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr) && Imm > 32)) {
2761 Error(ImmLoc, "immediate shift value out of range");
2764 // shift by zero is a nop. Always send it through as lsl.
2765 // ('as' compatibility)
2767 ShiftTy = ARM_AM::lsl;
2768 } else if (Parser.getTok().is(AsmToken::Identifier)) {
2769 SMLoc L = Parser.getTok().getLoc();
2770 EndLoc = Parser.getTok().getEndLoc();
2771 ShiftReg = tryParseRegister();
2772 if (ShiftReg == -1) {
2773 Error (L, "expected immediate or register in shift operand");
2777 Error (Parser.getTok().getLoc(),
2778 "expected immediate or register in shift operand");
2783 if (ShiftReg && ShiftTy != ARM_AM::rrx)
2784 Operands.push_back(ARMOperand::CreateShiftedRegister(ShiftTy, SrcReg,
2788 Operands.push_back(ARMOperand::CreateShiftedImmediate(ShiftTy, SrcReg, Imm,
2795 /// Try to parse a register name. The token must be an Identifier when called.
2796 /// If it's a register, an AsmOperand is created. Another AsmOperand is created
2797 /// if there is a "writeback". 'true' if it's not a register.
2799 /// TODO this is likely to change to allow different register types and or to
2800 /// parse for a specific register type.
2802 tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2803 const AsmToken &RegTok = Parser.getTok();
2804 int RegNo = tryParseRegister();
2808 Operands.push_back(ARMOperand::CreateReg(RegNo, RegTok.getLoc(),
2809 RegTok.getEndLoc()));
2811 const AsmToken &ExclaimTok = Parser.getTok();
2812 if (ExclaimTok.is(AsmToken::Exclaim)) {
2813 Operands.push_back(ARMOperand::CreateToken(ExclaimTok.getString(),
2814 ExclaimTok.getLoc()));
2815 Parser.Lex(); // Eat exclaim token
2819 // Also check for an index operand. This is only legal for vector registers,
2820 // but that'll get caught OK in operand matching, so we don't need to
2821 // explicitly filter everything else out here.
2822 if (Parser.getTok().is(AsmToken::LBrac)) {
2823 SMLoc SIdx = Parser.getTok().getLoc();
2824 Parser.Lex(); // Eat left bracket token.
2826 const MCExpr *ImmVal;
2827 if (getParser().parseExpression(ImmVal))
2829 const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(ImmVal);
2831 return TokError("immediate value expected for vector index");
2833 if (Parser.getTok().isNot(AsmToken::RBrac))
2834 return Error(Parser.getTok().getLoc(), "']' expected");
2836 SMLoc E = Parser.getTok().getEndLoc();
2837 Parser.Lex(); // Eat right bracket token.
2839 Operands.push_back(ARMOperand::CreateVectorIndex(MCE->getValue(),
2847 /// MatchCoprocessorOperandName - Try to parse an coprocessor related
2848 /// instruction with a symbolic operand name. Example: "p1", "p7", "c3",
2850 static int MatchCoprocessorOperandName(StringRef Name, char CoprocOp) {
2851 // Use the same layout as the tablegen'erated register name matcher. Ugly,
2853 switch (Name.size()) {
2856 if (Name[0] != CoprocOp)
2872 if (Name[0] != CoprocOp || Name[1] != '1')
2876 // p10 and p11 are invalid for coproc instructions (reserved for FP/NEON)
2877 case '0': return CoprocOp == 'p'? -1: 10;
2878 case '1': return CoprocOp == 'p'? -1: 11;
2879 case '2': return 12;
2880 case '3': return 13;
2881 case '4': return 14;
2882 case '5': return 15;
2887 /// parseITCondCode - Try to parse a condition code for an IT instruction.
2888 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2889 parseITCondCode(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2890 SMLoc S = Parser.getTok().getLoc();
2891 const AsmToken &Tok = Parser.getTok();
2892 if (!Tok.is(AsmToken::Identifier))
2893 return MatchOperand_NoMatch;
2894 unsigned CC = StringSwitch<unsigned>(Tok.getString().lower())
2895 .Case("eq", ARMCC::EQ)
2896 .Case("ne", ARMCC::NE)
2897 .Case("hs", ARMCC::HS)
2898 .Case("cs", ARMCC::HS)
2899 .Case("lo", ARMCC::LO)
2900 .Case("cc", ARMCC::LO)
2901 .Case("mi", ARMCC::MI)
2902 .Case("pl", ARMCC::PL)
2903 .Case("vs", ARMCC::VS)
2904 .Case("vc", ARMCC::VC)
2905 .Case("hi", ARMCC::HI)
2906 .Case("ls", ARMCC::LS)
2907 .Case("ge", ARMCC::GE)
2908 .Case("lt", ARMCC::LT)
2909 .Case("gt", ARMCC::GT)
2910 .Case("le", ARMCC::LE)
2911 .Case("al", ARMCC::AL)
2914 return MatchOperand_NoMatch;
2915 Parser.Lex(); // Eat the token.
2917 Operands.push_back(ARMOperand::CreateCondCode(ARMCC::CondCodes(CC), S));
2919 return MatchOperand_Success;
2922 /// parseCoprocNumOperand - Try to parse an coprocessor number operand. The
2923 /// token must be an Identifier when called, and if it is a coprocessor
2924 /// number, the token is eaten and the operand is added to the operand list.
2925 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2926 parseCoprocNumOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2927 SMLoc S = Parser.getTok().getLoc();
2928 const AsmToken &Tok = Parser.getTok();
2929 if (Tok.isNot(AsmToken::Identifier))
2930 return MatchOperand_NoMatch;
2932 int Num = MatchCoprocessorOperandName(Tok.getString(), 'p');
2934 return MatchOperand_NoMatch;
2936 Parser.Lex(); // Eat identifier token.
2937 Operands.push_back(ARMOperand::CreateCoprocNum(Num, S));
2938 return MatchOperand_Success;
2941 /// parseCoprocRegOperand - Try to parse an coprocessor register operand. The
2942 /// token must be an Identifier when called, and if it is a coprocessor
2943 /// number, the token is eaten and the operand is added to the operand list.
2944 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2945 parseCoprocRegOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2946 SMLoc S = Parser.getTok().getLoc();
2947 const AsmToken &Tok = Parser.getTok();
2948 if (Tok.isNot(AsmToken::Identifier))
2949 return MatchOperand_NoMatch;
2951 int Reg = MatchCoprocessorOperandName(Tok.getString(), 'c');
2953 return MatchOperand_NoMatch;
2955 Parser.Lex(); // Eat identifier token.
2956 Operands.push_back(ARMOperand::CreateCoprocReg(Reg, S));
2957 return MatchOperand_Success;
2960 /// parseCoprocOptionOperand - Try to parse an coprocessor option operand.
2961 /// coproc_option : '{' imm0_255 '}'
2962 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2963 parseCoprocOptionOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2964 SMLoc S = Parser.getTok().getLoc();
2966 // If this isn't a '{', this isn't a coprocessor immediate operand.
2967 if (Parser.getTok().isNot(AsmToken::LCurly))
2968 return MatchOperand_NoMatch;
2969 Parser.Lex(); // Eat the '{'
2972 SMLoc Loc = Parser.getTok().getLoc();
2973 if (getParser().parseExpression(Expr)) {
2974 Error(Loc, "illegal expression");
2975 return MatchOperand_ParseFail;
2977 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
2978 if (!CE || CE->getValue() < 0 || CE->getValue() > 255) {
2979 Error(Loc, "coprocessor option must be an immediate in range [0, 255]");
2980 return MatchOperand_ParseFail;
2982 int Val = CE->getValue();
2984 // Check for and consume the closing '}'
2985 if (Parser.getTok().isNot(AsmToken::RCurly))
2986 return MatchOperand_ParseFail;
2987 SMLoc E = Parser.getTok().getEndLoc();
2988 Parser.Lex(); // Eat the '}'
2990 Operands.push_back(ARMOperand::CreateCoprocOption(Val, S, E));
2991 return MatchOperand_Success;
2994 // For register list parsing, we need to map from raw GPR register numbering
2995 // to the enumeration values. The enumeration values aren't sorted by
2996 // register number due to our using "sp", "lr" and "pc" as canonical names.
2997 static unsigned getNextRegister(unsigned Reg) {
2998 // If this is a GPR, we need to do it manually, otherwise we can rely
2999 // on the sort ordering of the enumeration since the other reg-classes
3001 if (!ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
3004 default: llvm_unreachable("Invalid GPR number!");
3005 case ARM::R0: return ARM::R1; case ARM::R1: return ARM::R2;
3006 case ARM::R2: return ARM::R3; case ARM::R3: return ARM::R4;
3007 case ARM::R4: return ARM::R5; case ARM::R5: return ARM::R6;
3008 case ARM::R6: return ARM::R7; case ARM::R7: return ARM::R8;
3009 case ARM::R8: return ARM::R9; case ARM::R9: return ARM::R10;
3010 case ARM::R10: return ARM::R11; case ARM::R11: return ARM::R12;
3011 case ARM::R12: return ARM::SP; case ARM::SP: return ARM::LR;
3012 case ARM::LR: return ARM::PC; case ARM::PC: return ARM::R0;
3016 // Return the low-subreg of a given Q register.
3017 static unsigned getDRegFromQReg(unsigned QReg) {
3019 default: llvm_unreachable("expected a Q register!");
3020 case ARM::Q0: return ARM::D0;
3021 case ARM::Q1: return ARM::D2;
3022 case ARM::Q2: return ARM::D4;
3023 case ARM::Q3: return ARM::D6;
3024 case ARM::Q4: return ARM::D8;
3025 case ARM::Q5: return ARM::D10;
3026 case ARM::Q6: return ARM::D12;
3027 case ARM::Q7: return ARM::D14;
3028 case ARM::Q8: return ARM::D16;
3029 case ARM::Q9: return ARM::D18;
3030 case ARM::Q10: return ARM::D20;
3031 case ARM::Q11: return ARM::D22;
3032 case ARM::Q12: return ARM::D24;
3033 case ARM::Q13: return ARM::D26;
3034 case ARM::Q14: return ARM::D28;
3035 case ARM::Q15: return ARM::D30;
3039 /// Parse a register list.
3041 parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3042 assert(Parser.getTok().is(AsmToken::LCurly) &&
3043 "Token is not a Left Curly Brace");
3044 SMLoc S = Parser.getTok().getLoc();
3045 Parser.Lex(); // Eat '{' token.
3046 SMLoc RegLoc = Parser.getTok().getLoc();
3048 // Check the first register in the list to see what register class
3049 // this is a list of.
3050 int Reg = tryParseRegister();
3052 return Error(RegLoc, "register expected");
3054 // The reglist instructions have at most 16 registers, so reserve
3055 // space for that many.
3057 SmallVector<std::pair<unsigned, unsigned>, 16> Registers;
3059 // Allow Q regs and just interpret them as the two D sub-registers.
3060 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3061 Reg = getDRegFromQReg(Reg);
3062 EReg = MRI->getEncodingValue(Reg);
3063 Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3066 const MCRegisterClass *RC;
3067 if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
3068 RC = &ARMMCRegisterClasses[ARM::GPRRegClassID];
3069 else if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg))
3070 RC = &ARMMCRegisterClasses[ARM::DPRRegClassID];
3071 else if (ARMMCRegisterClasses[ARM::SPRRegClassID].contains(Reg))
3072 RC = &ARMMCRegisterClasses[ARM::SPRRegClassID];
3074 return Error(RegLoc, "invalid register in register list");
3076 // Store the register.
3077 EReg = MRI->getEncodingValue(Reg);
3078 Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3080 // This starts immediately after the first register token in the list,
3081 // so we can see either a comma or a minus (range separator) as a legal
3083 while (Parser.getTok().is(AsmToken::Comma) ||
3084 Parser.getTok().is(AsmToken::Minus)) {
3085 if (Parser.getTok().is(AsmToken::Minus)) {
3086 Parser.Lex(); // Eat the minus.
3087 SMLoc AfterMinusLoc = Parser.getTok().getLoc();
3088 int EndReg = tryParseRegister();
3090 return Error(AfterMinusLoc, "register expected");
3091 // Allow Q regs and just interpret them as the two D sub-registers.
3092 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg))
3093 EndReg = getDRegFromQReg(EndReg) + 1;
3094 // If the register is the same as the start reg, there's nothing
3098 // The register must be in the same register class as the first.
3099 if (!RC->contains(EndReg))
3100 return Error(AfterMinusLoc, "invalid register in register list");
3101 // Ranges must go from low to high.
3102 if (MRI->getEncodingValue(Reg) > MRI->getEncodingValue(EndReg))
3103 return Error(AfterMinusLoc, "bad range in register list");
3105 // Add all the registers in the range to the register list.
3106 while (Reg != EndReg) {
3107 Reg = getNextRegister(Reg);
3108 EReg = MRI->getEncodingValue(Reg);
3109 Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3113 Parser.Lex(); // Eat the comma.
3114 RegLoc = Parser.getTok().getLoc();
3116 const AsmToken RegTok = Parser.getTok();
3117 Reg = tryParseRegister();
3119 return Error(RegLoc, "register expected");
3120 // Allow Q regs and just interpret them as the two D sub-registers.
3121 bool isQReg = false;
3122 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3123 Reg = getDRegFromQReg(Reg);
3126 // The register must be in the same register class as the first.
3127 if (!RC->contains(Reg))
3128 return Error(RegLoc, "invalid register in register list");
3129 // List must be monotonically increasing.
3130 if (MRI->getEncodingValue(Reg) < MRI->getEncodingValue(OldReg)) {
3131 if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
3132 Warning(RegLoc, "register list not in ascending order");
3134 return Error(RegLoc, "register list not in ascending order");
3136 if (MRI->getEncodingValue(Reg) == MRI->getEncodingValue(OldReg)) {
3137 Warning(RegLoc, "duplicated register (" + RegTok.getString() +
3138 ") in register list");
3141 // VFP register lists must also be contiguous.
3142 if (RC != &ARMMCRegisterClasses[ARM::GPRRegClassID] &&
3144 return Error(RegLoc, "non-contiguous register range");
3145 EReg = MRI->getEncodingValue(Reg);
3146 Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3148 EReg = MRI->getEncodingValue(++Reg);
3149 Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3153 if (Parser.getTok().isNot(AsmToken::RCurly))
3154 return Error(Parser.getTok().getLoc(), "'}' expected");
3155 SMLoc E = Parser.getTok().getEndLoc();
3156 Parser.Lex(); // Eat '}' token.
3158 // Push the register list operand.
3159 Operands.push_back(ARMOperand::CreateRegList(Registers, S, E));
3161 // The ARM system instruction variants for LDM/STM have a '^' token here.
3162 if (Parser.getTok().is(AsmToken::Caret)) {
3163 Operands.push_back(ARMOperand::CreateToken("^",Parser.getTok().getLoc()));
3164 Parser.Lex(); // Eat '^' token.
3170 // Helper function to parse the lane index for vector lists.
3171 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3172 parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index, SMLoc &EndLoc) {
3173 Index = 0; // Always return a defined index value.
3174 if (Parser.getTok().is(AsmToken::LBrac)) {
3175 Parser.Lex(); // Eat the '['.
3176 if (Parser.getTok().is(AsmToken::RBrac)) {
3177 // "Dn[]" is the 'all lanes' syntax.
3178 LaneKind = AllLanes;
3179 EndLoc = Parser.getTok().getEndLoc();
3180 Parser.Lex(); // Eat the ']'.
3181 return MatchOperand_Success;
3184 // There's an optional '#' token here. Normally there wouldn't be, but
3185 // inline assemble puts one in, and it's friendly to accept that.
3186 if (Parser.getTok().is(AsmToken::Hash))
3187 Parser.Lex(); // Eat '#' or '$'.
3189 const MCExpr *LaneIndex;
3190 SMLoc Loc = Parser.getTok().getLoc();
3191 if (getParser().parseExpression(LaneIndex)) {
3192 Error(Loc, "illegal expression");
3193 return MatchOperand_ParseFail;
3195 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LaneIndex);
3197 Error(Loc, "lane index must be empty or an integer");
3198 return MatchOperand_ParseFail;
3200 if (Parser.getTok().isNot(AsmToken::RBrac)) {
3201 Error(Parser.getTok().getLoc(), "']' expected");
3202 return MatchOperand_ParseFail;
3204 EndLoc = Parser.getTok().getEndLoc();
3205 Parser.Lex(); // Eat the ']'.
3206 int64_t Val = CE->getValue();
3208 // FIXME: Make this range check context sensitive for .8, .16, .32.
3209 if (Val < 0 || Val > 7) {
3210 Error(Parser.getTok().getLoc(), "lane index out of range");
3211 return MatchOperand_ParseFail;
3214 LaneKind = IndexedLane;
3215 return MatchOperand_Success;
3218 return MatchOperand_Success;
3221 // parse a vector register list
3222 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3223 parseVectorList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3224 VectorLaneTy LaneKind;
3226 SMLoc S = Parser.getTok().getLoc();
3227 // As an extension (to match gas), support a plain D register or Q register
3228 // (without encosing curly braces) as a single or double entry list,
3230 if (Parser.getTok().is(AsmToken::Identifier)) {
3231 SMLoc E = Parser.getTok().getEndLoc();
3232 int Reg = tryParseRegister();
3234 return MatchOperand_NoMatch;
3235 if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg)) {
3236 OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex, E);
3237 if (Res != MatchOperand_Success)
3241 Operands.push_back(ARMOperand::CreateVectorList(Reg, 1, false, S, E));
3244 Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 1, false,
3248 Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 1,
3253 return MatchOperand_Success;
3255 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3256 Reg = getDRegFromQReg(Reg);
3257 OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex, E);
3258 if (Res != MatchOperand_Success)
3262 Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0,
3263 &ARMMCRegisterClasses[ARM::DPairRegClassID]);
3264 Operands.push_back(ARMOperand::CreateVectorList(Reg, 2, false, S, E));
3267 Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0,
3268 &ARMMCRegisterClasses[ARM::DPairRegClassID]);
3269 Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 2, false,
3273 Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 2,
3278 return MatchOperand_Success;
3280 Error(S, "vector register expected");
3281 return MatchOperand_ParseFail;
3284 if (Parser.getTok().isNot(AsmToken::LCurly))
3285 return MatchOperand_NoMatch;
3287 Parser.Lex(); // Eat '{' token.
3288 SMLoc RegLoc = Parser.getTok().getLoc();
3290 int Reg = tryParseRegister();
3292 Error(RegLoc, "register expected");
3293 return MatchOperand_ParseFail;
3297 unsigned FirstReg = Reg;
3298 // The list is of D registers, but we also allow Q regs and just interpret
3299 // them as the two D sub-registers.
3300 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3301 FirstReg = Reg = getDRegFromQReg(Reg);
3302 Spacing = 1; // double-spacing requires explicit D registers, otherwise
3303 // it's ambiguous with four-register single spaced.
3309 if (parseVectorLane(LaneKind, LaneIndex, E) != MatchOperand_Success)
3310 return MatchOperand_ParseFail;
3312 while (Parser.getTok().is(AsmToken::Comma) ||
3313 Parser.getTok().is(AsmToken::Minus)) {
3314 if (Parser.getTok().is(AsmToken::Minus)) {
3316 Spacing = 1; // Register range implies a single spaced list.
3317 else if (Spacing == 2) {
3318 Error(Parser.getTok().getLoc(),
3319 "sequential registers in double spaced list");
3320 return MatchOperand_ParseFail;
3322 Parser.Lex(); // Eat the minus.
3323 SMLoc AfterMinusLoc = Parser.getTok().getLoc();
3324 int EndReg = tryParseRegister();
3326 Error(AfterMinusLoc, "register expected");
3327 return MatchOperand_ParseFail;
3329 // Allow Q regs and just interpret them as the two D sub-registers.
3330 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg))
3331 EndReg = getDRegFromQReg(EndReg) + 1;
3332 // If the register is the same as the start reg, there's nothing
3336 // The register must be in the same register class as the first.
3337 if (!ARMMCRegisterClasses[ARM::DPRRegClassID].contains(EndReg)) {
3338 Error(AfterMinusLoc, "invalid register in register list");
3339 return MatchOperand_ParseFail;
3341 // Ranges must go from low to high.
3343 Error(AfterMinusLoc, "bad range in register list");
3344 return MatchOperand_ParseFail;
3346 // Parse the lane specifier if present.
3347 VectorLaneTy NextLaneKind;
3348 unsigned NextLaneIndex;
3349 if (parseVectorLane(NextLaneKind, NextLaneIndex, E) !=
3350 MatchOperand_Success)
3351 return MatchOperand_ParseFail;
3352 if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
3353 Error(AfterMinusLoc, "mismatched lane index in register list");
3354 return MatchOperand_ParseFail;
3357 // Add all the registers in the range to the register list.
3358 Count += EndReg - Reg;
3362 Parser.Lex(); // Eat the comma.
3363 RegLoc = Parser.getTok().getLoc();
3365 Reg = tryParseRegister();
3367 Error(RegLoc, "register expected");
3368 return MatchOperand_ParseFail;
3370 // vector register lists must be contiguous.
3371 // It's OK to use the enumeration values directly here rather, as the
3372 // VFP register classes have the enum sorted properly.
3374 // The list is of D registers, but we also allow Q regs and just interpret
3375 // them as the two D sub-registers.
3376 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3378 Spacing = 1; // Register range implies a single spaced list.
3379 else if (Spacing == 2) {
3381 "invalid register in double-spaced list (must be 'D' register')");
3382 return MatchOperand_ParseFail;
3384 Reg = getDRegFromQReg(Reg);
3385 if (Reg != OldReg + 1) {
3386 Error(RegLoc, "non-contiguous register range");
3387 return MatchOperand_ParseFail;
3391 // Parse the lane specifier if present.
3392 VectorLaneTy NextLaneKind;
3393 unsigned NextLaneIndex;
3394 SMLoc LaneLoc = Parser.getTok().getLoc();
3395 if (parseVectorLane(NextLaneKind, NextLaneIndex, E) !=
3396 MatchOperand_Success)
3397 return MatchOperand_ParseFail;
3398 if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
3399 Error(LaneLoc, "mismatched lane index in register list");
3400 return MatchOperand_ParseFail;
3404 // Normal D register.
3405 // Figure out the register spacing (single or double) of the list if
3406 // we don't know it already.
3408 Spacing = 1 + (Reg == OldReg + 2);
3410 // Just check that it's contiguous and keep going.
3411 if (Reg != OldReg + Spacing) {
3412 Error(RegLoc, "non-contiguous register range");
3413 return MatchOperand_ParseFail;
3416 // Parse the lane specifier if present.
3417 VectorLaneTy NextLaneKind;
3418 unsigned NextLaneIndex;
3419 SMLoc EndLoc = Parser.getTok().getLoc();
3420 if (parseVectorLane(NextLaneKind, NextLaneIndex, E) != MatchOperand_Success)
3421 return MatchOperand_ParseFail;
3422 if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
3423 Error(EndLoc, "mismatched lane index in register list");
3424 return MatchOperand_ParseFail;
3428 if (Parser.getTok().isNot(AsmToken::RCurly)) {
3429 Error(Parser.getTok().getLoc(), "'}' expected");
3430 return MatchOperand_ParseFail;
3432 E = Parser.getTok().getEndLoc();
3433 Parser.Lex(); // Eat '}' token.
3437 // Two-register operands have been converted to the
3438 // composite register classes.
3440 const MCRegisterClass *RC = (Spacing == 1) ?
3441 &ARMMCRegisterClasses[ARM::DPairRegClassID] :
3442 &ARMMCRegisterClasses[ARM::DPairSpcRegClassID];
3443 FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC);
3446 Operands.push_back(ARMOperand::CreateVectorList(FirstReg, Count,
3447 (Spacing == 2), S, E));
3450 // Two-register operands have been converted to the
3451 // composite register classes.
3453 const MCRegisterClass *RC = (Spacing == 1) ?
3454 &ARMMCRegisterClasses[ARM::DPairRegClassID] :
3455 &ARMMCRegisterClasses[ARM::DPairSpcRegClassID];
3456 FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC);
3458 Operands.push_back(ARMOperand::CreateVectorListAllLanes(FirstReg, Count,
3463 Operands.push_back(ARMOperand::CreateVectorListIndexed(FirstReg, Count,
3469 return MatchOperand_Success;
3472 /// parseMemBarrierOptOperand - Try to parse DSB/DMB data barrier options.
3473 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3474 parseMemBarrierOptOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3475 SMLoc S = Parser.getTok().getLoc();
3476 const AsmToken &Tok = Parser.getTok();
3479 if (Tok.is(AsmToken::Identifier)) {
3480 StringRef OptStr = Tok.getString();
3482 Opt = StringSwitch<unsigned>(OptStr.slice(0, OptStr.size()).lower())
3483 .Case("sy", ARM_MB::SY)
3484 .Case("st", ARM_MB::ST)
3485 .Case("ld", ARM_MB::LD)
3486 .Case("sh", ARM_MB::ISH)
3487 .Case("ish", ARM_MB::ISH)
3488 .Case("shst", ARM_MB::ISHST)
3489 .Case("ishst", ARM_MB::ISHST)
3490 .Case("ishld", ARM_MB::ISHLD)
3491 .Case("nsh", ARM_MB::NSH)
3492 .Case("un", ARM_MB::NSH)
3493 .Case("nshst", ARM_MB::NSHST)
3494 .Case("nshld", ARM_MB::NSHLD)
3495 .Case("unst", ARM_MB::NSHST)
3496 .Case("osh", ARM_MB::OSH)
3497 .Case("oshst", ARM_MB::OSHST)
3498 .Case("oshld", ARM_MB::OSHLD)
3501 // ishld, oshld, nshld and ld are only available from ARMv8.
3502 if (!hasV8Ops() && (Opt == ARM_MB::ISHLD || Opt == ARM_MB::OSHLD ||
3503 Opt == ARM_MB::NSHLD || Opt == ARM_MB::LD))
3507 return MatchOperand_NoMatch;
3509 Parser.Lex(); // Eat identifier token.
3510 } else if (Tok.is(AsmToken::Hash) ||
3511 Tok.is(AsmToken::Dollar) ||
3512 Tok.is(AsmToken::Integer)) {
3513 if (Parser.getTok().isNot(AsmToken::Integer))
3514 Parser.Lex(); // Eat '#' or '$'.
3515 SMLoc Loc = Parser.getTok().getLoc();
3517 const MCExpr *MemBarrierID;
3518 if (getParser().parseExpression(MemBarrierID)) {
3519 Error(Loc, "illegal expression");
3520 return MatchOperand_ParseFail;
3523 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(MemBarrierID);
3525 Error(Loc, "constant expression expected");
3526 return MatchOperand_ParseFail;
3529 int Val = CE->getValue();
3531 Error(Loc, "immediate value out of range");
3532 return MatchOperand_ParseFail;
3535 Opt = ARM_MB::RESERVED_0 + Val;
3537 return MatchOperand_ParseFail;
3539 Operands.push_back(ARMOperand::CreateMemBarrierOpt((ARM_MB::MemBOpt)Opt, S));
3540 return MatchOperand_Success;
3543 /// parseInstSyncBarrierOptOperand - Try to parse ISB inst sync barrier options.
3544 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3545 parseInstSyncBarrierOptOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3546 SMLoc S = Parser.getTok().getLoc();
3547 const AsmToken &Tok = Parser.getTok();
3550 if (Tok.is(AsmToken::Identifier)) {
3551 StringRef OptStr = Tok.getString();
3553 if (OptStr.equals_lower("sy"))
3556 return MatchOperand_NoMatch;
3558 Parser.Lex(); // Eat identifier token.
3559 } else if (Tok.is(AsmToken::Hash) ||
3560 Tok.is(AsmToken::Dollar) ||
3561 Tok.is(AsmToken::Integer)) {
3562 if (Parser.getTok().isNot(AsmToken::Integer))
3563 Parser.Lex(); // Eat '#' or '$'.
3564 SMLoc Loc = Parser.getTok().getLoc();
3566 const MCExpr *ISBarrierID;
3567 if (getParser().parseExpression(ISBarrierID)) {
3568 Error(Loc, "illegal expression");
3569 return MatchOperand_ParseFail;
3572 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ISBarrierID);
3574 Error(Loc, "constant expression expected");
3575 return MatchOperand_ParseFail;
3578 int Val = CE->getValue();
3580 Error(Loc, "immediate value out of range");
3581 return MatchOperand_ParseFail;
3584 Opt = ARM_ISB::RESERVED_0 + Val;
3586 return MatchOperand_ParseFail;
3588 Operands.push_back(ARMOperand::CreateInstSyncBarrierOpt(
3589 (ARM_ISB::InstSyncBOpt)Opt, S));
3590 return MatchOperand_Success;
3594 /// parseProcIFlagsOperand - Try to parse iflags from CPS instruction.
3595 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3596 parseProcIFlagsOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3597 SMLoc S = Parser.getTok().getLoc();
3598 const AsmToken &Tok = Parser.getTok();
3599 if (!Tok.is(AsmToken::Identifier))
3600 return MatchOperand_NoMatch;
3601 StringRef IFlagsStr = Tok.getString();
3603 // An iflags string of "none" is interpreted to mean that none of the AIF
3604 // bits are set. Not a terribly useful instruction, but a valid encoding.
3605 unsigned IFlags = 0;
3606 if (IFlagsStr != "none") {
3607 for (int i = 0, e = IFlagsStr.size(); i != e; ++i) {
3608 unsigned Flag = StringSwitch<unsigned>(IFlagsStr.substr(i, 1))
3609 .Case("a", ARM_PROC::A)
3610 .Case("i", ARM_PROC::I)
3611 .Case("f", ARM_PROC::F)
3614 // If some specific iflag is already set, it means that some letter is
3615 // present more than once, this is not acceptable.
3616 if (Flag == ~0U || (IFlags & Flag))
3617 return MatchOperand_NoMatch;
3623 Parser.Lex(); // Eat identifier token.
3624 Operands.push_back(ARMOperand::CreateProcIFlags((ARM_PROC::IFlags)IFlags, S));
3625 return MatchOperand_Success;
3628 /// parseMSRMaskOperand - Try to parse mask flags from MSR instruction.
3629 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3630 parseMSRMaskOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3631 SMLoc S = Parser.getTok().getLoc();
3632 const AsmToken &Tok = Parser.getTok();
3633 if (!Tok.is(AsmToken::Identifier))
3634 return MatchOperand_NoMatch;
3635 StringRef Mask = Tok.getString();
3638 // See ARMv6-M 10.1.1
3639 std::string Name = Mask.lower();
3640 unsigned FlagsVal = StringSwitch<unsigned>(Name)
3641 // Note: in the documentation:
3642 // ARM deprecates using MSR APSR without a _<bits> qualifier as an alias
3643 // for MSR APSR_nzcvq.
3644 // but we do make it an alias here. This is so to get the "mask encoding"
3645 // bits correct on MSR APSR writes.
3647 // FIXME: Note the 0xc00 "mask encoding" bits version of the registers
3648 // should really only be allowed when writing a special register. Note
3649 // they get dropped in the MRS instruction reading a special register as
3650 // the SYSm field is only 8 bits.
3652 // FIXME: the _g and _nzcvqg versions are only allowed if the processor
3653 // includes the DSP extension but that is not checked.
3654 .Case("apsr", 0x800)
3655 .Case("apsr_nzcvq", 0x800)
3656 .Case("apsr_g", 0x400)
3657 .Case("apsr_nzcvqg", 0xc00)
3658 .Case("iapsr", 0x801)
3659 .Case("iapsr_nzcvq", 0x801)
3660 .Case("iapsr_g", 0x401)
3661 .Case("iapsr_nzcvqg", 0xc01)
3662 .Case("eapsr", 0x802)
3663 .Case("eapsr_nzcvq", 0x802)
3664 .Case("eapsr_g", 0x402)
3665 .Case("eapsr_nzcvqg", 0xc02)
3666 .Case("xpsr", 0x803)
3667 .Case("xpsr_nzcvq", 0x803)
3668 .Case("xpsr_g", 0x403)
3669 .Case("xpsr_nzcvqg", 0xc03)
3670 .Case("ipsr", 0x805)
3671 .Case("epsr", 0x806)
3672 .Case("iepsr", 0x807)
3675 .Case("primask", 0x810)
3676 .Case("basepri", 0x811)
3677 .Case("basepri_max", 0x812)
3678 .Case("faultmask", 0x813)
3679 .Case("control", 0x814)
3682 if (FlagsVal == ~0U)
3683 return MatchOperand_NoMatch;
3685 if (!hasV7Ops() && FlagsVal >= 0x811 && FlagsVal <= 0x813)
3686 // basepri, basepri_max and faultmask only valid for V7m.
3687 return MatchOperand_NoMatch;
3689 Parser.Lex(); // Eat identifier token.
3690 Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S));
3691 return MatchOperand_Success;
3694 // Split spec_reg from flag, example: CPSR_sxf => "CPSR" and "sxf"
3695 size_t Start = 0, Next = Mask.find('_');
3696 StringRef Flags = "";
3697 std::string SpecReg = Mask.slice(Start, Next).lower();
3698 if (Next != StringRef::npos)
3699 Flags = Mask.slice(Next+1, Mask.size());
3701 // FlagsVal contains the complete mask:
3703 // 4: Special Reg (cpsr, apsr => 0; spsr => 1)
3704 unsigned FlagsVal = 0;
3706 if (SpecReg == "apsr") {
3707 FlagsVal = StringSwitch<unsigned>(Flags)
3708 .Case("nzcvq", 0x8) // same as CPSR_f
3709 .Case("g", 0x4) // same as CPSR_s
3710 .Case("nzcvqg", 0xc) // same as CPSR_fs
3713 if (FlagsVal == ~0U) {
3715 return MatchOperand_NoMatch;
3717 FlagsVal = 8; // No flag
3719 } else if (SpecReg == "cpsr" || SpecReg == "spsr") {
3720 // cpsr_all is an alias for cpsr_fc, as is plain cpsr.
3721 if (Flags == "all" || Flags == "")
3723 for (int i = 0, e = Flags.size(); i != e; ++i) {
3724 unsigned Flag = StringSwitch<unsigned>(Flags.substr(i, 1))
3731 // If some specific flag is already set, it means that some letter is
3732 // present more than once, this is not acceptable.
3733 if (FlagsVal == ~0U || (FlagsVal & Flag))
3734 return MatchOperand_NoMatch;
3737 } else // No match for special register.
3738 return MatchOperand_NoMatch;
3740 // Special register without flags is NOT equivalent to "fc" flags.
3741 // NOTE: This is a divergence from gas' behavior. Uncommenting the following
3742 // two lines would enable gas compatibility at the expense of breaking
3748 // Bit 4: Special Reg (cpsr, apsr => 0; spsr => 1)
3749 if (SpecReg == "spsr")
3752 Parser.Lex(); // Eat identifier token.
3753 Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S));
3754 return MatchOperand_Success;
3757 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3758 parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands, StringRef Op,
3759 int Low, int High) {
3760 const AsmToken &Tok = Parser.getTok();
3761 if (Tok.isNot(AsmToken::Identifier)) {
3762 Error(Parser.getTok().getLoc(), Op + " operand expected.");
3763 return MatchOperand_ParseFail;
3765 StringRef ShiftName = Tok.getString();
3766 std::string LowerOp = Op.lower();
3767 std::string UpperOp = Op.upper();
3768 if (ShiftName != LowerOp && ShiftName != UpperOp) {
3769 Error(Parser.getTok().getLoc(), Op + " operand expected.");
3770 return MatchOperand_ParseFail;
3772 Parser.Lex(); // Eat shift type token.
3774 // There must be a '#' and a shift amount.
3775 if (Parser.getTok().isNot(AsmToken::Hash) &&
3776 Parser.getTok().isNot(AsmToken::Dollar)) {
3777 Error(Parser.getTok().getLoc(), "'#' expected");
3778 return MatchOperand_ParseFail;
3780 Parser.Lex(); // Eat hash token.
3782 const MCExpr *ShiftAmount;
3783 SMLoc Loc = Parser.getTok().getLoc();
3785 if (getParser().parseExpression(ShiftAmount, EndLoc)) {
3786 Error(Loc, "illegal expression");
3787 return MatchOperand_ParseFail;
3789 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
3791 Error(Loc, "constant expression expected");
3792 return MatchOperand_ParseFail;
3794 int Val = CE->getValue();
3795 if (Val < Low || Val > High) {
3796 Error(Loc, "immediate value out of range");
3797 return MatchOperand_ParseFail;
3800 Operands.push_back(ARMOperand::CreateImm(CE, Loc, EndLoc));
3802 return MatchOperand_Success;
3805 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3806 parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3807 const AsmToken &Tok = Parser.getTok();
3808 SMLoc S = Tok.getLoc();
3809 if (Tok.isNot(AsmToken::Identifier)) {
3810 Error(S, "'be' or 'le' operand expected");
3811 return MatchOperand_ParseFail;
3813 int Val = StringSwitch<int>(Tok.getString().lower())
3817 Parser.Lex(); // Eat the token.
3820 Error(S, "'be' or 'le' operand expected");
3821 return MatchOperand_ParseFail;
3823 Operands.push_back(ARMOperand::CreateImm(MCConstantExpr::Create(Val,
3825 S, Tok.getEndLoc()));
3826 return MatchOperand_Success;
3829 /// parseShifterImm - Parse the shifter immediate operand for SSAT/USAT
3830 /// instructions. Legal values are:
3831 /// lsl #n 'n' in [0,31]
3832 /// asr #n 'n' in [1,32]
3833 /// n == 32 encoded as n == 0.
3834 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3835 parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3836 const AsmToken &Tok = Parser.getTok();
3837 SMLoc S = Tok.getLoc();
3838 if (Tok.isNot(AsmToken::Identifier)) {
3839 Error(S, "shift operator 'asr' or 'lsl' expected");
3840 return MatchOperand_ParseFail;
3842 StringRef ShiftName = Tok.getString();
3844 if (ShiftName == "lsl" || ShiftName == "LSL")
3846 else if (ShiftName == "asr" || ShiftName == "ASR")
3849 Error(S, "shift operator 'asr' or 'lsl' expected");
3850 return MatchOperand_ParseFail;
3852 Parser.Lex(); // Eat the operator.
3854 // A '#' and a shift amount.
3855 if (Parser.getTok().isNot(AsmToken::Hash) &&
3856 Parser.getTok().isNot(AsmToken::Dollar)) {
3857 Error(Parser.getTok().getLoc(), "'#' expected");
3858 return MatchOperand_ParseFail;
3860 Parser.Lex(); // Eat hash token.
3861 SMLoc ExLoc = Parser.getTok().getLoc();
3863 const MCExpr *ShiftAmount;
3865 if (getParser().parseExpression(ShiftAmount, EndLoc)) {
3866 Error(ExLoc, "malformed shift expression");
3867 return MatchOperand_ParseFail;
3869 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
3871 Error(ExLoc, "shift amount must be an immediate");
3872 return MatchOperand_ParseFail;
3875 int64_t Val = CE->getValue();
3877 // Shift amount must be in [1,32]
3878 if (Val < 1 || Val > 32) {
3879 Error(ExLoc, "'asr' shift amount must be in range [1,32]");
3880 return MatchOperand_ParseFail;
3882 // asr #32 encoded as asr #0, but is not allowed in Thumb2 mode.
3883 if (isThumb() && Val == 32) {
3884 Error(ExLoc, "'asr #32' shift amount not allowed in Thumb mode");
3885 return MatchOperand_ParseFail;
3887 if (Val == 32) Val = 0;
3889 // Shift amount must be in [1,32]
3890 if (Val < 0 || Val > 31) {
3891 Error(ExLoc, "'lsr' shift amount must be in range [0,31]");
3892 return MatchOperand_ParseFail;
3896 Operands.push_back(ARMOperand::CreateShifterImm(isASR, Val, S, EndLoc));
3898 return MatchOperand_Success;
3901 /// parseRotImm - Parse the shifter immediate operand for SXTB/UXTB family
3902 /// of instructions. Legal values are:
3903 /// ror #n 'n' in {0, 8, 16, 24}
3904 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3905 parseRotImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3906 const AsmToken &Tok = Parser.getTok();
3907 SMLoc S = Tok.getLoc();
3908 if (Tok.isNot(AsmToken::Identifier))
3909 return MatchOperand_NoMatch;
3910 StringRef ShiftName = Tok.getString();
3911 if (ShiftName != "ror" && ShiftName != "ROR")
3912 return MatchOperand_NoMatch;
3913 Parser.Lex(); // Eat the operator.
3915 // A '#' and a rotate amount.
3916 if (Parser.getTok().isNot(AsmToken::Hash) &&
3917 Parser.getTok().isNot(AsmToken::Dollar)) {
3918 Error(Parser.getTok().getLoc(), "'#' expected");
3919 return MatchOperand_ParseFail;
3921 Parser.Lex(); // Eat hash token.
3922 SMLoc ExLoc = Parser.getTok().getLoc();
3924 const MCExpr *ShiftAmount;
3926 if (getParser().parseExpression(ShiftAmount, EndLoc)) {
3927 Error(ExLoc, "malformed rotate expression");
3928 return MatchOperand_ParseFail;
3930 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
3932 Error(ExLoc, "rotate amount must be an immediate");
3933 return MatchOperand_ParseFail;
3936 int64_t Val = CE->getValue();
3937 // Shift amount must be in {0, 8, 16, 24} (0 is undocumented extension)
3938 // normally, zero is represented in asm by omitting the rotate operand
3940 if (Val != 8 && Val != 16 && Val != 24 && Val != 0) {
3941 Error(ExLoc, "'ror' rotate amount must be 8, 16, or 24");
3942 return MatchOperand_ParseFail;
3945 Operands.push_back(ARMOperand::CreateRotImm(Val, S, EndLoc));
3947 return MatchOperand_Success;
3950 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3951 parseBitfield(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3952 SMLoc S = Parser.getTok().getLoc();
3953 // The bitfield descriptor is really two operands, the LSB and the width.
3954 if (Parser.getTok().isNot(AsmToken::Hash) &&
3955 Parser.getTok().isNot(AsmToken::Dollar)) {
3956 Error(Parser.getTok().getLoc(), "'#' expected");
3957 return MatchOperand_ParseFail;
3959 Parser.Lex(); // Eat hash token.
3961 const MCExpr *LSBExpr;
3962 SMLoc E = Parser.getTok().getLoc();
3963 if (getParser().parseExpression(LSBExpr)) {
3964 Error(E, "malformed immediate expression");
3965 return MatchOperand_ParseFail;
3967 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LSBExpr);
3969 Error(E, "'lsb' operand must be an immediate");
3970 return MatchOperand_ParseFail;
3973 int64_t LSB = CE->getValue();
3974 // The LSB must be in the range [0,31]
3975 if (LSB < 0 || LSB > 31) {
3976 Error(E, "'lsb' operand must be in the range [0,31]");
3977 return MatchOperand_ParseFail;
3979 E = Parser.getTok().getLoc();
3981 // Expect another immediate operand.
3982 if (Parser.getTok().isNot(AsmToken::Comma)) {
3983 Error(Parser.getTok().getLoc(), "too few operands");
3984 return MatchOperand_ParseFail;
3986 Parser.Lex(); // Eat hash token.
3987 if (Parser.getTok().isNot(AsmToken::Hash) &&
3988 Parser.getTok().isNot(AsmToken::Dollar)) {
3989 Error(Parser.getTok().getLoc(), "'#' expected");
3990 return MatchOperand_ParseFail;
3992 Parser.Lex(); // Eat hash token.
3994 const MCExpr *WidthExpr;
3996 if (getParser().parseExpression(WidthExpr, EndLoc)) {
3997 Error(E, "malformed immediate expression");
3998 return MatchOperand_ParseFail;
4000 CE = dyn_cast<MCConstantExpr>(WidthExpr);
4002 Error(E, "'width' operand must be an immediate");
4003 return MatchOperand_ParseFail;
4006 int64_t Width = CE->getValue();
4007 // The LSB must be in the range [1,32-lsb]
4008 if (Width < 1 || Width > 32 - LSB) {
4009 Error(E, "'width' operand must be in the range [1,32-lsb]");
4010 return MatchOperand_ParseFail;
4013 Operands.push_back(ARMOperand::CreateBitfield(LSB, Width, S, EndLoc));
4015 return MatchOperand_Success;
4018 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
4019 parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4020 // Check for a post-index addressing register operand. Specifically:
4021 // postidx_reg := '+' register {, shift}
4022 // | '-' register {, shift}
4023 // | register {, shift}
4025 // This method must return MatchOperand_NoMatch without consuming any tokens
4026 // in the case where there is no match, as other alternatives take other
4028 AsmToken Tok = Parser.getTok();
4029 SMLoc S = Tok.getLoc();
4030 bool haveEaten = false;
4032 if (Tok.is(AsmToken::Plus)) {
4033 Parser.Lex(); // Eat the '+' token.
4035 } else if (Tok.is(AsmToken::Minus)) {
4036 Parser.Lex(); // Eat the '-' token.
4041 SMLoc E = Parser.getTok().getEndLoc();
4042 int Reg = tryParseRegister();
4045 return MatchOperand_NoMatch;
4046 Error(Parser.getTok().getLoc(), "register expected");
4047 return MatchOperand_ParseFail;
4050 ARM_AM::ShiftOpc ShiftTy = ARM_AM::no_shift;
4051 unsigned ShiftImm = 0;
4052 if (Parser.getTok().is(AsmToken::Comma)) {
4053 Parser.Lex(); // Eat the ','.
4054 if (parseMemRegOffsetShift(ShiftTy, ShiftImm))
4055 return MatchOperand_ParseFail;
4057 // FIXME: Only approximates end...may include intervening whitespace.
4058 E = Parser.getTok().getLoc();
4061 Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ShiftTy,
4064 return MatchOperand_Success;
4067 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
4068 parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4069 // Check for a post-index addressing register operand. Specifically:
4070 // am3offset := '+' register
4077 // This method must return MatchOperand_NoMatch without consuming any tokens
4078 // in the case where there is no match, as other alternatives take other
4080 AsmToken Tok = Parser.getTok();
4081 SMLoc S = Tok.getLoc();
4083 // Do immediates first, as we always parse those if we have a '#'.
4084 if (Parser.getTok().is(AsmToken::Hash) ||
4085 Parser.getTok().is(AsmToken::Dollar)) {
4086 Parser.Lex(); // Eat '#' or '$'.
4087 // Explicitly look for a '-', as we need to encode negative zero
4089 bool isNegative = Parser.getTok().is(AsmToken::Minus);
4090 const MCExpr *Offset;
4092 if (getParser().parseExpression(Offset, E))
4093 return MatchOperand_ParseFail;
4094 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
4096 Error(S, "constant expression expected");
4097 return MatchOperand_ParseFail;
4099 // Negative zero is encoded as the flag value INT32_MIN.
4100 int32_t Val = CE->getValue();
4101 if (isNegative && Val == 0)
4105 ARMOperand::CreateImm(MCConstantExpr::Create(Val, getContext()), S, E));
4107 return MatchOperand_Success;
4111 bool haveEaten = false;
4113 if (Tok.is(AsmToken::Plus)) {
4114 Parser.Lex(); // Eat the '+' token.
4116 } else if (Tok.is(AsmToken::Minus)) {
4117 Parser.Lex(); // Eat the '-' token.
4122 Tok = Parser.getTok();
4123 int Reg = tryParseRegister();
4126 return MatchOperand_NoMatch;
4127 Error(Tok.getLoc(), "register expected");
4128 return MatchOperand_ParseFail;
4131 Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ARM_AM::no_shift,
4132 0, S, Tok.getEndLoc()));
4134 return MatchOperand_Success;
4137 /// Convert parsed operands to MCInst. Needed here because this instruction
4138 /// only has two register operands, but multiplication is commutative so
4139 /// assemblers should accept both "mul rD, rN, rD" and "mul rD, rD, rN".
4141 cvtThumbMultiply(MCInst &Inst,
4142 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4143 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
4144 ((ARMOperand*)Operands[1])->addCCOutOperands(Inst, 1);
4145 // If we have a three-operand form, make sure to set Rn to be the operand
4146 // that isn't the same as Rd.
4148 if (Operands.size() == 6 &&
4149 ((ARMOperand*)Operands[4])->getReg() ==
4150 ((ARMOperand*)Operands[3])->getReg())
4152 ((ARMOperand*)Operands[RegOp])->addRegOperands(Inst, 1);
4153 Inst.addOperand(Inst.getOperand(0));
4154 ((ARMOperand*)Operands[2])->addCondCodeOperands(Inst, 2);
4158 cvtThumbBranches(MCInst &Inst,
4159 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4160 int CondOp = -1, ImmOp = -1;
4161 switch(Inst.getOpcode()) {
4163 case ARM::tBcc: CondOp = 1; ImmOp = 2; break;
4166 case ARM::t2Bcc: CondOp = 1; ImmOp = 3; break;
4168 default: llvm_unreachable("Unexpected instruction in cvtThumbBranches");
4170 // first decide whether or not the branch should be conditional
4171 // by looking at it's location relative to an IT block
4173 // inside an IT block we cannot have any conditional branches. any
4174 // such instructions needs to be converted to unconditional form
4175 switch(Inst.getOpcode()) {
4176 case ARM::tBcc: Inst.setOpcode(ARM::tB); break;
4177 case ARM::t2Bcc: Inst.setOpcode(ARM::t2B); break;
4180 // outside IT blocks we can only have unconditional branches with AL
4181 // condition code or conditional branches with non-AL condition code
4182 unsigned Cond = static_cast<ARMOperand*>(Operands[CondOp])->getCondCode();
4183 switch(Inst.getOpcode()) {
4186 Inst.setOpcode(Cond == ARMCC::AL ? ARM::tB : ARM::tBcc);
4190 Inst.setOpcode(Cond == ARMCC::AL ? ARM::t2B : ARM::t2Bcc);
4195 // now decide on encoding size based on branch target range
4196 switch(Inst.getOpcode()) {
4197 // classify tB as either t2B or t1B based on range of immediate operand
4199 ARMOperand* op = static_cast<ARMOperand*>(Operands[ImmOp]);
4200 if(!op->isSignedOffset<11, 1>() && isThumbTwo())
4201 Inst.setOpcode(ARM::t2B);
4204 // classify tBcc as either t2Bcc or t1Bcc based on range of immediate operand
4206 ARMOperand* op = static_cast<ARMOperand*>(Operands[ImmOp]);
4207 if(!op->isSignedOffset<8, 1>() && isThumbTwo())
4208 Inst.setOpcode(ARM::t2Bcc);
4212 ((ARMOperand*)Operands[ImmOp])->addImmOperands(Inst, 1);
4213 ((ARMOperand*)Operands[CondOp])->addCondCodeOperands(Inst, 2);
4216 /// Parse an ARM memory expression, return false if successful else return true
4217 /// or an error. The first token must be a '[' when called.
4219 parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4221 assert(Parser.getTok().is(AsmToken::LBrac) &&
4222 "Token is not a Left Bracket");
4223 S = Parser.getTok().getLoc();
4224 Parser.Lex(); // Eat left bracket token.
4226 const AsmToken &BaseRegTok = Parser.getTok();
4227 int BaseRegNum = tryParseRegister();
4228 if (BaseRegNum == -1)
4229 return Error(BaseRegTok.getLoc(), "register expected");
4231 // The next token must either be a comma, a colon or a closing bracket.
4232 const AsmToken &Tok = Parser.getTok();
4233 if (!Tok.is(AsmToken::Colon) && !Tok.is(AsmToken::Comma) &&
4234 !Tok.is(AsmToken::RBrac))
4235 return Error(Tok.getLoc(), "malformed memory operand");
4237 if (Tok.is(AsmToken::RBrac)) {
4238 E = Tok.getEndLoc();
4239 Parser.Lex(); // Eat right bracket token.
4241 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, 0, ARM_AM::no_shift,
4242 0, 0, false, S, E));
4244 // If there's a pre-indexing writeback marker, '!', just add it as a token
4245 // operand. It's rather odd, but syntactically valid.
4246 if (Parser.getTok().is(AsmToken::Exclaim)) {
4247 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4248 Parser.Lex(); // Eat the '!'.
4254 assert((Tok.is(AsmToken::Colon) || Tok.is(AsmToken::Comma)) &&
4255 "Lost colon or comma in memory operand?!");
4256 if (Tok.is(AsmToken::Comma)) {
4257 Parser.Lex(); // Eat the comma.
4260 // If we have a ':', it's an alignment specifier.
4261 if (Parser.getTok().is(AsmToken::Colon)) {
4262 Parser.Lex(); // Eat the ':'.
4263 E = Parser.getTok().getLoc();
4266 if (getParser().parseExpression(Expr))
4269 // The expression has to be a constant. Memory references with relocations
4270 // don't come through here, as they use the <label> forms of the relevant
4272 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
4274 return Error (E, "constant expression expected");
4277 switch (CE->getValue()) {
4280 "alignment specifier must be 16, 32, 64, 128, or 256 bits");
4281 case 16: Align = 2; break;
4282 case 32: Align = 4; break;
4283 case 64: Align = 8; break;
4284 case 128: Align = 16; break;
4285 case 256: Align = 32; break;
4288 // Now we should have the closing ']'
4289 if (Parser.getTok().isNot(AsmToken::RBrac))
4290 return Error(Parser.getTok().getLoc(), "']' expected");
4291 E = Parser.getTok().getEndLoc();
4292 Parser.Lex(); // Eat right bracket token.
4294 // Don't worry about range checking the value here. That's handled by
4295 // the is*() predicates.
4296 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, 0,
4297 ARM_AM::no_shift, 0, Align,
4300 // If there's a pre-indexing writeback marker, '!', just add it as a token
4302 if (Parser.getTok().is(AsmToken::Exclaim)) {
4303 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4304 Parser.Lex(); // Eat the '!'.
4310 // If we have a '#', it's an immediate offset, else assume it's a register
4311 // offset. Be friendly and also accept a plain integer (without a leading
4312 // hash) for gas compatibility.
4313 if (Parser.getTok().is(AsmToken::Hash) ||
4314 Parser.getTok().is(AsmToken::Dollar) ||
4315 Parser.getTok().is(AsmToken::Integer)) {
4316 if (Parser.getTok().isNot(AsmToken::Integer))
4317 Parser.Lex(); // Eat '#' or '$'.
4318 E = Parser.getTok().getLoc();
4320 bool isNegative = getParser().getTok().is(AsmToken::Minus);
4321 const MCExpr *Offset;
4322 if (getParser().parseExpression(Offset))
4325 // The expression has to be a constant. Memory references with relocations
4326 // don't come through here, as they use the <label> forms of the relevant
4328 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
4330 return Error (E, "constant expression expected");
4332 // If the constant was #-0, represent it as INT32_MIN.
4333 int32_t Val = CE->getValue();
4334 if (isNegative && Val == 0)
4335 CE = MCConstantExpr::Create(INT32_MIN, getContext());
4337 // Now we should have the closing ']'
4338 if (Parser.getTok().isNot(AsmToken::RBrac))
4339 return Error(Parser.getTok().getLoc(), "']' expected");
4340 E = Parser.getTok().getEndLoc();
4341 Parser.Lex(); // Eat right bracket token.
4343 // Don't worry about range checking the value here. That's handled by
4344 // the is*() predicates.
4345 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, CE, 0,
4346 ARM_AM::no_shift, 0, 0,
4349 // If there's a pre-indexing writeback marker, '!', just add it as a token
4351 if (Parser.getTok().is(AsmToken::Exclaim)) {
4352 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4353 Parser.Lex(); // Eat the '!'.
4359 // The register offset is optionally preceded by a '+' or '-'
4360 bool isNegative = false;
4361 if (Parser.getTok().is(AsmToken::Minus)) {
4363 Parser.Lex(); // Eat the '-'.
4364 } else if (Parser.getTok().is(AsmToken::Plus)) {
4366 Parser.Lex(); // Eat the '+'.
4369 E = Parser.getTok().getLoc();
4370 int OffsetRegNum = tryParseRegister();
4371 if (OffsetRegNum == -1)
4372 return Error(E, "register expected");
4374 // If there's a shift operator, handle it.
4375 ARM_AM::ShiftOpc ShiftType = ARM_AM::no_shift;
4376 unsigned ShiftImm = 0;
4377 if (Parser.getTok().is(AsmToken::Comma)) {
4378 Parser.Lex(); // Eat the ','.
4379 if (parseMemRegOffsetShift(ShiftType, ShiftImm))
4383 // Now we should have the closing ']'
4384 if (Parser.getTok().isNot(AsmToken::RBrac))
4385 return Error(Parser.getTok().getLoc(), "']' expected");
4386 E = Parser.getTok().getEndLoc();
4387 Parser.Lex(); // Eat right bracket token.
4389 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, OffsetRegNum,
4390 ShiftType, ShiftImm, 0, isNegative,
4393 // If there's a pre-indexing writeback marker, '!', just add it as a token
4395 if (Parser.getTok().is(AsmToken::Exclaim)) {
4396 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4397 Parser.Lex(); // Eat the '!'.
4403 /// parseMemRegOffsetShift - one of these two:
4404 /// ( lsl | lsr | asr | ror ) , # shift_amount
4406 /// return true if it parses a shift otherwise it returns false.
4407 bool ARMAsmParser::parseMemRegOffsetShift(ARM_AM::ShiftOpc &St,
4409 SMLoc Loc = Parser.getTok().getLoc();
4410 const AsmToken &Tok = Parser.getTok();
4411 if (Tok.isNot(AsmToken::Identifier))
4413 StringRef ShiftName = Tok.getString();
4414 if (ShiftName == "lsl" || ShiftName == "LSL" ||
4415 ShiftName == "asl" || ShiftName == "ASL")
4417 else if (ShiftName == "lsr" || ShiftName == "LSR")
4419 else if (ShiftName == "asr" || ShiftName == "ASR")
4421 else if (ShiftName == "ror" || ShiftName == "ROR")
4423 else if (ShiftName == "rrx" || ShiftName == "RRX")
4426 return Error(Loc, "illegal shift operator");
4427 Parser.Lex(); // Eat shift type token.
4429 // rrx stands alone.
4431 if (St != ARM_AM::rrx) {
4432 Loc = Parser.getTok().getLoc();
4433 // A '#' and a shift amount.
4434 const AsmToken &HashTok = Parser.getTok();
4435 if (HashTok.isNot(AsmToken::Hash) &&
4436 HashTok.isNot(AsmToken::Dollar))
4437 return Error(HashTok.getLoc(), "'#' expected");
4438 Parser.Lex(); // Eat hash token.
4441 if (getParser().parseExpression(Expr))
4443 // Range check the immediate.
4444 // lsl, ror: 0 <= imm <= 31
4445 // lsr, asr: 0 <= imm <= 32
4446 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
4448 return Error(Loc, "shift amount must be an immediate");
4449 int64_t Imm = CE->getValue();
4451 ((St == ARM_AM::lsl || St == ARM_AM::ror) && Imm > 31) ||
4452 ((St == ARM_AM::lsr || St == ARM_AM::asr) && Imm > 32))
4453 return Error(Loc, "immediate shift value out of range");
4454 // If <ShiftTy> #0, turn it into a no_shift.
4457 // For consistency, treat lsr #32 and asr #32 as having immediate value 0.
4466 /// parseFPImm - A floating point immediate expression operand.
4467 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
4468 parseFPImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4469 // Anything that can accept a floating point constant as an operand
4470 // needs to go through here, as the regular parseExpression is
4473 // This routine still creates a generic Immediate operand, containing
4474 // a bitcast of the 64-bit floating point value. The various operands
4475 // that accept floats can check whether the value is valid for them
4476 // via the standard is*() predicates.
4478 SMLoc S = Parser.getTok().getLoc();
4480 if (Parser.getTok().isNot(AsmToken::Hash) &&
4481 Parser.getTok().isNot(AsmToken::Dollar))
4482 return MatchOperand_NoMatch;
4484 // Disambiguate the VMOV forms that can accept an FP immediate.
4485 // vmov.f32 <sreg>, #imm
4486 // vmov.f64 <dreg>, #imm
4487 // vmov.f32 <dreg>, #imm @ vector f32x2
4488 // vmov.f32 <qreg>, #imm @ vector f32x4
4490 // There are also the NEON VMOV instructions which expect an
4491 // integer constant. Make sure we don't try to parse an FPImm
4493 // vmov.i{8|16|32|64} <dreg|qreg>, #imm
4494 ARMOperand *TyOp = static_cast<ARMOperand*>(Operands[2]);
4495 if (!TyOp->isToken() || (TyOp->getToken() != ".f32" &&
4496 TyOp->getToken() != ".f64"))
4497 return MatchOperand_NoMatch;
4499 Parser.Lex(); // Eat '#' or '$'.
4501 // Handle negation, as that still comes through as a separate token.
4502 bool isNegative = false;
4503 if (Parser.getTok().is(AsmToken::Minus)) {
4507 const AsmToken &Tok = Parser.getTok();
4508 SMLoc Loc = Tok.getLoc();
4509 if (Tok.is(AsmToken::Real)) {
4510 APFloat RealVal(APFloat::IEEEsingle, Tok.getString());
4511 uint64_t IntVal = RealVal.bitcastToAPInt().getZExtValue();
4512 // If we had a '-' in front, toggle the sign bit.
4513 IntVal ^= (uint64_t)isNegative << 31;
4514 Parser.Lex(); // Eat the token.
4515 Operands.push_back(ARMOperand::CreateImm(
4516 MCConstantExpr::Create(IntVal, getContext()),
4517 S, Parser.getTok().getLoc()));
4518 return MatchOperand_Success;
4520 // Also handle plain integers. Instructions which allow floating point
4521 // immediates also allow a raw encoded 8-bit value.
4522 if (Tok.is(AsmToken::Integer)) {
4523 int64_t Val = Tok.getIntVal();
4524 Parser.Lex(); // Eat the token.
4525 if (Val > 255 || Val < 0) {
4526 Error(Loc, "encoded floating point value out of range");
4527 return MatchOperand_ParseFail;
4529 double RealVal = ARM_AM::getFPImmFloat(Val);
4530 Val = APFloat(APFloat::IEEEdouble, RealVal).bitcastToAPInt().getZExtValue();
4531 Operands.push_back(ARMOperand::CreateImm(
4532 MCConstantExpr::Create(Val, getContext()), S,
4533 Parser.getTok().getLoc()));
4534 return MatchOperand_Success;
4537 Error(Loc, "invalid floating point immediate");
4538 return MatchOperand_ParseFail;
4541 /// Parse a arm instruction operand. For now this parses the operand regardless
4542 /// of the mnemonic.
4543 bool ARMAsmParser::parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
4544 StringRef Mnemonic) {
4547 // Check if the current operand has a custom associated parser, if so, try to
4548 // custom parse the operand, or fallback to the general approach.
4549 OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
4550 if (ResTy == MatchOperand_Success)
4552 // If there wasn't a custom match, try the generic matcher below. Otherwise,
4553 // there was a match, but an error occurred, in which case, just return that
4554 // the operand parsing failed.
4555 if (ResTy == MatchOperand_ParseFail)
4558 switch (getLexer().getKind()) {
4560 Error(Parser.getTok().getLoc(), "unexpected token in operand");
4562 case AsmToken::Identifier: {
4563 // If we've seen a branch mnemonic, the next operand must be a label. This
4564 // is true even if the label is a register name. So "br r1" means branch to
4566 bool ExpectLabel = Mnemonic == "b" || Mnemonic == "bl";
4568 if (!tryParseRegisterWithWriteBack(Operands))
4570 int Res = tryParseShiftRegister(Operands);
4571 if (Res == 0) // success
4573 else if (Res == -1) // irrecoverable error
4575 // If this is VMRS, check for the apsr_nzcv operand.
4576 if (Mnemonic == "vmrs" &&
4577 Parser.getTok().getString().equals_lower("apsr_nzcv")) {
4578 S = Parser.getTok().getLoc();
4580 Operands.push_back(ARMOperand::CreateToken("APSR_nzcv", S));
4585 // Fall though for the Identifier case that is not a register or a
4588 case AsmToken::LParen: // parenthesized expressions like (_strcmp-4)
4589 case AsmToken::Integer: // things like 1f and 2b as a branch targets
4590 case AsmToken::String: // quoted label names.
4591 case AsmToken::Dot: { // . as a branch target
4592 // This was not a register so parse other operands that start with an
4593 // identifier (like labels) as expressions and create them as immediates.
4594 const MCExpr *IdVal;
4595 S = Parser.getTok().getLoc();
4596 if (getParser().parseExpression(IdVal))
4598 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
4599 Operands.push_back(ARMOperand::CreateImm(IdVal, S, E));
4602 case AsmToken::LBrac:
4603 return parseMemory(Operands);
4604 case AsmToken::LCurly:
4605 return parseRegisterList(Operands);
4606 case AsmToken::Dollar:
4607 case AsmToken::Hash: {
4608 // #42 -> immediate.
4609 S = Parser.getTok().getLoc();
4612 if (Parser.getTok().isNot(AsmToken::Colon)) {
4613 bool isNegative = Parser.getTok().is(AsmToken::Minus);
4614 const MCExpr *ImmVal;
4615 if (getParser().parseExpression(ImmVal))
4617 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ImmVal);
4619 int32_t Val = CE->getValue();
4620 if (isNegative && Val == 0)
4621 ImmVal = MCConstantExpr::Create(INT32_MIN, getContext());
4623 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
4624 Operands.push_back(ARMOperand::CreateImm(ImmVal, S, E));
4626 // There can be a trailing '!' on operands that we want as a separate
4627 // '!' Token operand. Handle that here. For example, the compatibilty
4628 // alias for 'srsdb sp!, #imm' is 'srsdb #imm!'.
4629 if (Parser.getTok().is(AsmToken::Exclaim)) {
4630 Operands.push_back(ARMOperand::CreateToken(Parser.getTok().getString(),
4631 Parser.getTok().getLoc()));
4632 Parser.Lex(); // Eat exclaim token
4636 // w/ a ':' after the '#', it's just like a plain ':'.
4639 case AsmToken::Colon: {
4640 // ":lower16:" and ":upper16:" expression prefixes
4641 // FIXME: Check it's an expression prefix,
4642 // e.g. (FOO - :lower16:BAR) isn't legal.
4643 ARMMCExpr::VariantKind RefKind;
4644 if (parsePrefix(RefKind))
4647 const MCExpr *SubExprVal;
4648 if (getParser().parseExpression(SubExprVal))
4651 const MCExpr *ExprVal = ARMMCExpr::Create(RefKind, SubExprVal,
4653 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
4654 Operands.push_back(ARMOperand::CreateImm(ExprVal, S, E));
4660 // parsePrefix - Parse ARM 16-bit relocations expression prefix, i.e.
4661 // :lower16: and :upper16:.
4662 bool ARMAsmParser::parsePrefix(ARMMCExpr::VariantKind &RefKind) {
4663 RefKind = ARMMCExpr::VK_ARM_None;
4665 // :lower16: and :upper16: modifiers
4666 assert(getLexer().is(AsmToken::Colon) && "expected a :");
4667 Parser.Lex(); // Eat ':'
4669 if (getLexer().isNot(AsmToken::Identifier)) {
4670 Error(Parser.getTok().getLoc(), "expected prefix identifier in operand");
4674 StringRef IDVal = Parser.getTok().getIdentifier();
4675 if (IDVal == "lower16") {
4676 RefKind = ARMMCExpr::VK_ARM_LO16;
4677 } else if (IDVal == "upper16") {
4678 RefKind = ARMMCExpr::VK_ARM_HI16;
4680 Error(Parser.getTok().getLoc(), "unexpected prefix in operand");
4685 if (getLexer().isNot(AsmToken::Colon)) {
4686 Error(Parser.getTok().getLoc(), "unexpected token after prefix");
4689 Parser.Lex(); // Eat the last ':'
4693 /// \brief Given a mnemonic, split out possible predication code and carry
4694 /// setting letters to form a canonical mnemonic and flags.
4696 // FIXME: Would be nice to autogen this.
4697 // FIXME: This is a bit of a maze of special cases.
4698 StringRef ARMAsmParser::splitMnemonic(StringRef Mnemonic,
4699 unsigned &PredicationCode,
4701 unsigned &ProcessorIMod,
4702 StringRef &ITMask) {
4703 PredicationCode = ARMCC::AL;
4704 CarrySetting = false;
4707 // Ignore some mnemonics we know aren't predicated forms.
4709 // FIXME: Would be nice to autogen this.
4710 if ((Mnemonic == "movs" && isThumb()) ||
4711 Mnemonic == "teq" || Mnemonic == "vceq" || Mnemonic == "svc" ||
4712 Mnemonic == "mls" || Mnemonic == "smmls" || Mnemonic == "vcls" ||
4713 Mnemonic == "vmls" || Mnemonic == "vnmls" || Mnemonic == "vacge" ||
4714 Mnemonic == "vcge" || Mnemonic == "vclt" || Mnemonic == "vacgt" ||
4715 Mnemonic == "vaclt" || Mnemonic == "vacle" || Mnemonic == "hlt" ||
4716 Mnemonic == "vcgt" || Mnemonic == "vcle" || Mnemonic == "smlal" ||
4717 Mnemonic == "umaal" || Mnemonic == "umlal" || Mnemonic == "vabal" ||
4718 Mnemonic == "vmlal" || Mnemonic == "vpadal" || Mnemonic == "vqdmlal" ||
4719 Mnemonic == "fmuls" || Mnemonic == "vmaxnm" || Mnemonic == "vminnm" ||
4720 Mnemonic == "vcvta" || Mnemonic == "vcvtn" || Mnemonic == "vcvtp" ||
4721 Mnemonic == "vcvtm" || Mnemonic == "vrinta" || Mnemonic == "vrintn" ||
4722 Mnemonic == "vrintp" || Mnemonic == "vrintm" || Mnemonic.startswith("vsel"))
4725 // First, split out any predication code. Ignore mnemonics we know aren't
4726 // predicated but do have a carry-set and so weren't caught above.
4727 if (Mnemonic != "adcs" && Mnemonic != "bics" && Mnemonic != "movs" &&
4728 Mnemonic != "muls" && Mnemonic != "smlals" && Mnemonic != "smulls" &&
4729 Mnemonic != "umlals" && Mnemonic != "umulls" && Mnemonic != "lsls" &&
4730 Mnemonic != "sbcs" && Mnemonic != "rscs") {
4731 unsigned CC = StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2))
4732 .Case("eq", ARMCC::EQ)
4733 .Case("ne", ARMCC::NE)
4734 .Case("hs", ARMCC::HS)
4735 .Case("cs", ARMCC::HS)
4736 .Case("lo", ARMCC::LO)
4737 .Case("cc", ARMCC::LO)
4738 .Case("mi", ARMCC::MI)
4739 .Case("pl", ARMCC::PL)
4740 .Case("vs", ARMCC::VS)
4741 .Case("vc", ARMCC::VC)
4742 .Case("hi", ARMCC::HI)
4743 .Case("ls", ARMCC::LS)
4744 .Case("ge", ARMCC::GE)
4745 .Case("lt", ARMCC::LT)
4746 .Case("gt", ARMCC::GT)
4747 .Case("le", ARMCC::LE)
4748 .Case("al", ARMCC::AL)
4751 Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 2);
4752 PredicationCode = CC;
4756 // Next, determine if we have a carry setting bit. We explicitly ignore all
4757 // the instructions we know end in 's'.
4758 if (Mnemonic.endswith("s") &&
4759 !(Mnemonic == "cps" || Mnemonic == "mls" ||
4760 Mnemonic == "mrs" || Mnemonic == "smmls" || Mnemonic == "vabs" ||
4761 Mnemonic == "vcls" || Mnemonic == "vmls" || Mnemonic == "vmrs" ||
4762 Mnemonic == "vnmls" || Mnemonic == "vqabs" || Mnemonic == "vrecps" ||
4763 Mnemonic == "vrsqrts" || Mnemonic == "srs" || Mnemonic == "flds" ||
4764 Mnemonic == "fmrs" || Mnemonic == "fsqrts" || Mnemonic == "fsubs" ||
4765 Mnemonic == "fsts" || Mnemonic == "fcpys" || Mnemonic == "fdivs" ||
4766 Mnemonic == "fmuls" || Mnemonic == "fcmps" || Mnemonic == "fcmpzs" ||
4767 Mnemonic == "vfms" || Mnemonic == "vfnms" ||
4768 (Mnemonic == "movs" && isThumb()))) {
4769 Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 1);
4770 CarrySetting = true;
4773 // The "cps" instruction can have a interrupt mode operand which is glued into
4774 // the mnemonic. Check if this is the case, split it and parse the imod op
4775 if (Mnemonic.startswith("cps")) {
4776 // Split out any imod code.
4778 StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2, 2))
4779 .Case("ie", ARM_PROC::IE)
4780 .Case("id", ARM_PROC::ID)
4783 Mnemonic = Mnemonic.slice(0, Mnemonic.size()-2);
4784 ProcessorIMod = IMod;
4788 // The "it" instruction has the condition mask on the end of the mnemonic.
4789 if (Mnemonic.startswith("it")) {
4790 ITMask = Mnemonic.slice(2, Mnemonic.size());
4791 Mnemonic = Mnemonic.slice(0, 2);
4797 /// \brief Given a canonical mnemonic, determine if the instruction ever allows
4798 /// inclusion of carry set or predication code operands.
4800 // FIXME: It would be nice to autogen this.
4802 getMnemonicAcceptInfo(StringRef Mnemonic, StringRef FullInst,
4803 bool &CanAcceptCarrySet, bool &CanAcceptPredicationCode) {
4804 if (Mnemonic == "and" || Mnemonic == "lsl" || Mnemonic == "lsr" ||
4805 Mnemonic == "rrx" || Mnemonic == "ror" || Mnemonic == "sub" ||
4806 Mnemonic == "add" || Mnemonic == "adc" ||
4807 Mnemonic == "mul" || Mnemonic == "bic" || Mnemonic == "asr" ||
4808 Mnemonic == "orr" || Mnemonic == "mvn" ||
4809 Mnemonic == "rsb" || Mnemonic == "rsc" || Mnemonic == "orn" ||
4810 Mnemonic == "sbc" || Mnemonic == "eor" || Mnemonic == "neg" ||
4811 Mnemonic == "vfm" || Mnemonic == "vfnm" ||
4812 (!isThumb() && (Mnemonic == "smull" || Mnemonic == "mov" ||
4813 Mnemonic == "mla" || Mnemonic == "smlal" ||
4814 Mnemonic == "umlal" || Mnemonic == "umull"))) {
4815 CanAcceptCarrySet = true;
4817 CanAcceptCarrySet = false;
4819 if (Mnemonic == "bkpt" || Mnemonic == "cbnz" || Mnemonic == "setend" ||
4820 Mnemonic == "cps" || Mnemonic == "it" || Mnemonic == "cbz" ||
4821 Mnemonic == "trap" || Mnemonic == "hlt" || Mnemonic.startswith("crc32") ||
4822 Mnemonic.startswith("cps") || Mnemonic.startswith("vsel") ||
4823 Mnemonic == "vmaxnm" || Mnemonic == "vminnm" || Mnemonic == "vcvta" ||
4824 Mnemonic == "vcvtn" || Mnemonic == "vcvtp" || Mnemonic == "vcvtm" ||
4825 Mnemonic == "vrinta" || Mnemonic == "vrintn" || Mnemonic == "vrintp" ||
4826 Mnemonic == "vrintm" || Mnemonic.startswith("aes") ||
4827 Mnemonic.startswith("sha1") || Mnemonic.startswith("sha256") ||
4828 (FullInst.startswith("vmull") && FullInst.endswith(".p64"))) {
4829 // These mnemonics are never predicable
4830 CanAcceptPredicationCode = false;
4831 } else if (!isThumb()) {
4832 // Some instructions are only predicable in Thumb mode
4833 CanAcceptPredicationCode
4834 = Mnemonic != "cdp2" && Mnemonic != "clrex" && Mnemonic != "mcr2" &&
4835 Mnemonic != "mcrr2" && Mnemonic != "mrc2" && Mnemonic != "mrrc2" &&
4836 Mnemonic != "dmb" && Mnemonic != "dsb" && Mnemonic != "isb" &&
4837 Mnemonic != "pld" && Mnemonic != "pli" && Mnemonic != "pldw" &&
4838 Mnemonic != "ldc2" && Mnemonic != "ldc2l" &&
4839 Mnemonic != "stc2" && Mnemonic != "stc2l" &&
4840 !Mnemonic.startswith("rfe") && !Mnemonic.startswith("srs");
4841 } else if (isThumbOne()) {
4843 CanAcceptPredicationCode = Mnemonic != "movs";
4845 CanAcceptPredicationCode = Mnemonic != "nop" && Mnemonic != "movs";
4847 CanAcceptPredicationCode = true;
4850 bool ARMAsmParser::shouldOmitCCOutOperand(StringRef Mnemonic,
4851 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4852 // FIXME: This is all horribly hacky. We really need a better way to deal
4853 // with optional operands like this in the matcher table.
4855 // The 'mov' mnemonic is special. One variant has a cc_out operand, while
4856 // another does not. Specifically, the MOVW instruction does not. So we
4857 // special case it here and remove the defaulted (non-setting) cc_out
4858 // operand if that's the instruction we're trying to match.
4860 // We do this as post-processing of the explicit operands rather than just
4861 // conditionally adding the cc_out in the first place because we need
4862 // to check the type of the parsed immediate operand.
4863 if (Mnemonic == "mov" && Operands.size() > 4 && !isThumb() &&
4864 !static_cast<ARMOperand*>(Operands[4])->isARMSOImm() &&
4865 static_cast<ARMOperand*>(Operands[4])->isImm0_65535Expr() &&
4866 static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
4869 // Register-register 'add' for thumb does not have a cc_out operand
4870 // when there are only two register operands.
4871 if (isThumb() && Mnemonic == "add" && Operands.size() == 5 &&
4872 static_cast<ARMOperand*>(Operands[3])->isReg() &&
4873 static_cast<ARMOperand*>(Operands[4])->isReg() &&
4874 static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
4876 // Register-register 'add' for thumb does not have a cc_out operand
4877 // when it's an ADD Rdm, SP, {Rdm|#imm0_255} instruction. We do
4878 // have to check the immediate range here since Thumb2 has a variant
4879 // that can handle a different range and has a cc_out operand.
4880 if (((isThumb() && Mnemonic == "add") ||
4881 (isThumbTwo() && Mnemonic == "sub")) &&
4882 Operands.size() == 6 &&
4883 static_cast<ARMOperand*>(Operands[3])->isReg() &&
4884 static_cast<ARMOperand*>(Operands[4])->isReg() &&
4885 static_cast<ARMOperand*>(Operands[4])->getReg() == ARM::SP &&
4886 static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
4887 ((Mnemonic == "add" &&static_cast<ARMOperand*>(Operands[5])->isReg()) ||
4888 static_cast<ARMOperand*>(Operands[5])->isImm0_1020s4()))
4890 // For Thumb2, add/sub immediate does not have a cc_out operand for the
4891 // imm0_4095 variant. That's the least-preferred variant when
4892 // selecting via the generic "add" mnemonic, so to know that we
4893 // should remove the cc_out operand, we have to explicitly check that
4894 // it's not one of the other variants. Ugh.
4895 if (isThumbTwo() && (Mnemonic == "add" || Mnemonic == "sub") &&
4896 Operands.size() == 6 &&
4897 static_cast<ARMOperand*>(Operands[3])->isReg() &&
4898 static_cast<ARMOperand*>(Operands[4])->isReg() &&
4899 static_cast<ARMOperand*>(Operands[5])->isImm()) {
4900 // Nest conditions rather than one big 'if' statement for readability.
4902 // If both registers are low, we're in an IT block, and the immediate is
4903 // in range, we should use encoding T1 instead, which has a cc_out.
4905 isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) &&
4906 isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) &&
4907 static_cast<ARMOperand*>(Operands[5])->isImm0_7())
4909 // Check against T3. If the second register is the PC, this is an
4910 // alternate form of ADR, which uses encoding T4, so check for that too.
4911 if (static_cast<ARMOperand*>(Operands[4])->getReg() != ARM::PC &&
4912 static_cast<ARMOperand*>(Operands[5])->isT2SOImm())
4915 // Otherwise, we use encoding T4, which does not have a cc_out
4920 // The thumb2 multiply instruction doesn't have a CCOut register, so
4921 // if we have a "mul" mnemonic in Thumb mode, check if we'll be able to
4922 // use the 16-bit encoding or not.
4923 if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 6 &&
4924 static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
4925 static_cast<ARMOperand*>(Operands[3])->isReg() &&
4926 static_cast<ARMOperand*>(Operands[4])->isReg() &&
4927 static_cast<ARMOperand*>(Operands[5])->isReg() &&
4928 // If the registers aren't low regs, the destination reg isn't the
4929 // same as one of the source regs, or the cc_out operand is zero
4930 // outside of an IT block, we have to use the 32-bit encoding, so
4931 // remove the cc_out operand.
4932 (!isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) ||
4933 !isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) ||
4934 !isARMLowRegister(static_cast<ARMOperand*>(Operands[5])->getReg()) ||
4936 (static_cast<ARMOperand*>(Operands[3])->getReg() !=
4937 static_cast<ARMOperand*>(Operands[5])->getReg() &&
4938 static_cast<ARMOperand*>(Operands[3])->getReg() !=
4939 static_cast<ARMOperand*>(Operands[4])->getReg())))
4942 // Also check the 'mul' syntax variant that doesn't specify an explicit
4943 // destination register.
4944 if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 5 &&
4945 static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
4946 static_cast<ARMOperand*>(Operands[3])->isReg() &&
4947 static_cast<ARMOperand*>(Operands[4])->isReg() &&
4948 // If the registers aren't low regs or the cc_out operand is zero
4949 // outside of an IT block, we have to use the 32-bit encoding, so
4950 // remove the cc_out operand.
4951 (!isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) ||
4952 !isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) ||
4958 // Register-register 'add/sub' for thumb does not have a cc_out operand
4959 // when it's an ADD/SUB SP, #imm. Be lenient on count since there's also
4960 // the "add/sub SP, SP, #imm" version. If the follow-up operands aren't
4961 // right, this will result in better diagnostics (which operand is off)
4963 if (isThumb() && (Mnemonic == "add" || Mnemonic == "sub") &&
4964 (Operands.size() == 5 || Operands.size() == 6) &&
4965 static_cast<ARMOperand*>(Operands[3])->isReg() &&
4966 static_cast<ARMOperand*>(Operands[3])->getReg() == ARM::SP &&
4967 static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
4968 (static_cast<ARMOperand*>(Operands[4])->isImm() ||
4969 (Operands.size() == 6 &&
4970 static_cast<ARMOperand*>(Operands[5])->isImm())))
4976 bool ARMAsmParser::shouldOmitPredicateOperand(
4977 StringRef Mnemonic, SmallVectorImpl<MCParsedAsmOperand *> &Operands) {
4978 // VRINT{Z, R, X} have a predicate operand in VFP, but not in NEON
4979 unsigned RegIdx = 3;
4980 if ((Mnemonic == "vrintz" || Mnemonic == "vrintx" || Mnemonic == "vrintr") &&
4981 static_cast<ARMOperand *>(Operands[2])->getToken() == ".f32") {
4982 if (static_cast<ARMOperand *>(Operands[3])->isToken() &&
4983 static_cast<ARMOperand *>(Operands[3])->getToken() == ".f32")
4986 if (static_cast<ARMOperand *>(Operands[RegIdx])->isReg() &&
4987 (ARMMCRegisterClasses[ARM::DPRRegClassID]
4988 .contains(static_cast<ARMOperand *>(Operands[RegIdx])->getReg()) ||
4989 ARMMCRegisterClasses[ARM::QPRRegClassID]
4990 .contains(static_cast<ARMOperand *>(Operands[RegIdx])->getReg())))
4996 static bool isDataTypeToken(StringRef Tok) {
4997 return Tok == ".8" || Tok == ".16" || Tok == ".32" || Tok == ".64" ||
4998 Tok == ".i8" || Tok == ".i16" || Tok == ".i32" || Tok == ".i64" ||
4999 Tok == ".u8" || Tok == ".u16" || Tok == ".u32" || Tok == ".u64" ||
5000 Tok == ".s8" || Tok == ".s16" || Tok == ".s32" || Tok == ".s64" ||
5001 Tok == ".p8" || Tok == ".p16" || Tok == ".f32" || Tok == ".f64" ||
5002 Tok == ".f" || Tok == ".d";
5005 // FIXME: This bit should probably be handled via an explicit match class
5006 // in the .td files that matches the suffix instead of having it be
5007 // a literal string token the way it is now.
5008 static bool doesIgnoreDataTypeSuffix(StringRef Mnemonic, StringRef DT) {
5009 return Mnemonic.startswith("vldm") || Mnemonic.startswith("vstm");
5011 static void applyMnemonicAliases(StringRef &Mnemonic, unsigned Features,
5012 unsigned VariantID);
5013 /// Parse an arm instruction mnemonic followed by its operands.
5014 bool ARMAsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
5016 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
5017 // Apply mnemonic aliases before doing anything else, as the destination
5018 // mnemnonic may include suffices and we want to handle them normally.
5019 // The generic tblgen'erated code does this later, at the start of
5020 // MatchInstructionImpl(), but that's too late for aliases that include
5021 // any sort of suffix.
5022 unsigned AvailableFeatures = getAvailableFeatures();
5023 unsigned AssemblerDialect = getParser().getAssemblerDialect();
5024 applyMnemonicAliases(Name, AvailableFeatures, AssemblerDialect);
5026 // First check for the ARM-specific .req directive.
5027 if (Parser.getTok().is(AsmToken::Identifier) &&
5028 Parser.getTok().getIdentifier() == ".req") {
5029 parseDirectiveReq(Name, NameLoc);
5030 // We always return 'error' for this, as we're done with this
5031 // statement and don't need to match the 'instruction."
5035 // Create the leading tokens for the mnemonic, split by '.' characters.
5036 size_t Start = 0, Next = Name.find('.');
5037 StringRef Mnemonic = Name.slice(Start, Next);
5039 // Split out the predication code and carry setting flag from the mnemonic.
5040 unsigned PredicationCode;
5041 unsigned ProcessorIMod;
5044 Mnemonic = splitMnemonic(Mnemonic, PredicationCode, CarrySetting,
5045 ProcessorIMod, ITMask);
5047 // In Thumb1, only the branch (B) instruction can be predicated.
5048 if (isThumbOne() && PredicationCode != ARMCC::AL && Mnemonic != "b") {
5049 Parser.eatToEndOfStatement();
5050 return Error(NameLoc, "conditional execution not supported in Thumb1");
5053 Operands.push_back(ARMOperand::CreateToken(Mnemonic, NameLoc));
5055 // Handle the IT instruction ITMask. Convert it to a bitmask. This
5056 // is the mask as it will be for the IT encoding if the conditional
5057 // encoding has a '1' as it's bit0 (i.e. 't' ==> '1'). In the case
5058 // where the conditional bit0 is zero, the instruction post-processing
5059 // will adjust the mask accordingly.
5060 if (Mnemonic == "it") {
5061 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + 2);
5062 if (ITMask.size() > 3) {
5063 Parser.eatToEndOfStatement();
5064 return Error(Loc, "too many conditions on IT instruction");
5067 for (unsigned i = ITMask.size(); i != 0; --i) {
5068 char pos = ITMask[i - 1];
5069 if (pos != 't' && pos != 'e') {
5070 Parser.eatToEndOfStatement();
5071 return Error(Loc, "illegal IT block condition mask '" + ITMask + "'");
5074 if (ITMask[i - 1] == 't')
5077 Operands.push_back(ARMOperand::CreateITMask(Mask, Loc));
5080 // FIXME: This is all a pretty gross hack. We should automatically handle
5081 // optional operands like this via tblgen.
5083 // Next, add the CCOut and ConditionCode operands, if needed.
5085 // For mnemonics which can ever incorporate a carry setting bit or predication
5086 // code, our matching model involves us always generating CCOut and
5087 // ConditionCode operands to match the mnemonic "as written" and then we let
5088 // the matcher deal with finding the right instruction or generating an
5089 // appropriate error.
5090 bool CanAcceptCarrySet, CanAcceptPredicationCode;
5091 getMnemonicAcceptInfo(Mnemonic, Name, CanAcceptCarrySet, CanAcceptPredicationCode);
5093 // If we had a carry-set on an instruction that can't do that, issue an
5095 if (!CanAcceptCarrySet && CarrySetting) {
5096 Parser.eatToEndOfStatement();
5097 return Error(NameLoc, "instruction '" + Mnemonic +
5098 "' can not set flags, but 's' suffix specified");
5100 // If we had a predication code on an instruction that can't do that, issue an
5102 if (!CanAcceptPredicationCode && PredicationCode != ARMCC::AL) {
5103 Parser.eatToEndOfStatement();
5104 return Error(NameLoc, "instruction '" + Mnemonic +
5105 "' is not predicable, but condition code specified");
5108 // Add the carry setting operand, if necessary.
5109 if (CanAcceptCarrySet) {
5110 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size());
5111 Operands.push_back(ARMOperand::CreateCCOut(CarrySetting ? ARM::CPSR : 0,
5115 // Add the predication code operand, if necessary.
5116 if (CanAcceptPredicationCode) {
5117 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size() +
5119 Operands.push_back(ARMOperand::CreateCondCode(
5120 ARMCC::CondCodes(PredicationCode), Loc));
5123 // Add the processor imod operand, if necessary.
5124 if (ProcessorIMod) {
5125 Operands.push_back(ARMOperand::CreateImm(
5126 MCConstantExpr::Create(ProcessorIMod, getContext()),
5130 // Add the remaining tokens in the mnemonic.
5131 while (Next != StringRef::npos) {
5133 Next = Name.find('.', Start + 1);
5134 StringRef ExtraToken = Name.slice(Start, Next);
5136 // Some NEON instructions have an optional datatype suffix that is
5137 // completely ignored. Check for that.
5138 if (isDataTypeToken(ExtraToken) &&
5139 doesIgnoreDataTypeSuffix(Mnemonic, ExtraToken))
5142 // For for ARM mode generate an error if the .n qualifier is used.
5143 if (ExtraToken == ".n" && !isThumb()) {
5144 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Start);
5145 return Error(Loc, "instruction with .n (narrow) qualifier not allowed in "
5149 // The .n qualifier is always discarded as that is what the tables
5150 // and matcher expect. In ARM mode the .w qualifier has no effect,
5151 // so discard it to avoid errors that can be caused by the matcher.
5152 if (ExtraToken != ".n" && (isThumb() || ExtraToken != ".w")) {
5153 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Start);
5154 Operands.push_back(ARMOperand::CreateToken(ExtraToken, Loc));
5158 // Read the remaining operands.
5159 if (getLexer().isNot(AsmToken::EndOfStatement)) {
5160 // Read the first operand.
5161 if (parseOperand(Operands, Mnemonic)) {
5162 Parser.eatToEndOfStatement();
5166 while (getLexer().is(AsmToken::Comma)) {
5167 Parser.Lex(); // Eat the comma.
5169 // Parse and remember the operand.
5170 if (parseOperand(Operands, Mnemonic)) {
5171 Parser.eatToEndOfStatement();
5177 if (getLexer().isNot(AsmToken::EndOfStatement)) {
5178 SMLoc Loc = getLexer().getLoc();
5179 Parser.eatToEndOfStatement();
5180 return Error(Loc, "unexpected token in argument list");
5183 Parser.Lex(); // Consume the EndOfStatement
5185 // Some instructions, mostly Thumb, have forms for the same mnemonic that
5186 // do and don't have a cc_out optional-def operand. With some spot-checks
5187 // of the operand list, we can figure out which variant we're trying to
5188 // parse and adjust accordingly before actually matching. We shouldn't ever
5189 // try to remove a cc_out operand that was explicitly set on the the
5190 // mnemonic, of course (CarrySetting == true). Reason number #317 the
5191 // table driven matcher doesn't fit well with the ARM instruction set.
5192 if (!CarrySetting && shouldOmitCCOutOperand(Mnemonic, Operands)) {
5193 ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]);
5194 Operands.erase(Operands.begin() + 1);
5198 // Some instructions have the same mnemonic, but don't always
5199 // have a predicate. Distinguish them here and delete the
5200 // predicate if needed.
5201 if (shouldOmitPredicateOperand(Mnemonic, Operands)) {
5202 ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]);
5203 Operands.erase(Operands.begin() + 1);
5207 // ARM mode 'blx' need special handling, as the register operand version
5208 // is predicable, but the label operand version is not. So, we can't rely
5209 // on the Mnemonic based checking to correctly figure out when to put
5210 // a k_CondCode operand in the list. If we're trying to match the label
5211 // version, remove the k_CondCode operand here.
5212 if (!isThumb() && Mnemonic == "blx" && Operands.size() == 3 &&
5213 static_cast<ARMOperand*>(Operands[2])->isImm()) {
5214 ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]);
5215 Operands.erase(Operands.begin() + 1);
5219 // Adjust operands of ldrexd/strexd to MCK_GPRPair.
5220 // ldrexd/strexd require even/odd GPR pair. To enforce this constraint,
5221 // a single GPRPair reg operand is used in the .td file to replace the two
5222 // GPRs. However, when parsing from asm, the two GRPs cannot be automatically
5223 // expressed as a GPRPair, so we have to manually merge them.
5224 // FIXME: We would really like to be able to tablegen'erate this.
5225 if (!isThumb() && Operands.size() > 4 &&
5226 (Mnemonic == "ldrexd" || Mnemonic == "strexd" || Mnemonic == "ldaexd" ||
5227 Mnemonic == "stlexd")) {
5228 bool isLoad = (Mnemonic == "ldrexd" || Mnemonic == "ldaexd");
5229 unsigned Idx = isLoad ? 2 : 3;
5230 ARMOperand* Op1 = static_cast<ARMOperand*>(Operands[Idx]);
5231 ARMOperand* Op2 = static_cast<ARMOperand*>(Operands[Idx+1]);
5233 const MCRegisterClass& MRC = MRI->getRegClass(ARM::GPRRegClassID);
5234 // Adjust only if Op1 and Op2 are GPRs.
5235 if (Op1->isReg() && Op2->isReg() && MRC.contains(Op1->getReg()) &&
5236 MRC.contains(Op2->getReg())) {
5237 unsigned Reg1 = Op1->getReg();
5238 unsigned Reg2 = Op2->getReg();
5239 unsigned Rt = MRI->getEncodingValue(Reg1);
5240 unsigned Rt2 = MRI->getEncodingValue(Reg2);
5242 // Rt2 must be Rt + 1 and Rt must be even.
5243 if (Rt + 1 != Rt2 || (Rt & 1)) {
5244 Error(Op2->getStartLoc(), isLoad ?
5245 "destination operands must be sequential" :
5246 "source operands must be sequential");
5249 unsigned NewReg = MRI->getMatchingSuperReg(Reg1, ARM::gsub_0,
5250 &(MRI->getRegClass(ARM::GPRPairRegClassID)));
5251 Operands.erase(Operands.begin() + Idx, Operands.begin() + Idx + 2);
5252 Operands.insert(Operands.begin() + Idx, ARMOperand::CreateReg(
5253 NewReg, Op1->getStartLoc(), Op2->getEndLoc()));
5259 // FIXME: As said above, this is all a pretty gross hack. This instruction
5260 // does not fit with other "subs" and tblgen.
5261 // Adjust operands of B9.3.19 SUBS PC, LR, #imm (Thumb2) system instruction
5262 // so the Mnemonic is the original name "subs" and delete the predicate
5263 // operand so it will match the table entry.
5264 if (isThumbTwo() && Mnemonic == "sub" && Operands.size() == 6 &&
5265 static_cast<ARMOperand*>(Operands[3])->isReg() &&
5266 static_cast<ARMOperand*>(Operands[3])->getReg() == ARM::PC &&
5267 static_cast<ARMOperand*>(Operands[4])->isReg() &&
5268 static_cast<ARMOperand*>(Operands[4])->getReg() == ARM::LR &&
5269 static_cast<ARMOperand*>(Operands[5])->isImm()) {
5270 ARMOperand *Op0 = static_cast<ARMOperand*>(Operands[0]);
5271 Operands.erase(Operands.begin());
5273 Operands.insert(Operands.begin(), ARMOperand::CreateToken(Name, NameLoc));
5275 ARMOperand *Op1 = static_cast<ARMOperand*>(Operands[1]);
5276 Operands.erase(Operands.begin() + 1);
5282 // Validate context-sensitive operand constraints.
5284 // return 'true' if register list contains non-low GPR registers,
5285 // 'false' otherwise. If Reg is in the register list or is HiReg, set
5286 // 'containsReg' to true.
5287 static bool checkLowRegisterList(MCInst Inst, unsigned OpNo, unsigned Reg,
5288 unsigned HiReg, bool &containsReg) {
5289 containsReg = false;
5290 for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) {
5291 unsigned OpReg = Inst.getOperand(i).getReg();
5294 // Anything other than a low register isn't legal here.
5295 if (!isARMLowRegister(OpReg) && (!HiReg || OpReg != HiReg))
5301 // Check if the specified regisgter is in the register list of the inst,
5302 // starting at the indicated operand number.
5303 static bool listContainsReg(MCInst &Inst, unsigned OpNo, unsigned Reg) {
5304 for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) {
5305 unsigned OpReg = Inst.getOperand(i).getReg();
5312 // Return true if instruction has the interesting property of being
5313 // allowed in IT blocks, but not being predicable.
5314 static bool instIsBreakpoint(const MCInst &Inst) {
5315 return Inst.getOpcode() == ARM::tBKPT ||
5316 Inst.getOpcode() == ARM::BKPT ||
5317 Inst.getOpcode() == ARM::tHLT ||
5318 Inst.getOpcode() == ARM::HLT;
5322 // FIXME: We would really like to be able to tablegen'erate this.
5324 validateInstruction(MCInst &Inst,
5325 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
5326 const MCInstrDesc &MCID = MII.get(Inst.getOpcode());
5327 SMLoc Loc = Operands[0]->getStartLoc();
5329 // Check the IT block state first.
5330 // NOTE: BKPT and HLT instructions have the interesting property of being
5331 // allowed in IT blocks, but not being predicable. They just always execute.
5332 if (inITBlock() && !instIsBreakpoint(Inst)) {
5334 if (ITState.FirstCond)
5335 ITState.FirstCond = false;
5337 Bit = (ITState.Mask >> (5 - ITState.CurPosition)) & 1;
5338 // The instruction must be predicable.
5339 if (!MCID.isPredicable())
5340 return Error(Loc, "instructions in IT block must be predicable");
5341 unsigned Cond = Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm();
5342 unsigned ITCond = Bit ? ITState.Cond :
5343 ARMCC::getOppositeCondition(ITState.Cond);
5344 if (Cond != ITCond) {
5345 // Find the condition code Operand to get its SMLoc information.
5347 for (unsigned I = 1; I < Operands.size(); ++I)
5348 if (static_cast<ARMOperand*>(Operands[I])->isCondCode())
5349 CondLoc = Operands[I]->getStartLoc();
5350 return Error(CondLoc, "incorrect condition in IT block; got '" +
5351 StringRef(ARMCondCodeToString(ARMCC::CondCodes(Cond))) +
5352 "', but expected '" +
5353 ARMCondCodeToString(ARMCC::CondCodes(ITCond)) + "'");
5355 // Check for non-'al' condition codes outside of the IT block.
5356 } else if (isThumbTwo() && MCID.isPredicable() &&
5357 Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm() !=
5358 ARMCC::AL && Inst.getOpcode() != ARM::tBcc &&
5359 Inst.getOpcode() != ARM::t2Bcc)
5360 return Error(Loc, "predicated instructions must be in IT block");
5362 const unsigned Opcode = Inst.getOpcode();
5366 case ARM::LDRD_POST: {
5367 const unsigned RtReg = Inst.getOperand(0).getReg();
5370 if (RtReg == ARM::LR)
5371 return Error(Operands[3]->getStartLoc(),
5374 const unsigned Rt = MRI->getEncodingValue(RtReg);
5375 // Rt must be even-numbered.
5377 return Error(Operands[3]->getStartLoc(),
5378 "Rt must be even-numbered");
5380 // Rt2 must be Rt + 1.
5381 const unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg());
5383 return Error(Operands[3]->getStartLoc(),
5384 "destination operands must be sequential");
5386 if (Opcode == ARM::LDRD_PRE || Opcode == ARM::LDRD_POST) {
5387 const unsigned Rn = MRI->getEncodingValue(Inst.getOperand(3).getReg());
5388 // For addressing modes with writeback, the base register needs to be
5389 // different from the destination registers.
5390 if (Rn == Rt || Rn == Rt2)
5391 return Error(Operands[3]->getStartLoc(),
5392 "base register needs to be different from destination "
5399 case ARM::t2LDRD_PRE:
5400 case ARM::t2LDRD_POST: {
5401 // Rt2 must be different from Rt.
5402 unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg());
5403 unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg());
5405 return Error(Operands[3]->getStartLoc(),
5406 "destination operands can't be identical");
5410 // Rt2 must be Rt + 1.
5411 unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg());
5412 unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg());
5414 return Error(Operands[3]->getStartLoc(),
5415 "source operands must be sequential");
5419 case ARM::STRD_POST: {
5420 // Rt2 must be Rt + 1.
5421 unsigned Rt = MRI->getEncodingValue(Inst.getOperand(1).getReg());
5422 unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(2).getReg());
5424 return Error(Operands[3]->getStartLoc(),
5425 "source operands must be sequential");
5430 // Width must be in range [1, 32-lsb].
5431 unsigned LSB = Inst.getOperand(2).getImm();
5432 unsigned Widthm1 = Inst.getOperand(3).getImm();
5433 if (Widthm1 >= 32 - LSB)
5434 return Error(Operands[5]->getStartLoc(),
5435 "bitfield width must be in range [1,32-lsb]");
5438 // Notionally handles ARM::tLDMIA_UPD too.
5440 // If we're parsing Thumb2, the .w variant is available and handles
5441 // most cases that are normally illegal for a Thumb1 LDM instruction.
5442 // We'll make the transformation in processInstruction() if necessary.
5444 // Thumb LDM instructions are writeback iff the base register is not
5445 // in the register list.
5446 unsigned Rn = Inst.getOperand(0).getReg();
5447 bool HasWritebackToken =
5448 (static_cast<ARMOperand*>(Operands[3])->isToken() &&
5449 static_cast<ARMOperand*>(Operands[3])->getToken() == "!");
5450 bool ListContainsBase;
5451 if (checkLowRegisterList(Inst, 3, Rn, 0, ListContainsBase) && !isThumbTwo())
5452 return Error(Operands[3 + HasWritebackToken]->getStartLoc(),
5453 "registers must be in range r0-r7");
5454 // If we should have writeback, then there should be a '!' token.
5455 if (!ListContainsBase && !HasWritebackToken && !isThumbTwo())
5456 return Error(Operands[2]->getStartLoc(),
5457 "writeback operator '!' expected");
5458 // If we should not have writeback, there must not be a '!'. This is
5459 // true even for the 32-bit wide encodings.
5460 if (ListContainsBase && HasWritebackToken)
5461 return Error(Operands[3]->getStartLoc(),
5462 "writeback operator '!' not allowed when base register "
5463 "in register list");
5467 case ARM::LDMIA_UPD:
5468 case ARM::LDMDB_UPD:
5469 case ARM::LDMIB_UPD:
5470 case ARM::LDMDA_UPD:
5471 // ARM variants loading and updating the same register are only officially
5472 // UNPREDICTABLE on v7 upwards. Goodness knows what they did before.
5476 case ARM::t2LDMIA_UPD:
5477 case ARM::t2LDMDB_UPD:
5478 case ARM::t2STMIA_UPD:
5479 case ARM::t2STMDB_UPD: {
5480 if (listContainsReg(Inst, 3, Inst.getOperand(0).getReg()))
5481 return Error(Operands.back()->getStartLoc(),
5482 "writeback register not allowed in register list");
5485 case ARM::sysLDMIA_UPD:
5486 case ARM::sysLDMDA_UPD:
5487 case ARM::sysLDMDB_UPD:
5488 case ARM::sysLDMIB_UPD:
5489 if (!listContainsReg(Inst, 3, ARM::PC))
5490 return Error(Operands[4]->getStartLoc(),
5491 "writeback register only allowed on system LDM "
5492 "if PC in register-list");
5494 case ARM::sysSTMIA_UPD:
5495 case ARM::sysSTMDA_UPD:
5496 case ARM::sysSTMDB_UPD:
5497 case ARM::sysSTMIB_UPD:
5498 return Error(Operands[2]->getStartLoc(),
5499 "system STM cannot have writeback register");
5502 // The second source operand must be the same register as the destination
5505 // In this case, we must directly check the parsed operands because the
5506 // cvtThumbMultiply() function is written in such a way that it guarantees
5507 // this first statement is always true for the new Inst. Essentially, the
5508 // destination is unconditionally copied into the second source operand
5509 // without checking to see if it matches what we actually parsed.
5510 if (Operands.size() == 6 &&
5511 (((ARMOperand*)Operands[3])->getReg() !=
5512 ((ARMOperand*)Operands[5])->getReg()) &&
5513 (((ARMOperand*)Operands[3])->getReg() !=
5514 ((ARMOperand*)Operands[4])->getReg())) {
5515 return Error(Operands[3]->getStartLoc(),
5516 "destination register must match source register");
5520 // Like for ldm/stm, push and pop have hi-reg handling version in Thumb2,
5521 // so only issue a diagnostic for thumb1. The instructions will be
5522 // switched to the t2 encodings in processInstruction() if necessary.
5524 bool ListContainsBase;
5525 if (checkLowRegisterList(Inst, 2, 0, ARM::PC, ListContainsBase) &&
5527 return Error(Operands[2]->getStartLoc(),
5528 "registers must be in range r0-r7 or pc");
5532 bool ListContainsBase;
5533 if (checkLowRegisterList(Inst, 2, 0, ARM::LR, ListContainsBase) &&
5535 return Error(Operands[2]->getStartLoc(),
5536 "registers must be in range r0-r7 or lr");
5539 case ARM::tSTMIA_UPD: {
5540 bool ListContainsBase, InvalidLowList;
5541 InvalidLowList = checkLowRegisterList(Inst, 4, Inst.getOperand(0).getReg(),
5542 0, ListContainsBase);
5543 if (InvalidLowList && !isThumbTwo())
5544 return Error(Operands[4]->getStartLoc(),
5545 "registers must be in range r0-r7");
5547 // This would be converted to a 32-bit stm, but that's not valid if the
5548 // writeback register is in the list.
5549 if (InvalidLowList && ListContainsBase)
5550 return Error(Operands[4]->getStartLoc(),
5551 "writeback operator '!' not allowed when base register "
5552 "in register list");
5555 case ARM::tADDrSP: {
5556 // If the non-SP source operand and the destination operand are not the
5557 // same, we need thumb2 (for the wide encoding), or we have an error.
5558 if (!isThumbTwo() &&
5559 Inst.getOperand(0).getReg() != Inst.getOperand(2).getReg()) {
5560 return Error(Operands[4]->getStartLoc(),
5561 "source register must be the same as destination");
5565 // Final range checking for Thumb unconditional branch instructions.
5567 if (!(static_cast<ARMOperand*>(Operands[2]))->isSignedOffset<11, 1>())
5568 return Error(Operands[2]->getStartLoc(), "branch target out of range");
5571 int op = (Operands[2]->isImm()) ? 2 : 3;
5572 if (!(static_cast<ARMOperand*>(Operands[op]))->isSignedOffset<24, 1>())
5573 return Error(Operands[op]->getStartLoc(), "branch target out of range");
5576 // Final range checking for Thumb conditional branch instructions.
5578 if (!(static_cast<ARMOperand*>(Operands[2]))->isSignedOffset<8, 1>())
5579 return Error(Operands[2]->getStartLoc(), "branch target out of range");
5582 int Op = (Operands[2]->isImm()) ? 2 : 3;
5583 if (!(static_cast<ARMOperand*>(Operands[Op]))->isSignedOffset<20, 1>())
5584 return Error(Operands[Op]->getStartLoc(), "branch target out of range");
5592 static unsigned getRealVSTOpcode(unsigned Opc, unsigned &Spacing) {
5594 default: llvm_unreachable("unexpected opcode!");
5596 case ARM::VST1LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST1LNd8_UPD;
5597 case ARM::VST1LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST1LNd16_UPD;
5598 case ARM::VST1LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST1LNd32_UPD;
5599 case ARM::VST1LNdWB_register_Asm_8: Spacing = 1; return ARM::VST1LNd8_UPD;
5600 case ARM::VST1LNdWB_register_Asm_16: Spacing = 1; return ARM::VST1LNd16_UPD;
5601 case ARM::VST1LNdWB_register_Asm_32: Spacing = 1; return ARM::VST1LNd32_UPD;
5602 case ARM::VST1LNdAsm_8: Spacing = 1; return ARM::VST1LNd8;
5603 case ARM::VST1LNdAsm_16: Spacing = 1; return ARM::VST1LNd16;
5604 case ARM::VST1LNdAsm_32: Spacing = 1; return ARM::VST1LNd32;
5607 case ARM::VST2LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST2LNd8_UPD;
5608 case ARM::VST2LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST2LNd16_UPD;
5609 case ARM::VST2LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST2LNd32_UPD;
5610 case ARM::VST2LNqWB_fixed_Asm_16: Spacing = 2; return ARM::VST2LNq16_UPD;
5611 case ARM::VST2LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST2LNq32_UPD;
5613 case ARM::VST2LNdWB_register_Asm_8: Spacing = 1; return ARM::VST2LNd8_UPD;
5614 case ARM::VST2LNdWB_register_Asm_16: Spacing = 1; return ARM::VST2LNd16_UPD;
5615 case ARM::VST2LNdWB_register_Asm_32: Spacing = 1; return ARM::VST2LNd32_UPD;
5616 case ARM::VST2LNqWB_register_Asm_16: Spacing = 2; return ARM::VST2LNq16_UPD;
5617 case ARM::VST2LNqWB_register_Asm_32: Spacing = 2; return ARM::VST2LNq32_UPD;
5619 case ARM::VST2LNdAsm_8: Spacing = 1; return ARM::VST2LNd8;
5620 case ARM::VST2LNdAsm_16: Spacing = 1; return ARM::VST2LNd16;
5621 case ARM::VST2LNdAsm_32: Spacing = 1; return ARM::VST2LNd32;
5622 case ARM::VST2LNqAsm_16: Spacing = 2; return ARM::VST2LNq16;
5623 case ARM::VST2LNqAsm_32: Spacing = 2; return ARM::VST2LNq32;
5626 case ARM::VST3LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST3LNd8_UPD;
5627 case ARM::VST3LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST3LNd16_UPD;
5628 case ARM::VST3LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST3LNd32_UPD;
5629 case ARM::VST3LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VST3LNq16_UPD;
5630 case ARM::VST3LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST3LNq32_UPD;
5631 case ARM::VST3LNdWB_register_Asm_8: Spacing = 1; return ARM::VST3LNd8_UPD;
5632 case ARM::VST3LNdWB_register_Asm_16: Spacing = 1; return ARM::VST3LNd16_UPD;
5633 case ARM::VST3LNdWB_register_Asm_32: Spacing = 1; return ARM::VST3LNd32_UPD;
5634 case ARM::VST3LNqWB_register_Asm_16: Spacing = 2; return ARM::VST3LNq16_UPD;
5635 case ARM::VST3LNqWB_register_Asm_32: Spacing = 2; return ARM::VST3LNq32_UPD;
5636 case ARM::VST3LNdAsm_8: Spacing = 1; return ARM::VST3LNd8;
5637 case ARM::VST3LNdAsm_16: Spacing = 1; return ARM::VST3LNd16;
5638 case ARM::VST3LNdAsm_32: Spacing = 1; return ARM::VST3LNd32;
5639 case ARM::VST3LNqAsm_16: Spacing = 2; return ARM::VST3LNq16;
5640 case ARM::VST3LNqAsm_32: Spacing = 2; return ARM::VST3LNq32;
5643 case ARM::VST3dWB_fixed_Asm_8: Spacing = 1; return ARM::VST3d8_UPD;
5644 case ARM::VST3dWB_fixed_Asm_16: Spacing = 1; return ARM::VST3d16_UPD;
5645 case ARM::VST3dWB_fixed_Asm_32: Spacing = 1; return ARM::VST3d32_UPD;
5646 case ARM::VST3qWB_fixed_Asm_8: Spacing = 2; return ARM::VST3q8_UPD;
5647 case ARM::VST3qWB_fixed_Asm_16: Spacing = 2; return ARM::VST3q16_UPD;
5648 case ARM::VST3qWB_fixed_Asm_32: Spacing = 2; return ARM::VST3q32_UPD;
5649 case ARM::VST3dWB_register_Asm_8: Spacing = 1; return ARM::VST3d8_UPD;
5650 case ARM::VST3dWB_register_Asm_16: Spacing = 1; return ARM::VST3d16_UPD;
5651 case ARM::VST3dWB_register_Asm_32: Spacing = 1; return ARM::VST3d32_UPD;
5652 case ARM::VST3qWB_register_Asm_8: Spacing = 2; return ARM::VST3q8_UPD;
5653 case ARM::VST3qWB_register_Asm_16: Spacing = 2; return ARM::VST3q16_UPD;
5654 case ARM::VST3qWB_register_Asm_32: Spacing = 2; return ARM::VST3q32_UPD;
5655 case ARM::VST3dAsm_8: Spacing = 1; return ARM::VST3d8;
5656 case ARM::VST3dAsm_16: Spacing = 1; return ARM::VST3d16;
5657 case ARM::VST3dAsm_32: Spacing = 1; return ARM::VST3d32;
5658 case ARM::VST3qAsm_8: Spacing = 2; return ARM::VST3q8;
5659 case ARM::VST3qAsm_16: Spacing = 2; return ARM::VST3q16;
5660 case ARM::VST3qAsm_32: Spacing = 2; return ARM::VST3q32;
5663 case ARM::VST4LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST4LNd8_UPD;
5664 case ARM::VST4LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST4LNd16_UPD;
5665 case ARM::VST4LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST4LNd32_UPD;
5666 case ARM::VST4LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VST4LNq16_UPD;
5667 case ARM::VST4LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST4LNq32_UPD;
5668 case ARM::VST4LNdWB_register_Asm_8: Spacing = 1; return ARM::VST4LNd8_UPD;
5669 case ARM::VST4LNdWB_register_Asm_16: Spacing = 1; return ARM::VST4LNd16_UPD;
5670 case ARM::VST4LNdWB_register_Asm_32: Spacing = 1; return ARM::VST4LNd32_UPD;
5671 case ARM::VST4LNqWB_register_Asm_16: Spacing = 2; return ARM::VST4LNq16_UPD;
5672 case ARM::VST4LNqWB_register_Asm_32: Spacing = 2; return ARM::VST4LNq32_UPD;
5673 case ARM::VST4LNdAsm_8: Spacing = 1; return ARM::VST4LNd8;
5674 case ARM::VST4LNdAsm_16: Spacing = 1; return ARM::VST4LNd16;
5675 case ARM::VST4LNdAsm_32: Spacing = 1; return ARM::VST4LNd32;
5676 case ARM::VST4LNqAsm_16: Spacing = 2; return ARM::VST4LNq16;
5677 case ARM::VST4LNqAsm_32: Spacing = 2; return ARM::VST4LNq32;
5680 case ARM::VST4dWB_fixed_Asm_8: Spacing = 1; return ARM::VST4d8_UPD;
5681 case ARM::VST4dWB_fixed_Asm_16: Spacing = 1; return ARM::VST4d16_UPD;
5682 case ARM::VST4dWB_fixed_Asm_32: Spacing = 1; return ARM::VST4d32_UPD;
5683 case ARM::VST4qWB_fixed_Asm_8: Spacing = 2; return ARM::VST4q8_UPD;
5684 case ARM::VST4qWB_fixed_Asm_16: Spacing = 2; return ARM::VST4q16_UPD;
5685 case ARM::VST4qWB_fixed_Asm_32: Spacing = 2; return ARM::VST4q32_UPD;
5686 case ARM::VST4dWB_register_Asm_8: Spacing = 1; return ARM::VST4d8_UPD;
5687 case ARM::VST4dWB_register_Asm_16: Spacing = 1; return ARM::VST4d16_UPD;
5688 case ARM::VST4dWB_register_Asm_32: Spacing = 1; return ARM::VST4d32_UPD;
5689 case ARM::VST4qWB_register_Asm_8: Spacing = 2; return ARM::VST4q8_UPD;
5690 case ARM::VST4qWB_register_Asm_16: Spacing = 2; return ARM::VST4q16_UPD;
5691 case ARM::VST4qWB_register_Asm_32: Spacing = 2; return ARM::VST4q32_UPD;
5692 case ARM::VST4dAsm_8: Spacing = 1; return ARM::VST4d8;
5693 case ARM::VST4dAsm_16: Spacing = 1; return ARM::VST4d16;
5694 case ARM::VST4dAsm_32: Spacing = 1; return ARM::VST4d32;
5695 case ARM::VST4qAsm_8: Spacing = 2; return ARM::VST4q8;
5696 case ARM::VST4qAsm_16: Spacing = 2; return ARM::VST4q16;
5697 case ARM::VST4qAsm_32: Spacing = 2; return ARM::VST4q32;
5701 static unsigned getRealVLDOpcode(unsigned Opc, unsigned &Spacing) {
5703 default: llvm_unreachable("unexpected opcode!");
5705 case ARM::VLD1LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD1LNd8_UPD;
5706 case ARM::VLD1LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD1LNd16_UPD;
5707 case ARM::VLD1LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD1LNd32_UPD;
5708 case ARM::VLD1LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD1LNd8_UPD;
5709 case ARM::VLD1LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD1LNd16_UPD;
5710 case ARM::VLD1LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD1LNd32_UPD;
5711 case ARM::VLD1LNdAsm_8: Spacing = 1; return ARM::VLD1LNd8;
5712 case ARM::VLD1LNdAsm_16: Spacing = 1; return ARM::VLD1LNd16;
5713 case ARM::VLD1LNdAsm_32: Spacing = 1; return ARM::VLD1LNd32;
5716 case ARM::VLD2LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD2LNd8_UPD;
5717 case ARM::VLD2LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD2LNd16_UPD;
5718 case ARM::VLD2LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD2LNd32_UPD;
5719 case ARM::VLD2LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD2LNq16_UPD;
5720 case ARM::VLD2LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD2LNq32_UPD;
5721 case ARM::VLD2LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD2LNd8_UPD;
5722 case ARM::VLD2LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD2LNd16_UPD;
5723 case ARM::VLD2LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD2LNd32_UPD;
5724 case ARM::VLD2LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD2LNq16_UPD;
5725 case ARM::VLD2LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD2LNq32_UPD;
5726 case ARM::VLD2LNdAsm_8: Spacing = 1; return ARM::VLD2LNd8;
5727 case ARM::VLD2LNdAsm_16: Spacing = 1; return ARM::VLD2LNd16;
5728 case ARM::VLD2LNdAsm_32: Spacing = 1; return ARM::VLD2LNd32;
5729 case ARM::VLD2LNqAsm_16: Spacing = 2; return ARM::VLD2LNq16;
5730 case ARM::VLD2LNqAsm_32: Spacing = 2; return ARM::VLD2LNq32;
5733 case ARM::VLD3DUPdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3DUPd8_UPD;
5734 case ARM::VLD3DUPdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3DUPd16_UPD;
5735 case ARM::VLD3DUPdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3DUPd32_UPD;
5736 case ARM::VLD3DUPqWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3DUPq8_UPD;
5737 case ARM::VLD3DUPqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3DUPq16_UPD;
5738 case ARM::VLD3DUPqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3DUPq32_UPD;
5739 case ARM::VLD3DUPdWB_register_Asm_8: Spacing = 1; return ARM::VLD3DUPd8_UPD;
5740 case ARM::VLD3DUPdWB_register_Asm_16: Spacing = 1; return ARM::VLD3DUPd16_UPD;
5741 case ARM::VLD3DUPdWB_register_Asm_32: Spacing = 1; return ARM::VLD3DUPd32_UPD;
5742 case ARM::VLD3DUPqWB_register_Asm_8: Spacing = 2; return ARM::VLD3DUPq8_UPD;
5743 case ARM::VLD3DUPqWB_register_Asm_16: Spacing = 2; return ARM::VLD3DUPq16_UPD;
5744 case ARM::VLD3DUPqWB_register_Asm_32: Spacing = 2; return ARM::VLD3DUPq32_UPD;
5745 case ARM::VLD3DUPdAsm_8: Spacing = 1; return ARM::VLD3DUPd8;
5746 case ARM::VLD3DUPdAsm_16: Spacing = 1; return ARM::VLD3DUPd16;
5747 case ARM::VLD3DUPdAsm_32: Spacing = 1; return ARM::VLD3DUPd32;
5748 case ARM::VLD3DUPqAsm_8: Spacing = 2; return ARM::VLD3DUPq8;
5749 case ARM::VLD3DUPqAsm_16: Spacing = 2; return ARM::VLD3DUPq16;
5750 case ARM::VLD3DUPqAsm_32: Spacing = 2; return ARM::VLD3DUPq32;
5753 case ARM::VLD3LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3LNd8_UPD;
5754 case ARM::VLD3LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3LNd16_UPD;
5755 case ARM::VLD3LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3LNd32_UPD;
5756 case ARM::VLD3LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3LNq16_UPD;
5757 case ARM::VLD3LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3LNq32_UPD;
5758 case ARM::VLD3LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD3LNd8_UPD;
5759 case ARM::VLD3LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD3LNd16_UPD;
5760 case ARM::VLD3LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD3LNd32_UPD;
5761 case ARM::VLD3LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD3LNq16_UPD;
5762 case ARM::VLD3LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD3LNq32_UPD;
5763 case ARM::VLD3LNdAsm_8: Spacing = 1; return ARM::VLD3LNd8;
5764 case ARM::VLD3LNdAsm_16: Spacing = 1; return ARM::VLD3LNd16;
5765 case ARM::VLD3LNdAsm_32: Spacing = 1; return ARM::VLD3LNd32;
5766 case ARM::VLD3LNqAsm_16: Spacing = 2; return ARM::VLD3LNq16;
5767 case ARM::VLD3LNqAsm_32: Spacing = 2; return ARM::VLD3LNq32;
5770 case ARM::VLD3dWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3d8_UPD;
5771 case ARM::VLD3dWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3d16_UPD;
5772 case ARM::VLD3dWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3d32_UPD;
5773 case ARM::VLD3qWB_fixed_Asm_8: Spacing = 2; return ARM::VLD3q8_UPD;
5774 case ARM::VLD3qWB_fixed_Asm_16: Spacing = 2; return ARM::VLD3q16_UPD;
5775 case ARM::VLD3qWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3q32_UPD;
5776 case ARM::VLD3dWB_register_Asm_8: Spacing = 1; return ARM::VLD3d8_UPD;
5777 case ARM::VLD3dWB_register_Asm_16: Spacing = 1; return ARM::VLD3d16_UPD;
5778 case ARM::VLD3dWB_register_Asm_32: Spacing = 1; return ARM::VLD3d32_UPD;
5779 case ARM::VLD3qWB_register_Asm_8: Spacing = 2; return ARM::VLD3q8_UPD;
5780 case ARM::VLD3qWB_register_Asm_16: Spacing = 2; return ARM::VLD3q16_UPD;
5781 case ARM::VLD3qWB_register_Asm_32: Spacing = 2; return ARM::VLD3q32_UPD;
5782 case ARM::VLD3dAsm_8: Spacing = 1; return ARM::VLD3d8;
5783 case ARM::VLD3dAsm_16: Spacing = 1; return ARM::VLD3d16;
5784 case ARM::VLD3dAsm_32: Spacing = 1; return ARM::VLD3d32;
5785 case ARM::VLD3qAsm_8: Spacing = 2; return ARM::VLD3q8;
5786 case ARM::VLD3qAsm_16: Spacing = 2; return ARM::VLD3q16;
5787 case ARM::VLD3qAsm_32: Spacing = 2; return ARM::VLD3q32;
5790 case ARM::VLD4LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4LNd8_UPD;
5791 case ARM::VLD4LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4LNd16_UPD;
5792 case ARM::VLD4LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4LNd32_UPD;
5793 case ARM::VLD4LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4LNq16_UPD;
5794 case ARM::VLD4LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4LNq32_UPD;
5795 case ARM::VLD4LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD4LNd8_UPD;
5796 case ARM::VLD4LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD4LNd16_UPD;
5797 case ARM::VLD4LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD4LNd32_UPD;
5798 case ARM::VLD4LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD4LNq16_UPD;
5799 case ARM::VLD4LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD4LNq32_UPD;
5800 case ARM::VLD4LNdAsm_8: Spacing = 1; return ARM::VLD4LNd8;
5801 case ARM::VLD4LNdAsm_16: Spacing = 1; return ARM::VLD4LNd16;
5802 case ARM::VLD4LNdAsm_32: Spacing = 1; return ARM::VLD4LNd32;
5803 case ARM::VLD4LNqAsm_16: Spacing = 2; return ARM::VLD4LNq16;
5804 case ARM::VLD4LNqAsm_32: Spacing = 2; return ARM::VLD4LNq32;
5807 case ARM::VLD4DUPdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4DUPd8_UPD;
5808 case ARM::VLD4DUPdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4DUPd16_UPD;
5809 case ARM::VLD4DUPdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4DUPd32_UPD;
5810 case ARM::VLD4DUPqWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4DUPq8_UPD;
5811 case ARM::VLD4DUPqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4DUPq16_UPD;
5812 case ARM::VLD4DUPqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4DUPq32_UPD;
5813 case ARM::VLD4DUPdWB_register_Asm_8: Spacing = 1; return ARM::VLD4DUPd8_UPD;
5814 case ARM::VLD4DUPdWB_register_Asm_16: Spacing = 1; return ARM::VLD4DUPd16_UPD;
5815 case ARM::VLD4DUPdWB_register_Asm_32: Spacing = 1; return ARM::VLD4DUPd32_UPD;
5816 case ARM::VLD4DUPqWB_register_Asm_8: Spacing = 2; return ARM::VLD4DUPq8_UPD;
5817 case ARM::VLD4DUPqWB_register_Asm_16: Spacing = 2; return ARM::VLD4DUPq16_UPD;
5818 case ARM::VLD4DUPqWB_register_Asm_32: Spacing = 2; return ARM::VLD4DUPq32_UPD;
5819 case ARM::VLD4DUPdAsm_8: Spacing = 1; return ARM::VLD4DUPd8;
5820 case ARM::VLD4DUPdAsm_16: Spacing = 1; return ARM::VLD4DUPd16;
5821 case ARM::VLD4DUPdAsm_32: Spacing = 1; return ARM::VLD4DUPd32;
5822 case ARM::VLD4DUPqAsm_8: Spacing = 2; return ARM::VLD4DUPq8;
5823 case ARM::VLD4DUPqAsm_16: Spacing = 2; return ARM::VLD4DUPq16;
5824 case ARM::VLD4DUPqAsm_32: Spacing = 2; return ARM::VLD4DUPq32;
5827 case ARM::VLD4dWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4d8_UPD;
5828 case ARM::VLD4dWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4d16_UPD;
5829 case ARM::VLD4dWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4d32_UPD;
5830 case ARM::VLD4qWB_fixed_Asm_8: Spacing = 2; return ARM::VLD4q8_UPD;
5831 case ARM::VLD4qWB_fixed_Asm_16: Spacing = 2; return ARM::VLD4q16_UPD;
5832 case ARM::VLD4qWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4q32_UPD;
5833 case ARM::VLD4dWB_register_Asm_8: Spacing = 1; return ARM::VLD4d8_UPD;
5834 case ARM::VLD4dWB_register_Asm_16: Spacing = 1; return ARM::VLD4d16_UPD;
5835 case ARM::VLD4dWB_register_Asm_32: Spacing = 1; return ARM::VLD4d32_UPD;
5836 case ARM::VLD4qWB_register_Asm_8: Spacing = 2; return ARM::VLD4q8_UPD;
5837 case ARM::VLD4qWB_register_Asm_16: Spacing = 2; return ARM::VLD4q16_UPD;
5838 case ARM::VLD4qWB_register_Asm_32: Spacing = 2; return ARM::VLD4q32_UPD;
5839 case ARM::VLD4dAsm_8: Spacing = 1; return ARM::VLD4d8;
5840 case ARM::VLD4dAsm_16: Spacing = 1; return ARM::VLD4d16;
5841 case ARM::VLD4dAsm_32: Spacing = 1; return ARM::VLD4d32;
5842 case ARM::VLD4qAsm_8: Spacing = 2; return ARM::VLD4q8;
5843 case ARM::VLD4qAsm_16: Spacing = 2; return ARM::VLD4q16;
5844 case ARM::VLD4qAsm_32: Spacing = 2; return ARM::VLD4q32;
5849 processInstruction(MCInst &Inst,
5850 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
5851 switch (Inst.getOpcode()) {
5852 // Alias for alternate form of 'ADR Rd, #imm' instruction.
5854 if (Inst.getOperand(1).getReg() != ARM::PC ||
5855 Inst.getOperand(5).getReg() != 0)
5858 TmpInst.setOpcode(ARM::ADR);
5859 TmpInst.addOperand(Inst.getOperand(0));
5860 TmpInst.addOperand(Inst.getOperand(2));
5861 TmpInst.addOperand(Inst.getOperand(3));
5862 TmpInst.addOperand(Inst.getOperand(4));
5866 // Aliases for alternate PC+imm syntax of LDR instructions.
5867 case ARM::t2LDRpcrel:
5868 // Select the narrow version if the immediate will fit.
5869 if (Inst.getOperand(1).getImm() > 0 &&
5870 Inst.getOperand(1).getImm() <= 0xff &&
5871 !(static_cast<ARMOperand*>(Operands[2])->isToken() &&
5872 static_cast<ARMOperand*>(Operands[2])->getToken() == ".w"))
5873 Inst.setOpcode(ARM::tLDRpci);
5875 Inst.setOpcode(ARM::t2LDRpci);
5877 case ARM::t2LDRBpcrel:
5878 Inst.setOpcode(ARM::t2LDRBpci);
5880 case ARM::t2LDRHpcrel:
5881 Inst.setOpcode(ARM::t2LDRHpci);
5883 case ARM::t2LDRSBpcrel:
5884 Inst.setOpcode(ARM::t2LDRSBpci);
5886 case ARM::t2LDRSHpcrel:
5887 Inst.setOpcode(ARM::t2LDRSHpci);
5889 // Handle NEON VST complex aliases.
5890 case ARM::VST1LNdWB_register_Asm_8:
5891 case ARM::VST1LNdWB_register_Asm_16:
5892 case ARM::VST1LNdWB_register_Asm_32: {
5894 // Shuffle the operands around so the lane index operand is in the
5897 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5898 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5899 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5900 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5901 TmpInst.addOperand(Inst.getOperand(4)); // Rm
5902 TmpInst.addOperand(Inst.getOperand(0)); // Vd
5903 TmpInst.addOperand(Inst.getOperand(1)); // lane
5904 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
5905 TmpInst.addOperand(Inst.getOperand(6));
5910 case ARM::VST2LNdWB_register_Asm_8:
5911 case ARM::VST2LNdWB_register_Asm_16:
5912 case ARM::VST2LNdWB_register_Asm_32:
5913 case ARM::VST2LNqWB_register_Asm_16:
5914 case ARM::VST2LNqWB_register_Asm_32: {
5916 // Shuffle the operands around so the lane index operand is in the
5919 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5920 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5921 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5922 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5923 TmpInst.addOperand(Inst.getOperand(4)); // Rm
5924 TmpInst.addOperand(Inst.getOperand(0)); // Vd
5925 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5927 TmpInst.addOperand(Inst.getOperand(1)); // lane
5928 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
5929 TmpInst.addOperand(Inst.getOperand(6));
5934 case ARM::VST3LNdWB_register_Asm_8:
5935 case ARM::VST3LNdWB_register_Asm_16:
5936 case ARM::VST3LNdWB_register_Asm_32:
5937 case ARM::VST3LNqWB_register_Asm_16:
5938 case ARM::VST3LNqWB_register_Asm_32: {
5940 // Shuffle the operands around so the lane index operand is in the
5943 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5944 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5945 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5946 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5947 TmpInst.addOperand(Inst.getOperand(4)); // Rm
5948 TmpInst.addOperand(Inst.getOperand(0)); // Vd
5949 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5951 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5953 TmpInst.addOperand(Inst.getOperand(1)); // lane
5954 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
5955 TmpInst.addOperand(Inst.getOperand(6));
5960 case ARM::VST4LNdWB_register_Asm_8:
5961 case ARM::VST4LNdWB_register_Asm_16:
5962 case ARM::VST4LNdWB_register_Asm_32:
5963 case ARM::VST4LNqWB_register_Asm_16:
5964 case ARM::VST4LNqWB_register_Asm_32: {
5966 // Shuffle the operands around so the lane index operand is in the
5969 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5970 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5971 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5972 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5973 TmpInst.addOperand(Inst.getOperand(4)); // Rm
5974 TmpInst.addOperand(Inst.getOperand(0)); // Vd
5975 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5977 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5979 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5981 TmpInst.addOperand(Inst.getOperand(1)); // lane
5982 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
5983 TmpInst.addOperand(Inst.getOperand(6));
5988 case ARM::VST1LNdWB_fixed_Asm_8:
5989 case ARM::VST1LNdWB_fixed_Asm_16:
5990 case ARM::VST1LNdWB_fixed_Asm_32: {
5992 // Shuffle the operands around so the lane index operand is in the
5995 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5996 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5997 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5998 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5999 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6000 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6001 TmpInst.addOperand(Inst.getOperand(1)); // lane
6002 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6003 TmpInst.addOperand(Inst.getOperand(5));
6008 case ARM::VST2LNdWB_fixed_Asm_8:
6009 case ARM::VST2LNdWB_fixed_Asm_16:
6010 case ARM::VST2LNdWB_fixed_Asm_32:
6011 case ARM::VST2LNqWB_fixed_Asm_16:
6012 case ARM::VST2LNqWB_fixed_Asm_32: {
6014 // Shuffle the operands around so the lane index operand is in the
6017 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6018 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6019 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6020 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6021 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6022 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6023 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6025 TmpInst.addOperand(Inst.getOperand(1)); // lane
6026 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6027 TmpInst.addOperand(Inst.getOperand(5));
6032 case ARM::VST3LNdWB_fixed_Asm_8:
6033 case ARM::VST3LNdWB_fixed_Asm_16:
6034 case ARM::VST3LNdWB_fixed_Asm_32:
6035 case ARM::VST3LNqWB_fixed_Asm_16:
6036 case ARM::VST3LNqWB_fixed_Asm_32: {
6038 // Shuffle the operands around so the lane index operand is in the
6041 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6042 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6043 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6044 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6045 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6046 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6047 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6049 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6051 TmpInst.addOperand(Inst.getOperand(1)); // lane
6052 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6053 TmpInst.addOperand(Inst.getOperand(5));
6058 case ARM::VST4LNdWB_fixed_Asm_8:
6059 case ARM::VST4LNdWB_fixed_Asm_16:
6060 case ARM::VST4LNdWB_fixed_Asm_32:
6061 case ARM::VST4LNqWB_fixed_Asm_16:
6062 case ARM::VST4LNqWB_fixed_Asm_32: {
6064 // Shuffle the operands around so the lane index operand is in the
6067 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6068 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6069 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6070 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6071 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6072 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6073 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6075 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6077 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6079 TmpInst.addOperand(Inst.getOperand(1)); // lane
6080 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6081 TmpInst.addOperand(Inst.getOperand(5));
6086 case ARM::VST1LNdAsm_8:
6087 case ARM::VST1LNdAsm_16:
6088 case ARM::VST1LNdAsm_32: {
6090 // Shuffle the operands around so the lane index operand is in the
6093 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6094 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6095 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6096 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6097 TmpInst.addOperand(Inst.getOperand(1)); // lane
6098 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6099 TmpInst.addOperand(Inst.getOperand(5));
6104 case ARM::VST2LNdAsm_8:
6105 case ARM::VST2LNdAsm_16:
6106 case ARM::VST2LNdAsm_32:
6107 case ARM::VST2LNqAsm_16:
6108 case ARM::VST2LNqAsm_32: {
6110 // Shuffle the operands around so the lane index operand is in the
6113 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6114 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6115 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6116 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6117 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6119 TmpInst.addOperand(Inst.getOperand(1)); // lane
6120 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6121 TmpInst.addOperand(Inst.getOperand(5));
6126 case ARM::VST3LNdAsm_8:
6127 case ARM::VST3LNdAsm_16:
6128 case ARM::VST3LNdAsm_32:
6129 case ARM::VST3LNqAsm_16:
6130 case ARM::VST3LNqAsm_32: {
6132 // Shuffle the operands around so the lane index operand is in the
6135 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6136 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6137 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6138 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6139 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6141 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6143 TmpInst.addOperand(Inst.getOperand(1)); // lane
6144 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6145 TmpInst.addOperand(Inst.getOperand(5));
6150 case ARM::VST4LNdAsm_8:
6151 case ARM::VST4LNdAsm_16:
6152 case ARM::VST4LNdAsm_32:
6153 case ARM::VST4LNqAsm_16:
6154 case ARM::VST4LNqAsm_32: {
6156 // Shuffle the operands around so the lane index operand is in the
6159 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6160 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6161 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6162 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6163 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6165 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6167 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6169 TmpInst.addOperand(Inst.getOperand(1)); // lane
6170 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6171 TmpInst.addOperand(Inst.getOperand(5));
6176 // Handle NEON VLD complex aliases.
6177 case ARM::VLD1LNdWB_register_Asm_8:
6178 case ARM::VLD1LNdWB_register_Asm_16:
6179 case ARM::VLD1LNdWB_register_Asm_32: {
6181 // Shuffle the operands around so the lane index operand is in the
6184 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6185 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6186 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6187 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6188 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6189 TmpInst.addOperand(Inst.getOperand(4)); // Rm
6190 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6191 TmpInst.addOperand(Inst.getOperand(1)); // lane
6192 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6193 TmpInst.addOperand(Inst.getOperand(6));
6198 case ARM::VLD2LNdWB_register_Asm_8:
6199 case ARM::VLD2LNdWB_register_Asm_16:
6200 case ARM::VLD2LNdWB_register_Asm_32:
6201 case ARM::VLD2LNqWB_register_Asm_16:
6202 case ARM::VLD2LNqWB_register_Asm_32: {
6204 // Shuffle the operands around so the lane index operand is in the
6207 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6208 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6209 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6211 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6212 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6213 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6214 TmpInst.addOperand(Inst.getOperand(4)); // Rm
6215 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6216 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6218 TmpInst.addOperand(Inst.getOperand(1)); // lane
6219 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6220 TmpInst.addOperand(Inst.getOperand(6));
6225 case ARM::VLD3LNdWB_register_Asm_8:
6226 case ARM::VLD3LNdWB_register_Asm_16:
6227 case ARM::VLD3LNdWB_register_Asm_32:
6228 case ARM::VLD3LNqWB_register_Asm_16:
6229 case ARM::VLD3LNqWB_register_Asm_32: {
6231 // Shuffle the operands around so the lane index operand is in the
6234 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6235 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6236 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6238 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6240 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6241 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6242 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6243 TmpInst.addOperand(Inst.getOperand(4)); // Rm
6244 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6245 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6247 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6249 TmpInst.addOperand(Inst.getOperand(1)); // lane
6250 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6251 TmpInst.addOperand(Inst.getOperand(6));
6256 case ARM::VLD4LNdWB_register_Asm_8:
6257 case ARM::VLD4LNdWB_register_Asm_16:
6258 case ARM::VLD4LNdWB_register_Asm_32:
6259 case ARM::VLD4LNqWB_register_Asm_16:
6260 case ARM::VLD4LNqWB_register_Asm_32: {
6262 // Shuffle the operands around so the lane index operand is in the
6265 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6266 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6267 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6269 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6271 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6273 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6274 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6275 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6276 TmpInst.addOperand(Inst.getOperand(4)); // Rm
6277 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6278 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6280 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6282 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6284 TmpInst.addOperand(Inst.getOperand(1)); // lane
6285 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6286 TmpInst.addOperand(Inst.getOperand(6));
6291 case ARM::VLD1LNdWB_fixed_Asm_8:
6292 case ARM::VLD1LNdWB_fixed_Asm_16:
6293 case ARM::VLD1LNdWB_fixed_Asm_32: {
6295 // Shuffle the operands around so the lane index operand is in the
6298 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6299 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6300 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6301 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6302 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6303 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6304 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6305 TmpInst.addOperand(Inst.getOperand(1)); // lane
6306 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6307 TmpInst.addOperand(Inst.getOperand(5));
6312 case ARM::VLD2LNdWB_fixed_Asm_8:
6313 case ARM::VLD2LNdWB_fixed_Asm_16:
6314 case ARM::VLD2LNdWB_fixed_Asm_32:
6315 case ARM::VLD2LNqWB_fixed_Asm_16:
6316 case ARM::VLD2LNqWB_fixed_Asm_32: {
6318 // Shuffle the operands around so the lane index operand is in the
6321 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6322 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6323 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6325 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6326 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6327 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6328 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6329 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6330 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6332 TmpInst.addOperand(Inst.getOperand(1)); // lane
6333 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6334 TmpInst.addOperand(Inst.getOperand(5));
6339 case ARM::VLD3LNdWB_fixed_Asm_8:
6340 case ARM::VLD3LNdWB_fixed_Asm_16:
6341 case ARM::VLD3LNdWB_fixed_Asm_32:
6342 case ARM::VLD3LNqWB_fixed_Asm_16:
6343 case ARM::VLD3LNqWB_fixed_Asm_32: {
6345 // Shuffle the operands around so the lane index operand is in the
6348 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6349 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6350 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6352 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6354 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6355 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6356 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6357 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6358 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6359 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6361 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6363 TmpInst.addOperand(Inst.getOperand(1)); // lane
6364 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6365 TmpInst.addOperand(Inst.getOperand(5));
6370 case ARM::VLD4LNdWB_fixed_Asm_8:
6371 case ARM::VLD4LNdWB_fixed_Asm_16:
6372 case ARM::VLD4LNdWB_fixed_Asm_32:
6373 case ARM::VLD4LNqWB_fixed_Asm_16:
6374 case ARM::VLD4LNqWB_fixed_Asm_32: {
6376 // Shuffle the operands around so the lane index operand is in the
6379 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6380 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6381 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6383 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6385 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6387 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6388 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6389 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6390 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6391 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6392 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6394 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6396 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6398 TmpInst.addOperand(Inst.getOperand(1)); // lane
6399 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6400 TmpInst.addOperand(Inst.getOperand(5));
6405 case ARM::VLD1LNdAsm_8:
6406 case ARM::VLD1LNdAsm_16:
6407 case ARM::VLD1LNdAsm_32: {
6409 // Shuffle the operands around so the lane index operand is in the
6412 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6413 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6414 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6415 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6416 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6417 TmpInst.addOperand(Inst.getOperand(1)); // lane
6418 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6419 TmpInst.addOperand(Inst.getOperand(5));
6424 case ARM::VLD2LNdAsm_8:
6425 case ARM::VLD2LNdAsm_16:
6426 case ARM::VLD2LNdAsm_32:
6427 case ARM::VLD2LNqAsm_16:
6428 case ARM::VLD2LNqAsm_32: {
6430 // Shuffle the operands around so the lane index operand is in the
6433 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6434 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6435 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6437 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6438 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6439 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6440 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6442 TmpInst.addOperand(Inst.getOperand(1)); // lane
6443 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6444 TmpInst.addOperand(Inst.getOperand(5));
6449 case ARM::VLD3LNdAsm_8:
6450 case ARM::VLD3LNdAsm_16:
6451 case ARM::VLD3LNdAsm_32:
6452 case ARM::VLD3LNqAsm_16:
6453 case ARM::VLD3LNqAsm_32: {
6455 // Shuffle the operands around so the lane index operand is in the
6458 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6459 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6460 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6462 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6464 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6465 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6466 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6467 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6469 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6471 TmpInst.addOperand(Inst.getOperand(1)); // lane
6472 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6473 TmpInst.addOperand(Inst.getOperand(5));
6478 case ARM::VLD4LNdAsm_8:
6479 case ARM::VLD4LNdAsm_16:
6480 case ARM::VLD4LNdAsm_32:
6481 case ARM::VLD4LNqAsm_16:
6482 case ARM::VLD4LNqAsm_32: {
6484 // Shuffle the operands around so the lane index operand is in the
6487 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6488 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6489 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6491 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6493 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6495 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6496 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6497 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6498 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6500 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6502 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6504 TmpInst.addOperand(Inst.getOperand(1)); // lane
6505 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6506 TmpInst.addOperand(Inst.getOperand(5));
6511 // VLD3DUP single 3-element structure to all lanes instructions.
6512 case ARM::VLD3DUPdAsm_8:
6513 case ARM::VLD3DUPdAsm_16:
6514 case ARM::VLD3DUPdAsm_32:
6515 case ARM::VLD3DUPqAsm_8:
6516 case ARM::VLD3DUPqAsm_16:
6517 case ARM::VLD3DUPqAsm_32: {
6520 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6521 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6522 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6524 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6526 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6527 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6528 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6529 TmpInst.addOperand(Inst.getOperand(4));
6534 case ARM::VLD3DUPdWB_fixed_Asm_8:
6535 case ARM::VLD3DUPdWB_fixed_Asm_16:
6536 case ARM::VLD3DUPdWB_fixed_Asm_32:
6537 case ARM::VLD3DUPqWB_fixed_Asm_8:
6538 case ARM::VLD3DUPqWB_fixed_Asm_16:
6539 case ARM::VLD3DUPqWB_fixed_Asm_32: {
6542 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6543 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6544 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6546 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6548 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6549 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6550 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6551 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6552 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6553 TmpInst.addOperand(Inst.getOperand(4));
6558 case ARM::VLD3DUPdWB_register_Asm_8:
6559 case ARM::VLD3DUPdWB_register_Asm_16:
6560 case ARM::VLD3DUPdWB_register_Asm_32:
6561 case ARM::VLD3DUPqWB_register_Asm_8:
6562 case ARM::VLD3DUPqWB_register_Asm_16:
6563 case ARM::VLD3DUPqWB_register_Asm_32: {
6566 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6567 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6568 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6570 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6572 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6573 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6574 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6575 TmpInst.addOperand(Inst.getOperand(3)); // Rm
6576 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6577 TmpInst.addOperand(Inst.getOperand(5));
6582 // VLD3 multiple 3-element structure instructions.
6583 case ARM::VLD3dAsm_8:
6584 case ARM::VLD3dAsm_16:
6585 case ARM::VLD3dAsm_32:
6586 case ARM::VLD3qAsm_8:
6587 case ARM::VLD3qAsm_16:
6588 case ARM::VLD3qAsm_32: {
6591 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6592 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6593 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6595 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6597 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6598 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6599 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6600 TmpInst.addOperand(Inst.getOperand(4));
6605 case ARM::VLD3dWB_fixed_Asm_8:
6606 case ARM::VLD3dWB_fixed_Asm_16:
6607 case ARM::VLD3dWB_fixed_Asm_32:
6608 case ARM::VLD3qWB_fixed_Asm_8:
6609 case ARM::VLD3qWB_fixed_Asm_16:
6610 case ARM::VLD3qWB_fixed_Asm_32: {
6613 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6614 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6615 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6617 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6619 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6620 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6621 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6622 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6623 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6624 TmpInst.addOperand(Inst.getOperand(4));
6629 case ARM::VLD3dWB_register_Asm_8:
6630 case ARM::VLD3dWB_register_Asm_16:
6631 case ARM::VLD3dWB_register_Asm_32:
6632 case ARM::VLD3qWB_register_Asm_8:
6633 case ARM::VLD3qWB_register_Asm_16:
6634 case ARM::VLD3qWB_register_Asm_32: {
6637 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6638 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6639 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6641 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6643 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6644 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6645 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6646 TmpInst.addOperand(Inst.getOperand(3)); // Rm
6647 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6648 TmpInst.addOperand(Inst.getOperand(5));
6653 // VLD4DUP single 3-element structure to all lanes instructions.
6654 case ARM::VLD4DUPdAsm_8:
6655 case ARM::VLD4DUPdAsm_16:
6656 case ARM::VLD4DUPdAsm_32:
6657 case ARM::VLD4DUPqAsm_8:
6658 case ARM::VLD4DUPqAsm_16:
6659 case ARM::VLD4DUPqAsm_32: {
6662 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6663 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6664 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6666 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6668 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6670 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6671 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6672 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6673 TmpInst.addOperand(Inst.getOperand(4));
6678 case ARM::VLD4DUPdWB_fixed_Asm_8:
6679 case ARM::VLD4DUPdWB_fixed_Asm_16:
6680 case ARM::VLD4DUPdWB_fixed_Asm_32:
6681 case ARM::VLD4DUPqWB_fixed_Asm_8:
6682 case ARM::VLD4DUPqWB_fixed_Asm_16:
6683 case ARM::VLD4DUPqWB_fixed_Asm_32: {
6686 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6687 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6688 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6690 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6692 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6694 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6695 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6696 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6697 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6698 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6699 TmpInst.addOperand(Inst.getOperand(4));
6704 case ARM::VLD4DUPdWB_register_Asm_8:
6705 case ARM::VLD4DUPdWB_register_Asm_16:
6706 case ARM::VLD4DUPdWB_register_Asm_32:
6707 case ARM::VLD4DUPqWB_register_Asm_8:
6708 case ARM::VLD4DUPqWB_register_Asm_16:
6709 case ARM::VLD4DUPqWB_register_Asm_32: {
6712 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6713 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6714 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6716 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6718 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6720 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6721 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6722 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6723 TmpInst.addOperand(Inst.getOperand(3)); // Rm
6724 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6725 TmpInst.addOperand(Inst.getOperand(5));
6730 // VLD4 multiple 4-element structure instructions.
6731 case ARM::VLD4dAsm_8:
6732 case ARM::VLD4dAsm_16:
6733 case ARM::VLD4dAsm_32:
6734 case ARM::VLD4qAsm_8:
6735 case ARM::VLD4qAsm_16:
6736 case ARM::VLD4qAsm_32: {
6739 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6740 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6741 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6743 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6745 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6747 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6748 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6749 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6750 TmpInst.addOperand(Inst.getOperand(4));
6755 case ARM::VLD4dWB_fixed_Asm_8:
6756 case ARM::VLD4dWB_fixed_Asm_16:
6757 case ARM::VLD4dWB_fixed_Asm_32:
6758 case ARM::VLD4qWB_fixed_Asm_8:
6759 case ARM::VLD4qWB_fixed_Asm_16:
6760 case ARM::VLD4qWB_fixed_Asm_32: {
6763 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6764 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6765 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6767 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6769 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6771 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6772 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6773 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6774 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6775 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6776 TmpInst.addOperand(Inst.getOperand(4));
6781 case ARM::VLD4dWB_register_Asm_8:
6782 case ARM::VLD4dWB_register_Asm_16:
6783 case ARM::VLD4dWB_register_Asm_32:
6784 case ARM::VLD4qWB_register_Asm_8:
6785 case ARM::VLD4qWB_register_Asm_16:
6786 case ARM::VLD4qWB_register_Asm_32: {
6789 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6790 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6791 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6793 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6795 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6797 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6798 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6799 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6800 TmpInst.addOperand(Inst.getOperand(3)); // Rm
6801 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6802 TmpInst.addOperand(Inst.getOperand(5));
6807 // VST3 multiple 3-element structure instructions.
6808 case ARM::VST3dAsm_8:
6809 case ARM::VST3dAsm_16:
6810 case ARM::VST3dAsm_32:
6811 case ARM::VST3qAsm_8:
6812 case ARM::VST3qAsm_16:
6813 case ARM::VST3qAsm_32: {
6816 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6817 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6818 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6819 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6820 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6822 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6824 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6825 TmpInst.addOperand(Inst.getOperand(4));
6830 case ARM::VST3dWB_fixed_Asm_8:
6831 case ARM::VST3dWB_fixed_Asm_16:
6832 case ARM::VST3dWB_fixed_Asm_32:
6833 case ARM::VST3qWB_fixed_Asm_8:
6834 case ARM::VST3qWB_fixed_Asm_16:
6835 case ARM::VST3qWB_fixed_Asm_32: {
6838 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6839 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6840 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6841 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6842 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6843 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6844 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6846 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6848 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6849 TmpInst.addOperand(Inst.getOperand(4));
6854 case ARM::VST3dWB_register_Asm_8:
6855 case ARM::VST3dWB_register_Asm_16:
6856 case ARM::VST3dWB_register_Asm_32:
6857 case ARM::VST3qWB_register_Asm_8:
6858 case ARM::VST3qWB_register_Asm_16:
6859 case ARM::VST3qWB_register_Asm_32: {
6862 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6863 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6864 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6865 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6866 TmpInst.addOperand(Inst.getOperand(3)); // Rm
6867 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6868 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6870 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6872 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6873 TmpInst.addOperand(Inst.getOperand(5));
6878 // VST4 multiple 3-element structure instructions.
6879 case ARM::VST4dAsm_8:
6880 case ARM::VST4dAsm_16:
6881 case ARM::VST4dAsm_32:
6882 case ARM::VST4qAsm_8:
6883 case ARM::VST4qAsm_16:
6884 case ARM::VST4qAsm_32: {
6887 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6888 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6889 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6890 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6891 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6893 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6895 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6897 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6898 TmpInst.addOperand(Inst.getOperand(4));
6903 case ARM::VST4dWB_fixed_Asm_8:
6904 case ARM::VST4dWB_fixed_Asm_16:
6905 case ARM::VST4dWB_fixed_Asm_32:
6906 case ARM::VST4qWB_fixed_Asm_8:
6907 case ARM::VST4qWB_fixed_Asm_16:
6908 case ARM::VST4qWB_fixed_Asm_32: {
6911 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6912 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6913 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6914 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6915 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6916 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6917 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6919 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6921 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6923 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6924 TmpInst.addOperand(Inst.getOperand(4));
6929 case ARM::VST4dWB_register_Asm_8:
6930 case ARM::VST4dWB_register_Asm_16:
6931 case ARM::VST4dWB_register_Asm_32:
6932 case ARM::VST4qWB_register_Asm_8:
6933 case ARM::VST4qWB_register_Asm_16:
6934 case ARM::VST4qWB_register_Asm_32: {
6937 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6938 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6939 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6940 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6941 TmpInst.addOperand(Inst.getOperand(3)); // Rm
6942 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6943 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6945 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6947 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6949 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6950 TmpInst.addOperand(Inst.getOperand(5));
6955 // Handle encoding choice for the shift-immediate instructions.
6958 case ARM::t2ASRri: {
6959 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
6960 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
6961 Inst.getOperand(5).getReg() == (inITBlock() ? 0 : ARM::CPSR) &&
6962 !(static_cast<ARMOperand*>(Operands[3])->isToken() &&
6963 static_cast<ARMOperand*>(Operands[3])->getToken() == ".w")) {
6965 switch (Inst.getOpcode()) {
6966 default: llvm_unreachable("unexpected opcode");
6967 case ARM::t2LSLri: NewOpc = ARM::tLSLri; break;
6968 case ARM::t2LSRri: NewOpc = ARM::tLSRri; break;
6969 case ARM::t2ASRri: NewOpc = ARM::tASRri; break;
6971 // The Thumb1 operands aren't in the same order. Awesome, eh?
6973 TmpInst.setOpcode(NewOpc);
6974 TmpInst.addOperand(Inst.getOperand(0));
6975 TmpInst.addOperand(Inst.getOperand(5));
6976 TmpInst.addOperand(Inst.getOperand(1));
6977 TmpInst.addOperand(Inst.getOperand(2));
6978 TmpInst.addOperand(Inst.getOperand(3));
6979 TmpInst.addOperand(Inst.getOperand(4));
6986 // Handle the Thumb2 mode MOV complex aliases.
6988 case ARM::t2MOVSsr: {
6989 // Which instruction to expand to depends on the CCOut operand and
6990 // whether we're in an IT block if the register operands are low
6992 bool isNarrow = false;
6993 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
6994 isARMLowRegister(Inst.getOperand(1).getReg()) &&
6995 isARMLowRegister(Inst.getOperand(2).getReg()) &&
6996 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
6997 inITBlock() == (Inst.getOpcode() == ARM::t2MOVsr))
7001 switch(ARM_AM::getSORegShOp(Inst.getOperand(3).getImm())) {
7002 default: llvm_unreachable("unexpected opcode!");
7003 case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRrr : ARM::t2ASRrr; break;
7004 case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRrr : ARM::t2LSRrr; break;
7005 case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLrr : ARM::t2LSLrr; break;
7006 case ARM_AM::ror: newOpc = isNarrow ? ARM::tROR : ARM::t2RORrr; break;
7008 TmpInst.setOpcode(newOpc);
7009 TmpInst.addOperand(Inst.getOperand(0)); // Rd
7011 TmpInst.addOperand(MCOperand::CreateReg(
7012 Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0));
7013 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7014 TmpInst.addOperand(Inst.getOperand(2)); // Rm
7015 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7016 TmpInst.addOperand(Inst.getOperand(5));
7018 TmpInst.addOperand(MCOperand::CreateReg(
7019 Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0));
7024 case ARM::t2MOVSsi: {
7025 // Which instruction to expand to depends on the CCOut operand and
7026 // whether we're in an IT block if the register operands are low
7028 bool isNarrow = false;
7029 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7030 isARMLowRegister(Inst.getOperand(1).getReg()) &&
7031 inITBlock() == (Inst.getOpcode() == ARM::t2MOVsi))
7035 switch(ARM_AM::getSORegShOp(Inst.getOperand(2).getImm())) {
7036 default: llvm_unreachable("unexpected opcode!");
7037 case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRri : ARM::t2ASRri; break;
7038 case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRri : ARM::t2LSRri; break;
7039 case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLri : ARM::t2LSLri; break;
7040 case ARM_AM::ror: newOpc = ARM::t2RORri; isNarrow = false; break;
7041 case ARM_AM::rrx: isNarrow = false; newOpc = ARM::t2RRX; break;
7043 unsigned Amount = ARM_AM::getSORegOffset(Inst.getOperand(2).getImm());
7044 if (Amount == 32) Amount = 0;
7045 TmpInst.setOpcode(newOpc);
7046 TmpInst.addOperand(Inst.getOperand(0)); // Rd
7048 TmpInst.addOperand(MCOperand::CreateReg(
7049 Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0));
7050 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7051 if (newOpc != ARM::t2RRX)
7052 TmpInst.addOperand(MCOperand::CreateImm(Amount));
7053 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7054 TmpInst.addOperand(Inst.getOperand(4));
7056 TmpInst.addOperand(MCOperand::CreateReg(
7057 Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0));
7061 // Handle the ARM mode MOV complex aliases.
7066 ARM_AM::ShiftOpc ShiftTy;
7067 switch(Inst.getOpcode()) {
7068 default: llvm_unreachable("unexpected opcode!");
7069 case ARM::ASRr: ShiftTy = ARM_AM::asr; break;
7070 case ARM::LSRr: ShiftTy = ARM_AM::lsr; break;
7071 case ARM::LSLr: ShiftTy = ARM_AM::lsl; break;
7072 case ARM::RORr: ShiftTy = ARM_AM::ror; break;
7074 unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, 0);
7076 TmpInst.setOpcode(ARM::MOVsr);
7077 TmpInst.addOperand(Inst.getOperand(0)); // Rd
7078 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7079 TmpInst.addOperand(Inst.getOperand(2)); // Rm
7080 TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty
7081 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7082 TmpInst.addOperand(Inst.getOperand(4));
7083 TmpInst.addOperand(Inst.getOperand(5)); // cc_out
7091 ARM_AM::ShiftOpc ShiftTy;
7092 switch(Inst.getOpcode()) {
7093 default: llvm_unreachable("unexpected opcode!");
7094 case ARM::ASRi: ShiftTy = ARM_AM::asr; break;
7095 case ARM::LSRi: ShiftTy = ARM_AM::lsr; break;
7096 case ARM::LSLi: ShiftTy = ARM_AM::lsl; break;
7097 case ARM::RORi: ShiftTy = ARM_AM::ror; break;
7099 // A shift by zero is a plain MOVr, not a MOVsi.
7100 unsigned Amt = Inst.getOperand(2).getImm();
7101 unsigned Opc = Amt == 0 ? ARM::MOVr : ARM::MOVsi;
7102 // A shift by 32 should be encoded as 0 when permitted
7103 if (Amt == 32 && (ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr))
7105 unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, Amt);
7107 TmpInst.setOpcode(Opc);
7108 TmpInst.addOperand(Inst.getOperand(0)); // Rd
7109 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7110 if (Opc == ARM::MOVsi)
7111 TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty
7112 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7113 TmpInst.addOperand(Inst.getOperand(4));
7114 TmpInst.addOperand(Inst.getOperand(5)); // cc_out
7119 unsigned Shifter = ARM_AM::getSORegOpc(ARM_AM::rrx, 0);
7121 TmpInst.setOpcode(ARM::MOVsi);
7122 TmpInst.addOperand(Inst.getOperand(0)); // Rd
7123 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7124 TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty
7125 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
7126 TmpInst.addOperand(Inst.getOperand(3));
7127 TmpInst.addOperand(Inst.getOperand(4)); // cc_out
7131 case ARM::t2LDMIA_UPD: {
7132 // If this is a load of a single register, then we should use
7133 // a post-indexed LDR instruction instead, per the ARM ARM.
7134 if (Inst.getNumOperands() != 5)
7137 TmpInst.setOpcode(ARM::t2LDR_POST);
7138 TmpInst.addOperand(Inst.getOperand(4)); // Rt
7139 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
7140 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7141 TmpInst.addOperand(MCOperand::CreateImm(4));
7142 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
7143 TmpInst.addOperand(Inst.getOperand(3));
7147 case ARM::t2STMDB_UPD: {
7148 // If this is a store of a single register, then we should use
7149 // a pre-indexed STR instruction instead, per the ARM ARM.
7150 if (Inst.getNumOperands() != 5)
7153 TmpInst.setOpcode(ARM::t2STR_PRE);
7154 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
7155 TmpInst.addOperand(Inst.getOperand(4)); // Rt
7156 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7157 TmpInst.addOperand(MCOperand::CreateImm(-4));
7158 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
7159 TmpInst.addOperand(Inst.getOperand(3));
7163 case ARM::LDMIA_UPD:
7164 // If this is a load of a single register via a 'pop', then we should use
7165 // a post-indexed LDR instruction instead, per the ARM ARM.
7166 if (static_cast<ARMOperand*>(Operands[0])->getToken() == "pop" &&
7167 Inst.getNumOperands() == 5) {
7169 TmpInst.setOpcode(ARM::LDR_POST_IMM);
7170 TmpInst.addOperand(Inst.getOperand(4)); // Rt
7171 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
7172 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7173 TmpInst.addOperand(MCOperand::CreateReg(0)); // am2offset
7174 TmpInst.addOperand(MCOperand::CreateImm(4));
7175 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
7176 TmpInst.addOperand(Inst.getOperand(3));
7181 case ARM::STMDB_UPD:
7182 // If this is a store of a single register via a 'push', then we should use
7183 // a pre-indexed STR instruction instead, per the ARM ARM.
7184 if (static_cast<ARMOperand*>(Operands[0])->getToken() == "push" &&
7185 Inst.getNumOperands() == 5) {
7187 TmpInst.setOpcode(ARM::STR_PRE_IMM);
7188 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
7189 TmpInst.addOperand(Inst.getOperand(4)); // Rt
7190 TmpInst.addOperand(Inst.getOperand(1)); // addrmode_imm12
7191 TmpInst.addOperand(MCOperand::CreateImm(-4));
7192 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
7193 TmpInst.addOperand(Inst.getOperand(3));
7197 case ARM::t2ADDri12:
7198 // If the immediate fits for encoding T3 (t2ADDri) and the generic "add"
7199 // mnemonic was used (not "addw"), encoding T3 is preferred.
7200 if (static_cast<ARMOperand*>(Operands[0])->getToken() != "add" ||
7201 ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1)
7203 Inst.setOpcode(ARM::t2ADDri);
7204 Inst.addOperand(MCOperand::CreateReg(0)); // cc_out
7206 case ARM::t2SUBri12:
7207 // If the immediate fits for encoding T3 (t2SUBri) and the generic "sub"
7208 // mnemonic was used (not "subw"), encoding T3 is preferred.
7209 if (static_cast<ARMOperand*>(Operands[0])->getToken() != "sub" ||
7210 ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1)
7212 Inst.setOpcode(ARM::t2SUBri);
7213 Inst.addOperand(MCOperand::CreateReg(0)); // cc_out
7216 // If the immediate is in the range 0-7, we want tADDi3 iff Rd was
7217 // explicitly specified. From the ARM ARM: "Encoding T1 is preferred
7218 // to encoding T2 if <Rd> is specified and encoding T2 is preferred
7219 // to encoding T1 if <Rd> is omitted."
7220 if ((unsigned)Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) {
7221 Inst.setOpcode(ARM::tADDi3);
7226 // If the immediate is in the range 0-7, we want tADDi3 iff Rd was
7227 // explicitly specified. From the ARM ARM: "Encoding T1 is preferred
7228 // to encoding T2 if <Rd> is specified and encoding T2 is preferred
7229 // to encoding T1 if <Rd> is omitted."
7230 if ((unsigned)Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) {
7231 Inst.setOpcode(ARM::tSUBi3);
7236 case ARM::t2SUBri: {
7237 // If the destination and first source operand are the same, and
7238 // the flags are compatible with the current IT status, use encoding T2
7239 // instead of T3. For compatibility with the system 'as'. Make sure the
7240 // wide encoding wasn't explicit.
7241 if (Inst.getOperand(0).getReg() != Inst.getOperand(1).getReg() ||
7242 !isARMLowRegister(Inst.getOperand(0).getReg()) ||
7243 (unsigned)Inst.getOperand(2).getImm() > 255 ||
7244 ((!inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR) ||
7245 (inITBlock() && Inst.getOperand(5).getReg() != 0)) ||
7246 (static_cast<ARMOperand*>(Operands[3])->isToken() &&
7247 static_cast<ARMOperand*>(Operands[3])->getToken() == ".w"))
7250 TmpInst.setOpcode(Inst.getOpcode() == ARM::t2ADDri ?
7251 ARM::tADDi8 : ARM::tSUBi8);
7252 TmpInst.addOperand(Inst.getOperand(0));
7253 TmpInst.addOperand(Inst.getOperand(5));
7254 TmpInst.addOperand(Inst.getOperand(0));
7255 TmpInst.addOperand(Inst.getOperand(2));
7256 TmpInst.addOperand(Inst.getOperand(3));
7257 TmpInst.addOperand(Inst.getOperand(4));
7261 case ARM::t2ADDrr: {
7262 // If the destination and first source operand are the same, and
7263 // there's no setting of the flags, use encoding T2 instead of T3.
7264 // Note that this is only for ADD, not SUB. This mirrors the system
7265 // 'as' behaviour. Make sure the wide encoding wasn't explicit.
7266 if (Inst.getOperand(0).getReg() != Inst.getOperand(1).getReg() ||
7267 Inst.getOperand(5).getReg() != 0 ||
7268 (static_cast<ARMOperand*>(Operands[3])->isToken() &&
7269 static_cast<ARMOperand*>(Operands[3])->getToken() == ".w"))
7272 TmpInst.setOpcode(ARM::tADDhirr);
7273 TmpInst.addOperand(Inst.getOperand(0));
7274 TmpInst.addOperand(Inst.getOperand(0));
7275 TmpInst.addOperand(Inst.getOperand(2));
7276 TmpInst.addOperand(Inst.getOperand(3));
7277 TmpInst.addOperand(Inst.getOperand(4));
7281 case ARM::tADDrSP: {
7282 // If the non-SP source operand and the destination operand are not the
7283 // same, we need to use the 32-bit encoding if it's available.
7284 if (Inst.getOperand(0).getReg() != Inst.getOperand(2).getReg()) {
7285 Inst.setOpcode(ARM::t2ADDrr);
7286 Inst.addOperand(MCOperand::CreateReg(0)); // cc_out
7292 // A Thumb conditional branch outside of an IT block is a tBcc.
7293 if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()) {
7294 Inst.setOpcode(ARM::tBcc);
7299 // A Thumb2 conditional branch outside of an IT block is a t2Bcc.
7300 if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()){
7301 Inst.setOpcode(ARM::t2Bcc);
7306 // If the conditional is AL or we're in an IT block, we really want t2B.
7307 if (Inst.getOperand(1).getImm() == ARMCC::AL || inITBlock()) {
7308 Inst.setOpcode(ARM::t2B);
7313 // If the conditional is AL, we really want tB.
7314 if (Inst.getOperand(1).getImm() == ARMCC::AL) {
7315 Inst.setOpcode(ARM::tB);
7320 // If the register list contains any high registers, or if the writeback
7321 // doesn't match what tLDMIA can do, we need to use the 32-bit encoding
7322 // instead if we're in Thumb2. Otherwise, this should have generated
7323 // an error in validateInstruction().
7324 unsigned Rn = Inst.getOperand(0).getReg();
7325 bool hasWritebackToken =
7326 (static_cast<ARMOperand*>(Operands[3])->isToken() &&
7327 static_cast<ARMOperand*>(Operands[3])->getToken() == "!");
7328 bool listContainsBase;
7329 if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase) ||
7330 (!listContainsBase && !hasWritebackToken) ||
7331 (listContainsBase && hasWritebackToken)) {
7332 // 16-bit encoding isn't sufficient. Switch to the 32-bit version.
7333 assert (isThumbTwo());
7334 Inst.setOpcode(hasWritebackToken ? ARM::t2LDMIA_UPD : ARM::t2LDMIA);
7335 // If we're switching to the updating version, we need to insert
7336 // the writeback tied operand.
7337 if (hasWritebackToken)
7338 Inst.insert(Inst.begin(),
7339 MCOperand::CreateReg(Inst.getOperand(0).getReg()));
7344 case ARM::tSTMIA_UPD: {
7345 // If the register list contains any high registers, we need to use
7346 // the 32-bit encoding instead if we're in Thumb2. Otherwise, this
7347 // should have generated an error in validateInstruction().
7348 unsigned Rn = Inst.getOperand(0).getReg();
7349 bool listContainsBase;
7350 if (checkLowRegisterList(Inst, 4, Rn, 0, listContainsBase)) {
7351 // 16-bit encoding isn't sufficient. Switch to the 32-bit version.
7352 assert (isThumbTwo());
7353 Inst.setOpcode(ARM::t2STMIA_UPD);
7359 bool listContainsBase;
7360 // If the register list contains any high registers, we need to use
7361 // the 32-bit encoding instead if we're in Thumb2. Otherwise, this
7362 // should have generated an error in validateInstruction().
7363 if (!checkLowRegisterList(Inst, 2, 0, ARM::PC, listContainsBase))
7365 assert (isThumbTwo());
7366 Inst.setOpcode(ARM::t2LDMIA_UPD);
7367 // Add the base register and writeback operands.
7368 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
7369 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
7373 bool listContainsBase;
7374 if (!checkLowRegisterList(Inst, 2, 0, ARM::LR, listContainsBase))
7376 assert (isThumbTwo());
7377 Inst.setOpcode(ARM::t2STMDB_UPD);
7378 // Add the base register and writeback operands.
7379 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
7380 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
7384 // If we can use the 16-bit encoding and the user didn't explicitly
7385 // request the 32-bit variant, transform it here.
7386 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7387 (unsigned)Inst.getOperand(1).getImm() <= 255 &&
7388 ((!inITBlock() && Inst.getOperand(2).getImm() == ARMCC::AL &&
7389 Inst.getOperand(4).getReg() == ARM::CPSR) ||
7390 (inITBlock() && Inst.getOperand(4).getReg() == 0)) &&
7391 (!static_cast<ARMOperand*>(Operands[2])->isToken() ||
7392 static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) {
7393 // The operands aren't in the same order for tMOVi8...
7395 TmpInst.setOpcode(ARM::tMOVi8);
7396 TmpInst.addOperand(Inst.getOperand(0));
7397 TmpInst.addOperand(Inst.getOperand(4));
7398 TmpInst.addOperand(Inst.getOperand(1));
7399 TmpInst.addOperand(Inst.getOperand(2));
7400 TmpInst.addOperand(Inst.getOperand(3));
7407 // If we can use the 16-bit encoding and the user didn't explicitly
7408 // request the 32-bit variant, transform it here.
7409 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7410 isARMLowRegister(Inst.getOperand(1).getReg()) &&
7411 Inst.getOperand(2).getImm() == ARMCC::AL &&
7412 Inst.getOperand(4).getReg() == ARM::CPSR &&
7413 (!static_cast<ARMOperand*>(Operands[2])->isToken() ||
7414 static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) {
7415 // The operands aren't the same for tMOV[S]r... (no cc_out)
7417 TmpInst.setOpcode(Inst.getOperand(4).getReg() ? ARM::tMOVSr : ARM::tMOVr);
7418 TmpInst.addOperand(Inst.getOperand(0));
7419 TmpInst.addOperand(Inst.getOperand(1));
7420 TmpInst.addOperand(Inst.getOperand(2));
7421 TmpInst.addOperand(Inst.getOperand(3));
7431 // If we can use the 16-bit encoding and the user didn't explicitly
7432 // request the 32-bit variant, transform it here.
7433 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7434 isARMLowRegister(Inst.getOperand(1).getReg()) &&
7435 Inst.getOperand(2).getImm() == 0 &&
7436 (!static_cast<ARMOperand*>(Operands[2])->isToken() ||
7437 static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) {
7439 switch (Inst.getOpcode()) {
7440 default: llvm_unreachable("Illegal opcode!");
7441 case ARM::t2SXTH: NewOpc = ARM::tSXTH; break;
7442 case ARM::t2SXTB: NewOpc = ARM::tSXTB; break;
7443 case ARM::t2UXTH: NewOpc = ARM::tUXTH; break;
7444 case ARM::t2UXTB: NewOpc = ARM::tUXTB; break;
7446 // The operands aren't the same for thumb1 (no rotate operand).
7448 TmpInst.setOpcode(NewOpc);
7449 TmpInst.addOperand(Inst.getOperand(0));
7450 TmpInst.addOperand(Inst.getOperand(1));
7451 TmpInst.addOperand(Inst.getOperand(3));
7452 TmpInst.addOperand(Inst.getOperand(4));
7459 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(2).getImm());
7460 // rrx shifts and asr/lsr of #32 is encoded as 0
7461 if (SOpc == ARM_AM::rrx || SOpc == ARM_AM::asr || SOpc == ARM_AM::lsr)
7463 if (ARM_AM::getSORegOffset(Inst.getOperand(2).getImm()) == 0) {
7464 // Shifting by zero is accepted as a vanilla 'MOVr'
7466 TmpInst.setOpcode(ARM::MOVr);
7467 TmpInst.addOperand(Inst.getOperand(0));
7468 TmpInst.addOperand(Inst.getOperand(1));
7469 TmpInst.addOperand(Inst.getOperand(3));
7470 TmpInst.addOperand(Inst.getOperand(4));
7471 TmpInst.addOperand(Inst.getOperand(5));
7484 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(3).getImm());
7485 if (SOpc == ARM_AM::rrx) return false;
7486 switch (Inst.getOpcode()) {
7487 default: llvm_unreachable("unexpected opcode!");
7488 case ARM::ANDrsi: newOpc = ARM::ANDrr; break;
7489 case ARM::ORRrsi: newOpc = ARM::ORRrr; break;
7490 case ARM::EORrsi: newOpc = ARM::EORrr; break;
7491 case ARM::BICrsi: newOpc = ARM::BICrr; break;
7492 case ARM::SUBrsi: newOpc = ARM::SUBrr; break;
7493 case ARM::ADDrsi: newOpc = ARM::ADDrr; break;
7495 // If the shift is by zero, use the non-shifted instruction definition.
7496 // The exception is for right shifts, where 0 == 32
7497 if (ARM_AM::getSORegOffset(Inst.getOperand(3).getImm()) == 0 &&
7498 !(SOpc == ARM_AM::lsr || SOpc == ARM_AM::asr)) {
7500 TmpInst.setOpcode(newOpc);
7501 TmpInst.addOperand(Inst.getOperand(0));
7502 TmpInst.addOperand(Inst.getOperand(1));
7503 TmpInst.addOperand(Inst.getOperand(2));
7504 TmpInst.addOperand(Inst.getOperand(4));
7505 TmpInst.addOperand(Inst.getOperand(5));
7506 TmpInst.addOperand(Inst.getOperand(6));
7514 // The mask bits for all but the first condition are represented as
7515 // the low bit of the condition code value implies 't'. We currently
7516 // always have 1 implies 't', so XOR toggle the bits if the low bit
7517 // of the condition code is zero.
7518 MCOperand &MO = Inst.getOperand(1);
7519 unsigned Mask = MO.getImm();
7520 unsigned OrigMask = Mask;
7521 unsigned TZ = countTrailingZeros(Mask);
7522 if ((Inst.getOperand(0).getImm() & 1) == 0) {
7523 assert(Mask && TZ <= 3 && "illegal IT mask value!");
7524 Mask ^= (0xE << TZ) & 0xF;
7528 // Set up the IT block state according to the IT instruction we just
7530 assert(!inITBlock() && "nested IT blocks?!");
7531 ITState.Cond = ARMCC::CondCodes(Inst.getOperand(0).getImm());
7532 ITState.Mask = OrigMask; // Use the original mask, not the updated one.
7533 ITState.CurPosition = 0;
7534 ITState.FirstCond = true;
7544 // Assemblers should use the narrow encodings of these instructions when permissible.
7545 if ((isARMLowRegister(Inst.getOperand(1).getReg()) &&
7546 isARMLowRegister(Inst.getOperand(2).getReg())) &&
7547 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
7548 ((!inITBlock() && Inst.getOperand(5).getReg() == ARM::CPSR) ||
7549 (inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR)) &&
7550 (!static_cast<ARMOperand*>(Operands[3])->isToken() ||
7551 !static_cast<ARMOperand*>(Operands[3])->getToken().equals_lower(".w"))) {
7553 switch (Inst.getOpcode()) {
7554 default: llvm_unreachable("unexpected opcode");
7555 case ARM::t2LSLrr: NewOpc = ARM::tLSLrr; break;
7556 case ARM::t2LSRrr: NewOpc = ARM::tLSRrr; break;
7557 case ARM::t2ASRrr: NewOpc = ARM::tASRrr; break;
7558 case ARM::t2SBCrr: NewOpc = ARM::tSBC; break;
7559 case ARM::t2RORrr: NewOpc = ARM::tROR; break;
7560 case ARM::t2BICrr: NewOpc = ARM::tBIC; break;
7563 TmpInst.setOpcode(NewOpc);
7564 TmpInst.addOperand(Inst.getOperand(0));
7565 TmpInst.addOperand(Inst.getOperand(5));
7566 TmpInst.addOperand(Inst.getOperand(1));
7567 TmpInst.addOperand(Inst.getOperand(2));
7568 TmpInst.addOperand(Inst.getOperand(3));
7569 TmpInst.addOperand(Inst.getOperand(4));
7580 // Assemblers should use the narrow encodings of these instructions when permissible.
7581 // These instructions are special in that they are commutable, so shorter encodings
7582 // are available more often.
7583 if ((isARMLowRegister(Inst.getOperand(1).getReg()) &&
7584 isARMLowRegister(Inst.getOperand(2).getReg())) &&
7585 (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() ||
7586 Inst.getOperand(0).getReg() == Inst.getOperand(2).getReg()) &&
7587 ((!inITBlock() && Inst.getOperand(5).getReg() == ARM::CPSR) ||
7588 (inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR)) &&
7589 (!static_cast<ARMOperand*>(Operands[3])->isToken() ||
7590 !static_cast<ARMOperand*>(Operands[3])->getToken().equals_lower(".w"))) {
7592 switch (Inst.getOpcode()) {
7593 default: llvm_unreachable("unexpected opcode");
7594 case ARM::t2ADCrr: NewOpc = ARM::tADC; break;
7595 case ARM::t2ANDrr: NewOpc = ARM::tAND; break;
7596 case ARM::t2EORrr: NewOpc = ARM::tEOR; break;
7597 case ARM::t2ORRrr: NewOpc = ARM::tORR; break;
7600 TmpInst.setOpcode(NewOpc);
7601 TmpInst.addOperand(Inst.getOperand(0));
7602 TmpInst.addOperand(Inst.getOperand(5));
7603 if (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()) {
7604 TmpInst.addOperand(Inst.getOperand(1));
7605 TmpInst.addOperand(Inst.getOperand(2));
7607 TmpInst.addOperand(Inst.getOperand(2));
7608 TmpInst.addOperand(Inst.getOperand(1));
7610 TmpInst.addOperand(Inst.getOperand(3));
7611 TmpInst.addOperand(Inst.getOperand(4));
7621 unsigned ARMAsmParser::checkTargetMatchPredicate(MCInst &Inst) {
7622 // 16-bit thumb arithmetic instructions either require or preclude the 'S'
7623 // suffix depending on whether they're in an IT block or not.
7624 unsigned Opc = Inst.getOpcode();
7625 const MCInstrDesc &MCID = MII.get(Opc);
7626 if (MCID.TSFlags & ARMII::ThumbArithFlagSetting) {
7627 assert(MCID.hasOptionalDef() &&
7628 "optionally flag setting instruction missing optional def operand");
7629 assert(MCID.NumOperands == Inst.getNumOperands() &&
7630 "operand count mismatch!");
7631 // Find the optional-def operand (cc_out).
7634 !MCID.OpInfo[OpNo].isOptionalDef() && OpNo < MCID.NumOperands;
7637 // If we're parsing Thumb1, reject it completely.
7638 if (isThumbOne() && Inst.getOperand(OpNo).getReg() != ARM::CPSR)
7639 return Match_MnemonicFail;
7640 // If we're parsing Thumb2, which form is legal depends on whether we're
7642 if (isThumbTwo() && Inst.getOperand(OpNo).getReg() != ARM::CPSR &&
7644 return Match_RequiresITBlock;
7645 if (isThumbTwo() && Inst.getOperand(OpNo).getReg() == ARM::CPSR &&
7647 return Match_RequiresNotITBlock;
7649 // Some high-register supporting Thumb1 encodings only allow both registers
7650 // to be from r0-r7 when in Thumb2.
7651 else if (Opc == ARM::tADDhirr && isThumbOne() &&
7652 isARMLowRegister(Inst.getOperand(1).getReg()) &&
7653 isARMLowRegister(Inst.getOperand(2).getReg()))
7654 return Match_RequiresThumb2;
7655 // Others only require ARMv6 or later.
7656 else if (Opc == ARM::tMOVr && isThumbOne() && !hasV6Ops() &&
7657 isARMLowRegister(Inst.getOperand(0).getReg()) &&
7658 isARMLowRegister(Inst.getOperand(1).getReg()))
7659 return Match_RequiresV6;
7660 return Match_Success;
7663 static const char *getSubtargetFeatureName(unsigned Val);
7665 MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
7666 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
7667 MCStreamer &Out, unsigned &ErrorInfo,
7668 bool MatchingInlineAsm) {
7670 unsigned MatchResult;
7672 MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo,
7674 switch (MatchResult) {
7677 // Context sensitive operand constraints aren't handled by the matcher,
7678 // so check them here.
7679 if (validateInstruction(Inst, Operands)) {
7680 // Still progress the IT block, otherwise one wrong condition causes
7681 // nasty cascading errors.
7682 forwardITPosition();
7686 { // processInstruction() updates inITBlock state, we need to save it away
7687 bool wasInITBlock = inITBlock();
7689 // Some instructions need post-processing to, for example, tweak which
7690 // encoding is selected. Loop on it while changes happen so the
7691 // individual transformations can chain off each other. E.g.,
7692 // tPOP(r8)->t2LDMIA_UPD(sp,r8)->t2STR_POST(sp,r8)
7693 while (processInstruction(Inst, Operands))
7696 // Only after the instruction is fully processed, we can validate it
7697 if (wasInITBlock && hasV8Ops() && isThumb() &&
7698 !isV8EligibleForIT(&Inst, 2)) {
7699 Warning(IDLoc, "deprecated instruction in IT block");
7703 // Only move forward at the very end so that everything in validate
7704 // and process gets a consistent answer about whether we're in an IT
7706 forwardITPosition();
7708 // ITasm is an ARM mode pseudo-instruction that just sets the ITblock and
7709 // doesn't actually encode.
7710 if (Inst.getOpcode() == ARM::ITasm)
7714 Out.EmitInstruction(Inst);
7716 case Match_MissingFeature: {
7717 assert(ErrorInfo && "Unknown missing feature!");
7718 // Special case the error message for the very common case where only
7719 // a single subtarget feature is missing (Thumb vs. ARM, e.g.).
7720 std::string Msg = "instruction requires:";
7722 for (unsigned i = 0; i < (sizeof(ErrorInfo)*8-1); ++i) {
7723 if (ErrorInfo & Mask) {
7725 Msg += getSubtargetFeatureName(ErrorInfo & Mask);
7729 return Error(IDLoc, Msg);
7731 case Match_InvalidOperand: {
7732 SMLoc ErrorLoc = IDLoc;
7733 if (ErrorInfo != ~0U) {
7734 if (ErrorInfo >= Operands.size())
7735 return Error(IDLoc, "too few operands for instruction");
7737 ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc();
7738 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
7741 return Error(ErrorLoc, "invalid operand for instruction");
7743 case Match_MnemonicFail:
7744 return Error(IDLoc, "invalid instruction",
7745 ((ARMOperand*)Operands[0])->getLocRange());
7746 case Match_RequiresNotITBlock:
7747 return Error(IDLoc, "flag setting instruction only valid outside IT block");
7748 case Match_RequiresITBlock:
7749 return Error(IDLoc, "instruction only valid inside IT block");
7750 case Match_RequiresV6:
7751 return Error(IDLoc, "instruction variant requires ARMv6 or later");
7752 case Match_RequiresThumb2:
7753 return Error(IDLoc, "instruction variant requires Thumb2");
7754 case Match_ImmRange0_15: {
7755 SMLoc ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc();
7756 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
7757 return Error(ErrorLoc, "immediate operand must be in the range [0,15]");
7759 case Match_ImmRange0_239: {
7760 SMLoc ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc();
7761 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
7762 return Error(ErrorLoc, "immediate operand must be in the range [0,239]");
7766 llvm_unreachable("Implement any new match types added!");
7769 /// parseDirective parses the arm specific directives
7770 bool ARMAsmParser::ParseDirective(AsmToken DirectiveID) {
7771 StringRef IDVal = DirectiveID.getIdentifier();
7772 if (IDVal == ".word")
7773 return parseDirectiveWord(4, DirectiveID.getLoc());
7774 else if (IDVal == ".thumb")
7775 return parseDirectiveThumb(DirectiveID.getLoc());
7776 else if (IDVal == ".arm")
7777 return parseDirectiveARM(DirectiveID.getLoc());
7778 else if (IDVal == ".thumb_func")
7779 return parseDirectiveThumbFunc(DirectiveID.getLoc());
7780 else if (IDVal == ".code")
7781 return parseDirectiveCode(DirectiveID.getLoc());
7782 else if (IDVal == ".syntax")
7783 return parseDirectiveSyntax(DirectiveID.getLoc());
7784 else if (IDVal == ".unreq")
7785 return parseDirectiveUnreq(DirectiveID.getLoc());
7786 else if (IDVal == ".arch")
7787 return parseDirectiveArch(DirectiveID.getLoc());
7788 else if (IDVal == ".eabi_attribute")
7789 return parseDirectiveEabiAttr(DirectiveID.getLoc());
7790 else if (IDVal == ".cpu")
7791 return parseDirectiveCPU(DirectiveID.getLoc());
7792 else if (IDVal == ".fpu")
7793 return parseDirectiveFPU(DirectiveID.getLoc());
7794 else if (IDVal == ".fnstart")
7795 return parseDirectiveFnStart(DirectiveID.getLoc());
7796 else if (IDVal == ".fnend")
7797 return parseDirectiveFnEnd(DirectiveID.getLoc());
7798 else if (IDVal == ".cantunwind")
7799 return parseDirectiveCantUnwind(DirectiveID.getLoc());
7800 else if (IDVal == ".personality")
7801 return parseDirectivePersonality(DirectiveID.getLoc());
7802 else if (IDVal == ".handlerdata")
7803 return parseDirectiveHandlerData(DirectiveID.getLoc());
7804 else if (IDVal == ".setfp")
7805 return parseDirectiveSetFP(DirectiveID.getLoc());
7806 else if (IDVal == ".pad")
7807 return parseDirectivePad(DirectiveID.getLoc());
7808 else if (IDVal == ".save")
7809 return parseDirectiveRegSave(DirectiveID.getLoc(), false);
7810 else if (IDVal == ".vsave")
7811 return parseDirectiveRegSave(DirectiveID.getLoc(), true);
7815 /// parseDirectiveWord
7816 /// ::= .word [ expression (, expression)* ]
7817 bool ARMAsmParser::parseDirectiveWord(unsigned Size, SMLoc L) {
7818 if (getLexer().isNot(AsmToken::EndOfStatement)) {
7820 const MCExpr *Value;
7821 if (getParser().parseExpression(Value))
7824 getParser().getStreamer().EmitValue(Value, Size);
7826 if (getLexer().is(AsmToken::EndOfStatement))
7829 // FIXME: Improve diagnostic.
7830 if (getLexer().isNot(AsmToken::Comma))
7831 return Error(L, "unexpected token in directive");
7840 /// parseDirectiveThumb
7842 bool ARMAsmParser::parseDirectiveThumb(SMLoc L) {
7843 if (getLexer().isNot(AsmToken::EndOfStatement))
7844 return Error(L, "unexpected token in directive");
7848 return Error(L, "target does not support Thumb mode");
7852 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
7856 /// parseDirectiveARM
7858 bool ARMAsmParser::parseDirectiveARM(SMLoc L) {
7859 if (getLexer().isNot(AsmToken::EndOfStatement))
7860 return Error(L, "unexpected token in directive");
7864 return Error(L, "target does not support ARM mode");
7868 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
7872 void ARMAsmParser::onLabelParsed(MCSymbol *Symbol) {
7873 if (NextSymbolIsThumb) {
7874 getParser().getStreamer().EmitThumbFunc(Symbol);
7875 NextSymbolIsThumb = false;
7879 /// parseDirectiveThumbFunc
7880 /// ::= .thumbfunc symbol_name
7881 bool ARMAsmParser::parseDirectiveThumbFunc(SMLoc L) {
7882 const MCAsmInfo *MAI = getParser().getStreamer().getContext().getAsmInfo();
7883 bool isMachO = MAI->hasSubsectionsViaSymbols();
7885 // Darwin asm has (optionally) function name after .thumb_func direction
7888 const AsmToken &Tok = Parser.getTok();
7889 if (Tok.isNot(AsmToken::EndOfStatement)) {
7890 if (Tok.isNot(AsmToken::Identifier) && Tok.isNot(AsmToken::String))
7891 return Error(L, "unexpected token in .thumb_func directive");
7893 getParser().getContext().GetOrCreateSymbol(Tok.getIdentifier());
7894 getParser().getStreamer().EmitThumbFunc(Func);
7895 Parser.Lex(); // Consume the identifier token.
7900 if (getLexer().isNot(AsmToken::EndOfStatement))
7901 return Error(L, "unexpected token in directive");
7903 NextSymbolIsThumb = true;
7908 /// parseDirectiveSyntax
7909 /// ::= .syntax unified | divided
7910 bool ARMAsmParser::parseDirectiveSyntax(SMLoc L) {
7911 const AsmToken &Tok = Parser.getTok();
7912 if (Tok.isNot(AsmToken::Identifier))
7913 return Error(L, "unexpected token in .syntax directive");
7914 StringRef Mode = Tok.getString();
7915 if (Mode == "unified" || Mode == "UNIFIED")
7917 else if (Mode == "divided" || Mode == "DIVIDED")
7918 return Error(L, "'.syntax divided' arm asssembly not supported");
7920 return Error(L, "unrecognized syntax mode in .syntax directive");
7922 if (getLexer().isNot(AsmToken::EndOfStatement))
7923 return Error(Parser.getTok().getLoc(), "unexpected token in directive");
7926 // TODO tell the MC streamer the mode
7927 // getParser().getStreamer().Emit???();
7931 /// parseDirectiveCode
7932 /// ::= .code 16 | 32
7933 bool ARMAsmParser::parseDirectiveCode(SMLoc L) {
7934 const AsmToken &Tok = Parser.getTok();
7935 if (Tok.isNot(AsmToken::Integer))
7936 return Error(L, "unexpected token in .code directive");
7937 int64_t Val = Parser.getTok().getIntVal();
7943 return Error(L, "invalid operand to .code directive");
7945 if (getLexer().isNot(AsmToken::EndOfStatement))
7946 return Error(Parser.getTok().getLoc(), "unexpected token in directive");
7951 return Error(L, "target does not support Thumb mode");
7955 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
7958 return Error(L, "target does not support ARM mode");
7962 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
7968 /// parseDirectiveReq
7969 /// ::= name .req registername
7970 bool ARMAsmParser::parseDirectiveReq(StringRef Name, SMLoc L) {
7971 Parser.Lex(); // Eat the '.req' token.
7973 SMLoc SRegLoc, ERegLoc;
7974 if (ParseRegister(Reg, SRegLoc, ERegLoc)) {
7975 Parser.eatToEndOfStatement();
7976 return Error(SRegLoc, "register name expected");
7979 // Shouldn't be anything else.
7980 if (Parser.getTok().isNot(AsmToken::EndOfStatement)) {
7981 Parser.eatToEndOfStatement();
7982 return Error(Parser.getTok().getLoc(),
7983 "unexpected input in .req directive.");
7986 Parser.Lex(); // Consume the EndOfStatement
7988 if (RegisterReqs.GetOrCreateValue(Name, Reg).getValue() != Reg)
7989 return Error(SRegLoc, "redefinition of '" + Name +
7990 "' does not match original.");
7995 /// parseDirectiveUneq
7996 /// ::= .unreq registername
7997 bool ARMAsmParser::parseDirectiveUnreq(SMLoc L) {
7998 if (Parser.getTok().isNot(AsmToken::Identifier)) {
7999 Parser.eatToEndOfStatement();
8000 return Error(L, "unexpected input in .unreq directive.");
8002 RegisterReqs.erase(Parser.getTok().getIdentifier());
8003 Parser.Lex(); // Eat the identifier.
8007 /// parseDirectiveArch
8009 bool ARMAsmParser::parseDirectiveArch(SMLoc L) {
8010 StringRef Arch = getParser().parseStringToEndOfStatement().trim();
8012 unsigned ID = StringSwitch<unsigned>(Arch)
8013 #define ARM_ARCH_NAME(NAME, ID, DEFAULT_CPU_NAME, DEFAULT_CPU_ARCH) \
8014 .Case(NAME, ARM::ID)
8015 #include "MCTargetDesc/ARMArchName.def"
8016 .Default(ARM::INVALID_ARCH);
8018 if (ID == ARM::INVALID_ARCH)
8019 return Error(L, "Unknown arch name");
8021 getTargetStreamer().emitArch(ID);
8025 /// parseDirectiveEabiAttr
8026 /// ::= .eabi_attribute int, int
8027 bool ARMAsmParser::parseDirectiveEabiAttr(SMLoc L) {
8028 if (Parser.getTok().isNot(AsmToken::Integer))
8029 return Error(L, "integer expected");
8030 int64_t Tag = Parser.getTok().getIntVal();
8031 Parser.Lex(); // eat tag integer
8033 if (Parser.getTok().isNot(AsmToken::Comma))
8034 return Error(L, "comma expected");
8035 Parser.Lex(); // skip comma
8037 L = Parser.getTok().getLoc();
8038 if (Parser.getTok().isNot(AsmToken::Integer))
8039 return Error(L, "integer expected");
8040 int64_t Value = Parser.getTok().getIntVal();
8041 Parser.Lex(); // eat value integer
8043 getTargetStreamer().emitAttribute(Tag, Value);
8047 /// parseDirectiveCPU
8049 bool ARMAsmParser::parseDirectiveCPU(SMLoc L) {
8050 StringRef CPU = getParser().parseStringToEndOfStatement().trim();
8051 getTargetStreamer().emitTextAttribute(ARMBuildAttrs::CPU_name, CPU);
8055 /// parseDirectiveFPU
8057 bool ARMAsmParser::parseDirectiveFPU(SMLoc L) {
8058 StringRef FPU = getParser().parseStringToEndOfStatement().trim();
8060 unsigned ID = StringSwitch<unsigned>(FPU)
8061 #define ARM_FPU_NAME(NAME, ID) .Case(NAME, ARM::ID)
8062 #include "ARMFPUName.def"
8063 .Default(ARM::INVALID_FPU);
8065 if (ID == ARM::INVALID_FPU)
8066 return Error(L, "Unknown FPU name");
8068 getTargetStreamer().emitFPU(ID);
8072 /// parseDirectiveFnStart
8074 bool ARMAsmParser::parseDirectiveFnStart(SMLoc L) {
8075 if (FnStartLoc.isValid()) {
8076 Error(L, ".fnstart starts before the end of previous one");
8077 Error(FnStartLoc, "previous .fnstart starts here");
8082 getTargetStreamer().emitFnStart();
8086 /// parseDirectiveFnEnd
8088 bool ARMAsmParser::parseDirectiveFnEnd(SMLoc L) {
8089 // Check the ordering of unwind directives
8090 if (!FnStartLoc.isValid())
8091 return Error(L, ".fnstart must precede .fnend directive");
8093 // Reset the unwind directives parser state
8094 resetUnwindDirectiveParserState();
8095 getTargetStreamer().emitFnEnd();
8099 /// parseDirectiveCantUnwind
8101 bool ARMAsmParser::parseDirectiveCantUnwind(SMLoc L) {
8102 // Check the ordering of unwind directives
8104 if (!FnStartLoc.isValid())
8105 return Error(L, ".fnstart must precede .cantunwind directive");
8106 if (HandlerDataLoc.isValid()) {
8107 Error(L, ".cantunwind can't be used with .handlerdata directive");
8108 Error(HandlerDataLoc, ".handlerdata was specified here");
8111 if (PersonalityLoc.isValid()) {
8112 Error(L, ".cantunwind can't be used with .personality directive");
8113 Error(PersonalityLoc, ".personality was specified here");
8117 getTargetStreamer().emitCantUnwind();
8121 /// parseDirectivePersonality
8122 /// ::= .personality name
8123 bool ARMAsmParser::parseDirectivePersonality(SMLoc L) {
8124 // Check the ordering of unwind directives
8126 if (!FnStartLoc.isValid())
8127 return Error(L, ".fnstart must precede .personality directive");
8128 if (CantUnwindLoc.isValid()) {
8129 Error(L, ".personality can't be used with .cantunwind directive");
8130 Error(CantUnwindLoc, ".cantunwind was specified here");
8133 if (HandlerDataLoc.isValid()) {
8134 Error(L, ".personality must precede .handlerdata directive");
8135 Error(HandlerDataLoc, ".handlerdata was specified here");
8139 // Parse the name of the personality routine
8140 if (Parser.getTok().isNot(AsmToken::Identifier)) {
8141 Parser.eatToEndOfStatement();
8142 return Error(L, "unexpected input in .personality directive.");
8144 StringRef Name(Parser.getTok().getIdentifier());
8147 MCSymbol *PR = getParser().getContext().GetOrCreateSymbol(Name);
8148 getTargetStreamer().emitPersonality(PR);
8152 /// parseDirectiveHandlerData
8153 /// ::= .handlerdata
8154 bool ARMAsmParser::parseDirectiveHandlerData(SMLoc L) {
8155 // Check the ordering of unwind directives
8157 if (!FnStartLoc.isValid())
8158 return Error(L, ".fnstart must precede .personality directive");
8159 if (CantUnwindLoc.isValid()) {
8160 Error(L, ".handlerdata can't be used with .cantunwind directive");
8161 Error(CantUnwindLoc, ".cantunwind was specified here");
8165 getTargetStreamer().emitHandlerData();
8169 /// parseDirectiveSetFP
8170 /// ::= .setfp fpreg, spreg [, offset]
8171 bool ARMAsmParser::parseDirectiveSetFP(SMLoc L) {
8172 // Check the ordering of unwind directives
8173 if (!FnStartLoc.isValid())
8174 return Error(L, ".fnstart must precede .setfp directive");
8175 if (HandlerDataLoc.isValid())
8176 return Error(L, ".setfp must precede .handlerdata directive");
8179 SMLoc NewFPRegLoc = Parser.getTok().getLoc();
8180 int NewFPReg = tryParseRegister();
8182 return Error(NewFPRegLoc, "frame pointer register expected");
8185 if (!Parser.getTok().is(AsmToken::Comma))
8186 return Error(Parser.getTok().getLoc(), "comma expected");
8187 Parser.Lex(); // skip comma
8190 SMLoc NewSPRegLoc = Parser.getTok().getLoc();
8191 int NewSPReg = tryParseRegister();
8193 return Error(NewSPRegLoc, "stack pointer register expected");
8195 if (NewSPReg != ARM::SP && NewSPReg != FPReg)
8196 return Error(NewSPRegLoc,
8197 "register should be either $sp or the latest fp register");
8199 // Update the frame pointer register
8204 if (Parser.getTok().is(AsmToken::Comma)) {
8205 Parser.Lex(); // skip comma
8207 if (Parser.getTok().isNot(AsmToken::Hash) &&
8208 Parser.getTok().isNot(AsmToken::Dollar)) {
8209 return Error(Parser.getTok().getLoc(), "'#' expected");
8211 Parser.Lex(); // skip hash token.
8213 const MCExpr *OffsetExpr;
8214 SMLoc ExLoc = Parser.getTok().getLoc();
8216 if (getParser().parseExpression(OffsetExpr, EndLoc))
8217 return Error(ExLoc, "malformed setfp offset");
8218 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr);
8220 return Error(ExLoc, "setfp offset must be an immediate");
8222 Offset = CE->getValue();
8225 getTargetStreamer().emitSetFP(static_cast<unsigned>(NewFPReg),
8226 static_cast<unsigned>(NewSPReg), Offset);
8232 bool ARMAsmParser::parseDirectivePad(SMLoc L) {
8233 // Check the ordering of unwind directives
8234 if (!FnStartLoc.isValid())
8235 return Error(L, ".fnstart must precede .pad directive");
8236 if (HandlerDataLoc.isValid())
8237 return Error(L, ".pad must precede .handlerdata directive");
8240 if (Parser.getTok().isNot(AsmToken::Hash) &&
8241 Parser.getTok().isNot(AsmToken::Dollar)) {
8242 return Error(Parser.getTok().getLoc(), "'#' expected");
8244 Parser.Lex(); // skip hash token.
8246 const MCExpr *OffsetExpr;
8247 SMLoc ExLoc = Parser.getTok().getLoc();
8249 if (getParser().parseExpression(OffsetExpr, EndLoc))
8250 return Error(ExLoc, "malformed pad offset");
8251 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr);
8253 return Error(ExLoc, "pad offset must be an immediate");
8255 getTargetStreamer().emitPad(CE->getValue());
8259 /// parseDirectiveRegSave
8260 /// ::= .save { registers }
8261 /// ::= .vsave { registers }
8262 bool ARMAsmParser::parseDirectiveRegSave(SMLoc L, bool IsVector) {
8263 // Check the ordering of unwind directives
8264 if (!FnStartLoc.isValid())
8265 return Error(L, ".fnstart must precede .save or .vsave directives");
8266 if (HandlerDataLoc.isValid())
8267 return Error(L, ".save or .vsave must precede .handlerdata directive");
8269 // RAII object to make sure parsed operands are deleted.
8270 struct CleanupObject {
8271 SmallVector<MCParsedAsmOperand *, 1> Operands;
8273 for (unsigned I = 0, E = Operands.size(); I != E; ++I)
8278 // Parse the register list
8279 if (parseRegisterList(CO.Operands))
8281 ARMOperand *Op = (ARMOperand*)CO.Operands[0];
8282 if (!IsVector && !Op->isRegList())
8283 return Error(L, ".save expects GPR registers");
8284 if (IsVector && !Op->isDPRRegList())
8285 return Error(L, ".vsave expects DPR registers");
8287 getTargetStreamer().emitRegSave(Op->getRegList(), IsVector);
8291 /// Force static initialization.
8292 extern "C" void LLVMInitializeARMAsmParser() {
8293 RegisterMCAsmParser<ARMAsmParser> X(TheARMTarget);
8294 RegisterMCAsmParser<ARMAsmParser> Y(TheThumbTarget);
8297 #define GET_REGISTER_MATCHER
8298 #define GET_SUBTARGET_FEATURE_NAME
8299 #define GET_MATCHER_IMPLEMENTATION
8300 #include "ARMGenAsmMatcher.inc"
8302 // Define this matcher function after the auto-generated include so we
8303 // have the match class enum definitions.
8304 unsigned ARMAsmParser::validateTargetOperandClass(MCParsedAsmOperand *AsmOp,
8306 ARMOperand *Op = static_cast<ARMOperand*>(AsmOp);
8307 // If the kind is a token for a literal immediate, check if our asm
8308 // operand matches. This is for InstAliases which have a fixed-value
8309 // immediate in the syntax.
8310 if (Kind == MCK__35_0 && Op->isImm()) {
8311 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op->getImm());
8313 return Match_InvalidOperand;
8314 if (CE->getValue() == 0)
8315 return Match_Success;
8317 return Match_InvalidOperand;