1 //===-- ARMAsmParser.cpp - Parse ARM assembly to MCInst instructions ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "llvm/MC/MCTargetAsmParser.h"
11 #include "MCTargetDesc/ARMAddressingModes.h"
12 #include "MCTargetDesc/ARMBaseInfo.h"
13 #include "MCTargetDesc/ARMMCExpr.h"
14 #include "llvm/ADT/BitVector.h"
15 #include "llvm/ADT/OwningPtr.h"
16 #include "llvm/ADT/STLExtras.h"
17 #include "llvm/ADT/SmallVector.h"
18 #include "llvm/ADT/StringSwitch.h"
19 #include "llvm/ADT/Twine.h"
20 #include "llvm/MC/MCAsmInfo.h"
21 #include "llvm/MC/MCAssembler.h"
22 #include "llvm/MC/MCContext.h"
23 #include "llvm/MC/MCELFStreamer.h"
24 #include "llvm/MC/MCExpr.h"
25 #include "llvm/MC/MCInst.h"
26 #include "llvm/MC/MCInstrDesc.h"
27 #include "llvm/MC/MCParser/MCAsmLexer.h"
28 #include "llvm/MC/MCParser/MCAsmParser.h"
29 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
30 #include "llvm/MC/MCRegisterInfo.h"
31 #include "llvm/MC/MCStreamer.h"
32 #include "llvm/MC/MCSubtargetInfo.h"
33 #include "llvm/Support/ELF.h"
34 #include "llvm/Support/MathExtras.h"
35 #include "llvm/Support/SourceMgr.h"
36 #include "llvm/Support/TargetRegistry.h"
37 #include "llvm/Support/raw_ostream.h"
45 enum VectorLaneTy { NoLanes, AllLanes, IndexedLane };
47 class ARMAsmParser : public MCTargetAsmParser {
50 const MCRegisterInfo *MRI;
52 // Map of register aliases registers via the .req directive.
53 StringMap<unsigned> RegisterReqs;
56 ARMCC::CondCodes Cond; // Condition for IT block.
57 unsigned Mask:4; // Condition mask for instructions.
58 // Starting at first 1 (from lsb).
59 // '1' condition as indicated in IT.
60 // '0' inverse of condition (else).
61 // Count of instructions in IT block is
62 // 4 - trailingzeroes(mask)
64 bool FirstCond; // Explicit flag for when we're parsing the
65 // First instruction in the IT block. It's
66 // implied in the mask, so needs special
69 unsigned CurPosition; // Current position in parsing of IT
70 // block. In range [0,3]. Initialized
71 // according to count of instructions in block.
72 // ~0U if no active IT block.
74 bool inITBlock() { return ITState.CurPosition != ~0U;}
75 void forwardITPosition() {
76 if (!inITBlock()) return;
77 // Move to the next instruction in the IT block, if there is one. If not,
78 // mark the block as done.
79 unsigned TZ = CountTrailingZeros_32(ITState.Mask);
80 if (++ITState.CurPosition == 5 - TZ)
81 ITState.CurPosition = ~0U; // Done with the IT block after this.
85 MCAsmParser &getParser() const { return Parser; }
86 MCAsmLexer &getLexer() const { return Parser.getLexer(); }
88 bool Warning(SMLoc L, const Twine &Msg,
89 ArrayRef<SMRange> Ranges = ArrayRef<SMRange>()) {
90 return Parser.Warning(L, Msg, Ranges);
92 bool Error(SMLoc L, const Twine &Msg,
93 ArrayRef<SMRange> Ranges = ArrayRef<SMRange>()) {
94 return Parser.Error(L, Msg, Ranges);
97 int tryParseRegister();
98 bool tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &);
99 int tryParseShiftRegister(SmallVectorImpl<MCParsedAsmOperand*> &);
100 bool parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &);
101 bool parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &);
102 bool parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &, StringRef Mnemonic);
103 bool parsePrefix(ARMMCExpr::VariantKind &RefKind);
104 bool parseMemRegOffsetShift(ARM_AM::ShiftOpc &ShiftType,
105 unsigned &ShiftAmount);
106 bool parseDirectiveWord(unsigned Size, SMLoc L);
107 bool parseDirectiveThumb(SMLoc L);
108 bool parseDirectiveARM(SMLoc L);
109 bool parseDirectiveThumbFunc(SMLoc L);
110 bool parseDirectiveCode(SMLoc L);
111 bool parseDirectiveSyntax(SMLoc L);
112 bool parseDirectiveReq(StringRef Name, SMLoc L);
113 bool parseDirectiveUnreq(SMLoc L);
114 bool parseDirectiveArch(SMLoc L);
115 bool parseDirectiveEabiAttr(SMLoc L);
117 StringRef splitMnemonic(StringRef Mnemonic, unsigned &PredicationCode,
118 bool &CarrySetting, unsigned &ProcessorIMod,
120 void getMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet,
121 bool &CanAcceptPredicationCode);
123 bool isThumb() const {
124 // FIXME: Can tablegen auto-generate this?
125 return (STI.getFeatureBits() & ARM::ModeThumb) != 0;
127 bool isThumbOne() const {
128 return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2) == 0;
130 bool isThumbTwo() const {
131 return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2);
133 bool hasV6Ops() const {
134 return STI.getFeatureBits() & ARM::HasV6Ops;
136 bool hasV7Ops() const {
137 return STI.getFeatureBits() & ARM::HasV7Ops;
140 unsigned FB = ComputeAvailableFeatures(STI.ToggleFeature(ARM::ModeThumb));
141 setAvailableFeatures(FB);
143 bool isMClass() const {
144 return STI.getFeatureBits() & ARM::FeatureMClass;
147 /// @name Auto-generated Match Functions
150 #define GET_ASSEMBLER_HEADER
151 #include "ARMGenAsmMatcher.inc"
155 OperandMatchResultTy parseITCondCode(SmallVectorImpl<MCParsedAsmOperand*>&);
156 OperandMatchResultTy parseCoprocNumOperand(
157 SmallVectorImpl<MCParsedAsmOperand*>&);
158 OperandMatchResultTy parseCoprocRegOperand(
159 SmallVectorImpl<MCParsedAsmOperand*>&);
160 OperandMatchResultTy parseCoprocOptionOperand(
161 SmallVectorImpl<MCParsedAsmOperand*>&);
162 OperandMatchResultTy parseMemBarrierOptOperand(
163 SmallVectorImpl<MCParsedAsmOperand*>&);
164 OperandMatchResultTy parseProcIFlagsOperand(
165 SmallVectorImpl<MCParsedAsmOperand*>&);
166 OperandMatchResultTy parseMSRMaskOperand(
167 SmallVectorImpl<MCParsedAsmOperand*>&);
168 OperandMatchResultTy parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &O,
169 StringRef Op, int Low, int High);
170 OperandMatchResultTy parsePKHLSLImm(SmallVectorImpl<MCParsedAsmOperand*> &O) {
171 return parsePKHImm(O, "lsl", 0, 31);
173 OperandMatchResultTy parsePKHASRImm(SmallVectorImpl<MCParsedAsmOperand*> &O) {
174 return parsePKHImm(O, "asr", 1, 32);
176 OperandMatchResultTy parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*>&);
177 OperandMatchResultTy parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*>&);
178 OperandMatchResultTy parseRotImm(SmallVectorImpl<MCParsedAsmOperand*>&);
179 OperandMatchResultTy parseBitfield(SmallVectorImpl<MCParsedAsmOperand*>&);
180 OperandMatchResultTy parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*>&);
181 OperandMatchResultTy parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*>&);
182 OperandMatchResultTy parseFPImm(SmallVectorImpl<MCParsedAsmOperand*>&);
183 OperandMatchResultTy parseVectorList(SmallVectorImpl<MCParsedAsmOperand*>&);
184 OperandMatchResultTy parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index,
187 // Asm Match Converter Methods
188 void cvtT2LdrdPre(MCInst &Inst, const SmallVectorImpl<MCParsedAsmOperand*> &);
189 void cvtT2StrdPre(MCInst &Inst, const SmallVectorImpl<MCParsedAsmOperand*> &);
190 void cvtLdWriteBackRegT2AddrModeImm8(MCInst &Inst,
191 const SmallVectorImpl<MCParsedAsmOperand*> &);
192 void cvtStWriteBackRegT2AddrModeImm8(MCInst &Inst,
193 const SmallVectorImpl<MCParsedAsmOperand*> &);
194 void cvtLdWriteBackRegAddrMode2(MCInst &Inst,
195 const SmallVectorImpl<MCParsedAsmOperand*> &);
196 void cvtLdWriteBackRegAddrModeImm12(MCInst &Inst,
197 const SmallVectorImpl<MCParsedAsmOperand*> &);
198 void cvtStWriteBackRegAddrModeImm12(MCInst &Inst,
199 const SmallVectorImpl<MCParsedAsmOperand*> &);
200 void cvtStWriteBackRegAddrMode2(MCInst &Inst,
201 const SmallVectorImpl<MCParsedAsmOperand*> &);
202 void cvtStWriteBackRegAddrMode3(MCInst &Inst,
203 const SmallVectorImpl<MCParsedAsmOperand*> &);
204 void cvtLdExtTWriteBackImm(MCInst &Inst,
205 const SmallVectorImpl<MCParsedAsmOperand*> &);
206 void cvtLdExtTWriteBackReg(MCInst &Inst,
207 const SmallVectorImpl<MCParsedAsmOperand*> &);
208 void cvtStExtTWriteBackImm(MCInst &Inst,
209 const SmallVectorImpl<MCParsedAsmOperand*> &);
210 void cvtStExtTWriteBackReg(MCInst &Inst,
211 const SmallVectorImpl<MCParsedAsmOperand*> &);
212 void cvtLdrdPre(MCInst &Inst, const SmallVectorImpl<MCParsedAsmOperand*> &);
213 void cvtStrdPre(MCInst &Inst, const SmallVectorImpl<MCParsedAsmOperand*> &);
214 void cvtLdWriteBackRegAddrMode3(MCInst &Inst,
215 const SmallVectorImpl<MCParsedAsmOperand*> &);
216 void cvtThumbMultiply(MCInst &Inst,
217 const SmallVectorImpl<MCParsedAsmOperand*> &);
218 void cvtVLDwbFixed(MCInst &Inst,
219 const SmallVectorImpl<MCParsedAsmOperand*> &);
220 void cvtVLDwbRegister(MCInst &Inst,
221 const SmallVectorImpl<MCParsedAsmOperand*> &);
222 void cvtVSTwbFixed(MCInst &Inst,
223 const SmallVectorImpl<MCParsedAsmOperand*> &);
224 void cvtVSTwbRegister(MCInst &Inst,
225 const SmallVectorImpl<MCParsedAsmOperand*> &);
226 bool validateInstruction(MCInst &Inst,
227 const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
228 bool processInstruction(MCInst &Inst,
229 const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
230 bool shouldOmitCCOutOperand(StringRef Mnemonic,
231 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
234 enum ARMMatchResultTy {
235 Match_RequiresITBlock = FIRST_TARGET_MATCH_RESULT_TY,
236 Match_RequiresNotITBlock,
238 Match_RequiresThumb2,
239 #define GET_OPERAND_DIAGNOSTIC_TYPES
240 #include "ARMGenAsmMatcher.inc"
244 ARMAsmParser(MCSubtargetInfo &_STI, MCAsmParser &_Parser)
245 : MCTargetAsmParser(), STI(_STI), Parser(_Parser) {
246 MCAsmParserExtension::Initialize(_Parser);
248 // Cache the MCRegisterInfo.
249 MRI = &getContext().getRegisterInfo();
251 // Initialize the set of available features.
252 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
254 // Not in an ITBlock to start with.
255 ITState.CurPosition = ~0U;
257 // Set ELF header flags.
258 // FIXME: This should eventually end up somewhere else where more
259 // intelligent flag decisions can be made. For now we are just maintaining
260 // the statu/parseDirects quo for ARM and setting EF_ARM_EABI_VER5 as the default.
261 if (MCELFStreamer *MES = dyn_cast<MCELFStreamer>(&Parser.getStreamer()))
262 MES->getAssembler().setELFHeaderEFlags(ELF::EF_ARM_EABI_VER5);
265 // Implementation of the MCTargetAsmParser interface:
266 bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc);
267 bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
269 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
270 bool ParseDirective(AsmToken DirectiveID);
272 unsigned validateTargetOperandClass(MCParsedAsmOperand *Op, unsigned Kind);
273 unsigned checkTargetMatchPredicate(MCInst &Inst);
275 bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
276 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
277 MCStreamer &Out, unsigned &ErrorInfo,
278 bool MatchingInlineAsm);
280 } // end anonymous namespace
284 /// ARMOperand - Instances of this class represent a parsed ARM machine
286 class ARMOperand : public MCParsedAsmOperand {
306 k_VectorListAllLanes,
312 k_BitfieldDescriptor,
316 SMLoc StartLoc, EndLoc;
317 SmallVector<unsigned, 8> Registers;
320 ARMCC::CondCodes Val;
327 struct CoprocOptionOp {
340 ARM_PROC::IFlags Val;
356 // A vector register list is a sequential list of 1 to 4 registers.
357 struct VectorListOp {
364 struct VectorIndexOp {
372 /// Combined record for all forms of ARM address expressions.
375 // Offset is in OffsetReg or OffsetImm. If both are zero, no offset
377 const MCConstantExpr *OffsetImm; // Offset immediate value
378 unsigned OffsetRegNum; // Offset register num, when OffsetImm == NULL
379 ARM_AM::ShiftOpc ShiftType; // Shift type for OffsetReg
380 unsigned ShiftImm; // shift for OffsetReg.
381 unsigned Alignment; // 0 = no alignment specified
382 // n = alignment in bytes (2, 4, 8, 16, or 32)
383 unsigned isNegative : 1; // Negated OffsetReg? (~'U' bit)
386 struct PostIdxRegOp {
389 ARM_AM::ShiftOpc ShiftTy;
393 struct ShifterImmOp {
398 struct RegShiftedRegOp {
399 ARM_AM::ShiftOpc ShiftTy;
405 struct RegShiftedImmOp {
406 ARM_AM::ShiftOpc ShiftTy;
423 struct CoprocOptionOp CoprocOption;
424 struct MBOptOp MBOpt;
425 struct ITMaskOp ITMask;
426 struct IFlagsOp IFlags;
427 struct MMaskOp MMask;
430 struct VectorListOp VectorList;
431 struct VectorIndexOp VectorIndex;
433 struct MemoryOp Memory;
434 struct PostIdxRegOp PostIdxReg;
435 struct ShifterImmOp ShifterImm;
436 struct RegShiftedRegOp RegShiftedReg;
437 struct RegShiftedImmOp RegShiftedImm;
438 struct RotImmOp RotImm;
439 struct BitfieldOp Bitfield;
442 ARMOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
444 ARMOperand(const ARMOperand &o) : MCParsedAsmOperand() {
446 StartLoc = o.StartLoc;
463 case k_DPRRegisterList:
464 case k_SPRRegisterList:
465 Registers = o.Registers;
468 case k_VectorListAllLanes:
469 case k_VectorListIndexed:
470 VectorList = o.VectorList;
477 CoprocOption = o.CoprocOption;
482 case k_MemBarrierOpt:
488 case k_PostIndexRegister:
489 PostIdxReg = o.PostIdxReg;
497 case k_ShifterImmediate:
498 ShifterImm = o.ShifterImm;
500 case k_ShiftedRegister:
501 RegShiftedReg = o.RegShiftedReg;
503 case k_ShiftedImmediate:
504 RegShiftedImm = o.RegShiftedImm;
506 case k_RotateImmediate:
509 case k_BitfieldDescriptor:
510 Bitfield = o.Bitfield;
513 VectorIndex = o.VectorIndex;
518 /// getStartLoc - Get the location of the first token of this operand.
519 SMLoc getStartLoc() const { return StartLoc; }
520 /// getEndLoc - Get the location of the last token of this operand.
521 SMLoc getEndLoc() const { return EndLoc; }
522 /// getLocRange - Get the range between the first and last token of this
524 SMRange getLocRange() const { return SMRange(StartLoc, EndLoc); }
526 ARMCC::CondCodes getCondCode() const {
527 assert(Kind == k_CondCode && "Invalid access!");
531 unsigned getCoproc() const {
532 assert((Kind == k_CoprocNum || Kind == k_CoprocReg) && "Invalid access!");
536 StringRef getToken() const {
537 assert(Kind == k_Token && "Invalid access!");
538 return StringRef(Tok.Data, Tok.Length);
541 unsigned getReg() const {
542 assert((Kind == k_Register || Kind == k_CCOut) && "Invalid access!");
546 const SmallVectorImpl<unsigned> &getRegList() const {
547 assert((Kind == k_RegisterList || Kind == k_DPRRegisterList ||
548 Kind == k_SPRRegisterList) && "Invalid access!");
552 const MCExpr *getImm() const {
553 assert(isImm() && "Invalid access!");
557 unsigned getVectorIndex() const {
558 assert(Kind == k_VectorIndex && "Invalid access!");
559 return VectorIndex.Val;
562 ARM_MB::MemBOpt getMemBarrierOpt() const {
563 assert(Kind == k_MemBarrierOpt && "Invalid access!");
567 ARM_PROC::IFlags getProcIFlags() const {
568 assert(Kind == k_ProcIFlags && "Invalid access!");
572 unsigned getMSRMask() const {
573 assert(Kind == k_MSRMask && "Invalid access!");
577 bool isCoprocNum() const { return Kind == k_CoprocNum; }
578 bool isCoprocReg() const { return Kind == k_CoprocReg; }
579 bool isCoprocOption() const { return Kind == k_CoprocOption; }
580 bool isCondCode() const { return Kind == k_CondCode; }
581 bool isCCOut() const { return Kind == k_CCOut; }
582 bool isITMask() const { return Kind == k_ITCondMask; }
583 bool isITCondCode() const { return Kind == k_CondCode; }
584 bool isImm() const { return Kind == k_Immediate; }
585 bool isFPImm() const {
586 if (!isImm()) return false;
587 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
588 if (!CE) return false;
589 int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue()));
592 bool isFBits16() const {
593 if (!isImm()) return false;
594 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
595 if (!CE) return false;
596 int64_t Value = CE->getValue();
597 return Value >= 0 && Value <= 16;
599 bool isFBits32() const {
600 if (!isImm()) return false;
601 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
602 if (!CE) return false;
603 int64_t Value = CE->getValue();
604 return Value >= 1 && Value <= 32;
606 bool isImm8s4() const {
607 if (!isImm()) return false;
608 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
609 if (!CE) return false;
610 int64_t Value = CE->getValue();
611 return ((Value & 3) == 0) && Value >= -1020 && Value <= 1020;
613 bool isImm0_1020s4() const {
614 if (!isImm()) return false;
615 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
616 if (!CE) return false;
617 int64_t Value = CE->getValue();
618 return ((Value & 3) == 0) && Value >= 0 && Value <= 1020;
620 bool isImm0_508s4() const {
621 if (!isImm()) return false;
622 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
623 if (!CE) return false;
624 int64_t Value = CE->getValue();
625 return ((Value & 3) == 0) && Value >= 0 && Value <= 508;
627 bool isImm0_508s4Neg() const {
628 if (!isImm()) return false;
629 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
630 if (!CE) return false;
631 int64_t Value = -CE->getValue();
632 // explicitly exclude zero. we want that to use the normal 0_508 version.
633 return ((Value & 3) == 0) && Value > 0 && Value <= 508;
635 bool isImm0_255() const {
636 if (!isImm()) return false;
637 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
638 if (!CE) return false;
639 int64_t Value = CE->getValue();
640 return Value >= 0 && Value < 256;
642 bool isImm0_4095() const {
643 if (!isImm()) return false;
644 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
645 if (!CE) return false;
646 int64_t Value = CE->getValue();
647 return Value >= 0 && Value < 4096;
649 bool isImm0_4095Neg() const {
650 if (!isImm()) return false;
651 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
652 if (!CE) return false;
653 int64_t Value = -CE->getValue();
654 return Value > 0 && Value < 4096;
656 bool isImm0_1() const {
657 if (!isImm()) return false;
658 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
659 if (!CE) return false;
660 int64_t Value = CE->getValue();
661 return Value >= 0 && Value < 2;
663 bool isImm0_3() const {
664 if (!isImm()) return false;
665 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
666 if (!CE) return false;
667 int64_t Value = CE->getValue();
668 return Value >= 0 && Value < 4;
670 bool isImm0_7() const {
671 if (!isImm()) return false;
672 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
673 if (!CE) return false;
674 int64_t Value = CE->getValue();
675 return Value >= 0 && Value < 8;
677 bool isImm0_15() const {
678 if (!isImm()) return false;
679 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
680 if (!CE) return false;
681 int64_t Value = CE->getValue();
682 return Value >= 0 && Value < 16;
684 bool isImm0_31() const {
685 if (!isImm()) return false;
686 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
687 if (!CE) return false;
688 int64_t Value = CE->getValue();
689 return Value >= 0 && Value < 32;
691 bool isImm0_63() const {
692 if (!isImm()) return false;
693 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
694 if (!CE) return false;
695 int64_t Value = CE->getValue();
696 return Value >= 0 && Value < 64;
698 bool isImm8() const {
699 if (!isImm()) return false;
700 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
701 if (!CE) return false;
702 int64_t Value = CE->getValue();
705 bool isImm16() const {
706 if (!isImm()) return false;
707 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
708 if (!CE) return false;
709 int64_t Value = CE->getValue();
712 bool isImm32() const {
713 if (!isImm()) return false;
714 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
715 if (!CE) return false;
716 int64_t Value = CE->getValue();
719 bool isShrImm8() const {
720 if (!isImm()) return false;
721 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
722 if (!CE) return false;
723 int64_t Value = CE->getValue();
724 return Value > 0 && Value <= 8;
726 bool isShrImm16() const {
727 if (!isImm()) return false;
728 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
729 if (!CE) return false;
730 int64_t Value = CE->getValue();
731 return Value > 0 && Value <= 16;
733 bool isShrImm32() const {
734 if (!isImm()) return false;
735 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
736 if (!CE) return false;
737 int64_t Value = CE->getValue();
738 return Value > 0 && Value <= 32;
740 bool isShrImm64() const {
741 if (!isImm()) return false;
742 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
743 if (!CE) return false;
744 int64_t Value = CE->getValue();
745 return Value > 0 && Value <= 64;
747 bool isImm1_7() const {
748 if (!isImm()) return false;
749 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
750 if (!CE) return false;
751 int64_t Value = CE->getValue();
752 return Value > 0 && Value < 8;
754 bool isImm1_15() const {
755 if (!isImm()) return false;
756 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
757 if (!CE) return false;
758 int64_t Value = CE->getValue();
759 return Value > 0 && Value < 16;
761 bool isImm1_31() const {
762 if (!isImm()) return false;
763 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
764 if (!CE) return false;
765 int64_t Value = CE->getValue();
766 return Value > 0 && Value < 32;
768 bool isImm1_16() const {
769 if (!isImm()) return false;
770 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
771 if (!CE) return false;
772 int64_t Value = CE->getValue();
773 return Value > 0 && Value < 17;
775 bool isImm1_32() const {
776 if (!isImm()) return false;
777 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
778 if (!CE) return false;
779 int64_t Value = CE->getValue();
780 return Value > 0 && Value < 33;
782 bool isImm0_32() const {
783 if (!isImm()) return false;
784 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
785 if (!CE) return false;
786 int64_t Value = CE->getValue();
787 return Value >= 0 && Value < 33;
789 bool isImm0_65535() const {
790 if (!isImm()) return false;
791 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
792 if (!CE) return false;
793 int64_t Value = CE->getValue();
794 return Value >= 0 && Value < 65536;
796 bool isImm0_65535Expr() const {
797 if (!isImm()) return false;
798 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
799 // If it's not a constant expression, it'll generate a fixup and be
801 if (!CE) return true;
802 int64_t Value = CE->getValue();
803 return Value >= 0 && Value < 65536;
805 bool isImm24bit() const {
806 if (!isImm()) return false;
807 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
808 if (!CE) return false;
809 int64_t Value = CE->getValue();
810 return Value >= 0 && Value <= 0xffffff;
812 bool isImmThumbSR() const {
813 if (!isImm()) return false;
814 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
815 if (!CE) return false;
816 int64_t Value = CE->getValue();
817 return Value > 0 && Value < 33;
819 bool isPKHLSLImm() const {
820 if (!isImm()) return false;
821 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
822 if (!CE) return false;
823 int64_t Value = CE->getValue();
824 return Value >= 0 && Value < 32;
826 bool isPKHASRImm() const {
827 if (!isImm()) return false;
828 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
829 if (!CE) return false;
830 int64_t Value = CE->getValue();
831 return Value > 0 && Value <= 32;
833 bool isAdrLabel() const {
834 // If we have an immediate that's not a constant, treat it as a label
835 // reference needing a fixup. If it is a constant, but it can't fit
836 // into shift immediate encoding, we reject it.
837 if (isImm() && !isa<MCConstantExpr>(getImm())) return true;
838 else return (isARMSOImm() || isARMSOImmNeg());
840 bool isARMSOImm() const {
841 if (!isImm()) return false;
842 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
843 if (!CE) return false;
844 int64_t Value = CE->getValue();
845 return ARM_AM::getSOImmVal(Value) != -1;
847 bool isARMSOImmNot() const {
848 if (!isImm()) return false;
849 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
850 if (!CE) return false;
851 int64_t Value = CE->getValue();
852 return ARM_AM::getSOImmVal(~Value) != -1;
854 bool isARMSOImmNeg() const {
855 if (!isImm()) return false;
856 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
857 if (!CE) return false;
858 int64_t Value = CE->getValue();
859 // Only use this when not representable as a plain so_imm.
860 return ARM_AM::getSOImmVal(Value) == -1 &&
861 ARM_AM::getSOImmVal(-Value) != -1;
863 bool isT2SOImm() const {
864 if (!isImm()) return false;
865 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
866 if (!CE) return false;
867 int64_t Value = CE->getValue();
868 return ARM_AM::getT2SOImmVal(Value) != -1;
870 bool isT2SOImmNot() const {
871 if (!isImm()) return false;
872 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
873 if (!CE) return false;
874 int64_t Value = CE->getValue();
875 return ARM_AM::getT2SOImmVal(~Value) != -1;
877 bool isT2SOImmNeg() const {
878 if (!isImm()) return false;
879 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
880 if (!CE) return false;
881 int64_t Value = CE->getValue();
882 // Only use this when not representable as a plain so_imm.
883 return ARM_AM::getT2SOImmVal(Value) == -1 &&
884 ARM_AM::getT2SOImmVal(-Value) != -1;
886 bool isSetEndImm() const {
887 if (!isImm()) return false;
888 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
889 if (!CE) return false;
890 int64_t Value = CE->getValue();
891 return Value == 1 || Value == 0;
893 bool isReg() const { return Kind == k_Register; }
894 bool isRegList() const { return Kind == k_RegisterList; }
895 bool isDPRRegList() const { return Kind == k_DPRRegisterList; }
896 bool isSPRRegList() const { return Kind == k_SPRRegisterList; }
897 bool isToken() const { return Kind == k_Token; }
898 bool isMemBarrierOpt() const { return Kind == k_MemBarrierOpt; }
899 bool isMem() const { return Kind == k_Memory; }
900 bool isShifterImm() const { return Kind == k_ShifterImmediate; }
901 bool isRegShiftedReg() const { return Kind == k_ShiftedRegister; }
902 bool isRegShiftedImm() const { return Kind == k_ShiftedImmediate; }
903 bool isRotImm() const { return Kind == k_RotateImmediate; }
904 bool isBitfield() const { return Kind == k_BitfieldDescriptor; }
905 bool isPostIdxRegShifted() const { return Kind == k_PostIndexRegister; }
906 bool isPostIdxReg() const {
907 return Kind == k_PostIndexRegister && PostIdxReg.ShiftTy ==ARM_AM::no_shift;
909 bool isMemNoOffset(bool alignOK = false) const {
912 // No offset of any kind.
913 return Memory.OffsetRegNum == 0 && Memory.OffsetImm == 0 &&
914 (alignOK || Memory.Alignment == 0);
916 bool isMemPCRelImm12() const {
917 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
919 // Base register must be PC.
920 if (Memory.BaseRegNum != ARM::PC)
922 // Immediate offset in range [-4095, 4095].
923 if (!Memory.OffsetImm) return true;
924 int64_t Val = Memory.OffsetImm->getValue();
925 return (Val > -4096 && Val < 4096) || (Val == INT32_MIN);
927 bool isAlignedMemory() const {
928 return isMemNoOffset(true);
930 bool isAddrMode2() const {
931 if (!isMem() || Memory.Alignment != 0) return false;
932 // Check for register offset.
933 if (Memory.OffsetRegNum) return true;
934 // Immediate offset in range [-4095, 4095].
935 if (!Memory.OffsetImm) return true;
936 int64_t Val = Memory.OffsetImm->getValue();
937 return Val > -4096 && Val < 4096;
939 bool isAM2OffsetImm() const {
940 if (!isImm()) return false;
941 // Immediate offset in range [-4095, 4095].
942 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
943 if (!CE) return false;
944 int64_t Val = CE->getValue();
945 return Val > -4096 && Val < 4096;
947 bool isAddrMode3() const {
948 // If we have an immediate that's not a constant, treat it as a label
949 // reference needing a fixup. If it is a constant, it's something else
951 if (isImm() && !isa<MCConstantExpr>(getImm()))
953 if (!isMem() || Memory.Alignment != 0) return false;
954 // No shifts are legal for AM3.
955 if (Memory.ShiftType != ARM_AM::no_shift) return false;
956 // Check for register offset.
957 if (Memory.OffsetRegNum) return true;
958 // Immediate offset in range [-255, 255].
959 if (!Memory.OffsetImm) return true;
960 int64_t Val = Memory.OffsetImm->getValue();
961 // The #-0 offset is encoded as INT32_MIN, and we have to check
963 return (Val > -256 && Val < 256) || Val == INT32_MIN;
965 bool isAM3Offset() const {
966 if (Kind != k_Immediate && Kind != k_PostIndexRegister)
968 if (Kind == k_PostIndexRegister)
969 return PostIdxReg.ShiftTy == ARM_AM::no_shift;
970 // Immediate offset in range [-255, 255].
971 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
972 if (!CE) return false;
973 int64_t Val = CE->getValue();
974 // Special case, #-0 is INT32_MIN.
975 return (Val > -256 && Val < 256) || Val == INT32_MIN;
977 bool isAddrMode5() const {
978 // If we have an immediate that's not a constant, treat it as a label
979 // reference needing a fixup. If it is a constant, it's something else
981 if (isImm() && !isa<MCConstantExpr>(getImm()))
983 if (!isMem() || Memory.Alignment != 0) return false;
984 // Check for register offset.
985 if (Memory.OffsetRegNum) return false;
986 // Immediate offset in range [-1020, 1020] and a multiple of 4.
987 if (!Memory.OffsetImm) return true;
988 int64_t Val = Memory.OffsetImm->getValue();
989 return (Val >= -1020 && Val <= 1020 && ((Val & 3) == 0)) ||
992 bool isMemTBB() const {
993 if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
994 Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0)
998 bool isMemTBH() const {
999 if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1000 Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm != 1 ||
1001 Memory.Alignment != 0 )
1005 bool isMemRegOffset() const {
1006 if (!isMem() || !Memory.OffsetRegNum || Memory.Alignment != 0)
1010 bool isT2MemRegOffset() const {
1011 if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1012 Memory.Alignment != 0)
1014 // Only lsl #{0, 1, 2, 3} allowed.
1015 if (Memory.ShiftType == ARM_AM::no_shift)
1017 if (Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm > 3)
1021 bool isMemThumbRR() const {
1022 // Thumb reg+reg addressing is simple. Just two registers, a base and
1023 // an offset. No shifts, negations or any other complicating factors.
1024 if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1025 Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0)
1027 return isARMLowRegister(Memory.BaseRegNum) &&
1028 (!Memory.OffsetRegNum || isARMLowRegister(Memory.OffsetRegNum));
1030 bool isMemThumbRIs4() const {
1031 if (!isMem() || Memory.OffsetRegNum != 0 ||
1032 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
1034 // Immediate offset, multiple of 4 in range [0, 124].
1035 if (!Memory.OffsetImm) return true;
1036 int64_t Val = Memory.OffsetImm->getValue();
1037 return Val >= 0 && Val <= 124 && (Val % 4) == 0;
1039 bool isMemThumbRIs2() const {
1040 if (!isMem() || Memory.OffsetRegNum != 0 ||
1041 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
1043 // Immediate offset, multiple of 4 in range [0, 62].
1044 if (!Memory.OffsetImm) return true;
1045 int64_t Val = Memory.OffsetImm->getValue();
1046 return Val >= 0 && Val <= 62 && (Val % 2) == 0;
1048 bool isMemThumbRIs1() const {
1049 if (!isMem() || Memory.OffsetRegNum != 0 ||
1050 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
1052 // Immediate offset in range [0, 31].
1053 if (!Memory.OffsetImm) return true;
1054 int64_t Val = Memory.OffsetImm->getValue();
1055 return Val >= 0 && Val <= 31;
1057 bool isMemThumbSPI() const {
1058 if (!isMem() || Memory.OffsetRegNum != 0 ||
1059 Memory.BaseRegNum != ARM::SP || Memory.Alignment != 0)
1061 // Immediate offset, multiple of 4 in range [0, 1020].
1062 if (!Memory.OffsetImm) return true;
1063 int64_t Val = Memory.OffsetImm->getValue();
1064 return Val >= 0 && Val <= 1020 && (Val % 4) == 0;
1066 bool isMemImm8s4Offset() const {
1067 // If we have an immediate that's not a constant, treat it as a label
1068 // reference needing a fixup. If it is a constant, it's something else
1069 // and we reject it.
1070 if (isImm() && !isa<MCConstantExpr>(getImm()))
1072 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1074 // Immediate offset a multiple of 4 in range [-1020, 1020].
1075 if (!Memory.OffsetImm) return true;
1076 int64_t Val = Memory.OffsetImm->getValue();
1077 // Special case, #-0 is INT32_MIN.
1078 return (Val >= -1020 && Val <= 1020 && (Val & 3) == 0) || Val == INT32_MIN;
1080 bool isMemImm0_1020s4Offset() const {
1081 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1083 // Immediate offset a multiple of 4 in range [0, 1020].
1084 if (!Memory.OffsetImm) return true;
1085 int64_t Val = Memory.OffsetImm->getValue();
1086 return Val >= 0 && Val <= 1020 && (Val & 3) == 0;
1088 bool isMemImm8Offset() const {
1089 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1091 // Base reg of PC isn't allowed for these encodings.
1092 if (Memory.BaseRegNum == ARM::PC) return false;
1093 // Immediate offset in range [-255, 255].
1094 if (!Memory.OffsetImm) return true;
1095 int64_t Val = Memory.OffsetImm->getValue();
1096 return (Val == INT32_MIN) || (Val > -256 && Val < 256);
1098 bool isMemPosImm8Offset() const {
1099 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1101 // Immediate offset in range [0, 255].
1102 if (!Memory.OffsetImm) return true;
1103 int64_t Val = Memory.OffsetImm->getValue();
1104 return Val >= 0 && Val < 256;
1106 bool isMemNegImm8Offset() const {
1107 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1109 // Base reg of PC isn't allowed for these encodings.
1110 if (Memory.BaseRegNum == ARM::PC) return false;
1111 // Immediate offset in range [-255, -1].
1112 if (!Memory.OffsetImm) return false;
1113 int64_t Val = Memory.OffsetImm->getValue();
1114 return (Val == INT32_MIN) || (Val > -256 && Val < 0);
1116 bool isMemUImm12Offset() const {
1117 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1119 // Immediate offset in range [0, 4095].
1120 if (!Memory.OffsetImm) return true;
1121 int64_t Val = Memory.OffsetImm->getValue();
1122 return (Val >= 0 && Val < 4096);
1124 bool isMemImm12Offset() const {
1125 // If we have an immediate that's not a constant, treat it as a label
1126 // reference needing a fixup. If it is a constant, it's something else
1127 // and we reject it.
1128 if (isImm() && !isa<MCConstantExpr>(getImm()))
1131 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1133 // Immediate offset in range [-4095, 4095].
1134 if (!Memory.OffsetImm) return true;
1135 int64_t Val = Memory.OffsetImm->getValue();
1136 return (Val > -4096 && Val < 4096) || (Val == INT32_MIN);
1138 bool isPostIdxImm8() const {
1139 if (!isImm()) return false;
1140 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1141 if (!CE) return false;
1142 int64_t Val = CE->getValue();
1143 return (Val > -256 && Val < 256) || (Val == INT32_MIN);
1145 bool isPostIdxImm8s4() const {
1146 if (!isImm()) return false;
1147 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1148 if (!CE) return false;
1149 int64_t Val = CE->getValue();
1150 return ((Val & 3) == 0 && Val >= -1020 && Val <= 1020) ||
1154 bool isMSRMask() const { return Kind == k_MSRMask; }
1155 bool isProcIFlags() const { return Kind == k_ProcIFlags; }
1158 bool isSingleSpacedVectorList() const {
1159 return Kind == k_VectorList && !VectorList.isDoubleSpaced;
1161 bool isDoubleSpacedVectorList() const {
1162 return Kind == k_VectorList && VectorList.isDoubleSpaced;
1164 bool isVecListOneD() const {
1165 if (!isSingleSpacedVectorList()) return false;
1166 return VectorList.Count == 1;
1169 bool isVecListDPair() const {
1170 if (!isSingleSpacedVectorList()) return false;
1171 return (ARMMCRegisterClasses[ARM::DPairRegClassID]
1172 .contains(VectorList.RegNum));
1175 bool isVecListThreeD() const {
1176 if (!isSingleSpacedVectorList()) return false;
1177 return VectorList.Count == 3;
1180 bool isVecListFourD() const {
1181 if (!isSingleSpacedVectorList()) return false;
1182 return VectorList.Count == 4;
1185 bool isVecListDPairSpaced() const {
1186 if (isSingleSpacedVectorList()) return false;
1187 return (ARMMCRegisterClasses[ARM::DPairSpcRegClassID]
1188 .contains(VectorList.RegNum));
1191 bool isVecListThreeQ() const {
1192 if (!isDoubleSpacedVectorList()) return false;
1193 return VectorList.Count == 3;
1196 bool isVecListFourQ() const {
1197 if (!isDoubleSpacedVectorList()) return false;
1198 return VectorList.Count == 4;
1201 bool isSingleSpacedVectorAllLanes() const {
1202 return Kind == k_VectorListAllLanes && !VectorList.isDoubleSpaced;
1204 bool isDoubleSpacedVectorAllLanes() const {
1205 return Kind == k_VectorListAllLanes && VectorList.isDoubleSpaced;
1207 bool isVecListOneDAllLanes() const {
1208 if (!isSingleSpacedVectorAllLanes()) return false;
1209 return VectorList.Count == 1;
1212 bool isVecListDPairAllLanes() const {
1213 if (!isSingleSpacedVectorAllLanes()) return false;
1214 return (ARMMCRegisterClasses[ARM::DPairRegClassID]
1215 .contains(VectorList.RegNum));
1218 bool isVecListDPairSpacedAllLanes() const {
1219 if (!isDoubleSpacedVectorAllLanes()) return false;
1220 return VectorList.Count == 2;
1223 bool isVecListThreeDAllLanes() const {
1224 if (!isSingleSpacedVectorAllLanes()) return false;
1225 return VectorList.Count == 3;
1228 bool isVecListThreeQAllLanes() const {
1229 if (!isDoubleSpacedVectorAllLanes()) return false;
1230 return VectorList.Count == 3;
1233 bool isVecListFourDAllLanes() const {
1234 if (!isSingleSpacedVectorAllLanes()) return false;
1235 return VectorList.Count == 4;
1238 bool isVecListFourQAllLanes() const {
1239 if (!isDoubleSpacedVectorAllLanes()) return false;
1240 return VectorList.Count == 4;
1243 bool isSingleSpacedVectorIndexed() const {
1244 return Kind == k_VectorListIndexed && !VectorList.isDoubleSpaced;
1246 bool isDoubleSpacedVectorIndexed() const {
1247 return Kind == k_VectorListIndexed && VectorList.isDoubleSpaced;
1249 bool isVecListOneDByteIndexed() const {
1250 if (!isSingleSpacedVectorIndexed()) return false;
1251 return VectorList.Count == 1 && VectorList.LaneIndex <= 7;
1254 bool isVecListOneDHWordIndexed() const {
1255 if (!isSingleSpacedVectorIndexed()) return false;
1256 return VectorList.Count == 1 && VectorList.LaneIndex <= 3;
1259 bool isVecListOneDWordIndexed() const {
1260 if (!isSingleSpacedVectorIndexed()) return false;
1261 return VectorList.Count == 1 && VectorList.LaneIndex <= 1;
1264 bool isVecListTwoDByteIndexed() const {
1265 if (!isSingleSpacedVectorIndexed()) return false;
1266 return VectorList.Count == 2 && VectorList.LaneIndex <= 7;
1269 bool isVecListTwoDHWordIndexed() const {
1270 if (!isSingleSpacedVectorIndexed()) return false;
1271 return VectorList.Count == 2 && VectorList.LaneIndex <= 3;
1274 bool isVecListTwoQWordIndexed() const {
1275 if (!isDoubleSpacedVectorIndexed()) return false;
1276 return VectorList.Count == 2 && VectorList.LaneIndex <= 1;
1279 bool isVecListTwoQHWordIndexed() const {
1280 if (!isDoubleSpacedVectorIndexed()) return false;
1281 return VectorList.Count == 2 && VectorList.LaneIndex <= 3;
1284 bool isVecListTwoDWordIndexed() const {
1285 if (!isSingleSpacedVectorIndexed()) return false;
1286 return VectorList.Count == 2 && VectorList.LaneIndex <= 1;
1289 bool isVecListThreeDByteIndexed() const {
1290 if (!isSingleSpacedVectorIndexed()) return false;
1291 return VectorList.Count == 3 && VectorList.LaneIndex <= 7;
1294 bool isVecListThreeDHWordIndexed() const {
1295 if (!isSingleSpacedVectorIndexed()) return false;
1296 return VectorList.Count == 3 && VectorList.LaneIndex <= 3;
1299 bool isVecListThreeQWordIndexed() const {
1300 if (!isDoubleSpacedVectorIndexed()) return false;
1301 return VectorList.Count == 3 && VectorList.LaneIndex <= 1;
1304 bool isVecListThreeQHWordIndexed() const {
1305 if (!isDoubleSpacedVectorIndexed()) return false;
1306 return VectorList.Count == 3 && VectorList.LaneIndex <= 3;
1309 bool isVecListThreeDWordIndexed() const {
1310 if (!isSingleSpacedVectorIndexed()) return false;
1311 return VectorList.Count == 3 && VectorList.LaneIndex <= 1;
1314 bool isVecListFourDByteIndexed() const {
1315 if (!isSingleSpacedVectorIndexed()) return false;
1316 return VectorList.Count == 4 && VectorList.LaneIndex <= 7;
1319 bool isVecListFourDHWordIndexed() const {
1320 if (!isSingleSpacedVectorIndexed()) return false;
1321 return VectorList.Count == 4 && VectorList.LaneIndex <= 3;
1324 bool isVecListFourQWordIndexed() const {
1325 if (!isDoubleSpacedVectorIndexed()) return false;
1326 return VectorList.Count == 4 && VectorList.LaneIndex <= 1;
1329 bool isVecListFourQHWordIndexed() const {
1330 if (!isDoubleSpacedVectorIndexed()) return false;
1331 return VectorList.Count == 4 && VectorList.LaneIndex <= 3;
1334 bool isVecListFourDWordIndexed() const {
1335 if (!isSingleSpacedVectorIndexed()) return false;
1336 return VectorList.Count == 4 && VectorList.LaneIndex <= 1;
1339 bool isVectorIndex8() const {
1340 if (Kind != k_VectorIndex) return false;
1341 return VectorIndex.Val < 8;
1343 bool isVectorIndex16() const {
1344 if (Kind != k_VectorIndex) return false;
1345 return VectorIndex.Val < 4;
1347 bool isVectorIndex32() const {
1348 if (Kind != k_VectorIndex) return false;
1349 return VectorIndex.Val < 2;
1352 bool isNEONi8splat() const {
1353 if (!isImm()) return false;
1354 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1355 // Must be a constant.
1356 if (!CE) return false;
1357 int64_t Value = CE->getValue();
1358 // i8 value splatted across 8 bytes. The immediate is just the 8 byte
1360 return Value >= 0 && Value < 256;
1363 bool isNEONi16splat() const {
1364 if (!isImm()) return false;
1365 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1366 // Must be a constant.
1367 if (!CE) return false;
1368 int64_t Value = CE->getValue();
1369 // i16 value in the range [0,255] or [0x0100, 0xff00]
1370 return (Value >= 0 && Value < 256) || (Value >= 0x0100 && Value <= 0xff00);
1373 bool isNEONi32splat() const {
1374 if (!isImm()) return false;
1375 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1376 // Must be a constant.
1377 if (!CE) return false;
1378 int64_t Value = CE->getValue();
1379 // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X.
1380 return (Value >= 0 && Value < 256) ||
1381 (Value >= 0x0100 && Value <= 0xff00) ||
1382 (Value >= 0x010000 && Value <= 0xff0000) ||
1383 (Value >= 0x01000000 && Value <= 0xff000000);
1386 bool isNEONi32vmov() const {
1387 if (!isImm()) return false;
1388 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1389 // Must be a constant.
1390 if (!CE) return false;
1391 int64_t Value = CE->getValue();
1392 // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X,
1393 // for VMOV/VMVN only, 00Xf or 0Xff are also accepted.
1394 return (Value >= 0 && Value < 256) ||
1395 (Value >= 0x0100 && Value <= 0xff00) ||
1396 (Value >= 0x010000 && Value <= 0xff0000) ||
1397 (Value >= 0x01000000 && Value <= 0xff000000) ||
1398 (Value >= 0x01ff && Value <= 0xffff && (Value & 0xff) == 0xff) ||
1399 (Value >= 0x01ffff && Value <= 0xffffff && (Value & 0xffff) == 0xffff);
1401 bool isNEONi32vmovNeg() const {
1402 if (!isImm()) return false;
1403 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1404 // Must be a constant.
1405 if (!CE) return false;
1406 int64_t Value = ~CE->getValue();
1407 // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X,
1408 // for VMOV/VMVN only, 00Xf or 0Xff are also accepted.
1409 return (Value >= 0 && Value < 256) ||
1410 (Value >= 0x0100 && Value <= 0xff00) ||
1411 (Value >= 0x010000 && Value <= 0xff0000) ||
1412 (Value >= 0x01000000 && Value <= 0xff000000) ||
1413 (Value >= 0x01ff && Value <= 0xffff && (Value & 0xff) == 0xff) ||
1414 (Value >= 0x01ffff && Value <= 0xffffff && (Value & 0xffff) == 0xffff);
1417 bool isNEONi64splat() const {
1418 if (!isImm()) return false;
1419 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1420 // Must be a constant.
1421 if (!CE) return false;
1422 uint64_t Value = CE->getValue();
1423 // i64 value with each byte being either 0 or 0xff.
1424 for (unsigned i = 0; i < 8; ++i)
1425 if ((Value & 0xff) != 0 && (Value & 0xff) != 0xff) return false;
1429 void addExpr(MCInst &Inst, const MCExpr *Expr) const {
1430 // Add as immediates when possible. Null MCExpr = 0.
1432 Inst.addOperand(MCOperand::CreateImm(0));
1433 else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
1434 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
1436 Inst.addOperand(MCOperand::CreateExpr(Expr));
1439 void addCondCodeOperands(MCInst &Inst, unsigned N) const {
1440 assert(N == 2 && "Invalid number of operands!");
1441 Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
1442 unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR;
1443 Inst.addOperand(MCOperand::CreateReg(RegNum));
1446 void addCoprocNumOperands(MCInst &Inst, unsigned N) const {
1447 assert(N == 1 && "Invalid number of operands!");
1448 Inst.addOperand(MCOperand::CreateImm(getCoproc()));
1451 void addCoprocRegOperands(MCInst &Inst, unsigned N) const {
1452 assert(N == 1 && "Invalid number of operands!");
1453 Inst.addOperand(MCOperand::CreateImm(getCoproc()));
1456 void addCoprocOptionOperands(MCInst &Inst, unsigned N) const {
1457 assert(N == 1 && "Invalid number of operands!");
1458 Inst.addOperand(MCOperand::CreateImm(CoprocOption.Val));
1461 void addITMaskOperands(MCInst &Inst, unsigned N) const {
1462 assert(N == 1 && "Invalid number of operands!");
1463 Inst.addOperand(MCOperand::CreateImm(ITMask.Mask));
1466 void addITCondCodeOperands(MCInst &Inst, unsigned N) const {
1467 assert(N == 1 && "Invalid number of operands!");
1468 Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
1471 void addCCOutOperands(MCInst &Inst, unsigned N) const {
1472 assert(N == 1 && "Invalid number of operands!");
1473 Inst.addOperand(MCOperand::CreateReg(getReg()));
1476 void addRegOperands(MCInst &Inst, unsigned N) const {
1477 assert(N == 1 && "Invalid number of operands!");
1478 Inst.addOperand(MCOperand::CreateReg(getReg()));
1481 void addRegShiftedRegOperands(MCInst &Inst, unsigned N) const {
1482 assert(N == 3 && "Invalid number of operands!");
1483 assert(isRegShiftedReg() &&
1484 "addRegShiftedRegOperands() on non RegShiftedReg!");
1485 Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.SrcReg));
1486 Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.ShiftReg));
1487 Inst.addOperand(MCOperand::CreateImm(
1488 ARM_AM::getSORegOpc(RegShiftedReg.ShiftTy, RegShiftedReg.ShiftImm)));
1491 void addRegShiftedImmOperands(MCInst &Inst, unsigned N) const {
1492 assert(N == 2 && "Invalid number of operands!");
1493 assert(isRegShiftedImm() &&
1494 "addRegShiftedImmOperands() on non RegShiftedImm!");
1495 Inst.addOperand(MCOperand::CreateReg(RegShiftedImm.SrcReg));
1496 // Shift of #32 is encoded as 0 where permitted
1497 unsigned Imm = (RegShiftedImm.ShiftImm == 32 ? 0 : RegShiftedImm.ShiftImm);
1498 Inst.addOperand(MCOperand::CreateImm(
1499 ARM_AM::getSORegOpc(RegShiftedImm.ShiftTy, Imm)));
1502 void addShifterImmOperands(MCInst &Inst, unsigned N) const {
1503 assert(N == 1 && "Invalid number of operands!");
1504 Inst.addOperand(MCOperand::CreateImm((ShifterImm.isASR << 5) |
1508 void addRegListOperands(MCInst &Inst, unsigned N) const {
1509 assert(N == 1 && "Invalid number of operands!");
1510 const SmallVectorImpl<unsigned> &RegList = getRegList();
1511 for (SmallVectorImpl<unsigned>::const_iterator
1512 I = RegList.begin(), E = RegList.end(); I != E; ++I)
1513 Inst.addOperand(MCOperand::CreateReg(*I));
1516 void addDPRRegListOperands(MCInst &Inst, unsigned N) const {
1517 addRegListOperands(Inst, N);
1520 void addSPRRegListOperands(MCInst &Inst, unsigned N) const {
1521 addRegListOperands(Inst, N);
1524 void addRotImmOperands(MCInst &Inst, unsigned N) const {
1525 assert(N == 1 && "Invalid number of operands!");
1526 // Encoded as val>>3. The printer handles display as 8, 16, 24.
1527 Inst.addOperand(MCOperand::CreateImm(RotImm.Imm >> 3));
1530 void addBitfieldOperands(MCInst &Inst, unsigned N) const {
1531 assert(N == 1 && "Invalid number of operands!");
1532 // Munge the lsb/width into a bitfield mask.
1533 unsigned lsb = Bitfield.LSB;
1534 unsigned width = Bitfield.Width;
1535 // Make a 32-bit mask w/ the referenced bits clear and all other bits set.
1536 uint32_t Mask = ~(((uint32_t)0xffffffff >> lsb) << (32 - width) >>
1537 (32 - (lsb + width)));
1538 Inst.addOperand(MCOperand::CreateImm(Mask));
1541 void addImmOperands(MCInst &Inst, unsigned N) const {
1542 assert(N == 1 && "Invalid number of operands!");
1543 addExpr(Inst, getImm());
1546 void addFBits16Operands(MCInst &Inst, unsigned N) const {
1547 assert(N == 1 && "Invalid number of operands!");
1548 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1549 Inst.addOperand(MCOperand::CreateImm(16 - CE->getValue()));
1552 void addFBits32Operands(MCInst &Inst, unsigned N) const {
1553 assert(N == 1 && "Invalid number of operands!");
1554 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1555 Inst.addOperand(MCOperand::CreateImm(32 - CE->getValue()));
1558 void addFPImmOperands(MCInst &Inst, unsigned N) const {
1559 assert(N == 1 && "Invalid number of operands!");
1560 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1561 int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue()));
1562 Inst.addOperand(MCOperand::CreateImm(Val));
1565 void addImm8s4Operands(MCInst &Inst, unsigned N) const {
1566 assert(N == 1 && "Invalid number of operands!");
1567 // FIXME: We really want to scale the value here, but the LDRD/STRD
1568 // instruction don't encode operands that way yet.
1569 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1570 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
1573 void addImm0_1020s4Operands(MCInst &Inst, unsigned N) const {
1574 assert(N == 1 && "Invalid number of operands!");
1575 // The immediate is scaled by four in the encoding and is stored
1576 // in the MCInst as such. Lop off the low two bits here.
1577 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1578 Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4));
1581 void addImm0_508s4NegOperands(MCInst &Inst, unsigned N) const {
1582 assert(N == 1 && "Invalid number of operands!");
1583 // The immediate is scaled by four in the encoding and is stored
1584 // in the MCInst as such. Lop off the low two bits here.
1585 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1586 Inst.addOperand(MCOperand::CreateImm(-(CE->getValue() / 4)));
1589 void addImm0_508s4Operands(MCInst &Inst, unsigned N) const {
1590 assert(N == 1 && "Invalid number of operands!");
1591 // The immediate is scaled by four in the encoding and is stored
1592 // in the MCInst as such. Lop off the low two bits here.
1593 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1594 Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4));
1597 void addImm1_16Operands(MCInst &Inst, unsigned N) const {
1598 assert(N == 1 && "Invalid number of operands!");
1599 // The constant encodes as the immediate-1, and we store in the instruction
1600 // the bits as encoded, so subtract off one here.
1601 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1602 Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
1605 void addImm1_32Operands(MCInst &Inst, unsigned N) const {
1606 assert(N == 1 && "Invalid number of operands!");
1607 // The constant encodes as the immediate-1, and we store in the instruction
1608 // the bits as encoded, so subtract off one here.
1609 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1610 Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
1613 void addImmThumbSROperands(MCInst &Inst, unsigned N) const {
1614 assert(N == 1 && "Invalid number of operands!");
1615 // The constant encodes as the immediate, except for 32, which encodes as
1617 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1618 unsigned Imm = CE->getValue();
1619 Inst.addOperand(MCOperand::CreateImm((Imm == 32 ? 0 : Imm)));
1622 void addPKHASRImmOperands(MCInst &Inst, unsigned N) const {
1623 assert(N == 1 && "Invalid number of operands!");
1624 // An ASR value of 32 encodes as 0, so that's how we want to add it to
1625 // the instruction as well.
1626 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1627 int Val = CE->getValue();
1628 Inst.addOperand(MCOperand::CreateImm(Val == 32 ? 0 : Val));
1631 void addT2SOImmNotOperands(MCInst &Inst, unsigned N) const {
1632 assert(N == 1 && "Invalid number of operands!");
1633 // The operand is actually a t2_so_imm, but we have its bitwise
1634 // negation in the assembly source, so twiddle it here.
1635 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1636 Inst.addOperand(MCOperand::CreateImm(~CE->getValue()));
1639 void addT2SOImmNegOperands(MCInst &Inst, unsigned N) const {
1640 assert(N == 1 && "Invalid number of operands!");
1641 // The operand is actually a t2_so_imm, but we have its
1642 // negation in the assembly source, so twiddle it here.
1643 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1644 Inst.addOperand(MCOperand::CreateImm(-CE->getValue()));
1647 void addImm0_4095NegOperands(MCInst &Inst, unsigned N) const {
1648 assert(N == 1 && "Invalid number of operands!");
1649 // The operand is actually an imm0_4095, but we have its
1650 // negation in the assembly source, so twiddle it here.
1651 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1652 Inst.addOperand(MCOperand::CreateImm(-CE->getValue()));
1655 void addARMSOImmNotOperands(MCInst &Inst, unsigned N) const {
1656 assert(N == 1 && "Invalid number of operands!");
1657 // The operand is actually a so_imm, but we have its bitwise
1658 // negation in the assembly source, so twiddle it here.
1659 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1660 Inst.addOperand(MCOperand::CreateImm(~CE->getValue()));
1663 void addARMSOImmNegOperands(MCInst &Inst, unsigned N) const {
1664 assert(N == 1 && "Invalid number of operands!");
1665 // The operand is actually a so_imm, but we have its
1666 // negation in the assembly source, so twiddle it here.
1667 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1668 Inst.addOperand(MCOperand::CreateImm(-CE->getValue()));
1671 void addMemBarrierOptOperands(MCInst &Inst, unsigned N) const {
1672 assert(N == 1 && "Invalid number of operands!");
1673 Inst.addOperand(MCOperand::CreateImm(unsigned(getMemBarrierOpt())));
1676 void addMemNoOffsetOperands(MCInst &Inst, unsigned N) const {
1677 assert(N == 1 && "Invalid number of operands!");
1678 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1681 void addMemPCRelImm12Operands(MCInst &Inst, unsigned N) const {
1682 assert(N == 1 && "Invalid number of operands!");
1683 int32_t Imm = Memory.OffsetImm->getValue();
1684 // FIXME: Handle #-0
1685 if (Imm == INT32_MIN) Imm = 0;
1686 Inst.addOperand(MCOperand::CreateImm(Imm));
1689 void addAdrLabelOperands(MCInst &Inst, unsigned N) const {
1690 assert(N == 1 && "Invalid number of operands!");
1691 assert(isImm() && "Not an immediate!");
1693 // If we have an immediate that's not a constant, treat it as a label
1694 // reference needing a fixup.
1695 if (!isa<MCConstantExpr>(getImm())) {
1696 Inst.addOperand(MCOperand::CreateExpr(getImm()));
1700 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1701 int Val = CE->getValue();
1702 Inst.addOperand(MCOperand::CreateImm(Val));
1705 void addAlignedMemoryOperands(MCInst &Inst, unsigned N) const {
1706 assert(N == 2 && "Invalid number of operands!");
1707 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1708 Inst.addOperand(MCOperand::CreateImm(Memory.Alignment));
1711 void addAddrMode2Operands(MCInst &Inst, unsigned N) const {
1712 assert(N == 3 && "Invalid number of operands!");
1713 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1714 if (!Memory.OffsetRegNum) {
1715 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1716 // Special case for #-0
1717 if (Val == INT32_MIN) Val = 0;
1718 if (Val < 0) Val = -Val;
1719 Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
1721 // For register offset, we encode the shift type and negation flag
1723 Val = ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add,
1724 Memory.ShiftImm, Memory.ShiftType);
1726 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1727 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1728 Inst.addOperand(MCOperand::CreateImm(Val));
1731 void addAM2OffsetImmOperands(MCInst &Inst, unsigned N) const {
1732 assert(N == 2 && "Invalid number of operands!");
1733 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1734 assert(CE && "non-constant AM2OffsetImm operand!");
1735 int32_t Val = CE->getValue();
1736 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1737 // Special case for #-0
1738 if (Val == INT32_MIN) Val = 0;
1739 if (Val < 0) Val = -Val;
1740 Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
1741 Inst.addOperand(MCOperand::CreateReg(0));
1742 Inst.addOperand(MCOperand::CreateImm(Val));
1745 void addAddrMode3Operands(MCInst &Inst, unsigned N) const {
1746 assert(N == 3 && "Invalid number of operands!");
1747 // If we have an immediate that's not a constant, treat it as a label
1748 // reference needing a fixup. If it is a constant, it's something else
1749 // and we reject it.
1751 Inst.addOperand(MCOperand::CreateExpr(getImm()));
1752 Inst.addOperand(MCOperand::CreateReg(0));
1753 Inst.addOperand(MCOperand::CreateImm(0));
1757 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1758 if (!Memory.OffsetRegNum) {
1759 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1760 // Special case for #-0
1761 if (Val == INT32_MIN) Val = 0;
1762 if (Val < 0) Val = -Val;
1763 Val = ARM_AM::getAM3Opc(AddSub, Val);
1765 // For register offset, we encode the shift type and negation flag
1767 Val = ARM_AM::getAM3Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add, 0);
1769 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1770 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1771 Inst.addOperand(MCOperand::CreateImm(Val));
1774 void addAM3OffsetOperands(MCInst &Inst, unsigned N) const {
1775 assert(N == 2 && "Invalid number of operands!");
1776 if (Kind == k_PostIndexRegister) {
1778 ARM_AM::getAM3Opc(PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub, 0);
1779 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
1780 Inst.addOperand(MCOperand::CreateImm(Val));
1785 const MCConstantExpr *CE = static_cast<const MCConstantExpr*>(getImm());
1786 int32_t Val = CE->getValue();
1787 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1788 // Special case for #-0
1789 if (Val == INT32_MIN) Val = 0;
1790 if (Val < 0) Val = -Val;
1791 Val = ARM_AM::getAM3Opc(AddSub, Val);
1792 Inst.addOperand(MCOperand::CreateReg(0));
1793 Inst.addOperand(MCOperand::CreateImm(Val));
1796 void addAddrMode5Operands(MCInst &Inst, unsigned N) const {
1797 assert(N == 2 && "Invalid number of operands!");
1798 // If we have an immediate that's not a constant, treat it as a label
1799 // reference needing a fixup. If it is a constant, it's something else
1800 // and we reject it.
1802 Inst.addOperand(MCOperand::CreateExpr(getImm()));
1803 Inst.addOperand(MCOperand::CreateImm(0));
1807 // The lower two bits are always zero and as such are not encoded.
1808 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0;
1809 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1810 // Special case for #-0
1811 if (Val == INT32_MIN) Val = 0;
1812 if (Val < 0) Val = -Val;
1813 Val = ARM_AM::getAM5Opc(AddSub, Val);
1814 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1815 Inst.addOperand(MCOperand::CreateImm(Val));
1818 void addMemImm8s4OffsetOperands(MCInst &Inst, unsigned N) const {
1819 assert(N == 2 && "Invalid number of operands!");
1820 // If we have an immediate that's not a constant, treat it as a label
1821 // reference needing a fixup. If it is a constant, it's something else
1822 // and we reject it.
1824 Inst.addOperand(MCOperand::CreateExpr(getImm()));
1825 Inst.addOperand(MCOperand::CreateImm(0));
1829 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1830 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1831 Inst.addOperand(MCOperand::CreateImm(Val));
1834 void addMemImm0_1020s4OffsetOperands(MCInst &Inst, unsigned N) const {
1835 assert(N == 2 && "Invalid number of operands!");
1836 // The lower two bits are always zero and as such are not encoded.
1837 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0;
1838 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1839 Inst.addOperand(MCOperand::CreateImm(Val));
1842 void addMemImm8OffsetOperands(MCInst &Inst, unsigned N) const {
1843 assert(N == 2 && "Invalid number of operands!");
1844 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1845 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1846 Inst.addOperand(MCOperand::CreateImm(Val));
1849 void addMemPosImm8OffsetOperands(MCInst &Inst, unsigned N) const {
1850 addMemImm8OffsetOperands(Inst, N);
1853 void addMemNegImm8OffsetOperands(MCInst &Inst, unsigned N) const {
1854 addMemImm8OffsetOperands(Inst, N);
1857 void addMemUImm12OffsetOperands(MCInst &Inst, unsigned N) const {
1858 assert(N == 2 && "Invalid number of operands!");
1859 // If this is an immediate, it's a label reference.
1861 addExpr(Inst, getImm());
1862 Inst.addOperand(MCOperand::CreateImm(0));
1866 // Otherwise, it's a normal memory reg+offset.
1867 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1868 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1869 Inst.addOperand(MCOperand::CreateImm(Val));
1872 void addMemImm12OffsetOperands(MCInst &Inst, unsigned N) const {
1873 assert(N == 2 && "Invalid number of operands!");
1874 // If this is an immediate, it's a label reference.
1876 addExpr(Inst, getImm());
1877 Inst.addOperand(MCOperand::CreateImm(0));
1881 // Otherwise, it's a normal memory reg+offset.
1882 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1883 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1884 Inst.addOperand(MCOperand::CreateImm(Val));
1887 void addMemTBBOperands(MCInst &Inst, unsigned N) const {
1888 assert(N == 2 && "Invalid number of operands!");
1889 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1890 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1893 void addMemTBHOperands(MCInst &Inst, unsigned N) const {
1894 assert(N == 2 && "Invalid number of operands!");
1895 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1896 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1899 void addMemRegOffsetOperands(MCInst &Inst, unsigned N) const {
1900 assert(N == 3 && "Invalid number of operands!");
1902 ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add,
1903 Memory.ShiftImm, Memory.ShiftType);
1904 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1905 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1906 Inst.addOperand(MCOperand::CreateImm(Val));
1909 void addT2MemRegOffsetOperands(MCInst &Inst, unsigned N) const {
1910 assert(N == 3 && "Invalid number of operands!");
1911 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1912 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1913 Inst.addOperand(MCOperand::CreateImm(Memory.ShiftImm));
1916 void addMemThumbRROperands(MCInst &Inst, unsigned N) const {
1917 assert(N == 2 && "Invalid number of operands!");
1918 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1919 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1922 void addMemThumbRIs4Operands(MCInst &Inst, unsigned N) const {
1923 assert(N == 2 && "Invalid number of operands!");
1924 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0;
1925 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1926 Inst.addOperand(MCOperand::CreateImm(Val));
1929 void addMemThumbRIs2Operands(MCInst &Inst, unsigned N) const {
1930 assert(N == 2 && "Invalid number of operands!");
1931 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 2) : 0;
1932 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1933 Inst.addOperand(MCOperand::CreateImm(Val));
1936 void addMemThumbRIs1Operands(MCInst &Inst, unsigned N) const {
1937 assert(N == 2 && "Invalid number of operands!");
1938 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue()) : 0;
1939 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1940 Inst.addOperand(MCOperand::CreateImm(Val));
1943 void addMemThumbSPIOperands(MCInst &Inst, unsigned N) const {
1944 assert(N == 2 && "Invalid number of operands!");
1945 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0;
1946 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1947 Inst.addOperand(MCOperand::CreateImm(Val));
1950 void addPostIdxImm8Operands(MCInst &Inst, unsigned N) const {
1951 assert(N == 1 && "Invalid number of operands!");
1952 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1953 assert(CE && "non-constant post-idx-imm8 operand!");
1954 int Imm = CE->getValue();
1955 bool isAdd = Imm >= 0;
1956 if (Imm == INT32_MIN) Imm = 0;
1957 Imm = (Imm < 0 ? -Imm : Imm) | (int)isAdd << 8;
1958 Inst.addOperand(MCOperand::CreateImm(Imm));
1961 void addPostIdxImm8s4Operands(MCInst &Inst, unsigned N) const {
1962 assert(N == 1 && "Invalid number of operands!");
1963 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1964 assert(CE && "non-constant post-idx-imm8s4 operand!");
1965 int Imm = CE->getValue();
1966 bool isAdd = Imm >= 0;
1967 if (Imm == INT32_MIN) Imm = 0;
1968 // Immediate is scaled by 4.
1969 Imm = ((Imm < 0 ? -Imm : Imm) / 4) | (int)isAdd << 8;
1970 Inst.addOperand(MCOperand::CreateImm(Imm));
1973 void addPostIdxRegOperands(MCInst &Inst, unsigned N) const {
1974 assert(N == 2 && "Invalid number of operands!");
1975 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
1976 Inst.addOperand(MCOperand::CreateImm(PostIdxReg.isAdd));
1979 void addPostIdxRegShiftedOperands(MCInst &Inst, unsigned N) const {
1980 assert(N == 2 && "Invalid number of operands!");
1981 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
1982 // The sign, shift type, and shift amount are encoded in a single operand
1983 // using the AM2 encoding helpers.
1984 ARM_AM::AddrOpc opc = PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub;
1985 unsigned Imm = ARM_AM::getAM2Opc(opc, PostIdxReg.ShiftImm,
1986 PostIdxReg.ShiftTy);
1987 Inst.addOperand(MCOperand::CreateImm(Imm));
1990 void addMSRMaskOperands(MCInst &Inst, unsigned N) const {
1991 assert(N == 1 && "Invalid number of operands!");
1992 Inst.addOperand(MCOperand::CreateImm(unsigned(getMSRMask())));
1995 void addProcIFlagsOperands(MCInst &Inst, unsigned N) const {
1996 assert(N == 1 && "Invalid number of operands!");
1997 Inst.addOperand(MCOperand::CreateImm(unsigned(getProcIFlags())));
2000 void addVecListOperands(MCInst &Inst, unsigned N) const {
2001 assert(N == 1 && "Invalid number of operands!");
2002 Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum));
2005 void addVecListIndexedOperands(MCInst &Inst, unsigned N) const {
2006 assert(N == 2 && "Invalid number of operands!");
2007 Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum));
2008 Inst.addOperand(MCOperand::CreateImm(VectorList.LaneIndex));
2011 void addVectorIndex8Operands(MCInst &Inst, unsigned N) const {
2012 assert(N == 1 && "Invalid number of operands!");
2013 Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
2016 void addVectorIndex16Operands(MCInst &Inst, unsigned N) const {
2017 assert(N == 1 && "Invalid number of operands!");
2018 Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
2021 void addVectorIndex32Operands(MCInst &Inst, unsigned N) const {
2022 assert(N == 1 && "Invalid number of operands!");
2023 Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
2026 void addNEONi8splatOperands(MCInst &Inst, unsigned N) const {
2027 assert(N == 1 && "Invalid number of operands!");
2028 // The immediate encodes the type of constant as well as the value.
2029 // Mask in that this is an i8 splat.
2030 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2031 Inst.addOperand(MCOperand::CreateImm(CE->getValue() | 0xe00));
2034 void addNEONi16splatOperands(MCInst &Inst, unsigned N) const {
2035 assert(N == 1 && "Invalid number of operands!");
2036 // The immediate encodes the type of constant as well as the value.
2037 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2038 unsigned Value = CE->getValue();
2040 Value = (Value >> 8) | 0xa00;
2043 Inst.addOperand(MCOperand::CreateImm(Value));
2046 void addNEONi32splatOperands(MCInst &Inst, unsigned N) const {
2047 assert(N == 1 && "Invalid number of operands!");
2048 // The immediate encodes the type of constant as well as the value.
2049 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2050 unsigned Value = CE->getValue();
2051 if (Value >= 256 && Value <= 0xff00)
2052 Value = (Value >> 8) | 0x200;
2053 else if (Value > 0xffff && Value <= 0xff0000)
2054 Value = (Value >> 16) | 0x400;
2055 else if (Value > 0xffffff)
2056 Value = (Value >> 24) | 0x600;
2057 Inst.addOperand(MCOperand::CreateImm(Value));
2060 void addNEONi32vmovOperands(MCInst &Inst, unsigned N) const {
2061 assert(N == 1 && "Invalid number of operands!");
2062 // The immediate encodes the type of constant as well as the value.
2063 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2064 unsigned Value = CE->getValue();
2065 if (Value >= 256 && Value <= 0xffff)
2066 Value = (Value >> 8) | ((Value & 0xff) ? 0xc00 : 0x200);
2067 else if (Value > 0xffff && Value <= 0xffffff)
2068 Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400);
2069 else if (Value > 0xffffff)
2070 Value = (Value >> 24) | 0x600;
2071 Inst.addOperand(MCOperand::CreateImm(Value));
2074 void addNEONi32vmovNegOperands(MCInst &Inst, unsigned N) const {
2075 assert(N == 1 && "Invalid number of operands!");
2076 // The immediate encodes the type of constant as well as the value.
2077 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2078 unsigned Value = ~CE->getValue();
2079 if (Value >= 256 && Value <= 0xffff)
2080 Value = (Value >> 8) | ((Value & 0xff) ? 0xc00 : 0x200);
2081 else if (Value > 0xffff && Value <= 0xffffff)
2082 Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400);
2083 else if (Value > 0xffffff)
2084 Value = (Value >> 24) | 0x600;
2085 Inst.addOperand(MCOperand::CreateImm(Value));
2088 void addNEONi64splatOperands(MCInst &Inst, unsigned N) const {
2089 assert(N == 1 && "Invalid number of operands!");
2090 // The immediate encodes the type of constant as well as the value.
2091 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2092 uint64_t Value = CE->getValue();
2094 for (unsigned i = 0; i < 8; ++i, Value >>= 8) {
2095 Imm |= (Value & 1) << i;
2097 Inst.addOperand(MCOperand::CreateImm(Imm | 0x1e00));
2100 virtual void print(raw_ostream &OS) const;
2102 static ARMOperand *CreateITMask(unsigned Mask, SMLoc S) {
2103 ARMOperand *Op = new ARMOperand(k_ITCondMask);
2104 Op->ITMask.Mask = Mask;
2110 static ARMOperand *CreateCondCode(ARMCC::CondCodes CC, SMLoc S) {
2111 ARMOperand *Op = new ARMOperand(k_CondCode);
2118 static ARMOperand *CreateCoprocNum(unsigned CopVal, SMLoc S) {
2119 ARMOperand *Op = new ARMOperand(k_CoprocNum);
2120 Op->Cop.Val = CopVal;
2126 static ARMOperand *CreateCoprocReg(unsigned CopVal, SMLoc S) {
2127 ARMOperand *Op = new ARMOperand(k_CoprocReg);
2128 Op->Cop.Val = CopVal;
2134 static ARMOperand *CreateCoprocOption(unsigned Val, SMLoc S, SMLoc E) {
2135 ARMOperand *Op = new ARMOperand(k_CoprocOption);
2142 static ARMOperand *CreateCCOut(unsigned RegNum, SMLoc S) {
2143 ARMOperand *Op = new ARMOperand(k_CCOut);
2144 Op->Reg.RegNum = RegNum;
2150 static ARMOperand *CreateToken(StringRef Str, SMLoc S) {
2151 ARMOperand *Op = new ARMOperand(k_Token);
2152 Op->Tok.Data = Str.data();
2153 Op->Tok.Length = Str.size();
2159 static ARMOperand *CreateReg(unsigned RegNum, SMLoc S, SMLoc E) {
2160 ARMOperand *Op = new ARMOperand(k_Register);
2161 Op->Reg.RegNum = RegNum;
2167 static ARMOperand *CreateShiftedRegister(ARM_AM::ShiftOpc ShTy,
2172 ARMOperand *Op = new ARMOperand(k_ShiftedRegister);
2173 Op->RegShiftedReg.ShiftTy = ShTy;
2174 Op->RegShiftedReg.SrcReg = SrcReg;
2175 Op->RegShiftedReg.ShiftReg = ShiftReg;
2176 Op->RegShiftedReg.ShiftImm = ShiftImm;
2182 static ARMOperand *CreateShiftedImmediate(ARM_AM::ShiftOpc ShTy,
2186 ARMOperand *Op = new ARMOperand(k_ShiftedImmediate);
2187 Op->RegShiftedImm.ShiftTy = ShTy;
2188 Op->RegShiftedImm.SrcReg = SrcReg;
2189 Op->RegShiftedImm.ShiftImm = ShiftImm;
2195 static ARMOperand *CreateShifterImm(bool isASR, unsigned Imm,
2197 ARMOperand *Op = new ARMOperand(k_ShifterImmediate);
2198 Op->ShifterImm.isASR = isASR;
2199 Op->ShifterImm.Imm = Imm;
2205 static ARMOperand *CreateRotImm(unsigned Imm, SMLoc S, SMLoc E) {
2206 ARMOperand *Op = new ARMOperand(k_RotateImmediate);
2207 Op->RotImm.Imm = Imm;
2213 static ARMOperand *CreateBitfield(unsigned LSB, unsigned Width,
2215 ARMOperand *Op = new ARMOperand(k_BitfieldDescriptor);
2216 Op->Bitfield.LSB = LSB;
2217 Op->Bitfield.Width = Width;
2224 CreateRegList(const SmallVectorImpl<std::pair<unsigned, SMLoc> > &Regs,
2225 SMLoc StartLoc, SMLoc EndLoc) {
2226 KindTy Kind = k_RegisterList;
2228 if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Regs.front().first))
2229 Kind = k_DPRRegisterList;
2230 else if (ARMMCRegisterClasses[ARM::SPRRegClassID].
2231 contains(Regs.front().first))
2232 Kind = k_SPRRegisterList;
2234 ARMOperand *Op = new ARMOperand(Kind);
2235 for (SmallVectorImpl<std::pair<unsigned, SMLoc> >::const_iterator
2236 I = Regs.begin(), E = Regs.end(); I != E; ++I)
2237 Op->Registers.push_back(I->first);
2238 array_pod_sort(Op->Registers.begin(), Op->Registers.end());
2239 Op->StartLoc = StartLoc;
2240 Op->EndLoc = EndLoc;
2244 static ARMOperand *CreateVectorList(unsigned RegNum, unsigned Count,
2245 bool isDoubleSpaced, SMLoc S, SMLoc E) {
2246 ARMOperand *Op = new ARMOperand(k_VectorList);
2247 Op->VectorList.RegNum = RegNum;
2248 Op->VectorList.Count = Count;
2249 Op->VectorList.isDoubleSpaced = isDoubleSpaced;
2255 static ARMOperand *CreateVectorListAllLanes(unsigned RegNum, unsigned Count,
2256 bool isDoubleSpaced,
2258 ARMOperand *Op = new ARMOperand(k_VectorListAllLanes);
2259 Op->VectorList.RegNum = RegNum;
2260 Op->VectorList.Count = Count;
2261 Op->VectorList.isDoubleSpaced = isDoubleSpaced;
2267 static ARMOperand *CreateVectorListIndexed(unsigned RegNum, unsigned Count,
2269 bool isDoubleSpaced,
2271 ARMOperand *Op = new ARMOperand(k_VectorListIndexed);
2272 Op->VectorList.RegNum = RegNum;
2273 Op->VectorList.Count = Count;
2274 Op->VectorList.LaneIndex = Index;
2275 Op->VectorList.isDoubleSpaced = isDoubleSpaced;
2281 static ARMOperand *CreateVectorIndex(unsigned Idx, SMLoc S, SMLoc E,
2283 ARMOperand *Op = new ARMOperand(k_VectorIndex);
2284 Op->VectorIndex.Val = Idx;
2290 static ARMOperand *CreateImm(const MCExpr *Val, SMLoc S, SMLoc E) {
2291 ARMOperand *Op = new ARMOperand(k_Immediate);
2298 static ARMOperand *CreateMem(unsigned BaseRegNum,
2299 const MCConstantExpr *OffsetImm,
2300 unsigned OffsetRegNum,
2301 ARM_AM::ShiftOpc ShiftType,
2306 ARMOperand *Op = new ARMOperand(k_Memory);
2307 Op->Memory.BaseRegNum = BaseRegNum;
2308 Op->Memory.OffsetImm = OffsetImm;
2309 Op->Memory.OffsetRegNum = OffsetRegNum;
2310 Op->Memory.ShiftType = ShiftType;
2311 Op->Memory.ShiftImm = ShiftImm;
2312 Op->Memory.Alignment = Alignment;
2313 Op->Memory.isNegative = isNegative;
2319 static ARMOperand *CreatePostIdxReg(unsigned RegNum, bool isAdd,
2320 ARM_AM::ShiftOpc ShiftTy,
2323 ARMOperand *Op = new ARMOperand(k_PostIndexRegister);
2324 Op->PostIdxReg.RegNum = RegNum;
2325 Op->PostIdxReg.isAdd = isAdd;
2326 Op->PostIdxReg.ShiftTy = ShiftTy;
2327 Op->PostIdxReg.ShiftImm = ShiftImm;
2333 static ARMOperand *CreateMemBarrierOpt(ARM_MB::MemBOpt Opt, SMLoc S) {
2334 ARMOperand *Op = new ARMOperand(k_MemBarrierOpt);
2335 Op->MBOpt.Val = Opt;
2341 static ARMOperand *CreateProcIFlags(ARM_PROC::IFlags IFlags, SMLoc S) {
2342 ARMOperand *Op = new ARMOperand(k_ProcIFlags);
2343 Op->IFlags.Val = IFlags;
2349 static ARMOperand *CreateMSRMask(unsigned MMask, SMLoc S) {
2350 ARMOperand *Op = new ARMOperand(k_MSRMask);
2351 Op->MMask.Val = MMask;
2358 } // end anonymous namespace.
2360 void ARMOperand::print(raw_ostream &OS) const {
2363 OS << "<ARMCC::" << ARMCondCodeToString(getCondCode()) << ">";
2366 OS << "<ccout " << getReg() << ">";
2368 case k_ITCondMask: {
2369 static const char *const MaskStr[] = {
2370 "()", "(t)", "(e)", "(tt)", "(et)", "(te)", "(ee)", "(ttt)", "(ett)",
2371 "(tet)", "(eet)", "(tte)", "(ete)", "(tee)", "(eee)"
2373 assert((ITMask.Mask & 0xf) == ITMask.Mask);
2374 OS << "<it-mask " << MaskStr[ITMask.Mask] << ">";
2378 OS << "<coprocessor number: " << getCoproc() << ">";
2381 OS << "<coprocessor register: " << getCoproc() << ">";
2383 case k_CoprocOption:
2384 OS << "<coprocessor option: " << CoprocOption.Val << ">";
2387 OS << "<mask: " << getMSRMask() << ">";
2390 getImm()->print(OS);
2392 case k_MemBarrierOpt:
2393 OS << "<ARM_MB::" << MemBOptToString(getMemBarrierOpt()) << ">";
2397 << " base:" << Memory.BaseRegNum;
2400 case k_PostIndexRegister:
2401 OS << "post-idx register " << (PostIdxReg.isAdd ? "" : "-")
2402 << PostIdxReg.RegNum;
2403 if (PostIdxReg.ShiftTy != ARM_AM::no_shift)
2404 OS << ARM_AM::getShiftOpcStr(PostIdxReg.ShiftTy) << " "
2405 << PostIdxReg.ShiftImm;
2408 case k_ProcIFlags: {
2409 OS << "<ARM_PROC::";
2410 unsigned IFlags = getProcIFlags();
2411 for (int i=2; i >= 0; --i)
2412 if (IFlags & (1 << i))
2413 OS << ARM_PROC::IFlagsToString(1 << i);
2418 OS << "<register " << getReg() << ">";
2420 case k_ShifterImmediate:
2421 OS << "<shift " << (ShifterImm.isASR ? "asr" : "lsl")
2422 << " #" << ShifterImm.Imm << ">";
2424 case k_ShiftedRegister:
2425 OS << "<so_reg_reg "
2426 << RegShiftedReg.SrcReg << " "
2427 << ARM_AM::getShiftOpcStr(RegShiftedReg.ShiftTy)
2428 << " " << RegShiftedReg.ShiftReg << ">";
2430 case k_ShiftedImmediate:
2431 OS << "<so_reg_imm "
2432 << RegShiftedImm.SrcReg << " "
2433 << ARM_AM::getShiftOpcStr(RegShiftedImm.ShiftTy)
2434 << " #" << RegShiftedImm.ShiftImm << ">";
2436 case k_RotateImmediate:
2437 OS << "<ror " << " #" << (RotImm.Imm * 8) << ">";
2439 case k_BitfieldDescriptor:
2440 OS << "<bitfield " << "lsb: " << Bitfield.LSB
2441 << ", width: " << Bitfield.Width << ">";
2443 case k_RegisterList:
2444 case k_DPRRegisterList:
2445 case k_SPRRegisterList: {
2446 OS << "<register_list ";
2448 const SmallVectorImpl<unsigned> &RegList = getRegList();
2449 for (SmallVectorImpl<unsigned>::const_iterator
2450 I = RegList.begin(), E = RegList.end(); I != E; ) {
2452 if (++I < E) OS << ", ";
2459 OS << "<vector_list " << VectorList.Count << " * "
2460 << VectorList.RegNum << ">";
2462 case k_VectorListAllLanes:
2463 OS << "<vector_list(all lanes) " << VectorList.Count << " * "
2464 << VectorList.RegNum << ">";
2466 case k_VectorListIndexed:
2467 OS << "<vector_list(lane " << VectorList.LaneIndex << ") "
2468 << VectorList.Count << " * " << VectorList.RegNum << ">";
2471 OS << "'" << getToken() << "'";
2474 OS << "<vectorindex " << getVectorIndex() << ">";
2479 /// @name Auto-generated Match Functions
2482 static unsigned MatchRegisterName(StringRef Name);
2486 bool ARMAsmParser::ParseRegister(unsigned &RegNo,
2487 SMLoc &StartLoc, SMLoc &EndLoc) {
2488 StartLoc = Parser.getTok().getLoc();
2489 EndLoc = Parser.getTok().getEndLoc();
2490 RegNo = tryParseRegister();
2492 return (RegNo == (unsigned)-1);
2495 /// Try to parse a register name. The token must be an Identifier when called,
2496 /// and if it is a register name the token is eaten and the register number is
2497 /// returned. Otherwise return -1.
2499 int ARMAsmParser::tryParseRegister() {
2500 const AsmToken &Tok = Parser.getTok();
2501 if (Tok.isNot(AsmToken::Identifier)) return -1;
2503 std::string lowerCase = Tok.getString().lower();
2504 unsigned RegNum = MatchRegisterName(lowerCase);
2506 RegNum = StringSwitch<unsigned>(lowerCase)
2507 .Case("r13", ARM::SP)
2508 .Case("r14", ARM::LR)
2509 .Case("r15", ARM::PC)
2510 .Case("ip", ARM::R12)
2511 // Additional register name aliases for 'gas' compatibility.
2512 .Case("a1", ARM::R0)
2513 .Case("a2", ARM::R1)
2514 .Case("a3", ARM::R2)
2515 .Case("a4", ARM::R3)
2516 .Case("v1", ARM::R4)
2517 .Case("v2", ARM::R5)
2518 .Case("v3", ARM::R6)
2519 .Case("v4", ARM::R7)
2520 .Case("v5", ARM::R8)
2521 .Case("v6", ARM::R9)
2522 .Case("v7", ARM::R10)
2523 .Case("v8", ARM::R11)
2524 .Case("sb", ARM::R9)
2525 .Case("sl", ARM::R10)
2526 .Case("fp", ARM::R11)
2530 // Check for aliases registered via .req. Canonicalize to lower case.
2531 // That's more consistent since register names are case insensitive, and
2532 // it's how the original entry was passed in from MC/MCParser/AsmParser.
2533 StringMap<unsigned>::const_iterator Entry = RegisterReqs.find(lowerCase);
2534 // If no match, return failure.
2535 if (Entry == RegisterReqs.end())
2537 Parser.Lex(); // Eat identifier token.
2538 return Entry->getValue();
2541 Parser.Lex(); // Eat identifier token.
2546 // Try to parse a shifter (e.g., "lsl <amt>"). On success, return 0.
2547 // If a recoverable error occurs, return 1. If an irrecoverable error
2548 // occurs, return -1. An irrecoverable error is one where tokens have been
2549 // consumed in the process of trying to parse the shifter (i.e., when it is
2550 // indeed a shifter operand, but malformed).
2551 int ARMAsmParser::tryParseShiftRegister(
2552 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2553 SMLoc S = Parser.getTok().getLoc();
2554 const AsmToken &Tok = Parser.getTok();
2555 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
2557 std::string lowerCase = Tok.getString().lower();
2558 ARM_AM::ShiftOpc ShiftTy = StringSwitch<ARM_AM::ShiftOpc>(lowerCase)
2559 .Case("asl", ARM_AM::lsl)
2560 .Case("lsl", ARM_AM::lsl)
2561 .Case("lsr", ARM_AM::lsr)
2562 .Case("asr", ARM_AM::asr)
2563 .Case("ror", ARM_AM::ror)
2564 .Case("rrx", ARM_AM::rrx)
2565 .Default(ARM_AM::no_shift);
2567 if (ShiftTy == ARM_AM::no_shift)
2570 Parser.Lex(); // Eat the operator.
2572 // The source register for the shift has already been added to the
2573 // operand list, so we need to pop it off and combine it into the shifted
2574 // register operand instead.
2575 OwningPtr<ARMOperand> PrevOp((ARMOperand*)Operands.pop_back_val());
2576 if (!PrevOp->isReg())
2577 return Error(PrevOp->getStartLoc(), "shift must be of a register");
2578 int SrcReg = PrevOp->getReg();
2583 if (ShiftTy == ARM_AM::rrx) {
2584 // RRX Doesn't have an explicit shift amount. The encoder expects
2585 // the shift register to be the same as the source register. Seems odd,
2589 // Figure out if this is shifted by a constant or a register (for non-RRX).
2590 if (Parser.getTok().is(AsmToken::Hash) ||
2591 Parser.getTok().is(AsmToken::Dollar)) {
2592 Parser.Lex(); // Eat hash.
2593 SMLoc ImmLoc = Parser.getTok().getLoc();
2594 const MCExpr *ShiftExpr = 0;
2595 if (getParser().parseExpression(ShiftExpr, EndLoc)) {
2596 Error(ImmLoc, "invalid immediate shift value");
2599 // The expression must be evaluatable as an immediate.
2600 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftExpr);
2602 Error(ImmLoc, "invalid immediate shift value");
2605 // Range check the immediate.
2606 // lsl, ror: 0 <= imm <= 31
2607 // lsr, asr: 0 <= imm <= 32
2608 Imm = CE->getValue();
2610 ((ShiftTy == ARM_AM::lsl || ShiftTy == ARM_AM::ror) && Imm > 31) ||
2611 ((ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr) && Imm > 32)) {
2612 Error(ImmLoc, "immediate shift value out of range");
2615 // shift by zero is a nop. Always send it through as lsl.
2616 // ('as' compatibility)
2618 ShiftTy = ARM_AM::lsl;
2619 } else if (Parser.getTok().is(AsmToken::Identifier)) {
2620 SMLoc L = Parser.getTok().getLoc();
2621 EndLoc = Parser.getTok().getEndLoc();
2622 ShiftReg = tryParseRegister();
2623 if (ShiftReg == -1) {
2624 Error (L, "expected immediate or register in shift operand");
2628 Error (Parser.getTok().getLoc(),
2629 "expected immediate or register in shift operand");
2634 if (ShiftReg && ShiftTy != ARM_AM::rrx)
2635 Operands.push_back(ARMOperand::CreateShiftedRegister(ShiftTy, SrcReg,
2639 Operands.push_back(ARMOperand::CreateShiftedImmediate(ShiftTy, SrcReg, Imm,
2646 /// Try to parse a register name. The token must be an Identifier when called.
2647 /// If it's a register, an AsmOperand is created. Another AsmOperand is created
2648 /// if there is a "writeback". 'true' if it's not a register.
2650 /// TODO this is likely to change to allow different register types and or to
2651 /// parse for a specific register type.
2653 tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2654 const AsmToken &RegTok = Parser.getTok();
2655 int RegNo = tryParseRegister();
2659 Operands.push_back(ARMOperand::CreateReg(RegNo, RegTok.getLoc(),
2660 RegTok.getEndLoc()));
2662 const AsmToken &ExclaimTok = Parser.getTok();
2663 if (ExclaimTok.is(AsmToken::Exclaim)) {
2664 Operands.push_back(ARMOperand::CreateToken(ExclaimTok.getString(),
2665 ExclaimTok.getLoc()));
2666 Parser.Lex(); // Eat exclaim token
2670 // Also check for an index operand. This is only legal for vector registers,
2671 // but that'll get caught OK in operand matching, so we don't need to
2672 // explicitly filter everything else out here.
2673 if (Parser.getTok().is(AsmToken::LBrac)) {
2674 SMLoc SIdx = Parser.getTok().getLoc();
2675 Parser.Lex(); // Eat left bracket token.
2677 const MCExpr *ImmVal;
2678 if (getParser().parseExpression(ImmVal))
2680 const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(ImmVal);
2682 return TokError("immediate value expected for vector index");
2684 if (Parser.getTok().isNot(AsmToken::RBrac))
2685 return Error(Parser.getTok().getLoc(), "']' expected");
2687 SMLoc E = Parser.getTok().getEndLoc();
2688 Parser.Lex(); // Eat right bracket token.
2690 Operands.push_back(ARMOperand::CreateVectorIndex(MCE->getValue(),
2698 /// MatchCoprocessorOperandName - Try to parse an coprocessor related
2699 /// instruction with a symbolic operand name. Example: "p1", "p7", "c3",
2701 static int MatchCoprocessorOperandName(StringRef Name, char CoprocOp) {
2702 // Use the same layout as the tablegen'erated register name matcher. Ugly,
2704 switch (Name.size()) {
2707 if (Name[0] != CoprocOp)
2723 if (Name[0] != CoprocOp || Name[1] != '1')
2727 case '0': return 10;
2728 case '1': return 11;
2729 case '2': return 12;
2730 case '3': return 13;
2731 case '4': return 14;
2732 case '5': return 15;
2737 /// parseITCondCode - Try to parse a condition code for an IT instruction.
2738 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2739 parseITCondCode(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2740 SMLoc S = Parser.getTok().getLoc();
2741 const AsmToken &Tok = Parser.getTok();
2742 if (!Tok.is(AsmToken::Identifier))
2743 return MatchOperand_NoMatch;
2744 unsigned CC = StringSwitch<unsigned>(Tok.getString().lower())
2745 .Case("eq", ARMCC::EQ)
2746 .Case("ne", ARMCC::NE)
2747 .Case("hs", ARMCC::HS)
2748 .Case("cs", ARMCC::HS)
2749 .Case("lo", ARMCC::LO)
2750 .Case("cc", ARMCC::LO)
2751 .Case("mi", ARMCC::MI)
2752 .Case("pl", ARMCC::PL)
2753 .Case("vs", ARMCC::VS)
2754 .Case("vc", ARMCC::VC)
2755 .Case("hi", ARMCC::HI)
2756 .Case("ls", ARMCC::LS)
2757 .Case("ge", ARMCC::GE)
2758 .Case("lt", ARMCC::LT)
2759 .Case("gt", ARMCC::GT)
2760 .Case("le", ARMCC::LE)
2761 .Case("al", ARMCC::AL)
2764 return MatchOperand_NoMatch;
2765 Parser.Lex(); // Eat the token.
2767 Operands.push_back(ARMOperand::CreateCondCode(ARMCC::CondCodes(CC), S));
2769 return MatchOperand_Success;
2772 /// parseCoprocNumOperand - Try to parse an coprocessor number operand. The
2773 /// token must be an Identifier when called, and if it is a coprocessor
2774 /// number, the token is eaten and the operand is added to the operand list.
2775 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2776 parseCoprocNumOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2777 SMLoc S = Parser.getTok().getLoc();
2778 const AsmToken &Tok = Parser.getTok();
2779 if (Tok.isNot(AsmToken::Identifier))
2780 return MatchOperand_NoMatch;
2782 int Num = MatchCoprocessorOperandName(Tok.getString(), 'p');
2784 return MatchOperand_NoMatch;
2786 Parser.Lex(); // Eat identifier token.
2787 Operands.push_back(ARMOperand::CreateCoprocNum(Num, S));
2788 return MatchOperand_Success;
2791 /// parseCoprocRegOperand - Try to parse an coprocessor register operand. The
2792 /// token must be an Identifier when called, and if it is a coprocessor
2793 /// number, the token is eaten and the operand is added to the operand list.
2794 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2795 parseCoprocRegOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2796 SMLoc S = Parser.getTok().getLoc();
2797 const AsmToken &Tok = Parser.getTok();
2798 if (Tok.isNot(AsmToken::Identifier))
2799 return MatchOperand_NoMatch;
2801 int Reg = MatchCoprocessorOperandName(Tok.getString(), 'c');
2803 return MatchOperand_NoMatch;
2805 Parser.Lex(); // Eat identifier token.
2806 Operands.push_back(ARMOperand::CreateCoprocReg(Reg, S));
2807 return MatchOperand_Success;
2810 /// parseCoprocOptionOperand - Try to parse an coprocessor option operand.
2811 /// coproc_option : '{' imm0_255 '}'
2812 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2813 parseCoprocOptionOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2814 SMLoc S = Parser.getTok().getLoc();
2816 // If this isn't a '{', this isn't a coprocessor immediate operand.
2817 if (Parser.getTok().isNot(AsmToken::LCurly))
2818 return MatchOperand_NoMatch;
2819 Parser.Lex(); // Eat the '{'
2822 SMLoc Loc = Parser.getTok().getLoc();
2823 if (getParser().parseExpression(Expr)) {
2824 Error(Loc, "illegal expression");
2825 return MatchOperand_ParseFail;
2827 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
2828 if (!CE || CE->getValue() < 0 || CE->getValue() > 255) {
2829 Error(Loc, "coprocessor option must be an immediate in range [0, 255]");
2830 return MatchOperand_ParseFail;
2832 int Val = CE->getValue();
2834 // Check for and consume the closing '}'
2835 if (Parser.getTok().isNot(AsmToken::RCurly))
2836 return MatchOperand_ParseFail;
2837 SMLoc E = Parser.getTok().getEndLoc();
2838 Parser.Lex(); // Eat the '}'
2840 Operands.push_back(ARMOperand::CreateCoprocOption(Val, S, E));
2841 return MatchOperand_Success;
2844 // For register list parsing, we need to map from raw GPR register numbering
2845 // to the enumeration values. The enumeration values aren't sorted by
2846 // register number due to our using "sp", "lr" and "pc" as canonical names.
2847 static unsigned getNextRegister(unsigned Reg) {
2848 // If this is a GPR, we need to do it manually, otherwise we can rely
2849 // on the sort ordering of the enumeration since the other reg-classes
2851 if (!ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
2854 default: llvm_unreachable("Invalid GPR number!");
2855 case ARM::R0: return ARM::R1; case ARM::R1: return ARM::R2;
2856 case ARM::R2: return ARM::R3; case ARM::R3: return ARM::R4;
2857 case ARM::R4: return ARM::R5; case ARM::R5: return ARM::R6;
2858 case ARM::R6: return ARM::R7; case ARM::R7: return ARM::R8;
2859 case ARM::R8: return ARM::R9; case ARM::R9: return ARM::R10;
2860 case ARM::R10: return ARM::R11; case ARM::R11: return ARM::R12;
2861 case ARM::R12: return ARM::SP; case ARM::SP: return ARM::LR;
2862 case ARM::LR: return ARM::PC; case ARM::PC: return ARM::R0;
2866 // Return the low-subreg of a given Q register.
2867 static unsigned getDRegFromQReg(unsigned QReg) {
2869 default: llvm_unreachable("expected a Q register!");
2870 case ARM::Q0: return ARM::D0;
2871 case ARM::Q1: return ARM::D2;
2872 case ARM::Q2: return ARM::D4;
2873 case ARM::Q3: return ARM::D6;
2874 case ARM::Q4: return ARM::D8;
2875 case ARM::Q5: return ARM::D10;
2876 case ARM::Q6: return ARM::D12;
2877 case ARM::Q7: return ARM::D14;
2878 case ARM::Q8: return ARM::D16;
2879 case ARM::Q9: return ARM::D18;
2880 case ARM::Q10: return ARM::D20;
2881 case ARM::Q11: return ARM::D22;
2882 case ARM::Q12: return ARM::D24;
2883 case ARM::Q13: return ARM::D26;
2884 case ARM::Q14: return ARM::D28;
2885 case ARM::Q15: return ARM::D30;
2889 /// Parse a register list.
2891 parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2892 assert(Parser.getTok().is(AsmToken::LCurly) &&
2893 "Token is not a Left Curly Brace");
2894 SMLoc S = Parser.getTok().getLoc();
2895 Parser.Lex(); // Eat '{' token.
2896 SMLoc RegLoc = Parser.getTok().getLoc();
2898 // Check the first register in the list to see what register class
2899 // this is a list of.
2900 int Reg = tryParseRegister();
2902 return Error(RegLoc, "register expected");
2904 // The reglist instructions have at most 16 registers, so reserve
2905 // space for that many.
2906 SmallVector<std::pair<unsigned, SMLoc>, 16> Registers;
2908 // Allow Q regs and just interpret them as the two D sub-registers.
2909 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
2910 Reg = getDRegFromQReg(Reg);
2911 Registers.push_back(std::pair<unsigned, SMLoc>(Reg, RegLoc));
2914 const MCRegisterClass *RC;
2915 if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
2916 RC = &ARMMCRegisterClasses[ARM::GPRRegClassID];
2917 else if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg))
2918 RC = &ARMMCRegisterClasses[ARM::DPRRegClassID];
2919 else if (ARMMCRegisterClasses[ARM::SPRRegClassID].contains(Reg))
2920 RC = &ARMMCRegisterClasses[ARM::SPRRegClassID];
2922 return Error(RegLoc, "invalid register in register list");
2924 // Store the register.
2925 Registers.push_back(std::pair<unsigned, SMLoc>(Reg, RegLoc));
2927 // This starts immediately after the first register token in the list,
2928 // so we can see either a comma or a minus (range separator) as a legal
2930 while (Parser.getTok().is(AsmToken::Comma) ||
2931 Parser.getTok().is(AsmToken::Minus)) {
2932 if (Parser.getTok().is(AsmToken::Minus)) {
2933 Parser.Lex(); // Eat the minus.
2934 SMLoc AfterMinusLoc = Parser.getTok().getLoc();
2935 int EndReg = tryParseRegister();
2937 return Error(AfterMinusLoc, "register expected");
2938 // Allow Q regs and just interpret them as the two D sub-registers.
2939 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg))
2940 EndReg = getDRegFromQReg(EndReg) + 1;
2941 // If the register is the same as the start reg, there's nothing
2945 // The register must be in the same register class as the first.
2946 if (!RC->contains(EndReg))
2947 return Error(AfterMinusLoc, "invalid register in register list");
2948 // Ranges must go from low to high.
2949 if (MRI->getEncodingValue(Reg) > MRI->getEncodingValue(EndReg))
2950 return Error(AfterMinusLoc, "bad range in register list");
2952 // Add all the registers in the range to the register list.
2953 while (Reg != EndReg) {
2954 Reg = getNextRegister(Reg);
2955 Registers.push_back(std::pair<unsigned, SMLoc>(Reg, RegLoc));
2959 Parser.Lex(); // Eat the comma.
2960 RegLoc = Parser.getTok().getLoc();
2962 const AsmToken RegTok = Parser.getTok();
2963 Reg = tryParseRegister();
2965 return Error(RegLoc, "register expected");
2966 // Allow Q regs and just interpret them as the two D sub-registers.
2967 bool isQReg = false;
2968 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
2969 Reg = getDRegFromQReg(Reg);
2972 // The register must be in the same register class as the first.
2973 if (!RC->contains(Reg))
2974 return Error(RegLoc, "invalid register in register list");
2975 // List must be monotonically increasing.
2976 if (MRI->getEncodingValue(Reg) < MRI->getEncodingValue(OldReg)) {
2977 if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
2978 Warning(RegLoc, "register list not in ascending order");
2980 return Error(RegLoc, "register list not in ascending order");
2982 if (MRI->getEncodingValue(Reg) == MRI->getEncodingValue(OldReg)) {
2983 Warning(RegLoc, "duplicated register (" + RegTok.getString() +
2984 ") in register list");
2987 // VFP register lists must also be contiguous.
2988 // It's OK to use the enumeration values directly here rather, as the
2989 // VFP register classes have the enum sorted properly.
2990 if (RC != &ARMMCRegisterClasses[ARM::GPRRegClassID] &&
2992 return Error(RegLoc, "non-contiguous register range");
2993 Registers.push_back(std::pair<unsigned, SMLoc>(Reg, RegLoc));
2995 Registers.push_back(std::pair<unsigned, SMLoc>(++Reg, RegLoc));
2998 if (Parser.getTok().isNot(AsmToken::RCurly))
2999 return Error(Parser.getTok().getLoc(), "'}' expected");
3000 SMLoc E = Parser.getTok().getEndLoc();
3001 Parser.Lex(); // Eat '}' token.
3003 // Push the register list operand.
3004 Operands.push_back(ARMOperand::CreateRegList(Registers, S, E));
3006 // The ARM system instruction variants for LDM/STM have a '^' token here.
3007 if (Parser.getTok().is(AsmToken::Caret)) {
3008 Operands.push_back(ARMOperand::CreateToken("^",Parser.getTok().getLoc()));
3009 Parser.Lex(); // Eat '^' token.
3015 // Helper function to parse the lane index for vector lists.
3016 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3017 parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index, SMLoc &EndLoc) {
3018 Index = 0; // Always return a defined index value.
3019 if (Parser.getTok().is(AsmToken::LBrac)) {
3020 Parser.Lex(); // Eat the '['.
3021 if (Parser.getTok().is(AsmToken::RBrac)) {
3022 // "Dn[]" is the 'all lanes' syntax.
3023 LaneKind = AllLanes;
3024 EndLoc = Parser.getTok().getEndLoc();
3025 Parser.Lex(); // Eat the ']'.
3026 return MatchOperand_Success;
3029 // There's an optional '#' token here. Normally there wouldn't be, but
3030 // inline assemble puts one in, and it's friendly to accept that.
3031 if (Parser.getTok().is(AsmToken::Hash))
3032 Parser.Lex(); // Eat the '#'
3034 const MCExpr *LaneIndex;
3035 SMLoc Loc = Parser.getTok().getLoc();
3036 if (getParser().parseExpression(LaneIndex)) {
3037 Error(Loc, "illegal expression");
3038 return MatchOperand_ParseFail;
3040 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LaneIndex);
3042 Error(Loc, "lane index must be empty or an integer");
3043 return MatchOperand_ParseFail;
3045 if (Parser.getTok().isNot(AsmToken::RBrac)) {
3046 Error(Parser.getTok().getLoc(), "']' expected");
3047 return MatchOperand_ParseFail;
3049 EndLoc = Parser.getTok().getEndLoc();
3050 Parser.Lex(); // Eat the ']'.
3051 int64_t Val = CE->getValue();
3053 // FIXME: Make this range check context sensitive for .8, .16, .32.
3054 if (Val < 0 || Val > 7) {
3055 Error(Parser.getTok().getLoc(), "lane index out of range");
3056 return MatchOperand_ParseFail;
3059 LaneKind = IndexedLane;
3060 return MatchOperand_Success;
3063 return MatchOperand_Success;
3066 // parse a vector register list
3067 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3068 parseVectorList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3069 VectorLaneTy LaneKind;
3071 SMLoc S = Parser.getTok().getLoc();
3072 // As an extension (to match gas), support a plain D register or Q register
3073 // (without encosing curly braces) as a single or double entry list,
3075 if (Parser.getTok().is(AsmToken::Identifier)) {
3076 SMLoc E = Parser.getTok().getEndLoc();
3077 int Reg = tryParseRegister();
3079 return MatchOperand_NoMatch;
3080 if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg)) {
3081 OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex, E);
3082 if (Res != MatchOperand_Success)
3086 Operands.push_back(ARMOperand::CreateVectorList(Reg, 1, false, S, E));
3089 Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 1, false,
3093 Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 1,
3098 return MatchOperand_Success;
3100 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3101 Reg = getDRegFromQReg(Reg);
3102 OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex, E);
3103 if (Res != MatchOperand_Success)
3107 Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0,
3108 &ARMMCRegisterClasses[ARM::DPairRegClassID]);
3109 Operands.push_back(ARMOperand::CreateVectorList(Reg, 2, false, S, E));
3112 Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0,
3113 &ARMMCRegisterClasses[ARM::DPairRegClassID]);
3114 Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 2, false,
3118 Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 2,
3123 return MatchOperand_Success;
3125 Error(S, "vector register expected");
3126 return MatchOperand_ParseFail;
3129 if (Parser.getTok().isNot(AsmToken::LCurly))
3130 return MatchOperand_NoMatch;
3132 Parser.Lex(); // Eat '{' token.
3133 SMLoc RegLoc = Parser.getTok().getLoc();
3135 int Reg = tryParseRegister();
3137 Error(RegLoc, "register expected");
3138 return MatchOperand_ParseFail;
3142 unsigned FirstReg = Reg;
3143 // The list is of D registers, but we also allow Q regs and just interpret
3144 // them as the two D sub-registers.
3145 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3146 FirstReg = Reg = getDRegFromQReg(Reg);
3147 Spacing = 1; // double-spacing requires explicit D registers, otherwise
3148 // it's ambiguous with four-register single spaced.
3154 if (parseVectorLane(LaneKind, LaneIndex, E) != MatchOperand_Success)
3155 return MatchOperand_ParseFail;
3157 while (Parser.getTok().is(AsmToken::Comma) ||
3158 Parser.getTok().is(AsmToken::Minus)) {
3159 if (Parser.getTok().is(AsmToken::Minus)) {
3161 Spacing = 1; // Register range implies a single spaced list.
3162 else if (Spacing == 2) {
3163 Error(Parser.getTok().getLoc(),
3164 "sequential registers in double spaced list");
3165 return MatchOperand_ParseFail;
3167 Parser.Lex(); // Eat the minus.
3168 SMLoc AfterMinusLoc = Parser.getTok().getLoc();
3169 int EndReg = tryParseRegister();
3171 Error(AfterMinusLoc, "register expected");
3172 return MatchOperand_ParseFail;
3174 // Allow Q regs and just interpret them as the two D sub-registers.
3175 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg))
3176 EndReg = getDRegFromQReg(EndReg) + 1;
3177 // If the register is the same as the start reg, there's nothing
3181 // The register must be in the same register class as the first.
3182 if (!ARMMCRegisterClasses[ARM::DPRRegClassID].contains(EndReg)) {
3183 Error(AfterMinusLoc, "invalid register in register list");
3184 return MatchOperand_ParseFail;
3186 // Ranges must go from low to high.
3188 Error(AfterMinusLoc, "bad range in register list");
3189 return MatchOperand_ParseFail;
3191 // Parse the lane specifier if present.
3192 VectorLaneTy NextLaneKind;
3193 unsigned NextLaneIndex;
3194 if (parseVectorLane(NextLaneKind, NextLaneIndex, E) !=
3195 MatchOperand_Success)
3196 return MatchOperand_ParseFail;
3197 if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
3198 Error(AfterMinusLoc, "mismatched lane index in register list");
3199 return MatchOperand_ParseFail;
3202 // Add all the registers in the range to the register list.
3203 Count += EndReg - Reg;
3207 Parser.Lex(); // Eat the comma.
3208 RegLoc = Parser.getTok().getLoc();
3210 Reg = tryParseRegister();
3212 Error(RegLoc, "register expected");
3213 return MatchOperand_ParseFail;
3215 // vector register lists must be contiguous.
3216 // It's OK to use the enumeration values directly here rather, as the
3217 // VFP register classes have the enum sorted properly.
3219 // The list is of D registers, but we also allow Q regs and just interpret
3220 // them as the two D sub-registers.
3221 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3223 Spacing = 1; // Register range implies a single spaced list.
3224 else if (Spacing == 2) {
3226 "invalid register in double-spaced list (must be 'D' register')");
3227 return MatchOperand_ParseFail;
3229 Reg = getDRegFromQReg(Reg);
3230 if (Reg != OldReg + 1) {
3231 Error(RegLoc, "non-contiguous register range");
3232 return MatchOperand_ParseFail;
3236 // Parse the lane specifier if present.
3237 VectorLaneTy NextLaneKind;
3238 unsigned NextLaneIndex;
3239 SMLoc LaneLoc = Parser.getTok().getLoc();
3240 if (parseVectorLane(NextLaneKind, NextLaneIndex, E) !=
3241 MatchOperand_Success)
3242 return MatchOperand_ParseFail;
3243 if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
3244 Error(LaneLoc, "mismatched lane index in register list");
3245 return MatchOperand_ParseFail;
3249 // Normal D register.
3250 // Figure out the register spacing (single or double) of the list if
3251 // we don't know it already.
3253 Spacing = 1 + (Reg == OldReg + 2);
3255 // Just check that it's contiguous and keep going.
3256 if (Reg != OldReg + Spacing) {
3257 Error(RegLoc, "non-contiguous register range");
3258 return MatchOperand_ParseFail;
3261 // Parse the lane specifier if present.
3262 VectorLaneTy NextLaneKind;
3263 unsigned NextLaneIndex;
3264 SMLoc EndLoc = Parser.getTok().getLoc();
3265 if (parseVectorLane(NextLaneKind, NextLaneIndex, E) != MatchOperand_Success)
3266 return MatchOperand_ParseFail;
3267 if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
3268 Error(EndLoc, "mismatched lane index in register list");
3269 return MatchOperand_ParseFail;
3273 if (Parser.getTok().isNot(AsmToken::RCurly)) {
3274 Error(Parser.getTok().getLoc(), "'}' expected");
3275 return MatchOperand_ParseFail;
3277 E = Parser.getTok().getEndLoc();
3278 Parser.Lex(); // Eat '}' token.
3282 // Two-register operands have been converted to the
3283 // composite register classes.
3285 const MCRegisterClass *RC = (Spacing == 1) ?
3286 &ARMMCRegisterClasses[ARM::DPairRegClassID] :
3287 &ARMMCRegisterClasses[ARM::DPairSpcRegClassID];
3288 FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC);
3291 Operands.push_back(ARMOperand::CreateVectorList(FirstReg, Count,
3292 (Spacing == 2), S, E));
3295 // Two-register operands have been converted to the
3296 // composite register classes.
3298 const MCRegisterClass *RC = (Spacing == 1) ?
3299 &ARMMCRegisterClasses[ARM::DPairRegClassID] :
3300 &ARMMCRegisterClasses[ARM::DPairSpcRegClassID];
3301 FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC);
3303 Operands.push_back(ARMOperand::CreateVectorListAllLanes(FirstReg, Count,
3308 Operands.push_back(ARMOperand::CreateVectorListIndexed(FirstReg, Count,
3314 return MatchOperand_Success;
3317 /// parseMemBarrierOptOperand - Try to parse DSB/DMB data barrier options.
3318 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3319 parseMemBarrierOptOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3320 SMLoc S = Parser.getTok().getLoc();
3321 const AsmToken &Tok = Parser.getTok();
3324 if (Tok.is(AsmToken::Identifier)) {
3325 StringRef OptStr = Tok.getString();
3327 Opt = StringSwitch<unsigned>(OptStr.slice(0, OptStr.size()).lower())
3328 .Case("sy", ARM_MB::SY)
3329 .Case("st", ARM_MB::ST)
3330 .Case("sh", ARM_MB::ISH)
3331 .Case("ish", ARM_MB::ISH)
3332 .Case("shst", ARM_MB::ISHST)
3333 .Case("ishst", ARM_MB::ISHST)
3334 .Case("nsh", ARM_MB::NSH)
3335 .Case("un", ARM_MB::NSH)
3336 .Case("nshst", ARM_MB::NSHST)
3337 .Case("unst", ARM_MB::NSHST)
3338 .Case("osh", ARM_MB::OSH)
3339 .Case("oshst", ARM_MB::OSHST)
3343 return MatchOperand_NoMatch;
3345 Parser.Lex(); // Eat identifier token.
3346 } else if (Tok.is(AsmToken::Hash) ||
3347 Tok.is(AsmToken::Dollar) ||
3348 Tok.is(AsmToken::Integer)) {
3349 if (Parser.getTok().isNot(AsmToken::Integer))
3350 Parser.Lex(); // Eat the '#'.
3351 SMLoc Loc = Parser.getTok().getLoc();
3353 const MCExpr *MemBarrierID;
3354 if (getParser().parseExpression(MemBarrierID)) {
3355 Error(Loc, "illegal expression");
3356 return MatchOperand_ParseFail;
3359 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(MemBarrierID);
3361 Error(Loc, "constant expression expected");
3362 return MatchOperand_ParseFail;
3365 int Val = CE->getValue();
3367 Error(Loc, "immediate value out of range");
3368 return MatchOperand_ParseFail;
3371 Opt = ARM_MB::RESERVED_0 + Val;
3373 return MatchOperand_ParseFail;
3375 Operands.push_back(ARMOperand::CreateMemBarrierOpt((ARM_MB::MemBOpt)Opt, S));
3376 return MatchOperand_Success;
3379 /// parseProcIFlagsOperand - Try to parse iflags from CPS instruction.
3380 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3381 parseProcIFlagsOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3382 SMLoc S = Parser.getTok().getLoc();
3383 const AsmToken &Tok = Parser.getTok();
3384 if (!Tok.is(AsmToken::Identifier))
3385 return MatchOperand_NoMatch;
3386 StringRef IFlagsStr = Tok.getString();
3388 // An iflags string of "none" is interpreted to mean that none of the AIF
3389 // bits are set. Not a terribly useful instruction, but a valid encoding.
3390 unsigned IFlags = 0;
3391 if (IFlagsStr != "none") {
3392 for (int i = 0, e = IFlagsStr.size(); i != e; ++i) {
3393 unsigned Flag = StringSwitch<unsigned>(IFlagsStr.substr(i, 1))
3394 .Case("a", ARM_PROC::A)
3395 .Case("i", ARM_PROC::I)
3396 .Case("f", ARM_PROC::F)
3399 // If some specific iflag is already set, it means that some letter is
3400 // present more than once, this is not acceptable.
3401 if (Flag == ~0U || (IFlags & Flag))
3402 return MatchOperand_NoMatch;
3408 Parser.Lex(); // Eat identifier token.
3409 Operands.push_back(ARMOperand::CreateProcIFlags((ARM_PROC::IFlags)IFlags, S));
3410 return MatchOperand_Success;
3413 /// parseMSRMaskOperand - Try to parse mask flags from MSR instruction.
3414 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3415 parseMSRMaskOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3416 SMLoc S = Parser.getTok().getLoc();
3417 const AsmToken &Tok = Parser.getTok();
3418 if (!Tok.is(AsmToken::Identifier))
3419 return MatchOperand_NoMatch;
3420 StringRef Mask = Tok.getString();
3423 // See ARMv6-M 10.1.1
3424 std::string Name = Mask.lower();
3425 unsigned FlagsVal = StringSwitch<unsigned>(Name)
3426 // Note: in the documentation:
3427 // ARM deprecates using MSR APSR without a _<bits> qualifier as an alias
3428 // for MSR APSR_nzcvq.
3429 // but we do make it an alias here. This is so to get the "mask encoding"
3430 // bits correct on MSR APSR writes.
3432 // FIXME: Note the 0xc00 "mask encoding" bits version of the registers
3433 // should really only be allowed when writing a special register. Note
3434 // they get dropped in the MRS instruction reading a special register as
3435 // the SYSm field is only 8 bits.
3437 // FIXME: the _g and _nzcvqg versions are only allowed if the processor
3438 // includes the DSP extension but that is not checked.
3439 .Case("apsr", 0x800)
3440 .Case("apsr_nzcvq", 0x800)
3441 .Case("apsr_g", 0x400)
3442 .Case("apsr_nzcvqg", 0xc00)
3443 .Case("iapsr", 0x801)
3444 .Case("iapsr_nzcvq", 0x801)
3445 .Case("iapsr_g", 0x401)
3446 .Case("iapsr_nzcvqg", 0xc01)
3447 .Case("eapsr", 0x802)
3448 .Case("eapsr_nzcvq", 0x802)
3449 .Case("eapsr_g", 0x402)
3450 .Case("eapsr_nzcvqg", 0xc02)
3451 .Case("xpsr", 0x803)
3452 .Case("xpsr_nzcvq", 0x803)
3453 .Case("xpsr_g", 0x403)
3454 .Case("xpsr_nzcvqg", 0xc03)
3455 .Case("ipsr", 0x805)
3456 .Case("epsr", 0x806)
3457 .Case("iepsr", 0x807)
3460 .Case("primask", 0x810)
3461 .Case("basepri", 0x811)
3462 .Case("basepri_max", 0x812)
3463 .Case("faultmask", 0x813)
3464 .Case("control", 0x814)
3467 if (FlagsVal == ~0U)
3468 return MatchOperand_NoMatch;
3470 if (!hasV7Ops() && FlagsVal >= 0x811 && FlagsVal <= 0x813)
3471 // basepri, basepri_max and faultmask only valid for V7m.
3472 return MatchOperand_NoMatch;
3474 Parser.Lex(); // Eat identifier token.
3475 Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S));
3476 return MatchOperand_Success;
3479 // Split spec_reg from flag, example: CPSR_sxf => "CPSR" and "sxf"
3480 size_t Start = 0, Next = Mask.find('_');
3481 StringRef Flags = "";
3482 std::string SpecReg = Mask.slice(Start, Next).lower();
3483 if (Next != StringRef::npos)
3484 Flags = Mask.slice(Next+1, Mask.size());
3486 // FlagsVal contains the complete mask:
3488 // 4: Special Reg (cpsr, apsr => 0; spsr => 1)
3489 unsigned FlagsVal = 0;
3491 if (SpecReg == "apsr") {
3492 FlagsVal = StringSwitch<unsigned>(Flags)
3493 .Case("nzcvq", 0x8) // same as CPSR_f
3494 .Case("g", 0x4) // same as CPSR_s
3495 .Case("nzcvqg", 0xc) // same as CPSR_fs
3498 if (FlagsVal == ~0U) {
3500 return MatchOperand_NoMatch;
3502 FlagsVal = 8; // No flag
3504 } else if (SpecReg == "cpsr" || SpecReg == "spsr") {
3505 // cpsr_all is an alias for cpsr_fc, as is plain cpsr.
3506 if (Flags == "all" || Flags == "")
3508 for (int i = 0, e = Flags.size(); i != e; ++i) {
3509 unsigned Flag = StringSwitch<unsigned>(Flags.substr(i, 1))
3516 // If some specific flag is already set, it means that some letter is
3517 // present more than once, this is not acceptable.
3518 if (FlagsVal == ~0U || (FlagsVal & Flag))
3519 return MatchOperand_NoMatch;
3522 } else // No match for special register.
3523 return MatchOperand_NoMatch;
3525 // Special register without flags is NOT equivalent to "fc" flags.
3526 // NOTE: This is a divergence from gas' behavior. Uncommenting the following
3527 // two lines would enable gas compatibility at the expense of breaking
3533 // Bit 4: Special Reg (cpsr, apsr => 0; spsr => 1)
3534 if (SpecReg == "spsr")
3537 Parser.Lex(); // Eat identifier token.
3538 Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S));
3539 return MatchOperand_Success;
3542 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3543 parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands, StringRef Op,
3544 int Low, int High) {
3545 const AsmToken &Tok = Parser.getTok();
3546 if (Tok.isNot(AsmToken::Identifier)) {
3547 Error(Parser.getTok().getLoc(), Op + " operand expected.");
3548 return MatchOperand_ParseFail;
3550 StringRef ShiftName = Tok.getString();
3551 std::string LowerOp = Op.lower();
3552 std::string UpperOp = Op.upper();
3553 if (ShiftName != LowerOp && ShiftName != UpperOp) {
3554 Error(Parser.getTok().getLoc(), Op + " operand expected.");
3555 return MatchOperand_ParseFail;
3557 Parser.Lex(); // Eat shift type token.
3559 // There must be a '#' and a shift amount.
3560 if (Parser.getTok().isNot(AsmToken::Hash) &&
3561 Parser.getTok().isNot(AsmToken::Dollar)) {
3562 Error(Parser.getTok().getLoc(), "'#' expected");
3563 return MatchOperand_ParseFail;
3565 Parser.Lex(); // Eat hash token.
3567 const MCExpr *ShiftAmount;
3568 SMLoc Loc = Parser.getTok().getLoc();
3570 if (getParser().parseExpression(ShiftAmount, EndLoc)) {
3571 Error(Loc, "illegal expression");
3572 return MatchOperand_ParseFail;
3574 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
3576 Error(Loc, "constant expression expected");
3577 return MatchOperand_ParseFail;
3579 int Val = CE->getValue();
3580 if (Val < Low || Val > High) {
3581 Error(Loc, "immediate value out of range");
3582 return MatchOperand_ParseFail;
3585 Operands.push_back(ARMOperand::CreateImm(CE, Loc, EndLoc));
3587 return MatchOperand_Success;
3590 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3591 parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3592 const AsmToken &Tok = Parser.getTok();
3593 SMLoc S = Tok.getLoc();
3594 if (Tok.isNot(AsmToken::Identifier)) {
3595 Error(S, "'be' or 'le' operand expected");
3596 return MatchOperand_ParseFail;
3598 int Val = StringSwitch<int>(Tok.getString())
3602 Parser.Lex(); // Eat the token.
3605 Error(S, "'be' or 'le' operand expected");
3606 return MatchOperand_ParseFail;
3608 Operands.push_back(ARMOperand::CreateImm(MCConstantExpr::Create(Val,
3610 S, Tok.getEndLoc()));
3611 return MatchOperand_Success;
3614 /// parseShifterImm - Parse the shifter immediate operand for SSAT/USAT
3615 /// instructions. Legal values are:
3616 /// lsl #n 'n' in [0,31]
3617 /// asr #n 'n' in [1,32]
3618 /// n == 32 encoded as n == 0.
3619 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3620 parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3621 const AsmToken &Tok = Parser.getTok();
3622 SMLoc S = Tok.getLoc();
3623 if (Tok.isNot(AsmToken::Identifier)) {
3624 Error(S, "shift operator 'asr' or 'lsl' expected");
3625 return MatchOperand_ParseFail;
3627 StringRef ShiftName = Tok.getString();
3629 if (ShiftName == "lsl" || ShiftName == "LSL")
3631 else if (ShiftName == "asr" || ShiftName == "ASR")
3634 Error(S, "shift operator 'asr' or 'lsl' expected");
3635 return MatchOperand_ParseFail;
3637 Parser.Lex(); // Eat the operator.
3639 // A '#' and a shift amount.
3640 if (Parser.getTok().isNot(AsmToken::Hash) &&
3641 Parser.getTok().isNot(AsmToken::Dollar)) {
3642 Error(Parser.getTok().getLoc(), "'#' expected");
3643 return MatchOperand_ParseFail;
3645 Parser.Lex(); // Eat hash token.
3646 SMLoc ExLoc = Parser.getTok().getLoc();
3648 const MCExpr *ShiftAmount;
3650 if (getParser().parseExpression(ShiftAmount, EndLoc)) {
3651 Error(ExLoc, "malformed shift expression");
3652 return MatchOperand_ParseFail;
3654 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
3656 Error(ExLoc, "shift amount must be an immediate");
3657 return MatchOperand_ParseFail;
3660 int64_t Val = CE->getValue();
3662 // Shift amount must be in [1,32]
3663 if (Val < 1 || Val > 32) {
3664 Error(ExLoc, "'asr' shift amount must be in range [1,32]");
3665 return MatchOperand_ParseFail;
3667 // asr #32 encoded as asr #0, but is not allowed in Thumb2 mode.
3668 if (isThumb() && Val == 32) {
3669 Error(ExLoc, "'asr #32' shift amount not allowed in Thumb mode");
3670 return MatchOperand_ParseFail;
3672 if (Val == 32) Val = 0;
3674 // Shift amount must be in [1,32]
3675 if (Val < 0 || Val > 31) {
3676 Error(ExLoc, "'lsr' shift amount must be in range [0,31]");
3677 return MatchOperand_ParseFail;
3681 Operands.push_back(ARMOperand::CreateShifterImm(isASR, Val, S, EndLoc));
3683 return MatchOperand_Success;
3686 /// parseRotImm - Parse the shifter immediate operand for SXTB/UXTB family
3687 /// of instructions. Legal values are:
3688 /// ror #n 'n' in {0, 8, 16, 24}
3689 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3690 parseRotImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3691 const AsmToken &Tok = Parser.getTok();
3692 SMLoc S = Tok.getLoc();
3693 if (Tok.isNot(AsmToken::Identifier))
3694 return MatchOperand_NoMatch;
3695 StringRef ShiftName = Tok.getString();
3696 if (ShiftName != "ror" && ShiftName != "ROR")
3697 return MatchOperand_NoMatch;
3698 Parser.Lex(); // Eat the operator.
3700 // A '#' and a rotate amount.
3701 if (Parser.getTok().isNot(AsmToken::Hash) &&
3702 Parser.getTok().isNot(AsmToken::Dollar)) {
3703 Error(Parser.getTok().getLoc(), "'#' expected");
3704 return MatchOperand_ParseFail;
3706 Parser.Lex(); // Eat hash token.
3707 SMLoc ExLoc = Parser.getTok().getLoc();
3709 const MCExpr *ShiftAmount;
3711 if (getParser().parseExpression(ShiftAmount, EndLoc)) {
3712 Error(ExLoc, "malformed rotate expression");
3713 return MatchOperand_ParseFail;
3715 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
3717 Error(ExLoc, "rotate amount must be an immediate");
3718 return MatchOperand_ParseFail;
3721 int64_t Val = CE->getValue();
3722 // Shift amount must be in {0, 8, 16, 24} (0 is undocumented extension)
3723 // normally, zero is represented in asm by omitting the rotate operand
3725 if (Val != 8 && Val != 16 && Val != 24 && Val != 0) {
3726 Error(ExLoc, "'ror' rotate amount must be 8, 16, or 24");
3727 return MatchOperand_ParseFail;
3730 Operands.push_back(ARMOperand::CreateRotImm(Val, S, EndLoc));
3732 return MatchOperand_Success;
3735 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3736 parseBitfield(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3737 SMLoc S = Parser.getTok().getLoc();
3738 // The bitfield descriptor is really two operands, the LSB and the width.
3739 if (Parser.getTok().isNot(AsmToken::Hash) &&
3740 Parser.getTok().isNot(AsmToken::Dollar)) {
3741 Error(Parser.getTok().getLoc(), "'#' expected");
3742 return MatchOperand_ParseFail;
3744 Parser.Lex(); // Eat hash token.
3746 const MCExpr *LSBExpr;
3747 SMLoc E = Parser.getTok().getLoc();
3748 if (getParser().parseExpression(LSBExpr)) {
3749 Error(E, "malformed immediate expression");
3750 return MatchOperand_ParseFail;
3752 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LSBExpr);
3754 Error(E, "'lsb' operand must be an immediate");
3755 return MatchOperand_ParseFail;
3758 int64_t LSB = CE->getValue();
3759 // The LSB must be in the range [0,31]
3760 if (LSB < 0 || LSB > 31) {
3761 Error(E, "'lsb' operand must be in the range [0,31]");
3762 return MatchOperand_ParseFail;
3764 E = Parser.getTok().getLoc();
3766 // Expect another immediate operand.
3767 if (Parser.getTok().isNot(AsmToken::Comma)) {
3768 Error(Parser.getTok().getLoc(), "too few operands");
3769 return MatchOperand_ParseFail;
3771 Parser.Lex(); // Eat hash token.
3772 if (Parser.getTok().isNot(AsmToken::Hash) &&
3773 Parser.getTok().isNot(AsmToken::Dollar)) {
3774 Error(Parser.getTok().getLoc(), "'#' expected");
3775 return MatchOperand_ParseFail;
3777 Parser.Lex(); // Eat hash token.
3779 const MCExpr *WidthExpr;
3781 if (getParser().parseExpression(WidthExpr, EndLoc)) {
3782 Error(E, "malformed immediate expression");
3783 return MatchOperand_ParseFail;
3785 CE = dyn_cast<MCConstantExpr>(WidthExpr);
3787 Error(E, "'width' operand must be an immediate");
3788 return MatchOperand_ParseFail;
3791 int64_t Width = CE->getValue();
3792 // The LSB must be in the range [1,32-lsb]
3793 if (Width < 1 || Width > 32 - LSB) {
3794 Error(E, "'width' operand must be in the range [1,32-lsb]");
3795 return MatchOperand_ParseFail;
3798 Operands.push_back(ARMOperand::CreateBitfield(LSB, Width, S, EndLoc));
3800 return MatchOperand_Success;
3803 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3804 parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3805 // Check for a post-index addressing register operand. Specifically:
3806 // postidx_reg := '+' register {, shift}
3807 // | '-' register {, shift}
3808 // | register {, shift}
3810 // This method must return MatchOperand_NoMatch without consuming any tokens
3811 // in the case where there is no match, as other alternatives take other
3813 AsmToken Tok = Parser.getTok();
3814 SMLoc S = Tok.getLoc();
3815 bool haveEaten = false;
3817 if (Tok.is(AsmToken::Plus)) {
3818 Parser.Lex(); // Eat the '+' token.
3820 } else if (Tok.is(AsmToken::Minus)) {
3821 Parser.Lex(); // Eat the '-' token.
3826 SMLoc E = Parser.getTok().getEndLoc();
3827 int Reg = tryParseRegister();
3830 return MatchOperand_NoMatch;
3831 Error(Parser.getTok().getLoc(), "register expected");
3832 return MatchOperand_ParseFail;
3835 ARM_AM::ShiftOpc ShiftTy = ARM_AM::no_shift;
3836 unsigned ShiftImm = 0;
3837 if (Parser.getTok().is(AsmToken::Comma)) {
3838 Parser.Lex(); // Eat the ','.
3839 if (parseMemRegOffsetShift(ShiftTy, ShiftImm))
3840 return MatchOperand_ParseFail;
3842 // FIXME: Only approximates end...may include intervening whitespace.
3843 E = Parser.getTok().getLoc();
3846 Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ShiftTy,
3849 return MatchOperand_Success;
3852 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3853 parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3854 // Check for a post-index addressing register operand. Specifically:
3855 // am3offset := '+' register
3862 // This method must return MatchOperand_NoMatch without consuming any tokens
3863 // in the case where there is no match, as other alternatives take other
3865 AsmToken Tok = Parser.getTok();
3866 SMLoc S = Tok.getLoc();
3868 // Do immediates first, as we always parse those if we have a '#'.
3869 if (Parser.getTok().is(AsmToken::Hash) ||
3870 Parser.getTok().is(AsmToken::Dollar)) {
3871 Parser.Lex(); // Eat the '#'.
3872 // Explicitly look for a '-', as we need to encode negative zero
3874 bool isNegative = Parser.getTok().is(AsmToken::Minus);
3875 const MCExpr *Offset;
3877 if (getParser().parseExpression(Offset, E))
3878 return MatchOperand_ParseFail;
3879 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
3881 Error(S, "constant expression expected");
3882 return MatchOperand_ParseFail;
3884 // Negative zero is encoded as the flag value INT32_MIN.
3885 int32_t Val = CE->getValue();
3886 if (isNegative && Val == 0)
3890 ARMOperand::CreateImm(MCConstantExpr::Create(Val, getContext()), S, E));
3892 return MatchOperand_Success;
3896 bool haveEaten = false;
3898 if (Tok.is(AsmToken::Plus)) {
3899 Parser.Lex(); // Eat the '+' token.
3901 } else if (Tok.is(AsmToken::Minus)) {
3902 Parser.Lex(); // Eat the '-' token.
3907 Tok = Parser.getTok();
3908 int Reg = tryParseRegister();
3911 return MatchOperand_NoMatch;
3912 Error(Tok.getLoc(), "register expected");
3913 return MatchOperand_ParseFail;
3916 Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ARM_AM::no_shift,
3917 0, S, Tok.getEndLoc()));
3919 return MatchOperand_Success;
3922 /// cvtT2LdrdPre - Convert parsed operands to MCInst.
3923 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
3924 /// when they refer multiple MIOperands inside a single one.
3926 cvtT2LdrdPre(MCInst &Inst,
3927 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3929 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3930 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
3931 // Create a writeback register dummy placeholder.
3932 Inst.addOperand(MCOperand::CreateReg(0));
3934 ((ARMOperand*)Operands[4])->addMemImm8s4OffsetOperands(Inst, 2);
3936 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3939 /// cvtT2StrdPre - Convert parsed operands to MCInst.
3940 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
3941 /// when they refer multiple MIOperands inside a single one.
3943 cvtT2StrdPre(MCInst &Inst,
3944 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3945 // Create a writeback register dummy placeholder.
3946 Inst.addOperand(MCOperand::CreateReg(0));
3948 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3949 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
3951 ((ARMOperand*)Operands[4])->addMemImm8s4OffsetOperands(Inst, 2);
3953 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3956 /// cvtLdWriteBackRegT2AddrModeImm8 - Convert parsed operands to MCInst.
3957 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
3958 /// when they refer multiple MIOperands inside a single one.
3960 cvtLdWriteBackRegT2AddrModeImm8(MCInst &Inst,
3961 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3962 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3964 // Create a writeback register dummy placeholder.
3965 Inst.addOperand(MCOperand::CreateImm(0));
3967 ((ARMOperand*)Operands[3])->addMemImm8OffsetOperands(Inst, 2);
3968 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3971 /// cvtStWriteBackRegT2AddrModeImm8 - Convert parsed operands to MCInst.
3972 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
3973 /// when they refer multiple MIOperands inside a single one.
3975 cvtStWriteBackRegT2AddrModeImm8(MCInst &Inst,
3976 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3977 // Create a writeback register dummy placeholder.
3978 Inst.addOperand(MCOperand::CreateImm(0));
3979 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3980 ((ARMOperand*)Operands[3])->addMemImm8OffsetOperands(Inst, 2);
3981 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3984 /// cvtLdWriteBackRegAddrMode2 - Convert parsed operands to MCInst.
3985 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
3986 /// when they refer multiple MIOperands inside a single one.
3988 cvtLdWriteBackRegAddrMode2(MCInst &Inst,
3989 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3990 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3992 // Create a writeback register dummy placeholder.
3993 Inst.addOperand(MCOperand::CreateImm(0));
3995 ((ARMOperand*)Operands[3])->addAddrMode2Operands(Inst, 3);
3996 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3999 /// cvtLdWriteBackRegAddrModeImm12 - Convert parsed operands to MCInst.
4000 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
4001 /// when they refer multiple MIOperands inside a single one.
4003 cvtLdWriteBackRegAddrModeImm12(MCInst &Inst,
4004 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4005 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
4007 // Create a writeback register dummy placeholder.
4008 Inst.addOperand(MCOperand::CreateImm(0));
4010 ((ARMOperand*)Operands[3])->addMemImm12OffsetOperands(Inst, 2);
4011 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4015 /// cvtStWriteBackRegAddrModeImm12 - Convert parsed operands to MCInst.
4016 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
4017 /// when they refer multiple MIOperands inside a single one.
4019 cvtStWriteBackRegAddrModeImm12(MCInst &Inst,
4020 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4021 // Create a writeback register dummy placeholder.
4022 Inst.addOperand(MCOperand::CreateImm(0));
4023 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
4024 ((ARMOperand*)Operands[3])->addMemImm12OffsetOperands(Inst, 2);
4025 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4028 /// cvtStWriteBackRegAddrMode2 - Convert parsed operands to MCInst.
4029 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
4030 /// when they refer multiple MIOperands inside a single one.
4032 cvtStWriteBackRegAddrMode2(MCInst &Inst,
4033 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4034 // Create a writeback register dummy placeholder.
4035 Inst.addOperand(MCOperand::CreateImm(0));
4036 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
4037 ((ARMOperand*)Operands[3])->addAddrMode2Operands(Inst, 3);
4038 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4041 /// cvtStWriteBackRegAddrMode3 - Convert parsed operands to MCInst.
4042 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
4043 /// when they refer multiple MIOperands inside a single one.
4045 cvtStWriteBackRegAddrMode3(MCInst &Inst,
4046 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4047 // Create a writeback register dummy placeholder.
4048 Inst.addOperand(MCOperand::CreateImm(0));
4049 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
4050 ((ARMOperand*)Operands[3])->addAddrMode3Operands(Inst, 3);
4051 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4054 /// cvtLdExtTWriteBackImm - Convert parsed operands to MCInst.
4055 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
4056 /// when they refer multiple MIOperands inside a single one.
4058 cvtLdExtTWriteBackImm(MCInst &Inst,
4059 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4061 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
4062 // Create a writeback register dummy placeholder.
4063 Inst.addOperand(MCOperand::CreateImm(0));
4065 ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
4067 ((ARMOperand*)Operands[4])->addPostIdxImm8Operands(Inst, 1);
4069 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4072 /// cvtLdExtTWriteBackReg - Convert parsed operands to MCInst.
4073 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
4074 /// when they refer multiple MIOperands inside a single one.
4076 cvtLdExtTWriteBackReg(MCInst &Inst,
4077 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4079 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
4080 // Create a writeback register dummy placeholder.
4081 Inst.addOperand(MCOperand::CreateImm(0));
4083 ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
4085 ((ARMOperand*)Operands[4])->addPostIdxRegOperands(Inst, 2);
4087 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4090 /// cvtStExtTWriteBackImm - Convert parsed operands to MCInst.
4091 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
4092 /// when they refer multiple MIOperands inside a single one.
4094 cvtStExtTWriteBackImm(MCInst &Inst,
4095 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4096 // Create a writeback register dummy placeholder.
4097 Inst.addOperand(MCOperand::CreateImm(0));
4099 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
4101 ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
4103 ((ARMOperand*)Operands[4])->addPostIdxImm8Operands(Inst, 1);
4105 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4108 /// cvtStExtTWriteBackReg - Convert parsed operands to MCInst.
4109 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
4110 /// when they refer multiple MIOperands inside a single one.
4112 cvtStExtTWriteBackReg(MCInst &Inst,
4113 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4114 // Create a writeback register dummy placeholder.
4115 Inst.addOperand(MCOperand::CreateImm(0));
4117 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
4119 ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
4121 ((ARMOperand*)Operands[4])->addPostIdxRegOperands(Inst, 2);
4123 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4126 /// cvtLdrdPre - Convert parsed operands to MCInst.
4127 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
4128 /// when they refer multiple MIOperands inside a single one.
4130 cvtLdrdPre(MCInst &Inst,
4131 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4133 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
4134 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
4135 // Create a writeback register dummy placeholder.
4136 Inst.addOperand(MCOperand::CreateImm(0));
4138 ((ARMOperand*)Operands[4])->addAddrMode3Operands(Inst, 3);
4140 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4143 /// cvtStrdPre - Convert parsed operands to MCInst.
4144 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
4145 /// when they refer multiple MIOperands inside a single one.
4147 cvtStrdPre(MCInst &Inst,
4148 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4149 // Create a writeback register dummy placeholder.
4150 Inst.addOperand(MCOperand::CreateImm(0));
4152 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
4153 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
4155 ((ARMOperand*)Operands[4])->addAddrMode3Operands(Inst, 3);
4157 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4160 /// cvtLdWriteBackRegAddrMode3 - Convert parsed operands to MCInst.
4161 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
4162 /// when they refer multiple MIOperands inside a single one.
4164 cvtLdWriteBackRegAddrMode3(MCInst &Inst,
4165 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4166 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
4167 // Create a writeback register dummy placeholder.
4168 Inst.addOperand(MCOperand::CreateImm(0));
4169 ((ARMOperand*)Operands[3])->addAddrMode3Operands(Inst, 3);
4170 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4173 /// cvtThumbMultiply - Convert parsed operands to MCInst.
4174 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
4175 /// when they refer multiple MIOperands inside a single one.
4177 cvtThumbMultiply(MCInst &Inst,
4178 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4179 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
4180 ((ARMOperand*)Operands[1])->addCCOutOperands(Inst, 1);
4181 // If we have a three-operand form, make sure to set Rn to be the operand
4182 // that isn't the same as Rd.
4184 if (Operands.size() == 6 &&
4185 ((ARMOperand*)Operands[4])->getReg() ==
4186 ((ARMOperand*)Operands[3])->getReg())
4188 ((ARMOperand*)Operands[RegOp])->addRegOperands(Inst, 1);
4189 Inst.addOperand(Inst.getOperand(0));
4190 ((ARMOperand*)Operands[2])->addCondCodeOperands(Inst, 2);
4194 cvtVLDwbFixed(MCInst &Inst,
4195 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4197 ((ARMOperand*)Operands[3])->addVecListOperands(Inst, 1);
4198 // Create a writeback register dummy placeholder.
4199 Inst.addOperand(MCOperand::CreateImm(0));
4201 ((ARMOperand*)Operands[4])->addAlignedMemoryOperands(Inst, 2);
4203 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4207 cvtVLDwbRegister(MCInst &Inst,
4208 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4210 ((ARMOperand*)Operands[3])->addVecListOperands(Inst, 1);
4211 // Create a writeback register dummy placeholder.
4212 Inst.addOperand(MCOperand::CreateImm(0));
4214 ((ARMOperand*)Operands[4])->addAlignedMemoryOperands(Inst, 2);
4216 ((ARMOperand*)Operands[5])->addRegOperands(Inst, 1);
4218 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4222 cvtVSTwbFixed(MCInst &Inst,
4223 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4224 // Create a writeback register dummy placeholder.
4225 Inst.addOperand(MCOperand::CreateImm(0));
4227 ((ARMOperand*)Operands[4])->addAlignedMemoryOperands(Inst, 2);
4229 ((ARMOperand*)Operands[3])->addVecListOperands(Inst, 1);
4231 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4235 cvtVSTwbRegister(MCInst &Inst,
4236 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4237 // Create a writeback register dummy placeholder.
4238 Inst.addOperand(MCOperand::CreateImm(0));
4240 ((ARMOperand*)Operands[4])->addAlignedMemoryOperands(Inst, 2);
4242 ((ARMOperand*)Operands[5])->addRegOperands(Inst, 1);
4244 ((ARMOperand*)Operands[3])->addVecListOperands(Inst, 1);
4246 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4249 /// Parse an ARM memory expression, return false if successful else return true
4250 /// or an error. The first token must be a '[' when called.
4252 parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4254 assert(Parser.getTok().is(AsmToken::LBrac) &&
4255 "Token is not a Left Bracket");
4256 S = Parser.getTok().getLoc();
4257 Parser.Lex(); // Eat left bracket token.
4259 const AsmToken &BaseRegTok = Parser.getTok();
4260 int BaseRegNum = tryParseRegister();
4261 if (BaseRegNum == -1)
4262 return Error(BaseRegTok.getLoc(), "register expected");
4264 // The next token must either be a comma, a colon or a closing bracket.
4265 const AsmToken &Tok = Parser.getTok();
4266 if (!Tok.is(AsmToken::Colon) && !Tok.is(AsmToken::Comma) &&
4267 !Tok.is(AsmToken::RBrac))
4268 return Error(Tok.getLoc(), "malformed memory operand");
4270 if (Tok.is(AsmToken::RBrac)) {
4271 E = Tok.getEndLoc();
4272 Parser.Lex(); // Eat right bracket token.
4274 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, 0, ARM_AM::no_shift,
4275 0, 0, false, S, E));
4277 // If there's a pre-indexing writeback marker, '!', just add it as a token
4278 // operand. It's rather odd, but syntactically valid.
4279 if (Parser.getTok().is(AsmToken::Exclaim)) {
4280 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4281 Parser.Lex(); // Eat the '!'.
4287 assert((Tok.is(AsmToken::Colon) || Tok.is(AsmToken::Comma)) &&
4288 "Lost colon or comma in memory operand?!");
4289 if (Tok.is(AsmToken::Comma)) {
4290 Parser.Lex(); // Eat the comma.
4293 // If we have a ':', it's an alignment specifier.
4294 if (Parser.getTok().is(AsmToken::Colon)) {
4295 Parser.Lex(); // Eat the ':'.
4296 E = Parser.getTok().getLoc();
4299 if (getParser().parseExpression(Expr))
4302 // The expression has to be a constant. Memory references with relocations
4303 // don't come through here, as they use the <label> forms of the relevant
4305 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
4307 return Error (E, "constant expression expected");
4310 switch (CE->getValue()) {
4313 "alignment specifier must be 16, 32, 64, 128, or 256 bits");
4314 case 16: Align = 2; break;
4315 case 32: Align = 4; break;
4316 case 64: Align = 8; break;
4317 case 128: Align = 16; break;
4318 case 256: Align = 32; break;
4321 // Now we should have the closing ']'
4322 if (Parser.getTok().isNot(AsmToken::RBrac))
4323 return Error(Parser.getTok().getLoc(), "']' expected");
4324 E = Parser.getTok().getEndLoc();
4325 Parser.Lex(); // Eat right bracket token.
4327 // Don't worry about range checking the value here. That's handled by
4328 // the is*() predicates.
4329 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, 0,
4330 ARM_AM::no_shift, 0, Align,
4333 // If there's a pre-indexing writeback marker, '!', just add it as a token
4335 if (Parser.getTok().is(AsmToken::Exclaim)) {
4336 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4337 Parser.Lex(); // Eat the '!'.
4343 // If we have a '#', it's an immediate offset, else assume it's a register
4344 // offset. Be friendly and also accept a plain integer (without a leading
4345 // hash) for gas compatibility.
4346 if (Parser.getTok().is(AsmToken::Hash) ||
4347 Parser.getTok().is(AsmToken::Dollar) ||
4348 Parser.getTok().is(AsmToken::Integer)) {
4349 if (Parser.getTok().isNot(AsmToken::Integer))
4350 Parser.Lex(); // Eat the '#'.
4351 E = Parser.getTok().getLoc();
4353 bool isNegative = getParser().getTok().is(AsmToken::Minus);
4354 const MCExpr *Offset;
4355 if (getParser().parseExpression(Offset))
4358 // The expression has to be a constant. Memory references with relocations
4359 // don't come through here, as they use the <label> forms of the relevant
4361 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
4363 return Error (E, "constant expression expected");
4365 // If the constant was #-0, represent it as INT32_MIN.
4366 int32_t Val = CE->getValue();
4367 if (isNegative && Val == 0)
4368 CE = MCConstantExpr::Create(INT32_MIN, getContext());
4370 // Now we should have the closing ']'
4371 if (Parser.getTok().isNot(AsmToken::RBrac))
4372 return Error(Parser.getTok().getLoc(), "']' expected");
4373 E = Parser.getTok().getEndLoc();
4374 Parser.Lex(); // Eat right bracket token.
4376 // Don't worry about range checking the value here. That's handled by
4377 // the is*() predicates.
4378 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, CE, 0,
4379 ARM_AM::no_shift, 0, 0,
4382 // If there's a pre-indexing writeback marker, '!', just add it as a token
4384 if (Parser.getTok().is(AsmToken::Exclaim)) {
4385 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4386 Parser.Lex(); // Eat the '!'.
4392 // The register offset is optionally preceded by a '+' or '-'
4393 bool isNegative = false;
4394 if (Parser.getTok().is(AsmToken::Minus)) {
4396 Parser.Lex(); // Eat the '-'.
4397 } else if (Parser.getTok().is(AsmToken::Plus)) {
4399 Parser.Lex(); // Eat the '+'.
4402 E = Parser.getTok().getLoc();
4403 int OffsetRegNum = tryParseRegister();
4404 if (OffsetRegNum == -1)
4405 return Error(E, "register expected");
4407 // If there's a shift operator, handle it.
4408 ARM_AM::ShiftOpc ShiftType = ARM_AM::no_shift;
4409 unsigned ShiftImm = 0;
4410 if (Parser.getTok().is(AsmToken::Comma)) {
4411 Parser.Lex(); // Eat the ','.
4412 if (parseMemRegOffsetShift(ShiftType, ShiftImm))
4416 // Now we should have the closing ']'
4417 if (Parser.getTok().isNot(AsmToken::RBrac))
4418 return Error(Parser.getTok().getLoc(), "']' expected");
4419 E = Parser.getTok().getEndLoc();
4420 Parser.Lex(); // Eat right bracket token.
4422 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, OffsetRegNum,
4423 ShiftType, ShiftImm, 0, isNegative,
4426 // If there's a pre-indexing writeback marker, '!', just add it as a token
4428 if (Parser.getTok().is(AsmToken::Exclaim)) {
4429 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4430 Parser.Lex(); // Eat the '!'.
4436 /// parseMemRegOffsetShift - one of these two:
4437 /// ( lsl | lsr | asr | ror ) , # shift_amount
4439 /// return true if it parses a shift otherwise it returns false.
4440 bool ARMAsmParser::parseMemRegOffsetShift(ARM_AM::ShiftOpc &St,
4442 SMLoc Loc = Parser.getTok().getLoc();
4443 const AsmToken &Tok = Parser.getTok();
4444 if (Tok.isNot(AsmToken::Identifier))
4446 StringRef ShiftName = Tok.getString();
4447 if (ShiftName == "lsl" || ShiftName == "LSL" ||
4448 ShiftName == "asl" || ShiftName == "ASL")
4450 else if (ShiftName == "lsr" || ShiftName == "LSR")
4452 else if (ShiftName == "asr" || ShiftName == "ASR")
4454 else if (ShiftName == "ror" || ShiftName == "ROR")
4456 else if (ShiftName == "rrx" || ShiftName == "RRX")
4459 return Error(Loc, "illegal shift operator");
4460 Parser.Lex(); // Eat shift type token.
4462 // rrx stands alone.
4464 if (St != ARM_AM::rrx) {
4465 Loc = Parser.getTok().getLoc();
4466 // A '#' and a shift amount.
4467 const AsmToken &HashTok = Parser.getTok();
4468 if (HashTok.isNot(AsmToken::Hash) &&
4469 HashTok.isNot(AsmToken::Dollar))
4470 return Error(HashTok.getLoc(), "'#' expected");
4471 Parser.Lex(); // Eat hash token.
4474 if (getParser().parseExpression(Expr))
4476 // Range check the immediate.
4477 // lsl, ror: 0 <= imm <= 31
4478 // lsr, asr: 0 <= imm <= 32
4479 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
4481 return Error(Loc, "shift amount must be an immediate");
4482 int64_t Imm = CE->getValue();
4484 ((St == ARM_AM::lsl || St == ARM_AM::ror) && Imm > 31) ||
4485 ((St == ARM_AM::lsr || St == ARM_AM::asr) && Imm > 32))
4486 return Error(Loc, "immediate shift value out of range");
4487 // If <ShiftTy> #0, turn it into a no_shift.
4490 // For consistency, treat lsr #32 and asr #32 as having immediate value 0.
4499 /// parseFPImm - A floating point immediate expression operand.
4500 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
4501 parseFPImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4502 // Anything that can accept a floating point constant as an operand
4503 // needs to go through here, as the regular parseExpression is
4506 // This routine still creates a generic Immediate operand, containing
4507 // a bitcast of the 64-bit floating point value. The various operands
4508 // that accept floats can check whether the value is valid for them
4509 // via the standard is*() predicates.
4511 SMLoc S = Parser.getTok().getLoc();
4513 if (Parser.getTok().isNot(AsmToken::Hash) &&
4514 Parser.getTok().isNot(AsmToken::Dollar))
4515 return MatchOperand_NoMatch;
4517 // Disambiguate the VMOV forms that can accept an FP immediate.
4518 // vmov.f32 <sreg>, #imm
4519 // vmov.f64 <dreg>, #imm
4520 // vmov.f32 <dreg>, #imm @ vector f32x2
4521 // vmov.f32 <qreg>, #imm @ vector f32x4
4523 // There are also the NEON VMOV instructions which expect an
4524 // integer constant. Make sure we don't try to parse an FPImm
4526 // vmov.i{8|16|32|64} <dreg|qreg>, #imm
4527 ARMOperand *TyOp = static_cast<ARMOperand*>(Operands[2]);
4528 if (!TyOp->isToken() || (TyOp->getToken() != ".f32" &&
4529 TyOp->getToken() != ".f64"))
4530 return MatchOperand_NoMatch;
4532 Parser.Lex(); // Eat the '#'.
4534 // Handle negation, as that still comes through as a separate token.
4535 bool isNegative = false;
4536 if (Parser.getTok().is(AsmToken::Minus)) {
4540 const AsmToken &Tok = Parser.getTok();
4541 SMLoc Loc = Tok.getLoc();
4542 if (Tok.is(AsmToken::Real)) {
4543 APFloat RealVal(APFloat::IEEEsingle, Tok.getString());
4544 uint64_t IntVal = RealVal.bitcastToAPInt().getZExtValue();
4545 // If we had a '-' in front, toggle the sign bit.
4546 IntVal ^= (uint64_t)isNegative << 31;
4547 Parser.Lex(); // Eat the token.
4548 Operands.push_back(ARMOperand::CreateImm(
4549 MCConstantExpr::Create(IntVal, getContext()),
4550 S, Parser.getTok().getLoc()));
4551 return MatchOperand_Success;
4553 // Also handle plain integers. Instructions which allow floating point
4554 // immediates also allow a raw encoded 8-bit value.
4555 if (Tok.is(AsmToken::Integer)) {
4556 int64_t Val = Tok.getIntVal();
4557 Parser.Lex(); // Eat the token.
4558 if (Val > 255 || Val < 0) {
4559 Error(Loc, "encoded floating point value out of range");
4560 return MatchOperand_ParseFail;
4562 double RealVal = ARM_AM::getFPImmFloat(Val);
4563 Val = APFloat(APFloat::IEEEdouble, RealVal).bitcastToAPInt().getZExtValue();
4564 Operands.push_back(ARMOperand::CreateImm(
4565 MCConstantExpr::Create(Val, getContext()), S,
4566 Parser.getTok().getLoc()));
4567 return MatchOperand_Success;
4570 Error(Loc, "invalid floating point immediate");
4571 return MatchOperand_ParseFail;
4574 /// Parse a arm instruction operand. For now this parses the operand regardless
4575 /// of the mnemonic.
4576 bool ARMAsmParser::parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
4577 StringRef Mnemonic) {
4580 // Check if the current operand has a custom associated parser, if so, try to
4581 // custom parse the operand, or fallback to the general approach.
4582 OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
4583 if (ResTy == MatchOperand_Success)
4585 // If there wasn't a custom match, try the generic matcher below. Otherwise,
4586 // there was a match, but an error occurred, in which case, just return that
4587 // the operand parsing failed.
4588 if (ResTy == MatchOperand_ParseFail)
4591 switch (getLexer().getKind()) {
4593 Error(Parser.getTok().getLoc(), "unexpected token in operand");
4595 case AsmToken::Identifier: {
4596 // If we've seen a branch mnemonic, the next operand must be a label. This
4597 // is true even if the label is a register name. So "br r1" means branch to
4599 bool ExpectLabel = Mnemonic == "b" || Mnemonic == "bl";
4601 if (!tryParseRegisterWithWriteBack(Operands))
4603 int Res = tryParseShiftRegister(Operands);
4604 if (Res == 0) // success
4606 else if (Res == -1) // irrecoverable error
4608 // If this is VMRS, check for the apsr_nzcv operand.
4609 if (Mnemonic == "vmrs" &&
4610 Parser.getTok().getString().equals_lower("apsr_nzcv")) {
4611 S = Parser.getTok().getLoc();
4613 Operands.push_back(ARMOperand::CreateToken("APSR_nzcv", S));
4618 // Fall though for the Identifier case that is not a register or a
4621 case AsmToken::LParen: // parenthesized expressions like (_strcmp-4)
4622 case AsmToken::Integer: // things like 1f and 2b as a branch targets
4623 case AsmToken::String: // quoted label names.
4624 case AsmToken::Dot: { // . as a branch target
4625 // This was not a register so parse other operands that start with an
4626 // identifier (like labels) as expressions and create them as immediates.
4627 const MCExpr *IdVal;
4628 S = Parser.getTok().getLoc();
4629 if (getParser().parseExpression(IdVal))
4631 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
4632 Operands.push_back(ARMOperand::CreateImm(IdVal, S, E));
4635 case AsmToken::LBrac:
4636 return parseMemory(Operands);
4637 case AsmToken::LCurly:
4638 return parseRegisterList(Operands);
4639 case AsmToken::Dollar:
4640 case AsmToken::Hash: {
4641 // #42 -> immediate.
4642 S = Parser.getTok().getLoc();
4645 if (Parser.getTok().isNot(AsmToken::Colon)) {
4646 bool isNegative = Parser.getTok().is(AsmToken::Minus);
4647 const MCExpr *ImmVal;
4648 if (getParser().parseExpression(ImmVal))
4650 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ImmVal);
4652 int32_t Val = CE->getValue();
4653 if (isNegative && Val == 0)
4654 ImmVal = MCConstantExpr::Create(INT32_MIN, getContext());
4656 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
4657 Operands.push_back(ARMOperand::CreateImm(ImmVal, S, E));
4659 // There can be a trailing '!' on operands that we want as a separate
4660 // '!' Token operand. Handle that here. For example, the compatibilty
4661 // alias for 'srsdb sp!, #imm' is 'srsdb #imm!'.
4662 if (Parser.getTok().is(AsmToken::Exclaim)) {
4663 Operands.push_back(ARMOperand::CreateToken(Parser.getTok().getString(),
4664 Parser.getTok().getLoc()));
4665 Parser.Lex(); // Eat exclaim token
4669 // w/ a ':' after the '#', it's just like a plain ':'.
4672 case AsmToken::Colon: {
4673 // ":lower16:" and ":upper16:" expression prefixes
4674 // FIXME: Check it's an expression prefix,
4675 // e.g. (FOO - :lower16:BAR) isn't legal.
4676 ARMMCExpr::VariantKind RefKind;
4677 if (parsePrefix(RefKind))
4680 const MCExpr *SubExprVal;
4681 if (getParser().parseExpression(SubExprVal))
4684 const MCExpr *ExprVal = ARMMCExpr::Create(RefKind, SubExprVal,
4686 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
4687 Operands.push_back(ARMOperand::CreateImm(ExprVal, S, E));
4693 // parsePrefix - Parse ARM 16-bit relocations expression prefix, i.e.
4694 // :lower16: and :upper16:.
4695 bool ARMAsmParser::parsePrefix(ARMMCExpr::VariantKind &RefKind) {
4696 RefKind = ARMMCExpr::VK_ARM_None;
4698 // :lower16: and :upper16: modifiers
4699 assert(getLexer().is(AsmToken::Colon) && "expected a :");
4700 Parser.Lex(); // Eat ':'
4702 if (getLexer().isNot(AsmToken::Identifier)) {
4703 Error(Parser.getTok().getLoc(), "expected prefix identifier in operand");
4707 StringRef IDVal = Parser.getTok().getIdentifier();
4708 if (IDVal == "lower16") {
4709 RefKind = ARMMCExpr::VK_ARM_LO16;
4710 } else if (IDVal == "upper16") {
4711 RefKind = ARMMCExpr::VK_ARM_HI16;
4713 Error(Parser.getTok().getLoc(), "unexpected prefix in operand");
4718 if (getLexer().isNot(AsmToken::Colon)) {
4719 Error(Parser.getTok().getLoc(), "unexpected token after prefix");
4722 Parser.Lex(); // Eat the last ':'
4726 /// \brief Given a mnemonic, split out possible predication code and carry
4727 /// setting letters to form a canonical mnemonic and flags.
4729 // FIXME: Would be nice to autogen this.
4730 // FIXME: This is a bit of a maze of special cases.
4731 StringRef ARMAsmParser::splitMnemonic(StringRef Mnemonic,
4732 unsigned &PredicationCode,
4734 unsigned &ProcessorIMod,
4735 StringRef &ITMask) {
4736 PredicationCode = ARMCC::AL;
4737 CarrySetting = false;
4740 // Ignore some mnemonics we know aren't predicated forms.
4742 // FIXME: Would be nice to autogen this.
4743 if ((Mnemonic == "movs" && isThumb()) ||
4744 Mnemonic == "teq" || Mnemonic == "vceq" || Mnemonic == "svc" ||
4745 Mnemonic == "mls" || Mnemonic == "smmls" || Mnemonic == "vcls" ||
4746 Mnemonic == "vmls" || Mnemonic == "vnmls" || Mnemonic == "vacge" ||
4747 Mnemonic == "vcge" || Mnemonic == "vclt" || Mnemonic == "vacgt" ||
4748 Mnemonic == "vaclt" || Mnemonic == "vacle" ||
4749 Mnemonic == "vcgt" || Mnemonic == "vcle" || Mnemonic == "smlal" ||
4750 Mnemonic == "umaal" || Mnemonic == "umlal" || Mnemonic == "vabal" ||
4751 Mnemonic == "vmlal" || Mnemonic == "vpadal" || Mnemonic == "vqdmlal" ||
4752 Mnemonic == "fmuls")
4755 // First, split out any predication code. Ignore mnemonics we know aren't
4756 // predicated but do have a carry-set and so weren't caught above.
4757 if (Mnemonic != "adcs" && Mnemonic != "bics" && Mnemonic != "movs" &&
4758 Mnemonic != "muls" && Mnemonic != "smlals" && Mnemonic != "smulls" &&
4759 Mnemonic != "umlals" && Mnemonic != "umulls" && Mnemonic != "lsls" &&
4760 Mnemonic != "sbcs" && Mnemonic != "rscs") {
4761 unsigned CC = StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2))
4762 .Case("eq", ARMCC::EQ)
4763 .Case("ne", ARMCC::NE)
4764 .Case("hs", ARMCC::HS)
4765 .Case("cs", ARMCC::HS)
4766 .Case("lo", ARMCC::LO)
4767 .Case("cc", ARMCC::LO)
4768 .Case("mi", ARMCC::MI)
4769 .Case("pl", ARMCC::PL)
4770 .Case("vs", ARMCC::VS)
4771 .Case("vc", ARMCC::VC)
4772 .Case("hi", ARMCC::HI)
4773 .Case("ls", ARMCC::LS)
4774 .Case("ge", ARMCC::GE)
4775 .Case("lt", ARMCC::LT)
4776 .Case("gt", ARMCC::GT)
4777 .Case("le", ARMCC::LE)
4778 .Case("al", ARMCC::AL)
4781 Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 2);
4782 PredicationCode = CC;
4786 // Next, determine if we have a carry setting bit. We explicitly ignore all
4787 // the instructions we know end in 's'.
4788 if (Mnemonic.endswith("s") &&
4789 !(Mnemonic == "cps" || Mnemonic == "mls" ||
4790 Mnemonic == "mrs" || Mnemonic == "smmls" || Mnemonic == "vabs" ||
4791 Mnemonic == "vcls" || Mnemonic == "vmls" || Mnemonic == "vmrs" ||
4792 Mnemonic == "vnmls" || Mnemonic == "vqabs" || Mnemonic == "vrecps" ||
4793 Mnemonic == "vrsqrts" || Mnemonic == "srs" || Mnemonic == "flds" ||
4794 Mnemonic == "fmrs" || Mnemonic == "fsqrts" || Mnemonic == "fsubs" ||
4795 Mnemonic == "fsts" || Mnemonic == "fcpys" || Mnemonic == "fdivs" ||
4796 Mnemonic == "fmuls" || Mnemonic == "fcmps" || Mnemonic == "fcmpzs" ||
4797 Mnemonic == "vfms" || Mnemonic == "vfnms" ||
4798 (Mnemonic == "movs" && isThumb()))) {
4799 Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 1);
4800 CarrySetting = true;
4803 // The "cps" instruction can have a interrupt mode operand which is glued into
4804 // the mnemonic. Check if this is the case, split it and parse the imod op
4805 if (Mnemonic.startswith("cps")) {
4806 // Split out any imod code.
4808 StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2, 2))
4809 .Case("ie", ARM_PROC::IE)
4810 .Case("id", ARM_PROC::ID)
4813 Mnemonic = Mnemonic.slice(0, Mnemonic.size()-2);
4814 ProcessorIMod = IMod;
4818 // The "it" instruction has the condition mask on the end of the mnemonic.
4819 if (Mnemonic.startswith("it")) {
4820 ITMask = Mnemonic.slice(2, Mnemonic.size());
4821 Mnemonic = Mnemonic.slice(0, 2);
4827 /// \brief Given a canonical mnemonic, determine if the instruction ever allows
4828 /// inclusion of carry set or predication code operands.
4830 // FIXME: It would be nice to autogen this.
4832 getMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet,
4833 bool &CanAcceptPredicationCode) {
4834 if (Mnemonic == "and" || Mnemonic == "lsl" || Mnemonic == "lsr" ||
4835 Mnemonic == "rrx" || Mnemonic == "ror" || Mnemonic == "sub" ||
4836 Mnemonic == "add" || Mnemonic == "adc" ||
4837 Mnemonic == "mul" || Mnemonic == "bic" || Mnemonic == "asr" ||
4838 Mnemonic == "orr" || Mnemonic == "mvn" ||
4839 Mnemonic == "rsb" || Mnemonic == "rsc" || Mnemonic == "orn" ||
4840 Mnemonic == "sbc" || Mnemonic == "eor" || Mnemonic == "neg" ||
4841 Mnemonic == "vfm" || Mnemonic == "vfnm" ||
4842 (!isThumb() && (Mnemonic == "smull" || Mnemonic == "mov" ||
4843 Mnemonic == "mla" || Mnemonic == "smlal" ||
4844 Mnemonic == "umlal" || Mnemonic == "umull"))) {
4845 CanAcceptCarrySet = true;
4847 CanAcceptCarrySet = false;
4849 if (Mnemonic == "cbnz" || Mnemonic == "setend" || Mnemonic == "dmb" ||
4850 Mnemonic == "cps" || Mnemonic == "mcr2" || Mnemonic == "it" ||
4851 Mnemonic == "mcrr2" || Mnemonic == "cbz" || Mnemonic == "cdp2" ||
4852 Mnemonic == "trap" || Mnemonic == "mrc2" || Mnemonic == "mrrc2" ||
4853 Mnemonic == "dsb" || Mnemonic == "isb" || Mnemonic == "setend" ||
4854 (Mnemonic == "clrex" && !isThumb()) ||
4855 (Mnemonic == "nop" && isThumbOne()) ||
4856 ((Mnemonic == "pld" || Mnemonic == "pli" || Mnemonic == "pldw" ||
4857 Mnemonic == "ldc2" || Mnemonic == "ldc2l" ||
4858 Mnemonic == "stc2" || Mnemonic == "stc2l") && !isThumb()) ||
4859 ((Mnemonic.startswith("rfe") || Mnemonic.startswith("srs")) &&
4861 Mnemonic.startswith("cps") || (Mnemonic == "movs" && isThumbOne())) {
4862 CanAcceptPredicationCode = false;
4864 CanAcceptPredicationCode = true;
4867 if (Mnemonic == "bkpt" || Mnemonic == "mcr" || Mnemonic == "mcrr" ||
4868 Mnemonic == "mrc" || Mnemonic == "mrrc" || Mnemonic == "cdp")
4869 CanAcceptPredicationCode = false;
4873 bool ARMAsmParser::shouldOmitCCOutOperand(StringRef Mnemonic,
4874 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4875 // FIXME: This is all horribly hacky. We really need a better way to deal
4876 // with optional operands like this in the matcher table.
4878 // The 'mov' mnemonic is special. One variant has a cc_out operand, while
4879 // another does not. Specifically, the MOVW instruction does not. So we
4880 // special case it here and remove the defaulted (non-setting) cc_out
4881 // operand if that's the instruction we're trying to match.
4883 // We do this as post-processing of the explicit operands rather than just
4884 // conditionally adding the cc_out in the first place because we need
4885 // to check the type of the parsed immediate operand.
4886 if (Mnemonic == "mov" && Operands.size() > 4 && !isThumb() &&
4887 !static_cast<ARMOperand*>(Operands[4])->isARMSOImm() &&
4888 static_cast<ARMOperand*>(Operands[4])->isImm0_65535Expr() &&
4889 static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
4892 // Register-register 'add' for thumb does not have a cc_out operand
4893 // when there are only two register operands.
4894 if (isThumb() && Mnemonic == "add" && Operands.size() == 5 &&
4895 static_cast<ARMOperand*>(Operands[3])->isReg() &&
4896 static_cast<ARMOperand*>(Operands[4])->isReg() &&
4897 static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
4899 // Register-register 'add' for thumb does not have a cc_out operand
4900 // when it's an ADD Rdm, SP, {Rdm|#imm0_255} instruction. We do
4901 // have to check the immediate range here since Thumb2 has a variant
4902 // that can handle a different range and has a cc_out operand.
4903 if (((isThumb() && Mnemonic == "add") ||
4904 (isThumbTwo() && Mnemonic == "sub")) &&
4905 Operands.size() == 6 &&
4906 static_cast<ARMOperand*>(Operands[3])->isReg() &&
4907 static_cast<ARMOperand*>(Operands[4])->isReg() &&
4908 static_cast<ARMOperand*>(Operands[4])->getReg() == ARM::SP &&
4909 static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
4910 ((Mnemonic == "add" &&static_cast<ARMOperand*>(Operands[5])->isReg()) ||
4911 static_cast<ARMOperand*>(Operands[5])->isImm0_1020s4()))
4913 // For Thumb2, add/sub immediate does not have a cc_out operand for the
4914 // imm0_4095 variant. That's the least-preferred variant when
4915 // selecting via the generic "add" mnemonic, so to know that we
4916 // should remove the cc_out operand, we have to explicitly check that
4917 // it's not one of the other variants. Ugh.
4918 if (isThumbTwo() && (Mnemonic == "add" || Mnemonic == "sub") &&
4919 Operands.size() == 6 &&
4920 static_cast<ARMOperand*>(Operands[3])->isReg() &&
4921 static_cast<ARMOperand*>(Operands[4])->isReg() &&
4922 static_cast<ARMOperand*>(Operands[5])->isImm()) {
4923 // Nest conditions rather than one big 'if' statement for readability.
4925 // If either register is a high reg, it's either one of the SP
4926 // variants (handled above) or a 32-bit encoding, so we just
4927 // check against T3. If the second register is the PC, this is an
4928 // alternate form of ADR, which uses encoding T4, so check for that too.
4929 if ((!isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) ||
4930 !isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg())) &&
4931 static_cast<ARMOperand*>(Operands[4])->getReg() != ARM::PC &&
4932 static_cast<ARMOperand*>(Operands[5])->isT2SOImm())
4934 // If both registers are low, we're in an IT block, and the immediate is
4935 // in range, we should use encoding T1 instead, which has a cc_out.
4937 isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) &&
4938 isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) &&
4939 static_cast<ARMOperand*>(Operands[5])->isImm0_7())
4942 // Otherwise, we use encoding T4, which does not have a cc_out
4947 // The thumb2 multiply instruction doesn't have a CCOut register, so
4948 // if we have a "mul" mnemonic in Thumb mode, check if we'll be able to
4949 // use the 16-bit encoding or not.
4950 if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 6 &&
4951 static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
4952 static_cast<ARMOperand*>(Operands[3])->isReg() &&
4953 static_cast<ARMOperand*>(Operands[4])->isReg() &&
4954 static_cast<ARMOperand*>(Operands[5])->isReg() &&
4955 // If the registers aren't low regs, the destination reg isn't the
4956 // same as one of the source regs, or the cc_out operand is zero
4957 // outside of an IT block, we have to use the 32-bit encoding, so
4958 // remove the cc_out operand.
4959 (!isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) ||
4960 !isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) ||
4961 !isARMLowRegister(static_cast<ARMOperand*>(Operands[5])->getReg()) ||
4963 (static_cast<ARMOperand*>(Operands[3])->getReg() !=
4964 static_cast<ARMOperand*>(Operands[5])->getReg() &&
4965 static_cast<ARMOperand*>(Operands[3])->getReg() !=
4966 static_cast<ARMOperand*>(Operands[4])->getReg())))
4969 // Also check the 'mul' syntax variant that doesn't specify an explicit
4970 // destination register.
4971 if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 5 &&
4972 static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
4973 static_cast<ARMOperand*>(Operands[3])->isReg() &&
4974 static_cast<ARMOperand*>(Operands[4])->isReg() &&
4975 // If the registers aren't low regs or the cc_out operand is zero
4976 // outside of an IT block, we have to use the 32-bit encoding, so
4977 // remove the cc_out operand.
4978 (!isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) ||
4979 !isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) ||
4985 // Register-register 'add/sub' for thumb does not have a cc_out operand
4986 // when it's an ADD/SUB SP, #imm. Be lenient on count since there's also
4987 // the "add/sub SP, SP, #imm" version. If the follow-up operands aren't
4988 // right, this will result in better diagnostics (which operand is off)
4990 if (isThumb() && (Mnemonic == "add" || Mnemonic == "sub") &&
4991 (Operands.size() == 5 || Operands.size() == 6) &&
4992 static_cast<ARMOperand*>(Operands[3])->isReg() &&
4993 static_cast<ARMOperand*>(Operands[3])->getReg() == ARM::SP &&
4994 static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
4995 (static_cast<ARMOperand*>(Operands[4])->isImm() ||
4996 (Operands.size() == 6 &&
4997 static_cast<ARMOperand*>(Operands[5])->isImm())))
5003 static bool isDataTypeToken(StringRef Tok) {
5004 return Tok == ".8" || Tok == ".16" || Tok == ".32" || Tok == ".64" ||
5005 Tok == ".i8" || Tok == ".i16" || Tok == ".i32" || Tok == ".i64" ||
5006 Tok == ".u8" || Tok == ".u16" || Tok == ".u32" || Tok == ".u64" ||
5007 Tok == ".s8" || Tok == ".s16" || Tok == ".s32" || Tok == ".s64" ||
5008 Tok == ".p8" || Tok == ".p16" || Tok == ".f32" || Tok == ".f64" ||
5009 Tok == ".f" || Tok == ".d";
5012 // FIXME: This bit should probably be handled via an explicit match class
5013 // in the .td files that matches the suffix instead of having it be
5014 // a literal string token the way it is now.
5015 static bool doesIgnoreDataTypeSuffix(StringRef Mnemonic, StringRef DT) {
5016 return Mnemonic.startswith("vldm") || Mnemonic.startswith("vstm");
5019 static void applyMnemonicAliases(StringRef &Mnemonic, unsigned Features);
5020 /// Parse an arm instruction mnemonic followed by its operands.
5021 bool ARMAsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
5023 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
5024 // Apply mnemonic aliases before doing anything else, as the destination
5025 // mnemnonic may include suffices and we want to handle them normally.
5026 // The generic tblgen'erated code does this later, at the start of
5027 // MatchInstructionImpl(), but that's too late for aliases that include
5028 // any sort of suffix.
5029 unsigned AvailableFeatures = getAvailableFeatures();
5030 applyMnemonicAliases(Name, AvailableFeatures);
5032 // First check for the ARM-specific .req directive.
5033 if (Parser.getTok().is(AsmToken::Identifier) &&
5034 Parser.getTok().getIdentifier() == ".req") {
5035 parseDirectiveReq(Name, NameLoc);
5036 // We always return 'error' for this, as we're done with this
5037 // statement and don't need to match the 'instruction."
5041 // Create the leading tokens for the mnemonic, split by '.' characters.
5042 size_t Start = 0, Next = Name.find('.');
5043 StringRef Mnemonic = Name.slice(Start, Next);
5045 // Split out the predication code and carry setting flag from the mnemonic.
5046 unsigned PredicationCode;
5047 unsigned ProcessorIMod;
5050 Mnemonic = splitMnemonic(Mnemonic, PredicationCode, CarrySetting,
5051 ProcessorIMod, ITMask);
5053 // In Thumb1, only the branch (B) instruction can be predicated.
5054 if (isThumbOne() && PredicationCode != ARMCC::AL && Mnemonic != "b") {
5055 Parser.eatToEndOfStatement();
5056 return Error(NameLoc, "conditional execution not supported in Thumb1");
5059 Operands.push_back(ARMOperand::CreateToken(Mnemonic, NameLoc));
5061 // Handle the IT instruction ITMask. Convert it to a bitmask. This
5062 // is the mask as it will be for the IT encoding if the conditional
5063 // encoding has a '1' as it's bit0 (i.e. 't' ==> '1'). In the case
5064 // where the conditional bit0 is zero, the instruction post-processing
5065 // will adjust the mask accordingly.
5066 if (Mnemonic == "it") {
5067 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + 2);
5068 if (ITMask.size() > 3) {
5069 Parser.eatToEndOfStatement();
5070 return Error(Loc, "too many conditions on IT instruction");
5073 for (unsigned i = ITMask.size(); i != 0; --i) {
5074 char pos = ITMask[i - 1];
5075 if (pos != 't' && pos != 'e') {
5076 Parser.eatToEndOfStatement();
5077 return Error(Loc, "illegal IT block condition mask '" + ITMask + "'");
5080 if (ITMask[i - 1] == 't')
5083 Operands.push_back(ARMOperand::CreateITMask(Mask, Loc));
5086 // FIXME: This is all a pretty gross hack. We should automatically handle
5087 // optional operands like this via tblgen.
5089 // Next, add the CCOut and ConditionCode operands, if needed.
5091 // For mnemonics which can ever incorporate a carry setting bit or predication
5092 // code, our matching model involves us always generating CCOut and
5093 // ConditionCode operands to match the mnemonic "as written" and then we let
5094 // the matcher deal with finding the right instruction or generating an
5095 // appropriate error.
5096 bool CanAcceptCarrySet, CanAcceptPredicationCode;
5097 getMnemonicAcceptInfo(Mnemonic, CanAcceptCarrySet, CanAcceptPredicationCode);
5099 // If we had a carry-set on an instruction that can't do that, issue an
5101 if (!CanAcceptCarrySet && CarrySetting) {
5102 Parser.eatToEndOfStatement();
5103 return Error(NameLoc, "instruction '" + Mnemonic +
5104 "' can not set flags, but 's' suffix specified");
5106 // If we had a predication code on an instruction that can't do that, issue an
5108 if (!CanAcceptPredicationCode && PredicationCode != ARMCC::AL) {
5109 Parser.eatToEndOfStatement();
5110 return Error(NameLoc, "instruction '" + Mnemonic +
5111 "' is not predicable, but condition code specified");
5114 // Add the carry setting operand, if necessary.
5115 if (CanAcceptCarrySet) {
5116 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size());
5117 Operands.push_back(ARMOperand::CreateCCOut(CarrySetting ? ARM::CPSR : 0,
5121 // Add the predication code operand, if necessary.
5122 if (CanAcceptPredicationCode) {
5123 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size() +
5125 Operands.push_back(ARMOperand::CreateCondCode(
5126 ARMCC::CondCodes(PredicationCode), Loc));
5129 // Add the processor imod operand, if necessary.
5130 if (ProcessorIMod) {
5131 Operands.push_back(ARMOperand::CreateImm(
5132 MCConstantExpr::Create(ProcessorIMod, getContext()),
5136 // Add the remaining tokens in the mnemonic.
5137 while (Next != StringRef::npos) {
5139 Next = Name.find('.', Start + 1);
5140 StringRef ExtraToken = Name.slice(Start, Next);
5142 // Some NEON instructions have an optional datatype suffix that is
5143 // completely ignored. Check for that.
5144 if (isDataTypeToken(ExtraToken) &&
5145 doesIgnoreDataTypeSuffix(Mnemonic, ExtraToken))
5148 if (ExtraToken != ".n") {
5149 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Start);
5150 Operands.push_back(ARMOperand::CreateToken(ExtraToken, Loc));
5154 // Read the remaining operands.
5155 if (getLexer().isNot(AsmToken::EndOfStatement)) {
5156 // Read the first operand.
5157 if (parseOperand(Operands, Mnemonic)) {
5158 Parser.eatToEndOfStatement();
5162 while (getLexer().is(AsmToken::Comma)) {
5163 Parser.Lex(); // Eat the comma.
5165 // Parse and remember the operand.
5166 if (parseOperand(Operands, Mnemonic)) {
5167 Parser.eatToEndOfStatement();
5173 if (getLexer().isNot(AsmToken::EndOfStatement)) {
5174 SMLoc Loc = getLexer().getLoc();
5175 Parser.eatToEndOfStatement();
5176 return Error(Loc, "unexpected token in argument list");
5179 Parser.Lex(); // Consume the EndOfStatement
5181 // Some instructions, mostly Thumb, have forms for the same mnemonic that
5182 // do and don't have a cc_out optional-def operand. With some spot-checks
5183 // of the operand list, we can figure out which variant we're trying to
5184 // parse and adjust accordingly before actually matching. We shouldn't ever
5185 // try to remove a cc_out operand that was explicitly set on the the
5186 // mnemonic, of course (CarrySetting == true). Reason number #317 the
5187 // table driven matcher doesn't fit well with the ARM instruction set.
5188 if (!CarrySetting && shouldOmitCCOutOperand(Mnemonic, Operands)) {
5189 ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]);
5190 Operands.erase(Operands.begin() + 1);
5194 // ARM mode 'blx' need special handling, as the register operand version
5195 // is predicable, but the label operand version is not. So, we can't rely
5196 // on the Mnemonic based checking to correctly figure out when to put
5197 // a k_CondCode operand in the list. If we're trying to match the label
5198 // version, remove the k_CondCode operand here.
5199 if (!isThumb() && Mnemonic == "blx" && Operands.size() == 3 &&
5200 static_cast<ARMOperand*>(Operands[2])->isImm()) {
5201 ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]);
5202 Operands.erase(Operands.begin() + 1);
5206 // Adjust operands of ldrexd/strexd to MCK_GPRPair.
5207 // ldrexd/strexd require even/odd GPR pair. To enforce this constraint,
5208 // a single GPRPair reg operand is used in the .td file to replace the two
5209 // GPRs. However, when parsing from asm, the two GRPs cannot be automatically
5210 // expressed as a GPRPair, so we have to manually merge them.
5211 // FIXME: We would really like to be able to tablegen'erate this.
5212 if (!isThumb() && Operands.size() > 4 &&
5213 (Mnemonic == "ldrexd" || Mnemonic == "strexd")) {
5214 bool isLoad = (Mnemonic == "ldrexd");
5215 unsigned Idx = isLoad ? 2 : 3;
5216 ARMOperand* Op1 = static_cast<ARMOperand*>(Operands[Idx]);
5217 ARMOperand* Op2 = static_cast<ARMOperand*>(Operands[Idx+1]);
5219 const MCRegisterClass& MRC = MRI->getRegClass(ARM::GPRRegClassID);
5220 // Adjust only if Op1 and Op2 are GPRs.
5221 if (Op1->isReg() && Op2->isReg() && MRC.contains(Op1->getReg()) &&
5222 MRC.contains(Op2->getReg())) {
5223 unsigned Reg1 = Op1->getReg();
5224 unsigned Reg2 = Op2->getReg();
5225 unsigned Rt = MRI->getEncodingValue(Reg1);
5226 unsigned Rt2 = MRI->getEncodingValue(Reg2);
5228 // Rt2 must be Rt + 1 and Rt must be even.
5229 if (Rt + 1 != Rt2 || (Rt & 1)) {
5230 Error(Op2->getStartLoc(), isLoad ?
5231 "destination operands must be sequential" :
5232 "source operands must be sequential");
5235 unsigned NewReg = MRI->getMatchingSuperReg(Reg1, ARM::gsub_0,
5236 &(MRI->getRegClass(ARM::GPRPairRegClassID)));
5237 Operands.erase(Operands.begin() + Idx, Operands.begin() + Idx + 2);
5238 Operands.insert(Operands.begin() + Idx, ARMOperand::CreateReg(
5239 NewReg, Op1->getStartLoc(), Op2->getEndLoc()));
5248 // Validate context-sensitive operand constraints.
5250 // return 'true' if register list contains non-low GPR registers,
5251 // 'false' otherwise. If Reg is in the register list or is HiReg, set
5252 // 'containsReg' to true.
5253 static bool checkLowRegisterList(MCInst Inst, unsigned OpNo, unsigned Reg,
5254 unsigned HiReg, bool &containsReg) {
5255 containsReg = false;
5256 for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) {
5257 unsigned OpReg = Inst.getOperand(i).getReg();
5260 // Anything other than a low register isn't legal here.
5261 if (!isARMLowRegister(OpReg) && (!HiReg || OpReg != HiReg))
5267 // Check if the specified regisgter is in the register list of the inst,
5268 // starting at the indicated operand number.
5269 static bool listContainsReg(MCInst &Inst, unsigned OpNo, unsigned Reg) {
5270 for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) {
5271 unsigned OpReg = Inst.getOperand(i).getReg();
5278 // FIXME: We would really prefer to have MCInstrInfo (the wrapper around
5279 // the ARMInsts array) instead. Getting that here requires awkward
5280 // API changes, though. Better way?
5282 extern const MCInstrDesc ARMInsts[];
5284 static const MCInstrDesc &getInstDesc(unsigned Opcode) {
5285 return ARMInsts[Opcode];
5288 // FIXME: We would really like to be able to tablegen'erate this.
5290 validateInstruction(MCInst &Inst,
5291 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
5292 const MCInstrDesc &MCID = getInstDesc(Inst.getOpcode());
5293 SMLoc Loc = Operands[0]->getStartLoc();
5294 // Check the IT block state first.
5295 // NOTE: BKPT instruction has the interesting property of being
5296 // allowed in IT blocks, but not being predicable. It just always
5298 if (inITBlock() && Inst.getOpcode() != ARM::tBKPT &&
5299 Inst.getOpcode() != ARM::BKPT) {
5301 if (ITState.FirstCond)
5302 ITState.FirstCond = false;
5304 bit = (ITState.Mask >> (5 - ITState.CurPosition)) & 1;
5305 // The instruction must be predicable.
5306 if (!MCID.isPredicable())
5307 return Error(Loc, "instructions in IT block must be predicable");
5308 unsigned Cond = Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm();
5309 unsigned ITCond = bit ? ITState.Cond :
5310 ARMCC::getOppositeCondition(ITState.Cond);
5311 if (Cond != ITCond) {
5312 // Find the condition code Operand to get its SMLoc information.
5314 for (unsigned i = 1; i < Operands.size(); ++i)
5315 if (static_cast<ARMOperand*>(Operands[i])->isCondCode())
5316 CondLoc = Operands[i]->getStartLoc();
5317 return Error(CondLoc, "incorrect condition in IT block; got '" +
5318 StringRef(ARMCondCodeToString(ARMCC::CondCodes(Cond))) +
5319 "', but expected '" +
5320 ARMCondCodeToString(ARMCC::CondCodes(ITCond)) + "'");
5322 // Check for non-'al' condition codes outside of the IT block.
5323 } else if (isThumbTwo() && MCID.isPredicable() &&
5324 Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm() !=
5325 ARMCC::AL && Inst.getOpcode() != ARM::tB &&
5326 Inst.getOpcode() != ARM::t2B)
5327 return Error(Loc, "predicated instructions must be in IT block");
5329 switch (Inst.getOpcode()) {
5332 case ARM::LDRD_POST: {
5333 // Rt2 must be Rt + 1.
5334 unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg());
5335 unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg());
5337 return Error(Operands[3]->getStartLoc(),
5338 "destination operands must be sequential");
5342 // Rt2 must be Rt + 1.
5343 unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg());
5344 unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg());
5346 return Error(Operands[3]->getStartLoc(),
5347 "source operands must be sequential");
5351 case ARM::STRD_POST: {
5352 // Rt2 must be Rt + 1.
5353 unsigned Rt = MRI->getEncodingValue(Inst.getOperand(1).getReg());
5354 unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(2).getReg());
5356 return Error(Operands[3]->getStartLoc(),
5357 "source operands must be sequential");
5362 // width must be in range [1, 32-lsb]
5363 unsigned lsb = Inst.getOperand(2).getImm();
5364 unsigned widthm1 = Inst.getOperand(3).getImm();
5365 if (widthm1 >= 32 - lsb)
5366 return Error(Operands[5]->getStartLoc(),
5367 "bitfield width must be in range [1,32-lsb]");
5371 // If we're parsing Thumb2, the .w variant is available and handles
5372 // most cases that are normally illegal for a Thumb1 LDM
5373 // instruction. We'll make the transformation in processInstruction()
5376 // Thumb LDM instructions are writeback iff the base register is not
5377 // in the register list.
5378 unsigned Rn = Inst.getOperand(0).getReg();
5379 bool hasWritebackToken =
5380 (static_cast<ARMOperand*>(Operands[3])->isToken() &&
5381 static_cast<ARMOperand*>(Operands[3])->getToken() == "!");
5382 bool listContainsBase;
5383 if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase) && !isThumbTwo())
5384 return Error(Operands[3 + hasWritebackToken]->getStartLoc(),
5385 "registers must be in range r0-r7");
5386 // If we should have writeback, then there should be a '!' token.
5387 if (!listContainsBase && !hasWritebackToken && !isThumbTwo())
5388 return Error(Operands[2]->getStartLoc(),
5389 "writeback operator '!' expected");
5390 // If we should not have writeback, there must not be a '!'. This is
5391 // true even for the 32-bit wide encodings.
5392 if (listContainsBase && hasWritebackToken)
5393 return Error(Operands[3]->getStartLoc(),
5394 "writeback operator '!' not allowed when base register "
5395 "in register list");
5399 case ARM::t2LDMIA_UPD: {
5400 if (listContainsReg(Inst, 3, Inst.getOperand(0).getReg()))
5401 return Error(Operands[4]->getStartLoc(),
5402 "writeback operator '!' not allowed when base register "
5403 "in register list");
5407 // The second source operand must be the same register as the destination
5410 // In this case, we must directly check the parsed operands because the
5411 // cvtThumbMultiply() function is written in such a way that it guarantees
5412 // this first statement is always true for the new Inst. Essentially, the
5413 // destination is unconditionally copied into the second source operand
5414 // without checking to see if it matches what we actually parsed.
5415 if (Operands.size() == 6 &&
5416 (((ARMOperand*)Operands[3])->getReg() !=
5417 ((ARMOperand*)Operands[5])->getReg()) &&
5418 (((ARMOperand*)Operands[3])->getReg() !=
5419 ((ARMOperand*)Operands[4])->getReg())) {
5420 return Error(Operands[3]->getStartLoc(),
5421 "destination register must match source register");
5425 // Like for ldm/stm, push and pop have hi-reg handling version in Thumb2,
5426 // so only issue a diagnostic for thumb1. The instructions will be
5427 // switched to the t2 encodings in processInstruction() if necessary.
5429 bool listContainsBase;
5430 if (checkLowRegisterList(Inst, 2, 0, ARM::PC, listContainsBase) &&
5432 return Error(Operands[2]->getStartLoc(),
5433 "registers must be in range r0-r7 or pc");
5437 bool listContainsBase;
5438 if (checkLowRegisterList(Inst, 2, 0, ARM::LR, listContainsBase) &&
5440 return Error(Operands[2]->getStartLoc(),
5441 "registers must be in range r0-r7 or lr");
5444 case ARM::tSTMIA_UPD: {
5445 bool listContainsBase;
5446 if (checkLowRegisterList(Inst, 4, 0, 0, listContainsBase) && !isThumbTwo())
5447 return Error(Operands[4]->getStartLoc(),
5448 "registers must be in range r0-r7");
5451 case ARM::tADDrSP: {
5452 // If the non-SP source operand and the destination operand are not the
5453 // same, we need thumb2 (for the wide encoding), or we have an error.
5454 if (!isThumbTwo() &&
5455 Inst.getOperand(0).getReg() != Inst.getOperand(2).getReg()) {
5456 return Error(Operands[4]->getStartLoc(),
5457 "source register must be the same as destination");
5466 static unsigned getRealVSTOpcode(unsigned Opc, unsigned &Spacing) {
5468 default: llvm_unreachable("unexpected opcode!");
5470 case ARM::VST1LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST1LNd8_UPD;
5471 case ARM::VST1LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST1LNd16_UPD;
5472 case ARM::VST1LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST1LNd32_UPD;
5473 case ARM::VST1LNdWB_register_Asm_8: Spacing = 1; return ARM::VST1LNd8_UPD;
5474 case ARM::VST1LNdWB_register_Asm_16: Spacing = 1; return ARM::VST1LNd16_UPD;
5475 case ARM::VST1LNdWB_register_Asm_32: Spacing = 1; return ARM::VST1LNd32_UPD;
5476 case ARM::VST1LNdAsm_8: Spacing = 1; return ARM::VST1LNd8;
5477 case ARM::VST1LNdAsm_16: Spacing = 1; return ARM::VST1LNd16;
5478 case ARM::VST1LNdAsm_32: Spacing = 1; return ARM::VST1LNd32;
5481 case ARM::VST2LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST2LNd8_UPD;
5482 case ARM::VST2LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST2LNd16_UPD;
5483 case ARM::VST2LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST2LNd32_UPD;
5484 case ARM::VST2LNqWB_fixed_Asm_16: Spacing = 2; return ARM::VST2LNq16_UPD;
5485 case ARM::VST2LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST2LNq32_UPD;
5487 case ARM::VST2LNdWB_register_Asm_8: Spacing = 1; return ARM::VST2LNd8_UPD;
5488 case ARM::VST2LNdWB_register_Asm_16: Spacing = 1; return ARM::VST2LNd16_UPD;
5489 case ARM::VST2LNdWB_register_Asm_32: Spacing = 1; return ARM::VST2LNd32_UPD;
5490 case ARM::VST2LNqWB_register_Asm_16: Spacing = 2; return ARM::VST2LNq16_UPD;
5491 case ARM::VST2LNqWB_register_Asm_32: Spacing = 2; return ARM::VST2LNq32_UPD;
5493 case ARM::VST2LNdAsm_8: Spacing = 1; return ARM::VST2LNd8;
5494 case ARM::VST2LNdAsm_16: Spacing = 1; return ARM::VST2LNd16;
5495 case ARM::VST2LNdAsm_32: Spacing = 1; return ARM::VST2LNd32;
5496 case ARM::VST2LNqAsm_16: Spacing = 2; return ARM::VST2LNq16;
5497 case ARM::VST2LNqAsm_32: Spacing = 2; return ARM::VST2LNq32;
5500 case ARM::VST3LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST3LNd8_UPD;
5501 case ARM::VST3LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST3LNd16_UPD;
5502 case ARM::VST3LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST3LNd32_UPD;
5503 case ARM::VST3LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VST3LNq16_UPD;
5504 case ARM::VST3LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST3LNq32_UPD;
5505 case ARM::VST3LNdWB_register_Asm_8: Spacing = 1; return ARM::VST3LNd8_UPD;
5506 case ARM::VST3LNdWB_register_Asm_16: Spacing = 1; return ARM::VST3LNd16_UPD;
5507 case ARM::VST3LNdWB_register_Asm_32: Spacing = 1; return ARM::VST3LNd32_UPD;
5508 case ARM::VST3LNqWB_register_Asm_16: Spacing = 2; return ARM::VST3LNq16_UPD;
5509 case ARM::VST3LNqWB_register_Asm_32: Spacing = 2; return ARM::VST3LNq32_UPD;
5510 case ARM::VST3LNdAsm_8: Spacing = 1; return ARM::VST3LNd8;
5511 case ARM::VST3LNdAsm_16: Spacing = 1; return ARM::VST3LNd16;
5512 case ARM::VST3LNdAsm_32: Spacing = 1; return ARM::VST3LNd32;
5513 case ARM::VST3LNqAsm_16: Spacing = 2; return ARM::VST3LNq16;
5514 case ARM::VST3LNqAsm_32: Spacing = 2; return ARM::VST3LNq32;
5517 case ARM::VST3dWB_fixed_Asm_8: Spacing = 1; return ARM::VST3d8_UPD;
5518 case ARM::VST3dWB_fixed_Asm_16: Spacing = 1; return ARM::VST3d16_UPD;
5519 case ARM::VST3dWB_fixed_Asm_32: Spacing = 1; return ARM::VST3d32_UPD;
5520 case ARM::VST3qWB_fixed_Asm_8: Spacing = 2; return ARM::VST3q8_UPD;
5521 case ARM::VST3qWB_fixed_Asm_16: Spacing = 2; return ARM::VST3q16_UPD;
5522 case ARM::VST3qWB_fixed_Asm_32: Spacing = 2; return ARM::VST3q32_UPD;
5523 case ARM::VST3dWB_register_Asm_8: Spacing = 1; return ARM::VST3d8_UPD;
5524 case ARM::VST3dWB_register_Asm_16: Spacing = 1; return ARM::VST3d16_UPD;
5525 case ARM::VST3dWB_register_Asm_32: Spacing = 1; return ARM::VST3d32_UPD;
5526 case ARM::VST3qWB_register_Asm_8: Spacing = 2; return ARM::VST3q8_UPD;
5527 case ARM::VST3qWB_register_Asm_16: Spacing = 2; return ARM::VST3q16_UPD;
5528 case ARM::VST3qWB_register_Asm_32: Spacing = 2; return ARM::VST3q32_UPD;
5529 case ARM::VST3dAsm_8: Spacing = 1; return ARM::VST3d8;
5530 case ARM::VST3dAsm_16: Spacing = 1; return ARM::VST3d16;
5531 case ARM::VST3dAsm_32: Spacing = 1; return ARM::VST3d32;
5532 case ARM::VST3qAsm_8: Spacing = 2; return ARM::VST3q8;
5533 case ARM::VST3qAsm_16: Spacing = 2; return ARM::VST3q16;
5534 case ARM::VST3qAsm_32: Spacing = 2; return ARM::VST3q32;
5537 case ARM::VST4LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST4LNd8_UPD;
5538 case ARM::VST4LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST4LNd16_UPD;
5539 case ARM::VST4LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST4LNd32_UPD;
5540 case ARM::VST4LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VST4LNq16_UPD;
5541 case ARM::VST4LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST4LNq32_UPD;
5542 case ARM::VST4LNdWB_register_Asm_8: Spacing = 1; return ARM::VST4LNd8_UPD;
5543 case ARM::VST4LNdWB_register_Asm_16: Spacing = 1; return ARM::VST4LNd16_UPD;
5544 case ARM::VST4LNdWB_register_Asm_32: Spacing = 1; return ARM::VST4LNd32_UPD;
5545 case ARM::VST4LNqWB_register_Asm_16: Spacing = 2; return ARM::VST4LNq16_UPD;
5546 case ARM::VST4LNqWB_register_Asm_32: Spacing = 2; return ARM::VST4LNq32_UPD;
5547 case ARM::VST4LNdAsm_8: Spacing = 1; return ARM::VST4LNd8;
5548 case ARM::VST4LNdAsm_16: Spacing = 1; return ARM::VST4LNd16;
5549 case ARM::VST4LNdAsm_32: Spacing = 1; return ARM::VST4LNd32;
5550 case ARM::VST4LNqAsm_16: Spacing = 2; return ARM::VST4LNq16;
5551 case ARM::VST4LNqAsm_32: Spacing = 2; return ARM::VST4LNq32;
5554 case ARM::VST4dWB_fixed_Asm_8: Spacing = 1; return ARM::VST4d8_UPD;
5555 case ARM::VST4dWB_fixed_Asm_16: Spacing = 1; return ARM::VST4d16_UPD;
5556 case ARM::VST4dWB_fixed_Asm_32: Spacing = 1; return ARM::VST4d32_UPD;
5557 case ARM::VST4qWB_fixed_Asm_8: Spacing = 2; return ARM::VST4q8_UPD;
5558 case ARM::VST4qWB_fixed_Asm_16: Spacing = 2; return ARM::VST4q16_UPD;
5559 case ARM::VST4qWB_fixed_Asm_32: Spacing = 2; return ARM::VST4q32_UPD;
5560 case ARM::VST4dWB_register_Asm_8: Spacing = 1; return ARM::VST4d8_UPD;
5561 case ARM::VST4dWB_register_Asm_16: Spacing = 1; return ARM::VST4d16_UPD;
5562 case ARM::VST4dWB_register_Asm_32: Spacing = 1; return ARM::VST4d32_UPD;
5563 case ARM::VST4qWB_register_Asm_8: Spacing = 2; return ARM::VST4q8_UPD;
5564 case ARM::VST4qWB_register_Asm_16: Spacing = 2; return ARM::VST4q16_UPD;
5565 case ARM::VST4qWB_register_Asm_32: Spacing = 2; return ARM::VST4q32_UPD;
5566 case ARM::VST4dAsm_8: Spacing = 1; return ARM::VST4d8;
5567 case ARM::VST4dAsm_16: Spacing = 1; return ARM::VST4d16;
5568 case ARM::VST4dAsm_32: Spacing = 1; return ARM::VST4d32;
5569 case ARM::VST4qAsm_8: Spacing = 2; return ARM::VST4q8;
5570 case ARM::VST4qAsm_16: Spacing = 2; return ARM::VST4q16;
5571 case ARM::VST4qAsm_32: Spacing = 2; return ARM::VST4q32;
5575 static unsigned getRealVLDOpcode(unsigned Opc, unsigned &Spacing) {
5577 default: llvm_unreachable("unexpected opcode!");
5579 case ARM::VLD1LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD1LNd8_UPD;
5580 case ARM::VLD1LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD1LNd16_UPD;
5581 case ARM::VLD1LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD1LNd32_UPD;
5582 case ARM::VLD1LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD1LNd8_UPD;
5583 case ARM::VLD1LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD1LNd16_UPD;
5584 case ARM::VLD1LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD1LNd32_UPD;
5585 case ARM::VLD1LNdAsm_8: Spacing = 1; return ARM::VLD1LNd8;
5586 case ARM::VLD1LNdAsm_16: Spacing = 1; return ARM::VLD1LNd16;
5587 case ARM::VLD1LNdAsm_32: Spacing = 1; return ARM::VLD1LNd32;
5590 case ARM::VLD2LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD2LNd8_UPD;
5591 case ARM::VLD2LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD2LNd16_UPD;
5592 case ARM::VLD2LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD2LNd32_UPD;
5593 case ARM::VLD2LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD2LNq16_UPD;
5594 case ARM::VLD2LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD2LNq32_UPD;
5595 case ARM::VLD2LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD2LNd8_UPD;
5596 case ARM::VLD2LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD2LNd16_UPD;
5597 case ARM::VLD2LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD2LNd32_UPD;
5598 case ARM::VLD2LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD2LNq16_UPD;
5599 case ARM::VLD2LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD2LNq32_UPD;
5600 case ARM::VLD2LNdAsm_8: Spacing = 1; return ARM::VLD2LNd8;
5601 case ARM::VLD2LNdAsm_16: Spacing = 1; return ARM::VLD2LNd16;
5602 case ARM::VLD2LNdAsm_32: Spacing = 1; return ARM::VLD2LNd32;
5603 case ARM::VLD2LNqAsm_16: Spacing = 2; return ARM::VLD2LNq16;
5604 case ARM::VLD2LNqAsm_32: Spacing = 2; return ARM::VLD2LNq32;
5607 case ARM::VLD3DUPdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3DUPd8_UPD;
5608 case ARM::VLD3DUPdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3DUPd16_UPD;
5609 case ARM::VLD3DUPdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3DUPd32_UPD;
5610 case ARM::VLD3DUPqWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3DUPq8_UPD;
5611 case ARM::VLD3DUPqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3DUPq16_UPD;
5612 case ARM::VLD3DUPqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3DUPq32_UPD;
5613 case ARM::VLD3DUPdWB_register_Asm_8: Spacing = 1; return ARM::VLD3DUPd8_UPD;
5614 case ARM::VLD3DUPdWB_register_Asm_16: Spacing = 1; return ARM::VLD3DUPd16_UPD;
5615 case ARM::VLD3DUPdWB_register_Asm_32: Spacing = 1; return ARM::VLD3DUPd32_UPD;
5616 case ARM::VLD3DUPqWB_register_Asm_8: Spacing = 2; return ARM::VLD3DUPq8_UPD;
5617 case ARM::VLD3DUPqWB_register_Asm_16: Spacing = 2; return ARM::VLD3DUPq16_UPD;
5618 case ARM::VLD3DUPqWB_register_Asm_32: Spacing = 2; return ARM::VLD3DUPq32_UPD;
5619 case ARM::VLD3DUPdAsm_8: Spacing = 1; return ARM::VLD3DUPd8;
5620 case ARM::VLD3DUPdAsm_16: Spacing = 1; return ARM::VLD3DUPd16;
5621 case ARM::VLD3DUPdAsm_32: Spacing = 1; return ARM::VLD3DUPd32;
5622 case ARM::VLD3DUPqAsm_8: Spacing = 2; return ARM::VLD3DUPq8;
5623 case ARM::VLD3DUPqAsm_16: Spacing = 2; return ARM::VLD3DUPq16;
5624 case ARM::VLD3DUPqAsm_32: Spacing = 2; return ARM::VLD3DUPq32;
5627 case ARM::VLD3LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3LNd8_UPD;
5628 case ARM::VLD3LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3LNd16_UPD;
5629 case ARM::VLD3LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3LNd32_UPD;
5630 case ARM::VLD3LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3LNq16_UPD;
5631 case ARM::VLD3LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3LNq32_UPD;
5632 case ARM::VLD3LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD3LNd8_UPD;
5633 case ARM::VLD3LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD3LNd16_UPD;
5634 case ARM::VLD3LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD3LNd32_UPD;
5635 case ARM::VLD3LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD3LNq16_UPD;
5636 case ARM::VLD3LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD3LNq32_UPD;
5637 case ARM::VLD3LNdAsm_8: Spacing = 1; return ARM::VLD3LNd8;
5638 case ARM::VLD3LNdAsm_16: Spacing = 1; return ARM::VLD3LNd16;
5639 case ARM::VLD3LNdAsm_32: Spacing = 1; return ARM::VLD3LNd32;
5640 case ARM::VLD3LNqAsm_16: Spacing = 2; return ARM::VLD3LNq16;
5641 case ARM::VLD3LNqAsm_32: Spacing = 2; return ARM::VLD3LNq32;
5644 case ARM::VLD3dWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3d8_UPD;
5645 case ARM::VLD3dWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3d16_UPD;
5646 case ARM::VLD3dWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3d32_UPD;
5647 case ARM::VLD3qWB_fixed_Asm_8: Spacing = 2; return ARM::VLD3q8_UPD;
5648 case ARM::VLD3qWB_fixed_Asm_16: Spacing = 2; return ARM::VLD3q16_UPD;
5649 case ARM::VLD3qWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3q32_UPD;
5650 case ARM::VLD3dWB_register_Asm_8: Spacing = 1; return ARM::VLD3d8_UPD;
5651 case ARM::VLD3dWB_register_Asm_16: Spacing = 1; return ARM::VLD3d16_UPD;
5652 case ARM::VLD3dWB_register_Asm_32: Spacing = 1; return ARM::VLD3d32_UPD;
5653 case ARM::VLD3qWB_register_Asm_8: Spacing = 2; return ARM::VLD3q8_UPD;
5654 case ARM::VLD3qWB_register_Asm_16: Spacing = 2; return ARM::VLD3q16_UPD;
5655 case ARM::VLD3qWB_register_Asm_32: Spacing = 2; return ARM::VLD3q32_UPD;
5656 case ARM::VLD3dAsm_8: Spacing = 1; return ARM::VLD3d8;
5657 case ARM::VLD3dAsm_16: Spacing = 1; return ARM::VLD3d16;
5658 case ARM::VLD3dAsm_32: Spacing = 1; return ARM::VLD3d32;
5659 case ARM::VLD3qAsm_8: Spacing = 2; return ARM::VLD3q8;
5660 case ARM::VLD3qAsm_16: Spacing = 2; return ARM::VLD3q16;
5661 case ARM::VLD3qAsm_32: Spacing = 2; return ARM::VLD3q32;
5664 case ARM::VLD4LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4LNd8_UPD;
5665 case ARM::VLD4LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4LNd16_UPD;
5666 case ARM::VLD4LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4LNd32_UPD;
5667 case ARM::VLD4LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4LNq16_UPD;
5668 case ARM::VLD4LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4LNq32_UPD;
5669 case ARM::VLD4LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD4LNd8_UPD;
5670 case ARM::VLD4LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD4LNd16_UPD;
5671 case ARM::VLD4LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD4LNd32_UPD;
5672 case ARM::VLD4LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD4LNq16_UPD;
5673 case ARM::VLD4LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD4LNq32_UPD;
5674 case ARM::VLD4LNdAsm_8: Spacing = 1; return ARM::VLD4LNd8;
5675 case ARM::VLD4LNdAsm_16: Spacing = 1; return ARM::VLD4LNd16;
5676 case ARM::VLD4LNdAsm_32: Spacing = 1; return ARM::VLD4LNd32;
5677 case ARM::VLD4LNqAsm_16: Spacing = 2; return ARM::VLD4LNq16;
5678 case ARM::VLD4LNqAsm_32: Spacing = 2; return ARM::VLD4LNq32;
5681 case ARM::VLD4DUPdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4DUPd8_UPD;
5682 case ARM::VLD4DUPdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4DUPd16_UPD;
5683 case ARM::VLD4DUPdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4DUPd32_UPD;
5684 case ARM::VLD4DUPqWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4DUPq8_UPD;
5685 case ARM::VLD4DUPqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4DUPq16_UPD;
5686 case ARM::VLD4DUPqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4DUPq32_UPD;
5687 case ARM::VLD4DUPdWB_register_Asm_8: Spacing = 1; return ARM::VLD4DUPd8_UPD;
5688 case ARM::VLD4DUPdWB_register_Asm_16: Spacing = 1; return ARM::VLD4DUPd16_UPD;
5689 case ARM::VLD4DUPdWB_register_Asm_32: Spacing = 1; return ARM::VLD4DUPd32_UPD;
5690 case ARM::VLD4DUPqWB_register_Asm_8: Spacing = 2; return ARM::VLD4DUPq8_UPD;
5691 case ARM::VLD4DUPqWB_register_Asm_16: Spacing = 2; return ARM::VLD4DUPq16_UPD;
5692 case ARM::VLD4DUPqWB_register_Asm_32: Spacing = 2; return ARM::VLD4DUPq32_UPD;
5693 case ARM::VLD4DUPdAsm_8: Spacing = 1; return ARM::VLD4DUPd8;
5694 case ARM::VLD4DUPdAsm_16: Spacing = 1; return ARM::VLD4DUPd16;
5695 case ARM::VLD4DUPdAsm_32: Spacing = 1; return ARM::VLD4DUPd32;
5696 case ARM::VLD4DUPqAsm_8: Spacing = 2; return ARM::VLD4DUPq8;
5697 case ARM::VLD4DUPqAsm_16: Spacing = 2; return ARM::VLD4DUPq16;
5698 case ARM::VLD4DUPqAsm_32: Spacing = 2; return ARM::VLD4DUPq32;
5701 case ARM::VLD4dWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4d8_UPD;
5702 case ARM::VLD4dWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4d16_UPD;
5703 case ARM::VLD4dWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4d32_UPD;
5704 case ARM::VLD4qWB_fixed_Asm_8: Spacing = 2; return ARM::VLD4q8_UPD;
5705 case ARM::VLD4qWB_fixed_Asm_16: Spacing = 2; return ARM::VLD4q16_UPD;
5706 case ARM::VLD4qWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4q32_UPD;
5707 case ARM::VLD4dWB_register_Asm_8: Spacing = 1; return ARM::VLD4d8_UPD;
5708 case ARM::VLD4dWB_register_Asm_16: Spacing = 1; return ARM::VLD4d16_UPD;
5709 case ARM::VLD4dWB_register_Asm_32: Spacing = 1; return ARM::VLD4d32_UPD;
5710 case ARM::VLD4qWB_register_Asm_8: Spacing = 2; return ARM::VLD4q8_UPD;
5711 case ARM::VLD4qWB_register_Asm_16: Spacing = 2; return ARM::VLD4q16_UPD;
5712 case ARM::VLD4qWB_register_Asm_32: Spacing = 2; return ARM::VLD4q32_UPD;
5713 case ARM::VLD4dAsm_8: Spacing = 1; return ARM::VLD4d8;
5714 case ARM::VLD4dAsm_16: Spacing = 1; return ARM::VLD4d16;
5715 case ARM::VLD4dAsm_32: Spacing = 1; return ARM::VLD4d32;
5716 case ARM::VLD4qAsm_8: Spacing = 2; return ARM::VLD4q8;
5717 case ARM::VLD4qAsm_16: Spacing = 2; return ARM::VLD4q16;
5718 case ARM::VLD4qAsm_32: Spacing = 2; return ARM::VLD4q32;
5723 processInstruction(MCInst &Inst,
5724 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
5725 switch (Inst.getOpcode()) {
5726 // Alias for alternate form of 'ADR Rd, #imm' instruction.
5728 if (Inst.getOperand(1).getReg() != ARM::PC ||
5729 Inst.getOperand(5).getReg() != 0)
5732 TmpInst.setOpcode(ARM::ADR);
5733 TmpInst.addOperand(Inst.getOperand(0));
5734 TmpInst.addOperand(Inst.getOperand(2));
5735 TmpInst.addOperand(Inst.getOperand(3));
5736 TmpInst.addOperand(Inst.getOperand(4));
5740 // Aliases for alternate PC+imm syntax of LDR instructions.
5741 case ARM::t2LDRpcrel:
5742 // Select the narrow version if the immediate will fit.
5743 if (Inst.getOperand(1).getImm() > 0 &&
5744 Inst.getOperand(1).getImm() <= 0xff)
5745 Inst.setOpcode(ARM::tLDRpci);
5747 Inst.setOpcode(ARM::t2LDRpci);
5749 case ARM::t2LDRBpcrel:
5750 Inst.setOpcode(ARM::t2LDRBpci);
5752 case ARM::t2LDRHpcrel:
5753 Inst.setOpcode(ARM::t2LDRHpci);
5755 case ARM::t2LDRSBpcrel:
5756 Inst.setOpcode(ARM::t2LDRSBpci);
5758 case ARM::t2LDRSHpcrel:
5759 Inst.setOpcode(ARM::t2LDRSHpci);
5761 // Handle NEON VST complex aliases.
5762 case ARM::VST1LNdWB_register_Asm_8:
5763 case ARM::VST1LNdWB_register_Asm_16:
5764 case ARM::VST1LNdWB_register_Asm_32: {
5766 // Shuffle the operands around so the lane index operand is in the
5769 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5770 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5771 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5772 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5773 TmpInst.addOperand(Inst.getOperand(4)); // Rm
5774 TmpInst.addOperand(Inst.getOperand(0)); // Vd
5775 TmpInst.addOperand(Inst.getOperand(1)); // lane
5776 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
5777 TmpInst.addOperand(Inst.getOperand(6));
5782 case ARM::VST2LNdWB_register_Asm_8:
5783 case ARM::VST2LNdWB_register_Asm_16:
5784 case ARM::VST2LNdWB_register_Asm_32:
5785 case ARM::VST2LNqWB_register_Asm_16:
5786 case ARM::VST2LNqWB_register_Asm_32: {
5788 // Shuffle the operands around so the lane index operand is in the
5791 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5792 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5793 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5794 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5795 TmpInst.addOperand(Inst.getOperand(4)); // Rm
5796 TmpInst.addOperand(Inst.getOperand(0)); // Vd
5797 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5799 TmpInst.addOperand(Inst.getOperand(1)); // lane
5800 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
5801 TmpInst.addOperand(Inst.getOperand(6));
5806 case ARM::VST3LNdWB_register_Asm_8:
5807 case ARM::VST3LNdWB_register_Asm_16:
5808 case ARM::VST3LNdWB_register_Asm_32:
5809 case ARM::VST3LNqWB_register_Asm_16:
5810 case ARM::VST3LNqWB_register_Asm_32: {
5812 // Shuffle the operands around so the lane index operand is in the
5815 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5816 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5817 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5818 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5819 TmpInst.addOperand(Inst.getOperand(4)); // Rm
5820 TmpInst.addOperand(Inst.getOperand(0)); // Vd
5821 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5823 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5825 TmpInst.addOperand(Inst.getOperand(1)); // lane
5826 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
5827 TmpInst.addOperand(Inst.getOperand(6));
5832 case ARM::VST4LNdWB_register_Asm_8:
5833 case ARM::VST4LNdWB_register_Asm_16:
5834 case ARM::VST4LNdWB_register_Asm_32:
5835 case ARM::VST4LNqWB_register_Asm_16:
5836 case ARM::VST4LNqWB_register_Asm_32: {
5838 // Shuffle the operands around so the lane index operand is in the
5841 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5842 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5843 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5844 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5845 TmpInst.addOperand(Inst.getOperand(4)); // Rm
5846 TmpInst.addOperand(Inst.getOperand(0)); // Vd
5847 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5849 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5851 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5853 TmpInst.addOperand(Inst.getOperand(1)); // lane
5854 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
5855 TmpInst.addOperand(Inst.getOperand(6));
5860 case ARM::VST1LNdWB_fixed_Asm_8:
5861 case ARM::VST1LNdWB_fixed_Asm_16:
5862 case ARM::VST1LNdWB_fixed_Asm_32: {
5864 // Shuffle the operands around so the lane index operand is in the
5867 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5868 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5869 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5870 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5871 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
5872 TmpInst.addOperand(Inst.getOperand(0)); // Vd
5873 TmpInst.addOperand(Inst.getOperand(1)); // lane
5874 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
5875 TmpInst.addOperand(Inst.getOperand(5));
5880 case ARM::VST2LNdWB_fixed_Asm_8:
5881 case ARM::VST2LNdWB_fixed_Asm_16:
5882 case ARM::VST2LNdWB_fixed_Asm_32:
5883 case ARM::VST2LNqWB_fixed_Asm_16:
5884 case ARM::VST2LNqWB_fixed_Asm_32: {
5886 // Shuffle the operands around so the lane index operand is in the
5889 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5890 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5891 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5892 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5893 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
5894 TmpInst.addOperand(Inst.getOperand(0)); // Vd
5895 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5897 TmpInst.addOperand(Inst.getOperand(1)); // lane
5898 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
5899 TmpInst.addOperand(Inst.getOperand(5));
5904 case ARM::VST3LNdWB_fixed_Asm_8:
5905 case ARM::VST3LNdWB_fixed_Asm_16:
5906 case ARM::VST3LNdWB_fixed_Asm_32:
5907 case ARM::VST3LNqWB_fixed_Asm_16:
5908 case ARM::VST3LNqWB_fixed_Asm_32: {
5910 // Shuffle the operands around so the lane index operand is in the
5913 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5914 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5915 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5916 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5917 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
5918 TmpInst.addOperand(Inst.getOperand(0)); // Vd
5919 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5921 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5923 TmpInst.addOperand(Inst.getOperand(1)); // lane
5924 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
5925 TmpInst.addOperand(Inst.getOperand(5));
5930 case ARM::VST4LNdWB_fixed_Asm_8:
5931 case ARM::VST4LNdWB_fixed_Asm_16:
5932 case ARM::VST4LNdWB_fixed_Asm_32:
5933 case ARM::VST4LNqWB_fixed_Asm_16:
5934 case ARM::VST4LNqWB_fixed_Asm_32: {
5936 // Shuffle the operands around so the lane index operand is in the
5939 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5940 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5941 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5942 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5943 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
5944 TmpInst.addOperand(Inst.getOperand(0)); // Vd
5945 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5947 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5949 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5951 TmpInst.addOperand(Inst.getOperand(1)); // lane
5952 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
5953 TmpInst.addOperand(Inst.getOperand(5));
5958 case ARM::VST1LNdAsm_8:
5959 case ARM::VST1LNdAsm_16:
5960 case ARM::VST1LNdAsm_32: {
5962 // Shuffle the operands around so the lane index operand is in the
5965 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5966 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5967 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5968 TmpInst.addOperand(Inst.getOperand(0)); // Vd
5969 TmpInst.addOperand(Inst.getOperand(1)); // lane
5970 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
5971 TmpInst.addOperand(Inst.getOperand(5));
5976 case ARM::VST2LNdAsm_8:
5977 case ARM::VST2LNdAsm_16:
5978 case ARM::VST2LNdAsm_32:
5979 case ARM::VST2LNqAsm_16:
5980 case ARM::VST2LNqAsm_32: {
5982 // Shuffle the operands around so the lane index operand is in the
5985 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5986 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5987 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5988 TmpInst.addOperand(Inst.getOperand(0)); // Vd
5989 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5991 TmpInst.addOperand(Inst.getOperand(1)); // lane
5992 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
5993 TmpInst.addOperand(Inst.getOperand(5));
5998 case ARM::VST3LNdAsm_8:
5999 case ARM::VST3LNdAsm_16:
6000 case ARM::VST3LNdAsm_32:
6001 case ARM::VST3LNqAsm_16:
6002 case ARM::VST3LNqAsm_32: {
6004 // Shuffle the operands around so the lane index operand is in the
6007 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6008 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6009 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6010 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6011 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6013 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6015 TmpInst.addOperand(Inst.getOperand(1)); // lane
6016 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6017 TmpInst.addOperand(Inst.getOperand(5));
6022 case ARM::VST4LNdAsm_8:
6023 case ARM::VST4LNdAsm_16:
6024 case ARM::VST4LNdAsm_32:
6025 case ARM::VST4LNqAsm_16:
6026 case ARM::VST4LNqAsm_32: {
6028 // Shuffle the operands around so the lane index operand is in the
6031 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6032 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6033 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6034 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6035 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6037 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6039 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6041 TmpInst.addOperand(Inst.getOperand(1)); // lane
6042 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6043 TmpInst.addOperand(Inst.getOperand(5));
6048 // Handle NEON VLD complex aliases.
6049 case ARM::VLD1LNdWB_register_Asm_8:
6050 case ARM::VLD1LNdWB_register_Asm_16:
6051 case ARM::VLD1LNdWB_register_Asm_32: {
6053 // Shuffle the operands around so the lane index operand is in the
6056 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6057 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6058 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6059 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6060 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6061 TmpInst.addOperand(Inst.getOperand(4)); // Rm
6062 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6063 TmpInst.addOperand(Inst.getOperand(1)); // lane
6064 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6065 TmpInst.addOperand(Inst.getOperand(6));
6070 case ARM::VLD2LNdWB_register_Asm_8:
6071 case ARM::VLD2LNdWB_register_Asm_16:
6072 case ARM::VLD2LNdWB_register_Asm_32:
6073 case ARM::VLD2LNqWB_register_Asm_16:
6074 case ARM::VLD2LNqWB_register_Asm_32: {
6076 // Shuffle the operands around so the lane index operand is in the
6079 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6080 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6081 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6083 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6084 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6085 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6086 TmpInst.addOperand(Inst.getOperand(4)); // Rm
6087 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6088 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6090 TmpInst.addOperand(Inst.getOperand(1)); // lane
6091 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6092 TmpInst.addOperand(Inst.getOperand(6));
6097 case ARM::VLD3LNdWB_register_Asm_8:
6098 case ARM::VLD3LNdWB_register_Asm_16:
6099 case ARM::VLD3LNdWB_register_Asm_32:
6100 case ARM::VLD3LNqWB_register_Asm_16:
6101 case ARM::VLD3LNqWB_register_Asm_32: {
6103 // Shuffle the operands around so the lane index operand is in the
6106 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6107 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6108 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6110 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6112 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6113 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6114 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6115 TmpInst.addOperand(Inst.getOperand(4)); // Rm
6116 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6117 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6119 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6121 TmpInst.addOperand(Inst.getOperand(1)); // lane
6122 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6123 TmpInst.addOperand(Inst.getOperand(6));
6128 case ARM::VLD4LNdWB_register_Asm_8:
6129 case ARM::VLD4LNdWB_register_Asm_16:
6130 case ARM::VLD4LNdWB_register_Asm_32:
6131 case ARM::VLD4LNqWB_register_Asm_16:
6132 case ARM::VLD4LNqWB_register_Asm_32: {
6134 // Shuffle the operands around so the lane index operand is in the
6137 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6138 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6139 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6141 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6143 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6145 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6146 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6147 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6148 TmpInst.addOperand(Inst.getOperand(4)); // Rm
6149 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6150 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6152 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6154 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6156 TmpInst.addOperand(Inst.getOperand(1)); // lane
6157 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6158 TmpInst.addOperand(Inst.getOperand(6));
6163 case ARM::VLD1LNdWB_fixed_Asm_8:
6164 case ARM::VLD1LNdWB_fixed_Asm_16:
6165 case ARM::VLD1LNdWB_fixed_Asm_32: {
6167 // Shuffle the operands around so the lane index operand is in the
6170 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6171 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6172 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6173 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6174 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6175 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6176 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6177 TmpInst.addOperand(Inst.getOperand(1)); // lane
6178 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6179 TmpInst.addOperand(Inst.getOperand(5));
6184 case ARM::VLD2LNdWB_fixed_Asm_8:
6185 case ARM::VLD2LNdWB_fixed_Asm_16:
6186 case ARM::VLD2LNdWB_fixed_Asm_32:
6187 case ARM::VLD2LNqWB_fixed_Asm_16:
6188 case ARM::VLD2LNqWB_fixed_Asm_32: {
6190 // Shuffle the operands around so the lane index operand is in the
6193 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6194 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6195 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6197 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6198 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6199 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6200 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6201 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6202 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6204 TmpInst.addOperand(Inst.getOperand(1)); // lane
6205 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6206 TmpInst.addOperand(Inst.getOperand(5));
6211 case ARM::VLD3LNdWB_fixed_Asm_8:
6212 case ARM::VLD3LNdWB_fixed_Asm_16:
6213 case ARM::VLD3LNdWB_fixed_Asm_32:
6214 case ARM::VLD3LNqWB_fixed_Asm_16:
6215 case ARM::VLD3LNqWB_fixed_Asm_32: {
6217 // Shuffle the operands around so the lane index operand is in the
6220 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6221 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6222 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6224 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6226 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6227 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6228 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6229 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6230 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6231 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6233 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6235 TmpInst.addOperand(Inst.getOperand(1)); // lane
6236 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6237 TmpInst.addOperand(Inst.getOperand(5));
6242 case ARM::VLD4LNdWB_fixed_Asm_8:
6243 case ARM::VLD4LNdWB_fixed_Asm_16:
6244 case ARM::VLD4LNdWB_fixed_Asm_32:
6245 case ARM::VLD4LNqWB_fixed_Asm_16:
6246 case ARM::VLD4LNqWB_fixed_Asm_32: {
6248 // Shuffle the operands around so the lane index operand is in the
6251 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6252 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6253 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6255 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6257 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6259 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6260 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6261 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6262 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6263 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6264 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6266 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6268 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6270 TmpInst.addOperand(Inst.getOperand(1)); // lane
6271 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6272 TmpInst.addOperand(Inst.getOperand(5));
6277 case ARM::VLD1LNdAsm_8:
6278 case ARM::VLD1LNdAsm_16:
6279 case ARM::VLD1LNdAsm_32: {
6281 // Shuffle the operands around so the lane index operand is in the
6284 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6285 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6286 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6287 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6288 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6289 TmpInst.addOperand(Inst.getOperand(1)); // lane
6290 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6291 TmpInst.addOperand(Inst.getOperand(5));
6296 case ARM::VLD2LNdAsm_8:
6297 case ARM::VLD2LNdAsm_16:
6298 case ARM::VLD2LNdAsm_32:
6299 case ARM::VLD2LNqAsm_16:
6300 case ARM::VLD2LNqAsm_32: {
6302 // Shuffle the operands around so the lane index operand is in the
6305 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6306 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6307 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6309 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6310 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6311 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6312 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6314 TmpInst.addOperand(Inst.getOperand(1)); // lane
6315 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6316 TmpInst.addOperand(Inst.getOperand(5));
6321 case ARM::VLD3LNdAsm_8:
6322 case ARM::VLD3LNdAsm_16:
6323 case ARM::VLD3LNdAsm_32:
6324 case ARM::VLD3LNqAsm_16:
6325 case ARM::VLD3LNqAsm_32: {
6327 // Shuffle the operands around so the lane index operand is in the
6330 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6331 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6332 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6334 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6336 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6337 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6338 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6339 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6341 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6343 TmpInst.addOperand(Inst.getOperand(1)); // lane
6344 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6345 TmpInst.addOperand(Inst.getOperand(5));
6350 case ARM::VLD4LNdAsm_8:
6351 case ARM::VLD4LNdAsm_16:
6352 case ARM::VLD4LNdAsm_32:
6353 case ARM::VLD4LNqAsm_16:
6354 case ARM::VLD4LNqAsm_32: {
6356 // Shuffle the operands around so the lane index operand is in the
6359 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6360 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6361 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6363 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6365 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6367 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6368 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6369 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6370 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6372 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6374 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6376 TmpInst.addOperand(Inst.getOperand(1)); // lane
6377 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6378 TmpInst.addOperand(Inst.getOperand(5));
6383 // VLD3DUP single 3-element structure to all lanes instructions.
6384 case ARM::VLD3DUPdAsm_8:
6385 case ARM::VLD3DUPdAsm_16:
6386 case ARM::VLD3DUPdAsm_32:
6387 case ARM::VLD3DUPqAsm_8:
6388 case ARM::VLD3DUPqAsm_16:
6389 case ARM::VLD3DUPqAsm_32: {
6392 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6393 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6394 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6396 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6398 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6399 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6400 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6401 TmpInst.addOperand(Inst.getOperand(4));
6406 case ARM::VLD3DUPdWB_fixed_Asm_8:
6407 case ARM::VLD3DUPdWB_fixed_Asm_16:
6408 case ARM::VLD3DUPdWB_fixed_Asm_32:
6409 case ARM::VLD3DUPqWB_fixed_Asm_8:
6410 case ARM::VLD3DUPqWB_fixed_Asm_16:
6411 case ARM::VLD3DUPqWB_fixed_Asm_32: {
6414 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6415 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6416 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6418 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6420 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6421 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6422 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6423 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6424 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6425 TmpInst.addOperand(Inst.getOperand(4));
6430 case ARM::VLD3DUPdWB_register_Asm_8:
6431 case ARM::VLD3DUPdWB_register_Asm_16:
6432 case ARM::VLD3DUPdWB_register_Asm_32:
6433 case ARM::VLD3DUPqWB_register_Asm_8:
6434 case ARM::VLD3DUPqWB_register_Asm_16:
6435 case ARM::VLD3DUPqWB_register_Asm_32: {
6438 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6439 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6440 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6442 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6444 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6445 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6446 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6447 TmpInst.addOperand(Inst.getOperand(3)); // Rm
6448 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6449 TmpInst.addOperand(Inst.getOperand(5));
6454 // VLD3 multiple 3-element structure instructions.
6455 case ARM::VLD3dAsm_8:
6456 case ARM::VLD3dAsm_16:
6457 case ARM::VLD3dAsm_32:
6458 case ARM::VLD3qAsm_8:
6459 case ARM::VLD3qAsm_16:
6460 case ARM::VLD3qAsm_32: {
6463 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6464 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6465 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6467 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6469 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6470 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6471 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6472 TmpInst.addOperand(Inst.getOperand(4));
6477 case ARM::VLD3dWB_fixed_Asm_8:
6478 case ARM::VLD3dWB_fixed_Asm_16:
6479 case ARM::VLD3dWB_fixed_Asm_32:
6480 case ARM::VLD3qWB_fixed_Asm_8:
6481 case ARM::VLD3qWB_fixed_Asm_16:
6482 case ARM::VLD3qWB_fixed_Asm_32: {
6485 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6486 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6487 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6489 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6491 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6492 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6493 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6494 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6495 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6496 TmpInst.addOperand(Inst.getOperand(4));
6501 case ARM::VLD3dWB_register_Asm_8:
6502 case ARM::VLD3dWB_register_Asm_16:
6503 case ARM::VLD3dWB_register_Asm_32:
6504 case ARM::VLD3qWB_register_Asm_8:
6505 case ARM::VLD3qWB_register_Asm_16:
6506 case ARM::VLD3qWB_register_Asm_32: {
6509 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6510 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6511 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6513 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6515 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6516 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6517 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6518 TmpInst.addOperand(Inst.getOperand(3)); // Rm
6519 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6520 TmpInst.addOperand(Inst.getOperand(5));
6525 // VLD4DUP single 3-element structure to all lanes instructions.
6526 case ARM::VLD4DUPdAsm_8:
6527 case ARM::VLD4DUPdAsm_16:
6528 case ARM::VLD4DUPdAsm_32:
6529 case ARM::VLD4DUPqAsm_8:
6530 case ARM::VLD4DUPqAsm_16:
6531 case ARM::VLD4DUPqAsm_32: {
6534 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6535 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6536 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6538 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6540 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6542 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6543 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6544 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6545 TmpInst.addOperand(Inst.getOperand(4));
6550 case ARM::VLD4DUPdWB_fixed_Asm_8:
6551 case ARM::VLD4DUPdWB_fixed_Asm_16:
6552 case ARM::VLD4DUPdWB_fixed_Asm_32:
6553 case ARM::VLD4DUPqWB_fixed_Asm_8:
6554 case ARM::VLD4DUPqWB_fixed_Asm_16:
6555 case ARM::VLD4DUPqWB_fixed_Asm_32: {
6558 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6559 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6560 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6562 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6564 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6566 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6567 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6568 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6569 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6570 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6571 TmpInst.addOperand(Inst.getOperand(4));
6576 case ARM::VLD4DUPdWB_register_Asm_8:
6577 case ARM::VLD4DUPdWB_register_Asm_16:
6578 case ARM::VLD4DUPdWB_register_Asm_32:
6579 case ARM::VLD4DUPqWB_register_Asm_8:
6580 case ARM::VLD4DUPqWB_register_Asm_16:
6581 case ARM::VLD4DUPqWB_register_Asm_32: {
6584 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6585 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6586 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6588 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6590 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6592 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6593 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6594 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6595 TmpInst.addOperand(Inst.getOperand(3)); // Rm
6596 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6597 TmpInst.addOperand(Inst.getOperand(5));
6602 // VLD4 multiple 4-element structure instructions.
6603 case ARM::VLD4dAsm_8:
6604 case ARM::VLD4dAsm_16:
6605 case ARM::VLD4dAsm_32:
6606 case ARM::VLD4qAsm_8:
6607 case ARM::VLD4qAsm_16:
6608 case ARM::VLD4qAsm_32: {
6611 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6612 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6613 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6615 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6617 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6619 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6620 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6621 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6622 TmpInst.addOperand(Inst.getOperand(4));
6627 case ARM::VLD4dWB_fixed_Asm_8:
6628 case ARM::VLD4dWB_fixed_Asm_16:
6629 case ARM::VLD4dWB_fixed_Asm_32:
6630 case ARM::VLD4qWB_fixed_Asm_8:
6631 case ARM::VLD4qWB_fixed_Asm_16:
6632 case ARM::VLD4qWB_fixed_Asm_32: {
6635 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6636 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6637 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6639 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6641 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6643 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6644 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6645 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6646 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6647 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6648 TmpInst.addOperand(Inst.getOperand(4));
6653 case ARM::VLD4dWB_register_Asm_8:
6654 case ARM::VLD4dWB_register_Asm_16:
6655 case ARM::VLD4dWB_register_Asm_32:
6656 case ARM::VLD4qWB_register_Asm_8:
6657 case ARM::VLD4qWB_register_Asm_16:
6658 case ARM::VLD4qWB_register_Asm_32: {
6661 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6662 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6663 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6665 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6667 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6669 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6670 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6671 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6672 TmpInst.addOperand(Inst.getOperand(3)); // Rm
6673 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6674 TmpInst.addOperand(Inst.getOperand(5));
6679 // VST3 multiple 3-element structure instructions.
6680 case ARM::VST3dAsm_8:
6681 case ARM::VST3dAsm_16:
6682 case ARM::VST3dAsm_32:
6683 case ARM::VST3qAsm_8:
6684 case ARM::VST3qAsm_16:
6685 case ARM::VST3qAsm_32: {
6688 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6689 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6690 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6691 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6692 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6694 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6696 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6697 TmpInst.addOperand(Inst.getOperand(4));
6702 case ARM::VST3dWB_fixed_Asm_8:
6703 case ARM::VST3dWB_fixed_Asm_16:
6704 case ARM::VST3dWB_fixed_Asm_32:
6705 case ARM::VST3qWB_fixed_Asm_8:
6706 case ARM::VST3qWB_fixed_Asm_16:
6707 case ARM::VST3qWB_fixed_Asm_32: {
6710 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6711 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6712 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6713 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6714 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6715 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6716 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6718 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6720 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6721 TmpInst.addOperand(Inst.getOperand(4));
6726 case ARM::VST3dWB_register_Asm_8:
6727 case ARM::VST3dWB_register_Asm_16:
6728 case ARM::VST3dWB_register_Asm_32:
6729 case ARM::VST3qWB_register_Asm_8:
6730 case ARM::VST3qWB_register_Asm_16:
6731 case ARM::VST3qWB_register_Asm_32: {
6734 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6735 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6736 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6737 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6738 TmpInst.addOperand(Inst.getOperand(3)); // Rm
6739 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6740 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6742 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6744 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6745 TmpInst.addOperand(Inst.getOperand(5));
6750 // VST4 multiple 3-element structure instructions.
6751 case ARM::VST4dAsm_8:
6752 case ARM::VST4dAsm_16:
6753 case ARM::VST4dAsm_32:
6754 case ARM::VST4qAsm_8:
6755 case ARM::VST4qAsm_16:
6756 case ARM::VST4qAsm_32: {
6759 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6760 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6761 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6762 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6763 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6765 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6767 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6769 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6770 TmpInst.addOperand(Inst.getOperand(4));
6775 case ARM::VST4dWB_fixed_Asm_8:
6776 case ARM::VST4dWB_fixed_Asm_16:
6777 case ARM::VST4dWB_fixed_Asm_32:
6778 case ARM::VST4qWB_fixed_Asm_8:
6779 case ARM::VST4qWB_fixed_Asm_16:
6780 case ARM::VST4qWB_fixed_Asm_32: {
6783 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6784 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6785 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6786 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6787 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6788 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6789 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6791 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6793 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6795 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6796 TmpInst.addOperand(Inst.getOperand(4));
6801 case ARM::VST4dWB_register_Asm_8:
6802 case ARM::VST4dWB_register_Asm_16:
6803 case ARM::VST4dWB_register_Asm_32:
6804 case ARM::VST4qWB_register_Asm_8:
6805 case ARM::VST4qWB_register_Asm_16:
6806 case ARM::VST4qWB_register_Asm_32: {
6809 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6810 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6811 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6812 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6813 TmpInst.addOperand(Inst.getOperand(3)); // Rm
6814 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6815 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6817 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6819 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6821 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6822 TmpInst.addOperand(Inst.getOperand(5));
6827 // Handle encoding choice for the shift-immediate instructions.
6830 case ARM::t2ASRri: {
6831 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
6832 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
6833 Inst.getOperand(5).getReg() == (inITBlock() ? 0 : ARM::CPSR) &&
6834 !(static_cast<ARMOperand*>(Operands[3])->isToken() &&
6835 static_cast<ARMOperand*>(Operands[3])->getToken() == ".w")) {
6837 switch (Inst.getOpcode()) {
6838 default: llvm_unreachable("unexpected opcode");
6839 case ARM::t2LSLri: NewOpc = ARM::tLSLri; break;
6840 case ARM::t2LSRri: NewOpc = ARM::tLSRri; break;
6841 case ARM::t2ASRri: NewOpc = ARM::tASRri; break;
6843 // The Thumb1 operands aren't in the same order. Awesome, eh?
6845 TmpInst.setOpcode(NewOpc);
6846 TmpInst.addOperand(Inst.getOperand(0));
6847 TmpInst.addOperand(Inst.getOperand(5));
6848 TmpInst.addOperand(Inst.getOperand(1));
6849 TmpInst.addOperand(Inst.getOperand(2));
6850 TmpInst.addOperand(Inst.getOperand(3));
6851 TmpInst.addOperand(Inst.getOperand(4));
6858 // Handle the Thumb2 mode MOV complex aliases.
6860 case ARM::t2MOVSsr: {
6861 // Which instruction to expand to depends on the CCOut operand and
6862 // whether we're in an IT block if the register operands are low
6864 bool isNarrow = false;
6865 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
6866 isARMLowRegister(Inst.getOperand(1).getReg()) &&
6867 isARMLowRegister(Inst.getOperand(2).getReg()) &&
6868 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
6869 inITBlock() == (Inst.getOpcode() == ARM::t2MOVsr))
6873 switch(ARM_AM::getSORegShOp(Inst.getOperand(3).getImm())) {
6874 default: llvm_unreachable("unexpected opcode!");
6875 case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRrr : ARM::t2ASRrr; break;
6876 case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRrr : ARM::t2LSRrr; break;
6877 case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLrr : ARM::t2LSLrr; break;
6878 case ARM_AM::ror: newOpc = isNarrow ? ARM::tROR : ARM::t2RORrr; break;
6880 TmpInst.setOpcode(newOpc);
6881 TmpInst.addOperand(Inst.getOperand(0)); // Rd
6883 TmpInst.addOperand(MCOperand::CreateReg(
6884 Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0));
6885 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6886 TmpInst.addOperand(Inst.getOperand(2)); // Rm
6887 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6888 TmpInst.addOperand(Inst.getOperand(5));
6890 TmpInst.addOperand(MCOperand::CreateReg(
6891 Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0));
6896 case ARM::t2MOVSsi: {
6897 // Which instruction to expand to depends on the CCOut operand and
6898 // whether we're in an IT block if the register operands are low
6900 bool isNarrow = false;
6901 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
6902 isARMLowRegister(Inst.getOperand(1).getReg()) &&
6903 inITBlock() == (Inst.getOpcode() == ARM::t2MOVsi))
6907 switch(ARM_AM::getSORegShOp(Inst.getOperand(2).getImm())) {
6908 default: llvm_unreachable("unexpected opcode!");
6909 case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRri : ARM::t2ASRri; break;
6910 case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRri : ARM::t2LSRri; break;
6911 case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLri : ARM::t2LSLri; break;
6912 case ARM_AM::ror: newOpc = ARM::t2RORri; isNarrow = false; break;
6913 case ARM_AM::rrx: isNarrow = false; newOpc = ARM::t2RRX; break;
6915 unsigned Amount = ARM_AM::getSORegOffset(Inst.getOperand(2).getImm());
6916 if (Amount == 32) Amount = 0;
6917 TmpInst.setOpcode(newOpc);
6918 TmpInst.addOperand(Inst.getOperand(0)); // Rd
6920 TmpInst.addOperand(MCOperand::CreateReg(
6921 Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0));
6922 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6923 if (newOpc != ARM::t2RRX)
6924 TmpInst.addOperand(MCOperand::CreateImm(Amount));
6925 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6926 TmpInst.addOperand(Inst.getOperand(4));
6928 TmpInst.addOperand(MCOperand::CreateReg(
6929 Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0));
6933 // Handle the ARM mode MOV complex aliases.
6938 ARM_AM::ShiftOpc ShiftTy;
6939 switch(Inst.getOpcode()) {
6940 default: llvm_unreachable("unexpected opcode!");
6941 case ARM::ASRr: ShiftTy = ARM_AM::asr; break;
6942 case ARM::LSRr: ShiftTy = ARM_AM::lsr; break;
6943 case ARM::LSLr: ShiftTy = ARM_AM::lsl; break;
6944 case ARM::RORr: ShiftTy = ARM_AM::ror; break;
6946 unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, 0);
6948 TmpInst.setOpcode(ARM::MOVsr);
6949 TmpInst.addOperand(Inst.getOperand(0)); // Rd
6950 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6951 TmpInst.addOperand(Inst.getOperand(2)); // Rm
6952 TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty
6953 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6954 TmpInst.addOperand(Inst.getOperand(4));
6955 TmpInst.addOperand(Inst.getOperand(5)); // cc_out
6963 ARM_AM::ShiftOpc ShiftTy;
6964 switch(Inst.getOpcode()) {
6965 default: llvm_unreachable("unexpected opcode!");
6966 case ARM::ASRi: ShiftTy = ARM_AM::asr; break;
6967 case ARM::LSRi: ShiftTy = ARM_AM::lsr; break;
6968 case ARM::LSLi: ShiftTy = ARM_AM::lsl; break;
6969 case ARM::RORi: ShiftTy = ARM_AM::ror; break;
6971 // A shift by zero is a plain MOVr, not a MOVsi.
6972 unsigned Amt = Inst.getOperand(2).getImm();
6973 unsigned Opc = Amt == 0 ? ARM::MOVr : ARM::MOVsi;
6974 // A shift by 32 should be encoded as 0 when permitted
6975 if (Amt == 32 && (ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr))
6977 unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, Amt);
6979 TmpInst.setOpcode(Opc);
6980 TmpInst.addOperand(Inst.getOperand(0)); // Rd
6981 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6982 if (Opc == ARM::MOVsi)
6983 TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty
6984 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6985 TmpInst.addOperand(Inst.getOperand(4));
6986 TmpInst.addOperand(Inst.getOperand(5)); // cc_out
6991 unsigned Shifter = ARM_AM::getSORegOpc(ARM_AM::rrx, 0);
6993 TmpInst.setOpcode(ARM::MOVsi);
6994 TmpInst.addOperand(Inst.getOperand(0)); // Rd
6995 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6996 TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty
6997 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
6998 TmpInst.addOperand(Inst.getOperand(3));
6999 TmpInst.addOperand(Inst.getOperand(4)); // cc_out
7003 case ARM::t2LDMIA_UPD: {
7004 // If this is a load of a single register, then we should use
7005 // a post-indexed LDR instruction instead, per the ARM ARM.
7006 if (Inst.getNumOperands() != 5)
7009 TmpInst.setOpcode(ARM::t2LDR_POST);
7010 TmpInst.addOperand(Inst.getOperand(4)); // Rt
7011 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
7012 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7013 TmpInst.addOperand(MCOperand::CreateImm(4));
7014 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
7015 TmpInst.addOperand(Inst.getOperand(3));
7019 case ARM::t2STMDB_UPD: {
7020 // If this is a store of a single register, then we should use
7021 // a pre-indexed STR instruction instead, per the ARM ARM.
7022 if (Inst.getNumOperands() != 5)
7025 TmpInst.setOpcode(ARM::t2STR_PRE);
7026 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
7027 TmpInst.addOperand(Inst.getOperand(4)); // Rt
7028 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7029 TmpInst.addOperand(MCOperand::CreateImm(-4));
7030 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
7031 TmpInst.addOperand(Inst.getOperand(3));
7035 case ARM::LDMIA_UPD:
7036 // If this is a load of a single register via a 'pop', then we should use
7037 // a post-indexed LDR instruction instead, per the ARM ARM.
7038 if (static_cast<ARMOperand*>(Operands[0])->getToken() == "pop" &&
7039 Inst.getNumOperands() == 5) {
7041 TmpInst.setOpcode(ARM::LDR_POST_IMM);
7042 TmpInst.addOperand(Inst.getOperand(4)); // Rt
7043 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
7044 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7045 TmpInst.addOperand(MCOperand::CreateReg(0)); // am2offset
7046 TmpInst.addOperand(MCOperand::CreateImm(4));
7047 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
7048 TmpInst.addOperand(Inst.getOperand(3));
7053 case ARM::STMDB_UPD:
7054 // If this is a store of a single register via a 'push', then we should use
7055 // a pre-indexed STR instruction instead, per the ARM ARM.
7056 if (static_cast<ARMOperand*>(Operands[0])->getToken() == "push" &&
7057 Inst.getNumOperands() == 5) {
7059 TmpInst.setOpcode(ARM::STR_PRE_IMM);
7060 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
7061 TmpInst.addOperand(Inst.getOperand(4)); // Rt
7062 TmpInst.addOperand(Inst.getOperand(1)); // addrmode_imm12
7063 TmpInst.addOperand(MCOperand::CreateImm(-4));
7064 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
7065 TmpInst.addOperand(Inst.getOperand(3));
7069 case ARM::t2ADDri12:
7070 // If the immediate fits for encoding T3 (t2ADDri) and the generic "add"
7071 // mnemonic was used (not "addw"), encoding T3 is preferred.
7072 if (static_cast<ARMOperand*>(Operands[0])->getToken() != "add" ||
7073 ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1)
7075 Inst.setOpcode(ARM::t2ADDri);
7076 Inst.addOperand(MCOperand::CreateReg(0)); // cc_out
7078 case ARM::t2SUBri12:
7079 // If the immediate fits for encoding T3 (t2SUBri) and the generic "sub"
7080 // mnemonic was used (not "subw"), encoding T3 is preferred.
7081 if (static_cast<ARMOperand*>(Operands[0])->getToken() != "sub" ||
7082 ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1)
7084 Inst.setOpcode(ARM::t2SUBri);
7085 Inst.addOperand(MCOperand::CreateReg(0)); // cc_out
7088 // If the immediate is in the range 0-7, we want tADDi3 iff Rd was
7089 // explicitly specified. From the ARM ARM: "Encoding T1 is preferred
7090 // to encoding T2 if <Rd> is specified and encoding T2 is preferred
7091 // to encoding T1 if <Rd> is omitted."
7092 if ((unsigned)Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) {
7093 Inst.setOpcode(ARM::tADDi3);
7098 // If the immediate is in the range 0-7, we want tADDi3 iff Rd was
7099 // explicitly specified. From the ARM ARM: "Encoding T1 is preferred
7100 // to encoding T2 if <Rd> is specified and encoding T2 is preferred
7101 // to encoding T1 if <Rd> is omitted."
7102 if ((unsigned)Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) {
7103 Inst.setOpcode(ARM::tSUBi3);
7108 case ARM::t2SUBri: {
7109 // If the destination and first source operand are the same, and
7110 // the flags are compatible with the current IT status, use encoding T2
7111 // instead of T3. For compatibility with the system 'as'. Make sure the
7112 // wide encoding wasn't explicit.
7113 if (Inst.getOperand(0).getReg() != Inst.getOperand(1).getReg() ||
7114 !isARMLowRegister(Inst.getOperand(0).getReg()) ||
7115 (unsigned)Inst.getOperand(2).getImm() > 255 ||
7116 ((!inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR) ||
7117 (inITBlock() && Inst.getOperand(5).getReg() != 0)) ||
7118 (static_cast<ARMOperand*>(Operands[3])->isToken() &&
7119 static_cast<ARMOperand*>(Operands[3])->getToken() == ".w"))
7122 TmpInst.setOpcode(Inst.getOpcode() == ARM::t2ADDri ?
7123 ARM::tADDi8 : ARM::tSUBi8);
7124 TmpInst.addOperand(Inst.getOperand(0));
7125 TmpInst.addOperand(Inst.getOperand(5));
7126 TmpInst.addOperand(Inst.getOperand(0));
7127 TmpInst.addOperand(Inst.getOperand(2));
7128 TmpInst.addOperand(Inst.getOperand(3));
7129 TmpInst.addOperand(Inst.getOperand(4));
7133 case ARM::t2ADDrr: {
7134 // If the destination and first source operand are the same, and
7135 // there's no setting of the flags, use encoding T2 instead of T3.
7136 // Note that this is only for ADD, not SUB. This mirrors the system
7137 // 'as' behaviour. Make sure the wide encoding wasn't explicit.
7138 if (Inst.getOperand(0).getReg() != Inst.getOperand(1).getReg() ||
7139 Inst.getOperand(5).getReg() != 0 ||
7140 (static_cast<ARMOperand*>(Operands[3])->isToken() &&
7141 static_cast<ARMOperand*>(Operands[3])->getToken() == ".w"))
7144 TmpInst.setOpcode(ARM::tADDhirr);
7145 TmpInst.addOperand(Inst.getOperand(0));
7146 TmpInst.addOperand(Inst.getOperand(0));
7147 TmpInst.addOperand(Inst.getOperand(2));
7148 TmpInst.addOperand(Inst.getOperand(3));
7149 TmpInst.addOperand(Inst.getOperand(4));
7153 case ARM::tADDrSP: {
7154 // If the non-SP source operand and the destination operand are not the
7155 // same, we need to use the 32-bit encoding if it's available.
7156 if (Inst.getOperand(0).getReg() != Inst.getOperand(2).getReg()) {
7157 Inst.setOpcode(ARM::t2ADDrr);
7158 Inst.addOperand(MCOperand::CreateReg(0)); // cc_out
7164 // A Thumb conditional branch outside of an IT block is a tBcc.
7165 if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()) {
7166 Inst.setOpcode(ARM::tBcc);
7171 // A Thumb2 conditional branch outside of an IT block is a t2Bcc.
7172 if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()){
7173 Inst.setOpcode(ARM::t2Bcc);
7178 // If the conditional is AL or we're in an IT block, we really want t2B.
7179 if (Inst.getOperand(1).getImm() == ARMCC::AL || inITBlock()) {
7180 Inst.setOpcode(ARM::t2B);
7185 // If the conditional is AL, we really want tB.
7186 if (Inst.getOperand(1).getImm() == ARMCC::AL) {
7187 Inst.setOpcode(ARM::tB);
7192 // If the register list contains any high registers, or if the writeback
7193 // doesn't match what tLDMIA can do, we need to use the 32-bit encoding
7194 // instead if we're in Thumb2. Otherwise, this should have generated
7195 // an error in validateInstruction().
7196 unsigned Rn = Inst.getOperand(0).getReg();
7197 bool hasWritebackToken =
7198 (static_cast<ARMOperand*>(Operands[3])->isToken() &&
7199 static_cast<ARMOperand*>(Operands[3])->getToken() == "!");
7200 bool listContainsBase;
7201 if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase) ||
7202 (!listContainsBase && !hasWritebackToken) ||
7203 (listContainsBase && hasWritebackToken)) {
7204 // 16-bit encoding isn't sufficient. Switch to the 32-bit version.
7205 assert (isThumbTwo());
7206 Inst.setOpcode(hasWritebackToken ? ARM::t2LDMIA_UPD : ARM::t2LDMIA);
7207 // If we're switching to the updating version, we need to insert
7208 // the writeback tied operand.
7209 if (hasWritebackToken)
7210 Inst.insert(Inst.begin(),
7211 MCOperand::CreateReg(Inst.getOperand(0).getReg()));
7216 case ARM::tSTMIA_UPD: {
7217 // If the register list contains any high registers, we need to use
7218 // the 32-bit encoding instead if we're in Thumb2. Otherwise, this
7219 // should have generated an error in validateInstruction().
7220 unsigned Rn = Inst.getOperand(0).getReg();
7221 bool listContainsBase;
7222 if (checkLowRegisterList(Inst, 4, Rn, 0, listContainsBase)) {
7223 // 16-bit encoding isn't sufficient. Switch to the 32-bit version.
7224 assert (isThumbTwo());
7225 Inst.setOpcode(ARM::t2STMIA_UPD);
7231 bool listContainsBase;
7232 // If the register list contains any high registers, we need to use
7233 // the 32-bit encoding instead if we're in Thumb2. Otherwise, this
7234 // should have generated an error in validateInstruction().
7235 if (!checkLowRegisterList(Inst, 2, 0, ARM::PC, listContainsBase))
7237 assert (isThumbTwo());
7238 Inst.setOpcode(ARM::t2LDMIA_UPD);
7239 // Add the base register and writeback operands.
7240 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
7241 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
7245 bool listContainsBase;
7246 if (!checkLowRegisterList(Inst, 2, 0, ARM::LR, listContainsBase))
7248 assert (isThumbTwo());
7249 Inst.setOpcode(ARM::t2STMDB_UPD);
7250 // Add the base register and writeback operands.
7251 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
7252 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
7256 // If we can use the 16-bit encoding and the user didn't explicitly
7257 // request the 32-bit variant, transform it here.
7258 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7259 (unsigned)Inst.getOperand(1).getImm() <= 255 &&
7260 ((!inITBlock() && Inst.getOperand(2).getImm() == ARMCC::AL &&
7261 Inst.getOperand(4).getReg() == ARM::CPSR) ||
7262 (inITBlock() && Inst.getOperand(4).getReg() == 0)) &&
7263 (!static_cast<ARMOperand*>(Operands[2])->isToken() ||
7264 static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) {
7265 // The operands aren't in the same order for tMOVi8...
7267 TmpInst.setOpcode(ARM::tMOVi8);
7268 TmpInst.addOperand(Inst.getOperand(0));
7269 TmpInst.addOperand(Inst.getOperand(4));
7270 TmpInst.addOperand(Inst.getOperand(1));
7271 TmpInst.addOperand(Inst.getOperand(2));
7272 TmpInst.addOperand(Inst.getOperand(3));
7279 // If we can use the 16-bit encoding and the user didn't explicitly
7280 // request the 32-bit variant, transform it here.
7281 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7282 isARMLowRegister(Inst.getOperand(1).getReg()) &&
7283 Inst.getOperand(2).getImm() == ARMCC::AL &&
7284 Inst.getOperand(4).getReg() == ARM::CPSR &&
7285 (!static_cast<ARMOperand*>(Operands[2])->isToken() ||
7286 static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) {
7287 // The operands aren't the same for tMOV[S]r... (no cc_out)
7289 TmpInst.setOpcode(Inst.getOperand(4).getReg() ? ARM::tMOVSr : ARM::tMOVr);
7290 TmpInst.addOperand(Inst.getOperand(0));
7291 TmpInst.addOperand(Inst.getOperand(1));
7292 TmpInst.addOperand(Inst.getOperand(2));
7293 TmpInst.addOperand(Inst.getOperand(3));
7303 // If we can use the 16-bit encoding and the user didn't explicitly
7304 // request the 32-bit variant, transform it here.
7305 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7306 isARMLowRegister(Inst.getOperand(1).getReg()) &&
7307 Inst.getOperand(2).getImm() == 0 &&
7308 (!static_cast<ARMOperand*>(Operands[2])->isToken() ||
7309 static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) {
7311 switch (Inst.getOpcode()) {
7312 default: llvm_unreachable("Illegal opcode!");
7313 case ARM::t2SXTH: NewOpc = ARM::tSXTH; break;
7314 case ARM::t2SXTB: NewOpc = ARM::tSXTB; break;
7315 case ARM::t2UXTH: NewOpc = ARM::tUXTH; break;
7316 case ARM::t2UXTB: NewOpc = ARM::tUXTB; break;
7318 // The operands aren't the same for thumb1 (no rotate operand).
7320 TmpInst.setOpcode(NewOpc);
7321 TmpInst.addOperand(Inst.getOperand(0));
7322 TmpInst.addOperand(Inst.getOperand(1));
7323 TmpInst.addOperand(Inst.getOperand(3));
7324 TmpInst.addOperand(Inst.getOperand(4));
7331 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(2).getImm());
7332 // rrx shifts and asr/lsr of #32 is encoded as 0
7333 if (SOpc == ARM_AM::rrx || SOpc == ARM_AM::asr || SOpc == ARM_AM::lsr)
7335 if (ARM_AM::getSORegOffset(Inst.getOperand(2).getImm()) == 0) {
7336 // Shifting by zero is accepted as a vanilla 'MOVr'
7338 TmpInst.setOpcode(ARM::MOVr);
7339 TmpInst.addOperand(Inst.getOperand(0));
7340 TmpInst.addOperand(Inst.getOperand(1));
7341 TmpInst.addOperand(Inst.getOperand(3));
7342 TmpInst.addOperand(Inst.getOperand(4));
7343 TmpInst.addOperand(Inst.getOperand(5));
7356 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(3).getImm());
7357 if (SOpc == ARM_AM::rrx) return false;
7358 switch (Inst.getOpcode()) {
7359 default: llvm_unreachable("unexpected opcode!");
7360 case ARM::ANDrsi: newOpc = ARM::ANDrr; break;
7361 case ARM::ORRrsi: newOpc = ARM::ORRrr; break;
7362 case ARM::EORrsi: newOpc = ARM::EORrr; break;
7363 case ARM::BICrsi: newOpc = ARM::BICrr; break;
7364 case ARM::SUBrsi: newOpc = ARM::SUBrr; break;
7365 case ARM::ADDrsi: newOpc = ARM::ADDrr; break;
7367 // If the shift is by zero, use the non-shifted instruction definition.
7368 // The exception is for right shifts, where 0 == 32
7369 if (ARM_AM::getSORegOffset(Inst.getOperand(3).getImm()) == 0 &&
7370 !(SOpc == ARM_AM::lsr || SOpc == ARM_AM::asr)) {
7372 TmpInst.setOpcode(newOpc);
7373 TmpInst.addOperand(Inst.getOperand(0));
7374 TmpInst.addOperand(Inst.getOperand(1));
7375 TmpInst.addOperand(Inst.getOperand(2));
7376 TmpInst.addOperand(Inst.getOperand(4));
7377 TmpInst.addOperand(Inst.getOperand(5));
7378 TmpInst.addOperand(Inst.getOperand(6));
7386 // The mask bits for all but the first condition are represented as
7387 // the low bit of the condition code value implies 't'. We currently
7388 // always have 1 implies 't', so XOR toggle the bits if the low bit
7389 // of the condition code is zero.
7390 MCOperand &MO = Inst.getOperand(1);
7391 unsigned Mask = MO.getImm();
7392 unsigned OrigMask = Mask;
7393 unsigned TZ = CountTrailingZeros_32(Mask);
7394 if ((Inst.getOperand(0).getImm() & 1) == 0) {
7395 assert(Mask && TZ <= 3 && "illegal IT mask value!");
7396 for (unsigned i = 3; i != TZ; --i)
7401 // Set up the IT block state according to the IT instruction we just
7403 assert(!inITBlock() && "nested IT blocks?!");
7404 ITState.Cond = ARMCC::CondCodes(Inst.getOperand(0).getImm());
7405 ITState.Mask = OrigMask; // Use the original mask, not the updated one.
7406 ITState.CurPosition = 0;
7407 ITState.FirstCond = true;
7417 // Assemblers should use the narrow encodings of these instructions when permissible.
7418 if ((isARMLowRegister(Inst.getOperand(1).getReg()) &&
7419 isARMLowRegister(Inst.getOperand(2).getReg())) &&
7420 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
7421 ((!inITBlock() && Inst.getOperand(5).getReg() == ARM::CPSR) ||
7422 (inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR)) &&
7423 (!static_cast<ARMOperand*>(Operands[3])->isToken() ||
7424 !static_cast<ARMOperand*>(Operands[3])->getToken().equals_lower(".w"))) {
7426 switch (Inst.getOpcode()) {
7427 default: llvm_unreachable("unexpected opcode");
7428 case ARM::t2LSLrr: NewOpc = ARM::tLSLrr; break;
7429 case ARM::t2LSRrr: NewOpc = ARM::tLSRrr; break;
7430 case ARM::t2ASRrr: NewOpc = ARM::tASRrr; break;
7431 case ARM::t2SBCrr: NewOpc = ARM::tSBC; break;
7432 case ARM::t2RORrr: NewOpc = ARM::tROR; break;
7433 case ARM::t2BICrr: NewOpc = ARM::tBIC; break;
7436 TmpInst.setOpcode(NewOpc);
7437 TmpInst.addOperand(Inst.getOperand(0));
7438 TmpInst.addOperand(Inst.getOperand(5));
7439 TmpInst.addOperand(Inst.getOperand(1));
7440 TmpInst.addOperand(Inst.getOperand(2));
7441 TmpInst.addOperand(Inst.getOperand(3));
7442 TmpInst.addOperand(Inst.getOperand(4));
7453 // Assemblers should use the narrow encodings of these instructions when permissible.
7454 // These instructions are special in that they are commutable, so shorter encodings
7455 // are available more often.
7456 if ((isARMLowRegister(Inst.getOperand(1).getReg()) &&
7457 isARMLowRegister(Inst.getOperand(2).getReg())) &&
7458 (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() ||
7459 Inst.getOperand(0).getReg() == Inst.getOperand(2).getReg()) &&
7460 ((!inITBlock() && Inst.getOperand(5).getReg() == ARM::CPSR) ||
7461 (inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR)) &&
7462 (!static_cast<ARMOperand*>(Operands[3])->isToken() ||
7463 !static_cast<ARMOperand*>(Operands[3])->getToken().equals_lower(".w"))) {
7465 switch (Inst.getOpcode()) {
7466 default: llvm_unreachable("unexpected opcode");
7467 case ARM::t2ADCrr: NewOpc = ARM::tADC; break;
7468 case ARM::t2ANDrr: NewOpc = ARM::tAND; break;
7469 case ARM::t2EORrr: NewOpc = ARM::tEOR; break;
7470 case ARM::t2ORRrr: NewOpc = ARM::tORR; break;
7473 TmpInst.setOpcode(NewOpc);
7474 TmpInst.addOperand(Inst.getOperand(0));
7475 TmpInst.addOperand(Inst.getOperand(5));
7476 if (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()) {
7477 TmpInst.addOperand(Inst.getOperand(1));
7478 TmpInst.addOperand(Inst.getOperand(2));
7480 TmpInst.addOperand(Inst.getOperand(2));
7481 TmpInst.addOperand(Inst.getOperand(1));
7483 TmpInst.addOperand(Inst.getOperand(3));
7484 TmpInst.addOperand(Inst.getOperand(4));
7494 unsigned ARMAsmParser::checkTargetMatchPredicate(MCInst &Inst) {
7495 // 16-bit thumb arithmetic instructions either require or preclude the 'S'
7496 // suffix depending on whether they're in an IT block or not.
7497 unsigned Opc = Inst.getOpcode();
7498 const MCInstrDesc &MCID = getInstDesc(Opc);
7499 if (MCID.TSFlags & ARMII::ThumbArithFlagSetting) {
7500 assert(MCID.hasOptionalDef() &&
7501 "optionally flag setting instruction missing optional def operand");
7502 assert(MCID.NumOperands == Inst.getNumOperands() &&
7503 "operand count mismatch!");
7504 // Find the optional-def operand (cc_out).
7507 !MCID.OpInfo[OpNo].isOptionalDef() && OpNo < MCID.NumOperands;
7510 // If we're parsing Thumb1, reject it completely.
7511 if (isThumbOne() && Inst.getOperand(OpNo).getReg() != ARM::CPSR)
7512 return Match_MnemonicFail;
7513 // If we're parsing Thumb2, which form is legal depends on whether we're
7515 if (isThumbTwo() && Inst.getOperand(OpNo).getReg() != ARM::CPSR &&
7517 return Match_RequiresITBlock;
7518 if (isThumbTwo() && Inst.getOperand(OpNo).getReg() == ARM::CPSR &&
7520 return Match_RequiresNotITBlock;
7522 // Some high-register supporting Thumb1 encodings only allow both registers
7523 // to be from r0-r7 when in Thumb2.
7524 else if (Opc == ARM::tADDhirr && isThumbOne() &&
7525 isARMLowRegister(Inst.getOperand(1).getReg()) &&
7526 isARMLowRegister(Inst.getOperand(2).getReg()))
7527 return Match_RequiresThumb2;
7528 // Others only require ARMv6 or later.
7529 else if (Opc == ARM::tMOVr && isThumbOne() && !hasV6Ops() &&
7530 isARMLowRegister(Inst.getOperand(0).getReg()) &&
7531 isARMLowRegister(Inst.getOperand(1).getReg()))
7532 return Match_RequiresV6;
7533 return Match_Success;
7536 static const char *getSubtargetFeatureName(unsigned Val);
7538 MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
7539 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
7540 MCStreamer &Out, unsigned &ErrorInfo,
7541 bool MatchingInlineAsm) {
7543 unsigned MatchResult;
7545 MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo,
7547 switch (MatchResult) {
7550 // Context sensitive operand constraints aren't handled by the matcher,
7551 // so check them here.
7552 if (validateInstruction(Inst, Operands)) {
7553 // Still progress the IT block, otherwise one wrong condition causes
7554 // nasty cascading errors.
7555 forwardITPosition();
7559 // Some instructions need post-processing to, for example, tweak which
7560 // encoding is selected. Loop on it while changes happen so the
7561 // individual transformations can chain off each other. E.g.,
7562 // tPOP(r8)->t2LDMIA_UPD(sp,r8)->t2STR_POST(sp,r8)
7563 while (processInstruction(Inst, Operands))
7566 // Only move forward at the very end so that everything in validate
7567 // and process gets a consistent answer about whether we're in an IT
7569 forwardITPosition();
7571 // ITasm is an ARM mode pseudo-instruction that just sets the ITblock and
7572 // doesn't actually encode.
7573 if (Inst.getOpcode() == ARM::ITasm)
7577 Out.EmitInstruction(Inst);
7579 case Match_MissingFeature: {
7580 assert(ErrorInfo && "Unknown missing feature!");
7581 // Special case the error message for the very common case where only
7582 // a single subtarget feature is missing (Thumb vs. ARM, e.g.).
7583 std::string Msg = "instruction requires:";
7585 for (unsigned i = 0; i < (sizeof(ErrorInfo)*8-1); ++i) {
7586 if (ErrorInfo & Mask) {
7588 Msg += getSubtargetFeatureName(ErrorInfo & Mask);
7592 return Error(IDLoc, Msg);
7594 case Match_InvalidOperand: {
7595 SMLoc ErrorLoc = IDLoc;
7596 if (ErrorInfo != ~0U) {
7597 if (ErrorInfo >= Operands.size())
7598 return Error(IDLoc, "too few operands for instruction");
7600 ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc();
7601 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
7604 return Error(ErrorLoc, "invalid operand for instruction");
7606 case Match_MnemonicFail:
7607 return Error(IDLoc, "invalid instruction",
7608 ((ARMOperand*)Operands[0])->getLocRange());
7609 case Match_RequiresNotITBlock:
7610 return Error(IDLoc, "flag setting instruction only valid outside IT block");
7611 case Match_RequiresITBlock:
7612 return Error(IDLoc, "instruction only valid inside IT block");
7613 case Match_RequiresV6:
7614 return Error(IDLoc, "instruction variant requires ARMv6 or later");
7615 case Match_RequiresThumb2:
7616 return Error(IDLoc, "instruction variant requires Thumb2");
7617 case Match_ImmRange0_15: {
7618 SMLoc ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc();
7619 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
7620 return Error(ErrorLoc, "immediate operand must be in the range [0,15]");
7624 llvm_unreachable("Implement any new match types added!");
7627 /// parseDirective parses the arm specific directives
7628 bool ARMAsmParser::ParseDirective(AsmToken DirectiveID) {
7629 StringRef IDVal = DirectiveID.getIdentifier();
7630 if (IDVal == ".word")
7631 return parseDirectiveWord(4, DirectiveID.getLoc());
7632 else if (IDVal == ".thumb")
7633 return parseDirectiveThumb(DirectiveID.getLoc());
7634 else if (IDVal == ".arm")
7635 return parseDirectiveARM(DirectiveID.getLoc());
7636 else if (IDVal == ".thumb_func")
7637 return parseDirectiveThumbFunc(DirectiveID.getLoc());
7638 else if (IDVal == ".code")
7639 return parseDirectiveCode(DirectiveID.getLoc());
7640 else if (IDVal == ".syntax")
7641 return parseDirectiveSyntax(DirectiveID.getLoc());
7642 else if (IDVal == ".unreq")
7643 return parseDirectiveUnreq(DirectiveID.getLoc());
7644 else if (IDVal == ".arch")
7645 return parseDirectiveArch(DirectiveID.getLoc());
7646 else if (IDVal == ".eabi_attribute")
7647 return parseDirectiveEabiAttr(DirectiveID.getLoc());
7651 /// parseDirectiveWord
7652 /// ::= .word [ expression (, expression)* ]
7653 bool ARMAsmParser::parseDirectiveWord(unsigned Size, SMLoc L) {
7654 if (getLexer().isNot(AsmToken::EndOfStatement)) {
7656 const MCExpr *Value;
7657 if (getParser().parseExpression(Value))
7660 getParser().getStreamer().EmitValue(Value, Size);
7662 if (getLexer().is(AsmToken::EndOfStatement))
7665 // FIXME: Improve diagnostic.
7666 if (getLexer().isNot(AsmToken::Comma))
7667 return Error(L, "unexpected token in directive");
7676 /// parseDirectiveThumb
7678 bool ARMAsmParser::parseDirectiveThumb(SMLoc L) {
7679 if (getLexer().isNot(AsmToken::EndOfStatement))
7680 return Error(L, "unexpected token in directive");
7685 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
7689 /// parseDirectiveARM
7691 bool ARMAsmParser::parseDirectiveARM(SMLoc L) {
7692 if (getLexer().isNot(AsmToken::EndOfStatement))
7693 return Error(L, "unexpected token in directive");
7698 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
7702 /// parseDirectiveThumbFunc
7703 /// ::= .thumbfunc symbol_name
7704 bool ARMAsmParser::parseDirectiveThumbFunc(SMLoc L) {
7705 const MCAsmInfo &MAI = getParser().getStreamer().getContext().getAsmInfo();
7706 bool isMachO = MAI.hasSubsectionsViaSymbols();
7708 bool needFuncName = true;
7710 // Darwin asm has (optionally) function name after .thumb_func direction
7713 const AsmToken &Tok = Parser.getTok();
7714 if (Tok.isNot(AsmToken::EndOfStatement)) {
7715 if (Tok.isNot(AsmToken::Identifier) && Tok.isNot(AsmToken::String))
7716 return Error(L, "unexpected token in .thumb_func directive");
7717 Name = Tok.getIdentifier();
7718 Parser.Lex(); // Consume the identifier token.
7719 needFuncName = false;
7723 if (getLexer().isNot(AsmToken::EndOfStatement))
7724 return Error(L, "unexpected token in directive");
7726 // Eat the end of statement and any blank lines that follow.
7727 while (getLexer().is(AsmToken::EndOfStatement))
7730 // FIXME: assuming function name will be the line following .thumb_func
7731 // We really should be checking the next symbol definition even if there's
7732 // stuff in between.
7734 Name = Parser.getTok().getIdentifier();
7737 // Mark symbol as a thumb symbol.
7738 MCSymbol *Func = getParser().getContext().GetOrCreateSymbol(Name);
7739 getParser().getStreamer().EmitThumbFunc(Func);
7743 /// parseDirectiveSyntax
7744 /// ::= .syntax unified | divided
7745 bool ARMAsmParser::parseDirectiveSyntax(SMLoc L) {
7746 const AsmToken &Tok = Parser.getTok();
7747 if (Tok.isNot(AsmToken::Identifier))
7748 return Error(L, "unexpected token in .syntax directive");
7749 StringRef Mode = Tok.getString();
7750 if (Mode == "unified" || Mode == "UNIFIED")
7752 else if (Mode == "divided" || Mode == "DIVIDED")
7753 return Error(L, "'.syntax divided' arm asssembly not supported");
7755 return Error(L, "unrecognized syntax mode in .syntax directive");
7757 if (getLexer().isNot(AsmToken::EndOfStatement))
7758 return Error(Parser.getTok().getLoc(), "unexpected token in directive");
7761 // TODO tell the MC streamer the mode
7762 // getParser().getStreamer().Emit???();
7766 /// parseDirectiveCode
7767 /// ::= .code 16 | 32
7768 bool ARMAsmParser::parseDirectiveCode(SMLoc L) {
7769 const AsmToken &Tok = Parser.getTok();
7770 if (Tok.isNot(AsmToken::Integer))
7771 return Error(L, "unexpected token in .code directive");
7772 int64_t Val = Parser.getTok().getIntVal();
7778 return Error(L, "invalid operand to .code directive");
7780 if (getLexer().isNot(AsmToken::EndOfStatement))
7781 return Error(Parser.getTok().getLoc(), "unexpected token in directive");
7787 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
7791 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
7797 /// parseDirectiveReq
7798 /// ::= name .req registername
7799 bool ARMAsmParser::parseDirectiveReq(StringRef Name, SMLoc L) {
7800 Parser.Lex(); // Eat the '.req' token.
7802 SMLoc SRegLoc, ERegLoc;
7803 if (ParseRegister(Reg, SRegLoc, ERegLoc)) {
7804 Parser.eatToEndOfStatement();
7805 return Error(SRegLoc, "register name expected");
7808 // Shouldn't be anything else.
7809 if (Parser.getTok().isNot(AsmToken::EndOfStatement)) {
7810 Parser.eatToEndOfStatement();
7811 return Error(Parser.getTok().getLoc(),
7812 "unexpected input in .req directive.");
7815 Parser.Lex(); // Consume the EndOfStatement
7817 if (RegisterReqs.GetOrCreateValue(Name, Reg).getValue() != Reg)
7818 return Error(SRegLoc, "redefinition of '" + Name +
7819 "' does not match original.");
7824 /// parseDirectiveUneq
7825 /// ::= .unreq registername
7826 bool ARMAsmParser::parseDirectiveUnreq(SMLoc L) {
7827 if (Parser.getTok().isNot(AsmToken::Identifier)) {
7828 Parser.eatToEndOfStatement();
7829 return Error(L, "unexpected input in .unreq directive.");
7831 RegisterReqs.erase(Parser.getTok().getIdentifier());
7832 Parser.Lex(); // Eat the identifier.
7836 /// parseDirectiveArch
7838 bool ARMAsmParser::parseDirectiveArch(SMLoc L) {
7842 /// parseDirectiveEabiAttr
7843 /// ::= .eabi_attribute int, int
7844 bool ARMAsmParser::parseDirectiveEabiAttr(SMLoc L) {
7848 /// Force static initialization.
7849 extern "C" void LLVMInitializeARMAsmParser() {
7850 RegisterMCAsmParser<ARMAsmParser> X(TheARMTarget);
7851 RegisterMCAsmParser<ARMAsmParser> Y(TheThumbTarget);
7854 #define GET_REGISTER_MATCHER
7855 #define GET_SUBTARGET_FEATURE_NAME
7856 #define GET_MATCHER_IMPLEMENTATION
7857 #include "ARMGenAsmMatcher.inc"
7859 // Define this matcher function after the auto-generated include so we
7860 // have the match class enum definitions.
7861 unsigned ARMAsmParser::validateTargetOperandClass(MCParsedAsmOperand *AsmOp,
7863 ARMOperand *Op = static_cast<ARMOperand*>(AsmOp);
7864 // If the kind is a token for a literal immediate, check if our asm
7865 // operand matches. This is for InstAliases which have a fixed-value
7866 // immediate in the syntax.
7867 if (Kind == MCK__35_0 && Op->isImm()) {
7868 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op->getImm());
7870 return Match_InvalidOperand;
7871 if (CE->getValue() == 0)
7872 return Match_Success;
7874 return Match_InvalidOperand;