1 //===-- ARMAsmParser.cpp - Parse ARM assembly to MCInst instructions ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "MCTargetDesc/ARMBaseInfo.h"
11 #include "MCTargetDesc/ARMAddressingModes.h"
12 #include "MCTargetDesc/ARMMCExpr.h"
13 #include "llvm/MC/MCParser/MCAsmLexer.h"
14 #include "llvm/MC/MCParser/MCAsmParser.h"
15 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
16 #include "llvm/MC/MCAsmInfo.h"
17 #include "llvm/MC/MCContext.h"
18 #include "llvm/MC/MCStreamer.h"
19 #include "llvm/MC/MCExpr.h"
20 #include "llvm/MC/MCInst.h"
21 #include "llvm/MC/MCInstrDesc.h"
22 #include "llvm/MC/MCRegisterInfo.h"
23 #include "llvm/MC/MCSubtargetInfo.h"
24 #include "llvm/MC/MCTargetAsmParser.h"
25 #include "llvm/Support/MathExtras.h"
26 #include "llvm/Support/SourceMgr.h"
27 #include "llvm/Support/TargetRegistry.h"
28 #include "llvm/Support/raw_ostream.h"
29 #include "llvm/ADT/BitVector.h"
30 #include "llvm/ADT/OwningPtr.h"
31 #include "llvm/ADT/STLExtras.h"
32 #include "llvm/ADT/SmallVector.h"
33 #include "llvm/ADT/StringExtras.h"
34 #include "llvm/ADT/StringSwitch.h"
35 #include "llvm/ADT/Twine.h"
43 class ARMAsmParser : public MCTargetAsmParser {
48 ARMCC::CondCodes Cond; // Condition for IT block.
49 unsigned Mask:4; // Condition mask for instructions.
50 // Starting at first 1 (from lsb).
51 // '1' condition as indicated in IT.
52 // '0' inverse of condition (else).
53 // Count of instructions in IT block is
54 // 4 - trailingzeroes(mask)
56 bool FirstCond; // Explicit flag for when we're parsing the
57 // First instruction in the IT block. It's
58 // implied in the mask, so needs special
61 unsigned CurPosition; // Current position in parsing of IT
62 // block. In range [0,3]. Initialized
63 // according to count of instructions in block.
64 // ~0U if no active IT block.
66 bool inITBlock() { return ITState.CurPosition != ~0U;}
67 void forwardITPosition() {
68 if (!inITBlock()) return;
69 // Move to the next instruction in the IT block, if there is one. If not,
70 // mark the block as done.
71 unsigned TZ = CountTrailingZeros_32(ITState.Mask);
72 if (++ITState.CurPosition == 5 - TZ)
73 ITState.CurPosition = ~0U; // Done with the IT block after this.
77 MCAsmParser &getParser() const { return Parser; }
78 MCAsmLexer &getLexer() const { return Parser.getLexer(); }
80 void Warning(SMLoc L, const Twine &Msg) { Parser.Warning(L, Msg); }
81 bool Error(SMLoc L, const Twine &Msg) { return Parser.Error(L, Msg); }
83 int tryParseRegister();
84 bool tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &);
85 int tryParseShiftRegister(SmallVectorImpl<MCParsedAsmOperand*> &);
86 bool parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &);
87 bool parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &);
88 bool parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &, StringRef Mnemonic);
89 bool parsePrefix(ARMMCExpr::VariantKind &RefKind);
90 bool parseMemRegOffsetShift(ARM_AM::ShiftOpc &ShiftType,
91 unsigned &ShiftAmount);
92 bool parseDirectiveWord(unsigned Size, SMLoc L);
93 bool parseDirectiveThumb(SMLoc L);
94 bool parseDirectiveThumbFunc(SMLoc L);
95 bool parseDirectiveCode(SMLoc L);
96 bool parseDirectiveSyntax(SMLoc L);
98 StringRef splitMnemonic(StringRef Mnemonic, unsigned &PredicationCode,
99 bool &CarrySetting, unsigned &ProcessorIMod,
101 void getMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet,
102 bool &CanAcceptPredicationCode);
104 bool isThumb() const {
105 // FIXME: Can tablegen auto-generate this?
106 return (STI.getFeatureBits() & ARM::ModeThumb) != 0;
108 bool isThumbOne() const {
109 return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2) == 0;
111 bool isThumbTwo() const {
112 return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2);
114 bool hasV6Ops() const {
115 return STI.getFeatureBits() & ARM::HasV6Ops;
117 bool hasV7Ops() const {
118 return STI.getFeatureBits() & ARM::HasV7Ops;
121 unsigned FB = ComputeAvailableFeatures(STI.ToggleFeature(ARM::ModeThumb));
122 setAvailableFeatures(FB);
124 bool isMClass() const {
125 return STI.getFeatureBits() & ARM::FeatureMClass;
128 /// @name Auto-generated Match Functions
131 #define GET_ASSEMBLER_HEADER
132 #include "ARMGenAsmMatcher.inc"
136 OperandMatchResultTy parseITCondCode(SmallVectorImpl<MCParsedAsmOperand*>&);
137 OperandMatchResultTy parseCoprocNumOperand(
138 SmallVectorImpl<MCParsedAsmOperand*>&);
139 OperandMatchResultTy parseCoprocRegOperand(
140 SmallVectorImpl<MCParsedAsmOperand*>&);
141 OperandMatchResultTy parseCoprocOptionOperand(
142 SmallVectorImpl<MCParsedAsmOperand*>&);
143 OperandMatchResultTy parseMemBarrierOptOperand(
144 SmallVectorImpl<MCParsedAsmOperand*>&);
145 OperandMatchResultTy parseProcIFlagsOperand(
146 SmallVectorImpl<MCParsedAsmOperand*>&);
147 OperandMatchResultTy parseMSRMaskOperand(
148 SmallVectorImpl<MCParsedAsmOperand*>&);
149 OperandMatchResultTy parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &O,
150 StringRef Op, int Low, int High);
151 OperandMatchResultTy parsePKHLSLImm(SmallVectorImpl<MCParsedAsmOperand*> &O) {
152 return parsePKHImm(O, "lsl", 0, 31);
154 OperandMatchResultTy parsePKHASRImm(SmallVectorImpl<MCParsedAsmOperand*> &O) {
155 return parsePKHImm(O, "asr", 1, 32);
157 OperandMatchResultTy parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*>&);
158 OperandMatchResultTy parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*>&);
159 OperandMatchResultTy parseRotImm(SmallVectorImpl<MCParsedAsmOperand*>&);
160 OperandMatchResultTy parseBitfield(SmallVectorImpl<MCParsedAsmOperand*>&);
161 OperandMatchResultTy parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*>&);
162 OperandMatchResultTy parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*>&);
163 OperandMatchResultTy parseFPImm(SmallVectorImpl<MCParsedAsmOperand*>&);
164 OperandMatchResultTy parseVectorList(SmallVectorImpl<MCParsedAsmOperand*>&);
166 // Asm Match Converter Methods
167 bool cvtT2LdrdPre(MCInst &Inst, unsigned Opcode,
168 const SmallVectorImpl<MCParsedAsmOperand*> &);
169 bool cvtT2StrdPre(MCInst &Inst, unsigned Opcode,
170 const SmallVectorImpl<MCParsedAsmOperand*> &);
171 bool cvtLdWriteBackRegT2AddrModeImm8(MCInst &Inst, unsigned Opcode,
172 const SmallVectorImpl<MCParsedAsmOperand*> &);
173 bool cvtStWriteBackRegT2AddrModeImm8(MCInst &Inst, unsigned Opcode,
174 const SmallVectorImpl<MCParsedAsmOperand*> &);
175 bool cvtLdWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
176 const SmallVectorImpl<MCParsedAsmOperand*> &);
177 bool cvtLdWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode,
178 const SmallVectorImpl<MCParsedAsmOperand*> &);
179 bool cvtStWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode,
180 const SmallVectorImpl<MCParsedAsmOperand*> &);
181 bool cvtStWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
182 const SmallVectorImpl<MCParsedAsmOperand*> &);
183 bool cvtStWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
184 const SmallVectorImpl<MCParsedAsmOperand*> &);
185 bool cvtLdExtTWriteBackImm(MCInst &Inst, unsigned Opcode,
186 const SmallVectorImpl<MCParsedAsmOperand*> &);
187 bool cvtLdExtTWriteBackReg(MCInst &Inst, unsigned Opcode,
188 const SmallVectorImpl<MCParsedAsmOperand*> &);
189 bool cvtStExtTWriteBackImm(MCInst &Inst, unsigned Opcode,
190 const SmallVectorImpl<MCParsedAsmOperand*> &);
191 bool cvtStExtTWriteBackReg(MCInst &Inst, unsigned Opcode,
192 const SmallVectorImpl<MCParsedAsmOperand*> &);
193 bool cvtLdrdPre(MCInst &Inst, unsigned Opcode,
194 const SmallVectorImpl<MCParsedAsmOperand*> &);
195 bool cvtStrdPre(MCInst &Inst, unsigned Opcode,
196 const SmallVectorImpl<MCParsedAsmOperand*> &);
197 bool cvtLdWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
198 const SmallVectorImpl<MCParsedAsmOperand*> &);
199 bool cvtThumbMultiply(MCInst &Inst, unsigned Opcode,
200 const SmallVectorImpl<MCParsedAsmOperand*> &);
201 bool cvtVLDwbFixed(MCInst &Inst, unsigned Opcode,
202 const SmallVectorImpl<MCParsedAsmOperand*> &);
203 bool cvtVLDwbRegister(MCInst &Inst, unsigned Opcode,
204 const SmallVectorImpl<MCParsedAsmOperand*> &);
205 bool cvtVSTwbFixed(MCInst &Inst, unsigned Opcode,
206 const SmallVectorImpl<MCParsedAsmOperand*> &);
207 bool cvtVSTwbRegister(MCInst &Inst, unsigned Opcode,
208 const SmallVectorImpl<MCParsedAsmOperand*> &);
210 bool validateInstruction(MCInst &Inst,
211 const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
212 void processInstruction(MCInst &Inst,
213 const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
214 bool shouldOmitCCOutOperand(StringRef Mnemonic,
215 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
218 enum ARMMatchResultTy {
219 Match_RequiresITBlock = FIRST_TARGET_MATCH_RESULT_TY,
220 Match_RequiresNotITBlock,
225 ARMAsmParser(MCSubtargetInfo &_STI, MCAsmParser &_Parser)
226 : MCTargetAsmParser(), STI(_STI), Parser(_Parser) {
227 MCAsmParserExtension::Initialize(_Parser);
229 // Initialize the set of available features.
230 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
232 // Not in an ITBlock to start with.
233 ITState.CurPosition = ~0U;
236 // Implementation of the MCTargetAsmParser interface:
237 bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc);
238 bool ParseInstruction(StringRef Name, SMLoc NameLoc,
239 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
240 bool ParseDirective(AsmToken DirectiveID);
242 unsigned checkTargetMatchPredicate(MCInst &Inst);
244 bool MatchAndEmitInstruction(SMLoc IDLoc,
245 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
248 } // end anonymous namespace
252 /// ARMOperand - Instances of this class represent a parsed ARM machine
254 class ARMOperand : public MCParsedAsmOperand {
279 k_BitfieldDescriptor,
283 SMLoc StartLoc, EndLoc;
284 SmallVector<unsigned, 8> Registers;
288 ARMCC::CondCodes Val;
308 ARM_PROC::IFlags Val;
324 // A vector register list is a sequential list of 1 to 4 registers.
339 unsigned Val; // encoded 8-bit representation
342 /// Combined record for all forms of ARM address expressions.
345 // Offset is in OffsetReg or OffsetImm. If both are zero, no offset
347 const MCConstantExpr *OffsetImm; // Offset immediate value
348 unsigned OffsetRegNum; // Offset register num, when OffsetImm == NULL
349 ARM_AM::ShiftOpc ShiftType; // Shift type for OffsetReg
350 unsigned ShiftImm; // shift for OffsetReg.
351 unsigned Alignment; // 0 = no alignment specified
352 // n = alignment in bytes (8, 16, or 32)
353 unsigned isNegative : 1; // Negated OffsetReg? (~'U' bit)
359 ARM_AM::ShiftOpc ShiftTy;
368 ARM_AM::ShiftOpc ShiftTy;
374 ARM_AM::ShiftOpc ShiftTy;
387 ARMOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
389 ARMOperand(const ARMOperand &o) : MCParsedAsmOperand() {
391 StartLoc = o.StartLoc;
408 case k_DPRRegisterList:
409 case k_SPRRegisterList:
410 Registers = o.Registers;
413 VectorList = o.VectorList;
420 CoprocOption = o.CoprocOption;
428 case k_MemBarrierOpt:
434 case k_PostIndexRegister:
435 PostIdxReg = o.PostIdxReg;
443 case k_ShifterImmediate:
444 ShifterImm = o.ShifterImm;
446 case k_ShiftedRegister:
447 RegShiftedReg = o.RegShiftedReg;
449 case k_ShiftedImmediate:
450 RegShiftedImm = o.RegShiftedImm;
452 case k_RotateImmediate:
455 case k_BitfieldDescriptor:
456 Bitfield = o.Bitfield;
459 VectorIndex = o.VectorIndex;
464 /// getStartLoc - Get the location of the first token of this operand.
465 SMLoc getStartLoc() const { return StartLoc; }
466 /// getEndLoc - Get the location of the last token of this operand.
467 SMLoc getEndLoc() const { return EndLoc; }
469 ARMCC::CondCodes getCondCode() const {
470 assert(Kind == k_CondCode && "Invalid access!");
474 unsigned getCoproc() const {
475 assert((Kind == k_CoprocNum || Kind == k_CoprocReg) && "Invalid access!");
479 StringRef getToken() const {
480 assert(Kind == k_Token && "Invalid access!");
481 return StringRef(Tok.Data, Tok.Length);
484 unsigned getReg() const {
485 assert((Kind == k_Register || Kind == k_CCOut) && "Invalid access!");
489 const SmallVectorImpl<unsigned> &getRegList() const {
490 assert((Kind == k_RegisterList || Kind == k_DPRRegisterList ||
491 Kind == k_SPRRegisterList) && "Invalid access!");
495 const MCExpr *getImm() const {
496 assert(Kind == k_Immediate && "Invalid access!");
500 unsigned getFPImm() const {
501 assert(Kind == k_FPImmediate && "Invalid access!");
505 unsigned getVectorIndex() const {
506 assert(Kind == k_VectorIndex && "Invalid access!");
507 return VectorIndex.Val;
510 ARM_MB::MemBOpt getMemBarrierOpt() const {
511 assert(Kind == k_MemBarrierOpt && "Invalid access!");
515 ARM_PROC::IFlags getProcIFlags() const {
516 assert(Kind == k_ProcIFlags && "Invalid access!");
520 unsigned getMSRMask() const {
521 assert(Kind == k_MSRMask && "Invalid access!");
525 bool isCoprocNum() const { return Kind == k_CoprocNum; }
526 bool isCoprocReg() const { return Kind == k_CoprocReg; }
527 bool isCoprocOption() const { return Kind == k_CoprocOption; }
528 bool isCondCode() const { return Kind == k_CondCode; }
529 bool isCCOut() const { return Kind == k_CCOut; }
530 bool isITMask() const { return Kind == k_ITCondMask; }
531 bool isITCondCode() const { return Kind == k_CondCode; }
532 bool isImm() const { return Kind == k_Immediate; }
533 bool isFPImm() const { return Kind == k_FPImmediate; }
534 bool isImm8s4() const {
535 if (Kind != k_Immediate)
537 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
538 if (!CE) return false;
539 int64_t Value = CE->getValue();
540 return ((Value & 3) == 0) && Value >= -1020 && Value <= 1020;
542 bool isImm0_1020s4() const {
543 if (Kind != k_Immediate)
545 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
546 if (!CE) return false;
547 int64_t Value = CE->getValue();
548 return ((Value & 3) == 0) && Value >= 0 && Value <= 1020;
550 bool isImm0_508s4() const {
551 if (Kind != k_Immediate)
553 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
554 if (!CE) return false;
555 int64_t Value = CE->getValue();
556 return ((Value & 3) == 0) && Value >= 0 && Value <= 508;
558 bool isImm0_255() const {
559 if (Kind != k_Immediate)
561 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
562 if (!CE) return false;
563 int64_t Value = CE->getValue();
564 return Value >= 0 && Value < 256;
566 bool isImm0_7() const {
567 if (Kind != k_Immediate)
569 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
570 if (!CE) return false;
571 int64_t Value = CE->getValue();
572 return Value >= 0 && Value < 8;
574 bool isImm0_15() const {
575 if (Kind != k_Immediate)
577 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
578 if (!CE) return false;
579 int64_t Value = CE->getValue();
580 return Value >= 0 && Value < 16;
582 bool isImm0_31() const {
583 if (Kind != k_Immediate)
585 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
586 if (!CE) return false;
587 int64_t Value = CE->getValue();
588 return Value >= 0 && Value < 32;
590 bool isImm1_16() const {
591 if (Kind != k_Immediate)
593 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
594 if (!CE) return false;
595 int64_t Value = CE->getValue();
596 return Value > 0 && Value < 17;
598 bool isImm1_32() const {
599 if (Kind != k_Immediate)
601 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
602 if (!CE) return false;
603 int64_t Value = CE->getValue();
604 return Value > 0 && Value < 33;
606 bool isImm0_65535() const {
607 if (Kind != k_Immediate)
609 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
610 if (!CE) return false;
611 int64_t Value = CE->getValue();
612 return Value >= 0 && Value < 65536;
614 bool isImm0_65535Expr() const {
615 if (Kind != k_Immediate)
617 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
618 // If it's not a constant expression, it'll generate a fixup and be
620 if (!CE) return true;
621 int64_t Value = CE->getValue();
622 return Value >= 0 && Value < 65536;
624 bool isImm24bit() const {
625 if (Kind != k_Immediate)
627 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
628 if (!CE) return false;
629 int64_t Value = CE->getValue();
630 return Value >= 0 && Value <= 0xffffff;
632 bool isImmThumbSR() const {
633 if (Kind != k_Immediate)
635 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
636 if (!CE) return false;
637 int64_t Value = CE->getValue();
638 return Value > 0 && Value < 33;
640 bool isPKHLSLImm() const {
641 if (Kind != k_Immediate)
643 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
644 if (!CE) return false;
645 int64_t Value = CE->getValue();
646 return Value >= 0 && Value < 32;
648 bool isPKHASRImm() const {
649 if (Kind != k_Immediate)
651 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
652 if (!CE) return false;
653 int64_t Value = CE->getValue();
654 return Value > 0 && Value <= 32;
656 bool isARMSOImm() const {
657 if (Kind != k_Immediate)
659 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
660 if (!CE) return false;
661 int64_t Value = CE->getValue();
662 return ARM_AM::getSOImmVal(Value) != -1;
664 bool isARMSOImmNot() const {
665 if (Kind != k_Immediate)
667 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
668 if (!CE) return false;
669 int64_t Value = CE->getValue();
670 return ARM_AM::getSOImmVal(~Value) != -1;
672 bool isT2SOImm() const {
673 if (Kind != k_Immediate)
675 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
676 if (!CE) return false;
677 int64_t Value = CE->getValue();
678 return ARM_AM::getT2SOImmVal(Value) != -1;
680 bool isT2SOImmNot() const {
681 if (Kind != k_Immediate)
683 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
684 if (!CE) return false;
685 int64_t Value = CE->getValue();
686 return ARM_AM::getT2SOImmVal(~Value) != -1;
688 bool isSetEndImm() const {
689 if (Kind != k_Immediate)
691 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
692 if (!CE) return false;
693 int64_t Value = CE->getValue();
694 return Value == 1 || Value == 0;
696 bool isReg() const { return Kind == k_Register; }
697 bool isRegList() const { return Kind == k_RegisterList; }
698 bool isDPRRegList() const { return Kind == k_DPRRegisterList; }
699 bool isSPRRegList() const { return Kind == k_SPRRegisterList; }
700 bool isToken() const { return Kind == k_Token; }
701 bool isMemBarrierOpt() const { return Kind == k_MemBarrierOpt; }
702 bool isMemory() const { return Kind == k_Memory; }
703 bool isShifterImm() const { return Kind == k_ShifterImmediate; }
704 bool isRegShiftedReg() const { return Kind == k_ShiftedRegister; }
705 bool isRegShiftedImm() const { return Kind == k_ShiftedImmediate; }
706 bool isRotImm() const { return Kind == k_RotateImmediate; }
707 bool isBitfield() const { return Kind == k_BitfieldDescriptor; }
708 bool isPostIdxRegShifted() const { return Kind == k_PostIndexRegister; }
709 bool isPostIdxReg() const {
710 return Kind == k_PostIndexRegister && PostIdxReg.ShiftTy == ARM_AM::no_shift;
712 bool isMemNoOffset(bool alignOK = false) const {
715 // No offset of any kind.
716 return Memory.OffsetRegNum == 0 && Memory.OffsetImm == 0 &&
717 (alignOK || Memory.Alignment == 0);
719 bool isAlignedMemory() const {
720 return isMemNoOffset(true);
722 bool isAddrMode2() const {
723 if (!isMemory() || Memory.Alignment != 0) return false;
724 // Check for register offset.
725 if (Memory.OffsetRegNum) return true;
726 // Immediate offset in range [-4095, 4095].
727 if (!Memory.OffsetImm) return true;
728 int64_t Val = Memory.OffsetImm->getValue();
729 return Val > -4096 && Val < 4096;
731 bool isAM2OffsetImm() const {
732 if (Kind != k_Immediate)
734 // Immediate offset in range [-4095, 4095].
735 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
736 if (!CE) return false;
737 int64_t Val = CE->getValue();
738 return Val > -4096 && Val < 4096;
740 bool isAddrMode3() const {
741 if (!isMemory() || Memory.Alignment != 0) return false;
742 // No shifts are legal for AM3.
743 if (Memory.ShiftType != ARM_AM::no_shift) return false;
744 // Check for register offset.
745 if (Memory.OffsetRegNum) return true;
746 // Immediate offset in range [-255, 255].
747 if (!Memory.OffsetImm) return true;
748 int64_t Val = Memory.OffsetImm->getValue();
749 return Val > -256 && Val < 256;
751 bool isAM3Offset() const {
752 if (Kind != k_Immediate && Kind != k_PostIndexRegister)
754 if (Kind == k_PostIndexRegister)
755 return PostIdxReg.ShiftTy == ARM_AM::no_shift;
756 // Immediate offset in range [-255, 255].
757 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
758 if (!CE) return false;
759 int64_t Val = CE->getValue();
760 // Special case, #-0 is INT32_MIN.
761 return (Val > -256 && Val < 256) || Val == INT32_MIN;
763 bool isAddrMode5() const {
764 // If we have an immediate that's not a constant, treat it as a label
765 // reference needing a fixup. If it is a constant, it's something else
767 if (Kind == k_Immediate && !isa<MCConstantExpr>(getImm()))
769 if (!isMemory() || Memory.Alignment != 0) return false;
770 // Check for register offset.
771 if (Memory.OffsetRegNum) return false;
772 // Immediate offset in range [-1020, 1020] and a multiple of 4.
773 if (!Memory.OffsetImm) return true;
774 int64_t Val = Memory.OffsetImm->getValue();
775 return (Val >= -1020 && Val <= 1020 && ((Val & 3) == 0)) ||
778 bool isMemTBB() const {
779 if (!isMemory() || !Memory.OffsetRegNum || Memory.isNegative ||
780 Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0)
784 bool isMemTBH() const {
785 if (!isMemory() || !Memory.OffsetRegNum || Memory.isNegative ||
786 Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm != 1 ||
787 Memory.Alignment != 0 )
791 bool isMemRegOffset() const {
792 if (!isMemory() || !Memory.OffsetRegNum || Memory.Alignment != 0)
796 bool isT2MemRegOffset() const {
797 if (!isMemory() || !Memory.OffsetRegNum || Memory.isNegative ||
798 Memory.Alignment != 0)
800 // Only lsl #{0, 1, 2, 3} allowed.
801 if (Memory.ShiftType == ARM_AM::no_shift)
803 if (Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm > 3)
807 bool isMemThumbRR() const {
808 // Thumb reg+reg addressing is simple. Just two registers, a base and
809 // an offset. No shifts, negations or any other complicating factors.
810 if (!isMemory() || !Memory.OffsetRegNum || Memory.isNegative ||
811 Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0)
813 return isARMLowRegister(Memory.BaseRegNum) &&
814 (!Memory.OffsetRegNum || isARMLowRegister(Memory.OffsetRegNum));
816 bool isMemThumbRIs4() const {
817 if (!isMemory() || Memory.OffsetRegNum != 0 ||
818 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
820 // Immediate offset, multiple of 4 in range [0, 124].
821 if (!Memory.OffsetImm) return true;
822 int64_t Val = Memory.OffsetImm->getValue();
823 return Val >= 0 && Val <= 124 && (Val % 4) == 0;
825 bool isMemThumbRIs2() const {
826 if (!isMemory() || Memory.OffsetRegNum != 0 ||
827 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
829 // Immediate offset, multiple of 4 in range [0, 62].
830 if (!Memory.OffsetImm) return true;
831 int64_t Val = Memory.OffsetImm->getValue();
832 return Val >= 0 && Val <= 62 && (Val % 2) == 0;
834 bool isMemThumbRIs1() const {
835 if (!isMemory() || Memory.OffsetRegNum != 0 ||
836 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
838 // Immediate offset in range [0, 31].
839 if (!Memory.OffsetImm) return true;
840 int64_t Val = Memory.OffsetImm->getValue();
841 return Val >= 0 && Val <= 31;
843 bool isMemThumbSPI() const {
844 if (!isMemory() || Memory.OffsetRegNum != 0 ||
845 Memory.BaseRegNum != ARM::SP || Memory.Alignment != 0)
847 // Immediate offset, multiple of 4 in range [0, 1020].
848 if (!Memory.OffsetImm) return true;
849 int64_t Val = Memory.OffsetImm->getValue();
850 return Val >= 0 && Val <= 1020 && (Val % 4) == 0;
852 bool isMemImm8s4Offset() const {
853 if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
855 // Immediate offset a multiple of 4 in range [-1020, 1020].
856 if (!Memory.OffsetImm) return true;
857 int64_t Val = Memory.OffsetImm->getValue();
858 return Val >= -1020 && Val <= 1020 && (Val & 3) == 0;
860 bool isMemImm0_1020s4Offset() const {
861 if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
863 // Immediate offset a multiple of 4 in range [0, 1020].
864 if (!Memory.OffsetImm) return true;
865 int64_t Val = Memory.OffsetImm->getValue();
866 return Val >= 0 && Val <= 1020 && (Val & 3) == 0;
868 bool isMemImm8Offset() const {
869 if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
871 // Immediate offset in range [-255, 255].
872 if (!Memory.OffsetImm) return true;
873 int64_t Val = Memory.OffsetImm->getValue();
874 return (Val == INT32_MIN) || (Val > -256 && Val < 256);
876 bool isMemPosImm8Offset() const {
877 if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
879 // Immediate offset in range [0, 255].
880 if (!Memory.OffsetImm) return true;
881 int64_t Val = Memory.OffsetImm->getValue();
882 return Val >= 0 && Val < 256;
884 bool isMemNegImm8Offset() const {
885 if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
887 // Immediate offset in range [-255, -1].
888 if (!Memory.OffsetImm) return true;
889 int64_t Val = Memory.OffsetImm->getValue();
890 return Val > -256 && Val < 0;
892 bool isMemUImm12Offset() const {
893 if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
895 // Immediate offset in range [0, 4095].
896 if (!Memory.OffsetImm) return true;
897 int64_t Val = Memory.OffsetImm->getValue();
898 return (Val >= 0 && Val < 4096);
900 bool isMemImm12Offset() const {
901 // If we have an immediate that's not a constant, treat it as a label
902 // reference needing a fixup. If it is a constant, it's something else
904 if (Kind == k_Immediate && !isa<MCConstantExpr>(getImm()))
907 if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
909 // Immediate offset in range [-4095, 4095].
910 if (!Memory.OffsetImm) return true;
911 int64_t Val = Memory.OffsetImm->getValue();
912 return (Val > -4096 && Val < 4096) || (Val == INT32_MIN);
914 bool isPostIdxImm8() const {
915 if (Kind != k_Immediate)
917 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
918 if (!CE) return false;
919 int64_t Val = CE->getValue();
920 return (Val > -256 && Val < 256) || (Val == INT32_MIN);
922 bool isPostIdxImm8s4() const {
923 if (Kind != k_Immediate)
925 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
926 if (!CE) return false;
927 int64_t Val = CE->getValue();
928 return ((Val & 3) == 0 && Val >= -1020 && Val <= 1020) ||
932 bool isMSRMask() const { return Kind == k_MSRMask; }
933 bool isProcIFlags() const { return Kind == k_ProcIFlags; }
936 bool isVecListOneD() const {
937 if (Kind != k_VectorList) return false;
938 return VectorList.Count == 1;
941 bool isVecListTwoD() const {
942 if (Kind != k_VectorList) return false;
943 return VectorList.Count == 2;
946 bool isVecListThreeD() const {
947 if (Kind != k_VectorList) return false;
948 return VectorList.Count == 3;
951 bool isVecListFourD() const {
952 if (Kind != k_VectorList) return false;
953 return VectorList.Count == 4;
956 bool isVecListTwoQ() const {
957 if (Kind != k_VectorList) return false;
958 //FIXME: We haven't taught the parser to handle by-two register lists
959 // yet, so don't pretend to know one.
960 return VectorList.Count == 2 && false;
963 bool isVectorIndex8() const {
964 if (Kind != k_VectorIndex) return false;
965 return VectorIndex.Val < 8;
967 bool isVectorIndex16() const {
968 if (Kind != k_VectorIndex) return false;
969 return VectorIndex.Val < 4;
971 bool isVectorIndex32() const {
972 if (Kind != k_VectorIndex) return false;
973 return VectorIndex.Val < 2;
976 bool isNEONi8splat() const {
977 if (Kind != k_Immediate)
979 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
980 // Must be a constant.
981 if (!CE) return false;
982 int64_t Value = CE->getValue();
983 // i8 value splatted across 8 bytes. The immediate is just the 8 byte
985 return Value >= 0 && Value < 256;
988 bool isNEONi16splat() const {
989 if (Kind != k_Immediate)
991 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
992 // Must be a constant.
993 if (!CE) return false;
994 int64_t Value = CE->getValue();
995 // i16 value in the range [0,255] or [0x0100, 0xff00]
996 return (Value >= 0 && Value < 256) || (Value >= 0x0100 && Value <= 0xff00);
999 bool isNEONi32splat() const {
1000 if (Kind != k_Immediate)
1002 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1003 // Must be a constant.
1004 if (!CE) return false;
1005 int64_t Value = CE->getValue();
1006 // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X.
1007 return (Value >= 0 && Value < 256) ||
1008 (Value >= 0x0100 && Value <= 0xff00) ||
1009 (Value >= 0x010000 && Value <= 0xff0000) ||
1010 (Value >= 0x01000000 && Value <= 0xff000000);
1013 bool isNEONi32vmov() const {
1014 if (Kind != k_Immediate)
1016 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1017 // Must be a constant.
1018 if (!CE) return false;
1019 int64_t Value = CE->getValue();
1020 // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X,
1021 // for VMOV/VMVN only, 00Xf or 0Xff are also accepted.
1022 return (Value >= 0 && Value < 256) ||
1023 (Value >= 0x0100 && Value <= 0xff00) ||
1024 (Value >= 0x010000 && Value <= 0xff0000) ||
1025 (Value >= 0x01000000 && Value <= 0xff000000) ||
1026 (Value >= 0x01ff && Value <= 0xffff && (Value & 0xff) == 0xff) ||
1027 (Value >= 0x01ffff && Value <= 0xffffff && (Value & 0xffff) == 0xffff);
1030 bool isNEONi64splat() const {
1031 if (Kind != k_Immediate)
1033 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1034 // Must be a constant.
1035 if (!CE) return false;
1036 uint64_t Value = CE->getValue();
1037 // i64 value with each byte being either 0 or 0xff.
1038 for (unsigned i = 0; i < 8; ++i)
1039 if ((Value & 0xff) != 0 && (Value & 0xff) != 0xff) return false;
1043 void addExpr(MCInst &Inst, const MCExpr *Expr) const {
1044 // Add as immediates when possible. Null MCExpr = 0.
1046 Inst.addOperand(MCOperand::CreateImm(0));
1047 else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
1048 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
1050 Inst.addOperand(MCOperand::CreateExpr(Expr));
1053 void addCondCodeOperands(MCInst &Inst, unsigned N) const {
1054 assert(N == 2 && "Invalid number of operands!");
1055 Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
1056 unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR;
1057 Inst.addOperand(MCOperand::CreateReg(RegNum));
1060 void addCoprocNumOperands(MCInst &Inst, unsigned N) const {
1061 assert(N == 1 && "Invalid number of operands!");
1062 Inst.addOperand(MCOperand::CreateImm(getCoproc()));
1065 void addCoprocRegOperands(MCInst &Inst, unsigned N) const {
1066 assert(N == 1 && "Invalid number of operands!");
1067 Inst.addOperand(MCOperand::CreateImm(getCoproc()));
1070 void addCoprocOptionOperands(MCInst &Inst, unsigned N) const {
1071 assert(N == 1 && "Invalid number of operands!");
1072 Inst.addOperand(MCOperand::CreateImm(CoprocOption.Val));
1075 void addITMaskOperands(MCInst &Inst, unsigned N) const {
1076 assert(N == 1 && "Invalid number of operands!");
1077 Inst.addOperand(MCOperand::CreateImm(ITMask.Mask));
1080 void addITCondCodeOperands(MCInst &Inst, unsigned N) const {
1081 assert(N == 1 && "Invalid number of operands!");
1082 Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
1085 void addCCOutOperands(MCInst &Inst, unsigned N) const {
1086 assert(N == 1 && "Invalid number of operands!");
1087 Inst.addOperand(MCOperand::CreateReg(getReg()));
1090 void addRegOperands(MCInst &Inst, unsigned N) const {
1091 assert(N == 1 && "Invalid number of operands!");
1092 Inst.addOperand(MCOperand::CreateReg(getReg()));
1095 void addRegShiftedRegOperands(MCInst &Inst, unsigned N) const {
1096 assert(N == 3 && "Invalid number of operands!");
1097 assert(isRegShiftedReg() && "addRegShiftedRegOperands() on non RegShiftedReg!");
1098 Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.SrcReg));
1099 Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.ShiftReg));
1100 Inst.addOperand(MCOperand::CreateImm(
1101 ARM_AM::getSORegOpc(RegShiftedReg.ShiftTy, RegShiftedReg.ShiftImm)));
1104 void addRegShiftedImmOperands(MCInst &Inst, unsigned N) const {
1105 assert(N == 2 && "Invalid number of operands!");
1106 assert(isRegShiftedImm() && "addRegShiftedImmOperands() on non RegShiftedImm!");
1107 Inst.addOperand(MCOperand::CreateReg(RegShiftedImm.SrcReg));
1108 Inst.addOperand(MCOperand::CreateImm(
1109 ARM_AM::getSORegOpc(RegShiftedImm.ShiftTy, RegShiftedImm.ShiftImm)));
1112 void addShifterImmOperands(MCInst &Inst, unsigned N) const {
1113 assert(N == 1 && "Invalid number of operands!");
1114 Inst.addOperand(MCOperand::CreateImm((ShifterImm.isASR << 5) |
1118 void addRegListOperands(MCInst &Inst, unsigned N) const {
1119 assert(N == 1 && "Invalid number of operands!");
1120 const SmallVectorImpl<unsigned> &RegList = getRegList();
1121 for (SmallVectorImpl<unsigned>::const_iterator
1122 I = RegList.begin(), E = RegList.end(); I != E; ++I)
1123 Inst.addOperand(MCOperand::CreateReg(*I));
1126 void addDPRRegListOperands(MCInst &Inst, unsigned N) const {
1127 addRegListOperands(Inst, N);
1130 void addSPRRegListOperands(MCInst &Inst, unsigned N) const {
1131 addRegListOperands(Inst, N);
1134 void addRotImmOperands(MCInst &Inst, unsigned N) const {
1135 assert(N == 1 && "Invalid number of operands!");
1136 // Encoded as val>>3. The printer handles display as 8, 16, 24.
1137 Inst.addOperand(MCOperand::CreateImm(RotImm.Imm >> 3));
1140 void addBitfieldOperands(MCInst &Inst, unsigned N) const {
1141 assert(N == 1 && "Invalid number of operands!");
1142 // Munge the lsb/width into a bitfield mask.
1143 unsigned lsb = Bitfield.LSB;
1144 unsigned width = Bitfield.Width;
1145 // Make a 32-bit mask w/ the referenced bits clear and all other bits set.
1146 uint32_t Mask = ~(((uint32_t)0xffffffff >> lsb) << (32 - width) >>
1147 (32 - (lsb + width)));
1148 Inst.addOperand(MCOperand::CreateImm(Mask));
1151 void addImmOperands(MCInst &Inst, unsigned N) const {
1152 assert(N == 1 && "Invalid number of operands!");
1153 addExpr(Inst, getImm());
1156 void addFPImmOperands(MCInst &Inst, unsigned N) const {
1157 assert(N == 1 && "Invalid number of operands!");
1158 Inst.addOperand(MCOperand::CreateImm(getFPImm()));
1161 void addImm8s4Operands(MCInst &Inst, unsigned N) const {
1162 assert(N == 1 && "Invalid number of operands!");
1163 // FIXME: We really want to scale the value here, but the LDRD/STRD
1164 // instruction don't encode operands that way yet.
1165 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1166 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
1169 void addImm0_1020s4Operands(MCInst &Inst, unsigned N) const {
1170 assert(N == 1 && "Invalid number of operands!");
1171 // The immediate is scaled by four in the encoding and is stored
1172 // in the MCInst as such. Lop off the low two bits here.
1173 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1174 Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4));
1177 void addImm0_508s4Operands(MCInst &Inst, unsigned N) const {
1178 assert(N == 1 && "Invalid number of operands!");
1179 // The immediate is scaled by four in the encoding and is stored
1180 // in the MCInst as such. Lop off the low two bits here.
1181 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1182 Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4));
1185 void addImm0_255Operands(MCInst &Inst, unsigned N) const {
1186 assert(N == 1 && "Invalid number of operands!");
1187 addExpr(Inst, getImm());
1190 void addImm0_7Operands(MCInst &Inst, unsigned N) const {
1191 assert(N == 1 && "Invalid number of operands!");
1192 addExpr(Inst, getImm());
1195 void addImm0_15Operands(MCInst &Inst, unsigned N) const {
1196 assert(N == 1 && "Invalid number of operands!");
1197 addExpr(Inst, getImm());
1200 void addImm0_31Operands(MCInst &Inst, unsigned N) const {
1201 assert(N == 1 && "Invalid number of operands!");
1202 addExpr(Inst, getImm());
1205 void addImm1_16Operands(MCInst &Inst, unsigned N) const {
1206 assert(N == 1 && "Invalid number of operands!");
1207 // The constant encodes as the immediate-1, and we store in the instruction
1208 // the bits as encoded, so subtract off one here.
1209 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1210 Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
1213 void addImm1_32Operands(MCInst &Inst, unsigned N) const {
1214 assert(N == 1 && "Invalid number of operands!");
1215 // The constant encodes as the immediate-1, and we store in the instruction
1216 // the bits as encoded, so subtract off one here.
1217 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1218 Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
1221 void addImm0_65535Operands(MCInst &Inst, unsigned N) const {
1222 assert(N == 1 && "Invalid number of operands!");
1223 addExpr(Inst, getImm());
1226 void addImm0_65535ExprOperands(MCInst &Inst, unsigned N) const {
1227 assert(N == 1 && "Invalid number of operands!");
1228 addExpr(Inst, getImm());
1231 void addImm24bitOperands(MCInst &Inst, unsigned N) const {
1232 assert(N == 1 && "Invalid number of operands!");
1233 addExpr(Inst, getImm());
1236 void addImmThumbSROperands(MCInst &Inst, unsigned N) const {
1237 assert(N == 1 && "Invalid number of operands!");
1238 // The constant encodes as the immediate, except for 32, which encodes as
1240 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1241 unsigned Imm = CE->getValue();
1242 Inst.addOperand(MCOperand::CreateImm((Imm == 32 ? 0 : Imm)));
1245 void addPKHLSLImmOperands(MCInst &Inst, unsigned N) const {
1246 assert(N == 1 && "Invalid number of operands!");
1247 addExpr(Inst, getImm());
1250 void addPKHASRImmOperands(MCInst &Inst, unsigned N) const {
1251 assert(N == 1 && "Invalid number of operands!");
1252 // An ASR value of 32 encodes as 0, so that's how we want to add it to
1253 // the instruction as well.
1254 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1255 int Val = CE->getValue();
1256 Inst.addOperand(MCOperand::CreateImm(Val == 32 ? 0 : Val));
1259 void addARMSOImmOperands(MCInst &Inst, unsigned N) const {
1260 assert(N == 1 && "Invalid number of operands!");
1261 addExpr(Inst, getImm());
1264 void addT2SOImmOperands(MCInst &Inst, unsigned N) const {
1265 assert(N == 1 && "Invalid number of operands!");
1266 addExpr(Inst, getImm());
1269 void addT2SOImmNotOperands(MCInst &Inst, unsigned N) const {
1270 assert(N == 1 && "Invalid number of operands!");
1271 // The operand is actually a t2_so_imm, but we have its bitwise
1272 // negation in the assembly source, so twiddle it here.
1273 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1274 Inst.addOperand(MCOperand::CreateImm(~CE->getValue()));
1277 void addARMSOImmNotOperands(MCInst &Inst, unsigned N) const {
1278 assert(N == 1 && "Invalid number of operands!");
1279 // The operand is actually a so_imm, but we have its bitwise
1280 // negation in the assembly source, so twiddle it here.
1281 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1282 Inst.addOperand(MCOperand::CreateImm(~CE->getValue()));
1285 void addSetEndImmOperands(MCInst &Inst, unsigned N) const {
1286 assert(N == 1 && "Invalid number of operands!");
1287 addExpr(Inst, getImm());
1290 void addMemBarrierOptOperands(MCInst &Inst, unsigned N) const {
1291 assert(N == 1 && "Invalid number of operands!");
1292 Inst.addOperand(MCOperand::CreateImm(unsigned(getMemBarrierOpt())));
1295 void addMemNoOffsetOperands(MCInst &Inst, unsigned N) const {
1296 assert(N == 1 && "Invalid number of operands!");
1297 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1300 void addAlignedMemoryOperands(MCInst &Inst, unsigned N) const {
1301 assert(N == 2 && "Invalid number of operands!");
1302 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1303 Inst.addOperand(MCOperand::CreateImm(Memory.Alignment));
1306 void addAddrMode2Operands(MCInst &Inst, unsigned N) const {
1307 assert(N == 3 && "Invalid number of operands!");
1308 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1309 if (!Memory.OffsetRegNum) {
1310 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1311 // Special case for #-0
1312 if (Val == INT32_MIN) Val = 0;
1313 if (Val < 0) Val = -Val;
1314 Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
1316 // For register offset, we encode the shift type and negation flag
1318 Val = ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add,
1319 Memory.ShiftImm, Memory.ShiftType);
1321 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1322 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1323 Inst.addOperand(MCOperand::CreateImm(Val));
1326 void addAM2OffsetImmOperands(MCInst &Inst, unsigned N) const {
1327 assert(N == 2 && "Invalid number of operands!");
1328 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1329 assert(CE && "non-constant AM2OffsetImm operand!");
1330 int32_t Val = CE->getValue();
1331 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1332 // Special case for #-0
1333 if (Val == INT32_MIN) Val = 0;
1334 if (Val < 0) Val = -Val;
1335 Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
1336 Inst.addOperand(MCOperand::CreateReg(0));
1337 Inst.addOperand(MCOperand::CreateImm(Val));
1340 void addAddrMode3Operands(MCInst &Inst, unsigned N) const {
1341 assert(N == 3 && "Invalid number of operands!");
1342 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1343 if (!Memory.OffsetRegNum) {
1344 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1345 // Special case for #-0
1346 if (Val == INT32_MIN) Val = 0;
1347 if (Val < 0) Val = -Val;
1348 Val = ARM_AM::getAM3Opc(AddSub, Val);
1350 // For register offset, we encode the shift type and negation flag
1352 Val = ARM_AM::getAM3Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add, 0);
1354 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1355 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1356 Inst.addOperand(MCOperand::CreateImm(Val));
1359 void addAM3OffsetOperands(MCInst &Inst, unsigned N) const {
1360 assert(N == 2 && "Invalid number of operands!");
1361 if (Kind == k_PostIndexRegister) {
1363 ARM_AM::getAM3Opc(PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub, 0);
1364 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
1365 Inst.addOperand(MCOperand::CreateImm(Val));
1370 const MCConstantExpr *CE = static_cast<const MCConstantExpr*>(getImm());
1371 int32_t Val = CE->getValue();
1372 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1373 // Special case for #-0
1374 if (Val == INT32_MIN) Val = 0;
1375 if (Val < 0) Val = -Val;
1376 Val = ARM_AM::getAM3Opc(AddSub, Val);
1377 Inst.addOperand(MCOperand::CreateReg(0));
1378 Inst.addOperand(MCOperand::CreateImm(Val));
1381 void addAddrMode5Operands(MCInst &Inst, unsigned N) const {
1382 assert(N == 2 && "Invalid number of operands!");
1383 // If we have an immediate that's not a constant, treat it as a label
1384 // reference needing a fixup. If it is a constant, it's something else
1385 // and we reject it.
1387 Inst.addOperand(MCOperand::CreateExpr(getImm()));
1388 Inst.addOperand(MCOperand::CreateImm(0));
1392 // The lower two bits are always zero and as such are not encoded.
1393 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0;
1394 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1395 // Special case for #-0
1396 if (Val == INT32_MIN) Val = 0;
1397 if (Val < 0) Val = -Val;
1398 Val = ARM_AM::getAM5Opc(AddSub, Val);
1399 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1400 Inst.addOperand(MCOperand::CreateImm(Val));
1403 void addMemImm8s4OffsetOperands(MCInst &Inst, unsigned N) const {
1404 assert(N == 2 && "Invalid number of operands!");
1405 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1406 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1407 Inst.addOperand(MCOperand::CreateImm(Val));
1410 void addMemImm0_1020s4OffsetOperands(MCInst &Inst, unsigned N) const {
1411 assert(N == 2 && "Invalid number of operands!");
1412 // The lower two bits are always zero and as such are not encoded.
1413 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0;
1414 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1415 Inst.addOperand(MCOperand::CreateImm(Val));
1418 void addMemImm8OffsetOperands(MCInst &Inst, unsigned N) const {
1419 assert(N == 2 && "Invalid number of operands!");
1420 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1421 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1422 Inst.addOperand(MCOperand::CreateImm(Val));
1425 void addMemPosImm8OffsetOperands(MCInst &Inst, unsigned N) const {
1426 addMemImm8OffsetOperands(Inst, N);
1429 void addMemNegImm8OffsetOperands(MCInst &Inst, unsigned N) const {
1430 addMemImm8OffsetOperands(Inst, N);
1433 void addMemUImm12OffsetOperands(MCInst &Inst, unsigned N) const {
1434 assert(N == 2 && "Invalid number of operands!");
1435 // If this is an immediate, it's a label reference.
1436 if (Kind == k_Immediate) {
1437 addExpr(Inst, getImm());
1438 Inst.addOperand(MCOperand::CreateImm(0));
1442 // Otherwise, it's a normal memory reg+offset.
1443 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1444 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1445 Inst.addOperand(MCOperand::CreateImm(Val));
1448 void addMemImm12OffsetOperands(MCInst &Inst, unsigned N) const {
1449 assert(N == 2 && "Invalid number of operands!");
1450 // If this is an immediate, it's a label reference.
1451 if (Kind == k_Immediate) {
1452 addExpr(Inst, getImm());
1453 Inst.addOperand(MCOperand::CreateImm(0));
1457 // Otherwise, it's a normal memory reg+offset.
1458 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1459 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1460 Inst.addOperand(MCOperand::CreateImm(Val));
1463 void addMemTBBOperands(MCInst &Inst, unsigned N) const {
1464 assert(N == 2 && "Invalid number of operands!");
1465 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1466 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1469 void addMemTBHOperands(MCInst &Inst, unsigned N) const {
1470 assert(N == 2 && "Invalid number of operands!");
1471 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1472 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1475 void addMemRegOffsetOperands(MCInst &Inst, unsigned N) const {
1476 assert(N == 3 && "Invalid number of operands!");
1477 unsigned Val = ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add,
1478 Memory.ShiftImm, Memory.ShiftType);
1479 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1480 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1481 Inst.addOperand(MCOperand::CreateImm(Val));
1484 void addT2MemRegOffsetOperands(MCInst &Inst, unsigned N) const {
1485 assert(N == 3 && "Invalid number of operands!");
1486 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1487 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1488 Inst.addOperand(MCOperand::CreateImm(Memory.ShiftImm));
1491 void addMemThumbRROperands(MCInst &Inst, unsigned N) const {
1492 assert(N == 2 && "Invalid number of operands!");
1493 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1494 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1497 void addMemThumbRIs4Operands(MCInst &Inst, unsigned N) const {
1498 assert(N == 2 && "Invalid number of operands!");
1499 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0;
1500 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1501 Inst.addOperand(MCOperand::CreateImm(Val));
1504 void addMemThumbRIs2Operands(MCInst &Inst, unsigned N) const {
1505 assert(N == 2 && "Invalid number of operands!");
1506 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 2) : 0;
1507 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1508 Inst.addOperand(MCOperand::CreateImm(Val));
1511 void addMemThumbRIs1Operands(MCInst &Inst, unsigned N) const {
1512 assert(N == 2 && "Invalid number of operands!");
1513 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue()) : 0;
1514 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1515 Inst.addOperand(MCOperand::CreateImm(Val));
1518 void addMemThumbSPIOperands(MCInst &Inst, unsigned N) const {
1519 assert(N == 2 && "Invalid number of operands!");
1520 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0;
1521 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1522 Inst.addOperand(MCOperand::CreateImm(Val));
1525 void addPostIdxImm8Operands(MCInst &Inst, unsigned N) const {
1526 assert(N == 1 && "Invalid number of operands!");
1527 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1528 assert(CE && "non-constant post-idx-imm8 operand!");
1529 int Imm = CE->getValue();
1530 bool isAdd = Imm >= 0;
1531 if (Imm == INT32_MIN) Imm = 0;
1532 Imm = (Imm < 0 ? -Imm : Imm) | (int)isAdd << 8;
1533 Inst.addOperand(MCOperand::CreateImm(Imm));
1536 void addPostIdxImm8s4Operands(MCInst &Inst, unsigned N) const {
1537 assert(N == 1 && "Invalid number of operands!");
1538 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1539 assert(CE && "non-constant post-idx-imm8s4 operand!");
1540 int Imm = CE->getValue();
1541 bool isAdd = Imm >= 0;
1542 if (Imm == INT32_MIN) Imm = 0;
1543 // Immediate is scaled by 4.
1544 Imm = ((Imm < 0 ? -Imm : Imm) / 4) | (int)isAdd << 8;
1545 Inst.addOperand(MCOperand::CreateImm(Imm));
1548 void addPostIdxRegOperands(MCInst &Inst, unsigned N) const {
1549 assert(N == 2 && "Invalid number of operands!");
1550 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
1551 Inst.addOperand(MCOperand::CreateImm(PostIdxReg.isAdd));
1554 void addPostIdxRegShiftedOperands(MCInst &Inst, unsigned N) const {
1555 assert(N == 2 && "Invalid number of operands!");
1556 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
1557 // The sign, shift type, and shift amount are encoded in a single operand
1558 // using the AM2 encoding helpers.
1559 ARM_AM::AddrOpc opc = PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub;
1560 unsigned Imm = ARM_AM::getAM2Opc(opc, PostIdxReg.ShiftImm,
1561 PostIdxReg.ShiftTy);
1562 Inst.addOperand(MCOperand::CreateImm(Imm));
1565 void addMSRMaskOperands(MCInst &Inst, unsigned N) const {
1566 assert(N == 1 && "Invalid number of operands!");
1567 Inst.addOperand(MCOperand::CreateImm(unsigned(getMSRMask())));
1570 void addProcIFlagsOperands(MCInst &Inst, unsigned N) const {
1571 assert(N == 1 && "Invalid number of operands!");
1572 Inst.addOperand(MCOperand::CreateImm(unsigned(getProcIFlags())));
1575 void addVecListOneDOperands(MCInst &Inst, unsigned N) const {
1576 assert(N == 1 && "Invalid number of operands!");
1577 Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum));
1580 void addVecListTwoDOperands(MCInst &Inst, unsigned N) const {
1581 assert(N == 1 && "Invalid number of operands!");
1582 // Only the first register actually goes on the instruction. The rest
1583 // are implied by the opcode.
1584 Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum));
1587 void addVecListThreeDOperands(MCInst &Inst, unsigned N) const {
1588 assert(N == 1 && "Invalid number of operands!");
1589 // Only the first register actually goes on the instruction. The rest
1590 // are implied by the opcode.
1591 Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum));
1594 void addVecListFourDOperands(MCInst &Inst, unsigned N) const {
1595 assert(N == 1 && "Invalid number of operands!");
1596 // Only the first register actually goes on the instruction. The rest
1597 // are implied by the opcode.
1598 Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum));
1601 void addVecListTwoQOperands(MCInst &Inst, unsigned N) const {
1602 assert(N == 1 && "Invalid number of operands!");
1603 // Only the first register actually goes on the instruction. The rest
1604 // are implied by the opcode.
1605 Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum));
1608 void addVectorIndex8Operands(MCInst &Inst, unsigned N) const {
1609 assert(N == 1 && "Invalid number of operands!");
1610 Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
1613 void addVectorIndex16Operands(MCInst &Inst, unsigned N) const {
1614 assert(N == 1 && "Invalid number of operands!");
1615 Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
1618 void addVectorIndex32Operands(MCInst &Inst, unsigned N) const {
1619 assert(N == 1 && "Invalid number of operands!");
1620 Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
1623 void addNEONi8splatOperands(MCInst &Inst, unsigned N) const {
1624 assert(N == 1 && "Invalid number of operands!");
1625 // The immediate encodes the type of constant as well as the value.
1626 // Mask in that this is an i8 splat.
1627 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1628 Inst.addOperand(MCOperand::CreateImm(CE->getValue() | 0xe00));
1631 void addNEONi16splatOperands(MCInst &Inst, unsigned N) const {
1632 assert(N == 1 && "Invalid number of operands!");
1633 // The immediate encodes the type of constant as well as the value.
1634 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1635 unsigned Value = CE->getValue();
1637 Value = (Value >> 8) | 0xa00;
1640 Inst.addOperand(MCOperand::CreateImm(Value));
1643 void addNEONi32splatOperands(MCInst &Inst, unsigned N) const {
1644 assert(N == 1 && "Invalid number of operands!");
1645 // The immediate encodes the type of constant as well as the value.
1646 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1647 unsigned Value = CE->getValue();
1648 if (Value >= 256 && Value <= 0xff00)
1649 Value = (Value >> 8) | 0x200;
1650 else if (Value > 0xffff && Value <= 0xff0000)
1651 Value = (Value >> 16) | 0x400;
1652 else if (Value > 0xffffff)
1653 Value = (Value >> 24) | 0x600;
1654 Inst.addOperand(MCOperand::CreateImm(Value));
1657 void addNEONi32vmovOperands(MCInst &Inst, unsigned N) const {
1658 assert(N == 1 && "Invalid number of operands!");
1659 // The immediate encodes the type of constant as well as the value.
1660 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1661 unsigned Value = CE->getValue();
1662 if (Value >= 256 && Value <= 0xffff)
1663 Value = (Value >> 8) | ((Value & 0xff) ? 0xc00 : 0x200);
1664 else if (Value > 0xffff && Value <= 0xffffff)
1665 Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400);
1666 else if (Value > 0xffffff)
1667 Value = (Value >> 24) | 0x600;
1668 Inst.addOperand(MCOperand::CreateImm(Value));
1671 void addNEONi64splatOperands(MCInst &Inst, unsigned N) const {
1672 assert(N == 1 && "Invalid number of operands!");
1673 // The immediate encodes the type of constant as well as the value.
1674 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1675 uint64_t Value = CE->getValue();
1677 for (unsigned i = 0; i < 8; ++i, Value >>= 8) {
1678 Imm |= (Value & 1) << i;
1680 Inst.addOperand(MCOperand::CreateImm(Imm | 0x1e00));
1683 virtual void print(raw_ostream &OS) const;
1685 static ARMOperand *CreateITMask(unsigned Mask, SMLoc S) {
1686 ARMOperand *Op = new ARMOperand(k_ITCondMask);
1687 Op->ITMask.Mask = Mask;
1693 static ARMOperand *CreateCondCode(ARMCC::CondCodes CC, SMLoc S) {
1694 ARMOperand *Op = new ARMOperand(k_CondCode);
1701 static ARMOperand *CreateCoprocNum(unsigned CopVal, SMLoc S) {
1702 ARMOperand *Op = new ARMOperand(k_CoprocNum);
1703 Op->Cop.Val = CopVal;
1709 static ARMOperand *CreateCoprocReg(unsigned CopVal, SMLoc S) {
1710 ARMOperand *Op = new ARMOperand(k_CoprocReg);
1711 Op->Cop.Val = CopVal;
1717 static ARMOperand *CreateCoprocOption(unsigned Val, SMLoc S, SMLoc E) {
1718 ARMOperand *Op = new ARMOperand(k_CoprocOption);
1725 static ARMOperand *CreateCCOut(unsigned RegNum, SMLoc S) {
1726 ARMOperand *Op = new ARMOperand(k_CCOut);
1727 Op->Reg.RegNum = RegNum;
1733 static ARMOperand *CreateToken(StringRef Str, SMLoc S) {
1734 ARMOperand *Op = new ARMOperand(k_Token);
1735 Op->Tok.Data = Str.data();
1736 Op->Tok.Length = Str.size();
1742 static ARMOperand *CreateReg(unsigned RegNum, SMLoc S, SMLoc E) {
1743 ARMOperand *Op = new ARMOperand(k_Register);
1744 Op->Reg.RegNum = RegNum;
1750 static ARMOperand *CreateShiftedRegister(ARM_AM::ShiftOpc ShTy,
1755 ARMOperand *Op = new ARMOperand(k_ShiftedRegister);
1756 Op->RegShiftedReg.ShiftTy = ShTy;
1757 Op->RegShiftedReg.SrcReg = SrcReg;
1758 Op->RegShiftedReg.ShiftReg = ShiftReg;
1759 Op->RegShiftedReg.ShiftImm = ShiftImm;
1765 static ARMOperand *CreateShiftedImmediate(ARM_AM::ShiftOpc ShTy,
1769 ARMOperand *Op = new ARMOperand(k_ShiftedImmediate);
1770 Op->RegShiftedImm.ShiftTy = ShTy;
1771 Op->RegShiftedImm.SrcReg = SrcReg;
1772 Op->RegShiftedImm.ShiftImm = ShiftImm;
1778 static ARMOperand *CreateShifterImm(bool isASR, unsigned Imm,
1780 ARMOperand *Op = new ARMOperand(k_ShifterImmediate);
1781 Op->ShifterImm.isASR = isASR;
1782 Op->ShifterImm.Imm = Imm;
1788 static ARMOperand *CreateRotImm(unsigned Imm, SMLoc S, SMLoc E) {
1789 ARMOperand *Op = new ARMOperand(k_RotateImmediate);
1790 Op->RotImm.Imm = Imm;
1796 static ARMOperand *CreateBitfield(unsigned LSB, unsigned Width,
1798 ARMOperand *Op = new ARMOperand(k_BitfieldDescriptor);
1799 Op->Bitfield.LSB = LSB;
1800 Op->Bitfield.Width = Width;
1807 CreateRegList(const SmallVectorImpl<std::pair<unsigned, SMLoc> > &Regs,
1808 SMLoc StartLoc, SMLoc EndLoc) {
1809 KindTy Kind = k_RegisterList;
1811 if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Regs.front().first))
1812 Kind = k_DPRRegisterList;
1813 else if (ARMMCRegisterClasses[ARM::SPRRegClassID].
1814 contains(Regs.front().first))
1815 Kind = k_SPRRegisterList;
1817 ARMOperand *Op = new ARMOperand(Kind);
1818 for (SmallVectorImpl<std::pair<unsigned, SMLoc> >::const_iterator
1819 I = Regs.begin(), E = Regs.end(); I != E; ++I)
1820 Op->Registers.push_back(I->first);
1821 array_pod_sort(Op->Registers.begin(), Op->Registers.end());
1822 Op->StartLoc = StartLoc;
1823 Op->EndLoc = EndLoc;
1827 static ARMOperand *CreateVectorList(unsigned RegNum, unsigned Count,
1829 ARMOperand *Op = new ARMOperand(k_VectorList);
1830 Op->VectorList.RegNum = RegNum;
1831 Op->VectorList.Count = Count;
1837 static ARMOperand *CreateVectorIndex(unsigned Idx, SMLoc S, SMLoc E,
1839 ARMOperand *Op = new ARMOperand(k_VectorIndex);
1840 Op->VectorIndex.Val = Idx;
1846 static ARMOperand *CreateImm(const MCExpr *Val, SMLoc S, SMLoc E) {
1847 ARMOperand *Op = new ARMOperand(k_Immediate);
1854 static ARMOperand *CreateFPImm(unsigned Val, SMLoc S, MCContext &Ctx) {
1855 ARMOperand *Op = new ARMOperand(k_FPImmediate);
1856 Op->FPImm.Val = Val;
1862 static ARMOperand *CreateMem(unsigned BaseRegNum,
1863 const MCConstantExpr *OffsetImm,
1864 unsigned OffsetRegNum,
1865 ARM_AM::ShiftOpc ShiftType,
1870 ARMOperand *Op = new ARMOperand(k_Memory);
1871 Op->Memory.BaseRegNum = BaseRegNum;
1872 Op->Memory.OffsetImm = OffsetImm;
1873 Op->Memory.OffsetRegNum = OffsetRegNum;
1874 Op->Memory.ShiftType = ShiftType;
1875 Op->Memory.ShiftImm = ShiftImm;
1876 Op->Memory.Alignment = Alignment;
1877 Op->Memory.isNegative = isNegative;
1883 static ARMOperand *CreatePostIdxReg(unsigned RegNum, bool isAdd,
1884 ARM_AM::ShiftOpc ShiftTy,
1887 ARMOperand *Op = new ARMOperand(k_PostIndexRegister);
1888 Op->PostIdxReg.RegNum = RegNum;
1889 Op->PostIdxReg.isAdd = isAdd;
1890 Op->PostIdxReg.ShiftTy = ShiftTy;
1891 Op->PostIdxReg.ShiftImm = ShiftImm;
1897 static ARMOperand *CreateMemBarrierOpt(ARM_MB::MemBOpt Opt, SMLoc S) {
1898 ARMOperand *Op = new ARMOperand(k_MemBarrierOpt);
1899 Op->MBOpt.Val = Opt;
1905 static ARMOperand *CreateProcIFlags(ARM_PROC::IFlags IFlags, SMLoc S) {
1906 ARMOperand *Op = new ARMOperand(k_ProcIFlags);
1907 Op->IFlags.Val = IFlags;
1913 static ARMOperand *CreateMSRMask(unsigned MMask, SMLoc S) {
1914 ARMOperand *Op = new ARMOperand(k_MSRMask);
1915 Op->MMask.Val = MMask;
1922 } // end anonymous namespace.
1924 void ARMOperand::print(raw_ostream &OS) const {
1927 OS << "<fpimm " << getFPImm() << "(" << ARM_AM::getFPImmFloat(getFPImm())
1931 OS << "<ARMCC::" << ARMCondCodeToString(getCondCode()) << ">";
1934 OS << "<ccout " << getReg() << ">";
1936 case k_ITCondMask: {
1937 static const char *MaskStr[] = {
1938 "()", "(t)", "(e)", "(tt)", "(et)", "(te)", "(ee)", "(ttt)", "(ett)",
1939 "(tet)", "(eet)", "(tte)", "(ete)", "(tee)", "(eee)"
1941 assert((ITMask.Mask & 0xf) == ITMask.Mask);
1942 OS << "<it-mask " << MaskStr[ITMask.Mask] << ">";
1946 OS << "<coprocessor number: " << getCoproc() << ">";
1949 OS << "<coprocessor register: " << getCoproc() << ">";
1951 case k_CoprocOption:
1952 OS << "<coprocessor option: " << CoprocOption.Val << ">";
1955 OS << "<mask: " << getMSRMask() << ">";
1958 getImm()->print(OS);
1960 case k_MemBarrierOpt:
1961 OS << "<ARM_MB::" << MemBOptToString(getMemBarrierOpt()) << ">";
1965 << " base:" << Memory.BaseRegNum;
1968 case k_PostIndexRegister:
1969 OS << "post-idx register " << (PostIdxReg.isAdd ? "" : "-")
1970 << PostIdxReg.RegNum;
1971 if (PostIdxReg.ShiftTy != ARM_AM::no_shift)
1972 OS << ARM_AM::getShiftOpcStr(PostIdxReg.ShiftTy) << " "
1973 << PostIdxReg.ShiftImm;
1976 case k_ProcIFlags: {
1977 OS << "<ARM_PROC::";
1978 unsigned IFlags = getProcIFlags();
1979 for (int i=2; i >= 0; --i)
1980 if (IFlags & (1 << i))
1981 OS << ARM_PROC::IFlagsToString(1 << i);
1986 OS << "<register " << getReg() << ">";
1988 case k_ShifterImmediate:
1989 OS << "<shift " << (ShifterImm.isASR ? "asr" : "lsl")
1990 << " #" << ShifterImm.Imm << ">";
1992 case k_ShiftedRegister:
1993 OS << "<so_reg_reg "
1994 << RegShiftedReg.SrcReg
1995 << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(RegShiftedReg.ShiftImm))
1996 << ", " << RegShiftedReg.ShiftReg << ", "
1997 << ARM_AM::getSORegOffset(RegShiftedReg.ShiftImm)
2000 case k_ShiftedImmediate:
2001 OS << "<so_reg_imm "
2002 << RegShiftedImm.SrcReg
2003 << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(RegShiftedImm.ShiftImm))
2004 << ", " << ARM_AM::getSORegOffset(RegShiftedImm.ShiftImm)
2007 case k_RotateImmediate:
2008 OS << "<ror " << " #" << (RotImm.Imm * 8) << ">";
2010 case k_BitfieldDescriptor:
2011 OS << "<bitfield " << "lsb: " << Bitfield.LSB
2012 << ", width: " << Bitfield.Width << ">";
2014 case k_RegisterList:
2015 case k_DPRRegisterList:
2016 case k_SPRRegisterList: {
2017 OS << "<register_list ";
2019 const SmallVectorImpl<unsigned> &RegList = getRegList();
2020 for (SmallVectorImpl<unsigned>::const_iterator
2021 I = RegList.begin(), E = RegList.end(); I != E; ) {
2023 if (++I < E) OS << ", ";
2030 OS << "<vector_list " << VectorList.Count << " * "
2031 << VectorList.RegNum << ">";
2034 OS << "'" << getToken() << "'";
2037 OS << "<vectorindex " << getVectorIndex() << ">";
2042 /// @name Auto-generated Match Functions
2045 static unsigned MatchRegisterName(StringRef Name);
2049 bool ARMAsmParser::ParseRegister(unsigned &RegNo,
2050 SMLoc &StartLoc, SMLoc &EndLoc) {
2051 RegNo = tryParseRegister();
2053 return (RegNo == (unsigned)-1);
2056 /// Try to parse a register name. The token must be an Identifier when called,
2057 /// and if it is a register name the token is eaten and the register number is
2058 /// returned. Otherwise return -1.
2060 int ARMAsmParser::tryParseRegister() {
2061 const AsmToken &Tok = Parser.getTok();
2062 if (Tok.isNot(AsmToken::Identifier)) return -1;
2064 // FIXME: Validate register for the current architecture; we have to do
2065 // validation later, so maybe there is no need for this here.
2066 std::string upperCase = Tok.getString().str();
2067 std::string lowerCase = LowercaseString(upperCase);
2068 unsigned RegNum = MatchRegisterName(lowerCase);
2070 RegNum = StringSwitch<unsigned>(lowerCase)
2071 .Case("r13", ARM::SP)
2072 .Case("r14", ARM::LR)
2073 .Case("r15", ARM::PC)
2074 .Case("ip", ARM::R12)
2077 if (!RegNum) return -1;
2079 Parser.Lex(); // Eat identifier token.
2084 // Try to parse a shifter (e.g., "lsl <amt>"). On success, return 0.
2085 // If a recoverable error occurs, return 1. If an irrecoverable error
2086 // occurs, return -1. An irrecoverable error is one where tokens have been
2087 // consumed in the process of trying to parse the shifter (i.e., when it is
2088 // indeed a shifter operand, but malformed).
2089 int ARMAsmParser::tryParseShiftRegister(
2090 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2091 SMLoc S = Parser.getTok().getLoc();
2092 const AsmToken &Tok = Parser.getTok();
2093 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
2095 std::string upperCase = Tok.getString().str();
2096 std::string lowerCase = LowercaseString(upperCase);
2097 ARM_AM::ShiftOpc ShiftTy = StringSwitch<ARM_AM::ShiftOpc>(lowerCase)
2098 .Case("lsl", ARM_AM::lsl)
2099 .Case("lsr", ARM_AM::lsr)
2100 .Case("asr", ARM_AM::asr)
2101 .Case("ror", ARM_AM::ror)
2102 .Case("rrx", ARM_AM::rrx)
2103 .Default(ARM_AM::no_shift);
2105 if (ShiftTy == ARM_AM::no_shift)
2108 Parser.Lex(); // Eat the operator.
2110 // The source register for the shift has already been added to the
2111 // operand list, so we need to pop it off and combine it into the shifted
2112 // register operand instead.
2113 OwningPtr<ARMOperand> PrevOp((ARMOperand*)Operands.pop_back_val());
2114 if (!PrevOp->isReg())
2115 return Error(PrevOp->getStartLoc(), "shift must be of a register");
2116 int SrcReg = PrevOp->getReg();
2119 if (ShiftTy == ARM_AM::rrx) {
2120 // RRX Doesn't have an explicit shift amount. The encoder expects
2121 // the shift register to be the same as the source register. Seems odd,
2125 // Figure out if this is shifted by a constant or a register (for non-RRX).
2126 if (Parser.getTok().is(AsmToken::Hash)) {
2127 Parser.Lex(); // Eat hash.
2128 SMLoc ImmLoc = Parser.getTok().getLoc();
2129 const MCExpr *ShiftExpr = 0;
2130 if (getParser().ParseExpression(ShiftExpr)) {
2131 Error(ImmLoc, "invalid immediate shift value");
2134 // The expression must be evaluatable as an immediate.
2135 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftExpr);
2137 Error(ImmLoc, "invalid immediate shift value");
2140 // Range check the immediate.
2141 // lsl, ror: 0 <= imm <= 31
2142 // lsr, asr: 0 <= imm <= 32
2143 Imm = CE->getValue();
2145 ((ShiftTy == ARM_AM::lsl || ShiftTy == ARM_AM::ror) && Imm > 31) ||
2146 ((ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr) && Imm > 32)) {
2147 Error(ImmLoc, "immediate shift value out of range");
2150 } else if (Parser.getTok().is(AsmToken::Identifier)) {
2151 ShiftReg = tryParseRegister();
2152 SMLoc L = Parser.getTok().getLoc();
2153 if (ShiftReg == -1) {
2154 Error (L, "expected immediate or register in shift operand");
2158 Error (Parser.getTok().getLoc(),
2159 "expected immediate or register in shift operand");
2164 if (ShiftReg && ShiftTy != ARM_AM::rrx)
2165 Operands.push_back(ARMOperand::CreateShiftedRegister(ShiftTy, SrcReg,
2167 S, Parser.getTok().getLoc()));
2169 Operands.push_back(ARMOperand::CreateShiftedImmediate(ShiftTy, SrcReg, Imm,
2170 S, Parser.getTok().getLoc()));
2176 /// Try to parse a register name. The token must be an Identifier when called.
2177 /// If it's a register, an AsmOperand is created. Another AsmOperand is created
2178 /// if there is a "writeback". 'true' if it's not a register.
2180 /// TODO this is likely to change to allow different register types and or to
2181 /// parse for a specific register type.
2183 tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2184 SMLoc S = Parser.getTok().getLoc();
2185 int RegNo = tryParseRegister();
2189 Operands.push_back(ARMOperand::CreateReg(RegNo, S, Parser.getTok().getLoc()));
2191 const AsmToken &ExclaimTok = Parser.getTok();
2192 if (ExclaimTok.is(AsmToken::Exclaim)) {
2193 Operands.push_back(ARMOperand::CreateToken(ExclaimTok.getString(),
2194 ExclaimTok.getLoc()));
2195 Parser.Lex(); // Eat exclaim token
2199 // Also check for an index operand. This is only legal for vector registers,
2200 // but that'll get caught OK in operand matching, so we don't need to
2201 // explicitly filter everything else out here.
2202 if (Parser.getTok().is(AsmToken::LBrac)) {
2203 SMLoc SIdx = Parser.getTok().getLoc();
2204 Parser.Lex(); // Eat left bracket token.
2206 const MCExpr *ImmVal;
2207 if (getParser().ParseExpression(ImmVal))
2208 return MatchOperand_ParseFail;
2209 const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(ImmVal);
2211 TokError("immediate value expected for vector index");
2212 return MatchOperand_ParseFail;
2215 SMLoc E = Parser.getTok().getLoc();
2216 if (Parser.getTok().isNot(AsmToken::RBrac)) {
2217 Error(E, "']' expected");
2218 return MatchOperand_ParseFail;
2221 Parser.Lex(); // Eat right bracket token.
2223 Operands.push_back(ARMOperand::CreateVectorIndex(MCE->getValue(),
2231 /// MatchCoprocessorOperandName - Try to parse an coprocessor related
2232 /// instruction with a symbolic operand name. Example: "p1", "p7", "c3",
2234 static int MatchCoprocessorOperandName(StringRef Name, char CoprocOp) {
2235 // Use the same layout as the tablegen'erated register name matcher. Ugly,
2237 switch (Name.size()) {
2240 if (Name[0] != CoprocOp)
2257 if (Name[0] != CoprocOp || Name[1] != '1')
2261 case '0': return 10;
2262 case '1': return 11;
2263 case '2': return 12;
2264 case '3': return 13;
2265 case '4': return 14;
2266 case '5': return 15;
2274 /// parseITCondCode - Try to parse a condition code for an IT instruction.
2275 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2276 parseITCondCode(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2277 SMLoc S = Parser.getTok().getLoc();
2278 const AsmToken &Tok = Parser.getTok();
2279 if (!Tok.is(AsmToken::Identifier))
2280 return MatchOperand_NoMatch;
2281 unsigned CC = StringSwitch<unsigned>(Tok.getString())
2282 .Case("eq", ARMCC::EQ)
2283 .Case("ne", ARMCC::NE)
2284 .Case("hs", ARMCC::HS)
2285 .Case("cs", ARMCC::HS)
2286 .Case("lo", ARMCC::LO)
2287 .Case("cc", ARMCC::LO)
2288 .Case("mi", ARMCC::MI)
2289 .Case("pl", ARMCC::PL)
2290 .Case("vs", ARMCC::VS)
2291 .Case("vc", ARMCC::VC)
2292 .Case("hi", ARMCC::HI)
2293 .Case("ls", ARMCC::LS)
2294 .Case("ge", ARMCC::GE)
2295 .Case("lt", ARMCC::LT)
2296 .Case("gt", ARMCC::GT)
2297 .Case("le", ARMCC::LE)
2298 .Case("al", ARMCC::AL)
2301 return MatchOperand_NoMatch;
2302 Parser.Lex(); // Eat the token.
2304 Operands.push_back(ARMOperand::CreateCondCode(ARMCC::CondCodes(CC), S));
2306 return MatchOperand_Success;
2309 /// parseCoprocNumOperand - Try to parse an coprocessor number operand. The
2310 /// token must be an Identifier when called, and if it is a coprocessor
2311 /// number, the token is eaten and the operand is added to the operand list.
2312 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2313 parseCoprocNumOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2314 SMLoc S = Parser.getTok().getLoc();
2315 const AsmToken &Tok = Parser.getTok();
2316 if (Tok.isNot(AsmToken::Identifier))
2317 return MatchOperand_NoMatch;
2319 int Num = MatchCoprocessorOperandName(Tok.getString(), 'p');
2321 return MatchOperand_NoMatch;
2323 Parser.Lex(); // Eat identifier token.
2324 Operands.push_back(ARMOperand::CreateCoprocNum(Num, S));
2325 return MatchOperand_Success;
2328 /// parseCoprocRegOperand - Try to parse an coprocessor register operand. The
2329 /// token must be an Identifier when called, and if it is a coprocessor
2330 /// number, the token is eaten and the operand is added to the operand list.
2331 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2332 parseCoprocRegOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2333 SMLoc S = Parser.getTok().getLoc();
2334 const AsmToken &Tok = Parser.getTok();
2335 if (Tok.isNot(AsmToken::Identifier))
2336 return MatchOperand_NoMatch;
2338 int Reg = MatchCoprocessorOperandName(Tok.getString(), 'c');
2340 return MatchOperand_NoMatch;
2342 Parser.Lex(); // Eat identifier token.
2343 Operands.push_back(ARMOperand::CreateCoprocReg(Reg, S));
2344 return MatchOperand_Success;
2347 /// parseCoprocOptionOperand - Try to parse an coprocessor option operand.
2348 /// coproc_option : '{' imm0_255 '}'
2349 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2350 parseCoprocOptionOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2351 SMLoc S = Parser.getTok().getLoc();
2353 // If this isn't a '{', this isn't a coprocessor immediate operand.
2354 if (Parser.getTok().isNot(AsmToken::LCurly))
2355 return MatchOperand_NoMatch;
2356 Parser.Lex(); // Eat the '{'
2359 SMLoc Loc = Parser.getTok().getLoc();
2360 if (getParser().ParseExpression(Expr)) {
2361 Error(Loc, "illegal expression");
2362 return MatchOperand_ParseFail;
2364 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
2365 if (!CE || CE->getValue() < 0 || CE->getValue() > 255) {
2366 Error(Loc, "coprocessor option must be an immediate in range [0, 255]");
2367 return MatchOperand_ParseFail;
2369 int Val = CE->getValue();
2371 // Check for and consume the closing '}'
2372 if (Parser.getTok().isNot(AsmToken::RCurly))
2373 return MatchOperand_ParseFail;
2374 SMLoc E = Parser.getTok().getLoc();
2375 Parser.Lex(); // Eat the '}'
2377 Operands.push_back(ARMOperand::CreateCoprocOption(Val, S, E));
2378 return MatchOperand_Success;
2381 // For register list parsing, we need to map from raw GPR register numbering
2382 // to the enumeration values. The enumeration values aren't sorted by
2383 // register number due to our using "sp", "lr" and "pc" as canonical names.
2384 static unsigned getNextRegister(unsigned Reg) {
2385 // If this is a GPR, we need to do it manually, otherwise we can rely
2386 // on the sort ordering of the enumeration since the other reg-classes
2388 if (!ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
2391 default: assert(0 && "Invalid GPR number!");
2392 case ARM::R0: return ARM::R1; case ARM::R1: return ARM::R2;
2393 case ARM::R2: return ARM::R3; case ARM::R3: return ARM::R4;
2394 case ARM::R4: return ARM::R5; case ARM::R5: return ARM::R6;
2395 case ARM::R6: return ARM::R7; case ARM::R7: return ARM::R8;
2396 case ARM::R8: return ARM::R9; case ARM::R9: return ARM::R10;
2397 case ARM::R10: return ARM::R11; case ARM::R11: return ARM::R12;
2398 case ARM::R12: return ARM::SP; case ARM::SP: return ARM::LR;
2399 case ARM::LR: return ARM::PC; case ARM::PC: return ARM::R0;
2403 /// Parse a register list.
2405 parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2406 assert(Parser.getTok().is(AsmToken::LCurly) &&
2407 "Token is not a Left Curly Brace");
2408 SMLoc S = Parser.getTok().getLoc();
2409 Parser.Lex(); // Eat '{' token.
2410 SMLoc RegLoc = Parser.getTok().getLoc();
2412 // Check the first register in the list to see what register class
2413 // this is a list of.
2414 int Reg = tryParseRegister();
2416 return Error(RegLoc, "register expected");
2418 const MCRegisterClass *RC;
2419 if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
2420 RC = &ARMMCRegisterClasses[ARM::GPRRegClassID];
2421 else if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg))
2422 RC = &ARMMCRegisterClasses[ARM::DPRRegClassID];
2423 else if (ARMMCRegisterClasses[ARM::SPRRegClassID].contains(Reg))
2424 RC = &ARMMCRegisterClasses[ARM::SPRRegClassID];
2426 return Error(RegLoc, "invalid register in register list");
2428 // The reglist instructions have at most 16 registers, so reserve
2429 // space for that many.
2430 SmallVector<std::pair<unsigned, SMLoc>, 16> Registers;
2431 // Store the first register.
2432 Registers.push_back(std::pair<unsigned, SMLoc>(Reg, RegLoc));
2434 // This starts immediately after the first register token in the list,
2435 // so we can see either a comma or a minus (range separator) as a legal
2437 while (Parser.getTok().is(AsmToken::Comma) ||
2438 Parser.getTok().is(AsmToken::Minus)) {
2439 if (Parser.getTok().is(AsmToken::Minus)) {
2440 Parser.Lex(); // Eat the comma.
2441 SMLoc EndLoc = Parser.getTok().getLoc();
2442 int EndReg = tryParseRegister();
2444 return Error(EndLoc, "register expected");
2445 // If the register is the same as the start reg, there's nothing
2449 // The register must be in the same register class as the first.
2450 if (!RC->contains(EndReg))
2451 return Error(EndLoc, "invalid register in register list");
2452 // Ranges must go from low to high.
2453 if (getARMRegisterNumbering(Reg) > getARMRegisterNumbering(EndReg))
2454 return Error(EndLoc, "bad range in register list");
2456 // Add all the registers in the range to the register list.
2457 while (Reg != EndReg) {
2458 Reg = getNextRegister(Reg);
2459 Registers.push_back(std::pair<unsigned, SMLoc>(Reg, RegLoc));
2463 Parser.Lex(); // Eat the comma.
2464 RegLoc = Parser.getTok().getLoc();
2466 Reg = tryParseRegister();
2468 return Error(RegLoc, "register expected");
2469 // The register must be in the same register class as the first.
2470 if (!RC->contains(Reg))
2471 return Error(RegLoc, "invalid register in register list");
2472 // List must be monotonically increasing.
2473 if (getARMRegisterNumbering(Reg) <= getARMRegisterNumbering(OldReg))
2474 return Error(RegLoc, "register list not in ascending order");
2475 // VFP register lists must also be contiguous.
2476 // It's OK to use the enumeration values directly here rather, as the
2477 // VFP register classes have the enum sorted properly.
2478 if (RC != &ARMMCRegisterClasses[ARM::GPRRegClassID] &&
2480 return Error(RegLoc, "non-contiguous register range");
2481 Registers.push_back(std::pair<unsigned, SMLoc>(Reg, RegLoc));
2484 SMLoc E = Parser.getTok().getLoc();
2485 if (Parser.getTok().isNot(AsmToken::RCurly))
2486 return Error(E, "'}' expected");
2487 Parser.Lex(); // Eat '}' token.
2489 Operands.push_back(ARMOperand::CreateRegList(Registers, S, E));
2493 // Return the low-subreg of a given Q register.
2494 static unsigned getDRegFromQReg(unsigned QReg) {
2496 default: llvm_unreachable("expected a Q register!");
2497 case ARM::Q0: return ARM::D0;
2498 case ARM::Q1: return ARM::D2;
2499 case ARM::Q2: return ARM::D4;
2500 case ARM::Q3: return ARM::D6;
2501 case ARM::Q4: return ARM::D8;
2502 case ARM::Q5: return ARM::D10;
2503 case ARM::Q6: return ARM::D12;
2504 case ARM::Q7: return ARM::D14;
2505 case ARM::Q8: return ARM::D16;
2506 case ARM::Q9: return ARM::D19;
2507 case ARM::Q10: return ARM::D20;
2508 case ARM::Q11: return ARM::D22;
2509 case ARM::Q12: return ARM::D24;
2510 case ARM::Q13: return ARM::D26;
2511 case ARM::Q14: return ARM::D28;
2512 case ARM::Q15: return ARM::D30;
2516 // parse a vector register list
2517 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2518 parseVectorList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2519 if(Parser.getTok().isNot(AsmToken::LCurly))
2520 return MatchOperand_NoMatch;
2522 SMLoc S = Parser.getTok().getLoc();
2523 Parser.Lex(); // Eat '{' token.
2524 SMLoc RegLoc = Parser.getTok().getLoc();
2526 int Reg = tryParseRegister();
2528 Error(RegLoc, "register expected");
2529 return MatchOperand_ParseFail;
2532 unsigned FirstReg = Reg;
2533 // The list is of D registers, but we also allow Q regs and just interpret
2534 // them as the two D sub-registers.
2535 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
2536 FirstReg = Reg = getDRegFromQReg(Reg);
2541 while (Parser.getTok().is(AsmToken::Comma)) {
2542 Parser.Lex(); // Eat the comma.
2543 RegLoc = Parser.getTok().getLoc();
2545 Reg = tryParseRegister();
2547 Error(RegLoc, "register expected");
2548 return MatchOperand_ParseFail;
2550 // vector register lists must be contiguous.
2551 // It's OK to use the enumeration values directly here rather, as the
2552 // VFP register classes have the enum sorted properly.
2554 // The list is of D registers, but we also allow Q regs and just interpret
2555 // them as the two D sub-registers.
2556 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
2557 Reg = getDRegFromQReg(Reg);
2558 if (Reg != OldReg + 1) {
2559 Error(RegLoc, "non-contiguous register range");
2560 return MatchOperand_ParseFail;
2566 // Normal D register. Just check that it's contiguous and keep going.
2567 if (Reg != OldReg + 1) {
2568 Error(RegLoc, "non-contiguous register range");
2569 return MatchOperand_ParseFail;
2574 SMLoc E = Parser.getTok().getLoc();
2575 if (Parser.getTok().isNot(AsmToken::RCurly)) {
2576 Error(E, "'}' expected");
2577 return MatchOperand_ParseFail;
2579 Parser.Lex(); // Eat '}' token.
2581 Operands.push_back(ARMOperand::CreateVectorList(FirstReg, Count, S, E));
2582 return MatchOperand_Success;
2585 /// parseMemBarrierOptOperand - Try to parse DSB/DMB data barrier options.
2586 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2587 parseMemBarrierOptOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2588 SMLoc S = Parser.getTok().getLoc();
2589 const AsmToken &Tok = Parser.getTok();
2590 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
2591 StringRef OptStr = Tok.getString();
2593 unsigned Opt = StringSwitch<unsigned>(OptStr.slice(0, OptStr.size()))
2594 .Case("sy", ARM_MB::SY)
2595 .Case("st", ARM_MB::ST)
2596 .Case("sh", ARM_MB::ISH)
2597 .Case("ish", ARM_MB::ISH)
2598 .Case("shst", ARM_MB::ISHST)
2599 .Case("ishst", ARM_MB::ISHST)
2600 .Case("nsh", ARM_MB::NSH)
2601 .Case("un", ARM_MB::NSH)
2602 .Case("nshst", ARM_MB::NSHST)
2603 .Case("unst", ARM_MB::NSHST)
2604 .Case("osh", ARM_MB::OSH)
2605 .Case("oshst", ARM_MB::OSHST)
2609 return MatchOperand_NoMatch;
2611 Parser.Lex(); // Eat identifier token.
2612 Operands.push_back(ARMOperand::CreateMemBarrierOpt((ARM_MB::MemBOpt)Opt, S));
2613 return MatchOperand_Success;
2616 /// parseProcIFlagsOperand - Try to parse iflags from CPS instruction.
2617 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2618 parseProcIFlagsOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2619 SMLoc S = Parser.getTok().getLoc();
2620 const AsmToken &Tok = Parser.getTok();
2621 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
2622 StringRef IFlagsStr = Tok.getString();
2624 // An iflags string of "none" is interpreted to mean that none of the AIF
2625 // bits are set. Not a terribly useful instruction, but a valid encoding.
2626 unsigned IFlags = 0;
2627 if (IFlagsStr != "none") {
2628 for (int i = 0, e = IFlagsStr.size(); i != e; ++i) {
2629 unsigned Flag = StringSwitch<unsigned>(IFlagsStr.substr(i, 1))
2630 .Case("a", ARM_PROC::A)
2631 .Case("i", ARM_PROC::I)
2632 .Case("f", ARM_PROC::F)
2635 // If some specific iflag is already set, it means that some letter is
2636 // present more than once, this is not acceptable.
2637 if (Flag == ~0U || (IFlags & Flag))
2638 return MatchOperand_NoMatch;
2644 Parser.Lex(); // Eat identifier token.
2645 Operands.push_back(ARMOperand::CreateProcIFlags((ARM_PROC::IFlags)IFlags, S));
2646 return MatchOperand_Success;
2649 /// parseMSRMaskOperand - Try to parse mask flags from MSR instruction.
2650 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2651 parseMSRMaskOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2652 SMLoc S = Parser.getTok().getLoc();
2653 const AsmToken &Tok = Parser.getTok();
2654 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
2655 StringRef Mask = Tok.getString();
2658 // See ARMv6-M 10.1.1
2659 unsigned FlagsVal = StringSwitch<unsigned>(Mask)
2669 .Case("primask", 16)
2670 .Case("basepri", 17)
2671 .Case("basepri_max", 18)
2672 .Case("faultmask", 19)
2673 .Case("control", 20)
2676 if (FlagsVal == ~0U)
2677 return MatchOperand_NoMatch;
2679 if (!hasV7Ops() && FlagsVal >= 17 && FlagsVal <= 19)
2680 // basepri, basepri_max and faultmask only valid for V7m.
2681 return MatchOperand_NoMatch;
2683 Parser.Lex(); // Eat identifier token.
2684 Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S));
2685 return MatchOperand_Success;
2688 // Split spec_reg from flag, example: CPSR_sxf => "CPSR" and "sxf"
2689 size_t Start = 0, Next = Mask.find('_');
2690 StringRef Flags = "";
2691 std::string SpecReg = LowercaseString(Mask.slice(Start, Next));
2692 if (Next != StringRef::npos)
2693 Flags = Mask.slice(Next+1, Mask.size());
2695 // FlagsVal contains the complete mask:
2697 // 4: Special Reg (cpsr, apsr => 0; spsr => 1)
2698 unsigned FlagsVal = 0;
2700 if (SpecReg == "apsr") {
2701 FlagsVal = StringSwitch<unsigned>(Flags)
2702 .Case("nzcvq", 0x8) // same as CPSR_f
2703 .Case("g", 0x4) // same as CPSR_s
2704 .Case("nzcvqg", 0xc) // same as CPSR_fs
2707 if (FlagsVal == ~0U) {
2709 return MatchOperand_NoMatch;
2711 FlagsVal = 8; // No flag
2713 } else if (SpecReg == "cpsr" || SpecReg == "spsr") {
2714 if (Flags == "all") // cpsr_all is an alias for cpsr_fc
2716 for (int i = 0, e = Flags.size(); i != e; ++i) {
2717 unsigned Flag = StringSwitch<unsigned>(Flags.substr(i, 1))
2724 // If some specific flag is already set, it means that some letter is
2725 // present more than once, this is not acceptable.
2726 if (FlagsVal == ~0U || (FlagsVal & Flag))
2727 return MatchOperand_NoMatch;
2730 } else // No match for special register.
2731 return MatchOperand_NoMatch;
2733 // Special register without flags is NOT equivalent to "fc" flags.
2734 // NOTE: This is a divergence from gas' behavior. Uncommenting the following
2735 // two lines would enable gas compatibility at the expense of breaking
2741 // Bit 4: Special Reg (cpsr, apsr => 0; spsr => 1)
2742 if (SpecReg == "spsr")
2745 Parser.Lex(); // Eat identifier token.
2746 Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S));
2747 return MatchOperand_Success;
2750 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2751 parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands, StringRef Op,
2752 int Low, int High) {
2753 const AsmToken &Tok = Parser.getTok();
2754 if (Tok.isNot(AsmToken::Identifier)) {
2755 Error(Parser.getTok().getLoc(), Op + " operand expected.");
2756 return MatchOperand_ParseFail;
2758 StringRef ShiftName = Tok.getString();
2759 std::string LowerOp = LowercaseString(Op);
2760 std::string UpperOp = UppercaseString(Op);
2761 if (ShiftName != LowerOp && ShiftName != UpperOp) {
2762 Error(Parser.getTok().getLoc(), Op + " operand expected.");
2763 return MatchOperand_ParseFail;
2765 Parser.Lex(); // Eat shift type token.
2767 // There must be a '#' and a shift amount.
2768 if (Parser.getTok().isNot(AsmToken::Hash)) {
2769 Error(Parser.getTok().getLoc(), "'#' expected");
2770 return MatchOperand_ParseFail;
2772 Parser.Lex(); // Eat hash token.
2774 const MCExpr *ShiftAmount;
2775 SMLoc Loc = Parser.getTok().getLoc();
2776 if (getParser().ParseExpression(ShiftAmount)) {
2777 Error(Loc, "illegal expression");
2778 return MatchOperand_ParseFail;
2780 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
2782 Error(Loc, "constant expression expected");
2783 return MatchOperand_ParseFail;
2785 int Val = CE->getValue();
2786 if (Val < Low || Val > High) {
2787 Error(Loc, "immediate value out of range");
2788 return MatchOperand_ParseFail;
2791 Operands.push_back(ARMOperand::CreateImm(CE, Loc, Parser.getTok().getLoc()));
2793 return MatchOperand_Success;
2796 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2797 parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2798 const AsmToken &Tok = Parser.getTok();
2799 SMLoc S = Tok.getLoc();
2800 if (Tok.isNot(AsmToken::Identifier)) {
2801 Error(Tok.getLoc(), "'be' or 'le' operand expected");
2802 return MatchOperand_ParseFail;
2804 int Val = StringSwitch<int>(Tok.getString())
2808 Parser.Lex(); // Eat the token.
2811 Error(Tok.getLoc(), "'be' or 'le' operand expected");
2812 return MatchOperand_ParseFail;
2814 Operands.push_back(ARMOperand::CreateImm(MCConstantExpr::Create(Val,
2816 S, Parser.getTok().getLoc()));
2817 return MatchOperand_Success;
2820 /// parseShifterImm - Parse the shifter immediate operand for SSAT/USAT
2821 /// instructions. Legal values are:
2822 /// lsl #n 'n' in [0,31]
2823 /// asr #n 'n' in [1,32]
2824 /// n == 32 encoded as n == 0.
2825 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2826 parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2827 const AsmToken &Tok = Parser.getTok();
2828 SMLoc S = Tok.getLoc();
2829 if (Tok.isNot(AsmToken::Identifier)) {
2830 Error(S, "shift operator 'asr' or 'lsl' expected");
2831 return MatchOperand_ParseFail;
2833 StringRef ShiftName = Tok.getString();
2835 if (ShiftName == "lsl" || ShiftName == "LSL")
2837 else if (ShiftName == "asr" || ShiftName == "ASR")
2840 Error(S, "shift operator 'asr' or 'lsl' expected");
2841 return MatchOperand_ParseFail;
2843 Parser.Lex(); // Eat the operator.
2845 // A '#' and a shift amount.
2846 if (Parser.getTok().isNot(AsmToken::Hash)) {
2847 Error(Parser.getTok().getLoc(), "'#' expected");
2848 return MatchOperand_ParseFail;
2850 Parser.Lex(); // Eat hash token.
2852 const MCExpr *ShiftAmount;
2853 SMLoc E = Parser.getTok().getLoc();
2854 if (getParser().ParseExpression(ShiftAmount)) {
2855 Error(E, "malformed shift expression");
2856 return MatchOperand_ParseFail;
2858 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
2860 Error(E, "shift amount must be an immediate");
2861 return MatchOperand_ParseFail;
2864 int64_t Val = CE->getValue();
2866 // Shift amount must be in [1,32]
2867 if (Val < 1 || Val > 32) {
2868 Error(E, "'asr' shift amount must be in range [1,32]");
2869 return MatchOperand_ParseFail;
2871 // asr #32 encoded as asr #0, but is not allowed in Thumb2 mode.
2872 if (isThumb() && Val == 32) {
2873 Error(E, "'asr #32' shift amount not allowed in Thumb mode");
2874 return MatchOperand_ParseFail;
2876 if (Val == 32) Val = 0;
2878 // Shift amount must be in [1,32]
2879 if (Val < 0 || Val > 31) {
2880 Error(E, "'lsr' shift amount must be in range [0,31]");
2881 return MatchOperand_ParseFail;
2885 E = Parser.getTok().getLoc();
2886 Operands.push_back(ARMOperand::CreateShifterImm(isASR, Val, S, E));
2888 return MatchOperand_Success;
2891 /// parseRotImm - Parse the shifter immediate operand for SXTB/UXTB family
2892 /// of instructions. Legal values are:
2893 /// ror #n 'n' in {0, 8, 16, 24}
2894 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2895 parseRotImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2896 const AsmToken &Tok = Parser.getTok();
2897 SMLoc S = Tok.getLoc();
2898 if (Tok.isNot(AsmToken::Identifier))
2899 return MatchOperand_NoMatch;
2900 StringRef ShiftName = Tok.getString();
2901 if (ShiftName != "ror" && ShiftName != "ROR")
2902 return MatchOperand_NoMatch;
2903 Parser.Lex(); // Eat the operator.
2905 // A '#' and a rotate amount.
2906 if (Parser.getTok().isNot(AsmToken::Hash)) {
2907 Error(Parser.getTok().getLoc(), "'#' expected");
2908 return MatchOperand_ParseFail;
2910 Parser.Lex(); // Eat hash token.
2912 const MCExpr *ShiftAmount;
2913 SMLoc E = Parser.getTok().getLoc();
2914 if (getParser().ParseExpression(ShiftAmount)) {
2915 Error(E, "malformed rotate expression");
2916 return MatchOperand_ParseFail;
2918 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
2920 Error(E, "rotate amount must be an immediate");
2921 return MatchOperand_ParseFail;
2924 int64_t Val = CE->getValue();
2925 // Shift amount must be in {0, 8, 16, 24} (0 is undocumented extension)
2926 // normally, zero is represented in asm by omitting the rotate operand
2928 if (Val != 8 && Val != 16 && Val != 24 && Val != 0) {
2929 Error(E, "'ror' rotate amount must be 8, 16, or 24");
2930 return MatchOperand_ParseFail;
2933 E = Parser.getTok().getLoc();
2934 Operands.push_back(ARMOperand::CreateRotImm(Val, S, E));
2936 return MatchOperand_Success;
2939 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2940 parseBitfield(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2941 SMLoc S = Parser.getTok().getLoc();
2942 // The bitfield descriptor is really two operands, the LSB and the width.
2943 if (Parser.getTok().isNot(AsmToken::Hash)) {
2944 Error(Parser.getTok().getLoc(), "'#' expected");
2945 return MatchOperand_ParseFail;
2947 Parser.Lex(); // Eat hash token.
2949 const MCExpr *LSBExpr;
2950 SMLoc E = Parser.getTok().getLoc();
2951 if (getParser().ParseExpression(LSBExpr)) {
2952 Error(E, "malformed immediate expression");
2953 return MatchOperand_ParseFail;
2955 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LSBExpr);
2957 Error(E, "'lsb' operand must be an immediate");
2958 return MatchOperand_ParseFail;
2961 int64_t LSB = CE->getValue();
2962 // The LSB must be in the range [0,31]
2963 if (LSB < 0 || LSB > 31) {
2964 Error(E, "'lsb' operand must be in the range [0,31]");
2965 return MatchOperand_ParseFail;
2967 E = Parser.getTok().getLoc();
2969 // Expect another immediate operand.
2970 if (Parser.getTok().isNot(AsmToken::Comma)) {
2971 Error(Parser.getTok().getLoc(), "too few operands");
2972 return MatchOperand_ParseFail;
2974 Parser.Lex(); // Eat hash token.
2975 if (Parser.getTok().isNot(AsmToken::Hash)) {
2976 Error(Parser.getTok().getLoc(), "'#' expected");
2977 return MatchOperand_ParseFail;
2979 Parser.Lex(); // Eat hash token.
2981 const MCExpr *WidthExpr;
2982 if (getParser().ParseExpression(WidthExpr)) {
2983 Error(E, "malformed immediate expression");
2984 return MatchOperand_ParseFail;
2986 CE = dyn_cast<MCConstantExpr>(WidthExpr);
2988 Error(E, "'width' operand must be an immediate");
2989 return MatchOperand_ParseFail;
2992 int64_t Width = CE->getValue();
2993 // The LSB must be in the range [1,32-lsb]
2994 if (Width < 1 || Width > 32 - LSB) {
2995 Error(E, "'width' operand must be in the range [1,32-lsb]");
2996 return MatchOperand_ParseFail;
2998 E = Parser.getTok().getLoc();
3000 Operands.push_back(ARMOperand::CreateBitfield(LSB, Width, S, E));
3002 return MatchOperand_Success;
3005 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3006 parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3007 // Check for a post-index addressing register operand. Specifically:
3008 // postidx_reg := '+' register {, shift}
3009 // | '-' register {, shift}
3010 // | register {, shift}
3012 // This method must return MatchOperand_NoMatch without consuming any tokens
3013 // in the case where there is no match, as other alternatives take other
3015 AsmToken Tok = Parser.getTok();
3016 SMLoc S = Tok.getLoc();
3017 bool haveEaten = false;
3020 if (Tok.is(AsmToken::Plus)) {
3021 Parser.Lex(); // Eat the '+' token.
3023 } else if (Tok.is(AsmToken::Minus)) {
3024 Parser.Lex(); // Eat the '-' token.
3028 if (Parser.getTok().is(AsmToken::Identifier))
3029 Reg = tryParseRegister();
3032 return MatchOperand_NoMatch;
3033 Error(Parser.getTok().getLoc(), "register expected");
3034 return MatchOperand_ParseFail;
3036 SMLoc E = Parser.getTok().getLoc();
3038 ARM_AM::ShiftOpc ShiftTy = ARM_AM::no_shift;
3039 unsigned ShiftImm = 0;
3040 if (Parser.getTok().is(AsmToken::Comma)) {
3041 Parser.Lex(); // Eat the ','.
3042 if (parseMemRegOffsetShift(ShiftTy, ShiftImm))
3043 return MatchOperand_ParseFail;
3046 Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ShiftTy,
3049 return MatchOperand_Success;
3052 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3053 parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3054 // Check for a post-index addressing register operand. Specifically:
3055 // am3offset := '+' register
3062 // This method must return MatchOperand_NoMatch without consuming any tokens
3063 // in the case where there is no match, as other alternatives take other
3065 AsmToken Tok = Parser.getTok();
3066 SMLoc S = Tok.getLoc();
3068 // Do immediates first, as we always parse those if we have a '#'.
3069 if (Parser.getTok().is(AsmToken::Hash)) {
3070 Parser.Lex(); // Eat the '#'.
3071 // Explicitly look for a '-', as we need to encode negative zero
3073 bool isNegative = Parser.getTok().is(AsmToken::Minus);
3074 const MCExpr *Offset;
3075 if (getParser().ParseExpression(Offset))
3076 return MatchOperand_ParseFail;
3077 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
3079 Error(S, "constant expression expected");
3080 return MatchOperand_ParseFail;
3082 SMLoc E = Tok.getLoc();
3083 // Negative zero is encoded as the flag value INT32_MIN.
3084 int32_t Val = CE->getValue();
3085 if (isNegative && Val == 0)
3089 ARMOperand::CreateImm(MCConstantExpr::Create(Val, getContext()), S, E));
3091 return MatchOperand_Success;
3095 bool haveEaten = false;
3098 if (Tok.is(AsmToken::Plus)) {
3099 Parser.Lex(); // Eat the '+' token.
3101 } else if (Tok.is(AsmToken::Minus)) {
3102 Parser.Lex(); // Eat the '-' token.
3106 if (Parser.getTok().is(AsmToken::Identifier))
3107 Reg = tryParseRegister();
3110 return MatchOperand_NoMatch;
3111 Error(Parser.getTok().getLoc(), "register expected");
3112 return MatchOperand_ParseFail;
3114 SMLoc E = Parser.getTok().getLoc();
3116 Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ARM_AM::no_shift,
3119 return MatchOperand_Success;
3122 /// cvtT2LdrdPre - Convert parsed operands to MCInst.
3123 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
3124 /// when they refer multiple MIOperands inside a single one.
3126 cvtT2LdrdPre(MCInst &Inst, unsigned Opcode,
3127 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3129 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3130 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
3131 // Create a writeback register dummy placeholder.
3132 Inst.addOperand(MCOperand::CreateReg(0));
3134 ((ARMOperand*)Operands[4])->addMemImm8s4OffsetOperands(Inst, 2);
3136 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3140 /// cvtT2StrdPre - Convert parsed operands to MCInst.
3141 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
3142 /// when they refer multiple MIOperands inside a single one.
3144 cvtT2StrdPre(MCInst &Inst, unsigned Opcode,
3145 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3146 // Create a writeback register dummy placeholder.
3147 Inst.addOperand(MCOperand::CreateReg(0));
3149 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3150 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
3152 ((ARMOperand*)Operands[4])->addMemImm8s4OffsetOperands(Inst, 2);
3154 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3158 /// cvtLdWriteBackRegT2AddrModeImm8 - Convert parsed operands to MCInst.
3159 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
3160 /// when they refer multiple MIOperands inside a single one.
3162 cvtLdWriteBackRegT2AddrModeImm8(MCInst &Inst, unsigned Opcode,
3163 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3164 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3166 // Create a writeback register dummy placeholder.
3167 Inst.addOperand(MCOperand::CreateImm(0));
3169 ((ARMOperand*)Operands[3])->addMemImm8OffsetOperands(Inst, 2);
3170 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3174 /// cvtStWriteBackRegT2AddrModeImm8 - Convert parsed operands to MCInst.
3175 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
3176 /// when they refer multiple MIOperands inside a single one.
3178 cvtStWriteBackRegT2AddrModeImm8(MCInst &Inst, unsigned Opcode,
3179 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3180 // Create a writeback register dummy placeholder.
3181 Inst.addOperand(MCOperand::CreateImm(0));
3182 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3183 ((ARMOperand*)Operands[3])->addMemImm8OffsetOperands(Inst, 2);
3184 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3188 /// cvtLdWriteBackRegAddrMode2 - Convert parsed operands to MCInst.
3189 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
3190 /// when they refer multiple MIOperands inside a single one.
3192 cvtLdWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
3193 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3194 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3196 // Create a writeback register dummy placeholder.
3197 Inst.addOperand(MCOperand::CreateImm(0));
3199 ((ARMOperand*)Operands[3])->addAddrMode2Operands(Inst, 3);
3200 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3204 /// cvtLdWriteBackRegAddrModeImm12 - Convert parsed operands to MCInst.
3205 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
3206 /// when they refer multiple MIOperands inside a single one.
3208 cvtLdWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode,
3209 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3210 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3212 // Create a writeback register dummy placeholder.
3213 Inst.addOperand(MCOperand::CreateImm(0));
3215 ((ARMOperand*)Operands[3])->addMemImm12OffsetOperands(Inst, 2);
3216 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3221 /// cvtStWriteBackRegAddrModeImm12 - Convert parsed operands to MCInst.
3222 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
3223 /// when they refer multiple MIOperands inside a single one.
3225 cvtStWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode,
3226 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3227 // Create a writeback register dummy placeholder.
3228 Inst.addOperand(MCOperand::CreateImm(0));
3229 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3230 ((ARMOperand*)Operands[3])->addMemImm12OffsetOperands(Inst, 2);
3231 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3235 /// cvtStWriteBackRegAddrMode2 - Convert parsed operands to MCInst.
3236 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
3237 /// when they refer multiple MIOperands inside a single one.
3239 cvtStWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
3240 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3241 // Create a writeback register dummy placeholder.
3242 Inst.addOperand(MCOperand::CreateImm(0));
3243 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3244 ((ARMOperand*)Operands[3])->addAddrMode2Operands(Inst, 3);
3245 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3249 /// cvtStWriteBackRegAddrMode3 - Convert parsed operands to MCInst.
3250 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
3251 /// when they refer multiple MIOperands inside a single one.
3253 cvtStWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
3254 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3255 // Create a writeback register dummy placeholder.
3256 Inst.addOperand(MCOperand::CreateImm(0));
3257 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3258 ((ARMOperand*)Operands[3])->addAddrMode3Operands(Inst, 3);
3259 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3263 /// cvtLdExtTWriteBackImm - Convert parsed operands to MCInst.
3264 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
3265 /// when they refer multiple MIOperands inside a single one.
3267 cvtLdExtTWriteBackImm(MCInst &Inst, unsigned Opcode,
3268 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3270 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3271 // Create a writeback register dummy placeholder.
3272 Inst.addOperand(MCOperand::CreateImm(0));
3274 ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
3276 ((ARMOperand*)Operands[4])->addPostIdxImm8Operands(Inst, 1);
3278 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3282 /// cvtLdExtTWriteBackReg - Convert parsed operands to MCInst.
3283 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
3284 /// when they refer multiple MIOperands inside a single one.
3286 cvtLdExtTWriteBackReg(MCInst &Inst, unsigned Opcode,
3287 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3289 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3290 // Create a writeback register dummy placeholder.
3291 Inst.addOperand(MCOperand::CreateImm(0));
3293 ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
3295 ((ARMOperand*)Operands[4])->addPostIdxRegOperands(Inst, 2);
3297 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3301 /// cvtStExtTWriteBackImm - Convert parsed operands to MCInst.
3302 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
3303 /// when they refer multiple MIOperands inside a single one.
3305 cvtStExtTWriteBackImm(MCInst &Inst, unsigned Opcode,
3306 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3307 // Create a writeback register dummy placeholder.
3308 Inst.addOperand(MCOperand::CreateImm(0));
3310 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3312 ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
3314 ((ARMOperand*)Operands[4])->addPostIdxImm8Operands(Inst, 1);
3316 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3320 /// cvtStExtTWriteBackReg - Convert parsed operands to MCInst.
3321 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
3322 /// when they refer multiple MIOperands inside a single one.
3324 cvtStExtTWriteBackReg(MCInst &Inst, unsigned Opcode,
3325 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3326 // Create a writeback register dummy placeholder.
3327 Inst.addOperand(MCOperand::CreateImm(0));
3329 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3331 ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
3333 ((ARMOperand*)Operands[4])->addPostIdxRegOperands(Inst, 2);
3335 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3339 /// cvtLdrdPre - Convert parsed operands to MCInst.
3340 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
3341 /// when they refer multiple MIOperands inside a single one.
3343 cvtLdrdPre(MCInst &Inst, unsigned Opcode,
3344 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3346 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3347 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
3348 // Create a writeback register dummy placeholder.
3349 Inst.addOperand(MCOperand::CreateImm(0));
3351 ((ARMOperand*)Operands[4])->addAddrMode3Operands(Inst, 3);
3353 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3357 /// cvtStrdPre - Convert parsed operands to MCInst.
3358 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
3359 /// when they refer multiple MIOperands inside a single one.
3361 cvtStrdPre(MCInst &Inst, unsigned Opcode,
3362 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3363 // Create a writeback register dummy placeholder.
3364 Inst.addOperand(MCOperand::CreateImm(0));
3366 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3367 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
3369 ((ARMOperand*)Operands[4])->addAddrMode3Operands(Inst, 3);
3371 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3375 /// cvtLdWriteBackRegAddrMode3 - Convert parsed operands to MCInst.
3376 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
3377 /// when they refer multiple MIOperands inside a single one.
3379 cvtLdWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
3380 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3381 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3382 // Create a writeback register dummy placeholder.
3383 Inst.addOperand(MCOperand::CreateImm(0));
3384 ((ARMOperand*)Operands[3])->addAddrMode3Operands(Inst, 3);
3385 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3389 /// cvtThumbMultiple- Convert parsed operands to MCInst.
3390 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
3391 /// when they refer multiple MIOperands inside a single one.
3393 cvtThumbMultiply(MCInst &Inst, unsigned Opcode,
3394 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3395 // The second source operand must be the same register as the destination
3397 if (Operands.size() == 6 &&
3398 (((ARMOperand*)Operands[3])->getReg() !=
3399 ((ARMOperand*)Operands[5])->getReg()) &&
3400 (((ARMOperand*)Operands[3])->getReg() !=
3401 ((ARMOperand*)Operands[4])->getReg())) {
3402 Error(Operands[3]->getStartLoc(),
3403 "destination register must match source register");
3406 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
3407 ((ARMOperand*)Operands[1])->addCCOutOperands(Inst, 1);
3408 ((ARMOperand*)Operands[4])->addRegOperands(Inst, 1);
3409 // If we have a three-operand form, use that, else the second source operand
3410 // is just the destination operand again.
3411 if (Operands.size() == 6)
3412 ((ARMOperand*)Operands[5])->addRegOperands(Inst, 1);
3414 Inst.addOperand(Inst.getOperand(0));
3415 ((ARMOperand*)Operands[2])->addCondCodeOperands(Inst, 2);
3421 cvtVLDwbFixed(MCInst &Inst, unsigned Opcode,
3422 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3424 ((ARMOperand*)Operands[3])->addVecListTwoDOperands(Inst, 1);
3425 // Create a writeback register dummy placeholder.
3426 Inst.addOperand(MCOperand::CreateImm(0));
3428 ((ARMOperand*)Operands[4])->addAlignedMemoryOperands(Inst, 2);
3430 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3435 cvtVLDwbRegister(MCInst &Inst, unsigned Opcode,
3436 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3438 ((ARMOperand*)Operands[3])->addVecListTwoDOperands(Inst, 1);
3439 // Create a writeback register dummy placeholder.
3440 Inst.addOperand(MCOperand::CreateImm(0));
3442 ((ARMOperand*)Operands[4])->addAlignedMemoryOperands(Inst, 2);
3444 ((ARMOperand*)Operands[5])->addRegOperands(Inst, 1);
3446 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3451 cvtVSTwbFixed(MCInst &Inst, unsigned Opcode,
3452 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3453 // Create a writeback register dummy placeholder.
3454 Inst.addOperand(MCOperand::CreateImm(0));
3456 ((ARMOperand*)Operands[4])->addAlignedMemoryOperands(Inst, 2);
3458 ((ARMOperand*)Operands[3])->addVecListTwoDOperands(Inst, 1);
3460 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3465 cvtVSTwbRegister(MCInst &Inst, unsigned Opcode,
3466 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3467 // Create a writeback register dummy placeholder.
3468 Inst.addOperand(MCOperand::CreateImm(0));
3470 ((ARMOperand*)Operands[4])->addAlignedMemoryOperands(Inst, 2);
3472 ((ARMOperand*)Operands[5])->addRegOperands(Inst, 1);
3474 ((ARMOperand*)Operands[3])->addVecListTwoDOperands(Inst, 1);
3476 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3480 /// Parse an ARM memory expression, return false if successful else return true
3481 /// or an error. The first token must be a '[' when called.
3483 parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3485 assert(Parser.getTok().is(AsmToken::LBrac) &&
3486 "Token is not a Left Bracket");
3487 S = Parser.getTok().getLoc();
3488 Parser.Lex(); // Eat left bracket token.
3490 const AsmToken &BaseRegTok = Parser.getTok();
3491 int BaseRegNum = tryParseRegister();
3492 if (BaseRegNum == -1)
3493 return Error(BaseRegTok.getLoc(), "register expected");
3495 // The next token must either be a comma or a closing bracket.
3496 const AsmToken &Tok = Parser.getTok();
3497 if (!Tok.is(AsmToken::Comma) && !Tok.is(AsmToken::RBrac))
3498 return Error(Tok.getLoc(), "malformed memory operand");
3500 if (Tok.is(AsmToken::RBrac)) {
3502 Parser.Lex(); // Eat right bracket token.
3504 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, 0, ARM_AM::no_shift,
3505 0, 0, false, S, E));
3507 // If there's a pre-indexing writeback marker, '!', just add it as a token
3508 // operand. It's rather odd, but syntactically valid.
3509 if (Parser.getTok().is(AsmToken::Exclaim)) {
3510 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
3511 Parser.Lex(); // Eat the '!'.
3517 assert(Tok.is(AsmToken::Comma) && "Lost comma in memory operand?!");
3518 Parser.Lex(); // Eat the comma.
3520 // If we have a ':', it's an alignment specifier.
3521 if (Parser.getTok().is(AsmToken::Colon)) {
3522 Parser.Lex(); // Eat the ':'.
3523 E = Parser.getTok().getLoc();
3526 if (getParser().ParseExpression(Expr))
3529 // The expression has to be a constant. Memory references with relocations
3530 // don't come through here, as they use the <label> forms of the relevant
3532 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
3534 return Error (E, "constant expression expected");
3537 switch (CE->getValue()) {
3539 return Error(E, "alignment specifier must be 64, 128, or 256 bits");
3540 case 64: Align = 8; break;
3541 case 128: Align = 16; break;
3542 case 256: Align = 32; break;
3545 // Now we should have the closing ']'
3546 E = Parser.getTok().getLoc();
3547 if (Parser.getTok().isNot(AsmToken::RBrac))
3548 return Error(E, "']' expected");
3549 Parser.Lex(); // Eat right bracket token.
3551 // Don't worry about range checking the value here. That's handled by
3552 // the is*() predicates.
3553 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, 0,
3554 ARM_AM::no_shift, 0, Align,
3557 // If there's a pre-indexing writeback marker, '!', just add it as a token
3559 if (Parser.getTok().is(AsmToken::Exclaim)) {
3560 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
3561 Parser.Lex(); // Eat the '!'.
3567 // If we have a '#', it's an immediate offset, else assume it's a register
3569 if (Parser.getTok().is(AsmToken::Hash)) {
3570 Parser.Lex(); // Eat the '#'.
3571 E = Parser.getTok().getLoc();
3573 bool isNegative = getParser().getTok().is(AsmToken::Minus);
3574 const MCExpr *Offset;
3575 if (getParser().ParseExpression(Offset))
3578 // The expression has to be a constant. Memory references with relocations
3579 // don't come through here, as they use the <label> forms of the relevant
3581 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
3583 return Error (E, "constant expression expected");
3585 // If the constant was #-0, represent it as INT32_MIN.
3586 int32_t Val = CE->getValue();
3587 if (isNegative && Val == 0)
3588 CE = MCConstantExpr::Create(INT32_MIN, getContext());
3590 // Now we should have the closing ']'
3591 E = Parser.getTok().getLoc();
3592 if (Parser.getTok().isNot(AsmToken::RBrac))
3593 return Error(E, "']' expected");
3594 Parser.Lex(); // Eat right bracket token.
3596 // Don't worry about range checking the value here. That's handled by
3597 // the is*() predicates.
3598 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, CE, 0,
3599 ARM_AM::no_shift, 0, 0,
3602 // If there's a pre-indexing writeback marker, '!', just add it as a token
3604 if (Parser.getTok().is(AsmToken::Exclaim)) {
3605 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
3606 Parser.Lex(); // Eat the '!'.
3612 // The register offset is optionally preceded by a '+' or '-'
3613 bool isNegative = false;
3614 if (Parser.getTok().is(AsmToken::Minus)) {
3616 Parser.Lex(); // Eat the '-'.
3617 } else if (Parser.getTok().is(AsmToken::Plus)) {
3619 Parser.Lex(); // Eat the '+'.
3622 E = Parser.getTok().getLoc();
3623 int OffsetRegNum = tryParseRegister();
3624 if (OffsetRegNum == -1)
3625 return Error(E, "register expected");
3627 // If there's a shift operator, handle it.
3628 ARM_AM::ShiftOpc ShiftType = ARM_AM::no_shift;
3629 unsigned ShiftImm = 0;
3630 if (Parser.getTok().is(AsmToken::Comma)) {
3631 Parser.Lex(); // Eat the ','.
3632 if (parseMemRegOffsetShift(ShiftType, ShiftImm))
3636 // Now we should have the closing ']'
3637 E = Parser.getTok().getLoc();
3638 if (Parser.getTok().isNot(AsmToken::RBrac))
3639 return Error(E, "']' expected");
3640 Parser.Lex(); // Eat right bracket token.
3642 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, OffsetRegNum,
3643 ShiftType, ShiftImm, 0, isNegative,
3646 // If there's a pre-indexing writeback marker, '!', just add it as a token
3648 if (Parser.getTok().is(AsmToken::Exclaim)) {
3649 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
3650 Parser.Lex(); // Eat the '!'.
3656 /// parseMemRegOffsetShift - one of these two:
3657 /// ( lsl | lsr | asr | ror ) , # shift_amount
3659 /// return true if it parses a shift otherwise it returns false.
3660 bool ARMAsmParser::parseMemRegOffsetShift(ARM_AM::ShiftOpc &St,
3662 SMLoc Loc = Parser.getTok().getLoc();
3663 const AsmToken &Tok = Parser.getTok();
3664 if (Tok.isNot(AsmToken::Identifier))
3666 StringRef ShiftName = Tok.getString();
3667 if (ShiftName == "lsl" || ShiftName == "LSL")
3669 else if (ShiftName == "lsr" || ShiftName == "LSR")
3671 else if (ShiftName == "asr" || ShiftName == "ASR")
3673 else if (ShiftName == "ror" || ShiftName == "ROR")
3675 else if (ShiftName == "rrx" || ShiftName == "RRX")
3678 return Error(Loc, "illegal shift operator");
3679 Parser.Lex(); // Eat shift type token.
3681 // rrx stands alone.
3683 if (St != ARM_AM::rrx) {
3684 Loc = Parser.getTok().getLoc();
3685 // A '#' and a shift amount.
3686 const AsmToken &HashTok = Parser.getTok();
3687 if (HashTok.isNot(AsmToken::Hash))
3688 return Error(HashTok.getLoc(), "'#' expected");
3689 Parser.Lex(); // Eat hash token.
3692 if (getParser().ParseExpression(Expr))
3694 // Range check the immediate.
3695 // lsl, ror: 0 <= imm <= 31
3696 // lsr, asr: 0 <= imm <= 32
3697 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
3699 return Error(Loc, "shift amount must be an immediate");
3700 int64_t Imm = CE->getValue();
3702 ((St == ARM_AM::lsl || St == ARM_AM::ror) && Imm > 31) ||
3703 ((St == ARM_AM::lsr || St == ARM_AM::asr) && Imm > 32))
3704 return Error(Loc, "immediate shift value out of range");
3711 /// parseFPImm - A floating point immediate expression operand.
3712 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3713 parseFPImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3714 SMLoc S = Parser.getTok().getLoc();
3716 if (Parser.getTok().isNot(AsmToken::Hash))
3717 return MatchOperand_NoMatch;
3719 // Disambiguate the VMOV forms that can accept an FP immediate.
3720 // vmov.f32 <sreg>, #imm
3721 // vmov.f64 <dreg>, #imm
3722 // vmov.f32 <dreg>, #imm @ vector f32x2
3723 // vmov.f32 <qreg>, #imm @ vector f32x4
3725 // There are also the NEON VMOV instructions which expect an
3726 // integer constant. Make sure we don't try to parse an FPImm
3728 // vmov.i{8|16|32|64} <dreg|qreg>, #imm
3729 ARMOperand *TyOp = static_cast<ARMOperand*>(Operands[2]);
3730 if (!TyOp->isToken() || (TyOp->getToken() != ".f32" &&
3731 TyOp->getToken() != ".f64"))
3732 return MatchOperand_NoMatch;
3734 Parser.Lex(); // Eat the '#'.
3736 // Handle negation, as that still comes through as a separate token.
3737 bool isNegative = false;
3738 if (Parser.getTok().is(AsmToken::Minus)) {
3742 const AsmToken &Tok = Parser.getTok();
3743 if (Tok.is(AsmToken::Real)) {
3744 APFloat RealVal(APFloat::IEEEdouble, Tok.getString());
3745 uint64_t IntVal = RealVal.bitcastToAPInt().getZExtValue();
3746 // If we had a '-' in front, toggle the sign bit.
3747 IntVal ^= (uint64_t)isNegative << 63;
3748 int Val = ARM_AM::getFP64Imm(APInt(64, IntVal));
3749 Parser.Lex(); // Eat the token.
3751 TokError("floating point value out of range");
3752 return MatchOperand_ParseFail;
3754 Operands.push_back(ARMOperand::CreateFPImm(Val, S, getContext()));
3755 return MatchOperand_Success;
3757 if (Tok.is(AsmToken::Integer)) {
3758 int64_t Val = Tok.getIntVal();
3759 Parser.Lex(); // Eat the token.
3760 if (Val > 255 || Val < 0) {
3761 TokError("encoded floating point value out of range");
3762 return MatchOperand_ParseFail;
3764 Operands.push_back(ARMOperand::CreateFPImm(Val, S, getContext()));
3765 return MatchOperand_Success;
3768 TokError("invalid floating point immediate");
3769 return MatchOperand_ParseFail;
3771 /// Parse a arm instruction operand. For now this parses the operand regardless
3772 /// of the mnemonic.
3773 bool ARMAsmParser::parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
3774 StringRef Mnemonic) {
3777 // Check if the current operand has a custom associated parser, if so, try to
3778 // custom parse the operand, or fallback to the general approach.
3779 OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
3780 if (ResTy == MatchOperand_Success)
3782 // If there wasn't a custom match, try the generic matcher below. Otherwise,
3783 // there was a match, but an error occurred, in which case, just return that
3784 // the operand parsing failed.
3785 if (ResTy == MatchOperand_ParseFail)
3788 switch (getLexer().getKind()) {
3790 Error(Parser.getTok().getLoc(), "unexpected token in operand");
3792 case AsmToken::Identifier: {
3793 // If this is VMRS, check for the apsr_nzcv operand.
3794 if (!tryParseRegisterWithWriteBack(Operands))
3796 int Res = tryParseShiftRegister(Operands);
3797 if (Res == 0) // success
3799 else if (Res == -1) // irrecoverable error
3801 if (Mnemonic == "vmrs" && Parser.getTok().getString() == "apsr_nzcv") {
3802 S = Parser.getTok().getLoc();
3804 Operands.push_back(ARMOperand::CreateToken("apsr_nzcv", S));
3808 // Fall though for the Identifier case that is not a register or a
3811 case AsmToken::LParen: // parenthesized expressions like (_strcmp-4)
3812 case AsmToken::Integer: // things like 1f and 2b as a branch targets
3813 case AsmToken::String: // quoted label names.
3814 case AsmToken::Dot: { // . as a branch target
3815 // This was not a register so parse other operands that start with an
3816 // identifier (like labels) as expressions and create them as immediates.
3817 const MCExpr *IdVal;
3818 S = Parser.getTok().getLoc();
3819 if (getParser().ParseExpression(IdVal))
3821 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
3822 Operands.push_back(ARMOperand::CreateImm(IdVal, S, E));
3825 case AsmToken::LBrac:
3826 return parseMemory(Operands);
3827 case AsmToken::LCurly:
3828 return parseRegisterList(Operands);
3829 case AsmToken::Hash: {
3830 // #42 -> immediate.
3831 // TODO: ":lower16:" and ":upper16:" modifiers after # before immediate
3832 S = Parser.getTok().getLoc();
3834 bool isNegative = Parser.getTok().is(AsmToken::Minus);
3835 const MCExpr *ImmVal;
3836 if (getParser().ParseExpression(ImmVal))
3838 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ImmVal);
3840 int32_t Val = CE->getValue();
3841 if (isNegative && Val == 0)
3842 ImmVal = MCConstantExpr::Create(INT32_MIN, getContext());
3844 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
3845 Operands.push_back(ARMOperand::CreateImm(ImmVal, S, E));
3848 case AsmToken::Colon: {
3849 // ":lower16:" and ":upper16:" expression prefixes
3850 // FIXME: Check it's an expression prefix,
3851 // e.g. (FOO - :lower16:BAR) isn't legal.
3852 ARMMCExpr::VariantKind RefKind;
3853 if (parsePrefix(RefKind))
3856 const MCExpr *SubExprVal;
3857 if (getParser().ParseExpression(SubExprVal))
3860 const MCExpr *ExprVal = ARMMCExpr::Create(RefKind, SubExprVal,
3862 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
3863 Operands.push_back(ARMOperand::CreateImm(ExprVal, S, E));
3869 // parsePrefix - Parse ARM 16-bit relocations expression prefix, i.e.
3870 // :lower16: and :upper16:.
3871 bool ARMAsmParser::parsePrefix(ARMMCExpr::VariantKind &RefKind) {
3872 RefKind = ARMMCExpr::VK_ARM_None;
3874 // :lower16: and :upper16: modifiers
3875 assert(getLexer().is(AsmToken::Colon) && "expected a :");
3876 Parser.Lex(); // Eat ':'
3878 if (getLexer().isNot(AsmToken::Identifier)) {
3879 Error(Parser.getTok().getLoc(), "expected prefix identifier in operand");
3883 StringRef IDVal = Parser.getTok().getIdentifier();
3884 if (IDVal == "lower16") {
3885 RefKind = ARMMCExpr::VK_ARM_LO16;
3886 } else if (IDVal == "upper16") {
3887 RefKind = ARMMCExpr::VK_ARM_HI16;
3889 Error(Parser.getTok().getLoc(), "unexpected prefix in operand");
3894 if (getLexer().isNot(AsmToken::Colon)) {
3895 Error(Parser.getTok().getLoc(), "unexpected token after prefix");
3898 Parser.Lex(); // Eat the last ':'
3902 /// \brief Given a mnemonic, split out possible predication code and carry
3903 /// setting letters to form a canonical mnemonic and flags.
3905 // FIXME: Would be nice to autogen this.
3906 // FIXME: This is a bit of a maze of special cases.
3907 StringRef ARMAsmParser::splitMnemonic(StringRef Mnemonic,
3908 unsigned &PredicationCode,
3910 unsigned &ProcessorIMod,
3911 StringRef &ITMask) {
3912 PredicationCode = ARMCC::AL;
3913 CarrySetting = false;
3916 // Ignore some mnemonics we know aren't predicated forms.
3918 // FIXME: Would be nice to autogen this.
3919 if ((Mnemonic == "movs" && isThumb()) ||
3920 Mnemonic == "teq" || Mnemonic == "vceq" || Mnemonic == "svc" ||
3921 Mnemonic == "mls" || Mnemonic == "smmls" || Mnemonic == "vcls" ||
3922 Mnemonic == "vmls" || Mnemonic == "vnmls" || Mnemonic == "vacge" ||
3923 Mnemonic == "vcge" || Mnemonic == "vclt" || Mnemonic == "vacgt" ||
3924 Mnemonic == "vcgt" || Mnemonic == "vcle" || Mnemonic == "smlal" ||
3925 Mnemonic == "umaal" || Mnemonic == "umlal" || Mnemonic == "vabal" ||
3926 Mnemonic == "vmlal" || Mnemonic == "vpadal" || Mnemonic == "vqdmlal")
3929 // First, split out any predication code. Ignore mnemonics we know aren't
3930 // predicated but do have a carry-set and so weren't caught above.
3931 if (Mnemonic != "adcs" && Mnemonic != "bics" && Mnemonic != "movs" &&
3932 Mnemonic != "muls" && Mnemonic != "smlals" && Mnemonic != "smulls" &&
3933 Mnemonic != "umlals" && Mnemonic != "umulls" && Mnemonic != "lsls" &&
3934 Mnemonic != "sbcs" && Mnemonic != "rscs") {
3935 unsigned CC = StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2))
3936 .Case("eq", ARMCC::EQ)
3937 .Case("ne", ARMCC::NE)
3938 .Case("hs", ARMCC::HS)
3939 .Case("cs", ARMCC::HS)
3940 .Case("lo", ARMCC::LO)
3941 .Case("cc", ARMCC::LO)
3942 .Case("mi", ARMCC::MI)
3943 .Case("pl", ARMCC::PL)
3944 .Case("vs", ARMCC::VS)
3945 .Case("vc", ARMCC::VC)
3946 .Case("hi", ARMCC::HI)
3947 .Case("ls", ARMCC::LS)
3948 .Case("ge", ARMCC::GE)
3949 .Case("lt", ARMCC::LT)
3950 .Case("gt", ARMCC::GT)
3951 .Case("le", ARMCC::LE)
3952 .Case("al", ARMCC::AL)
3955 Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 2);
3956 PredicationCode = CC;
3960 // Next, determine if we have a carry setting bit. We explicitly ignore all
3961 // the instructions we know end in 's'.
3962 if (Mnemonic.endswith("s") &&
3963 !(Mnemonic == "cps" || Mnemonic == "mls" ||
3964 Mnemonic == "mrs" || Mnemonic == "smmls" || Mnemonic == "vabs" ||
3965 Mnemonic == "vcls" || Mnemonic == "vmls" || Mnemonic == "vmrs" ||
3966 Mnemonic == "vnmls" || Mnemonic == "vqabs" || Mnemonic == "vrecps" ||
3967 Mnemonic == "vrsqrts" || Mnemonic == "srs" ||
3968 (Mnemonic == "movs" && isThumb()))) {
3969 Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 1);
3970 CarrySetting = true;
3973 // The "cps" instruction can have a interrupt mode operand which is glued into
3974 // the mnemonic. Check if this is the case, split it and parse the imod op
3975 if (Mnemonic.startswith("cps")) {
3976 // Split out any imod code.
3978 StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2, 2))
3979 .Case("ie", ARM_PROC::IE)
3980 .Case("id", ARM_PROC::ID)
3983 Mnemonic = Mnemonic.slice(0, Mnemonic.size()-2);
3984 ProcessorIMod = IMod;
3988 // The "it" instruction has the condition mask on the end of the mnemonic.
3989 if (Mnemonic.startswith("it")) {
3990 ITMask = Mnemonic.slice(2, Mnemonic.size());
3991 Mnemonic = Mnemonic.slice(0, 2);
3997 /// \brief Given a canonical mnemonic, determine if the instruction ever allows
3998 /// inclusion of carry set or predication code operands.
4000 // FIXME: It would be nice to autogen this.
4002 getMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet,
4003 bool &CanAcceptPredicationCode) {
4004 if (Mnemonic == "and" || Mnemonic == "lsl" || Mnemonic == "lsr" ||
4005 Mnemonic == "rrx" || Mnemonic == "ror" || Mnemonic == "sub" ||
4006 Mnemonic == "add" || Mnemonic == "adc" ||
4007 Mnemonic == "mul" || Mnemonic == "bic" || Mnemonic == "asr" ||
4008 Mnemonic == "orr" || Mnemonic == "mvn" ||
4009 Mnemonic == "rsb" || Mnemonic == "rsc" || Mnemonic == "orn" ||
4010 Mnemonic == "sbc" || Mnemonic == "eor" || Mnemonic == "neg" ||
4011 (!isThumb() && (Mnemonic == "smull" || Mnemonic == "mov" ||
4012 Mnemonic == "mla" || Mnemonic == "smlal" ||
4013 Mnemonic == "umlal" || Mnemonic == "umull"))) {
4014 CanAcceptCarrySet = true;
4016 CanAcceptCarrySet = false;
4018 if (Mnemonic == "cbnz" || Mnemonic == "setend" || Mnemonic == "dmb" ||
4019 Mnemonic == "cps" || Mnemonic == "mcr2" || Mnemonic == "it" ||
4020 Mnemonic == "mcrr2" || Mnemonic == "cbz" || Mnemonic == "cdp2" ||
4021 Mnemonic == "trap" || Mnemonic == "mrc2" || Mnemonic == "mrrc2" ||
4022 Mnemonic == "dsb" || Mnemonic == "isb" || Mnemonic == "setend" ||
4023 (Mnemonic == "clrex" && !isThumb()) ||
4024 (Mnemonic == "nop" && isThumbOne()) ||
4025 ((Mnemonic == "pld" || Mnemonic == "pli" || Mnemonic == "pldw" ||
4026 Mnemonic == "ldc2" || Mnemonic == "ldc2l" ||
4027 Mnemonic == "stc2" || Mnemonic == "stc2l") && !isThumb()) ||
4028 ((Mnemonic.startswith("rfe") || Mnemonic.startswith("srs")) &&
4030 Mnemonic.startswith("cps") || (Mnemonic == "movs" && isThumbOne())) {
4031 CanAcceptPredicationCode = false;
4033 CanAcceptPredicationCode = true;
4036 if (Mnemonic == "bkpt" || Mnemonic == "mcr" || Mnemonic == "mcrr" ||
4037 Mnemonic == "mrc" || Mnemonic == "mrrc" || Mnemonic == "cdp")
4038 CanAcceptPredicationCode = false;
4042 bool ARMAsmParser::shouldOmitCCOutOperand(StringRef Mnemonic,
4043 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4044 // FIXME: This is all horribly hacky. We really need a better way to deal
4045 // with optional operands like this in the matcher table.
4047 // The 'mov' mnemonic is special. One variant has a cc_out operand, while
4048 // another does not. Specifically, the MOVW instruction does not. So we
4049 // special case it here and remove the defaulted (non-setting) cc_out
4050 // operand if that's the instruction we're trying to match.
4052 // We do this as post-processing of the explicit operands rather than just
4053 // conditionally adding the cc_out in the first place because we need
4054 // to check the type of the parsed immediate operand.
4055 if (Mnemonic == "mov" && Operands.size() > 4 && !isThumb() &&
4056 !static_cast<ARMOperand*>(Operands[4])->isARMSOImm() &&
4057 static_cast<ARMOperand*>(Operands[4])->isImm0_65535Expr() &&
4058 static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
4061 // Register-register 'add' for thumb does not have a cc_out operand
4062 // when there are only two register operands.
4063 if (isThumb() && Mnemonic == "add" && Operands.size() == 5 &&
4064 static_cast<ARMOperand*>(Operands[3])->isReg() &&
4065 static_cast<ARMOperand*>(Operands[4])->isReg() &&
4066 static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
4068 // Register-register 'add' for thumb does not have a cc_out operand
4069 // when it's an ADD Rdm, SP, {Rdm|#imm0_255} instruction. We do
4070 // have to check the immediate range here since Thumb2 has a variant
4071 // that can handle a different range and has a cc_out operand.
4072 if (((isThumb() && Mnemonic == "add") ||
4073 (isThumbTwo() && Mnemonic == "sub")) &&
4074 Operands.size() == 6 &&
4075 static_cast<ARMOperand*>(Operands[3])->isReg() &&
4076 static_cast<ARMOperand*>(Operands[4])->isReg() &&
4077 static_cast<ARMOperand*>(Operands[4])->getReg() == ARM::SP &&
4078 static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
4079 (static_cast<ARMOperand*>(Operands[5])->isReg() ||
4080 static_cast<ARMOperand*>(Operands[5])->isImm0_1020s4()))
4082 // For Thumb2, add/sub immediate does not have a cc_out operand for the
4083 // imm0_4095 variant. That's the least-preferred variant when
4084 // selecting via the generic "add" mnemonic, so to know that we
4085 // should remove the cc_out operand, we have to explicitly check that
4086 // it's not one of the other variants. Ugh.
4087 if (isThumbTwo() && (Mnemonic == "add" || Mnemonic == "sub") &&
4088 Operands.size() == 6 &&
4089 static_cast<ARMOperand*>(Operands[3])->isReg() &&
4090 static_cast<ARMOperand*>(Operands[4])->isReg() &&
4091 static_cast<ARMOperand*>(Operands[5])->isImm()) {
4092 // Nest conditions rather than one big 'if' statement for readability.
4094 // If either register is a high reg, it's either one of the SP
4095 // variants (handled above) or a 32-bit encoding, so we just
4096 // check against T3.
4097 if ((!isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) ||
4098 !isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg())) &&
4099 static_cast<ARMOperand*>(Operands[5])->isT2SOImm())
4101 // If both registers are low, we're in an IT block, and the immediate is
4102 // in range, we should use encoding T1 instead, which has a cc_out.
4104 isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) &&
4105 isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) &&
4106 static_cast<ARMOperand*>(Operands[5])->isImm0_7())
4109 // Otherwise, we use encoding T4, which does not have a cc_out
4114 // The thumb2 multiply instruction doesn't have a CCOut register, so
4115 // if we have a "mul" mnemonic in Thumb mode, check if we'll be able to
4116 // use the 16-bit encoding or not.
4117 if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 6 &&
4118 static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
4119 static_cast<ARMOperand*>(Operands[3])->isReg() &&
4120 static_cast<ARMOperand*>(Operands[4])->isReg() &&
4121 static_cast<ARMOperand*>(Operands[5])->isReg() &&
4122 // If the registers aren't low regs, the destination reg isn't the
4123 // same as one of the source regs, or the cc_out operand is zero
4124 // outside of an IT block, we have to use the 32-bit encoding, so
4125 // remove the cc_out operand.
4126 (!isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) ||
4127 !isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) ||
4129 (static_cast<ARMOperand*>(Operands[3])->getReg() !=
4130 static_cast<ARMOperand*>(Operands[5])->getReg() &&
4131 static_cast<ARMOperand*>(Operands[3])->getReg() !=
4132 static_cast<ARMOperand*>(Operands[4])->getReg())))
4137 // Register-register 'add/sub' for thumb does not have a cc_out operand
4138 // when it's an ADD/SUB SP, #imm. Be lenient on count since there's also
4139 // the "add/sub SP, SP, #imm" version. If the follow-up operands aren't
4140 // right, this will result in better diagnostics (which operand is off)
4142 if (isThumb() && (Mnemonic == "add" || Mnemonic == "sub") &&
4143 (Operands.size() == 5 || Operands.size() == 6) &&
4144 static_cast<ARMOperand*>(Operands[3])->isReg() &&
4145 static_cast<ARMOperand*>(Operands[3])->getReg() == ARM::SP &&
4146 static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
4152 /// Parse an arm instruction mnemonic followed by its operands.
4153 bool ARMAsmParser::ParseInstruction(StringRef Name, SMLoc NameLoc,
4154 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4155 // Create the leading tokens for the mnemonic, split by '.' characters.
4156 size_t Start = 0, Next = Name.find('.');
4157 StringRef Mnemonic = Name.slice(Start, Next);
4159 // Split out the predication code and carry setting flag from the mnemonic.
4160 unsigned PredicationCode;
4161 unsigned ProcessorIMod;
4164 Mnemonic = splitMnemonic(Mnemonic, PredicationCode, CarrySetting,
4165 ProcessorIMod, ITMask);
4167 // In Thumb1, only the branch (B) instruction can be predicated.
4168 if (isThumbOne() && PredicationCode != ARMCC::AL && Mnemonic != "b") {
4169 Parser.EatToEndOfStatement();
4170 return Error(NameLoc, "conditional execution not supported in Thumb1");
4173 Operands.push_back(ARMOperand::CreateToken(Mnemonic, NameLoc));
4175 // Handle the IT instruction ITMask. Convert it to a bitmask. This
4176 // is the mask as it will be for the IT encoding if the conditional
4177 // encoding has a '1' as it's bit0 (i.e. 't' ==> '1'). In the case
4178 // where the conditional bit0 is zero, the instruction post-processing
4179 // will adjust the mask accordingly.
4180 if (Mnemonic == "it") {
4181 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + 2);
4182 if (ITMask.size() > 3) {
4183 Parser.EatToEndOfStatement();
4184 return Error(Loc, "too many conditions on IT instruction");
4187 for (unsigned i = ITMask.size(); i != 0; --i) {
4188 char pos = ITMask[i - 1];
4189 if (pos != 't' && pos != 'e') {
4190 Parser.EatToEndOfStatement();
4191 return Error(Loc, "illegal IT block condition mask '" + ITMask + "'");
4194 if (ITMask[i - 1] == 't')
4197 Operands.push_back(ARMOperand::CreateITMask(Mask, Loc));
4200 // FIXME: This is all a pretty gross hack. We should automatically handle
4201 // optional operands like this via tblgen.
4203 // Next, add the CCOut and ConditionCode operands, if needed.
4205 // For mnemonics which can ever incorporate a carry setting bit or predication
4206 // code, our matching model involves us always generating CCOut and
4207 // ConditionCode operands to match the mnemonic "as written" and then we let
4208 // the matcher deal with finding the right instruction or generating an
4209 // appropriate error.
4210 bool CanAcceptCarrySet, CanAcceptPredicationCode;
4211 getMnemonicAcceptInfo(Mnemonic, CanAcceptCarrySet, CanAcceptPredicationCode);
4213 // If we had a carry-set on an instruction that can't do that, issue an
4215 if (!CanAcceptCarrySet && CarrySetting) {
4216 Parser.EatToEndOfStatement();
4217 return Error(NameLoc, "instruction '" + Mnemonic +
4218 "' can not set flags, but 's' suffix specified");
4220 // If we had a predication code on an instruction that can't do that, issue an
4222 if (!CanAcceptPredicationCode && PredicationCode != ARMCC::AL) {
4223 Parser.EatToEndOfStatement();
4224 return Error(NameLoc, "instruction '" + Mnemonic +
4225 "' is not predicable, but condition code specified");
4228 // Add the carry setting operand, if necessary.
4229 if (CanAcceptCarrySet) {
4230 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size());
4231 Operands.push_back(ARMOperand::CreateCCOut(CarrySetting ? ARM::CPSR : 0,
4235 // Add the predication code operand, if necessary.
4236 if (CanAcceptPredicationCode) {
4237 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size() +
4239 Operands.push_back(ARMOperand::CreateCondCode(
4240 ARMCC::CondCodes(PredicationCode), Loc));
4243 // Add the processor imod operand, if necessary.
4244 if (ProcessorIMod) {
4245 Operands.push_back(ARMOperand::CreateImm(
4246 MCConstantExpr::Create(ProcessorIMod, getContext()),
4250 // Add the remaining tokens in the mnemonic.
4251 while (Next != StringRef::npos) {
4253 Next = Name.find('.', Start + 1);
4254 StringRef ExtraToken = Name.slice(Start, Next);
4256 // For now, we're only parsing Thumb1 (for the most part), so
4257 // just ignore ".n" qualifiers. We'll use them to restrict
4258 // matching when we do Thumb2.
4259 if (ExtraToken != ".n") {
4260 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Start);
4261 Operands.push_back(ARMOperand::CreateToken(ExtraToken, Loc));
4265 // Read the remaining operands.
4266 if (getLexer().isNot(AsmToken::EndOfStatement)) {
4267 // Read the first operand.
4268 if (parseOperand(Operands, Mnemonic)) {
4269 Parser.EatToEndOfStatement();
4273 while (getLexer().is(AsmToken::Comma)) {
4274 Parser.Lex(); // Eat the comma.
4276 // Parse and remember the operand.
4277 if (parseOperand(Operands, Mnemonic)) {
4278 Parser.EatToEndOfStatement();
4284 if (getLexer().isNot(AsmToken::EndOfStatement)) {
4285 SMLoc Loc = getLexer().getLoc();
4286 Parser.EatToEndOfStatement();
4287 return Error(Loc, "unexpected token in argument list");
4290 Parser.Lex(); // Consume the EndOfStatement
4292 // Some instructions, mostly Thumb, have forms for the same mnemonic that
4293 // do and don't have a cc_out optional-def operand. With some spot-checks
4294 // of the operand list, we can figure out which variant we're trying to
4295 // parse and adjust accordingly before actually matching. We shouldn't ever
4296 // try to remove a cc_out operand that was explicitly set on the the
4297 // mnemonic, of course (CarrySetting == true). Reason number #317 the
4298 // table driven matcher doesn't fit well with the ARM instruction set.
4299 if (!CarrySetting && shouldOmitCCOutOperand(Mnemonic, Operands)) {
4300 ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]);
4301 Operands.erase(Operands.begin() + 1);
4305 // ARM mode 'blx' need special handling, as the register operand version
4306 // is predicable, but the label operand version is not. So, we can't rely
4307 // on the Mnemonic based checking to correctly figure out when to put
4308 // a k_CondCode operand in the list. If we're trying to match the label
4309 // version, remove the k_CondCode operand here.
4310 if (!isThumb() && Mnemonic == "blx" && Operands.size() == 3 &&
4311 static_cast<ARMOperand*>(Operands[2])->isImm()) {
4312 ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]);
4313 Operands.erase(Operands.begin() + 1);
4317 // The vector-compare-to-zero instructions have a literal token "#0" at
4318 // the end that comes to here as an immediate operand. Convert it to a
4319 // token to play nicely with the matcher.
4320 if ((Mnemonic == "vceq" || Mnemonic == "vcge" || Mnemonic == "vcgt" ||
4321 Mnemonic == "vcle" || Mnemonic == "vclt") && Operands.size() == 6 &&
4322 static_cast<ARMOperand*>(Operands[5])->isImm()) {
4323 ARMOperand *Op = static_cast<ARMOperand*>(Operands[5]);
4324 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op->getImm());
4325 if (CE && CE->getValue() == 0) {
4326 Operands.erase(Operands.begin() + 5);
4327 Operands.push_back(ARMOperand::CreateToken("#0", Op->getStartLoc()));
4331 // VCMP{E} does the same thing, but with a different operand count.
4332 if ((Mnemonic == "vcmp" || Mnemonic == "vcmpe") && Operands.size() == 5 &&
4333 static_cast<ARMOperand*>(Operands[4])->isImm()) {
4334 ARMOperand *Op = static_cast<ARMOperand*>(Operands[4]);
4335 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op->getImm());
4336 if (CE && CE->getValue() == 0) {
4337 Operands.erase(Operands.begin() + 4);
4338 Operands.push_back(ARMOperand::CreateToken("#0", Op->getStartLoc()));
4342 // Similarly, the Thumb1 "RSB" instruction has a literal "#0" on the
4343 // end. Convert it to a token here.
4344 if (Mnemonic == "rsb" && isThumb() && Operands.size() == 6 &&
4345 static_cast<ARMOperand*>(Operands[5])->isImm()) {
4346 ARMOperand *Op = static_cast<ARMOperand*>(Operands[5]);
4347 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op->getImm());
4348 if (CE && CE->getValue() == 0) {
4349 Operands.erase(Operands.begin() + 5);
4350 Operands.push_back(ARMOperand::CreateToken("#0", Op->getStartLoc()));
4358 // Validate context-sensitive operand constraints.
4360 // return 'true' if register list contains non-low GPR registers,
4361 // 'false' otherwise. If Reg is in the register list or is HiReg, set
4362 // 'containsReg' to true.
4363 static bool checkLowRegisterList(MCInst Inst, unsigned OpNo, unsigned Reg,
4364 unsigned HiReg, bool &containsReg) {
4365 containsReg = false;
4366 for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) {
4367 unsigned OpReg = Inst.getOperand(i).getReg();
4370 // Anything other than a low register isn't legal here.
4371 if (!isARMLowRegister(OpReg) && (!HiReg || OpReg != HiReg))
4377 // Check if the specified regisgter is in the register list of the inst,
4378 // starting at the indicated operand number.
4379 static bool listContainsReg(MCInst &Inst, unsigned OpNo, unsigned Reg) {
4380 for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) {
4381 unsigned OpReg = Inst.getOperand(i).getReg();
4388 // FIXME: We would really prefer to have MCInstrInfo (the wrapper around
4389 // the ARMInsts array) instead. Getting that here requires awkward
4390 // API changes, though. Better way?
4392 extern const MCInstrDesc ARMInsts[];
4394 static const MCInstrDesc &getInstDesc(unsigned Opcode) {
4395 return ARMInsts[Opcode];
4398 // FIXME: We would really like to be able to tablegen'erate this.
4400 validateInstruction(MCInst &Inst,
4401 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4402 const MCInstrDesc &MCID = getInstDesc(Inst.getOpcode());
4403 SMLoc Loc = Operands[0]->getStartLoc();
4404 // Check the IT block state first.
4405 // NOTE: In Thumb mode, the BKPT instruction has the interesting property of
4406 // being allowed in IT blocks, but not being predicable. It just always
4408 if (inITBlock() && Inst.getOpcode() != ARM::tBKPT) {
4410 if (ITState.FirstCond)
4411 ITState.FirstCond = false;
4413 bit = (ITState.Mask >> (5 - ITState.CurPosition)) & 1;
4414 // The instruction must be predicable.
4415 if (!MCID.isPredicable())
4416 return Error(Loc, "instructions in IT block must be predicable");
4417 unsigned Cond = Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm();
4418 unsigned ITCond = bit ? ITState.Cond :
4419 ARMCC::getOppositeCondition(ITState.Cond);
4420 if (Cond != ITCond) {
4421 // Find the condition code Operand to get its SMLoc information.
4423 for (unsigned i = 1; i < Operands.size(); ++i)
4424 if (static_cast<ARMOperand*>(Operands[i])->isCondCode())
4425 CondLoc = Operands[i]->getStartLoc();
4426 return Error(CondLoc, "incorrect condition in IT block; got '" +
4427 StringRef(ARMCondCodeToString(ARMCC::CondCodes(Cond))) +
4428 "', but expected '" +
4429 ARMCondCodeToString(ARMCC::CondCodes(ITCond)) + "'");
4431 // Check for non-'al' condition codes outside of the IT block.
4432 } else if (isThumbTwo() && MCID.isPredicable() &&
4433 Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm() !=
4434 ARMCC::AL && Inst.getOpcode() != ARM::tB &&
4435 Inst.getOpcode() != ARM::t2B)
4436 return Error(Loc, "predicated instructions must be in IT block");
4438 switch (Inst.getOpcode()) {
4441 case ARM::LDRD_POST:
4443 // Rt2 must be Rt + 1.
4444 unsigned Rt = getARMRegisterNumbering(Inst.getOperand(0).getReg());
4445 unsigned Rt2 = getARMRegisterNumbering(Inst.getOperand(1).getReg());
4447 return Error(Operands[3]->getStartLoc(),
4448 "destination operands must be sequential");
4452 // Rt2 must be Rt + 1.
4453 unsigned Rt = getARMRegisterNumbering(Inst.getOperand(0).getReg());
4454 unsigned Rt2 = getARMRegisterNumbering(Inst.getOperand(1).getReg());
4456 return Error(Operands[3]->getStartLoc(),
4457 "source operands must be sequential");
4461 case ARM::STRD_POST:
4463 // Rt2 must be Rt + 1.
4464 unsigned Rt = getARMRegisterNumbering(Inst.getOperand(1).getReg());
4465 unsigned Rt2 = getARMRegisterNumbering(Inst.getOperand(2).getReg());
4467 return Error(Operands[3]->getStartLoc(),
4468 "source operands must be sequential");
4473 // width must be in range [1, 32-lsb]
4474 unsigned lsb = Inst.getOperand(2).getImm();
4475 unsigned widthm1 = Inst.getOperand(3).getImm();
4476 if (widthm1 >= 32 - lsb)
4477 return Error(Operands[5]->getStartLoc(),
4478 "bitfield width must be in range [1,32-lsb]");
4482 // If we're parsing Thumb2, the .w variant is available and handles
4483 // most cases that are normally illegal for a Thumb1 LDM
4484 // instruction. We'll make the transformation in processInstruction()
4487 // Thumb LDM instructions are writeback iff the base register is not
4488 // in the register list.
4489 unsigned Rn = Inst.getOperand(0).getReg();
4490 bool hasWritebackToken =
4491 (static_cast<ARMOperand*>(Operands[3])->isToken() &&
4492 static_cast<ARMOperand*>(Operands[3])->getToken() == "!");
4493 bool listContainsBase;
4494 if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase) && !isThumbTwo())
4495 return Error(Operands[3 + hasWritebackToken]->getStartLoc(),
4496 "registers must be in range r0-r7");
4497 // If we should have writeback, then there should be a '!' token.
4498 if (!listContainsBase && !hasWritebackToken && !isThumbTwo())
4499 return Error(Operands[2]->getStartLoc(),
4500 "writeback operator '!' expected");
4501 // If we should not have writeback, there must not be a '!'. This is
4502 // true even for the 32-bit wide encodings.
4503 if (listContainsBase && hasWritebackToken)
4504 return Error(Operands[3]->getStartLoc(),
4505 "writeback operator '!' not allowed when base register "
4506 "in register list");
4510 case ARM::t2LDMIA_UPD: {
4511 if (listContainsReg(Inst, 3, Inst.getOperand(0).getReg()))
4512 return Error(Operands[4]->getStartLoc(),
4513 "writeback operator '!' not allowed when base register "
4514 "in register list");
4518 bool listContainsBase;
4519 if (checkLowRegisterList(Inst, 3, 0, ARM::PC, listContainsBase))
4520 return Error(Operands[2]->getStartLoc(),
4521 "registers must be in range r0-r7 or pc");
4525 bool listContainsBase;
4526 if (checkLowRegisterList(Inst, 3, 0, ARM::LR, listContainsBase))
4527 return Error(Operands[2]->getStartLoc(),
4528 "registers must be in range r0-r7 or lr");
4531 case ARM::tSTMIA_UPD: {
4532 bool listContainsBase;
4533 if (checkLowRegisterList(Inst, 4, 0, 0, listContainsBase) && !isThumbTwo())
4534 return Error(Operands[4]->getStartLoc(),
4535 "registers must be in range r0-r7");
4544 processInstruction(MCInst &Inst,
4545 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4546 switch (Inst.getOpcode()) {
4547 case ARM::LDMIA_UPD:
4548 // If this is a load of a single register via a 'pop', then we should use
4549 // a post-indexed LDR instruction instead, per the ARM ARM.
4550 if (static_cast<ARMOperand*>(Operands[0])->getToken() == "pop" &&
4551 Inst.getNumOperands() == 5) {
4553 TmpInst.setOpcode(ARM::LDR_POST_IMM);
4554 TmpInst.addOperand(Inst.getOperand(4)); // Rt
4555 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
4556 TmpInst.addOperand(Inst.getOperand(1)); // Rn
4557 TmpInst.addOperand(MCOperand::CreateReg(0)); // am2offset
4558 TmpInst.addOperand(MCOperand::CreateImm(4));
4559 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
4560 TmpInst.addOperand(Inst.getOperand(3));
4564 case ARM::STMDB_UPD:
4565 // If this is a store of a single register via a 'push', then we should use
4566 // a pre-indexed STR instruction instead, per the ARM ARM.
4567 if (static_cast<ARMOperand*>(Operands[0])->getToken() == "push" &&
4568 Inst.getNumOperands() == 5) {
4570 TmpInst.setOpcode(ARM::STR_PRE_IMM);
4571 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
4572 TmpInst.addOperand(Inst.getOperand(4)); // Rt
4573 TmpInst.addOperand(Inst.getOperand(1)); // addrmode_imm12
4574 TmpInst.addOperand(MCOperand::CreateImm(-4));
4575 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
4576 TmpInst.addOperand(Inst.getOperand(3));
4581 // If the immediate is in the range 0-7, we want tADDi3 iff Rd was
4582 // explicitly specified. From the ARM ARM: "Encoding T1 is preferred
4583 // to encoding T2 if <Rd> is specified and encoding T2 is preferred
4584 // to encoding T1 if <Rd> is omitted."
4585 if (Inst.getOperand(3).getImm() < 8 && Operands.size() == 6)
4586 Inst.setOpcode(ARM::tADDi3);
4589 // If the immediate is in the range 0-7, we want tADDi3 iff Rd was
4590 // explicitly specified. From the ARM ARM: "Encoding T1 is preferred
4591 // to encoding T2 if <Rd> is specified and encoding T2 is preferred
4592 // to encoding T1 if <Rd> is omitted."
4593 if (Inst.getOperand(3).getImm() < 8 && Operands.size() == 6)
4594 Inst.setOpcode(ARM::tSUBi3);
4597 // A Thumb conditional branch outside of an IT block is a tBcc.
4598 if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock())
4599 Inst.setOpcode(ARM::tBcc);
4602 // A Thumb2 conditional branch outside of an IT block is a t2Bcc.
4603 if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock())
4604 Inst.setOpcode(ARM::t2Bcc);
4607 // If the conditional is AL or we're in an IT block, we really want t2B.
4608 if (Inst.getOperand(1).getImm() == ARMCC::AL || inITBlock())
4609 Inst.setOpcode(ARM::t2B);
4612 // If the conditional is AL, we really want tB.
4613 if (Inst.getOperand(1).getImm() == ARMCC::AL)
4614 Inst.setOpcode(ARM::tB);
4617 // If the register list contains any high registers, or if the writeback
4618 // doesn't match what tLDMIA can do, we need to use the 32-bit encoding
4619 // instead if we're in Thumb2. Otherwise, this should have generated
4620 // an error in validateInstruction().
4621 unsigned Rn = Inst.getOperand(0).getReg();
4622 bool hasWritebackToken =
4623 (static_cast<ARMOperand*>(Operands[3])->isToken() &&
4624 static_cast<ARMOperand*>(Operands[3])->getToken() == "!");
4625 bool listContainsBase;
4626 if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase) ||
4627 (!listContainsBase && !hasWritebackToken) ||
4628 (listContainsBase && hasWritebackToken)) {
4629 // 16-bit encoding isn't sufficient. Switch to the 32-bit version.
4630 assert (isThumbTwo());
4631 Inst.setOpcode(hasWritebackToken ? ARM::t2LDMIA_UPD : ARM::t2LDMIA);
4632 // If we're switching to the updating version, we need to insert
4633 // the writeback tied operand.
4634 if (hasWritebackToken)
4635 Inst.insert(Inst.begin(),
4636 MCOperand::CreateReg(Inst.getOperand(0).getReg()));
4640 case ARM::tSTMIA_UPD: {
4641 // If the register list contains any high registers, we need to use
4642 // the 32-bit encoding instead if we're in Thumb2. Otherwise, this
4643 // should have generated an error in validateInstruction().
4644 unsigned Rn = Inst.getOperand(0).getReg();
4645 bool listContainsBase;
4646 if (checkLowRegisterList(Inst, 4, Rn, 0, listContainsBase)) {
4647 // 16-bit encoding isn't sufficient. Switch to the 32-bit version.
4648 assert (isThumbTwo());
4649 Inst.setOpcode(ARM::t2STMIA_UPD);
4654 // If we can use the 16-bit encoding and the user didn't explicitly
4655 // request the 32-bit variant, transform it here.
4656 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
4657 Inst.getOperand(1).getImm() <= 255 &&
4658 ((!inITBlock() && Inst.getOperand(2).getImm() == ARMCC::AL &&
4659 Inst.getOperand(4).getReg() == ARM::CPSR) ||
4660 (inITBlock() && Inst.getOperand(4).getReg() == 0)) &&
4661 (!static_cast<ARMOperand*>(Operands[2])->isToken() ||
4662 static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) {
4663 // The operands aren't in the same order for tMOVi8...
4665 TmpInst.setOpcode(ARM::tMOVi8);
4666 TmpInst.addOperand(Inst.getOperand(0));
4667 TmpInst.addOperand(Inst.getOperand(4));
4668 TmpInst.addOperand(Inst.getOperand(1));
4669 TmpInst.addOperand(Inst.getOperand(2));
4670 TmpInst.addOperand(Inst.getOperand(3));
4676 // If we can use the 16-bit encoding and the user didn't explicitly
4677 // request the 32-bit variant, transform it here.
4678 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
4679 isARMLowRegister(Inst.getOperand(1).getReg()) &&
4680 Inst.getOperand(2).getImm() == ARMCC::AL &&
4681 Inst.getOperand(4).getReg() == ARM::CPSR &&
4682 (!static_cast<ARMOperand*>(Operands[2])->isToken() ||
4683 static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) {
4684 // The operands aren't the same for tMOV[S]r... (no cc_out)
4686 TmpInst.setOpcode(Inst.getOperand(4).getReg() ? ARM::tMOVSr : ARM::tMOVr);
4687 TmpInst.addOperand(Inst.getOperand(0));
4688 TmpInst.addOperand(Inst.getOperand(1));
4689 TmpInst.addOperand(Inst.getOperand(2));
4690 TmpInst.addOperand(Inst.getOperand(3));
4699 // If we can use the 16-bit encoding and the user didn't explicitly
4700 // request the 32-bit variant, transform it here.
4701 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
4702 isARMLowRegister(Inst.getOperand(1).getReg()) &&
4703 Inst.getOperand(2).getImm() == 0 &&
4704 (!static_cast<ARMOperand*>(Operands[2])->isToken() ||
4705 static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) {
4707 switch (Inst.getOpcode()) {
4708 default: llvm_unreachable("Illegal opcode!");
4709 case ARM::t2SXTH: NewOpc = ARM::tSXTH; break;
4710 case ARM::t2SXTB: NewOpc = ARM::tSXTB; break;
4711 case ARM::t2UXTH: NewOpc = ARM::tUXTH; break;
4712 case ARM::t2UXTB: NewOpc = ARM::tUXTB; break;
4714 // The operands aren't the same for thumb1 (no rotate operand).
4716 TmpInst.setOpcode(NewOpc);
4717 TmpInst.addOperand(Inst.getOperand(0));
4718 TmpInst.addOperand(Inst.getOperand(1));
4719 TmpInst.addOperand(Inst.getOperand(3));
4720 TmpInst.addOperand(Inst.getOperand(4));
4726 // The mask bits for all but the first condition are represented as
4727 // the low bit of the condition code value implies 't'. We currently
4728 // always have 1 implies 't', so XOR toggle the bits if the low bit
4729 // of the condition code is zero. The encoding also expects the low
4730 // bit of the condition to be encoded as bit 4 of the mask operand,
4731 // so mask that in if needed
4732 MCOperand &MO = Inst.getOperand(1);
4733 unsigned Mask = MO.getImm();
4734 unsigned OrigMask = Mask;
4735 unsigned TZ = CountTrailingZeros_32(Mask);
4736 if ((Inst.getOperand(0).getImm() & 1) == 0) {
4737 assert(Mask && TZ <= 3 && "illegal IT mask value!");
4738 for (unsigned i = 3; i != TZ; --i)
4744 // Set up the IT block state according to the IT instruction we just
4746 assert(!inITBlock() && "nested IT blocks?!");
4747 ITState.Cond = ARMCC::CondCodes(Inst.getOperand(0).getImm());
4748 ITState.Mask = OrigMask; // Use the original mask, not the updated one.
4749 ITState.CurPosition = 0;
4750 ITState.FirstCond = true;
4756 unsigned ARMAsmParser::checkTargetMatchPredicate(MCInst &Inst) {
4757 // 16-bit thumb arithmetic instructions either require or preclude the 'S'
4758 // suffix depending on whether they're in an IT block or not.
4759 unsigned Opc = Inst.getOpcode();
4760 const MCInstrDesc &MCID = getInstDesc(Opc);
4761 if (MCID.TSFlags & ARMII::ThumbArithFlagSetting) {
4762 assert(MCID.hasOptionalDef() &&
4763 "optionally flag setting instruction missing optional def operand");
4764 assert(MCID.NumOperands == Inst.getNumOperands() &&
4765 "operand count mismatch!");
4766 // Find the optional-def operand (cc_out).
4769 !MCID.OpInfo[OpNo].isOptionalDef() && OpNo < MCID.NumOperands;
4772 // If we're parsing Thumb1, reject it completely.
4773 if (isThumbOne() && Inst.getOperand(OpNo).getReg() != ARM::CPSR)
4774 return Match_MnemonicFail;
4775 // If we're parsing Thumb2, which form is legal depends on whether we're
4777 if (isThumbTwo() && Inst.getOperand(OpNo).getReg() != ARM::CPSR &&
4779 return Match_RequiresITBlock;
4780 if (isThumbTwo() && Inst.getOperand(OpNo).getReg() == ARM::CPSR &&
4782 return Match_RequiresNotITBlock;
4784 // Some high-register supporting Thumb1 encodings only allow both registers
4785 // to be from r0-r7 when in Thumb2.
4786 else if (Opc == ARM::tADDhirr && isThumbOne() &&
4787 isARMLowRegister(Inst.getOperand(1).getReg()) &&
4788 isARMLowRegister(Inst.getOperand(2).getReg()))
4789 return Match_RequiresThumb2;
4790 // Others only require ARMv6 or later.
4791 else if (Opc == ARM::tMOVr && isThumbOne() && !hasV6Ops() &&
4792 isARMLowRegister(Inst.getOperand(0).getReg()) &&
4793 isARMLowRegister(Inst.getOperand(1).getReg()))
4794 return Match_RequiresV6;
4795 return Match_Success;
4799 MatchAndEmitInstruction(SMLoc IDLoc,
4800 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
4804 unsigned MatchResult;
4805 MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo);
4806 switch (MatchResult) {
4809 // Context sensitive operand constraints aren't handled by the matcher,
4810 // so check them here.
4811 if (validateInstruction(Inst, Operands)) {
4812 // Still progress the IT block, otherwise one wrong condition causes
4813 // nasty cascading errors.
4814 forwardITPosition();
4818 // Some instructions need post-processing to, for example, tweak which
4819 // encoding is selected.
4820 processInstruction(Inst, Operands);
4822 // Only move forward at the very end so that everything in validate
4823 // and process gets a consistent answer about whether we're in an IT
4825 forwardITPosition();
4827 Out.EmitInstruction(Inst);
4829 case Match_MissingFeature:
4830 Error(IDLoc, "instruction requires a CPU feature not currently enabled");
4832 case Match_InvalidOperand: {
4833 SMLoc ErrorLoc = IDLoc;
4834 if (ErrorInfo != ~0U) {
4835 if (ErrorInfo >= Operands.size())
4836 return Error(IDLoc, "too few operands for instruction");
4838 ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc();
4839 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
4842 return Error(ErrorLoc, "invalid operand for instruction");
4844 case Match_MnemonicFail:
4845 return Error(IDLoc, "invalid instruction");
4846 case Match_ConversionFail:
4847 // The converter function will have already emited a diagnostic.
4849 case Match_RequiresNotITBlock:
4850 return Error(IDLoc, "flag setting instruction only valid outside IT block");
4851 case Match_RequiresITBlock:
4852 return Error(IDLoc, "instruction only valid inside IT block");
4853 case Match_RequiresV6:
4854 return Error(IDLoc, "instruction variant requires ARMv6 or later");
4855 case Match_RequiresThumb2:
4856 return Error(IDLoc, "instruction variant requires Thumb2");
4859 llvm_unreachable("Implement any new match types added!");
4863 /// parseDirective parses the arm specific directives
4864 bool ARMAsmParser::ParseDirective(AsmToken DirectiveID) {
4865 StringRef IDVal = DirectiveID.getIdentifier();
4866 if (IDVal == ".word")
4867 return parseDirectiveWord(4, DirectiveID.getLoc());
4868 else if (IDVal == ".thumb")
4869 return parseDirectiveThumb(DirectiveID.getLoc());
4870 else if (IDVal == ".thumb_func")
4871 return parseDirectiveThumbFunc(DirectiveID.getLoc());
4872 else if (IDVal == ".code")
4873 return parseDirectiveCode(DirectiveID.getLoc());
4874 else if (IDVal == ".syntax")
4875 return parseDirectiveSyntax(DirectiveID.getLoc());
4879 /// parseDirectiveWord
4880 /// ::= .word [ expression (, expression)* ]
4881 bool ARMAsmParser::parseDirectiveWord(unsigned Size, SMLoc L) {
4882 if (getLexer().isNot(AsmToken::EndOfStatement)) {
4884 const MCExpr *Value;
4885 if (getParser().ParseExpression(Value))
4888 getParser().getStreamer().EmitValue(Value, Size, 0/*addrspace*/);
4890 if (getLexer().is(AsmToken::EndOfStatement))
4893 // FIXME: Improve diagnostic.
4894 if (getLexer().isNot(AsmToken::Comma))
4895 return Error(L, "unexpected token in directive");
4904 /// parseDirectiveThumb
4906 bool ARMAsmParser::parseDirectiveThumb(SMLoc L) {
4907 if (getLexer().isNot(AsmToken::EndOfStatement))
4908 return Error(L, "unexpected token in directive");
4911 // TODO: set thumb mode
4912 // TODO: tell the MC streamer the mode
4913 // getParser().getStreamer().Emit???();
4917 /// parseDirectiveThumbFunc
4918 /// ::= .thumbfunc symbol_name
4919 bool ARMAsmParser::parseDirectiveThumbFunc(SMLoc L) {
4920 const MCAsmInfo &MAI = getParser().getStreamer().getContext().getAsmInfo();
4921 bool isMachO = MAI.hasSubsectionsViaSymbols();
4924 // Darwin asm has function name after .thumb_func direction
4927 const AsmToken &Tok = Parser.getTok();
4928 if (Tok.isNot(AsmToken::Identifier) && Tok.isNot(AsmToken::String))
4929 return Error(L, "unexpected token in .thumb_func directive");
4930 Name = Tok.getString();
4931 Parser.Lex(); // Consume the identifier token.
4934 if (getLexer().isNot(AsmToken::EndOfStatement))
4935 return Error(L, "unexpected token in directive");
4938 // FIXME: assuming function name will be the line following .thumb_func
4940 Name = Parser.getTok().getString();
4943 // Mark symbol as a thumb symbol.
4944 MCSymbol *Func = getParser().getContext().GetOrCreateSymbol(Name);
4945 getParser().getStreamer().EmitThumbFunc(Func);
4949 /// parseDirectiveSyntax
4950 /// ::= .syntax unified | divided
4951 bool ARMAsmParser::parseDirectiveSyntax(SMLoc L) {
4952 const AsmToken &Tok = Parser.getTok();
4953 if (Tok.isNot(AsmToken::Identifier))
4954 return Error(L, "unexpected token in .syntax directive");
4955 StringRef Mode = Tok.getString();
4956 if (Mode == "unified" || Mode == "UNIFIED")
4958 else if (Mode == "divided" || Mode == "DIVIDED")
4959 return Error(L, "'.syntax divided' arm asssembly not supported");
4961 return Error(L, "unrecognized syntax mode in .syntax directive");
4963 if (getLexer().isNot(AsmToken::EndOfStatement))
4964 return Error(Parser.getTok().getLoc(), "unexpected token in directive");
4967 // TODO tell the MC streamer the mode
4968 // getParser().getStreamer().Emit???();
4972 /// parseDirectiveCode
4973 /// ::= .code 16 | 32
4974 bool ARMAsmParser::parseDirectiveCode(SMLoc L) {
4975 const AsmToken &Tok = Parser.getTok();
4976 if (Tok.isNot(AsmToken::Integer))
4977 return Error(L, "unexpected token in .code directive");
4978 int64_t Val = Parser.getTok().getIntVal();
4984 return Error(L, "invalid operand to .code directive");
4986 if (getLexer().isNot(AsmToken::EndOfStatement))
4987 return Error(Parser.getTok().getLoc(), "unexpected token in directive");
4993 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
4997 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
5003 extern "C" void LLVMInitializeARMAsmLexer();
5005 /// Force static initialization.
5006 extern "C" void LLVMInitializeARMAsmParser() {
5007 RegisterMCAsmParser<ARMAsmParser> X(TheARMTarget);
5008 RegisterMCAsmParser<ARMAsmParser> Y(TheThumbTarget);
5009 LLVMInitializeARMAsmLexer();
5012 #define GET_REGISTER_MATCHER
5013 #define GET_MATCHER_IMPLEMENTATION
5014 #include "ARMGenAsmMatcher.inc"