1 //===-- ARMTargetMachine.h - Define TargetMachine for ARM -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file declares the ARM specific subclass of TargetMachine.
12 //===----------------------------------------------------------------------===//
14 #ifndef ARMTARGETMACHINE_H
15 #define ARMTARGETMACHINE_H
17 #include "llvm/Target/TargetMachine.h"
18 #include "llvm/Target/TargetData.h"
19 #include "llvm/MC/MCStreamer.h"
20 #include "ARMInstrInfo.h"
21 #include "ARMELFWriterInfo.h"
22 #include "ARMFrameInfo.h"
23 #include "ARMJITInfo.h"
24 #include "ARMSubtarget.h"
25 #include "ARMISelLowering.h"
26 #include "ARMSelectionDAGInfo.h"
27 #include "Thumb1InstrInfo.h"
28 #include "Thumb2InstrInfo.h"
29 #include "llvm/ADT/OwningPtr.h"
33 class ARMBaseTargetMachine : public LLVMTargetMachine {
35 ARMSubtarget Subtarget;
38 ARMFrameInfo FrameInfo;
40 InstrItineraryData InstrItins;
41 Reloc::Model DefRelocModel; // Reloc model before it's overridden.
44 const TargetData DataLayout; // Calculates type size & alignment
45 ARMELFWriterInfo ELFWriterInfo;
48 ARMBaseTargetMachine(const Target &T, const std::string &TT,
49 const std::string &FS, bool isThumb);
51 virtual const TargetData *getTargetData() const { return &DataLayout; }
52 virtual const ARMELFWriterInfo *getELFWriterInfo() const {
53 return Subtarget.isTargetELF() ? &ELFWriterInfo : 0;
56 virtual const ARMFrameInfo *getFrameInfo() const { return &FrameInfo; }
57 virtual ARMJITInfo *getJITInfo() { return &JITInfo; }
58 virtual const ARMSubtarget *getSubtargetImpl() const { return &Subtarget; }
59 virtual const InstrItineraryData *getInstrItineraryData() const {
63 // Pass Pipeline Configuration
64 virtual bool addPreISel(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
65 virtual bool addInstSelector(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
66 virtual bool addPreRegAlloc(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
67 virtual bool addPreSched2(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
68 virtual bool addPreEmitPass(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
69 virtual bool addCodeEmitter(PassManagerBase &PM, CodeGenOpt::Level OptLevel,
73 /// ARMTargetMachine - ARM target machine.
75 class ARMTargetMachine : public ARMBaseTargetMachine {
76 ARMInstrInfo InstrInfo;
77 ARMTargetLowering TLInfo;
78 ARMSelectionDAGInfo TSInfo;
80 ARMTargetMachine(const Target &T, const std::string &TT,
81 const std::string &FS);
83 virtual const ARMRegisterInfo *getRegisterInfo() const {
84 return &InstrInfo.getRegisterInfo();
87 virtual const ARMTargetLowering *getTargetLowering() const {
91 virtual const ARMSelectionDAGInfo* getSelectionDAGInfo() const {
95 virtual const ARMInstrInfo *getInstrInfo() const { return &InstrInfo; }
96 virtual const TargetData *getTargetData() const { return &DataLayout; }
99 /// ThumbTargetMachine - Thumb target machine.
100 /// Due to the way architectures are handled, this represents both
101 /// Thumb-1 and Thumb-2.
103 class ThumbTargetMachine : public ARMBaseTargetMachine {
104 // Either Thumb1InstrInfo or Thumb2InstrInfo.
105 OwningPtr<ARMBaseInstrInfo> InstrInfo;
106 ARMTargetLowering TLInfo;
107 ARMSelectionDAGInfo TSInfo;
109 ThumbTargetMachine(const Target &T, const std::string &TT,
110 const std::string &FS);
112 /// returns either Thumb1RegisterInfo or Thumb2RegisterInfo
113 virtual const ARMBaseRegisterInfo *getRegisterInfo() const {
114 return &InstrInfo->getRegisterInfo();
117 virtual const ARMTargetLowering *getTargetLowering() const {
121 virtual const ARMSelectionDAGInfo *getSelectionDAGInfo() const {
125 /// returns either Thumb1InstrInfo or Thumb2InstrInfo
126 virtual const ARMBaseInstrInfo *getInstrInfo() const {
127 return InstrInfo.get();
129 virtual const TargetData *getTargetData() const { return &DataLayout; }
132 } // end namespace llvm