ac9b6bfbd4646b1a6ec4c63b48e91d213a90d304
[oota-llvm.git] / lib / Target / ARM / ARMTargetMachine.cpp
1 //===-- ARMTargetMachine.cpp - Define TargetMachine for ARM ---------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 //
11 //===----------------------------------------------------------------------===//
12
13 #include "ARMTargetMachine.h"
14 #include "ARMMCAsmInfo.h"
15 #include "ARMFrameInfo.h"
16 #include "ARM.h"
17 #include "llvm/PassManager.h"
18 #include "llvm/CodeGen/Passes.h"
19 #include "llvm/Support/FormattedStream.h"
20 #include "llvm/Target/TargetOptions.h"
21 #include "llvm/Target/TargetRegistry.h"
22 using namespace llvm;
23
24 static MCAsmInfo *createMCAsmInfo(const Target &T, StringRef TT) {
25   Triple TheTriple(TT);
26   switch (TheTriple.getOS()) {
27   case Triple::Darwin:
28     return new ARMMCAsmInfoDarwin();
29   default:
30     return new ARMELFMCAsmInfo();
31   }
32 }
33
34 extern "C" void LLVMInitializeARMTarget() {
35   // Register the target.
36   RegisterTargetMachine<ARMTargetMachine> X(TheARMTarget);
37   RegisterTargetMachine<ThumbTargetMachine> Y(TheThumbTarget);
38
39   // Register the target asm info.
40   RegisterAsmInfoFn A(TheARMTarget, createMCAsmInfo);
41   RegisterAsmInfoFn B(TheThumbTarget, createMCAsmInfo);
42 }
43
44 /// TargetMachine ctor - Create an ARM architecture model.
45 ///
46 ARMBaseTargetMachine::ARMBaseTargetMachine(const Target &T,
47                                            const std::string &TT,
48                                            const std::string &FS,
49                                            bool isThumb)
50   : LLVMTargetMachine(T, TT),
51     Subtarget(TT, FS, isThumb),
52     FrameInfo(Subtarget),
53     JITInfo(),
54     InstrItins(Subtarget.getInstrItineraryData()) {
55   DefRelocModel = getRelocationModel();
56 }
57
58 ARMTargetMachine::ARMTargetMachine(const Target &T, const std::string &TT,
59                                    const std::string &FS)
60   : ARMBaseTargetMachine(T, TT, FS, false), InstrInfo(Subtarget),
61     DataLayout(Subtarget.isAPCS_ABI() ?
62                std::string("e-p:32:32-f64:32:32-i64:32:32-"
63                            "v128:32:128-v64:32:64-n32") :
64                std::string("e-p:32:32-f64:64:64-i64:64:64-"
65                            "v128:64:128-v64:64:64-n32")),
66     TLInfo(*this),
67     TSInfo(*this) {
68 }
69
70 ThumbTargetMachine::ThumbTargetMachine(const Target &T, const std::string &TT,
71                                        const std::string &FS)
72   : ARMBaseTargetMachine(T, TT, FS, true),
73     InstrInfo(Subtarget.hasThumb2()
74               ? ((ARMBaseInstrInfo*)new Thumb2InstrInfo(Subtarget))
75               : ((ARMBaseInstrInfo*)new Thumb1InstrInfo(Subtarget))),
76     DataLayout(Subtarget.isAPCS_ABI() ?
77                std::string("e-p:32:32-f64:32:32-i64:32:32-"
78                            "i16:16:32-i8:8:32-i1:8:32-"
79                            "v128:32:128-v64:32:64-a:0:32-n32") :
80                std::string("e-p:32:32-f64:64:64-i64:64:64-"
81                            "i16:16:32-i8:8:32-i1:8:32-"
82                            "v128:64:128-v64:64:64-a:0:32-n32")),
83     TLInfo(*this),
84     TSInfo(*this) {
85 }
86
87 // Pass Pipeline Configuration
88 bool ARMBaseTargetMachine::addPreISel(PassManagerBase &PM,
89                                       CodeGenOpt::Level OptLevel) {
90   if (OptLevel != CodeGenOpt::None)
91     PM.add(createARMGlobalMergePass(getTargetLowering()));
92
93   return false;
94 }
95
96 bool ARMBaseTargetMachine::addInstSelector(PassManagerBase &PM,
97                                            CodeGenOpt::Level OptLevel) {
98   PM.add(createARMISelDag(*this, OptLevel));
99   return false;
100 }
101
102 bool ARMBaseTargetMachine::addPreRegAlloc(PassManagerBase &PM,
103                                           CodeGenOpt::Level OptLevel) {
104   if (Subtarget.hasNEON())
105     PM.add(createNEONPreAllocPass());
106
107   // FIXME: temporarily disabling load / store optimization pass for Thumb1.
108   if (OptLevel != CodeGenOpt::None && !Subtarget.isThumb1Only())
109     PM.add(createARMLoadStoreOptimizationPass(true));
110
111   return true;
112 }
113
114 bool ARMBaseTargetMachine::addPreSched2(PassManagerBase &PM,
115                                         CodeGenOpt::Level OptLevel) {
116   // FIXME: temporarily disabling load / store optimization pass for Thumb1.
117   if (OptLevel != CodeGenOpt::None) {
118     if (!Subtarget.isThumb1Only())
119       PM.add(createARMLoadStoreOptimizationPass());
120     if (Subtarget.hasNEON())
121       PM.add(createNEONMoveFixPass());
122   }
123
124   // Expand some pseudo instructions into multiple instructions to allow
125   // proper scheduling.
126   PM.add(createARMExpandPseudoPass());
127
128   if (OptLevel != CodeGenOpt::None) {
129     if (!Subtarget.isThumb1Only())
130       PM.add(createIfConverterPass());
131   }
132   if (Subtarget.isThumb2())
133     PM.add(createThumb2ITBlockPass());
134
135   return true;
136 }
137
138 bool ARMBaseTargetMachine::addPreEmitPass(PassManagerBase &PM,
139                                           CodeGenOpt::Level OptLevel) {
140   if (Subtarget.isThumb2() && !Subtarget.prefers32BitThumb())
141     PM.add(createThumb2SizeReductionPass());
142
143   PM.add(createARMConstantIslandPass());
144   return true;
145 }
146
147 bool ARMBaseTargetMachine::addCodeEmitter(PassManagerBase &PM,
148                                           CodeGenOpt::Level OptLevel,
149                                           JITCodeEmitter &JCE) {
150   // FIXME: Move this to TargetJITInfo!
151   if (DefRelocModel == Reloc::Default)
152     setRelocationModel(Reloc::Static);
153
154   // Machine code emitter pass for ARM.
155   PM.add(createARMJITCodeEmitterPass(*this, JCE));
156   return false;
157 }