1 //===-- ARMTargetMachine.cpp - Define TargetMachine for ARM ---------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
14 #include "ARMTargetMachine.h"
15 #include "ARMFrameLowering.h"
16 #include "llvm/CodeGen/Passes.h"
17 #include "llvm/MC/MCAsmInfo.h"
18 #include "llvm/PassManager.h"
19 #include "llvm/Support/CommandLine.h"
20 #include "llvm/Support/FormattedStream.h"
21 #include "llvm/Support/TargetRegistry.h"
22 #include "llvm/Target/TargetOptions.h"
23 #include "llvm/Transforms/Scalar.h"
27 DisableA15SDOptimization("disable-a15-sd-optimization", cl::Hidden,
28 cl::desc("Inhibit optimization of S->D register accesses on A15"),
32 EnableAtomicTidy("arm-atomic-cfg-tidy", cl::Hidden,
33 cl::desc("Run SimplifyCFG after expanding atomic operations"
34 " to make use of cmpxchg flow-based information"),
37 extern "C" void LLVMInitializeARMTarget() {
38 // Register the target.
39 RegisterTargetMachine<ARMLETargetMachine> X(TheARMLETarget);
40 RegisterTargetMachine<ARMBETargetMachine> Y(TheARMBETarget);
41 RegisterTargetMachine<ThumbLETargetMachine> A(TheThumbLETarget);
42 RegisterTargetMachine<ThumbBETargetMachine> B(TheThumbBETarget);
46 /// TargetMachine ctor - Create an ARM architecture model.
48 ARMBaseTargetMachine::ARMBaseTargetMachine(const Target &T, StringRef TT,
49 StringRef CPU, StringRef FS,
50 const TargetOptions &Options,
51 Reloc::Model RM, CodeModel::Model CM,
54 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
55 Subtarget(TT, CPU, FS, isLittle, Options),
57 InstrItins(Subtarget.getInstrItineraryData()) {
59 // Default to triple-appropriate float ABI
60 if (Options.FloatABIType == FloatABI::Default)
61 this->Options.FloatABIType =
62 Subtarget.isTargetHardFloat() ? FloatABI::Hard : FloatABI::Soft;
65 void ARMBaseTargetMachine::addAnalysisPasses(PassManagerBase &PM) {
66 // Add first the target-independent BasicTTI pass, then our ARM pass. This
67 // allows the ARM pass to delegate to the target independent layer when
69 PM.add(createBasicTargetTransformInfoPass(this));
70 PM.add(createARMTargetTransformInfoPass(this));
74 void ARMTargetMachine::anchor() { }
76 ARMTargetMachine::ARMTargetMachine(const Target &T, StringRef TT,
77 StringRef CPU, StringRef FS,
78 const TargetOptions &Options,
79 Reloc::Model RM, CodeModel::Model CM,
82 : ARMBaseTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, isLittle),
85 TSInfo(*getDataLayout()),
86 FrameLowering(Subtarget) {
88 if (!Subtarget.hasARMOps())
89 report_fatal_error("CPU: '" + Subtarget.getCPUString() + "' does not "
90 "support ARM mode execution!");
93 void ARMLETargetMachine::anchor() { }
96 ARMLETargetMachine(const Target &T, StringRef TT,
97 StringRef CPU, StringRef FS, const TargetOptions &Options,
98 Reloc::Model RM, CodeModel::Model CM,
100 : ARMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
102 void ARMBETargetMachine::anchor() { }
105 ARMBETargetMachine(const Target &T, StringRef TT,
106 StringRef CPU, StringRef FS, const TargetOptions &Options,
107 Reloc::Model RM, CodeModel::Model CM,
108 CodeGenOpt::Level OL)
109 : ARMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
111 void ThumbTargetMachine::anchor() { }
113 ThumbTargetMachine::ThumbTargetMachine(const Target &T, StringRef TT,
114 StringRef CPU, StringRef FS,
115 const TargetOptions &Options,
116 Reloc::Model RM, CodeModel::Model CM,
117 CodeGenOpt::Level OL,
119 : ARMBaseTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, isLittle),
120 InstrInfo(Subtarget.hasThumb2()
121 ? ((ARMBaseInstrInfo*)new Thumb2InstrInfo(Subtarget))
122 : ((ARMBaseInstrInfo*)new Thumb1InstrInfo(Subtarget))),
124 TSInfo(*getDataLayout()),
125 FrameLowering(Subtarget.hasThumb2()
126 ? new ARMFrameLowering(Subtarget)
127 : (ARMFrameLowering*)new Thumb1FrameLowering(Subtarget)) {
131 void ThumbLETargetMachine::anchor() { }
133 ThumbLETargetMachine::
134 ThumbLETargetMachine(const Target &T, StringRef TT,
135 StringRef CPU, StringRef FS, const TargetOptions &Options,
136 Reloc::Model RM, CodeModel::Model CM,
137 CodeGenOpt::Level OL)
138 : ThumbTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
140 void ThumbBETargetMachine::anchor() { }
142 ThumbBETargetMachine::
143 ThumbBETargetMachine(const Target &T, StringRef TT,
144 StringRef CPU, StringRef FS, const TargetOptions &Options,
145 Reloc::Model RM, CodeModel::Model CM,
146 CodeGenOpt::Level OL)
147 : ThumbTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
150 /// ARM Code Generator Pass Configuration Options.
151 class ARMPassConfig : public TargetPassConfig {
153 ARMPassConfig(ARMBaseTargetMachine *TM, PassManagerBase &PM)
154 : TargetPassConfig(TM, PM) {}
156 ARMBaseTargetMachine &getARMTargetMachine() const {
157 return getTM<ARMBaseTargetMachine>();
160 const ARMSubtarget &getARMSubtarget() const {
161 return *getARMTargetMachine().getSubtargetImpl();
164 void addIRPasses() override;
165 bool addPreISel() override;
166 bool addInstSelector() override;
167 bool addPreRegAlloc() override;
168 bool addPreSched2() override;
169 bool addPreEmitPass() override;
173 TargetPassConfig *ARMBaseTargetMachine::createPassConfig(PassManagerBase &PM) {
174 return new ARMPassConfig(this, PM);
177 void ARMPassConfig::addIRPasses() {
178 const ARMSubtarget *Subtarget = &getARMSubtarget();
179 if (Subtarget->hasAnyDataBarrier() && !Subtarget->isThumb1Only()) {
180 addPass(createAtomicExpandLoadLinkedPass(TM));
182 // Cmpxchg instructions are often used with a subsequent comparison to
183 // determine whether it succeeded. We can exploit existing control-flow in
184 // ldrex/strex loops to simplify this, but it needs tidying up.
185 if (TM->getOptLevel() != CodeGenOpt::None && EnableAtomicTidy)
186 addPass(createCFGSimplificationPass());
189 TargetPassConfig::addIRPasses();
192 bool ARMPassConfig::addPreISel() {
193 if (TM->getOptLevel() != CodeGenOpt::None)
194 addPass(createGlobalMergePass(TM));
199 bool ARMPassConfig::addInstSelector() {
200 addPass(createARMISelDag(getARMTargetMachine(), getOptLevel()));
202 const ARMSubtarget *Subtarget = &getARMSubtarget();
203 if (Subtarget->isTargetELF() && !Subtarget->isThumb1Only() &&
204 TM->Options.EnableFastISel)
205 addPass(createARMGlobalBaseRegPass());
209 bool ARMPassConfig::addPreRegAlloc() {
210 // FIXME: Temporarily disabling Thumb-1 pre-RA Load/Store optimization pass
211 if (getOptLevel() != CodeGenOpt::None && !getARMSubtarget().isThumb1Only())
212 addPass(createARMLoadStoreOptimizationPass(true));
213 if (getOptLevel() != CodeGenOpt::None && getARMSubtarget().isCortexA9())
214 addPass(createMLxExpansionPass());
215 // Since the A15SDOptimizer pass can insert VDUP instructions, it can only be
216 // enabled when NEON is available.
217 if (getOptLevel() != CodeGenOpt::None && getARMSubtarget().isCortexA15() &&
218 getARMSubtarget().hasNEON() && !DisableA15SDOptimization) {
219 addPass(createA15SDOptimizerPass());
224 bool ARMPassConfig::addPreSched2() {
225 if (getOptLevel() != CodeGenOpt::None) {
226 // FIXME: Temporarily disabling Thumb-1 post-RA Load/Store optimization pass
227 if (!getARMSubtarget().isThumb1Only()) {
228 addPass(createARMLoadStoreOptimizationPass());
229 printAndVerify("After ARM load / store optimizer");
232 if (getARMSubtarget().hasNEON())
233 addPass(createExecutionDependencyFixPass(&ARM::DPRRegClass));
236 // Expand some pseudo instructions into multiple instructions to allow
237 // proper scheduling.
238 addPass(createARMExpandPseudoPass());
240 if (getOptLevel() != CodeGenOpt::None) {
241 if (!getARMSubtarget().isThumb1Only()) {
242 // in v8, IfConversion depends on Thumb instruction widths
243 if (getARMSubtarget().restrictIT() &&
244 !getARMSubtarget().prefers32BitThumb())
245 addPass(createThumb2SizeReductionPass());
246 addPass(&IfConverterID);
249 if (getARMSubtarget().isThumb2())
250 addPass(createThumb2ITBlockPass());
255 bool ARMPassConfig::addPreEmitPass() {
256 if (getARMSubtarget().isThumb2()) {
257 if (!getARMSubtarget().prefers32BitThumb())
258 addPass(createThumb2SizeReductionPass());
260 // Constant island pass work on unbundled instructions.
261 addPass(&UnpackMachineBundlesID);
264 addPass(createARMOptimizeBarriersPass());
265 addPass(createARMConstantIslandPass());
270 bool ARMBaseTargetMachine::addCodeEmitter(PassManagerBase &PM,
271 JITCodeEmitter &JCE) {
272 // Machine code emitter pass for ARM.
273 PM.add(createARMJITCodeEmitterPass(*this, JCE));