1 //===-- ARMTargetMachine.cpp - Define TargetMachine for ARM ---------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
13 #include "ARMTargetMachine.h"
14 #include "ARMMCAsmInfo.h"
15 #include "ARMFrameInfo.h"
17 #include "llvm/PassManager.h"
18 #include "llvm/CodeGen/Passes.h"
19 #include "llvm/Support/CommandLine.h"
20 #include "llvm/Support/FormattedStream.h"
21 #include "llvm/Target/TargetOptions.h"
22 #include "llvm/Target/TargetRegistry.h"
26 EarlyITBlockFormation("thumb2-early-it-blocks", cl::Hidden,
27 cl::desc("Form IT blocks early before register allocation"),
30 static MCAsmInfo *createMCAsmInfo(const Target &T, StringRef TT) {
32 switch (TheTriple.getOS()) {
34 return new ARMMCAsmInfoDarwin();
36 return new ARMELFMCAsmInfo();
41 extern "C" void LLVMInitializeARMTarget() {
42 // Register the target.
43 RegisterTargetMachine<ARMTargetMachine> X(TheARMTarget);
44 RegisterTargetMachine<ThumbTargetMachine> Y(TheThumbTarget);
46 // Register the target asm info.
47 RegisterAsmInfoFn A(TheARMTarget, createMCAsmInfo);
48 RegisterAsmInfoFn B(TheThumbTarget, createMCAsmInfo);
51 /// TargetMachine ctor - Create an ARM architecture model.
53 ARMBaseTargetMachine::ARMBaseTargetMachine(const Target &T,
54 const std::string &TT,
55 const std::string &FS,
57 : LLVMTargetMachine(T, TT),
58 Subtarget(TT, FS, isThumb),
61 InstrItins(Subtarget.getInstrItineraryData()) {
62 DefRelocModel = getRelocationModel();
65 ARMTargetMachine::ARMTargetMachine(const Target &T, const std::string &TT,
66 const std::string &FS)
67 : ARMBaseTargetMachine(T, TT, FS, false), InstrInfo(Subtarget),
68 DataLayout(Subtarget.isAPCS_ABI() ?
69 std::string("e-p:32:32-f64:32:32-i64:32:32-n32") :
70 std::string("e-p:32:32-f64:64:64-i64:64:64-n32")),
75 ThumbTargetMachine::ThumbTargetMachine(const Target &T, const std::string &TT,
76 const std::string &FS)
77 : ARMBaseTargetMachine(T, TT, FS, true),
78 InstrInfo(Subtarget.hasThumb2()
79 ? ((ARMBaseInstrInfo*)new Thumb2InstrInfo(Subtarget))
80 : ((ARMBaseInstrInfo*)new Thumb1InstrInfo(Subtarget))),
81 DataLayout(Subtarget.isAPCS_ABI() ?
82 std::string("e-p:32:32-f64:32:32-i64:32:32-"
83 "i16:16:32-i8:8:32-i1:8:32-a:0:32-n32") :
84 std::string("e-p:32:32-f64:64:64-i64:64:64-"
85 "i16:16:32-i8:8:32-i1:8:32-a:0:32-n32")),
92 // Pass Pipeline Configuration
93 bool ARMBaseTargetMachine::addInstSelector(PassManagerBase &PM,
94 CodeGenOpt::Level OptLevel) {
95 PM.add(createARMISelDag(*this, OptLevel));
99 bool ARMBaseTargetMachine::addPreRegAlloc(PassManagerBase &PM,
100 CodeGenOpt::Level OptLevel) {
101 if (Subtarget.hasNEON())
102 PM.add(createNEONPreAllocPass());
104 // FIXME: temporarily disabling load / store optimization pass for Thumb1.
105 if (OptLevel != CodeGenOpt::None && !Subtarget.isThumb1Only())
106 PM.add(createARMLoadStoreOptimizationPass(true));
108 if (OptLevel != CodeGenOpt::None && Subtarget.isThumb2() &&
109 EarlyITBlockFormation)
110 PM.add(createThumb2ITBlockPass(true));
114 bool ARMBaseTargetMachine::addPreSched2(PassManagerBase &PM,
115 CodeGenOpt::Level OptLevel) {
116 // FIXME: temporarily disabling load / store optimization pass for Thumb1.
117 if (OptLevel != CodeGenOpt::None) {
118 if (!Subtarget.isThumb1Only())
119 PM.add(createARMLoadStoreOptimizationPass());
120 if (Subtarget.hasNEON())
121 PM.add(createNEONMoveFixPass());
124 // Expand some pseudo instructions into multiple instructions to allow
125 // proper scheduling.
126 PM.add(createARMExpandPseudoPass());
131 bool ARMBaseTargetMachine::addPreEmitPass(PassManagerBase &PM,
132 CodeGenOpt::Level OptLevel) {
133 // FIXME: temporarily disabling load / store optimization pass for Thumb1.
134 if (OptLevel != CodeGenOpt::None) {
135 if (!Subtarget.isThumb1Only())
136 PM.add(createIfConverterPass());
139 if (Subtarget.isThumb2()) {
140 PM.add(createThumb2ITBlockPass());
141 PM.add(createThumb2SizeReductionPass());
144 PM.add(createARMConstantIslandPass());
148 bool ARMBaseTargetMachine::addCodeEmitter(PassManagerBase &PM,
149 CodeGenOpt::Level OptLevel,
150 JITCodeEmitter &JCE) {
151 // FIXME: Move this to TargetJITInfo!
152 if (DefRelocModel == Reloc::Default)
153 setRelocationModel(Reloc::Static);
155 // Machine code emitter pass for ARM.
156 PM.add(createARMJITCodeEmitterPass(*this, JCE));