1 //===-- ARMTargetMachine.cpp - Define TargetMachine for ARM ---------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
14 #include "ARMTargetMachine.h"
15 #include "ARMFrameLowering.h"
16 #include "ARMTargetObjectFile.h"
17 #include "llvm/CodeGen/Passes.h"
18 #include "llvm/IR/Function.h"
19 #include "llvm/MC/MCAsmInfo.h"
20 #include "llvm/PassManager.h"
21 #include "llvm/Support/CommandLine.h"
22 #include "llvm/Support/FormattedStream.h"
23 #include "llvm/Support/TargetRegistry.h"
24 #include "llvm/Target/TargetOptions.h"
25 #include "llvm/Transforms/Scalar.h"
29 DisableA15SDOptimization("disable-a15-sd-optimization", cl::Hidden,
30 cl::desc("Inhibit optimization of S->D register accesses on A15"),
34 EnableAtomicTidy("arm-atomic-cfg-tidy", cl::Hidden,
35 cl::desc("Run SimplifyCFG after expanding atomic operations"
36 " to make use of cmpxchg flow-based information"),
39 extern "C" void LLVMInitializeARMTarget() {
40 // Register the target.
41 RegisterTargetMachine<ARMLETargetMachine> X(TheARMLETarget);
42 RegisterTargetMachine<ARMBETargetMachine> Y(TheARMBETarget);
43 RegisterTargetMachine<ThumbLETargetMachine> A(TheThumbLETarget);
44 RegisterTargetMachine<ThumbBETargetMachine> B(TheThumbBETarget);
47 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
48 if (TT.isOSBinFormatMachO())
49 return make_unique<TargetLoweringObjectFileMachO>();
51 return make_unique<TargetLoweringObjectFileCOFF>();
52 return make_unique<ARMElfTargetObjectFile>();
55 /// TargetMachine ctor - Create an ARM architecture model.
57 ARMBaseTargetMachine::ARMBaseTargetMachine(const Target &T, StringRef TT,
58 StringRef CPU, StringRef FS,
59 const TargetOptions &Options,
60 Reloc::Model RM, CodeModel::Model CM,
61 CodeGenOpt::Level OL, bool isLittle)
62 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
63 TLOF(createTLOF(Triple(getTargetTriple()))),
64 Subtarget(TT, CPU, FS, *this, isLittle), isLittle(isLittle) {
66 // Default to triple-appropriate float ABI
67 if (Options.FloatABIType == FloatABI::Default)
68 this->Options.FloatABIType =
69 Subtarget.isTargetHardFloat() ? FloatABI::Hard : FloatABI::Soft;
72 ARMBaseTargetMachine::~ARMBaseTargetMachine() {}
75 ARMBaseTargetMachine::getSubtargetImpl(const Function &F) const {
76 AttributeSet FnAttrs = F.getAttributes();
78 FnAttrs.getAttribute(AttributeSet::FunctionIndex, "target-cpu");
80 FnAttrs.getAttribute(AttributeSet::FunctionIndex, "target-features");
82 std::string CPU = !CPUAttr.hasAttribute(Attribute::None)
83 ? CPUAttr.getValueAsString().str()
85 std::string FS = !FSAttr.hasAttribute(Attribute::None)
86 ? FSAttr.getValueAsString().str()
89 // FIXME: This is related to the code below to reset the target options,
90 // we need to know whether or not the soft float flag is set on the
91 // function before we can generate a subtarget. We also need to use
92 // it as a key for the subtarget since that can be the only difference
93 // between two functions.
95 FnAttrs.getAttribute(AttributeSet::FunctionIndex, "use-soft-float");
96 bool SoftFloat = !SFAttr.hasAttribute(Attribute::None)
97 ? SFAttr.getValueAsString() == "true"
98 : Options.UseSoftFloat;
100 auto &I = SubtargetMap[CPU + FS + (SoftFloat ? "use-soft-float=true"
101 : "use-soft-float=false")];
103 // This needs to be done before we create a new subtarget since any
104 // creation will depend on the TM and the code generation flags on the
105 // function that reside in TargetOptions.
106 resetTargetOptions(F);
107 I = llvm::make_unique<ARMSubtarget>(TargetTriple, CPU, FS, *this, isLittle);
112 void ARMBaseTargetMachine::addAnalysisPasses(PassManagerBase &PM) {
113 // Add first the target-independent BasicTTI pass, then our ARM pass. This
114 // allows the ARM pass to delegate to the target independent layer when
116 PM.add(createBasicTargetTransformInfoPass(this));
117 PM.add(createARMTargetTransformInfoPass(this));
121 void ARMTargetMachine::anchor() { }
123 ARMTargetMachine::ARMTargetMachine(const Target &T, StringRef TT, StringRef CPU,
124 StringRef FS, const TargetOptions &Options,
125 Reloc::Model RM, CodeModel::Model CM,
126 CodeGenOpt::Level OL, bool isLittle)
127 : ARMBaseTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, isLittle) {
129 if (!Subtarget.hasARMOps())
130 report_fatal_error("CPU: '" + Subtarget.getCPUString() + "' does not "
131 "support ARM mode execution!");
134 void ARMLETargetMachine::anchor() { }
136 ARMLETargetMachine::ARMLETargetMachine(const Target &T, StringRef TT,
137 StringRef CPU, StringRef FS,
138 const TargetOptions &Options,
139 Reloc::Model RM, CodeModel::Model CM,
140 CodeGenOpt::Level OL)
141 : ARMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
143 void ARMBETargetMachine::anchor() { }
145 ARMBETargetMachine::ARMBETargetMachine(const Target &T, StringRef TT,
146 StringRef CPU, StringRef FS,
147 const TargetOptions &Options,
148 Reloc::Model RM, CodeModel::Model CM,
149 CodeGenOpt::Level OL)
150 : ARMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
152 void ThumbTargetMachine::anchor() { }
154 ThumbTargetMachine::ThumbTargetMachine(const Target &T, StringRef TT,
155 StringRef CPU, StringRef FS,
156 const TargetOptions &Options,
157 Reloc::Model RM, CodeModel::Model CM,
158 CodeGenOpt::Level OL, bool isLittle)
159 : ARMBaseTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL,
164 void ThumbLETargetMachine::anchor() { }
166 ThumbLETargetMachine::ThumbLETargetMachine(const Target &T, StringRef TT,
167 StringRef CPU, StringRef FS,
168 const TargetOptions &Options,
169 Reloc::Model RM, CodeModel::Model CM,
170 CodeGenOpt::Level OL)
171 : ThumbTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
173 void ThumbBETargetMachine::anchor() { }
175 ThumbBETargetMachine::ThumbBETargetMachine(const Target &T, StringRef TT,
176 StringRef CPU, StringRef FS,
177 const TargetOptions &Options,
178 Reloc::Model RM, CodeModel::Model CM,
179 CodeGenOpt::Level OL)
180 : ThumbTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
183 /// ARM Code Generator Pass Configuration Options.
184 class ARMPassConfig : public TargetPassConfig {
186 ARMPassConfig(ARMBaseTargetMachine *TM, PassManagerBase &PM)
187 : TargetPassConfig(TM, PM) {}
189 ARMBaseTargetMachine &getARMTargetMachine() const {
190 return getTM<ARMBaseTargetMachine>();
193 const ARMSubtarget &getARMSubtarget() const {
194 return *getARMTargetMachine().getSubtargetImpl();
197 void addIRPasses() override;
198 bool addPreISel() override;
199 bool addInstSelector() override;
200 void addPreRegAlloc() override;
201 void addPreSched2() override;
202 void addPreEmitPass() override;
206 TargetPassConfig *ARMBaseTargetMachine::createPassConfig(PassManagerBase &PM) {
207 return new ARMPassConfig(this, PM);
210 void ARMPassConfig::addIRPasses() {
211 if (TM->Options.ThreadModel == ThreadModel::Single)
212 addPass(createLowerAtomicPass());
214 addPass(createAtomicExpandPass(TM));
216 // Cmpxchg instructions are often used with a subsequent comparison to
217 // determine whether it succeeded. We can exploit existing control-flow in
218 // ldrex/strex loops to simplify this, but it needs tidying up.
219 const ARMSubtarget *Subtarget = &getARMSubtarget();
220 if (Subtarget->hasAnyDataBarrier() && !Subtarget->isThumb1Only())
221 if (TM->getOptLevel() != CodeGenOpt::None && EnableAtomicTidy)
222 addPass(createCFGSimplificationPass());
224 TargetPassConfig::addIRPasses();
227 bool ARMPassConfig::addPreISel() {
228 if (TM->getOptLevel() != CodeGenOpt::None)
229 addPass(createGlobalMergePass(TM));
234 bool ARMPassConfig::addInstSelector() {
235 addPass(createARMISelDag(getARMTargetMachine(), getOptLevel()));
237 const ARMSubtarget *Subtarget = &getARMSubtarget();
238 if (Subtarget->isTargetELF() && !Subtarget->isThumb1Only() &&
239 TM->Options.EnableFastISel)
240 addPass(createARMGlobalBaseRegPass());
244 void ARMPassConfig::addPreRegAlloc() {
245 if (getOptLevel() != CodeGenOpt::None)
246 addPass(createARMLoadStoreOptimizationPass(true), false);
247 if (getOptLevel() != CodeGenOpt::None && getARMSubtarget().isCortexA9())
248 addPass(createMLxExpansionPass(), false);
249 // Since the A15SDOptimizer pass can insert VDUP instructions, it can only be
250 // enabled when NEON is available.
251 if (getOptLevel() != CodeGenOpt::None && getARMSubtarget().isCortexA15() &&
252 getARMSubtarget().hasNEON() && !DisableA15SDOptimization) {
253 addPass(createA15SDOptimizerPass());
257 void ARMPassConfig::addPreSched2() {
258 if (getOptLevel() != CodeGenOpt::None) {
259 addPass(createARMLoadStoreOptimizationPass(), false);
261 if (getARMSubtarget().hasNEON())
262 addPass(createExecutionDependencyFixPass(&ARM::DPRRegClass), false);
265 // Expand some pseudo instructions into multiple instructions to allow
266 // proper scheduling.
267 addPass(createARMExpandPseudoPass(), false);
269 if (getOptLevel() != CodeGenOpt::None) {
270 if (!getARMSubtarget().isThumb1Only()) {
271 // in v8, IfConversion depends on Thumb instruction widths
272 if (getARMSubtarget().restrictIT() &&
273 !getARMSubtarget().prefers32BitThumb())
274 addPass(createThumb2SizeReductionPass(), false);
275 addPass(&IfConverterID, false);
278 if (getARMSubtarget().isThumb2())
279 addPass(createThumb2ITBlockPass());
282 void ARMPassConfig::addPreEmitPass() {
283 if (getARMSubtarget().isThumb2()) {
284 if (!getARMSubtarget().prefers32BitThumb())
285 addPass(createThumb2SizeReductionPass(), false);
287 // Constant island pass work on unbundled instructions.
288 addPass(&UnpackMachineBundlesID, false);
291 addPass(createARMOptimizeBarriersPass(), false);
292 addPass(createARMConstantIslandPass());