1 //===-- ARMSubtarget.h - Define Subtarget for the ARM ----------*- C++ -*--===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file declares the ARM specific subclass of TargetSubtargetInfo.
12 //===----------------------------------------------------------------------===//
14 #ifndef ARMSUBTARGET_H
15 #define ARMSUBTARGET_H
17 #include "MCTargetDesc/ARMMCTargetDesc.h"
18 #include "llvm/ADT/Triple.h"
19 #include "llvm/MC/MCInstrItineraries.h"
20 #include "llvm/Target/TargetSubtargetInfo.h"
23 #define GET_SUBTARGETINFO_HEADER
24 #include "ARMGenSubtargetInfo.inc"
31 class ARMSubtarget : public ARMGenSubtargetInfo {
33 enum ARMProcFamilyEnum {
34 Others, CortexA5, CortexA8, CortexA9, CortexA15, CortexR5, Swift
37 /// ARMProcFamily - ARM processor family: Cortex-A8, Cortex-A9, and others.
38 ARMProcFamilyEnum ARMProcFamily;
40 /// HasV4TOps, HasV5TOps, HasV5TEOps,
41 /// HasV6Ops, HasV6T2Ops, HasV7Ops, HasV8Ops -
42 /// Specify whether target support specific ARM ISA variants.
51 /// HasVFPv2, HasVFPv3, HasVFPv4, HasNEON - Specify what
52 /// floating point ISAs are supported.
58 /// UseNEONForSinglePrecisionFP - if the NEONFP attribute has been
59 /// specified. Use the method useNEONForSinglePrecisionFP() to
60 /// determine if NEON should actually be used.
61 bool UseNEONForSinglePrecisionFP;
63 /// UseMulOps - True if non-microcoded fused integer multiply-add and
64 /// multiply-subtract instructions should be used.
67 /// SlowFPVMLx - If the VFP2 / NEON instructions are available, indicates
68 /// whether the FP VML[AS] instructions are slow (if so, don't use them).
71 /// HasVMLxForwarding - If true, NEON has special multiplier accumulator
72 /// forwarding to allow mul + mla being issued back to back.
73 bool HasVMLxForwarding;
75 /// SlowFPBrcc - True if floating point compare + branch is slow.
78 /// InThumbMode - True if compiling for Thumb, false for ARM.
81 /// HasThumb2 - True if Thumb2 instructions are supported.
84 /// IsMClass - True if the subtarget belongs to the 'M' profile of CPUs -
85 /// v6m, v7m for example.
88 /// NoARM - True if subtarget does not support ARM mode execution.
91 /// PostRAScheduler - True if using post-register-allocation scheduler.
94 /// IsR9Reserved - True if R9 is a not available as general purpose register.
97 /// UseMovt - True if MOVT / MOVW pairs are used for materialization of 32-bit
98 /// imms (including global addresses).
101 /// SupportsTailCall - True if the OS supports tail call. The dynamic linker
102 /// must be able to synthesize call stubs for interworking between ARM and
104 bool SupportsTailCall;
106 /// HasFP16 - True if subtarget supports half-precision FP (We support VFP+HF
110 /// HasD16 - True if subtarget is limited to 16 double precision
111 /// FP registers for VFPv3.
114 /// HasHardwareDivide - True if subtarget supports [su]div
115 bool HasHardwareDivide;
117 /// HasHardwareDivideInARM - True if subtarget supports [su]div in ARM mode
118 bool HasHardwareDivideInARM;
120 /// HasT2ExtractPack - True if subtarget supports thumb2 extract/pack
122 bool HasT2ExtractPack;
124 /// HasDataBarrier - True if the subtarget supports DMB / DSB data barrier
128 /// Pref32BitThumb - If true, codegen would prefer 32-bit Thumb instructions
129 /// over 16-bit ones.
132 /// AvoidCPSRPartialUpdate - If true, codegen would avoid using instructions
133 /// that partially update CPSR and add false dependency on the previous
134 /// CPSR setting instruction.
135 bool AvoidCPSRPartialUpdate;
137 /// AvoidMOVsShifterOperand - If true, codegen should avoid using flag setting
138 /// movs with shifter operand (i.e. asr, lsl, lsr).
139 bool AvoidMOVsShifterOperand;
141 /// HasRAS - Some processors perform return stack prediction. CodeGen should
142 /// avoid issue "normal" call instructions to callees which do not return.
145 /// HasMPExtension - True if the subtarget supports Multiprocessing
146 /// extension (ARMv7 only).
149 /// FPOnlySP - If true, the floating point unit only supports single
153 /// If true, the processor supports the Performance Monitor Extensions. These
154 /// include a generic cycle-counter as well as more fine-grained (often
155 /// implementation-specific) events.
158 /// HasTrustZone - if true, processor supports TrustZone security extensions
161 /// AllowsUnalignedMem - If true, the subtarget allows unaligned memory
162 /// accesses for some types. For details, see
163 /// ARMTargetLowering::allowsUnalignedMemoryAccesses().
164 bool AllowsUnalignedMem;
166 /// Thumb2DSP - If true, the subtarget supports the v7 DSP (saturating arith
167 /// and such) instructions in Thumb2 code.
170 /// NaCl TRAP instruction is generated instead of the regular TRAP.
173 /// Target machine allowed unsafe FP math (such as use of NEON fp)
176 /// stackAlignment - The minimum alignment known to hold of the stack frame on
177 /// entry to the function and which must be maintained by every function.
178 unsigned stackAlignment;
180 /// CPUString - String name of used CPU.
181 std::string CPUString;
183 /// TargetTriple - What processor and OS we're targeting.
186 /// SchedModel - Processor specific instruction costs.
187 const MCSchedModel *SchedModel;
189 /// Selected instruction itineraries (one entry per itinerary class.)
190 InstrItineraryData InstrItins;
192 /// Options passed via command line that could influence the target
193 const TargetOptions &Options;
202 ARM_ABI_AAPCS // ARM EABI
205 /// This constructor initializes the data members to match that
206 /// of the specified triple.
208 ARMSubtarget(const std::string &TT, const std::string &CPU,
209 const std::string &FS, const TargetOptions &Options);
211 /// getMaxInlineSizeThreshold - Returns the maximum memset / memcpy size
212 /// that still makes it profitable to inline the call.
213 unsigned getMaxInlineSizeThreshold() const {
214 // FIXME: For now, we don't lower memcpy's to loads / stores for Thumb1.
215 // Change this once Thumb1 ldmia / stmia support is added.
216 return isThumb1Only() ? 0 : 64;
218 /// ParseSubtargetFeatures - Parses features string setting specified
219 /// subtarget options. Definition of function is auto generated by tblgen.
220 void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
222 /// \brief Reset the features for the ARM target.
223 virtual void resetSubtargetFeatures(const MachineFunction *MF);
225 void initializeEnvironment();
226 void resetSubtargetFeatures(StringRef CPU, StringRef FS);
228 void computeIssueWidth();
230 bool hasV4TOps() const { return HasV4TOps; }
231 bool hasV5TOps() const { return HasV5TOps; }
232 bool hasV5TEOps() const { return HasV5TEOps; }
233 bool hasV6Ops() const { return HasV6Ops; }
234 bool hasV6T2Ops() const { return HasV6T2Ops; }
235 bool hasV7Ops() const { return HasV7Ops; }
236 bool hasV8Ops() const { return HasV8Ops; }
238 bool isCortexA5() const { return ARMProcFamily == CortexA5; }
239 bool isCortexA8() const { return ARMProcFamily == CortexA8; }
240 bool isCortexA9() const { return ARMProcFamily == CortexA9; }
241 bool isCortexA15() const { return ARMProcFamily == CortexA15; }
242 bool isSwift() const { return ARMProcFamily == Swift; }
243 bool isCortexM3() const { return CPUString == "cortex-m3"; }
244 bool isLikeA9() const { return isCortexA9() || isCortexA15(); }
245 bool isCortexR5() const { return ARMProcFamily == CortexR5; }
247 bool hasARMOps() const { return !NoARM; }
249 bool hasVFP2() const { return HasVFPv2; }
250 bool hasVFP3() const { return HasVFPv3; }
251 bool hasVFP4() const { return HasVFPv4; }
252 bool hasNEON() const { return HasNEON; }
253 bool useNEONForSinglePrecisionFP() const {
254 return hasNEON() && UseNEONForSinglePrecisionFP; }
256 bool hasDivide() const { return HasHardwareDivide; }
257 bool hasDivideInARMMode() const { return HasHardwareDivideInARM; }
258 bool hasT2ExtractPack() const { return HasT2ExtractPack; }
259 bool hasDataBarrier() const { return HasDataBarrier; }
260 bool useMulOps() const { return UseMulOps; }
261 bool useFPVMLx() const { return !SlowFPVMLx; }
262 bool hasVMLxForwarding() const { return HasVMLxForwarding; }
263 bool isFPBrccSlow() const { return SlowFPBrcc; }
264 bool isFPOnlySP() const { return FPOnlySP; }
265 bool hasPerfMon() const { return HasPerfMon; }
266 bool hasTrustZone() const { return HasTrustZone; }
267 bool prefers32BitThumb() const { return Pref32BitThumb; }
268 bool avoidCPSRPartialUpdate() const { return AvoidCPSRPartialUpdate; }
269 bool avoidMOVsShifterOperand() const { return AvoidMOVsShifterOperand; }
270 bool hasRAS() const { return HasRAS; }
271 bool hasMPExtension() const { return HasMPExtension; }
272 bool hasThumb2DSP() const { return Thumb2DSP; }
273 bool useNaClTrap() const { return UseNaClTrap; }
275 bool hasFP16() const { return HasFP16; }
276 bool hasD16() const { return HasD16; }
278 const Triple &getTargetTriple() const { return TargetTriple; }
280 bool isTargetIOS() const { return TargetTriple.getOS() == Triple::IOS; }
281 bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); }
282 bool isTargetNaCl() const { return TargetTriple.getOS() == Triple::NaCl; }
283 bool isTargetLinux() const { return TargetTriple.getOS() == Triple::Linux; }
284 bool isTargetELF() const { return !isTargetDarwin(); }
286 bool isAPCS_ABI() const { return TargetABI == ARM_ABI_APCS; }
287 bool isAAPCS_ABI() const { return TargetABI == ARM_ABI_AAPCS; }
289 bool isThumb() const { return InThumbMode; }
290 bool isThumb1Only() const { return InThumbMode && !HasThumb2; }
291 bool isThumb2() const { return InThumbMode && HasThumb2; }
292 bool hasThumb2() const { return HasThumb2; }
293 bool isMClass() const { return IsMClass; }
294 bool isARClass() const { return !IsMClass; }
296 bool isR9Reserved() const { return IsR9Reserved; }
298 bool useMovt() const { return UseMovt && hasV6T2Ops(); }
299 bool supportsTailCall() const { return SupportsTailCall; }
301 bool allowsUnalignedMem() const { return AllowsUnalignedMem; }
303 const std::string & getCPUString() const { return CPUString; }
305 unsigned getMispredictionPenalty() const;
307 /// enablePostRAScheduler - True at 'More' optimization.
308 bool enablePostRAScheduler(CodeGenOpt::Level OptLevel,
309 TargetSubtargetInfo::AntiDepBreakMode& Mode,
310 RegClassVector& CriticalPathRCs) const;
312 /// getInstrItins - Return the instruction itineraies based on subtarget
314 const InstrItineraryData &getInstrItineraryData() const { return InstrItins; }
316 /// getStackAlignment - Returns the minimum alignment known to hold of the
317 /// stack frame on entry to the function and which must be maintained by every
318 /// function for this subtarget.
319 unsigned getStackAlignment() const { return stackAlignment; }
321 /// GVIsIndirectSymbol - true if the GV will be accessed via an indirect
323 bool GVIsIndirectSymbol(const GlobalValue *GV, Reloc::Model RelocM) const;
325 } // End llvm namespace
327 #endif // ARMSUBTARGET_H