1 //===-- ARMSubtarget.cpp - ARM Subtarget Information ----------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the ARM specific subclass of TargetSubtargetInfo.
12 //===----------------------------------------------------------------------===//
14 #include "ARMSubtarget.h"
15 #include "ARMFrameLowering.h"
16 #include "ARMISelLowering.h"
17 #include "ARMInstrInfo.h"
18 #include "ARMSelectionDAGInfo.h"
19 #include "ARMSubtarget.h"
20 #include "ARMMachineFunctionInfo.h"
21 #include "Thumb1FrameLowering.h"
22 #include "Thumb1InstrInfo.h"
23 #include "Thumb2InstrInfo.h"
24 #include "llvm/IR/Attributes.h"
25 #include "llvm/IR/Function.h"
26 #include "llvm/IR/GlobalValue.h"
27 #include "llvm/Support/CommandLine.h"
28 #include "llvm/Target/TargetInstrInfo.h"
29 #include "llvm/Target/TargetOptions.h"
30 #include "llvm/Target/TargetRegisterInfo.h"
31 #include "llvm/CodeGen/MachineRegisterInfo.h"
35 #define DEBUG_TYPE "arm-subtarget"
37 #define GET_SUBTARGETINFO_TARGET_DESC
38 #define GET_SUBTARGETINFO_CTOR
39 #include "ARMGenSubtargetInfo.inc"
42 ReserveR9("arm-reserve-r9", cl::Hidden,
43 cl::desc("Reserve R9, making it unavailable as GPR"));
46 ArmUseMOVT("arm-use-movt", cl::init(true), cl::Hidden);
49 UseFusedMulOps("arm-use-mulops",
50 cl::init(true), cl::Hidden);
60 static cl::opt<AlignMode>
61 Align(cl::desc("Load/store alignment support"),
62 cl::Hidden, cl::init(DefaultAlign),
64 clEnumValN(DefaultAlign, "arm-default-align",
65 "Generate unaligned accesses only on hardware/OS "
66 "combinations that are known to support them"),
67 clEnumValN(StrictAlign, "arm-strict-align",
68 "Disallow all unaligned memory accesses"),
69 clEnumValN(NoStrictAlign, "arm-no-strict-align",
70 "Allow unaligned memory accesses"),
79 static cl::opt<ITMode>
80 IT(cl::desc("IT block support"), cl::Hidden, cl::init(DefaultIT),
82 cl::values(clEnumValN(DefaultIT, "arm-default-it",
83 "Generate IT block based on arch"),
84 clEnumValN(RestrictedIT, "arm-restrict-it",
85 "Disallow deprecated IT based on ARMv8"),
86 clEnumValN(NoRestrictedIT, "arm-no-restrict-it",
87 "Allow IT blocks based on ARMv7"),
90 static std::string computeDataLayout(ARMSubtarget &ST) {
100 Ret += DataLayout::getManglingComponent(ST.getTargetTriple());
102 // Pointers are 32 bits and aligned to 32 bits.
105 // On thumb, i16,i18 and i1 have natural aligment requirements, but we try to
108 Ret += "-i1:8:32-i8:8:32-i16:16:32";
110 // ABIs other than APCS have 64 bit integers with natural alignment.
111 if (!ST.isAPCS_ABI())
114 // We have 64 bits floats. The APCS ABI requires them to be aligned to 32
115 // bits, others to 64 bits. We always try to align to 64 bits.
119 // We have 128 and 64 bit vectors. The APCS ABI aligns them to 32 bits, others
120 // to 64. We always ty to give them natural alignment.
122 Ret += "-v64:32:64-v128:32:128";
124 Ret += "-v128:64:128";
126 // Try to align aggregates to 32 bits (the default is 64 bits, which has no
127 // particular hardware support on 32-bit ARM).
130 // Integer registers are 32 bits.
133 // The stack is 128 bit aligned on NaCl, 64 bit aligned on AAPCS and 32 bit
134 // aligned everywhere else.
135 if (ST.isTargetNaCl())
137 else if (ST.isAAPCS_ABI())
145 /// initializeSubtargetDependencies - Initializes using a CPU and feature string
146 /// so that we can use initializer lists for subtarget initialization.
147 ARMSubtarget &ARMSubtarget::initializeSubtargetDependencies(StringRef CPU,
149 initializeEnvironment();
150 initSubtargetFeatures(CPU, FS);
154 ARMSubtarget::ARMSubtarget(const std::string &TT, const std::string &CPU,
155 const std::string &FS, const TargetMachine &TM,
157 : ARMGenSubtargetInfo(TT, CPU, FS), ARMProcFamily(Others),
158 ARMProcClass(None), stackAlignment(4), CPUString(CPU), IsLittle(IsLittle),
159 TargetTriple(TT), Options(TM.Options), TargetABI(ARM_ABI_UNKNOWN),
160 DL(computeDataLayout(initializeSubtargetDependencies(CPU, FS))),
162 InstrInfo(isThumb1Only()
163 ? (ARMBaseInstrInfo *)new Thumb1InstrInfo(*this)
165 ? (ARMBaseInstrInfo *)new ARMInstrInfo(*this)
166 : (ARMBaseInstrInfo *)new Thumb2InstrInfo(*this)),
168 FrameLowering(!isThumb1Only()
169 ? new ARMFrameLowering(*this)
170 : (ARMFrameLowering *)new Thumb1FrameLowering(*this)) {}
172 void ARMSubtarget::initializeEnvironment() {
186 UseNEONForSinglePrecisionFP = false;
187 UseMulOps = UseFusedMulOps;
189 HasVMLxForwarding = false;
194 IsR9Reserved = ReserveR9;
196 SupportsTailCall = false;
199 HasHardwareDivide = false;
200 HasHardwareDivideInARM = false;
201 HasT2ExtractPack = false;
202 HasDataBarrier = false;
203 Pref32BitThumb = false;
204 AvoidCPSRPartialUpdate = false;
205 AvoidMOVsShifterOperand = false;
207 HasMPExtension = false;
208 HasVirtualization = false;
211 HasTrustZone = false;
214 HasZeroCycleZeroing = false;
215 AllowsUnalignedMem = false;
218 UnsafeFPMath = false;
221 void ARMSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) {
222 if (CPUString.empty()) {
223 if (isTargetIOS() && TargetTriple.getArchName().endswith("v7s"))
224 // Default to the Swift CPU when targeting armv7s/thumbv7s.
227 CPUString = "generic";
230 // Insert the architecture feature derived from the target triple into the
231 // feature string. This is important for setting features that are implied
232 // based on the architecture version.
233 std::string ArchFS = ARM_MC::ParseARMTriple(TargetTriple.getTriple(),
237 ArchFS = ArchFS + "," + FS.str();
241 ParseSubtargetFeatures(CPUString, ArchFS);
243 // FIXME: This used enable V6T2 support implicitly for Thumb2 mode.
244 // Assert this for now to make the change obvious.
245 assert(hasV6T2Ops() || !hasThumb2());
247 // Keep a pointer to static instruction cost data for the specified CPU.
248 SchedModel = getSchedModelForCPU(CPUString);
250 // Initialize scheduling itinerary for the specified CPU.
251 InstrItins = getInstrItineraryForCPU(CPUString);
253 if (TargetABI == ARM_ABI_UNKNOWN) {
254 switch (TargetTriple.getEnvironment()) {
255 case Triple::Android:
258 case Triple::GNUEABI:
259 case Triple::GNUEABIHF:
260 TargetABI = ARM_ABI_AAPCS;
263 if ((isTargetIOS() && isMClass()) ||
264 (TargetTriple.isOSBinFormatMachO() &&
265 TargetTriple.getOS() == Triple::UnknownOS))
266 TargetABI = ARM_ABI_AAPCS;
268 TargetABI = ARM_ABI_APCS;
273 // FIXME: this is invalid for WindowsCE
274 if (isTargetWindows()) {
275 TargetABI = ARM_ABI_AAPCS;
284 UseMovt = hasV6T2Ops() && ArmUseMOVT;
286 if (isTargetMachO()) {
287 IsR9Reserved = ReserveR9 || !HasV6Ops;
288 SupportsTailCall = !isTargetIOS() || !getTargetTriple().isOSVersionLT(5, 0);
290 IsR9Reserved = ReserveR9;
291 SupportsTailCall = !isThumb1Only();
294 if (Align == DefaultAlign) {
295 // Assume pre-ARMv6 doesn't support unaligned accesses.
297 // ARMv6 may or may not support unaligned accesses depending on the
298 // SCTLR.U bit, which is architecture-specific. We assume ARMv6
299 // Darwin and NetBSD targets support unaligned accesses, and others don't.
301 // ARMv7 always has SCTLR.U set to 1, but it has a new SCTLR.A bit
302 // which raises an alignment fault on unaligned accesses. Linux
303 // defaults this bit to 0 and handles it as a system-wide (not
304 // per-process) setting. It is therefore safe to assume that ARMv7+
305 // Linux targets support unaligned accesses. The same goes for NaCl.
307 // The above behavior is consistent with GCC.
309 (hasV7Ops() && (isTargetLinux() || isTargetNaCl() ||
310 isTargetNetBSD())) ||
311 (hasV6Ops() && (isTargetMachO() || isTargetNetBSD()));
313 AllowsUnalignedMem = !(Align == StrictAlign);
316 // No v6M core supports unaligned memory access (v6M ARM ARM A3.2)
318 AllowsUnalignedMem = false;
322 RestrictIT = hasV8Ops() ? true : false;
332 // NEON f32 ops are non-IEEE 754 compliant. Darwin is ok with it by default.
333 uint64_t Bits = getFeatureBits();
334 if ((Bits & ARM::ProcA5 || Bits & ARM::ProcA8) && // Where this matters
335 (Options.UnsafeFPMath || isTargetDarwin()))
336 UseNEONForSinglePrecisionFP = true;
339 /// GVIsIndirectSymbol - true if the GV will be accessed via an indirect symbol.
341 ARMSubtarget::GVIsIndirectSymbol(const GlobalValue *GV,
342 Reloc::Model RelocM) const {
343 if (RelocM == Reloc::Static)
346 // Materializable GVs (in JIT lazy compilation mode) do not require an extra
348 bool isDecl = GV->hasAvailableExternallyLinkage();
349 if (GV->isDeclaration() && !GV->isMaterializable())
352 if (!isTargetMachO()) {
353 // Extra load is needed for all externally visible.
354 if (GV->hasLocalLinkage() || GV->hasHiddenVisibility())
358 if (RelocM == Reloc::PIC_) {
359 // If this is a strong reference to a definition, it is definitely not
361 if (!isDecl && !GV->isWeakForLinker())
364 // Unless we have a symbol with hidden visibility, we have to go through a
365 // normal $non_lazy_ptr stub because this symbol might be resolved late.
366 if (!GV->hasHiddenVisibility()) // Non-hidden $non_lazy_ptr reference.
369 // If symbol visibility is hidden, we have a stub for common symbol
370 // references and external declarations.
371 if (isDecl || GV->hasCommonLinkage())
372 // Hidden $non_lazy_ptr reference.
377 // If this is a strong reference to a definition, it is definitely not
379 if (!isDecl && !GV->isWeakForLinker())
382 // Unless we have a symbol with hidden visibility, we have to go through a
383 // normal $non_lazy_ptr stub because this symbol might be resolved late.
384 if (!GV->hasHiddenVisibility()) // Non-hidden $non_lazy_ptr reference.
392 unsigned ARMSubtarget::getMispredictionPenalty() const {
393 return SchedModel.MispredictPenalty;
396 bool ARMSubtarget::hasSinCos() const {
397 return getTargetTriple().isiOS() && !getTargetTriple().isOSVersionLT(7, 0);
400 // This overrides the PostRAScheduler bit in the SchedModel for any CPU.
401 bool ARMSubtarget::enablePostMachineScheduler() const {
402 return (!isThumb() || hasThumb2());
405 bool ARMSubtarget::enableAtomicExpand() const {
406 return hasAnyDataBarrier() && !isThumb1Only();
409 bool ARMSubtarget::useMovt(const MachineFunction &MF) const {
410 // NOTE Windows on ARM needs to use mov.w/mov.t pairs to materialise 32-bit
411 // immediates as it is inherently position independent, and may be out of
413 return UseMovt && (isTargetWindows() ||
414 !MF.getFunction()->getAttributes().hasAttribute(
415 AttributeSet::FunctionIndex, Attribute::MinSize));