1 //===-- ARMSubtarget.cpp - ARM Subtarget Information ------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the ARM specific subclass of TargetSubtarget.
12 //===----------------------------------------------------------------------===//
14 #include "ARMSubtarget.h"
15 #include "ARMGenSubtarget.inc"
16 #include "llvm/GlobalValue.h"
17 #include "llvm/Target/TargetOptions.h"
18 #include "llvm/Support/CommandLine.h"
19 #include "llvm/ADT/SmallVector.h"
23 ReserveR9("arm-reserve-r9", cl::Hidden,
24 cl::desc("Reserve R9, making it unavailable as GPR"));
27 UseMOVT("arm-use-movt",
28 cl::init(true), cl::Hidden);
30 ARMSubtarget::ARMSubtarget(const std::string &TT, const std::string &FS,
34 , UseNEONForSinglePrecisionFP(false)
38 , PostRAScheduler(false)
39 , IsR9Reserved(ReserveR9)
43 , CPUString("generic")
44 , TargetType(isELF) // Default to ELF unless otherwise specified.
45 , TargetABI(ARM_ABI_APCS) {
46 // default to soft float ABI
47 if (FloatABIType == FloatABI::Default)
48 FloatABIType = FloatABI::Soft;
50 // Determine default and user specified characteristics
52 // Parse features string.
53 CPUString = ParseSubtargetFeatures(FS, CPUString);
55 // When no arch is specified either by CPU or by attributes, make the default
57 if (CPUString == "generic" && (FS.empty() || FS == "generic"))
60 // Set the boolean corresponding to the current target triple, or the default
61 // if one cannot be determined, to true.
62 unsigned Len = TT.length();
65 if (Len >= 5 && TT.substr(0, 4) == "armv")
67 else if (Len >= 6 && TT.substr(0, 5) == "thumb") {
69 if (Len >= 7 && TT[5] == 'v')
73 unsigned SubVer = TT[Idx];
74 if (SubVer >= '7' && SubVer <= '9') {
76 } else if (SubVer == '6') {
78 if (Len >= Idx+3 && TT[Idx+1] == 't' && TT[Idx+2] == '2')
79 ARMArchVersion = V6T2;
80 } else if (SubVer == '5') {
82 if (Len >= Idx+3 && TT[Idx+1] == 't' && TT[Idx+2] == 'e')
83 ARMArchVersion = V5TE;
84 } else if (SubVer == '4') {
85 if (Len >= Idx+2 && TT[Idx+1] == 't')
92 // Thumb2 implies at least V6T2.
93 if (ARMArchVersion >= V6T2)
95 else if (ThumbMode >= Thumb2)
96 ARMArchVersion = V6T2;
99 if (TT.find("-darwin") != std::string::npos)
101 TargetType = isDarwin;
104 if (TT.find("eabi") != std::string::npos)
105 TargetABI = ARM_ABI_AAPCS;
110 if (isTargetDarwin())
111 IsR9Reserved = ReserveR9 | (ARMArchVersion < V6);
113 if (!isThumb() || hasThumb2())
114 PostRAScheduler = true;
117 /// GVIsIndirectSymbol - true if the GV will be accessed via an indirect symbol.
119 ARMSubtarget::GVIsIndirectSymbol(GlobalValue *GV, Reloc::Model RelocM) const {
120 if (RelocM == Reloc::Static)
123 // Materializable GVs (in JIT lazy compilation mode) do not require an extra
125 bool isDecl = GV->isDeclaration() && !GV->isMaterializable();
127 if (!isTargetDarwin()) {
128 // Extra load is needed for all externally visible.
129 if (GV->hasLocalLinkage() || GV->hasHiddenVisibility())
133 if (RelocM == Reloc::PIC_) {
134 // If this is a strong reference to a definition, it is definitely not
136 if (!isDecl && !GV->isWeakForLinker())
139 // Unless we have a symbol with hidden visibility, we have to go through a
140 // normal $non_lazy_ptr stub because this symbol might be resolved late.
141 if (!GV->hasHiddenVisibility()) // Non-hidden $non_lazy_ptr reference.
144 // If symbol visibility is hidden, we have a stub for common symbol
145 // references and external declarations.
146 if (isDecl || GV->hasCommonLinkage())
147 // Hidden $non_lazy_ptr reference.
152 // If this is a strong reference to a definition, it is definitely not
154 if (!isDecl && !GV->isWeakForLinker())
157 // Unless we have a symbol with hidden visibility, we have to go through a
158 // normal $non_lazy_ptr stub because this symbol might be resolved late.
159 if (!GV->hasHiddenVisibility()) // Non-hidden $non_lazy_ptr reference.
167 bool ARMSubtarget::enablePostRAScheduler(
168 CodeGenOpt::Level OptLevel,
169 TargetSubtarget::AntiDepBreakMode& Mode,
170 RegClassVector& CriticalPathRCs) const {
171 Mode = TargetSubtarget::ANTIDEP_CRITICAL;
172 CriticalPathRCs.clear();
173 CriticalPathRCs.push_back(&ARM::GPRRegClass);
174 return PostRAScheduler && OptLevel >= CodeGenOpt::Default;