1 //===-- ARMSubtarget.cpp - ARM Subtarget Information ------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the ARM specific subclass of TargetSubtarget.
12 //===----------------------------------------------------------------------===//
14 #include "ARMSubtarget.h"
15 #include "ARMGenSubtarget.inc"
16 #include "ARMBaseRegisterInfo.h"
17 #include "llvm/GlobalValue.h"
18 #include "llvm/Support/CommandLine.h"
19 #include "llvm/ADT/SmallVector.h"
23 ReserveR9("arm-reserve-r9", cl::Hidden,
24 cl::desc("Reserve R9, making it unavailable as GPR"));
27 DarwinUseMOVT("arm-darwin-use-movt", cl::init(true), cl::Hidden);
30 StrictAlign("arm-strict-align", cl::Hidden,
31 cl::desc("Disallow all unaligned memory accesses"));
33 ARMSubtarget::ARMSubtarget(const std::string &TT, const std::string &CPU,
34 const std::string &FS, bool isT)
36 , ARMProcFamily(Others)
38 , UseNEONForSinglePrecisionFP(false)
40 , HasVMLxForwarding(false)
45 , PostRAScheduler(false)
46 , IsR9Reserved(ReserveR9)
50 , HasHardwareDivide(false)
51 , HasT2ExtractPack(false)
52 , HasDataBarrier(false)
53 , Pref32BitThumb(false)
54 , AvoidCPSRPartialUpdate(false)
55 , HasMPExtension(false)
57 , AllowsUnalignedMem(false)
61 , TargetABI(ARM_ABI_APCS) {
62 // Determine default and user specified characteristics
64 // When no arch is specified either by CPU or by attributes, make the default
66 const char *ARMArchFeature = "";
67 if (CPUString.empty())
68 CPUString = "generic";
69 if (CPUString == "generic" && (FS.empty() || FS == "generic")) {
71 ARMArchFeature = "+v4t";
74 // Set the boolean corresponding to the current target triple, or the default
75 // if one cannot be determined, to true.
76 unsigned Len = TT.length();
79 if (Len >= 5 && TT.substr(0, 4) == "armv")
81 else if (Len >= 6 && TT.substr(0, 5) == "thumb") {
83 if (Len >= 7 && TT[5] == 'v')
87 unsigned SubVer = TT[Idx];
88 if (SubVer >= '7' && SubVer <= '9') {
90 ARMArchFeature = "+v7a";
91 if (Len >= Idx+2 && TT[Idx+1] == 'm') {
93 ARMArchFeature = "+v7m";
95 } else if (SubVer == '6') {
97 ARMArchFeature = "+v6";
98 if (Len >= Idx+3 && TT[Idx+1] == 't' && TT[Idx+2] == '2') {
99 ARMArchVersion = V6T2;
100 ARMArchFeature = "+v6t2";
102 } else if (SubVer == '5') {
103 ARMArchVersion = V5T;
104 ARMArchFeature = "+v5t";
105 if (Len >= Idx+3 && TT[Idx+1] == 't' && TT[Idx+2] == 'e') {
106 ARMArchVersion = V5TE;
107 ARMArchFeature = "+v5te";
109 } else if (SubVer == '4') {
110 if (Len >= Idx+2 && TT[Idx+1] == 't') {
111 ARMArchVersion = V4T;
112 ARMArchFeature = "+v4t";
120 if (TT.find("eabi") != std::string::npos)
121 TargetABI = ARM_ABI_AAPCS;
123 // Insert the architecture feature derived from the target triple into the
124 // feature string. This is important for setting features that are implied
125 // based on the architecture version.
126 std::string FSWithArch = std::string(ARMArchFeature);
127 if (FSWithArch.empty())
129 else if (!FS.empty())
130 FSWithArch = FSWithArch + "," + FS;
131 ParseSubtargetFeatures(FSWithArch, CPUString);
133 // After parsing Itineraries, set ItinData.IssueWidth.
136 // Thumb2 implies at least V6T2.
137 if (ARMArchVersion >= V6T2)
139 else if (ThumbMode >= Thumb2)
140 ARMArchVersion = V6T2;
145 if (!isTargetDarwin())
146 UseMovt = hasV6T2Ops();
148 IsR9Reserved = ReserveR9 | (ARMArchVersion < V6);
149 UseMovt = DarwinUseMOVT && hasV6T2Ops();
152 if (!isThumb() || hasThumb2())
153 PostRAScheduler = true;
155 // v6+ may or may not support unaligned mem access depending on the system
157 if (!StrictAlign && hasV6Ops() && isTargetDarwin())
158 AllowsUnalignedMem = true;
161 /// GVIsIndirectSymbol - true if the GV will be accessed via an indirect symbol.
163 ARMSubtarget::GVIsIndirectSymbol(const GlobalValue *GV,
164 Reloc::Model RelocM) const {
165 if (RelocM == Reloc::Static)
168 // Materializable GVs (in JIT lazy compilation mode) do not require an extra
170 bool isDecl = GV->hasAvailableExternallyLinkage();
171 if (GV->isDeclaration() && !GV->isMaterializable())
174 if (!isTargetDarwin()) {
175 // Extra load is needed for all externally visible.
176 if (GV->hasLocalLinkage() || GV->hasHiddenVisibility())
180 if (RelocM == Reloc::PIC_) {
181 // If this is a strong reference to a definition, it is definitely not
183 if (!isDecl && !GV->isWeakForLinker())
186 // Unless we have a symbol with hidden visibility, we have to go through a
187 // normal $non_lazy_ptr stub because this symbol might be resolved late.
188 if (!GV->hasHiddenVisibility()) // Non-hidden $non_lazy_ptr reference.
191 // If symbol visibility is hidden, we have a stub for common symbol
192 // references and external declarations.
193 if (isDecl || GV->hasCommonLinkage())
194 // Hidden $non_lazy_ptr reference.
199 // If this is a strong reference to a definition, it is definitely not
201 if (!isDecl && !GV->isWeakForLinker())
204 // Unless we have a symbol with hidden visibility, we have to go through a
205 // normal $non_lazy_ptr stub because this symbol might be resolved late.
206 if (!GV->hasHiddenVisibility()) // Non-hidden $non_lazy_ptr reference.
214 unsigned ARMSubtarget::getMispredictionPenalty() const {
215 // If we have a reasonable estimate of the pipeline depth, then we can
216 // estimate the penalty of a misprediction based on that.
219 else if (isCortexA9())
222 // Otherwise, just return a sensible default.
226 void ARMSubtarget::computeIssueWidth() {
227 unsigned allStage1Units = 0;
228 for (const InstrItinerary *itin = InstrItins.Itineraries;
229 itin->FirstStage != ~0U; ++itin) {
230 const InstrStage *IS = InstrItins.Stages + itin->FirstStage;
231 allStage1Units |= IS->getUnits();
233 InstrItins.IssueWidth = 0;
234 while (allStage1Units) {
235 ++InstrItins.IssueWidth;
236 // clear the lowest bit
237 allStage1Units ^= allStage1Units & ~(allStage1Units - 1);
239 assert(InstrItins.IssueWidth <= 2 && "itinerary bug, too many stage 1 units");
242 bool ARMSubtarget::enablePostRAScheduler(
243 CodeGenOpt::Level OptLevel,
244 TargetSubtarget::AntiDepBreakMode& Mode,
245 RegClassVector& CriticalPathRCs) const {
246 Mode = TargetSubtarget::ANTIDEP_CRITICAL;
247 CriticalPathRCs.clear();
248 CriticalPathRCs.push_back(&ARM::GPRRegClass);
249 return PostRAScheduler && OptLevel >= CodeGenOpt::Default;