lib/Target/ARM/ARMScheduleV7.td

   1 //===- ARMScheduleV7.td - ARM v7 Scheduling Definitions ----*- tablegen -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file defines the itinerary class data for the ARM v7 processors.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 //
  15 // Scheduling information derived from "Cortex-A8 Technical Reference Manual".
  16 //
  17 // Dual issue pipeline represented by FU_Pipe0 | FU_Pipe1
  18 //
  19 def CortexA8Itineraries : ProcessorItineraries<[
  20
  21   // Two fully-pipelined integer ALU pipelines
  22   //
  23   // No operand cycles
  24   InstrItinData<IIC_iALUx    , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>]>,
  25   //
  26   // Binary Instructions that produce a result
  27   InstrItinData<IIC_iALUi    , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [2, 2]>,
  28   InstrItinData<IIC_iALUr    , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [2, 2, 2]>,
  29   InstrItinData<IIC_iALUsi   , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [2, 2, 1]>,
  30   InstrItinData<IIC_iALUsr   , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [2, 2, 1, 1]>,
  31   //
  32   // Unary Instructions that produce a result
  33   InstrItinData<IIC_iUNAr    , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [2, 2]>,
  34   InstrItinData<IIC_iUNAsi   , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [2, 1]>,
  35   InstrItinData<IIC_iUNAsr   , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [2, 1, 1]>,
  36   //
  37   // Compare instructions
  38   InstrItinData<IIC_iCMPi    , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [2]>,
  39   InstrItinData<IIC_iCMPr    , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [2, 2]>,
  40   InstrItinData<IIC_iCMPsi   , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [2, 1]>,
  41   InstrItinData<IIC_iCMPsr   , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [2, 1, 1]>,
  42   //
  43   // Move instructions, unconditional
  44   InstrItinData<IIC_iMOVi    , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [1]>,
  45   InstrItinData<IIC_iMOVr    , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [1, 1]>,
  46   InstrItinData<IIC_iMOVsi   , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [1, 1]>,
  47   InstrItinData<IIC_iMOVsr   , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [1, 1, 1]>,
  48   //
  49   // Move instructions, conditional
  50   InstrItinData<IIC_iCMOVi   , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [2]>,
  51   InstrItinData<IIC_iCMOVr   , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [2, 1]>,
  52   InstrItinData<IIC_iCMOVsi  , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [2, 1]>,
  53   InstrItinData<IIC_iCMOVsr  , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [2, 1, 1]>,
  54
  55   // Integer multiply pipeline
  56   // Result written in E5, but that is relative to the last cycle of multicycle,
  57   // so we use 6 for those cases
  58   //
  59   InstrItinData<IIC_iMUL16   , [InstrStage<1, [FU_Pipe0]>], [5, 1, 1]>,
  60   InstrItinData<IIC_iMAC16   , [InstrStage<1, [FU_Pipe1], 0>,
  61                                 InstrStage<2, [FU_Pipe0]>], [6, 1, 1, 4]>,
  62   InstrItinData<IIC_iMUL32   , [InstrStage<1, [FU_Pipe1], 0>,
  63                                 InstrStage<2, [FU_Pipe0]>], [6, 1, 1]>,
  64   InstrItinData<IIC_iMAC32   , [InstrStage<1, [FU_Pipe1], 0>,
  65                                 InstrStage<2, [FU_Pipe0]>], [6, 1, 1, 4]>,
  66   InstrItinData<IIC_iMUL64   , [InstrStage<2, [FU_Pipe1], 0>,
  67                                 InstrStage<3, [FU_Pipe0]>], [6, 6, 1, 1]>,
  68   InstrItinData<IIC_iMAC64   , [InstrStage<2, [FU_Pipe1], 0>,
  69                                 InstrStage<3, [FU_Pipe0]>], [6, 6, 1, 1]>,
  70
  71   // Integer load pipeline
  72   //
  73   // loads have an extra cycle of latency, but are fully pipelined
  74   // use FU_Issue to enforce the 1 load/store per cycle limit
  75   //
  76   // Immediate offset
  77   InstrItinData<IIC_iLoadi   , [InstrStage<1, [FU_Issue], 0>,
  78                                 InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
  79                                 InstrStage<1, [FU_LdSt0]>], [3, 1]>,
  80   //
  81   // Register offset
  82   InstrItinData<IIC_iLoadr   , [InstrStage<1, [FU_Issue], 0>,
  83                                 InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
  84                                 InstrStage<1, [FU_LdSt0]>], [3, 1, 1]>,
  85   //
  86   // Scaled register offset, issues over 2 cycles
  87   InstrItinData<IIC_iLoadsi  , [InstrStage<2, [FU_Issue], 0>,
  88                                 InstrStage<1, [FU_Pipe0], 0>,
  89                                 InstrStage<1, [FU_Pipe1]>,
  90                                 InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
  91                                 InstrStage<1, [FU_LdSt0]>], [4, 1, 1]>,
  92   //
  93   // Immediate offset with update
  94   InstrItinData<IIC_iLoadiu  , [InstrStage<1, [FU_Issue], 0>,
  95                                 InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
  96                                 InstrStage<1, [FU_LdSt0]>], [3, 2, 1]>,
  97   //
  98   // Register offset with update
  99   InstrItinData<IIC_iLoadru  , [InstrStage<1, [FU_Issue], 0>,
 100                                 InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 101                                 InstrStage<1, [FU_LdSt0]>], [3, 2, 1, 1]>,
 102   //
 103   // Scaled register offset with update, issues over 2 cycles
 104   InstrItinData<IIC_iLoadsiu , [InstrStage<2, [FU_Issue], 0>,
 105                                 InstrStage<1, [FU_Pipe0], 0>,
 106                                 InstrStage<1, [FU_Pipe1]>,
 107                                 InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 108                                 InstrStage<1, [FU_LdSt0]>], [4, 3, 1, 1]>,
 109   //
 110   // Load multiple
 111   InstrItinData<IIC_iLoadm   , [InstrStage<2, [FU_Issue], 0>,
 112                                 InstrStage<2, [FU_Pipe0], 0>,
 113                                 InstrStage<2, [FU_Pipe1]>,
 114                                 InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 115                                 InstrStage<1, [FU_LdSt0]>]>,
 116
 117   // Integer store pipeline
 118   //
 119   // use FU_Issue to enforce the 1 load/store per cycle limit
 120   //
 121   // Immediate offset
 122   InstrItinData<IIC_iStorei  , [InstrStage<1, [FU_Issue], 0>,
 123                                 InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 124                                 InstrStage<1, [FU_LdSt0]>], [3, 1]>,
 125   //
 126   // Register offset
 127   InstrItinData<IIC_iStorer  , [InstrStage<1, [FU_Issue], 0>,
 128                                 InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 129                                 InstrStage<1, [FU_LdSt0]>], [3, 1, 1]>,
 130   //
 131   // Scaled register offset, issues over 2 cycles
 132   InstrItinData<IIC_iStoresi , [InstrStage<2, [FU_Issue], 0>,
 133                                 InstrStage<1, [FU_Pipe0], 0>,
 134                                 InstrStage<1, [FU_Pipe1]>,
 135                                 InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 136                                 InstrStage<1, [FU_LdSt0]>], [3, 1, 1]>,
 137   //
 138   // Immediate offset with update
 139   InstrItinData<IIC_iStoreiu , [InstrStage<1, [FU_Issue], 0>,
 140                                 InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 141                                 InstrStage<1, [FU_LdSt0]>], [2, 3, 1]>,
 142   //
 143   // Register offset with update
 144   InstrItinData<IIC_iStoreru  , [InstrStage<1, [FU_Issue], 0>,
 145                                 InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 146                                 InstrStage<1, [FU_LdSt0]>], [2, 3, 1, 1]>,
 147   //
 148   // Scaled register offset with update, issues over 2 cycles
 149   InstrItinData<IIC_iStoresiu, [InstrStage<2, [FU_Issue], 0>,
 150                                 InstrStage<1, [FU_Pipe0], 0>,
 151                                 InstrStage<1, [FU_Pipe1]>,
 152                                 InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 153                                 InstrStage<1, [FU_LdSt0]>], [3, 3, 1, 1]>,
 154   //
 155   // Store multiple
 156   InstrItinData<IIC_iStorem  , [InstrStage<2, [FU_Issue], 0>,
 157                                 InstrStage<2, [FU_Pipe0], 0>,
 158                                 InstrStage<2, [FU_Pipe1]>,
 159                                 InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 160                                 InstrStage<1, [FU_LdSt0]>]>,
 161
 162   // Branch
 163   //
 164   // no delay slots, so the latency of a branch is unimportant
 165   InstrItinData<IIC_Br      , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>]>,
 166
 167   // VFP
 168   // Issue through integer pipeline, and execute in NEON unit. We assume
 169   // RunFast mode so that NFP pipeline is used for single-precision when
 170   // possible.
 171   //
 172   // FP Special Register to Integer Register File Move
 173   InstrItinData<IIC_fpSTAT , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 174                               InstrStage<1, [FU_NLSPipe]>]>,
 175   //
 176   // Single-precision FP Unary
 177   InstrItinData<IIC_fpUNA32 , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 178                                InstrStage<1, [FU_NPipe]>], [7, 1]>,
 179   //
 180   // Double-precision FP Unary
 181   InstrItinData<IIC_fpUNA64 , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 182                                InstrStage<4, [FU_NPipe], 0>,
 183                                InstrStage<4, [FU_NLSPipe]>], [4, 1]>,
 184   //
 185   // Single-precision FP Compare
 186   InstrItinData<IIC_fpCMP32 , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 187                                InstrStage<1, [FU_NPipe]>], [1, 1]>,
 188   //
 189   // Double-precision FP Compare
 190   InstrItinData<IIC_fpCMP64 , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 191                                InstrStage<4, [FU_NPipe], 0>,
 192                                InstrStage<4, [FU_NLSPipe]>], [4, 1]>,
 193   //
 194   // Single to Double FP Convert
 195   InstrItinData<IIC_fpCVTSD , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 196                                InstrStage<7, [FU_NPipe], 0>,
 197                                InstrStage<7, [FU_NLSPipe]>], [7, 1]>,
 198   //
 199   // Double to Single FP Convert
 200   InstrItinData<IIC_fpCVTDS , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 201                                InstrStage<5, [FU_NPipe], 0>,
 202                                InstrStage<5, [FU_NLSPipe]>], [5, 1]>,
 203   //
 204   // Single-Precision FP to Integer Convert
 205   InstrItinData<IIC_fpCVTSI , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 206                                InstrStage<1, [FU_NPipe]>], [7, 1]>,
 207   //
 208   // Double-Precision FP to Integer Convert
 209   InstrItinData<IIC_fpCVTDI , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 210                                InstrStage<8, [FU_NPipe], 0>,
 211                                InstrStage<8, [FU_NLSPipe]>], [8, 1]>,
 212   //
 213   // Integer to Single-Precision FP Convert
 214   InstrItinData<IIC_fpCVTIS , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 215                                InstrStage<1, [FU_NPipe]>], [7, 1]>,
 216   //
 217   // Integer to Double-Precision FP Convert
 218   InstrItinData<IIC_fpCVTID , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 219                                InstrStage<8, [FU_NPipe], 0>,
 220                                InstrStage<8, [FU_NLSPipe]>], [8, 1]>,
 221   //
 222   // Single-precision FP ALU
 223   InstrItinData<IIC_fpALU32 , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 224                                InstrStage<1, [FU_NPipe]>], [7, 1, 1]>,
 225   //
 226   // Double-precision FP ALU
 227   InstrItinData<IIC_fpALU64 , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 228                                InstrStage<9, [FU_NPipe], 0>,
 229                                InstrStage<9, [FU_NLSPipe]>], [9, 1, 1]>,
 230   //
 231   // Single-precision FP Multiply
 232   InstrItinData<IIC_fpMUL32 , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 233                                InstrStage<1, [FU_NPipe]>], [7, 1, 1]>,
 234   //
 235   // Double-precision FP Multiply
 236   InstrItinData<IIC_fpMUL64 , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 237                                InstrStage<11, [FU_NPipe], 0>,
 238                                InstrStage<11, [FU_NLSPipe]>], [11, 1, 1]>,
 239   //
 240   // Single-precision FP MAC
 241   InstrItinData<IIC_fpMAC32 , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 242                                InstrStage<1, [FU_NPipe]>], [7, 2, 1, 1]>,
 243   //
 244   // Double-precision FP MAC
 245   InstrItinData<IIC_fpMAC64 , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 246                                InstrStage<19, [FU_NPipe], 0>,
 247                                InstrStage<19, [FU_NLSPipe]>], [19, 2, 1, 1]>,
 248   //
 249   // Single-precision FP DIV
 250   InstrItinData<IIC_fpDIV32 , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 251                                InstrStage<20, [FU_NPipe], 0>,
 252                                InstrStage<20, [FU_NLSPipe]>], [20, 1, 1]>,
 253   //
 254   // Double-precision FP DIV
 255   InstrItinData<IIC_fpDIV64 , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 256                                InstrStage<29, [FU_NPipe], 0>,
 257                                InstrStage<29, [FU_NLSPipe]>], [29, 1, 1]>,
 258   //
 259   // Single-precision FP SQRT
 260   InstrItinData<IIC_fpSQRT32, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 261                                InstrStage<19, [FU_NPipe], 0>,
 262                                InstrStage<19, [FU_NLSPipe]>], [19, 1]>,
 263   //
 264   // Double-precision FP SQRT
 265   InstrItinData<IIC_fpSQRT64, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 266                                InstrStage<29, [FU_NPipe], 0>,
 267                                InstrStage<29, [FU_NLSPipe]>], [29, 1]>,
 268   //
 269   // Single-precision FP Load
 270   // use FU_Issue to enforce the 1 load/store per cycle limit
 271   InstrItinData<IIC_fpLoad32, [InstrStage<1, [FU_Issue], 0>,
 272                                InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 273                                InstrStage<1, [FU_LdSt0], 0>,
 274                                InstrStage<1, [FU_NLSPipe]>]>,
 275   //
 276   // Double-precision FP Load
 277   // use FU_Issue to enforce the 1 load/store per cycle limit
 278   InstrItinData<IIC_fpLoad64, [InstrStage<2, [FU_Issue], 0>,
 279                                InstrStage<1, [FU_Pipe0], 0>,
 280                                InstrStage<1, [FU_Pipe1]>,
 281                                InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 282                                InstrStage<1, [FU_LdSt0], 0>,
 283                                InstrStage<1, [FU_NLSPipe]>]>,
 284   //
 285   // FP Load Multiple
 286   // use FU_Issue to enforce the 1 load/store per cycle limit
 287   InstrItinData<IIC_fpLoadm,  [InstrStage<3, [FU_Issue], 0>,
 288                                InstrStage<2, [FU_Pipe0], 0>,
 289                                InstrStage<2, [FU_Pipe1]>,
 290                                InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 291                                InstrStage<1, [FU_LdSt0], 0>,
 292                                InstrStage<1, [FU_NLSPipe]>]>,
 293   //
 294   // Single-precision FP Store
 295   // use FU_Issue to enforce the 1 load/store per cycle limit
 296   InstrItinData<IIC_fpStore32,[InstrStage<1, [FU_Issue], 0>,
 297                                InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 298                                InstrStage<1, [FU_LdSt0], 0>,
 299                                InstrStage<1, [FU_NLSPipe]>]>,
 300   //
 301   // Double-precision FP Store
 302   // use FU_Issue to enforce the 1 load/store per cycle limit
 303   InstrItinData<IIC_fpStore64,[InstrStage<2, [FU_Issue], 0>,
 304                                InstrStage<1, [FU_Pipe0], 0>,
 305                                InstrStage<1, [FU_Pipe1]>,
 306                                InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 307                                InstrStage<1, [FU_LdSt0], 0>,
 308                                InstrStage<1, [FU_NLSPipe]>]>,
 309   //
 310   // FP Store Multiple
 311   // use FU_Issue to enforce the 1 load/store per cycle limit
 312   InstrItinData<IIC_fpStorem, [InstrStage<3, [FU_Issue], 0>,
 313                                InstrStage<2, [FU_Pipe0], 0>,
 314                                InstrStage<2, [FU_Pipe1]>,
 315                                InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 316                                InstrStage<1, [FU_LdSt0], 0>,
 317                                InstrStage<1, [FU_NLSPipe]>]>,
 318
 319   // NEON
 320   // Issue through integer pipeline, and execute in NEON unit.
 321   //
 322   // VLD1
 323   // FIXME: We don't model this instruction properly
 324   InstrItinData<IIC_VLD1,     [InstrStage<1, [FU_Issue], 0>,
 325                                InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 326                                InstrStage<1, [FU_LdSt0], 0>,
 327                                InstrStage<1, [FU_NLSPipe]>]>,
 328   //
 329   // VLD2
 330   // FIXME: We don't model this instruction properly
 331   InstrItinData<IIC_VLD2,     [InstrStage<1, [FU_Issue], 0>,
 332                                InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 333                                InstrStage<1, [FU_LdSt0], 0>,
 334                                InstrStage<1, [FU_NLSPipe]>], [2, 2, 1]>,
 335   //
 336   // VLD3
 337   // FIXME: We don't model this instruction properly
 338   InstrItinData<IIC_VLD3,     [InstrStage<1, [FU_Issue], 0>,
 339                                InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 340                                InstrStage<1, [FU_LdSt0], 0>,
 341                                InstrStage<1, [FU_NLSPipe]>], [2, 2, 2, 1]>,
 342   //
 343   // VLD4
 344   // FIXME: We don't model this instruction properly
 345   InstrItinData<IIC_VLD4,     [InstrStage<1, [FU_Issue], 0>,
 346                                InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 347                                InstrStage<1, [FU_LdSt0], 0>,
 348                                InstrStage<1, [FU_NLSPipe]>], [2, 2, 2, 2, 1]>,
 349   //
 350   // VST
 351   // FIXME: We don't model this instruction properly
 352   InstrItinData<IIC_VST,      [InstrStage<1, [FU_Issue], 0>,
 353                                InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 354                                InstrStage<1, [FU_LdSt0], 0>,
 355                                InstrStage<1, [FU_NLSPipe]>]>,
 356   //
 357   // Double-register FP Unary
 358   InstrItinData<IIC_VUNAD,    [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 359                                InstrStage<1, [FU_NPipe]>], [5, 2]>,
 360   //
 361   // Quad-register FP Unary
 362   // Result written in N5, but that is relative to the last cycle of multicycle,
 363   // so we use 6 for those cases
 364   InstrItinData<IIC_VUNAQ,    [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 365                                InstrStage<2, [FU_NPipe]>], [6, 2]>,
 366   //
 367   // Double-register FP Binary
 368   InstrItinData<IIC_VBIND,    [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 369                                InstrStage<1, [FU_NPipe]>], [5, 2, 2]>,
 370   //
 371   // Quad-register FP Binary
 372   // Result written in N5, but that is relative to the last cycle of multicycle,
 373   // so we use 6 for those cases
 374   InstrItinData<IIC_VBINQ,    [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 375                                InstrStage<2, [FU_NPipe]>], [6, 2, 2]>,
 376   //
 377   // Move Immediate
 378   InstrItinData<IIC_VMOVImm,  [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 379                                InstrStage<1, [FU_NPipe]>], [3]>,
 380   //
 381   // Double-register Permute Move
 382   InstrItinData<IIC_VMOVD,    [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 383                                InstrStage<1, [FU_NLSPipe]>], [2, 1]>,
 384   //
 385   // Quad-register Permute Move
 386   // Result written in N2, but that is relative to the last cycle of multicycle,
 387   // so we use 3 for those cases
 388   InstrItinData<IIC_VMOVQ,    [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 389                                InstrStage<2, [FU_NLSPipe]>], [3, 1]>,
 390   //
 391   // Integer to Single-precision Move
 392   InstrItinData<IIC_VMOVIS ,  [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 393                                InstrStage<1, [FU_NLSPipe]>], [2, 1]>,
 394   //
 395   // Integer to Double-precision Move
 396   InstrItinData<IIC_VMOVID ,  [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 397                                InstrStage<1, [FU_NLSPipe]>], [2, 1, 1]>,
 398   //
 399   // Single-precision to Integer Move
 400   InstrItinData<IIC_VMOVSI ,  [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 401                                InstrStage<1, [FU_NLSPipe]>], [20, 1]>,
 402   //
 403   // Double-precision to Integer Move
 404   InstrItinData<IIC_VMOVDI ,  [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 405                                InstrStage<1, [FU_NLSPipe]>], [20, 20, 1]>,
 406   //
 407   // Integer to Lane Move
 408   InstrItinData<IIC_VMOVISL , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 409                                InstrStage<2, [FU_NLSPipe]>], [3, 1, 1]>,
 410   //
 411   // Double-register Permute
 412   InstrItinData<IIC_VPERMD,   [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 413                                InstrStage<1, [FU_NLSPipe]>], [2, 2, 1, 1]>,
 414   //
 415   // Quad-register Permute
 416   // Result written in N2, but that is relative to the last cycle of multicycle,
 417   // so we use 3 for those cases
 418   InstrItinData<IIC_VPERMQ,   [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 419                                InstrStage<2, [FU_NLSPipe]>], [3, 3, 1, 1]>,
 420   //
 421   // Quad-register Permute (3 cycle issue)
 422   // Result written in N2, but that is relative to the last cycle of multicycle,
 423   // so we use 4 for those cases
 424   InstrItinData<IIC_VPERMQ3,  [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 425                                InstrStage<1, [FU_NLSPipe]>,
 426                                InstrStage<1, [FU_NPipe], 0>,
 427                                InstrStage<2, [FU_NLSPipe]>], [4, 4, 1, 1]>,
 428   //
 429   // Double-register FP Multiple-Accumulate
 430   InstrItinData<IIC_VMACD,    [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 431                                InstrStage<1, [FU_NPipe]>], [9, 3, 2, 2]>,
 432   //
 433   // Quad-register FP Multiple-Accumulate
 434   // Result written in N9, but that is relative to the last cycle of multicycle,
 435   // so we use 10 for those cases
 436   InstrItinData<IIC_VMACQ,    [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 437                                InstrStage<2, [FU_NPipe]>], [10, 3, 2, 2]>,
 438   //
 439   // Double-register Reciprical Step
 440   InstrItinData<IIC_VRECSD,   [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 441                                InstrStage<1, [FU_NPipe]>], [9, 2, 2]>,
 442   //
 443   // Quad-register Reciprical Step
 444   InstrItinData<IIC_VRECSQ,   [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 445                                InstrStage<2, [FU_NPipe]>], [10, 2, 2]>,
 446   //
 447   // Double-register Integer Count
 448   InstrItinData<IIC_VCNTiD,   [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 449                                InstrStage<1, [FU_NPipe]>], [3, 2, 2]>,
 450   //
 451   // Quad-register Integer Count
 452   // Result written in N3, but that is relative to the last cycle of multicycle,
 453   // so we use 4 for those cases
 454   InstrItinData<IIC_VCNTiQ,   [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 455                                InstrStage<2, [FU_NPipe]>], [4, 2, 2]>,
 456   //
 457   // Double-register Integer Unary
 458   InstrItinData<IIC_VUNAiD,   [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 459                                InstrStage<1, [FU_NPipe]>], [4, 2]>,
 460   //
 461   // Quad-register Integer Unary
 462   InstrItinData<IIC_VUNAiQ,   [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 463                                InstrStage<1, [FU_NPipe]>], [4, 2]>,
 464   //
 465   // Double-register Integer Q-Unary
 466   InstrItinData<IIC_VQUNAiD,  [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 467                                InstrStage<1, [FU_NPipe]>], [4, 1]>,
 468   //
 469   // Quad-register Integer CountQ-Unary
 470   InstrItinData<IIC_VQUNAiQ,  [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 471                                InstrStage<1, [FU_NPipe]>], [4, 1]>,
 472   //
 473   // Double-register Integer Binary
 474   InstrItinData<IIC_VBINiD,   [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 475                                InstrStage<1, [FU_NPipe]>], [3, 2, 2]>,
 476   //
 477   // Quad-register Integer Binary
 478   InstrItinData<IIC_VBINiQ,   [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 479                                InstrStage<1, [FU_NPipe]>], [3, 2, 2]>,
 480   //
 481   // Double-register Integer Binary (4 cycle)
 482   InstrItinData<IIC_VBINi4D,  [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 483                                InstrStage<1, [FU_NPipe]>], [4, 2, 1]>,
 484   //
 485   // Quad-register Integer Binary (4 cycle)
 486   InstrItinData<IIC_VBINi4Q,  [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 487                                InstrStage<1, [FU_NPipe]>], [4, 2, 1]>,
 488
 489   //
 490   // Double-register Integer Subtract
 491   InstrItinData<IIC_VSUBiD,   [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 492                                InstrStage<1, [FU_NPipe]>], [3, 2, 1]>,
 493   //
 494   // Quad-register Integer Subtract
 495   InstrItinData<IIC_VSUBiQ,   [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 496                                InstrStage<1, [FU_NPipe]>], [3, 2, 1]>,
 497   //
 498   // Double-register Integer Subtract
 499   InstrItinData<IIC_VSUBi4D,  [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 500                                InstrStage<1, [FU_NPipe]>], [4, 2, 1]>,
 501   //
 502   // Quad-register Integer Subtract
 503   InstrItinData<IIC_VSUBi4Q,  [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 504                                InstrStage<1, [FU_NPipe]>], [4, 2, 1]>,
 505   //
 506   // Double-register Integer Shift
 507   InstrItinData<IIC_VSHLiD,   [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 508                                InstrStage<1, [FU_NPipe]>], [3, 1, 1]>,
 509   //
 510   // Quad-register Integer Shift
 511   InstrItinData<IIC_VSHLiQ,   [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 512                                InstrStage<2, [FU_NPipe]>], [4, 1, 1]>,
 513   //
 514   // Double-register Integer Shift (4 cycle)
 515   InstrItinData<IIC_VSHLi4D,   [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 516                                InstrStage<1, [FU_NPipe]>], [4, 1, 1]>,
 517   //
 518   // Quad-register Integer Shift (4 cycle)
 519   InstrItinData<IIC_VSHLi4Q,   [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 520                                InstrStage<2, [FU_NPipe]>], [5, 1, 1]>,
 521   //
 522   // Double-register Integer Pair Add Long
 523   InstrItinData<IIC_VPALiD,   [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 524                                InstrStage<1, [FU_NPipe]>], [6, 3, 1]>,
 525   //
 526   // Quad-register Integer Pair Add Long
 527   InstrItinData<IIC_VPALiQ,   [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 528                                InstrStage<2, [FU_NPipe]>], [7, 3, 1]>,
 529   //
 530   // Double-register Absolute Difference and Accumulate
 531   InstrItinData<IIC_VABAD,    [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 532                                InstrStage<1, [FU_NPipe]>], [6, 3, 2, 1]>,
 533   //
 534   // Quad-register Absolute Difference and Accumulate
 535   InstrItinData<IIC_VABAQ,    [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 536                                InstrStage<2, [FU_NPipe]>], [6, 3, 2, 1]>,
 537
 538   //
 539   // Double-register Integer Multiply (.8, .16)
 540   InstrItinData<IIC_VMULi16D, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 541                                InstrStage<1, [FU_NPipe]>], [6, 2, 2]>,
 542   //
 543   // Double-register Integer Multiply (.32)
 544   InstrItinData<IIC_VMULi32D, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 545                                InstrStage<2, [FU_NPipe]>], [7, 2, 1]>,
 546   //
 547   // Quad-register Integer Multiply (.8, .16)
 548   InstrItinData<IIC_VMULi16Q, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 549                                InstrStage<2, [FU_NPipe]>], [7, 2, 2]>,
 550   //
 551   // Quad-register Integer Multiply (.32)
 552   InstrItinData<IIC_VMULi32Q, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 553                                InstrStage<1, [FU_NPipe]>,
 554                                InstrStage<2, [FU_NLSPipe], 0>,
 555                                InstrStage<3, [FU_NPipe]>], [9, 2, 1]>,
 556   //
 557   // Double-register Integer Multiply-Accumulate (.8, .16)
 558   InstrItinData<IIC_VMACi16D, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 559                                InstrStage<1, [FU_NPipe]>], [6, 3, 2, 2]>,
 560   //
 561   // Double-register Integer Multiply-Accumulate (.32)
 562   InstrItinData<IIC_VMACi32D, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 563                                InstrStage<2, [FU_NPipe]>], [7, 3, 2, 1]>,
 564   //
 565   // Quad-register Integer Multiply-Accumulate (.8, .16)
 566   InstrItinData<IIC_VMACi16Q, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 567                                InstrStage<2, [FU_NPipe]>], [7, 3, 2, 2]>,
 568   //
 569   // Quad-register Integer Multiply-Accumulate (.32)
 570   InstrItinData<IIC_VMACi32Q, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 571                                InstrStage<1, [FU_NPipe]>,
 572                                InstrStage<2, [FU_NLSPipe], 0>,
 573                                InstrStage<3, [FU_NPipe]>], [9, 3, 2, 1]>,
 574   //
 575   // Double-register VEXT
 576   InstrItinData<IIC_VEXTD,    [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 577                                InstrStage<1, [FU_NLSPipe]>], [2, 1, 1]>,
 578   //
 579   // Quad-register VEXT
 580   InstrItinData<IIC_VEXTQ,    [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 581                                InstrStage<2, [FU_NLSPipe]>], [3, 1, 1]>,
 582   //
 583   // VTB
 584   InstrItinData<IIC_VTB1,     [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 585                                InstrStage<2, [FU_NLSPipe]>], [3, 2, 1]>,
 586   InstrItinData<IIC_VTB2,     [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 587                                InstrStage<2, [FU_NLSPipe]>], [3, 2, 2, 1]>,
 588   InstrItinData<IIC_VTB3,     [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 589                                InstrStage<1, [FU_NLSPipe]>,
 590                                InstrStage<1, [FU_NPipe], 0>,
 591                                InstrStage<2, [FU_NLSPipe]>], [4, 2, 2, 3, 1]>,
 592   InstrItinData<IIC_VTB4,     [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 593                                InstrStage<1, [FU_NLSPipe]>,
 594                                InstrStage<1, [FU_NPipe], 0>,
 595                                InstrStage<2, [FU_NLSPipe]>], [4, 2, 2, 3, 3, 1]>,
 596   //
 597   // VTBX
 598   InstrItinData<IIC_VTBX1,    [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 599                                InstrStage<2, [FU_NLSPipe]>], [3, 1, 2, 1]>,
 600   InstrItinData<IIC_VTBX2,    [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 601                                InstrStage<2, [FU_NLSPipe]>], [3, 1, 2, 2, 1]>,
 602   InstrItinData<IIC_VTBX3,    [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 603                                InstrStage<1, [FU_NLSPipe]>,
 604                                InstrStage<1, [FU_NPipe], 0>,
 605                                InstrStage<2, [FU_NLSPipe]>], [4, 1, 2, 2, 3, 1]>,
 606   InstrItinData<IIC_VTBX4,    [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 607                                InstrStage<1, [FU_NLSPipe]>,
 608                                InstrStage<1, [FU_NPipe], 0>,
 609                                InstrStage<2, [FU_NLSPipe]>], [4, 1, 2, 2, 3, 3, 1]>
 610 ]>;
 611
 612 //
 613 // Ad-hoc scheduling information derived from pretty vague "Cortex-A9 Technical
 614 // Reference Manual".
 615 //
 616 // Dual issue pipeline represented by FU_Pipe0 | FU_Pipe1
 617 //
 618 def CortexA9Itineraries : ProcessorItineraries<[
 619   // VFP and NEON shares the same register file. This means that every VFP
 620   // instruction should wait for full completion of the consecutive NEON
 621   // instruction and vice-versa. We model this behavior with two artificial FUs:
 622   // DRegsVFP and DRegsVFP.
 623   //
 624   // Every VFP instruction:
 625   //  - Acquires DRegsVFP resource for 1 cycle
 626   //  - Reserves DRegsN resource for the whole duration (including time to
 627   //    register file writeback!).
 628   // Every NEON instruction does the same but with FUs swapped.
 629   //
 630   // Since the reserved FU cannot be acquired this models precisly "cross-domain"
 631   // stalls.
 632
 633   // VFP
 634   // Issue through integer pipeline, and execute in NEON unit.
 635
 636   // FP Special Register to Integer Register File Move
 637   InstrItinData<IIC_fpSTAT , [InstrStage<1, [FU_DRegsVFP], 0, Required>,
 638                               InstrStage<2, [FU_DRegsN],   0, Reserved>,
 639                               InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 640                               InstrStage<1, [FU_NPipe]>]>,
 641   //
 642   // Single-precision FP Unary
 643   InstrItinData<IIC_fpUNA32 , [InstrStage<1, [FU_DRegsVFP], 0, Required>,
 644                                // Extra latency cycles since wbck is 2 cycles
 645                                InstrStage<3, [FU_DRegsN],   0, Reserved>,
 646                                InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 647                                InstrStage<1, [FU_NPipe]>], [1, 1]>,
 648   //
 649   // Double-precision FP Unary
 650   InstrItinData<IIC_fpUNA64 , [InstrStage<1, [FU_DRegsVFP], 0, Required>,
 651                                // Extra latency cycles since wbck is 2 cycles
 652                                InstrStage<3, [FU_DRegsN],   0, Reserved>,
 653                                InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 654                                InstrStage<1, [FU_NPipe]>], [1, 1]>,
 655
 656   //
 657   // Single-precision FP Compare
 658   InstrItinData<IIC_fpCMP32 , [InstrStage<1, [FU_DRegsVFP], 0, Required>,
 659                                // Extra latency cycles since wbck is 4 cycles
 660                                InstrStage<5, [FU_DRegsN],   0, Reserved>,
 661                                InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 662                                InstrStage<1, [FU_NPipe]>], [1, 1]>,
 663   //
 664   // Double-precision FP Compare
 665   InstrItinData<IIC_fpCMP64 , [InstrStage<1, [FU_DRegsVFP], 0, Required>,
 666                                // Extra latency cycles since wbck is 4 cycles
 667                                InstrStage<5, [FU_DRegsN],   0, Reserved>,
 668                                InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 669                                InstrStage<1, [FU_NPipe]>], [1, 1]>,
 670   //
 671   // Single to Double FP Convert
 672   InstrItinData<IIC_fpCVTSD , [InstrStage<1, [FU_DRegsVFP], 0, Required>,
 673                                InstrStage<5, [FU_DRegsN],   0, Reserved>,
 674                                InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 675                                InstrStage<1, [FU_NPipe]>], [4, 1]>,
 676   //
 677   // Double to Single FP Convert
 678   InstrItinData<IIC_fpCVTDS , [InstrStage<1, [FU_DRegsVFP], 0, Required>,
 679                                InstrStage<5, [FU_DRegsN],   0, Reserved>,
 680                                InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 681                                InstrStage<1, [FU_NPipe]>], [4, 1]>,
 682
 683   //
 684   // Single to Half FP Convert
 685   InstrItinData<IIC_fpCVTSH , [InstrStage<1, [FU_DRegsVFP], 0, Required>,
 686                                InstrStage<5, [FU_DRegsN],   0, Reserved>,
 687                                InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 688                                InstrStage<1, [FU_NPipe]>], [4, 1]>,
 689   //
 690   // Half to Single FP Convert
 691   InstrItinData<IIC_fpCVTHS , [InstrStage<1, [FU_DRegsVFP], 0, Required>,
 692                                InstrStage<3, [FU_DRegsN],   0, Reserved>,
 693                                InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 694                                InstrStage<1, [FU_NPipe]>], [2, 1]>,
 695
 696   //
 697   // Single-Precision FP to Integer Convert
 698   InstrItinData<IIC_fpCVTSI , [InstrStage<1, [FU_DRegsVFP], 0, Required>,
 699                                InstrStage<5, [FU_DRegsN],   0, Reserved>,
 700                                InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 701                                InstrStage<1, [FU_NPipe]>], [4, 1]>,
 702   //
 703   // Double-Precision FP to Integer Convert
 704   InstrItinData<IIC_fpCVTDI , [InstrStage<1, [FU_DRegsVFP], 0, Required>,
 705                                InstrStage<5, [FU_DRegsN],   0, Reserved>,
 706                                InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 707                                InstrStage<1, [FU_NPipe]>], [4, 1]>,
 708   //
 709   // Integer to Single-Precision FP Convert
 710   InstrItinData<IIC_fpCVTIS , [InstrStage<1, [FU_DRegsVFP], 0, Required>,
 711                                InstrStage<5, [FU_DRegsN],   0, Reserved>,
 712                                InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 713                                InstrStage<1, [FU_NPipe]>], [4, 1]>,
 714   //
 715   // Integer to Double-Precision FP Convert
 716   InstrItinData<IIC_fpCVTID , [InstrStage<1, [FU_DRegsVFP], 0, Required>,
 717                                InstrStage<5, [FU_DRegsN],   0, Reserved>,
 718                                InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 719                                InstrStage<1, [FU_NPipe]>], [4, 1]>,
 720   //
 721   // Single-precision FP ALU
 722   InstrItinData<IIC_fpALU32 , [InstrStage<1, [FU_DRegsVFP], 0, Required>,
 723                                InstrStage<5, [FU_DRegsN],   0, Reserved>,
 724                                InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 725                                InstrStage<1, [FU_NPipe]>], [4, 1, 1]>,
 726   //
 727   // Double-precision FP ALU
 728   InstrItinData<IIC_fpALU64 , [InstrStage<1, [FU_DRegsVFP], 0, Required>,
 729                                InstrStage<5, [FU_DRegsN],   0, Reserved>,
 730                                InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 731                                InstrStage<1, [FU_NPipe]>], [4, 1, 1]>,
 732   //
 733   // Single-precision FP Multiply
 734   InstrItinData<IIC_fpMUL32 , [InstrStage<1, [FU_DRegsVFP], 0, Required>,
 735                                InstrStage<6, [FU_DRegsN],   0, Reserved>,
 736                                InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 737                                InstrStage<1, [FU_NPipe]>], [5, 1, 1]>,
 738   //
 739   // Double-precision FP Multiply
 740   InstrItinData<IIC_fpMUL64 , [InstrStage<1, [FU_DRegsVFP], 0, Required>,
 741                                InstrStage<7, [FU_DRegsN],   0, Reserved>,
 742                                InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 743                                InstrStage<2, [FU_NPipe]>], [6, 1, 1]>,
 744   //
 745   // Single-precision FP MAC
 746   InstrItinData<IIC_fpMAC32 , [InstrStage<1, [FU_DRegsVFP], 0, Required>,
 747                                InstrStage<9, [FU_DRegsN],   0, Reserved>,
 748                                InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 749                                InstrStage<1, [FU_NPipe]>], [8, 0, 1, 1]>,
 750   //
 751   // Double-precision FP MAC
 752   InstrItinData<IIC_fpMAC64 , [InstrStage<1,  [FU_DRegsVFP], 0, Required>,
 753                                InstrStage<10, [FU_DRegsN],  0, Reserved>,
 754                                InstrStage<1,  [FU_Pipe0, FU_Pipe1]>,
 755                                InstrStage<2,  [FU_NPipe]>], [9, 0, 1, 1]>,
 756   //
 757   // Single-precision FP DIV
 758   InstrItinData<IIC_fpDIV32 , [InstrStage<1,  [FU_DRegsVFP], 0, Required>,
 759                                InstrStage<16, [FU_DRegsN],  0, Reserved>,
 760                                InstrStage<1,  [FU_Pipe0, FU_Pipe1]>,
 761                                InstrStage<10, [FU_NPipe]>], [15, 1, 1]>,
 762   //
 763   // Double-precision FP DIV
 764   InstrItinData<IIC_fpDIV64 , [InstrStage<1,  [FU_DRegsVFP], 0, Required>,
 765                                InstrStage<26, [FU_DRegsN],  0, Reserved>,
 766                                InstrStage<1,  [FU_Pipe0, FU_Pipe1]>,
 767                                InstrStage<20, [FU_NPipe]>], [25, 1, 1]>,
 768   //
 769   // Single-precision FP SQRT
 770   InstrItinData<IIC_fpSQRT32, [InstrStage<1,  [FU_DRegsVFP], 0, Required>,
 771                                InstrStage<18, [FU_DRegsN],   0, Reserved>,
 772                                InstrStage<1,   [FU_Pipe0, FU_Pipe1]>,
 773                                InstrStage<13,  [FU_NPipe]>], [17, 1]>,
 774   //
 775   // Double-precision FP SQRT
 776   InstrItinData<IIC_fpSQRT64, [InstrStage<1,  [FU_DRegsVFP], 0, Required>,
 777                                InstrStage<33, [FU_DRegsN],   0, Reserved>,
 778                                InstrStage<1,  [FU_Pipe0, FU_Pipe1]>,
 779                                InstrStage<28, [FU_NPipe]>], [32, 1]>,
 780
 781   //
 782   // Integer to Single-precision Move
 783   InstrItinData<IIC_fpMOVIS,  [InstrStage<1, [FU_DRegsVFP], 0, Required>,
 784                                // Extra 1 latency cycle since wbck is 2 cycles
 785                                InstrStage<3, [FU_DRegsN],   0, Reserved>,
 786                                InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 787                                InstrStage<1, [FU_NPipe]>], [1, 1]>,
 788   //
 789   // Integer to Double-precision Move
 790   InstrItinData<IIC_fpMOVID,  [InstrStage<1, [FU_DRegsVFP], 0, Required>,
 791                                // Extra 1 latency cycle since wbck is 2 cycles
 792                                InstrStage<3, [FU_DRegsN],   0, Reserved>,
 793                                InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 794                                InstrStage<1, [FU_NPipe]>], [1, 1, 1]>,
 795   //
 796   // Single-precision to Integer Move
 797   InstrItinData<IIC_fpMOVSI,  [InstrStage<1, [FU_DRegsVFP], 0, Required>,
 798                                InstrStage<2, [FU_DRegsN],   0, Reserved>,
 799                                InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 800                                InstrStage<1, [FU_NPipe]>], [1, 1]>,
 801   //
 802   // Double-precision to Integer Move
 803   InstrItinData<IIC_fpMOVDI,  [InstrStage<1, [FU_DRegsVFP], 0, Required>,
 804                                InstrStage<2, [FU_DRegsN],   0, Reserved>,
 805                                InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 806                                InstrStage<1, [FU_NPipe]>], [1, 1, 1]>,
 807   //
 808   // Single-precision FP Load
 809   // use FU_Issue to enforce the 1 load/store per cycle limit
 810   InstrItinData<IIC_fpLoad32, [InstrStage<1, [FU_DRegsVFP], 0, Required>,
 811                                InstrStage<2, [FU_DRegsN],   0, Reserved>,
 812                                InstrStage<1, [FU_Issue], 0>,
 813                                InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 814                                InstrStage<1, [FU_LdSt0], 0>,
 815                                InstrStage<1, [FU_NPipe]>]>,
 816   //
 817   // Double-precision FP Load
 818   // use FU_Issue to enforce the 1 load/store per cycle limit
 819   InstrItinData<IIC_fpLoad64, [InstrStage<1, [FU_DRegsVFP], 0, Required>,
 820                                InstrStage<2, [FU_DRegsN],   0, Reserved>,
 821                                InstrStage<1, [FU_Issue], 0>,
 822                                InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 823                                InstrStage<1, [FU_LdSt0], 0>,
 824                                InstrStage<1, [FU_NPipe]>]>,
 825   //
 826   // FP Load Multiple
 827   // use FU_Issue to enforce the 1 load/store per cycle limit
 828   InstrItinData<IIC_fpLoadm,  [InstrStage<1, [FU_DRegsVFP], 0, Required>,
 829                                InstrStage<2, [FU_DRegsN],   0, Reserved>,
 830                                InstrStage<1, [FU_Issue], 0>,
 831                                InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 832                                InstrStage<1, [FU_LdSt0], 0>,
 833                                InstrStage<1, [FU_NPipe]>]>,
 834   //
 835   // Single-precision FP Store
 836   // use FU_Issue to enforce the 1 load/store per cycle limit
 837   InstrItinData<IIC_fpStore32,[InstrStage<1, [FU_DRegsVFP], 0, Required>,
 838                                InstrStage<2, [FU_DRegsN],   0, Reserved>,
 839                                InstrStage<1, [FU_Issue], 0>,
 840                                InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 841                                InstrStage<1, [FU_LdSt0], 0>,
 842                                InstrStage<1, [FU_NPipe]>]>,
 843   //
 844   // Double-precision FP Store
 845   // use FU_Issue to enforce the 1 load/store per cycle limit
 846   InstrItinData<IIC_fpStore64,[InstrStage<1, [FU_DRegsVFP], 0, Required>,
 847                                InstrStage<2, [FU_DRegsN],   0, Reserved>,
 848                                InstrStage<1, [FU_Issue], 0>,
 849                                InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 850                                InstrStage<1, [FU_LdSt0], 0>,
 851                                InstrStage<1, [FU_NPipe]>]>,
 852   //
 853   // FP Store Multiple
 854   // use FU_Issue to enforce the 1 load/store per cycle limit
 855   InstrItinData<IIC_fpStorem, [InstrStage<1, [FU_DRegsVFP], 0, Required>,
 856                                InstrStage<2, [FU_DRegsN],   0, Reserved>,
 857                                InstrStage<1, [FU_Issue], 0>,
 858                                InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 859                                InstrStage<1, [FU_LdSt0], 0>,
 860                                InstrStage<1, [FU_NPipe]>]>,
 861   // NEON
 862   // Issue through integer pipeline, and execute in NEON unit.
 863   // FIXME: Neon pipeline and LdSt unit are multiplexed.
 864   //        Add some syntactic sugar to model this!
 865   // VLD1
 866   // FIXME: We don't model this instruction properly
 867   InstrItinData<IIC_VLD1,     [InstrStage<1, [FU_DRegsN],   0, Required>,
 868                                InstrStage<7, [FU_DRegsVFP], 0, Reserved>,
 869                                InstrStage<1, [FU_Issue], 0>,
 870                                InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 871                                InstrStage<1, [FU_LdSt0], 0>,
 872                                InstrStage<1, [FU_NPipe]>]>,
 873   //
 874   // VLD2
 875   // FIXME: We don't model this instruction properly
 876   InstrItinData<IIC_VLD2,     [InstrStage<1, [FU_DRegsN],   0, Required>,
 877                                // Extra latency cycles since wbck is 6 cycles
 878                                InstrStage<7, [FU_DRegsVFP], 0, Reserved>,
 879                                InstrStage<1, [FU_Issue], 0>,
 880                                InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 881                                InstrStage<1, [FU_LdSt0], 0>,
 882                                InstrStage<1, [FU_NPipe]>], [2, 2, 1]>,
 883   //
 884   // VLD3
 885   // FIXME: We don't model this instruction properly
 886   InstrItinData<IIC_VLD3,     [InstrStage<1, [FU_DRegsN],   0, Required>,
 887                                // Extra latency cycles since wbck is 6 cycles
 888                                InstrStage<7, [FU_DRegsVFP], 0, Reserved>,
 889                                InstrStage<1, [FU_Issue], 0>,
 890                                InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 891                                InstrStage<1, [FU_LdSt0], 0>,
 892                                InstrStage<1, [FU_NPipe]>], [2, 2, 2, 1]>,
 893   //
 894   // VLD4
 895   // FIXME: We don't model this instruction properly
 896   InstrItinData<IIC_VLD4,     [InstrStage<1, [FU_DRegsN],   0, Required>,
 897                                // Extra latency cycles since wbck is 6 cycles
 898                                InstrStage<7, [FU_DRegsVFP], 0, Reserved>,
 899                                InstrStage<1, [FU_Issue], 0>,
 900                                InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 901                                InstrStage<1, [FU_LdSt0], 0>,
 902                                InstrStage<1, [FU_NPipe]>], [2, 2, 2, 2, 1]>,
 903   //
 904   // VST
 905   // FIXME: We don't model this instruction properly
 906   InstrItinData<IIC_VST,      [InstrStage<1, [FU_DRegsN],   0, Required>,
 907                                // Extra latency cycles since wbck is 6 cycles
 908                                InstrStage<7, [FU_DRegsVFP], 0, Reserved>,
 909                                InstrStage<1, [FU_Issue], 0>,
 910                                InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 911                                InstrStage<1, [FU_LdSt0], 0>,
 912                                InstrStage<1, [FU_NPipe]>]>,
 913   //
 914   // Double-register Integer Unary
 915   InstrItinData<IIC_VUNAiD,   [InstrStage<1, [FU_DRegsN],   0, Required>,
 916                                // Extra latency cycles since wbck is 6 cycles
 917                                InstrStage<7, [FU_DRegsVFP], 0, Reserved>,
 918                                InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 919                                InstrStage<1, [FU_NPipe]>], [4, 2]>,
 920   //
 921   // Quad-register Integer Unary
 922   InstrItinData<IIC_VUNAiQ,   [InstrStage<1, [FU_DRegsN],   0, Required>,
 923                                // Extra latency cycles since wbck is 6 cycles
 924                                InstrStage<7, [FU_DRegsVFP], 0, Reserved>,
 925                                InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 926                                InstrStage<1, [FU_NPipe]>], [4, 2]>,
 927   //
 928   // Double-register Integer Q-Unary
 929   InstrItinData<IIC_VQUNAiD,  [InstrStage<1, [FU_DRegsN],   0, Required>,
 930                                // Extra latency cycles since wbck is 6 cycles
 931                                InstrStage<7, [FU_DRegsVFP], 0, Reserved>,
 932                                InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 933                                InstrStage<1, [FU_NPipe]>], [4, 1]>,
 934   //
 935   // Quad-register Integer CountQ-Unary
 936   InstrItinData<IIC_VQUNAiQ,  [InstrStage<1, [FU_DRegsN],   0, Required>,
 937                                // Extra latency cycles since wbck is 6 cycles
 938                                InstrStage<7, [FU_DRegsVFP], 0, Reserved>,
 939                                InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 940                                InstrStage<1, [FU_NPipe]>], [4, 1]>,
 941   //
 942   // Double-register Integer Binary
 943   InstrItinData<IIC_VBINiD,   [InstrStage<1, [FU_DRegsN],   0, Required>,
 944                                // Extra latency cycles since wbck is 6 cycles
 945                                InstrStage<7, [FU_DRegsVFP], 0, Reserved>,
 946                                InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 947                                InstrStage<1, [FU_NPipe]>], [3, 2, 2]>,
 948   //
 949   // Quad-register Integer Binary
 950   InstrItinData<IIC_VBINiQ,   [InstrStage<1, [FU_DRegsN],   0, Required>,
 951                                // Extra latency cycles since wbck is 6 cycles
 952                                InstrStage<7, [FU_DRegsVFP], 0, Reserved>,
 953                                InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 954                                InstrStage<1, [FU_NPipe]>], [3, 2, 2]>,
 955   //
 956   // Double-register Integer Subtract
 957   InstrItinData<IIC_VSUBiD,   [InstrStage<1, [FU_DRegsN],   0, Required>,
 958                                // Extra latency cycles since wbck is 6 cycles
 959                                InstrStage<7, [FU_DRegsVFP], 0, Reserved>,
 960                                InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 961                                InstrStage<1, [FU_NPipe]>], [3, 2, 1]>,
 962   //
 963   // Quad-register Integer Subtract
 964   InstrItinData<IIC_VSUBiQ,   [InstrStage<1, [FU_DRegsN],   0, Required>,
 965                                // Extra latency cycles since wbck is 6 cycles
 966                                InstrStage<7, [FU_DRegsVFP], 0, Reserved>,
 967                                InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 968                                InstrStage<1, [FU_NPipe]>], [3, 2, 1]>,
 969   //
 970   // Double-register Integer Shift
 971   InstrItinData<IIC_VSHLiD,   [InstrStage<1, [FU_DRegsN],   0, Required>,
 972                                // Extra latency cycles since wbck is 6 cycles
 973                                InstrStage<7, [FU_DRegsVFP], 0, Reserved>,
 974                                InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 975                                InstrStage<1, [FU_NPipe]>], [3, 1, 1]>,
 976   //
 977   // Quad-register Integer Shift
 978   InstrItinData<IIC_VSHLiQ,   [InstrStage<1, [FU_DRegsN],   0, Required>,
 979                                // Extra latency cycles since wbck is 6 cycles
 980                                InstrStage<7, [FU_DRegsVFP], 0, Reserved>,
 981                                InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 982                                InstrStage<1, [FU_NPipe]>], [3, 1, 1]>,
 983   //
 984   // Double-register Integer Shift (4 cycle)
 985   InstrItinData<IIC_VSHLi4D,  [InstrStage<1, [FU_DRegsN],   0, Required>,
 986                                // Extra latency cycles since wbck is 6 cycles
 987                                InstrStage<7, [FU_DRegsVFP], 0, Reserved>,
 988                                InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 989                                InstrStage<1, [FU_NPipe]>], [4, 1, 1]>,
 990   //
 991   // Quad-register Integer Shift (4 cycle)
 992   InstrItinData<IIC_VSHLi4Q,  [InstrStage<1, [FU_DRegsN],   0, Required>,
 993                                // Extra latency cycles since wbck is 6 cycles
 994                                InstrStage<7, [FU_DRegsVFP], 0, Reserved>,
 995                                InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
 996                                InstrStage<1, [FU_NPipe]>], [4, 1, 1]>,
 997   //
 998   // Double-register Integer Binary (4 cycle)
 999   InstrItinData<IIC_VBINi4D,  [InstrStage<1, [FU_DRegsN],   0, Required>,
1000                                // Extra latency cycles since wbck is 6 cycles
1001                                InstrStage<7, [FU_DRegsVFP], 0, Reserved>,
1002                                InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
1003                                InstrStage<1, [FU_NPipe]>], [4, 2, 2]>,
1004   //
1005   // Quad-register Integer Binary (4 cycle)
1006   InstrItinData<IIC_VBINi4Q,  [InstrStage<1, [FU_DRegsN],   0, Required>,
1007                                // Extra latency cycles since wbck is 6 cycles
1008                                InstrStage<7, [FU_DRegsVFP], 0, Reserved>,
1009                                InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
1010                                InstrStage<1, [FU_NPipe]>], [4, 2, 2]>,
1011   //
1012   // Double-register Integer Subtract (4 cycle)
1013   InstrItinData<IIC_VSUBiD,   [InstrStage<1, [FU_DRegsN],   0, Required>,
1014                                // Extra latency cycles since wbck is 6 cycles
1015                                InstrStage<7, [FU_DRegsVFP], 0, Reserved>,
1016                                InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
1017                                InstrStage<1, [FU_NPipe]>], [4, 2, 1]>,
1018   //
1019   // Quad-register Integer Subtract (4 cycle)
1020   InstrItinData<IIC_VSUBiQ,   [InstrStage<1, [FU_DRegsN],   0, Required>,
1021                                // Extra latency cycles since wbck is 6 cycles
1022                                InstrStage<7, [FU_DRegsVFP], 0, Reserved>,
1023                                InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
1024                                InstrStage<1, [FU_NPipe]>], [4, 2, 1]>,
1025
1026   //
1027   // Double-register Integer Count
1028   InstrItinData<IIC_VCNTiD,   [InstrStage<1, [FU_DRegsN],   0, Required>,
1029                                // Extra latency cycles since wbck is 6 cycles
1030                                InstrStage<7, [FU_DRegsVFP], 0, Reserved>,
1031                                InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
1032                                InstrStage<1, [FU_NPipe]>], [3, 2, 2]>,
1033   //
1034   // Quad-register Integer Count
1035   // Result written in N3, but that is relative to the last cycle of multicycle,
1036   // so we use 4 for those cases
1037   InstrItinData<IIC_VCNTiQ,   [InstrStage<1, [FU_DRegsN],   0, Required>,
1038                                // Extra latency cycles since wbck is 7 cycles
1039                                InstrStage<8, [FU_DRegsVFP], 0, Reserved>,
1040                                InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
1041                                InstrStage<2, [FU_NPipe]>], [4, 2, 2]>,
1042   //
1043   // Double-register Absolute Difference and Accumulate
1044   InstrItinData<IIC_VABAD,    [InstrStage<1, [FU_DRegsN],   0, Required>,
1045                                // Extra latency cycles since wbck is 6 cycles
1046                                InstrStage<7, [FU_DRegsVFP], 0, Reserved>,
1047                                InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
1048                                InstrStage<1, [FU_NPipe]>], [6, 3, 2, 1]>,
1049   //
1050   // Quad-register Absolute Difference and Accumulate
1051   InstrItinData<IIC_VABAQ,    [InstrStage<1, [FU_DRegsN],   0, Required>,
1052                                // Extra latency cycles since wbck is 6 cycles
1053                                InstrStage<7, [FU_DRegsVFP], 0, Reserved>,
1054                                InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
1055                                InstrStage<2, [FU_NPipe]>], [6, 3, 2, 1]>,
1056   //
1057   // Double-register Integer Pair Add Long
1058   InstrItinData<IIC_VPALiD,   [InstrStage<1, [FU_DRegsN],   0, Required>,
1059                                // Extra latency cycles since wbck is 6 cycles
1060                                InstrStage<7, [FU_DRegsVFP], 0, Reserved>,
1061                                InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
1062                                InstrStage<1, [FU_NPipe]>], [6, 3, 1]>,
1063   //
1064   // Quad-register Integer Pair Add Long
1065   InstrItinData<IIC_VPALiQ,   [InstrStage<1, [FU_DRegsN],   0, Required>,
1066                                // Extra latency cycles since wbck is 6 cycles
1067                                InstrStage<7, [FU_DRegsVFP], 0, Reserved>,
1068                                InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
1069                                InstrStage<2, [FU_NPipe]>], [6, 3, 1]>,
1070
1071   //
1072   // Double-register Integer Multiply (.8, .16)
1073   InstrItinData<IIC_VMULi16D, [InstrStage<1, [FU_DRegsN],   0, Required>,
1074                                // Extra latency cycles since wbck is 6 cycles
1075                                InstrStage<7, [FU_DRegsVFP], 0, Reserved>,
1076                                InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
1077                                InstrStage<1, [FU_NPipe]>], [6, 2, 2]>,
1078   //
1079   // Quad-register Integer Multiply (.8, .16)
1080   InstrItinData<IIC_VMULi16Q, [InstrStage<1, [FU_DRegsN],   0, Required>,
1081                                // Extra latency cycles since wbck is 7 cycles
1082                                InstrStage<8, [FU_DRegsVFP], 0, Reserved>,
1083                                InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
1084                                InstrStage<2, [FU_NPipe]>], [7, 2, 2]>,
1085
1086   //
1087   // Double-register Integer Multiply (.32)
1088   InstrItinData<IIC_VMULi32D, [InstrStage<1, [FU_DRegsN],   0, Required>,
1089                                // Extra latency cycles since wbck is 7 cycles
1090                                InstrStage<8, [FU_DRegsVFP], 0, Reserved>,
1091                                InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
1092                                InstrStage<2, [FU_NPipe]>], [7, 2, 1]>,
1093   //
1094   // Quad-register Integer Multiply (.32)
1095   InstrItinData<IIC_VMULi32Q, [InstrStage<1, [FU_DRegsN],   0, Required>,
1096                                // Extra latency cycles since wbck is 9 cycles
1097                                InstrStage<10, [FU_DRegsVFP], 0, Reserved>,
1098                                InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
1099                                InstrStage<4, [FU_NPipe]>], [9, 2, 1]>,
1100   //
1101   // Double-register Integer Multiply-Accumulate (.8, .16)
1102   InstrItinData<IIC_VMACi16D, [InstrStage<1, [FU_DRegsN],   0, Required>,
1103                                // Extra latency cycles since wbck is 6 cycles
1104                                InstrStage<7, [FU_DRegsVFP], 0, Reserved>,
1105                                InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
1106                                InstrStage<1, [FU_NPipe]>], [6, 3, 2, 2]>,
1107   //
1108   // Double-register Integer Multiply-Accumulate (.32)
1109   InstrItinData<IIC_VMACi32D, [InstrStage<1, [FU_DRegsN],   0, Required>,
1110                                // Extra latency cycles since wbck is 7 cycles
1111                                InstrStage<8, [FU_DRegsVFP], 0, Reserved>,
1112                                InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
1113                                InstrStage<2, [FU_NPipe]>], [7, 3, 2, 1]>,
1114   //
1115   // Quad-register Integer Multiply-Accumulate (.8, .16)
1116   InstrItinData<IIC_VMACi16Q, [InstrStage<1, [FU_DRegsN],   0, Required>,
1117                                // Extra latency cycles since wbck is 7 cycles
1118                                InstrStage<8, [FU_DRegsVFP], 0, Reserved>,
1119                                InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
1120                                InstrStage<2, [FU_NPipe]>], [7, 3, 2, 2]>,
1121   //
1122   // Quad-register Integer Multiply-Accumulate (.32)
1123   InstrItinData<IIC_VMACi32Q, [InstrStage<1, [FU_DRegsN],   0, Required>,
1124                                // Extra latency cycles since wbck is 9 cycles
1125                                InstrStage<10, [FU_DRegsVFP], 0, Reserved>,
1126                                InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
1127                                InstrStage<4, [FU_NPipe]>], [9, 3, 2, 1]>,
1128   //
1129   // Move Immediate
1130   InstrItinData<IIC_VMOVImm,  [InstrStage<1, [FU_DRegsN],   0, Required>,
1131                                // Extra latency cycles since wbck is 6 cycles
1132                                InstrStage<7, [FU_DRegsVFP], 0, Reserved>,
1133                                InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
1134                                InstrStage<1, [FU_NPipe]>], [3]>,
1135   //
1136   // Double-register Permute Move
1137   InstrItinData<IIC_VMOVD,    [InstrStage<1, [FU_DRegsN],   0, Required>,
1138   // FIXME: all latencies are arbitrary, no information is available
1139                                InstrStage<3, [FU_DRegsVFP], 0, Reserved>,
1140                                InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
1141                                InstrStage<1, [FU_NLSPipe]>], [2, 1]>,
1142   //
1143   // Quad-register Permute Move
1144   // Result written in N2, but that is relative to the last cycle of multicycle,
1145   // so we use 3 for those cases
1146   InstrItinData<IIC_VMOVQ,    [InstrStage<1, [FU_DRegsN],   0, Required>,
1147   // FIXME: all latencies are arbitrary, no information is available
1148                                InstrStage<4, [FU_DRegsVFP], 0, Reserved>,
1149                                InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
1150                                InstrStage<2, [FU_NPipe]>], [3, 1]>,
1151   //
1152   // Integer to Single-precision Move
1153   InstrItinData<IIC_VMOVIS ,  [InstrStage<1, [FU_DRegsN],   0, Required>,
1154   // FIXME: all latencies are arbitrary, no information is available
1155                                InstrStage<3, [FU_DRegsVFP], 0, Reserved>,
1156                                InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
1157                                InstrStage<1, [FU_NPipe]>], [2, 1]>,
1158   //
1159   // Integer to Double-precision Move
1160   InstrItinData<IIC_VMOVID ,  [InstrStage<1, [FU_DRegsN],   0, Required>,
1161   // FIXME: all latencies are arbitrary, no information is available
1162                                InstrStage<3, [FU_DRegsVFP], 0, Reserved>,
1163                                InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
1164                                InstrStage<1, [FU_NPipe]>], [2, 1, 1]>,
1165   //
1166   // Single-precision to Integer Move
1167   InstrItinData<IIC_VMOVSI ,  [InstrStage<1, [FU_DRegsN],   0, Required>,
1168   // FIXME: all latencies are arbitrary, no information is available
1169                                InstrStage<3, [FU_DRegsVFP], 0, Reserved>,
1170                                InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
1171                                InstrStage<1, [FU_NPipe]>], [2, 1]>,
1172   //
1173   // Double-precision to Integer Move
1174   InstrItinData<IIC_VMOVDI ,  [InstrStage<1, [FU_DRegsN],   0, Required>,
1175   // FIXME: all latencies are arbitrary, no information is available
1176                                InstrStage<3, [FU_DRegsVFP], 0, Reserved>,
1177                                InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
1178                                InstrStage<1, [FU_NPipe]>], [2, 2, 1]>,
1179   //
1180   // Integer to Lane Move
1181   InstrItinData<IIC_VMOVISL , [InstrStage<1, [FU_DRegsN],   0, Required>,
1182   // FIXME: all latencies are arbitrary, no information is available
1183                                InstrStage<4, [FU_DRegsVFP], 0, Reserved>,
1184                                InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
1185                                InstrStage<2, [FU_NPipe]>], [3, 1, 1]>,
1186
1187   //
1188   // Double-register FP Unary
1189   InstrItinData<IIC_VUNAD,    [InstrStage<1, [FU_DRegsN],   0, Required>,
1190                                // Extra latency cycles since wbck is 6 cycles
1191                                InstrStage<7, [FU_DRegsVFP], 0, Reserved>,
1192                                InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
1193                                InstrStage<1, [FU_NPipe]>], [5, 2]>,
1194   //
1195   // Quad-register FP Unary
1196   // Result written in N5, but that is relative to the last cycle of multicycle,
1197   // so we use 6 for those cases
1198   InstrItinData<IIC_VUNAQ,    [InstrStage<1, [FU_DRegsN],   0, Required>,
1199                                // Extra latency cycles since wbck is 7 cycles
1200                                InstrStage<8, [FU_DRegsVFP], 0, Reserved>,
1201                                InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
1202                                InstrStage<2, [FU_NPipe]>], [6, 2]>,
1203   //
1204   // Double-register FP Binary
1205   // FIXME: We're using this itin for many instructions and [2, 2] here is too
1206   // optimistic.
1207   InstrItinData<IIC_VBIND,    [InstrStage<1, [FU_DRegsN],   0, Required>,
1208                                // Extra latency cycles since wbck is 7 cycles
1209                                InstrStage<7, [FU_DRegsVFP], 0, Reserved>,
1210                                InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
1211                                InstrStage<1, [FU_NPipe]>], [5, 2, 2]>,
1212   //
1213   // Quad-register FP Binary
1214   // Result written in N5, but that is relative to the last cycle of multicycle,
1215   // so we use 6 for those cases
1216   // FIXME: We're using this itin for many instructions and [2, 2] here is too
1217   // optimistic.
1218   InstrItinData<IIC_VBINQ,    [InstrStage<1, [FU_DRegsN],   0, Required>,
1219                                // Extra latency cycles since wbck is 8 cycles
1220                                InstrStage<8, [FU_DRegsVFP], 0, Reserved>,
1221                                InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
1222                                InstrStage<2, [FU_NPipe]>], [6, 2, 2]>,
1223   //
1224   // Double-register FP Multiple-Accumulate
1225   InstrItinData<IIC_VMACD,    [InstrStage<1, [FU_DRegsN],   0, Required>,
1226                                // Extra latency cycles since wbck is 7 cycles
1227                                InstrStage<8, [FU_DRegsVFP], 0, Reserved>,
1228                                InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
1229                                InstrStage<2, [FU_NPipe]>], [6, 3, 2, 1]>,
1230   //
1231   // Quad-register FP Multiple-Accumulate
1232   // Result written in N9, but that is relative to the last cycle of multicycle,
1233   // so we use 10 for those cases
1234   InstrItinData<IIC_VMACQ,    [InstrStage<1, [FU_DRegsN],   0, Required>,
1235                                // Extra latency cycles since wbck is 9 cycles
1236                                InstrStage<10, [FU_DRegsVFP], 0, Reserved>,
1237                                InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
1238                                InstrStage<4, [FU_NPipe]>], [8, 4, 2, 1]>,
1239   //
1240   // Double-register Reciprical Step
1241   InstrItinData<IIC_VRECSD,   [InstrStage<1, [FU_DRegsN],   0, Required>,
1242                                // Extra latency cycles since wbck is 7 cycles
1243                                InstrStage<8, [FU_DRegsVFP], 0, Reserved>,
1244                                InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
1245                                InstrStage<2, [FU_NPipe]>], [6, 2, 2]>,
1246   //
1247   // Quad-register Reciprical Step
1248   InstrItinData<IIC_VRECSQ,   [InstrStage<1, [FU_DRegsN],   0, Required>,
1249                                // Extra latency cycles since wbck is 9 cycles
1250                                InstrStage<10, [FU_DRegsVFP], 0, Reserved>,
1251                                InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
1252                                InstrStage<4, [FU_NPipe]>], [8, 2, 2]>,
1253   //
1254   // Double-register Permute
1255   InstrItinData<IIC_VPERMD,   [InstrStage<1, [FU_DRegsN],   0, Required>,
1256                                // Extra latency cycles since wbck is 6 cycles
1257                                InstrStage<7, [FU_DRegsVFP], 0, Reserved>,
1258                                InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
1259                                InstrStage<1, [FU_NPipe]>], [2, 2, 1, 1]>,
1260   //
1261   // Quad-register Permute
1262   // Result written in N2, but that is relative to the last cycle of multicycle,
1263   // so we use 3 for those cases
1264   InstrItinData<IIC_VPERMQ,   [InstrStage<1, [FU_DRegsN],   0, Required>,
1265                                // Extra latency cycles since wbck is 7 cycles
1266                                InstrStage<8, [FU_DRegsVFP], 0, Reserved>,
1267                                InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
1268                                InstrStage<2, [FU_NPipe]>], [3, 3, 1, 1]>,
1269   //
1270   // Quad-register Permute (3 cycle issue)
1271   // Result written in N2, but that is relative to the last cycle of multicycle,
1272   // so we use 4 for those cases
1273   InstrItinData<IIC_VPERMQ3,  [InstrStage<1, [FU_DRegsN],   0, Required>,
1274                                // Extra latency cycles since wbck is 8 cycles
1275                                InstrStage<9, [FU_DRegsVFP], 0, Reserved>,
1276                                InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
1277                                InstrStage<3, [FU_NLSPipe]>], [4, 4, 1, 1]>,
1278
1279   //
1280   // Double-register VEXT
1281   InstrItinData<IIC_VEXTD,    [InstrStage<1, [FU_DRegsN],   0, Required>,
1282                                // Extra latency cycles since wbck is 7 cycles
1283                                InstrStage<7, [FU_DRegsVFP], 0, Reserved>,
1284                                InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
1285                                InstrStage<1, [FU_NPipe]>], [2, 1, 1]>,
1286   //
1287   // Quad-register VEXT
1288   InstrItinData<IIC_VEXTQ,    [InstrStage<1, [FU_DRegsN],   0, Required>,
1289                                // Extra latency cycles since wbck is 9 cycles
1290                                InstrStage<8, [FU_DRegsVFP], 0, Reserved>,
1291                                InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
1292                                InstrStage<2, [FU_NPipe]>], [3, 1, 1]>,
1293   //
1294   // VTB
1295   InstrItinData<IIC_VTB1,     [InstrStage<1, [FU_DRegsN],   0, Required>,
1296                                // Extra latency cycles since wbck is 7 cycles
1297                                InstrStage<8, [FU_DRegsVFP], 0, Reserved>,
1298                                InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
1299                                InstrStage<2, [FU_NPipe]>], [3, 2, 1]>,
1300   InstrItinData<IIC_VTB2,     [InstrStage<2, [FU_DRegsN],   0, Required>,
1301                                // Extra latency cycles since wbck is 7 cycles
1302                                InstrStage<8, [FU_DRegsVFP], 0, Reserved>,
1303                                InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
1304                                InstrStage<2, [FU_NPipe]>], [3, 2, 2, 1]>,
1305   InstrItinData<IIC_VTB3,     [InstrStage<2, [FU_DRegsN],   0, Required>,
1306                                // Extra latency cycles since wbck is 8 cycles
1307                                InstrStage<9, [FU_DRegsVFP], 0, Reserved>,
1308                                InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
1309                                InstrStage<3, [FU_NPipe]>], [4, 2, 2, 3, 1]>,
1310   InstrItinData<IIC_VTB4,     [InstrStage<1, [FU_DRegsN],   0, Required>,
1311                                // Extra latency cycles since wbck is 8 cycles
1312                                InstrStage<9, [FU_DRegsVFP], 0, Reserved>,
1313                                InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
1314                                InstrStage<3, [FU_NPipe]>], [4, 2, 2, 3, 3, 1]>,
1315   //
1316   // VTBX
1317   InstrItinData<IIC_VTBX1,    [InstrStage<1, [FU_DRegsN],   0, Required>,
1318                                // Extra latency cycles since wbck is 7 cycles
1319                                InstrStage<8, [FU_DRegsVFP], 0, Reserved>,
1320                                InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
1321                                InstrStage<2, [FU_NPipe]>], [3, 1, 2, 1]>,
1322   InstrItinData<IIC_VTBX2,    [InstrStage<1, [FU_DRegsN],   0, Required>,
1323                                // Extra latency cycles since wbck is 7 cycles
1324                                InstrStage<8, [FU_DRegsVFP], 0, Reserved>,
1325                                InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
1326                                InstrStage<2, [FU_NPipe]>], [3, 1, 2, 2, 1]>,
1327   InstrItinData<IIC_VTBX3,    [InstrStage<1, [FU_DRegsN],   0, Required>,
1328                                // Extra latency cycles since wbck is 8 cycles
1329                                InstrStage<9, [FU_DRegsVFP], 0, Reserved>,
1330                                InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
1331                                InstrStage<3, [FU_NPipe]>], [4, 1, 2, 2, 3, 1]>,
1332   InstrItinData<IIC_VTBX4,    [InstrStage<1, [FU_DRegsN],   0, Required>,
1333                                // Extra latency cycles since wbck is 8 cycles
1334                                InstrStage<9, [FU_DRegsVFP], 0, Reserved>,
1335                                InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
1336                                InstrStage<2, [FU_NPipe]>], [4, 1, 2, 2, 3, 3, 1]>
1337 ]>;
1338
1339