lib/Target/ARM/ARMScheduleV6.td

   1 //===- ARMScheduleV6.td - ARM v6 Scheduling Definitions ----*- tablegen -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file defines the itinerary class data for the ARM v6 processors.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 // TODO: this should model an ARM11
  15 // Single issue pipeline so every itinerary starts with FU_pipe0
  16 def V6Itineraries : ProcessorItineraries<[
  17   InstrItinData<IIC_iALUx   , [InstrStage<1, [FU_Pipe0]>]>,
  18   InstrItinData<IIC_iALUi   , [InstrStage<1, [FU_Pipe0]>]>,
  19   InstrItinData<IIC_iALUr   , [InstrStage<1, [FU_Pipe0]>]>,
  20   InstrItinData<IIC_iALUsi  , [InstrStage<1, [FU_Pipe0]>]>,
  21   InstrItinData<IIC_iALUsr  , [InstrStage<1, [FU_Pipe0]>]>,
  22   InstrItinData<IIC_iUNAr   , [InstrStage<1, [FU_Pipe0]>]>,
  23   InstrItinData<IIC_iUNAsi  , [InstrStage<1, [FU_Pipe0]>]>,
  24   InstrItinData<IIC_iUNAsr  , [InstrStage<1, [FU_Pipe0]>]>,
  25   InstrItinData<IIC_iCMPi   , [InstrStage<1, [FU_Pipe0]>]>,
  26   InstrItinData<IIC_iCMPr   , [InstrStage<1, [FU_Pipe0]>]>,
  27   InstrItinData<IIC_iCMPsi  , [InstrStage<1, [FU_Pipe0]>]>,
  28   InstrItinData<IIC_iCMPsr  , [InstrStage<1, [FU_Pipe0]>]>,
  29   InstrItinData<IIC_iMOVi   , [InstrStage<1, [FU_Pipe0]>]>,
  30   InstrItinData<IIC_iMOVr   , [InstrStage<1, [FU_Pipe0]>]>,
  31   InstrItinData<IIC_iMOVsi  , [InstrStage<1, [FU_Pipe0]>]>,
  32   InstrItinData<IIC_iMOVsr  , [InstrStage<1, [FU_Pipe0]>]>,
  33   InstrItinData<IIC_iCMOVi  , [InstrStage<1, [FU_Pipe0]>]>,
  34   InstrItinData<IIC_iCMOVr  , [InstrStage<1, [FU_Pipe0]>]>,
  35   InstrItinData<IIC_iCMOVsi , [InstrStage<1, [FU_Pipe0]>]>,
  36   InstrItinData<IIC_iCMOVsr , [InstrStage<1, [FU_Pipe0]>]>,
  37   InstrItinData<IIC_iMUL16  , [InstrStage<1, [FU_Pipe0]>]>,
  38   InstrItinData<IIC_iMAC16  , [InstrStage<1, [FU_Pipe0]>]>,
  39   InstrItinData<IIC_iMUL32  , [InstrStage<1, [FU_Pipe0]>]>,
  40   InstrItinData<IIC_iMAC32  , [InstrStage<1, [FU_Pipe0]>]>,
  41   InstrItinData<IIC_iMUL64  , [InstrStage<1, [FU_Pipe0]>]>,
  42   InstrItinData<IIC_iMAC64  , [InstrStage<1, [FU_Pipe0]>]>,
  43   InstrItinData<IIC_iLoadi  , [InstrStage<1, [FU_Pipe0]>,
  44                                InstrStage<1, [FU_LdSt0]>]>,
  45   InstrItinData<IIC_iLoadr  , [InstrStage<1, [FU_Pipe0]>,
  46                                InstrStage<1, [FU_LdSt0]>]>,
  47   InstrItinData<IIC_iLoadsi , [InstrStage<1, [FU_Pipe0]>,
  48                                InstrStage<1, [FU_LdSt0]>]>,
  49   InstrItinData<IIC_iLoadiu , [InstrStage<1, [FU_Pipe0]>,
  50                                InstrStage<1, [FU_LdSt0]>]>,
  51   InstrItinData<IIC_iLoadru , [InstrStage<1, [FU_Pipe0]>,
  52                                InstrStage<1, [FU_LdSt0]>]>,
  53   InstrItinData<IIC_iLoadsiu, [InstrStage<1, [FU_Pipe0]>,
  54                                InstrStage<1, [FU_LdSt0]>]>,
  55   InstrItinData<IIC_iLoadm  , [InstrStage<2, [FU_Pipe0]>,
  56                                InstrStage<2, [FU_LdSt0]>]>,
  57   InstrItinData<IIC_iStorei  , [InstrStage<1, [FU_Pipe0]>]>,
  58   InstrItinData<IIC_iStorer  , [InstrStage<1, [FU_Pipe0]>]>,
  59   InstrItinData<IIC_iStoresi , [InstrStage<1, [FU_Pipe0]>]>,
  60   InstrItinData<IIC_iStoreiu , [InstrStage<1, [FU_Pipe0]>]>,
  61   InstrItinData<IIC_iStoreru , [InstrStage<1, [FU_Pipe0]>]>,
  62   InstrItinData<IIC_iStoresiu, [InstrStage<1, [FU_Pipe0]>]>,
  63   InstrItinData<IIC_iStorem  , [InstrStage<2, [FU_Pipe0]>]>,
  64   InstrItinData<IIC_Br      , [InstrStage<1, [FU_Pipe0]>]>,
  65   InstrItinData<IIC_fpALU   , [InstrStage<1, [FU_Pipe0]>]>,
  66   InstrItinData<IIC_fpMPY   , [InstrStage<1, [FU_Pipe0]>]>,
  67   InstrItinData<IIC_fpLoad  , [InstrStage<1, [FU_Pipe0]>,
  68                                InstrStage<1, [FU_LdSt0]>]>,
  69   InstrItinData<IIC_fpStore , [InstrStage<1, [FU_Pipe0]>]>
  70 ]>;