1 //=- ARMScheduleA9.td - ARM Cortex-A9 Scheduling Definitions -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the itinerary class data for the ARM Cortex A9 processors.
12 //===----------------------------------------------------------------------===//
15 // Ad-hoc scheduling information derived from pretty vague "Cortex-A9 Technical
19 def A9_Pipe0 : FuncUnit; // pipeline 0
20 def A9_Pipe1 : FuncUnit; // pipeline 1
21 def A9_LSPipe : FuncUnit; // LS pipe
22 def A9_NPipe : FuncUnit; // NEON ALU/MUL pipe
23 def A9_DRegsVFP: FuncUnit; // FP register set, VFP side
24 def A9_DRegsN : FuncUnit; // FP register set, NEON side
26 // Dual issue pipeline represented by A9_Pipe0 | A9_Pipe1
28 def CortexA9Itineraries : ProcessorItineraries<
29 [A9_NPipe, A9_DRegsN, A9_DRegsVFP, A9_LSPipe, A9_Pipe0, A9_Pipe1], [], [
30 // Two fully-pipelined integer ALU pipelines
31 // FIXME: There are no operand latencies for these instructions at all!
33 // Move instructions, unconditional
34 InstrItinData<IIC_iMOVi , [InstrStage<1, [A9_Pipe0, A9_Pipe1]>], [1]>,
35 InstrItinData<IIC_iMOVix2 , [InstrStage<1, [A9_Pipe0, A9_Pipe1]>,
36 InstrStage<1, [A9_Pipe0, A9_Pipe1]>], [2]>,
37 InstrItinData<IIC_iMOVr , [InstrStage<1, [A9_Pipe0, A9_Pipe1]>], [1, 1]>,
38 InstrItinData<IIC_iMOVsi , [InstrStage<1, [A9_Pipe0, A9_Pipe1]>], [1, 1]>,
39 InstrItinData<IIC_iMOVsr , [InstrStage<2, [A9_Pipe0, A9_Pipe1]>], [2, 2, 1]>,
42 InstrItinData<IIC_iALUx , [InstrStage<1, [A9_Pipe0, A9_Pipe1]>]>,
44 // Binary Instructions that produce a result
45 InstrItinData<IIC_iALUi , [InstrStage<1, [A9_Pipe0, A9_Pipe1]>], [2, 2]>,
46 InstrItinData<IIC_iALUr , [InstrStage<1, [A9_Pipe0, A9_Pipe1]>], [2, 2, 2]>,
47 InstrItinData<IIC_iALUsi, [InstrStage<2, [A9_Pipe0, A9_Pipe1]>], [2, 2, 1]>,
48 InstrItinData<IIC_iALUsr,[InstrStage<3, [A9_Pipe0, A9_Pipe1]>], [2, 2, 1, 1]>,
50 // Unary Instructions that produce a result
51 InstrItinData<IIC_iUNAr , [InstrStage<1, [A9_Pipe0, A9_Pipe1]>], [2, 2]>,
52 InstrItinData<IIC_iUNAsi , [InstrStage<2, [A9_Pipe0, A9_Pipe1]>], [2, 1]>,
54 // Zero and sign extension instructions
55 InstrItinData<IIC_iEXTr , [InstrStage<1, [A9_Pipe0, A9_Pipe1]>], [2, 1]>,
56 InstrItinData<IIC_iEXTAr, [InstrStage<2, [A9_Pipe0, A9_Pipe1]>], [3, 1, 1]>,
58 // Compare instructions
59 InstrItinData<IIC_iCMPi , [InstrStage<1, [A9_Pipe0, A9_Pipe1]>], [2]>,
60 InstrItinData<IIC_iCMPr , [InstrStage<1, [A9_Pipe0, A9_Pipe1]>], [2, 2]>,
61 InstrItinData<IIC_iCMPsi , [InstrStage<2, [A9_Pipe0, A9_Pipe1]>], [2, 1]>,
62 InstrItinData<IIC_iCMPsr , [InstrStage<3, [A9_Pipe0, A9_Pipe1]>], [2, 1, 1]>,
64 // Move instructions, conditional
65 InstrItinData<IIC_iCMOVi , [InstrStage<1, [A9_Pipe0, A9_Pipe1]>], [2]>,
66 InstrItinData<IIC_iCMOVr , [InstrStage<1, [A9_Pipe0, A9_Pipe1]>], [2, 1]>,
67 InstrItinData<IIC_iCMOVsi , [InstrStage<1, [A9_Pipe0, A9_Pipe1]>], [2, 1]>,
68 InstrItinData<IIC_iCMOVsr , [InstrStage<2, [A9_Pipe0, A9_Pipe1]>], [2, 1, 1]>,
70 // Integer multiply pipeline
72 InstrItinData<IIC_iMUL16 , [InstrStage<1, [A9_Pipe1], 0>,
73 InstrStage<2, [A9_Pipe0]>], [4, 1, 1]>,
74 InstrItinData<IIC_iMAC16 , [InstrStage<1, [A9_Pipe1], 0>,
75 InstrStage<2, [A9_Pipe0]>], [4, 1, 1, 2]>,
76 InstrItinData<IIC_iMUL32 , [InstrStage<1, [A9_Pipe1], 0>,
77 InstrStage<2, [A9_Pipe0]>], [4, 1, 1]>,
78 InstrItinData<IIC_iMAC32 , [InstrStage<1, [A9_Pipe1], 0>,
79 InstrStage<2, [A9_Pipe0]>], [4, 1, 1, 2]>,
80 InstrItinData<IIC_iMUL64 , [InstrStage<2, [A9_Pipe1], 0>,
81 InstrStage<3, [A9_Pipe0]>], [4, 5, 1, 1]>,
82 InstrItinData<IIC_iMAC64 , [InstrStage<2, [A9_Pipe1], 0>,
83 InstrStage<3, [A9_Pipe0]>], [4, 5, 1, 1]>,
84 // Integer load pipeline
85 // FIXME: The timings are some rough approximations
88 InstrItinData<IIC_iLoadi , [InstrStage<1, [A9_Pipe1]>,
89 InstrStage<1, [A9_LSPipe]>], [3, 1]>,
92 InstrItinData<IIC_iLoadr , [InstrStage<1, [A9_Pipe1]>,
93 InstrStage<1, [A9_LSPipe]>], [3, 1, 1]>,
95 // Scaled register offset
96 InstrItinData<IIC_iLoadsi , [InstrStage<1, [A9_Pipe1]>,
97 InstrStage<2, [A9_LSPipe]>], [4, 1, 1]>,
99 // Immediate offset with update
100 InstrItinData<IIC_iLoadiu , [InstrStage<1, [A9_Pipe1]>,
101 InstrStage<2, [A9_LSPipe]>], [3, 2, 1]>,
103 // Register offset with update
104 InstrItinData<IIC_iLoadru , [InstrStage<1, [A9_Pipe1]>,
105 InstrStage<2, [A9_LSPipe]>], [3, 2, 1, 1]>,
107 // Scaled register offset with update
108 InstrItinData<IIC_iLoadsiu , [InstrStage<1, [A9_Pipe1]>,
109 InstrStage<2, [A9_LSPipe]>], [4, 3, 1, 1]>,
112 InstrItinData<IIC_iLoadm , [InstrStage<1, [A9_Pipe1]>,
113 InstrStage<1, [A9_LSPipe]>]>,
116 // Load multiple plus branch
117 InstrItinData<IIC_iLoadmBr , [InstrStage<1, [A9_Pipe1]>,
118 InstrStage<1, [A9_LSPipe]>,
119 InstrStage<1, [A9_Pipe0, A9_Pipe1]>]>,
122 // iLoadi + iALUr for t2LDRpci_pic.
123 InstrItinData<IIC_iLoadiALU, [InstrStage<1, [A9_Pipe1]>,
124 InstrStage<1, [A9_LSPipe]>,
125 InstrStage<1, [A9_Pipe0, A9_Pipe1]>], [4, 1]>,
127 // Integer store pipeline
130 InstrItinData<IIC_iStorei , [InstrStage<1, [A9_Pipe1]>,
131 InstrStage<1, [A9_LSPipe]>], [3, 1]>,
134 InstrItinData<IIC_iStorer , [InstrStage<1, [ A9_Pipe1]>,
135 InstrStage<1, [A9_LSPipe]>], [3, 1, 1]>,
137 // Scaled register offset
138 InstrItinData<IIC_iStoresi , [InstrStage<1, [A9_Pipe1]>,
139 InstrStage<2, [A9_LSPipe]>], [3, 1, 1]>,
141 // Immediate offset with update
142 InstrItinData<IIC_iStoreiu , [InstrStage<1, [A9_Pipe1]>,
143 InstrStage<1, [A9_LSPipe]>], [2, 3, 1]>,
145 // Register offset with update
146 InstrItinData<IIC_iStoreru , [InstrStage<1, [A9_Pipe1]>,
147 InstrStage<1, [A9_LSPipe]>], [2, 3, 1, 1]>,
149 // Scaled register offset with update
150 InstrItinData<IIC_iStoresiu, [InstrStage<1, [A9_Pipe1]>,
151 InstrStage<2, [A9_LSPipe]>], [3, 3, 1, 1]>,
154 InstrItinData<IIC_iStorem , [InstrStage<1, [A9_Pipe1]>,
155 InstrStage<1, [A9_LSPipe]>]>,
158 // no delay slots, so the latency of a branch is unimportant
159 InstrItinData<IIC_Br , [InstrStage<1, [A9_Pipe0, A9_Pipe1]>]>,
161 // VFP and NEON shares the same register file. This means that every VFP
162 // instruction should wait for full completion of the consecutive NEON
163 // instruction and vice-versa. We model this behavior with two artificial FUs:
164 // DRegsVFP and DRegsVFP.
166 // Every VFP instruction:
167 // - Acquires DRegsVFP resource for 1 cycle
168 // - Reserves DRegsN resource for the whole duration (including time to
169 // register file writeback!).
170 // Every NEON instruction does the same but with FUs swapped.
172 // Since the reserved FU cannot be acquired, this models precisely
173 // "cross-domain" stalls.
176 // Issue through integer pipeline, and execute in NEON unit.
178 // FP Special Register to Integer Register File Move
179 InstrItinData<IIC_fpSTAT , [InstrStage<1, [A9_DRegsVFP], 0, Required>,
180 InstrStage<2, [A9_DRegsN], 0, Reserved>,
181 InstrStage<1, [A9_Pipe1]>,
182 InstrStage<1, [A9_NPipe]>]>,
184 // Single-precision FP Unary
185 InstrItinData<IIC_fpUNA32 , [InstrStage<1, [A9_DRegsVFP], 0, Required>,
186 // Extra latency cycles since wbck is 2 cycles
187 InstrStage<3, [A9_DRegsN], 0, Reserved>,
188 InstrStage<1, [A9_Pipe1]>,
189 InstrStage<1, [A9_NPipe]>], [1, 1]>,
191 // Double-precision FP Unary
192 InstrItinData<IIC_fpUNA64 , [InstrStage<1, [A9_DRegsVFP], 0, Required>,
193 // Extra latency cycles since wbck is 2 cycles
194 InstrStage<3, [A9_DRegsN], 0, Reserved>,
195 InstrStage<1, [A9_Pipe1]>,
196 InstrStage<1, [A9_NPipe]>], [1, 1]>,
199 // Single-precision FP Compare
200 InstrItinData<IIC_fpCMP32 , [InstrStage<1, [A9_DRegsVFP], 0, Required>,
201 // Extra latency cycles since wbck is 4 cycles
202 InstrStage<5, [A9_DRegsN], 0, Reserved>,
203 InstrStage<1, [A9_Pipe1]>,
204 InstrStage<1, [A9_NPipe]>], [1, 1]>,
206 // Double-precision FP Compare
207 InstrItinData<IIC_fpCMP64 , [InstrStage<1, [A9_DRegsVFP], 0, Required>,
208 // Extra latency cycles since wbck is 4 cycles
209 InstrStage<5, [A9_DRegsN], 0, Reserved>,
210 InstrStage<1, [A9_Pipe1]>,
211 InstrStage<1, [A9_NPipe]>], [1, 1]>,
213 // Single to Double FP Convert
214 InstrItinData<IIC_fpCVTSD , [InstrStage<1, [A9_DRegsVFP], 0, Required>,
215 InstrStage<5, [A9_DRegsN], 0, Reserved>,
216 InstrStage<1, [A9_Pipe1]>,
217 InstrStage<1, [A9_NPipe]>], [4, 1]>,
219 // Double to Single FP Convert
220 InstrItinData<IIC_fpCVTDS , [InstrStage<1, [A9_DRegsVFP], 0, Required>,
221 InstrStage<5, [A9_DRegsN], 0, Reserved>,
222 InstrStage<1, [A9_Pipe1]>,
223 InstrStage<1, [A9_NPipe]>], [4, 1]>,
226 // Single to Half FP Convert
227 InstrItinData<IIC_fpCVTSH , [InstrStage<1, [A9_DRegsVFP], 0, Required>,
228 InstrStage<5, [A9_DRegsN], 0, Reserved>,
229 InstrStage<1, [A9_Pipe1]>,
230 InstrStage<1, [A9_NPipe]>], [4, 1]>,
232 // Half to Single FP Convert
233 InstrItinData<IIC_fpCVTHS , [InstrStage<1, [A9_DRegsVFP], 0, Required>,
234 InstrStage<3, [A9_DRegsN], 0, Reserved>,
235 InstrStage<1, [A9_Pipe1]>,
236 InstrStage<1, [A9_NPipe]>], [2, 1]>,
239 // Single-Precision FP to Integer Convert
240 InstrItinData<IIC_fpCVTSI , [InstrStage<1, [A9_DRegsVFP], 0, Required>,
241 InstrStage<5, [A9_DRegsN], 0, Reserved>,
242 InstrStage<1, [A9_Pipe1]>,
243 InstrStage<1, [A9_NPipe]>], [4, 1]>,
245 // Double-Precision FP to Integer Convert
246 InstrItinData<IIC_fpCVTDI , [InstrStage<1, [A9_DRegsVFP], 0, Required>,
247 InstrStage<5, [A9_DRegsN], 0, Reserved>,
248 InstrStage<1, [A9_Pipe1]>,
249 InstrStage<1, [A9_NPipe]>], [4, 1]>,
251 // Integer to Single-Precision FP Convert
252 InstrItinData<IIC_fpCVTIS , [InstrStage<1, [A9_DRegsVFP], 0, Required>,
253 InstrStage<5, [A9_DRegsN], 0, Reserved>,
254 InstrStage<1, [A9_Pipe1]>,
255 InstrStage<1, [A9_NPipe]>], [4, 1]>,
257 // Integer to Double-Precision FP Convert
258 InstrItinData<IIC_fpCVTID , [InstrStage<1, [A9_DRegsVFP], 0, Required>,
259 InstrStage<5, [A9_DRegsN], 0, Reserved>,
260 InstrStage<1, [A9_Pipe1]>,
261 InstrStage<1, [A9_NPipe]>], [4, 1]>,
263 // Single-precision FP ALU
264 InstrItinData<IIC_fpALU32 , [InstrStage<1, [A9_DRegsVFP], 0, Required>,
265 InstrStage<5, [A9_DRegsN], 0, Reserved>,
266 InstrStage<1, [A9_Pipe1]>,
267 InstrStage<1, [A9_NPipe]>], [4, 1, 1]>,
269 // Double-precision FP ALU
270 InstrItinData<IIC_fpALU64 , [InstrStage<1, [A9_DRegsVFP], 0, Required>,
271 InstrStage<5, [A9_DRegsN], 0, Reserved>,
272 InstrStage<1, [A9_Pipe1]>,
273 InstrStage<1, [A9_NPipe]>], [4, 1, 1]>,
275 // Single-precision FP Multiply
276 InstrItinData<IIC_fpMUL32 , [InstrStage<1, [A9_DRegsVFP], 0, Required>,
277 InstrStage<6, [A9_DRegsN], 0, Reserved>,
278 InstrStage<1, [A9_Pipe1]>,
279 InstrStage<1, [A9_NPipe]>], [5, 1, 1]>,
281 // Double-precision FP Multiply
282 InstrItinData<IIC_fpMUL64 , [InstrStage<1, [A9_DRegsVFP], 0, Required>,
283 InstrStage<7, [A9_DRegsN], 0, Reserved>,
284 InstrStage<1, [A9_Pipe1]>,
285 InstrStage<2, [A9_NPipe]>], [6, 1, 1]>,
287 // Single-precision FP MAC
288 InstrItinData<IIC_fpMAC32 , [InstrStage<1, [A9_DRegsVFP], 0, Required>,
289 InstrStage<9, [A9_DRegsN], 0, Reserved>,
290 InstrStage<1, [A9_Pipe1]>,
291 InstrStage<1, [A9_NPipe]>], [8, 0, 1, 1]>,
293 // Double-precision FP MAC
294 InstrItinData<IIC_fpMAC64 , [InstrStage<1, [A9_DRegsVFP], 0, Required>,
295 InstrStage<10, [A9_DRegsN], 0, Reserved>,
296 InstrStage<1, [A9_Pipe1]>,
297 InstrStage<2, [A9_NPipe]>], [9, 0, 1, 1]>,
299 // Single-precision FP DIV
300 InstrItinData<IIC_fpDIV32 , [InstrStage<1, [A9_DRegsVFP], 0, Required>,
301 InstrStage<16, [A9_DRegsN], 0, Reserved>,
302 InstrStage<1, [A9_Pipe1]>,
303 InstrStage<10, [A9_NPipe]>], [15, 1, 1]>,
305 // Double-precision FP DIV
306 InstrItinData<IIC_fpDIV64 , [InstrStage<1, [A9_DRegsVFP], 0, Required>,
307 InstrStage<26, [A9_DRegsN], 0, Reserved>,
308 InstrStage<1, [A9_Pipe1]>,
309 InstrStage<20, [A9_NPipe]>], [25, 1, 1]>,
311 // Single-precision FP SQRT
312 InstrItinData<IIC_fpSQRT32, [InstrStage<1, [A9_DRegsVFP], 0, Required>,
313 InstrStage<18, [A9_DRegsN], 0, Reserved>,
314 InstrStage<1, [A9_Pipe1]>,
315 InstrStage<13, [A9_NPipe]>], [17, 1]>,
317 // Double-precision FP SQRT
318 InstrItinData<IIC_fpSQRT64, [InstrStage<1, [A9_DRegsVFP], 0, Required>,
319 InstrStage<33, [A9_DRegsN], 0, Reserved>,
320 InstrStage<1, [A9_Pipe1]>,
321 InstrStage<28, [A9_NPipe]>], [32, 1]>,
324 // Integer to Single-precision Move
325 InstrItinData<IIC_fpMOVIS, [InstrStage<1, [A9_DRegsVFP], 0, Required>,
326 // Extra 1 latency cycle since wbck is 2 cycles
327 InstrStage<3, [A9_DRegsN], 0, Reserved>,
328 InstrStage<1, [A9_Pipe1]>,
329 InstrStage<1, [A9_NPipe]>], [1, 1]>,
331 // Integer to Double-precision Move
332 InstrItinData<IIC_fpMOVID, [InstrStage<1, [A9_DRegsVFP], 0, Required>,
333 // Extra 1 latency cycle since wbck is 2 cycles
334 InstrStage<3, [A9_DRegsN], 0, Reserved>,
335 InstrStage<1, [A9_Pipe1]>,
336 InstrStage<1, [A9_NPipe]>], [1, 1, 1]>,
338 // Single-precision to Integer Move
339 InstrItinData<IIC_fpMOVSI, [InstrStage<1, [A9_DRegsVFP], 0, Required>,
340 InstrStage<2, [A9_DRegsN], 0, Reserved>,
341 InstrStage<1, [A9_Pipe1]>,
342 InstrStage<1, [A9_NPipe]>], [1, 1]>,
344 // Double-precision to Integer Move
345 InstrItinData<IIC_fpMOVDI, [InstrStage<1, [A9_DRegsVFP], 0, Required>,
346 InstrStage<2, [A9_DRegsN], 0, Reserved>,
347 InstrStage<1, [A9_Pipe1]>,
348 InstrStage<1, [A9_NPipe]>], [1, 1, 1]>,
350 // Single-precision FP Load
351 InstrItinData<IIC_fpLoad32, [InstrStage<1, [A9_DRegsVFP], 0, Required>,
352 InstrStage<2, [A9_DRegsN], 0, Reserved>,
353 InstrStage<1, [A9_Pipe1], 0>,
354 InstrStage<1, [A9_LSPipe]>,
355 InstrStage<1, [A9_NPipe]>]>,
357 // Double-precision FP Load
358 InstrItinData<IIC_fpLoad64, [InstrStage<1, [A9_DRegsVFP], 0, Required>,
359 InstrStage<2, [A9_DRegsN], 0, Reserved>,
360 InstrStage<1, [A9_Pipe1], 0>,
361 InstrStage<1, [A9_LSPipe]>,
362 InstrStage<1, [A9_NPipe]>]>,
365 InstrItinData<IIC_fpLoadm, [InstrStage<1, [A9_DRegsVFP], 0, Required>,
366 InstrStage<2, [A9_DRegsN], 0, Reserved>,
367 InstrStage<1, [A9_Pipe1], 0>,
368 InstrStage<1, [A9_LSPipe]>,
369 InstrStage<1, [A9_NPipe]>]>,
371 // Single-precision FP Store
372 InstrItinData<IIC_fpStore32,[InstrStage<1, [A9_DRegsVFP], 0, Required>,
373 InstrStage<2, [A9_DRegsN], 0, Reserved>,
374 InstrStage<1, [A9_Pipe1], 0>,
375 InstrStage<1, [A9_LSPipe]>,
376 InstrStage<1, [A9_NPipe]>]>,
378 // Double-precision FP Store
379 InstrItinData<IIC_fpStore64,[InstrStage<1, [A9_DRegsVFP], 0, Required>,
380 InstrStage<2, [A9_DRegsN], 0, Reserved>,
381 InstrStage<1, [A9_Pipe1], 0>,
382 InstrStage<1, [A9_LSPipe]>,
383 InstrStage<1, [A9_NPipe]>]>,
386 InstrItinData<IIC_fpStorem, [InstrStage<1, [A9_DRegsVFP], 0, Required>,
387 InstrStage<2, [A9_DRegsN], 0, Reserved>,
388 InstrStage<1, [A9_Pipe1], 0>,
389 InstrStage<1, [A9_LSPipe]>,
390 InstrStage<1, [A9_NPipe]>]>,
392 // Issue through integer pipeline, and execute in NEON unit.
393 // FIXME: Neon pipeline and LdSt unit are multiplexed.
394 // Add some syntactic sugar to model this!
396 // FIXME: We don't model this instruction properly
397 InstrItinData<IIC_VLD1, [InstrStage<1, [A9_DRegsN], 0, Required>,
398 InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
399 InstrStage<1, [A9_Pipe1], 0>,
400 InstrStage<1, [A9_LSPipe]>,
401 InstrStage<1, [A9_NPipe]>]>,
404 // FIXME: We don't model this instruction properly
405 InstrItinData<IIC_VLD2, [InstrStage<1, [A9_DRegsN], 0, Required>,
406 // Extra latency cycles since wbck is 6 cycles
407 InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
408 InstrStage<1, [A9_Pipe1], 0>,
409 InstrStage<1, [A9_LSPipe]>,
410 InstrStage<1, [A9_NPipe]>], [2, 2, 1]>,
413 // FIXME: We don't model this instruction properly
414 InstrItinData<IIC_VLD3, [InstrStage<1, [A9_DRegsN], 0, Required>,
415 // Extra latency cycles since wbck is 6 cycles
416 InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
417 InstrStage<1, [A9_Pipe1], 0>,
418 InstrStage<1, [A9_LSPipe]>,
419 InstrStage<1, [A9_NPipe]>], [2, 2, 2, 1]>,
422 // FIXME: We don't model this instruction properly
423 InstrItinData<IIC_VLD4, [InstrStage<1, [A9_DRegsN], 0, Required>,
424 // Extra latency cycles since wbck is 6 cycles
425 InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
426 InstrStage<1, [A9_Pipe1], 0>,
427 InstrStage<1, [A9_LSPipe]>,
428 InstrStage<1, [A9_NPipe]>], [2, 2, 2, 2, 1]>,
431 // FIXME: We don't model this instruction properly
432 InstrItinData<IIC_VST, [InstrStage<1, [A9_DRegsN], 0, Required>,
433 // Extra latency cycles since wbck is 6 cycles
434 InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
435 InstrStage<1, [A9_Pipe1], 0>,
436 InstrStage<1, [A9_LSPipe]>,
437 InstrStage<1, [A9_NPipe]>]>,
439 // Double-register Integer Unary
440 InstrItinData<IIC_VUNAiD, [InstrStage<1, [A9_DRegsN], 0, Required>,
441 // Extra latency cycles since wbck is 6 cycles
442 InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
443 InstrStage<1, [A9_Pipe1]>,
444 InstrStage<1, [A9_NPipe]>], [4, 2]>,
446 // Quad-register Integer Unary
447 InstrItinData<IIC_VUNAiQ, [InstrStage<1, [A9_DRegsN], 0, Required>,
448 // Extra latency cycles since wbck is 6 cycles
449 InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
450 InstrStage<1, [A9_Pipe1]>,
451 InstrStage<1, [A9_NPipe]>], [4, 2]>,
453 // Double-register Integer Q-Unary
454 InstrItinData<IIC_VQUNAiD, [InstrStage<1, [A9_DRegsN], 0, Required>,
455 // Extra latency cycles since wbck is 6 cycles
456 InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
457 InstrStage<1, [A9_Pipe1]>,
458 InstrStage<1, [A9_NPipe]>], [4, 1]>,
460 // Quad-register Integer CountQ-Unary
461 InstrItinData<IIC_VQUNAiQ, [InstrStage<1, [A9_DRegsN], 0, Required>,
462 // Extra latency cycles since wbck is 6 cycles
463 InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
464 InstrStage<1, [A9_Pipe1]>,
465 InstrStage<1, [A9_NPipe]>], [4, 1]>,
467 // Double-register Integer Binary
468 InstrItinData<IIC_VBINiD, [InstrStage<1, [A9_DRegsN], 0, Required>,
469 // Extra latency cycles since wbck is 6 cycles
470 InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
471 InstrStage<1, [A9_Pipe1]>,
472 InstrStage<1, [A9_NPipe]>], [3, 2, 2]>,
474 // Quad-register Integer Binary
475 InstrItinData<IIC_VBINiQ, [InstrStage<1, [A9_DRegsN], 0, Required>,
476 // Extra latency cycles since wbck is 6 cycles
477 InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
478 InstrStage<1, [A9_Pipe1]>,
479 InstrStage<1, [A9_NPipe]>], [3, 2, 2]>,
481 // Double-register Integer Subtract
482 InstrItinData<IIC_VSUBiD, [InstrStage<1, [A9_DRegsN], 0, Required>,
483 // Extra latency cycles since wbck is 6 cycles
484 InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
485 InstrStage<1, [A9_Pipe1]>,
486 InstrStage<1, [A9_NPipe]>], [3, 2, 1]>,
488 // Quad-register Integer Subtract
489 InstrItinData<IIC_VSUBiQ, [InstrStage<1, [A9_DRegsN], 0, Required>,
490 // Extra latency cycles since wbck is 6 cycles
491 InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
492 InstrStage<1, [A9_Pipe1]>,
493 InstrStage<1, [A9_NPipe]>], [3, 2, 1]>,
495 // Double-register Integer Shift
496 InstrItinData<IIC_VSHLiD, [InstrStage<1, [A9_DRegsN], 0, Required>,
497 // Extra latency cycles since wbck is 6 cycles
498 InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
499 InstrStage<1, [A9_Pipe1]>,
500 InstrStage<1, [A9_NPipe]>], [3, 1, 1]>,
502 // Quad-register Integer Shift
503 InstrItinData<IIC_VSHLiQ, [InstrStage<1, [A9_DRegsN], 0, Required>,
504 // Extra latency cycles since wbck is 6 cycles
505 InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
506 InstrStage<1, [A9_Pipe1]>,
507 InstrStage<1, [A9_NPipe]>], [3, 1, 1]>,
509 // Double-register Integer Shift (4 cycle)
510 InstrItinData<IIC_VSHLi4D, [InstrStage<1, [A9_DRegsN], 0, Required>,
511 // Extra latency cycles since wbck is 6 cycles
512 InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
513 InstrStage<1, [A9_Pipe1]>,
514 InstrStage<1, [A9_NPipe]>], [4, 1, 1]>,
516 // Quad-register Integer Shift (4 cycle)
517 InstrItinData<IIC_VSHLi4Q, [InstrStage<1, [A9_DRegsN], 0, Required>,
518 // Extra latency cycles since wbck is 6 cycles
519 InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
520 InstrStage<1, [A9_Pipe1]>,
521 InstrStage<1, [A9_NPipe]>], [4, 1, 1]>,
523 // Double-register Integer Binary (4 cycle)
524 InstrItinData<IIC_VBINi4D, [InstrStage<1, [A9_DRegsN], 0, Required>,
525 // Extra latency cycles since wbck is 6 cycles
526 InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
527 InstrStage<1, [A9_Pipe1]>,
528 InstrStage<1, [A9_NPipe]>], [4, 2, 2]>,
530 // Quad-register Integer Binary (4 cycle)
531 InstrItinData<IIC_VBINi4Q, [InstrStage<1, [A9_DRegsN], 0, Required>,
532 // Extra latency cycles since wbck is 6 cycles
533 InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
534 InstrStage<1, [A9_Pipe1]>,
535 InstrStage<1, [A9_NPipe]>], [4, 2, 2]>,
537 // Double-register Integer Subtract (4 cycle)
538 InstrItinData<IIC_VSUBiD, [InstrStage<1, [A9_DRegsN], 0, Required>,
539 // Extra latency cycles since wbck is 6 cycles
540 InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
541 InstrStage<1, [A9_Pipe1]>,
542 InstrStage<1, [A9_NPipe]>], [4, 2, 1]>,
544 // Quad-register Integer Subtract (4 cycle)
545 InstrItinData<IIC_VSUBiQ, [InstrStage<1, [A9_DRegsN], 0, Required>,
546 // Extra latency cycles since wbck is 6 cycles
547 InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
548 InstrStage<1, [A9_Pipe1]>,
549 InstrStage<1, [A9_NPipe]>], [4, 2, 1]>,
552 // Double-register Integer Count
553 InstrItinData<IIC_VCNTiD, [InstrStage<1, [A9_DRegsN], 0, Required>,
554 // Extra latency cycles since wbck is 6 cycles
555 InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
556 InstrStage<1, [A9_Pipe1]>,
557 InstrStage<1, [A9_NPipe]>], [3, 2, 2]>,
559 // Quad-register Integer Count
560 // Result written in N3, but that is relative to the last cycle of multicycle,
561 // so we use 4 for those cases
562 InstrItinData<IIC_VCNTiQ, [InstrStage<1, [A9_DRegsN], 0, Required>,
563 // Extra latency cycles since wbck is 7 cycles
564 InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
565 InstrStage<1, [A9_Pipe1]>,
566 InstrStage<2, [A9_NPipe]>], [4, 2, 2]>,
568 // Double-register Absolute Difference and Accumulate
569 InstrItinData<IIC_VABAD, [InstrStage<1, [A9_DRegsN], 0, Required>,
570 // Extra latency cycles since wbck is 6 cycles
571 InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
572 InstrStage<1, [A9_Pipe1]>,
573 InstrStage<1, [A9_NPipe]>], [6, 3, 2, 1]>,
575 // Quad-register Absolute Difference and Accumulate
576 InstrItinData<IIC_VABAQ, [InstrStage<1, [A9_DRegsN], 0, Required>,
577 // Extra latency cycles since wbck is 6 cycles
578 InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
579 InstrStage<1, [A9_Pipe1]>,
580 InstrStage<2, [A9_NPipe]>], [6, 3, 2, 1]>,
582 // Double-register Integer Pair Add Long
583 InstrItinData<IIC_VPALiD, [InstrStage<1, [A9_DRegsN], 0, Required>,
584 // Extra latency cycles since wbck is 6 cycles
585 InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
586 InstrStage<1, [A9_Pipe1]>,
587 InstrStage<1, [A9_NPipe]>], [6, 3, 1]>,
589 // Quad-register Integer Pair Add Long
590 InstrItinData<IIC_VPALiQ, [InstrStage<1, [A9_DRegsN], 0, Required>,
591 // Extra latency cycles since wbck is 6 cycles
592 InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
593 InstrStage<1, [A9_Pipe1]>,
594 InstrStage<2, [A9_NPipe]>], [6, 3, 1]>,
597 // Double-register Integer Multiply (.8, .16)
598 InstrItinData<IIC_VMULi16D, [InstrStage<1, [A9_DRegsN], 0, Required>,
599 // Extra latency cycles since wbck is 6 cycles
600 InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
601 InstrStage<1, [A9_Pipe1]>,
602 InstrStage<1, [A9_NPipe]>], [6, 2, 2]>,
604 // Quad-register Integer Multiply (.8, .16)
605 InstrItinData<IIC_VMULi16Q, [InstrStage<1, [A9_DRegsN], 0, Required>,
606 // Extra latency cycles since wbck is 7 cycles
607 InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
608 InstrStage<1, [A9_Pipe1]>,
609 InstrStage<2, [A9_NPipe]>], [7, 2, 2]>,
612 // Double-register Integer Multiply (.32)
613 InstrItinData<IIC_VMULi32D, [InstrStage<1, [A9_DRegsN], 0, Required>,
614 // Extra latency cycles since wbck is 7 cycles
615 InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
616 InstrStage<1, [A9_Pipe1]>,
617 InstrStage<2, [A9_NPipe]>], [7, 2, 1]>,
619 // Quad-register Integer Multiply (.32)
620 InstrItinData<IIC_VMULi32Q, [InstrStage<1, [A9_DRegsN], 0, Required>,
621 // Extra latency cycles since wbck is 9 cycles
622 InstrStage<10, [A9_DRegsVFP], 0, Reserved>,
623 InstrStage<1, [A9_Pipe1]>,
624 InstrStage<4, [A9_NPipe]>], [9, 2, 1]>,
626 // Double-register Integer Multiply-Accumulate (.8, .16)
627 InstrItinData<IIC_VMACi16D, [InstrStage<1, [A9_DRegsN], 0, Required>,
628 // Extra latency cycles since wbck is 6 cycles
629 InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
630 InstrStage<1, [A9_Pipe1]>,
631 InstrStage<1, [A9_NPipe]>], [6, 3, 2, 2]>,
633 // Double-register Integer Multiply-Accumulate (.32)
634 InstrItinData<IIC_VMACi32D, [InstrStage<1, [A9_DRegsN], 0, Required>,
635 // Extra latency cycles since wbck is 7 cycles
636 InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
637 InstrStage<1, [A9_Pipe1]>,
638 InstrStage<2, [A9_NPipe]>], [7, 3, 2, 1]>,
640 // Quad-register Integer Multiply-Accumulate (.8, .16)
641 InstrItinData<IIC_VMACi16Q, [InstrStage<1, [A9_DRegsN], 0, Required>,
642 // Extra latency cycles since wbck is 7 cycles
643 InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
644 InstrStage<1, [A9_Pipe1]>,
645 InstrStage<2, [A9_NPipe]>], [7, 3, 2, 2]>,
647 // Quad-register Integer Multiply-Accumulate (.32)
648 InstrItinData<IIC_VMACi32Q, [InstrStage<1, [A9_DRegsN], 0, Required>,
649 // Extra latency cycles since wbck is 9 cycles
650 InstrStage<10, [A9_DRegsVFP], 0, Reserved>,
651 InstrStage<1, [A9_Pipe1]>,
652 InstrStage<4, [A9_NPipe]>], [9, 3, 2, 1]>,
655 InstrItinData<IIC_VMOVImm, [InstrStage<1, [A9_DRegsN], 0, Required>,
656 // Extra latency cycles since wbck is 6 cycles
657 InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
658 InstrStage<1, [A9_Pipe1]>,
659 InstrStage<1, [A9_NPipe]>], [3]>,
661 // Double-register Permute Move
662 InstrItinData<IIC_VMOVD, [InstrStage<1, [A9_DRegsN], 0, Required>,
663 // FIXME: all latencies are arbitrary, no information is available
664 InstrStage<3, [A9_DRegsVFP], 0, Reserved>,
665 InstrStage<1, [A9_Pipe1]>,
666 InstrStage<1, [A9_LSPipe]>], [2, 1]>,
668 // Quad-register Permute Move
669 // Result written in N2, but that is relative to the last cycle of multicycle,
670 // so we use 3 for those cases
671 InstrItinData<IIC_VMOVQ, [InstrStage<1, [A9_DRegsN], 0, Required>,
672 // FIXME: all latencies are arbitrary, no information is available
673 InstrStage<4, [A9_DRegsVFP], 0, Reserved>,
674 InstrStage<1, [A9_Pipe1]>,
675 InstrStage<2, [A9_NPipe]>], [3, 1]>,
677 // Integer to Single-precision Move
678 InstrItinData<IIC_VMOVIS , [InstrStage<1, [A9_DRegsN], 0, Required>,
679 // FIXME: all latencies are arbitrary, no information is available
680 InstrStage<3, [A9_DRegsVFP], 0, Reserved>,
681 InstrStage<1, [A9_Pipe1]>,
682 InstrStage<1, [A9_NPipe]>], [2, 1]>,
684 // Integer to Double-precision Move
685 InstrItinData<IIC_VMOVID , [InstrStage<1, [A9_DRegsN], 0, Required>,
686 // FIXME: all latencies are arbitrary, no information is available
687 InstrStage<3, [A9_DRegsVFP], 0, Reserved>,
688 InstrStage<1, [A9_Pipe1]>,
689 InstrStage<1, [A9_NPipe]>], [2, 1, 1]>,
691 // Single-precision to Integer Move
692 InstrItinData<IIC_VMOVSI , [InstrStage<1, [A9_DRegsN], 0, Required>,
693 // FIXME: all latencies are arbitrary, no information is available
694 InstrStage<3, [A9_DRegsVFP], 0, Reserved>,
695 InstrStage<1, [A9_Pipe1]>,
696 InstrStage<1, [A9_NPipe]>], [2, 1]>,
698 // Double-precision to Integer Move
699 InstrItinData<IIC_VMOVDI , [InstrStage<1, [A9_DRegsN], 0, Required>,
700 // FIXME: all latencies are arbitrary, no information is available
701 InstrStage<3, [A9_DRegsVFP], 0, Reserved>,
702 InstrStage<1, [A9_Pipe1]>,
703 InstrStage<1, [A9_NPipe]>], [2, 2, 1]>,
705 // Integer to Lane Move
706 InstrItinData<IIC_VMOVISL , [InstrStage<1, [A9_DRegsN], 0, Required>,
707 // FIXME: all latencies are arbitrary, no information is available
708 InstrStage<4, [A9_DRegsVFP], 0, Reserved>,
709 InstrStage<1, [A9_Pipe1]>,
710 InstrStage<2, [A9_NPipe]>], [3, 1, 1]>,
713 // Double-register FP Unary
714 InstrItinData<IIC_VUNAD, [InstrStage<1, [A9_DRegsN], 0, Required>,
715 // Extra latency cycles since wbck is 6 cycles
716 InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
717 InstrStage<1, [A9_Pipe1]>,
718 InstrStage<1, [A9_NPipe]>], [5, 2]>,
720 // Quad-register FP Unary
721 // Result written in N5, but that is relative to the last cycle of multicycle,
722 // so we use 6 for those cases
723 InstrItinData<IIC_VUNAQ, [InstrStage<1, [A9_DRegsN], 0, Required>,
724 // Extra latency cycles since wbck is 7 cycles
725 InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
726 InstrStage<1, [A9_Pipe1]>,
727 InstrStage<2, [A9_NPipe]>], [6, 2]>,
729 // Double-register FP Binary
730 // FIXME: We're using this itin for many instructions and [2, 2] here is too
732 InstrItinData<IIC_VBIND, [InstrStage<1, [A9_DRegsN], 0, Required>,
733 // Extra latency cycles since wbck is 7 cycles
734 InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
735 InstrStage<1, [A9_Pipe1]>,
736 InstrStage<1, [A9_NPipe]>], [5, 2, 2]>,
738 // Quad-register FP Binary
739 // Result written in N5, but that is relative to the last cycle of multicycle,
740 // so we use 6 for those cases
741 // FIXME: We're using this itin for many instructions and [2, 2] here is too
743 InstrItinData<IIC_VBINQ, [InstrStage<1, [A9_DRegsN], 0, Required>,
744 // Extra latency cycles since wbck is 8 cycles
745 InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
746 InstrStage<1, [A9_Pipe1]>,
747 InstrStage<2, [A9_NPipe]>], [6, 2, 2]>,
749 // Double-register FP Multiple-Accumulate
750 InstrItinData<IIC_VMACD, [InstrStage<1, [A9_DRegsN], 0, Required>,
751 // Extra latency cycles since wbck is 7 cycles
752 InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
753 InstrStage<1, [A9_Pipe1]>,
754 InstrStage<2, [A9_NPipe]>], [6, 3, 2, 1]>,
756 // Quad-register FP Multiple-Accumulate
757 // Result written in N9, but that is relative to the last cycle of multicycle,
758 // so we use 10 for those cases
759 InstrItinData<IIC_VMACQ, [InstrStage<1, [A9_DRegsN], 0, Required>,
760 // Extra latency cycles since wbck is 9 cycles
761 InstrStage<10, [A9_DRegsVFP], 0, Reserved>,
762 InstrStage<1, [A9_Pipe1]>,
763 InstrStage<4, [A9_NPipe]>], [8, 4, 2, 1]>,
765 // Double-register Reciprical Step
766 InstrItinData<IIC_VRECSD, [InstrStage<1, [A9_DRegsN], 0, Required>,
767 // Extra latency cycles since wbck is 7 cycles
768 InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
769 InstrStage<1, [A9_Pipe1]>,
770 InstrStage<2, [A9_NPipe]>], [6, 2, 2]>,
772 // Quad-register Reciprical Step
773 InstrItinData<IIC_VRECSQ, [InstrStage<1, [A9_DRegsN], 0, Required>,
774 // Extra latency cycles since wbck is 9 cycles
775 InstrStage<10, [A9_DRegsVFP], 0, Reserved>,
776 InstrStage<1, [A9_Pipe1]>,
777 InstrStage<4, [A9_NPipe]>], [8, 2, 2]>,
779 // Double-register Permute
780 InstrItinData<IIC_VPERMD, [InstrStage<1, [A9_DRegsN], 0, Required>,
781 // Extra latency cycles since wbck is 6 cycles
782 InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
783 InstrStage<1, [A9_Pipe1]>,
784 InstrStage<1, [A9_NPipe]>], [2, 2, 1, 1]>,
786 // Quad-register Permute
787 // Result written in N2, but that is relative to the last cycle of multicycle,
788 // so we use 3 for those cases
789 InstrItinData<IIC_VPERMQ, [InstrStage<1, [A9_DRegsN], 0, Required>,
790 // Extra latency cycles since wbck is 7 cycles
791 InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
792 InstrStage<1, [A9_Pipe1]>,
793 InstrStage<2, [A9_NPipe]>], [3, 3, 1, 1]>,
795 // Quad-register Permute (3 cycle issue)
796 // Result written in N2, but that is relative to the last cycle of multicycle,
797 // so we use 4 for those cases
798 InstrItinData<IIC_VPERMQ3, [InstrStage<1, [A9_DRegsN], 0, Required>,
799 // Extra latency cycles since wbck is 8 cycles
800 InstrStage<9, [A9_DRegsVFP], 0, Reserved>,
801 InstrStage<1, [A9_Pipe1]>,
802 InstrStage<3, [A9_LSPipe]>], [4, 4, 1, 1]>,
805 // Double-register VEXT
806 InstrItinData<IIC_VEXTD, [InstrStage<1, [A9_DRegsN], 0, Required>,
807 // Extra latency cycles since wbck is 7 cycles
808 InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
809 InstrStage<1, [A9_Pipe1]>,
810 InstrStage<1, [A9_NPipe]>], [2, 1, 1]>,
812 // Quad-register VEXT
813 InstrItinData<IIC_VEXTQ, [InstrStage<1, [A9_DRegsN], 0, Required>,
814 // Extra latency cycles since wbck is 9 cycles
815 InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
816 InstrStage<1, [A9_Pipe1]>,
817 InstrStage<2, [A9_NPipe]>], [3, 1, 1]>,
820 InstrItinData<IIC_VTB1, [InstrStage<1, [A9_DRegsN], 0, Required>,
821 // Extra latency cycles since wbck is 7 cycles
822 InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
823 InstrStage<1, [A9_Pipe1]>,
824 InstrStage<2, [A9_NPipe]>], [3, 2, 1]>,
825 InstrItinData<IIC_VTB2, [InstrStage<2, [A9_DRegsN], 0, Required>,
826 // Extra latency cycles since wbck is 7 cycles
827 InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
828 InstrStage<1, [A9_Pipe1]>,
829 InstrStage<2, [A9_NPipe]>], [3, 2, 2, 1]>,
830 InstrItinData<IIC_VTB3, [InstrStage<2, [A9_DRegsN], 0, Required>,
831 // Extra latency cycles since wbck is 8 cycles
832 InstrStage<9, [A9_DRegsVFP], 0, Reserved>,
833 InstrStage<1, [A9_Pipe1]>,
834 InstrStage<3, [A9_NPipe]>], [4, 2, 2, 3, 1]>,
835 InstrItinData<IIC_VTB4, [InstrStage<1, [A9_DRegsN], 0, Required>,
836 // Extra latency cycles since wbck is 8 cycles
837 InstrStage<9, [A9_DRegsVFP], 0, Reserved>,
838 InstrStage<1, [A9_Pipe1]>,
839 InstrStage<3, [A9_NPipe]>], [4, 2, 2, 3, 3, 1]>,
842 InstrItinData<IIC_VTBX1, [InstrStage<1, [A9_DRegsN], 0, Required>,
843 // Extra latency cycles since wbck is 7 cycles
844 InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
845 InstrStage<1, [A9_Pipe1]>,
846 InstrStage<2, [A9_NPipe]>], [3, 1, 2, 1]>,
847 InstrItinData<IIC_VTBX2, [InstrStage<1, [A9_DRegsN], 0, Required>,
848 // Extra latency cycles since wbck is 7 cycles
849 InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
850 InstrStage<1, [A9_Pipe1]>,
851 InstrStage<2, [A9_NPipe]>], [3, 1, 2, 2, 1]>,
852 InstrItinData<IIC_VTBX3, [InstrStage<1, [A9_DRegsN], 0, Required>,
853 // Extra latency cycles since wbck is 8 cycles
854 InstrStage<9, [A9_DRegsVFP], 0, Reserved>,
855 InstrStage<1, [A9_Pipe1]>,
856 InstrStage<3, [A9_NPipe]>], [4, 1, 2, 2, 3, 1]>,
857 InstrItinData<IIC_VTBX4, [InstrStage<1, [A9_DRegsN], 0, Required>,
858 // Extra latency cycles since wbck is 8 cycles
859 InstrStage<9, [A9_DRegsVFP], 0, Reserved>,
860 InstrStage<1, [A9_Pipe1]>,
861 InstrStage<2, [A9_NPipe]>], [4, 1, 2, 2, 3, 3, 1]>