1 //===- ARMRegisterInfo.h - ARM Register Information Impl --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the ARM implementation of the TargetRegisterInfo class.
12 //===----------------------------------------------------------------------===//
14 #ifndef ARMREGISTERINFO_H
15 #define ARMREGISTERINFO_H
17 #include "llvm/Target/TargetRegisterInfo.h"
18 #include "ARMGenRegisterInfo.h.inc"
22 class TargetInstrInfo;
25 /// Register allocation hints.
33 struct ARMRegisterInfo : public ARMGenRegisterInfo {
34 const TargetInstrInfo &TII;
35 const ARMSubtarget &STI;
38 ARMRegisterInfo(const TargetInstrInfo &tii, const ARMSubtarget &STI);
40 /// emitLoadConstPool - Emits a load from constpool to materialize the
41 /// specified immediate.
42 void emitLoadConstPool(MachineBasicBlock &MBB,
43 MachineBasicBlock::iterator &MBBI,
44 unsigned DestReg, int Val,
45 unsigned Pred, unsigned PredReg,
46 const TargetInstrInfo *TII, bool isThumb,
49 /// getRegisterNumbering - Given the enum value for some register, e.g.
50 /// ARM::LR, return the number that it corresponds to (e.g. 14).
51 static unsigned getRegisterNumbering(unsigned RegEnum);
53 /// Same as previous getRegisterNumbering except it returns true in isSPVFP
54 /// if the register is a single precision VFP register.
55 static unsigned getRegisterNumbering(unsigned RegEnum, bool &isSPVFP);
57 /// Code Generation virtual methods...
58 const TargetRegisterClass *
59 getPhysicalRegisterRegClass(unsigned Reg, MVT VT = MVT::Other) const;
60 const unsigned *getCalleeSavedRegs(const MachineFunction *MF = 0) const;
62 const TargetRegisterClass* const*
63 getCalleeSavedRegClasses(const MachineFunction *MF = 0) const;
65 BitVector getReservedRegs(const MachineFunction &MF) const;
67 bool isReservedReg(const MachineFunction &MF, unsigned Reg) const;
69 const TargetRegisterClass *getPointerRegClass() const;
71 std::pair<TargetRegisterClass::iterator,TargetRegisterClass::iterator>
72 getAllocationOrder(const TargetRegisterClass *RC,
73 std::pair<unsigned,unsigned> Hint,
74 const MachineFunction &MF) const;
76 unsigned ResolveRegAllocHint(unsigned Type, unsigned Reg,
77 const MachineFunction &MF) const;
79 bool requiresRegisterScavenging(const MachineFunction &MF) const;
81 bool hasFP(const MachineFunction &MF) const;
83 bool hasReservedCallFrame(MachineFunction &MF) const;
85 void eliminateCallFramePseudoInstr(MachineFunction &MF,
86 MachineBasicBlock &MBB,
87 MachineBasicBlock::iterator I) const;
89 void eliminateFrameIndex(MachineBasicBlock::iterator II,
90 int SPAdj, RegScavenger *RS = NULL) const;
92 void processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
93 RegScavenger *RS = NULL) const;
95 void emitPrologue(MachineFunction &MF) const;
96 void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const;
98 // Debug information queries.
99 unsigned getRARegister() const;
100 unsigned getFrameRegister(MachineFunction &MF) const;
102 // Exception handling queries.
103 unsigned getEHExceptionRegister() const;
104 unsigned getEHHandlerRegister() const;
106 int getDwarfRegNum(unsigned RegNum, bool isEH) const;
108 bool isLowRegister(unsigned Reg) const;
111 /// FramePtr - ARM physical register used as frame ptr.
114 unsigned getRegisterPairEven(unsigned Reg, const MachineFunction &MF) const;
116 unsigned getRegisterPairOdd(unsigned Reg, const MachineFunction &MF) const;
120 } // end namespace llvm