lib/Target/ARM/ARMRegisterInfo.cpp

   1 //===- ARMRegisterInfo.cpp - ARM Register Information -----------*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file was developed by the "Instituto Nokia de Tecnologia" and
   6 // is distributed under the University of Illinois Open Source
   7 // License. See LICENSE.TXT for details.
   8 //
   9 //===----------------------------------------------------------------------===//
  10 //
  11 // This file contains the ARM implementation of the MRegisterInfo class.
  12 //
  13 //===----------------------------------------------------------------------===//
  14
  15 #include "ARM.h"
  16 #include "ARMRegisterInfo.h"
  17 #include "llvm/CodeGen/MachineInstrBuilder.h"
  18 #include "llvm/CodeGen/MachineFunction.h"
  19 #include "llvm/CodeGen/MachineFrameInfo.h"
  20 #include "llvm/CodeGen/MachineLocation.h"
  21 #include "llvm/Type.h"
  22 #include "llvm/ADT/STLExtras.h"
  23 #include <iostream>
  24 using namespace llvm;
  25
  26 ARMRegisterInfo::ARMRegisterInfo()
  27   : ARMGenRegisterInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP) {
  28 }
  29
  30 void ARMRegisterInfo::
  31 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
  32                     unsigned SrcReg, int FI,
  33                     const TargetRegisterClass *RC) const {
  34   // On the order of operands here: think "[FI + 0] = SrcReg".
  35   assert (RC == ARM::IntRegsRegisterClass);
  36   BuildMI(MBB, I, ARM::str, 3).addFrameIndex(FI).addImm(0).addReg(SrcReg);
  37 }
  38
  39 void ARMRegisterInfo::
  40 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
  41                      unsigned DestReg, int FI,
  42                      const TargetRegisterClass *RC) const {
  43   assert (RC == ARM::IntRegsRegisterClass);
  44   BuildMI(MBB, I, ARM::ldr, 2, DestReg).addFrameIndex(FI).addImm(0);
  45 }
  46
  47 void ARMRegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
  48                                      MachineBasicBlock::iterator I,
  49                                      unsigned DestReg, unsigned SrcReg,
  50                                      const TargetRegisterClass *RC) const {
  51   assert (RC == ARM::IntRegsRegisterClass);
  52   BuildMI(MBB, I, ARM::mov, 1, DestReg).addReg(SrcReg);
  53 }
  54
  55 MachineInstr *ARMRegisterInfo::foldMemoryOperand(MachineInstr* MI,
  56                                                    unsigned OpNum,
  57                                                    int FI) const {
  58   return NULL;
  59 }
  60
  61 void ARMRegisterInfo::
  62 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
  63                               MachineBasicBlock::iterator I) const {
  64   MBB.erase(I);
  65 }
  66
  67 void
  68 ARMRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const {
  69   assert(0 && "Not Implemented");
  70 }
  71
  72 void ARMRegisterInfo::
  73 processFunctionBeforeFrameFinalized(MachineFunction &MF) const {}
  74
  75 void ARMRegisterInfo::emitPrologue(MachineFunction &MF) const {
  76 }
  77
  78 void ARMRegisterInfo::emitEpilogue(MachineFunction &MF,
  79                                    MachineBasicBlock &MBB) const {
  80 }
  81
  82 unsigned ARMRegisterInfo::getRARegister() const {
  83   return ARM::R14;
  84 }
  85
  86 unsigned ARMRegisterInfo::getFrameRegister(MachineFunction &MF) const {
  87   return ARM::R13;
  88 }
  89
  90 #include "ARMGenRegisterInfo.inc"
  91