1 //===- ARMRegisterInfo.cpp - ARM Register Information -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the "Instituto Nokia de Tecnologia" and
6 // is distributed under the University of Illinois Open Source
7 // License. See LICENSE.TXT for details.
9 //===----------------------------------------------------------------------===//
11 // This file contains the ARM implementation of the MRegisterInfo class.
13 //===----------------------------------------------------------------------===//
16 #include "ARMRegisterInfo.h"
17 #include "llvm/CodeGen/MachineInstrBuilder.h"
18 #include "llvm/CodeGen/MachineFunction.h"
19 #include "llvm/CodeGen/MachineFrameInfo.h"
20 #include "llvm/CodeGen/MachineLocation.h"
21 #include "llvm/Type.h"
22 #include "llvm/ADT/STLExtras.h"
26 ARMRegisterInfo::ARMRegisterInfo()
27 : ARMGenRegisterInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP) {
30 void ARMRegisterInfo::
31 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
32 unsigned SrcReg, int FI,
33 const TargetRegisterClass *RC) const {
34 assert (RC == ARM::IntRegsRegisterClass);
35 BuildMI(MBB, I, ARM::str, 3).addReg(SrcReg).addImm(0).addFrameIndex(FI);
38 void ARMRegisterInfo::
39 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
40 unsigned DestReg, int FI,
41 const TargetRegisterClass *RC) const {
42 assert (RC == ARM::IntRegsRegisterClass);
43 BuildMI(MBB, I, ARM::ldr, 2, DestReg).addImm(0).addFrameIndex(FI);
46 void ARMRegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
47 MachineBasicBlock::iterator I,
48 unsigned DestReg, unsigned SrcReg,
49 const TargetRegisterClass *RC) const {
50 assert (RC == ARM::IntRegsRegisterClass);
51 BuildMI(MBB, I, ARM::movrr, 1, DestReg).addReg(SrcReg);
54 MachineInstr *ARMRegisterInfo::foldMemoryOperand(MachineInstr* MI,
60 const unsigned* ARMRegisterInfo::getCalleeSaveRegs() const {
61 static const unsigned CalleeSaveRegs[] = { 0 };
62 return CalleeSaveRegs;
65 const TargetRegisterClass* const *
66 ARMRegisterInfo::getCalleeSaveRegClasses() const {
67 static const TargetRegisterClass * const CalleeSaveRegClasses[] = { 0 };
68 return CalleeSaveRegClasses;
71 void ARMRegisterInfo::
72 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
73 MachineBasicBlock::iterator I) const {
78 ARMRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const {
79 MachineInstr &MI = *II;
80 MachineBasicBlock &MBB = *MI.getParent();
81 MachineFunction &MF = *MBB.getParent();
83 assert (MI.getOpcode() == ARM::ldr ||
84 MI.getOpcode() == ARM::str);
86 unsigned FrameIdx = 2;
89 int FrameIndex = MI.getOperand(FrameIdx).getFrameIndex();
91 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
92 assert (MI.getOperand(OffIdx).getImmedValue() == 0);
94 unsigned StackSize = MF.getFrameInfo()->getStackSize();
103 assert (Offset >= 0);
105 // Replace the FrameIndex with r13
106 MI.getOperand(FrameIdx).ChangeToRegister(ARM::R13);
107 // Replace the ldr offset with Offset
108 MI.getOperand(OffIdx).ChangeToImmediate(Offset);
110 // Insert a set of r12 with the full address
111 // r12 = r13 + offset
112 MachineBasicBlock *MBB2 = MI.getParent();
113 BuildMI(*MBB2, II, ARM::addri, 2, ARM::R12).addReg(ARM::R13).addImm(Offset);
115 // Replace the FrameIndex with r12
116 MI.getOperand(FrameIdx).ChangeToRegister(ARM::R12);
120 void ARMRegisterInfo::
121 processFunctionBeforeFrameFinalized(MachineFunction &MF) const {}
123 void ARMRegisterInfo::emitPrologue(MachineFunction &MF) const {
124 MachineBasicBlock &MBB = MF.front();
125 MachineBasicBlock::iterator MBBI = MBB.begin();
126 MachineFrameInfo *MFI = MF.getFrameInfo();
127 int NumBytes = (int) MFI->getStackSize();
129 if (MFI->hasCalls()) {
130 // We reserve argument space for call sites in the function immediately on
131 // entry to the current function. This eliminates the need for add/sub
132 // brackets around call sites.
133 NumBytes += MFI->getMaxCallFrameSize();
138 MFI->setStackSize(NumBytes);
140 //sub sp, sp, #NumBytes
141 BuildMI(MBB, MBBI, ARM::subri, 2, ARM::R13).addReg(ARM::R13).addImm(NumBytes);
142 //str lr, [sp, #NumBytes - 4]
143 BuildMI(MBB, MBBI, ARM::str, 2, ARM::R14).addImm(NumBytes - 4).addReg(ARM::R13);
146 void ARMRegisterInfo::emitEpilogue(MachineFunction &MF,
147 MachineBasicBlock &MBB) const {
148 MachineBasicBlock::iterator MBBI = prior(MBB.end());
149 assert(MBBI->getOpcode() == ARM::bx &&
150 "Can only insert epilog into returning blocks");
152 MachineFrameInfo *MFI = MF.getFrameInfo();
153 int NumBytes = (int) MFI->getStackSize();
156 BuildMI(MBB, MBBI, ARM::ldr, 2, ARM::R14).addImm(NumBytes - 4).addReg(ARM::R13);
157 //add sp, sp, #NumBytes
158 BuildMI(MBB, MBBI, ARM::addri, 2, ARM::R13).addReg(ARM::R13).addImm(NumBytes);
161 unsigned ARMRegisterInfo::getRARegister() const {
165 unsigned ARMRegisterInfo::getFrameRegister(MachineFunction &MF) const {
169 #include "ARMGenRegisterInfo.inc"