1 //===- ARMRegisterInfo.cpp - ARM Register Information -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the "Instituto Nokia de Tecnologia" and
6 // is distributed under the University of Illinois Open Source
7 // License. See LICENSE.TXT for details.
9 //===----------------------------------------------------------------------===//
11 // This file contains the ARM implementation of the MRegisterInfo class.
13 //===----------------------------------------------------------------------===//
16 #include "ARMAddressingModes.h"
17 #include "ARMInstrInfo.h"
18 #include "ARMMachineFunctionInfo.h"
19 #include "ARMRegisterInfo.h"
20 #include "ARMSubtarget.h"
21 #include "llvm/Constants.h"
22 #include "llvm/DerivedTypes.h"
23 #include "llvm/CodeGen/MachineConstantPool.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineFunction.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineLocation.h"
28 #include "llvm/CodeGen/RegisterScavenging.h"
29 #include "llvm/Target/TargetFrameInfo.h"
30 #include "llvm/Target/TargetMachine.h"
31 #include "llvm/Target/TargetOptions.h"
32 #include "llvm/ADT/BitVector.h"
33 #include "llvm/ADT/SmallVector.h"
34 #include "llvm/ADT/STLExtras.h"
35 #include "llvm/Support/CommandLine.h"
39 static cl::opt<bool> ThumbRegScavenging("enable-thumb-reg-scavenging",
41 cl::desc("Enable register scavenging on Thumb"));
43 unsigned ARMRegisterInfo::getRegisterNumbering(unsigned RegEnum) {
46 case R0: case S0: case D0: return 0;
47 case R1: case S1: case D1: return 1;
48 case R2: case S2: case D2: return 2;
49 case R3: case S3: case D3: return 3;
50 case R4: case S4: case D4: return 4;
51 case R5: case S5: case D5: return 5;
52 case R6: case S6: case D6: return 6;
53 case R7: case S7: case D7: return 7;
54 case R8: case S8: case D8: return 8;
55 case R9: case S9: case D9: return 9;
56 case R10: case S10: case D10: return 10;
57 case R11: case S11: case D11: return 11;
58 case R12: case S12: case D12: return 12;
59 case SP: case S13: case D13: return 13;
60 case LR: case S14: case D14: return 14;
61 case PC: case S15: case D15: return 15;
79 assert(0 && "Unknown ARM register!");
84 ARMRegisterInfo::ARMRegisterInfo(const TargetInstrInfo &tii,
85 const ARMSubtarget &sti)
86 : ARMGenRegisterInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP),
88 FramePtr((STI.useThumbBacktraces() || STI.isThumb()) ? ARM::R7 : ARM::R11) {
91 bool ARMRegisterInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
92 MachineBasicBlock::iterator MI,
93 const std::vector<CalleeSavedInfo> &CSI) const {
94 MachineFunction &MF = *MBB.getParent();
95 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
96 if (!AFI->isThumbFunction() || CSI.empty())
99 MachineInstrBuilder MIB = BuildMI(MBB, MI, TII.get(ARM::tPUSH));
100 for (unsigned i = CSI.size(); i != 0; --i) {
101 unsigned Reg = CSI[i-1].getReg();
102 // Add the callee-saved register as live-in. It's killed at the spill.
104 MIB.addReg(Reg, false/*isDef*/,false/*isImp*/,true/*isKill*/);
109 bool ARMRegisterInfo::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
110 MachineBasicBlock::iterator MI,
111 const std::vector<CalleeSavedInfo> &CSI) const {
112 MachineFunction &MF = *MBB.getParent();
113 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
114 if (!AFI->isThumbFunction() || CSI.empty())
117 bool isVarArg = AFI->getVarArgsRegSaveSize() > 0;
118 MachineInstr *PopMI = new MachineInstr(TII.get(ARM::tPOP));
119 MBB.insert(MI, PopMI);
120 for (unsigned i = CSI.size(); i != 0; --i) {
121 unsigned Reg = CSI[i-1].getReg();
122 if (Reg == ARM::LR) {
123 // Special epilogue for vararg functions. See emitEpilogue
127 PopMI->setInstrDescriptor(TII.get(ARM::tPOP_RET));
130 PopMI->addRegOperand(Reg, true);
135 void ARMRegisterInfo::
136 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
137 unsigned SrcReg, int FI,
138 const TargetRegisterClass *RC) const {
139 if (RC == ARM::GPRRegisterClass) {
140 MachineFunction &MF = *MBB.getParent();
141 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
142 if (AFI->isThumbFunction())
143 BuildMI(MBB, I, TII.get(ARM::tSpill)).addReg(SrcReg, false, false, true)
144 .addFrameIndex(FI).addImm(0);
146 BuildMI(MBB, I, TII.get(ARM::STR)).addReg(SrcReg, false, false, true)
147 .addFrameIndex(FI).addReg(0).addImm(0);
148 } else if (RC == ARM::DPRRegisterClass) {
149 BuildMI(MBB, I, TII.get(ARM::FSTD)).addReg(SrcReg, false, false, true)
150 .addFrameIndex(FI).addImm(0);
152 assert(RC == ARM::SPRRegisterClass && "Unknown regclass!");
153 BuildMI(MBB, I, TII.get(ARM::FSTS)).addReg(SrcReg, false, false, true)
154 .addFrameIndex(FI).addImm(0);
158 void ARMRegisterInfo::
159 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
160 unsigned DestReg, int FI,
161 const TargetRegisterClass *RC) const {
162 if (RC == ARM::GPRRegisterClass) {
163 MachineFunction &MF = *MBB.getParent();
164 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
165 if (AFI->isThumbFunction())
166 BuildMI(MBB, I, TII.get(ARM::tRestore), DestReg)
167 .addFrameIndex(FI).addImm(0);
169 BuildMI(MBB, I, TII.get(ARM::LDR), DestReg)
170 .addFrameIndex(FI).addReg(0).addImm(0);
171 } else if (RC == ARM::DPRRegisterClass) {
172 BuildMI(MBB, I, TII.get(ARM::FLDD), DestReg)
173 .addFrameIndex(FI).addImm(0);
175 assert(RC == ARM::SPRRegisterClass && "Unknown regclass!");
176 BuildMI(MBB, I, TII.get(ARM::FLDS), DestReg)
177 .addFrameIndex(FI).addImm(0);
181 void ARMRegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
182 MachineBasicBlock::iterator I,
183 unsigned DestReg, unsigned SrcReg,
184 const TargetRegisterClass *RC) const {
185 if (RC == ARM::GPRRegisterClass) {
186 MachineFunction &MF = *MBB.getParent();
187 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
188 BuildMI(MBB, I, TII.get(AFI->isThumbFunction() ? ARM::tMOVr : ARM::MOVr),
189 DestReg).addReg(SrcReg);
190 } else if (RC == ARM::SPRRegisterClass)
191 BuildMI(MBB, I, TII.get(ARM::FCPYS), DestReg).addReg(SrcReg);
192 else if (RC == ARM::DPRRegisterClass)
193 BuildMI(MBB, I, TII.get(ARM::FCPYD), DestReg).addReg(SrcReg);
198 /// emitLoadConstPool - Emits a load from constpool to materialize the
199 /// specified immediate.
200 static void emitLoadConstPool(MachineBasicBlock &MBB,
201 MachineBasicBlock::iterator &MBBI,
202 unsigned DestReg, int Val,
203 const TargetInstrInfo &TII, bool isThumb) {
204 MachineFunction &MF = *MBB.getParent();
205 MachineConstantPool *ConstantPool = MF.getConstantPool();
206 Constant *C = ConstantInt::get(Type::Int32Ty, Val);
207 unsigned Idx = ConstantPool->getConstantPoolIndex(C, 2);
209 BuildMI(MBB, MBBI, TII.get(ARM::tLDRcp), DestReg).addConstantPoolIndex(Idx);
211 BuildMI(MBB, MBBI, TII.get(ARM::LDRcp), DestReg).addConstantPoolIndex(Idx)
212 .addReg(0).addImm(0);
215 void ARMRegisterInfo::reMaterialize(MachineBasicBlock &MBB,
216 MachineBasicBlock::iterator I,
218 const MachineInstr *Orig) const {
219 if (Orig->getOpcode() == ARM::MOVi2pieces) {
220 emitLoadConstPool(MBB, I, DestReg, Orig->getOperand(1).getImmedValue(),
225 MachineInstr *MI = Orig->clone();
226 MI->getOperand(0).setReg(DestReg);
230 /// isLowRegister - Returns true if the register is low register r0-r7.
232 static bool isLowRegister(unsigned Reg) {
235 case R0: case R1: case R2: case R3:
236 case R4: case R5: case R6: case R7:
243 MachineInstr *ARMRegisterInfo::foldMemoryOperand(MachineInstr *MI,
244 unsigned OpNum, int FI) const {
245 unsigned Opc = MI->getOpcode();
246 MachineInstr *NewMI = NULL;
250 if (OpNum == 0) { // move -> store
251 unsigned SrcReg = MI->getOperand(1).getReg();
252 NewMI = BuildMI(TII.get(ARM::STR)).addReg(SrcReg).addFrameIndex(FI)
253 .addReg(0).addImm(0);
254 } else { // move -> load
255 unsigned DstReg = MI->getOperand(0).getReg();
256 NewMI = BuildMI(TII.get(ARM::LDR), DstReg).addFrameIndex(FI).addReg(0)
262 if (OpNum == 0) { // move -> store
263 unsigned SrcReg = MI->getOperand(1).getReg();
264 if (isPhysicalRegister(SrcReg) && !isLowRegister(SrcReg))
265 // tSpill cannot take a high register operand.
267 NewMI = BuildMI(TII.get(ARM::tSpill)).addReg(SrcReg).addFrameIndex(FI)
269 } else { // move -> load
270 unsigned DstReg = MI->getOperand(0).getReg();
271 if (isPhysicalRegister(DstReg) && !isLowRegister(DstReg))
272 // tRestore cannot target a high register operand.
274 NewMI = BuildMI(TII.get(ARM::tRestore), DstReg).addFrameIndex(FI)
280 if (OpNum == 0) { // move -> store
281 unsigned SrcReg = MI->getOperand(1).getReg();
282 NewMI = BuildMI(TII.get(ARM::FSTS)).addReg(SrcReg).addFrameIndex(FI)
284 } else { // move -> load
285 unsigned DstReg = MI->getOperand(0).getReg();
286 NewMI = BuildMI(TII.get(ARM::FLDS), DstReg).addFrameIndex(FI).addImm(0);
291 if (OpNum == 0) { // move -> store
292 unsigned SrcReg = MI->getOperand(1).getReg();
293 NewMI = BuildMI(TII.get(ARM::FSTD)).addReg(SrcReg).addFrameIndex(FI)
295 } else { // move -> load
296 unsigned DstReg = MI->getOperand(0).getReg();
297 NewMI = BuildMI(TII.get(ARM::FLDD), DstReg).addFrameIndex(FI).addImm(0);
304 NewMI->copyKillDeadInfo(MI);
308 const unsigned* ARMRegisterInfo::getCalleeSavedRegs() const {
309 static const unsigned CalleeSavedRegs[] = {
310 ARM::LR, ARM::R11, ARM::R10, ARM::R9, ARM::R8,
311 ARM::R7, ARM::R6, ARM::R5, ARM::R4,
313 ARM::D15, ARM::D14, ARM::D13, ARM::D12,
314 ARM::D11, ARM::D10, ARM::D9, ARM::D8,
318 static const unsigned DarwinCalleeSavedRegs[] = {
319 ARM::LR, ARM::R7, ARM::R6, ARM::R5, ARM::R4,
320 ARM::R11, ARM::R10, ARM::R9, ARM::R8,
322 ARM::D15, ARM::D14, ARM::D13, ARM::D12,
323 ARM::D11, ARM::D10, ARM::D9, ARM::D8,
326 return STI.isTargetDarwin() ? DarwinCalleeSavedRegs : CalleeSavedRegs;
329 const TargetRegisterClass* const *
330 ARMRegisterInfo::getCalleeSavedRegClasses() const {
331 static const TargetRegisterClass * const CalleeSavedRegClasses[] = {
332 &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
333 &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
334 &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
336 &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
337 &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
340 return CalleeSavedRegClasses;
343 BitVector ARMRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
344 // FIXME: avoid re-calculating this everytime.
345 BitVector Reserved(getNumRegs());
346 Reserved.set(ARM::SP);
347 Reserved.set(ARM::PC);
348 if (STI.isTargetDarwin() || hasFP(MF))
349 Reserved.set(FramePtr);
350 // Some targets reserve R9.
351 if (STI.isR9Reserved())
352 Reserved.set(ARM::R9);
357 ARMRegisterInfo::isReservedReg(const MachineFunction &MF, unsigned Reg) const {
365 if (FramePtr == Reg && (STI.isTargetDarwin() || hasFP(MF)))
369 return STI.isR9Reserved();
376 ARMRegisterInfo::requiresRegisterScavenging(const MachineFunction &MF) const {
377 const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
378 return ThumbRegScavenging || !AFI->isThumbFunction();
381 /// hasFP - Return true if the specified function should have a dedicated frame
382 /// pointer register. This is true if the function has variable sized allocas
383 /// or if frame pointer elimination is disabled.
385 bool ARMRegisterInfo::hasFP(const MachineFunction &MF) const {
386 return NoFramePointerElim || MF.getFrameInfo()->hasVarSizedObjects();
389 // hasReservedCallFrame - Under normal circumstances, when a frame pointer is
390 // not required, we reserve argument space for call sites in the function
391 // immediately on entry to the current function. This eliminates the need for
392 // add/sub sp brackets around call sites. Returns true if the call frame is
393 // included as part of the stack frame.
394 bool ARMRegisterInfo::hasReservedCallFrame(MachineFunction &MF) const {
395 const MachineFrameInfo *FFI = MF.getFrameInfo();
396 unsigned CFSize = FFI->getMaxCallFrameSize();
397 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
398 // It's not always a good idea to include the call frame as part of the
399 // stack frame. ARM (especially Thumb) has small immediate offset to
400 // address the stack frame. So a large call frame can cause poor codegen
401 // and may even makes it impossible to scavenge a register.
402 if (AFI->isThumbFunction()) {
403 if (CFSize >= ((1 << 8) - 1) * 4 / 2) // Half of imm8 * 4
406 if (CFSize >= ((1 << 12) - 1) / 2) // Half of imm12
412 /// emitARMRegPlusImmediate - Emits a series of instructions to materialize
413 /// a destreg = basereg + immediate in ARM code.
415 void emitARMRegPlusImmediate(MachineBasicBlock &MBB,
416 MachineBasicBlock::iterator &MBBI,
417 unsigned DestReg, unsigned BaseReg,
418 int NumBytes, const TargetInstrInfo &TII) {
419 bool isSub = NumBytes < 0;
420 if (isSub) NumBytes = -NumBytes;
423 unsigned RotAmt = ARM_AM::getSOImmValRotate(NumBytes);
424 unsigned ThisVal = NumBytes & ARM_AM::rotr32(0xFF, RotAmt);
425 assert(ThisVal && "Didn't extract field correctly");
427 // We will handle these bits from offset, clear them.
428 NumBytes &= ~ThisVal;
430 // Get the properly encoded SOImmVal field.
431 int SOImmVal = ARM_AM::getSOImmVal(ThisVal);
432 assert(SOImmVal != -1 && "Bit extraction didn't work?");
434 // Build the new ADD / SUB.
435 BuildMI(MBB, MBBI, TII.get(isSub ? ARM::SUBri : ARM::ADDri), DestReg)
436 .addReg(BaseReg, false, false, true).addImm(SOImmVal);
441 /// calcNumMI - Returns the number of instructions required to materialize
442 /// the specific add / sub r, c instruction.
443 static unsigned calcNumMI(int Opc, int ExtraOpc, unsigned Bytes,
444 unsigned NumBits, unsigned Scale) {
446 unsigned Chunk = ((1 << NumBits) - 1) * Scale;
448 if (Opc == ARM::tADDrSPi) {
449 unsigned ThisVal = (Bytes > Chunk) ? Chunk : Bytes;
453 Scale = 1; // Followed by a number of tADDi8.
454 Chunk = ((1 << NumBits) - 1) * Scale;
457 NumMIs += Bytes / Chunk;
458 if ((Bytes % Chunk) != 0)
465 /// emitThumbRegPlusImmInReg - Emits a series of instructions to materialize
466 /// a destreg = basereg + immediate in Thumb code. Materialize the immediate
467 /// in a register using mov / mvn sequences or load the immediate from a
470 void emitThumbRegPlusImmInReg(MachineBasicBlock &MBB,
471 MachineBasicBlock::iterator &MBBI,
472 unsigned DestReg, unsigned BaseReg,
473 int NumBytes, bool CanChangeCC,
474 const TargetInstrInfo &TII) {
475 bool isHigh = !isLowRegister(DestReg) ||
476 (BaseReg != 0 && !isLowRegister(BaseReg));
478 // Subtract doesn't have high register version. Load the negative value
479 // if either base or dest register is a high register. Also, if do not
480 // issue sub as part of the sequence if condition register is to be
482 if (NumBytes < 0 && !isHigh && CanChangeCC) {
484 NumBytes = -NumBytes;
486 unsigned LdReg = DestReg;
487 if (DestReg == ARM::SP) {
488 assert(BaseReg == ARM::SP && "Unexpected!");
490 BuildMI(MBB, MBBI, TII.get(ARM::tMOVr), ARM::R12)
491 .addReg(ARM::R3, false, false, true);
494 if (NumBytes <= 255 && NumBytes >= 0)
495 BuildMI(MBB, MBBI, TII.get(ARM::tMOVi8), LdReg).addImm(NumBytes);
496 else if (NumBytes < 0 && NumBytes >= -255) {
497 BuildMI(MBB, MBBI, TII.get(ARM::tMOVi8), LdReg).addImm(NumBytes);
498 BuildMI(MBB, MBBI, TII.get(ARM::tNEG), LdReg)
499 .addReg(LdReg, false, false, true);
501 emitLoadConstPool(MBB, MBBI, LdReg, NumBytes, TII, true);
504 int Opc = (isSub) ? ARM::tSUBrr : (isHigh ? ARM::tADDhirr : ARM::tADDrr);
505 const MachineInstrBuilder MIB = BuildMI(MBB, MBBI, TII.get(Opc), DestReg);
506 if (DestReg == ARM::SP || isSub)
507 MIB.addReg(BaseReg).addReg(LdReg, false, false, true);
509 MIB.addReg(LdReg).addReg(BaseReg, false, false, true);
510 if (DestReg == ARM::SP)
511 BuildMI(MBB, MBBI, TII.get(ARM::tMOVr), ARM::R3)
512 .addReg(ARM::R12, false, false, true);
515 /// emitThumbRegPlusImmediate - Emits a series of instructions to materialize
516 /// a destreg = basereg + immediate in Thumb code.
518 void emitThumbRegPlusImmediate(MachineBasicBlock &MBB,
519 MachineBasicBlock::iterator &MBBI,
520 unsigned DestReg, unsigned BaseReg,
521 int NumBytes, const TargetInstrInfo &TII) {
522 bool isSub = NumBytes < 0;
523 unsigned Bytes = (unsigned)NumBytes;
524 if (isSub) Bytes = -NumBytes;
525 bool isMul4 = (Bytes & 3) == 0;
526 bool isTwoAddr = false;
527 bool DstNotEqBase = false;
528 unsigned NumBits = 1;
533 if (DestReg == BaseReg && BaseReg == ARM::SP) {
534 assert(isMul4 && "Thumb sp inc / dec size must be multiple of 4!");
537 Opc = isSub ? ARM::tSUBspi : ARM::tADDspi;
539 } else if (!isSub && BaseReg == ARM::SP) {
542 // r1 = add sp, 100 * 4
546 ExtraOpc = ARM::tADDi3;
555 if (DestReg != BaseReg)
558 Opc = isSub ? ARM::tSUBi8 : ARM::tADDi8;
562 unsigned NumMIs = calcNumMI(Opc, ExtraOpc, Bytes, NumBits, Scale);
563 unsigned Threshold = (DestReg == ARM::SP) ? 3 : 2;
564 if (NumMIs > Threshold) {
565 // This will expand into too many instructions. Load the immediate from a
567 emitThumbRegPlusImmInReg(MBB, MBBI, DestReg, BaseReg, NumBytes, true, TII);
572 if (isLowRegister(DestReg) && isLowRegister(BaseReg)) {
573 // If both are low registers, emit DestReg = add BaseReg, max(Imm, 7)
574 unsigned Chunk = (1 << 3) - 1;
575 unsigned ThisVal = (Bytes > Chunk) ? Chunk : Bytes;
577 BuildMI(MBB, MBBI, TII.get(isSub ? ARM::tSUBi3 : ARM::tADDi3), DestReg)
578 .addReg(BaseReg, false, false, true).addImm(ThisVal);
580 BuildMI(MBB, MBBI, TII.get(ARM::tMOVr), DestReg)
581 .addReg(BaseReg, false, false, true);
586 unsigned Chunk = ((1 << NumBits) - 1) * Scale;
588 unsigned ThisVal = (Bytes > Chunk) ? Chunk : Bytes;
591 // Build the new tADD / tSUB.
593 BuildMI(MBB, MBBI, TII.get(Opc), DestReg).addReg(DestReg).addImm(ThisVal);
595 bool isKill = BaseReg != ARM::SP;
596 BuildMI(MBB, MBBI, TII.get(Opc), DestReg)
597 .addReg(BaseReg, false, false, isKill).addImm(ThisVal);
600 if (Opc == ARM::tADDrSPi) {
606 Chunk = ((1 << NumBits) - 1) * Scale;
607 Opc = isSub ? ARM::tSUBi8 : ARM::tADDi8;
614 BuildMI(MBB, MBBI, TII.get(ExtraOpc), DestReg)
615 .addReg(DestReg, false, false, true)
616 .addImm(((unsigned)NumBytes) & 3);
620 void emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
621 int NumBytes, bool isThumb, const TargetInstrInfo &TII) {
623 emitThumbRegPlusImmediate(MBB, MBBI, ARM::SP, ARM::SP, NumBytes, TII);
625 emitARMRegPlusImmediate(MBB, MBBI, ARM::SP, ARM::SP, NumBytes, TII);
628 void ARMRegisterInfo::
629 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
630 MachineBasicBlock::iterator I) const {
631 if (!hasReservedCallFrame(MF)) {
632 // If we have alloca, convert as follows:
633 // ADJCALLSTACKDOWN -> sub, sp, sp, amount
634 // ADJCALLSTACKUP -> add, sp, sp, amount
635 MachineInstr *Old = I;
636 unsigned Amount = Old->getOperand(0).getImmedValue();
638 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
639 // We need to keep the stack aligned properly. To do this, we round the
640 // amount of space needed for the outgoing arguments up to the next
641 // alignment boundary.
642 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
643 Amount = (Amount+Align-1)/Align*Align;
645 // Replace the pseudo instruction with a new instruction...
646 if (Old->getOpcode() == ARM::ADJCALLSTACKDOWN) {
647 emitSPUpdate(MBB, I, -Amount, AFI->isThumbFunction(), TII);
649 assert(Old->getOpcode() == ARM::ADJCALLSTACKUP);
650 emitSPUpdate(MBB, I, Amount, AFI->isThumbFunction(), TII);
657 /// emitThumbConstant - Emit a series of instructions to materialize a
659 static void emitThumbConstant(MachineBasicBlock &MBB,
660 MachineBasicBlock::iterator &MBBI,
661 unsigned DestReg, int Imm,
662 const TargetInstrInfo &TII) {
663 bool isSub = Imm < 0;
664 if (isSub) Imm = -Imm;
666 int Chunk = (1 << 8) - 1;
667 int ThisVal = (Imm > Chunk) ? Chunk : Imm;
669 BuildMI(MBB, MBBI, TII.get(ARM::tMOVi8), DestReg).addImm(ThisVal);
671 emitThumbRegPlusImmediate(MBB, MBBI, DestReg, DestReg, Imm, TII);
673 BuildMI(MBB, MBBI, TII.get(ARM::tNEG), DestReg)
674 .addReg(DestReg, false, false, true);
677 /// findScratchRegister - Find a 'free' ARM register. If register scavenger
678 /// is not being used, R12 is available. Otherwise, try for a call-clobbered
679 /// register first and then a spilled callee-saved register if that fails.
681 unsigned findScratchRegister(RegScavenger *RS, const TargetRegisterClass *RC,
682 ARMFunctionInfo *AFI) {
683 unsigned Reg = RS ? RS->FindUnusedReg(RC, true) : (unsigned) ARM::R12;
685 // Try a already spilled CS register.
686 Reg = RS->FindUnusedReg(RC, AFI->getSpilledCSRegisters());
691 void ARMRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
692 int SPAdj, RegScavenger *RS) const{
694 MachineInstr &MI = *II;
695 MachineBasicBlock &MBB = *MI.getParent();
696 MachineFunction &MF = *MBB.getParent();
697 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
698 bool isThumb = AFI->isThumbFunction();
700 while (!MI.getOperand(i).isFrameIndex()) {
702 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
705 unsigned FrameReg = ARM::SP;
706 int FrameIndex = MI.getOperand(i).getFrameIndex();
707 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
708 MF.getFrameInfo()->getStackSize() + SPAdj;
710 if (AFI->isGPRCalleeSavedArea1Frame(FrameIndex))
711 Offset -= AFI->getGPRCalleeSavedArea1Offset();
712 else if (AFI->isGPRCalleeSavedArea2Frame(FrameIndex))
713 Offset -= AFI->getGPRCalleeSavedArea2Offset();
714 else if (AFI->isDPRCalleeSavedAreaFrame(FrameIndex))
715 Offset -= AFI->getDPRCalleeSavedAreaOffset();
716 else if (hasFP(MF)) {
717 assert(SPAdj == 0 && "Unexpected");
718 // There is alloca()'s in this function, must reference off the frame
720 FrameReg = getFrameRegister(MF);
721 Offset -= AFI->getFramePtrSpillOffset();
724 unsigned Opcode = MI.getOpcode();
725 const TargetInstrDescriptor &Desc = TII.get(Opcode);
726 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
729 if (Opcode == ARM::ADDri) {
730 Offset += MI.getOperand(i+1).getImm();
732 // Turn it into a move.
733 MI.setInstrDescriptor(TII.get(ARM::MOVr));
734 MI.getOperand(i).ChangeToRegister(FrameReg, false);
735 MI.RemoveOperand(i+1);
737 } else if (Offset < 0) {
740 MI.setInstrDescriptor(TII.get(ARM::SUBri));
743 // Common case: small offset, fits into instruction.
744 int ImmedOffset = ARM_AM::getSOImmVal(Offset);
745 if (ImmedOffset != -1) {
746 // Replace the FrameIndex with sp / fp
747 MI.getOperand(i).ChangeToRegister(FrameReg, false);
748 MI.getOperand(i+1).ChangeToImmediate(ImmedOffset);
752 // Otherwise, we fallback to common code below to form the imm offset with
753 // a sequence of ADDri instructions. First though, pull as much of the imm
754 // into this ADDri as possible.
755 unsigned RotAmt = ARM_AM::getSOImmValRotate(Offset);
756 unsigned ThisImmVal = Offset & ARM_AM::rotr32(0xFF, RotAmt);
758 // We will handle these bits from offset, clear them.
759 Offset &= ~ThisImmVal;
761 // Get the properly encoded SOImmVal field.
762 int ThisSOImmVal = ARM_AM::getSOImmVal(ThisImmVal);
763 assert(ThisSOImmVal != -1 && "Bit extraction didn't work?");
764 MI.getOperand(i+1).ChangeToImmediate(ThisSOImmVal);
765 } else if (Opcode == ARM::tADDrSPi) {
766 Offset += MI.getOperand(i+1).getImm();
768 // Can't use tADDrSPi if it's based off the frame pointer.
769 unsigned NumBits = 0;
771 if (FrameReg != ARM::SP) {
772 Opcode = ARM::tADDi3;
773 MI.setInstrDescriptor(TII.get(ARM::tADDi3));
778 assert((Offset & 3) == 0 &&
779 "Thumb add/sub sp, #imm immediate must be multiple of 4!");
783 // Turn it into a move.
784 MI.setInstrDescriptor(TII.get(ARM::tMOVr));
785 MI.getOperand(i).ChangeToRegister(FrameReg, false);
786 MI.RemoveOperand(i+1);
790 // Common case: small offset, fits into instruction.
791 unsigned Mask = (1 << NumBits) - 1;
792 if (((Offset / Scale) & ~Mask) == 0) {
793 // Replace the FrameIndex with sp / fp
794 MI.getOperand(i).ChangeToRegister(FrameReg, false);
795 MI.getOperand(i+1).ChangeToImmediate(Offset / Scale);
799 unsigned DestReg = MI.getOperand(0).getReg();
800 unsigned Bytes = (Offset > 0) ? Offset : -Offset;
801 unsigned NumMIs = calcNumMI(Opcode, 0, Bytes, NumBits, Scale);
802 // MI would expand into a large number of instructions. Don't try to
803 // simplify the immediate.
805 emitThumbRegPlusImmediate(MBB, II, DestReg, FrameReg, Offset, TII);
811 // Translate r0 = add sp, imm to
812 // r0 = add sp, 255*4
813 // r0 = add r0, (imm - 255*4)
814 MI.getOperand(i).ChangeToRegister(FrameReg, false);
815 MI.getOperand(i+1).ChangeToImmediate(Mask);
816 Offset = (Offset - Mask * Scale);
817 MachineBasicBlock::iterator NII = next(II);
818 emitThumbRegPlusImmediate(MBB, NII, DestReg, DestReg, Offset, TII);
820 // Translate r0 = add sp, -imm to
821 // r0 = -imm (this is then translated into a series of instructons)
823 emitThumbConstant(MBB, II, DestReg, Offset, TII);
824 MI.setInstrDescriptor(TII.get(ARM::tADDhirr));
825 MI.getOperand(i).ChangeToRegister(DestReg, false, false, true);
826 MI.getOperand(i+1).ChangeToRegister(FrameReg, false);
832 unsigned NumBits = 0;
835 case ARMII::AddrMode2: {
837 InstrOffs = ARM_AM::getAM2Offset(MI.getOperand(ImmIdx).getImm());
838 if (ARM_AM::getAM2Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
843 case ARMII::AddrMode3: {
845 InstrOffs = ARM_AM::getAM3Offset(MI.getOperand(ImmIdx).getImm());
846 if (ARM_AM::getAM3Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
851 case ARMII::AddrMode5: {
853 InstrOffs = ARM_AM::getAM5Offset(MI.getOperand(ImmIdx).getImm());
854 if (ARM_AM::getAM5Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
860 case ARMII::AddrModeTs: {
862 InstrOffs = MI.getOperand(ImmIdx).getImm();
863 NumBits = (FrameReg == ARM::SP) ? 8 : 5;
868 assert(0 && "Unsupported addressing mode!");
873 Offset += InstrOffs * Scale;
874 assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!");
875 if (Offset < 0 && !isThumb) {
880 // Common case: small offset, fits into instruction.
881 MachineOperand &ImmOp = MI.getOperand(ImmIdx);
882 int ImmedOffset = Offset / Scale;
883 unsigned Mask = (1 << NumBits) - 1;
884 if ((unsigned)Offset <= Mask * Scale) {
885 // Replace the FrameIndex with sp
886 MI.getOperand(i).ChangeToRegister(FrameReg, false);
888 ImmedOffset |= 1 << NumBits;
889 ImmOp.ChangeToImmediate(ImmedOffset);
893 bool isThumSpillRestore = Opcode == ARM::tRestore || Opcode == ARM::tSpill;
894 if (AddrMode == ARMII::AddrModeTs) {
895 // Thumb tLDRspi, tSTRspi. These will change to instructions that use
896 // a different base register.
898 Mask = (1 << NumBits) - 1;
900 // If this is a thumb spill / restore, we will be using a constpool load to
901 // materialize the offset.
902 if (AddrMode == ARMII::AddrModeTs && isThumSpillRestore)
903 ImmOp.ChangeToImmediate(0);
905 // Otherwise, it didn't fit. Pull in what we can to simplify the immed.
906 ImmedOffset = ImmedOffset & Mask;
908 ImmedOffset |= 1 << NumBits;
909 ImmOp.ChangeToImmediate(ImmedOffset);
910 Offset &= ~(Mask*Scale);
914 // If we get here, the immediate doesn't fit into the instruction. We folded
915 // as much as possible above, handle the rest, providing a register that is
917 assert(Offset && "This code isn't needed if offset already handled!");
920 if (TII.isLoad(Opcode)) {
921 // Use the destination register to materialize sp + offset.
922 unsigned TmpReg = MI.getOperand(0).getReg();
924 if (Opcode == ARM::tRestore) {
925 if (FrameReg == ARM::SP)
926 emitThumbRegPlusImmInReg(MBB, II, TmpReg, FrameReg,Offset,false,TII);
928 emitLoadConstPool(MBB, II, TmpReg, Offset, TII, true);
932 emitThumbRegPlusImmediate(MBB, II, TmpReg, FrameReg, Offset, TII);
933 MI.setInstrDescriptor(TII.get(ARM::tLDR));
934 MI.getOperand(i).ChangeToRegister(TmpReg, false, false, true);
936 MI.addRegOperand(FrameReg, false); // Use [reg, reg] addrmode.
938 MI.addRegOperand(0, false); // tLDR has an extra register operand.
939 } else if (TII.isStore(Opcode)) {
940 // FIXME! This is horrific!!! We need register scavenging.
941 // Our temporary workaround has marked r3 unavailable. Of course, r3 is
942 // also a ABI register so it's possible that is is the register that is
943 // being storing here. If that's the case, we do the following:
945 // Use r2 to materialize sp + offset
948 unsigned ValReg = MI.getOperand(0).getReg();
949 unsigned TmpReg = ARM::R3;
951 if (ValReg == ARM::R3) {
952 BuildMI(MBB, II, TII.get(ARM::tMOVr), ARM::R12)
953 .addReg(ARM::R2, false, false, true);
956 if (TmpReg == ARM::R3 && AFI->isR3LiveIn())
957 BuildMI(MBB, II, TII.get(ARM::tMOVr), ARM::R12)
958 .addReg(ARM::R3, false, false, true);
959 if (Opcode == ARM::tSpill) {
960 if (FrameReg == ARM::SP)
961 emitThumbRegPlusImmInReg(MBB, II, TmpReg, FrameReg,Offset,false,TII);
963 emitLoadConstPool(MBB, II, TmpReg, Offset, TII, true);
967 emitThumbRegPlusImmediate(MBB, II, TmpReg, FrameReg, Offset, TII);
968 MI.setInstrDescriptor(TII.get(ARM::tSTR));
969 MI.getOperand(i).ChangeToRegister(TmpReg, false, false, true);
971 MI.addRegOperand(FrameReg, false); // Use [reg, reg] addrmode.
973 MI.addRegOperand(0, false); // tSTR has an extra register operand.
975 MachineBasicBlock::iterator NII = next(II);
976 if (ValReg == ARM::R3)
977 BuildMI(MBB, NII, TII.get(ARM::tMOVr), ARM::R2)
978 .addReg(ARM::R12, false, false, true);
979 if (TmpReg == ARM::R3 && AFI->isR3LiveIn())
980 BuildMI(MBB, NII, TII.get(ARM::tMOVr), ARM::R3)
981 .addReg(ARM::R12, false, false, true);
983 assert(false && "Unexpected opcode!");
985 // Insert a set of r12 with the full address: r12 = sp + offset
986 // If the offset we have is too large to fit into the instruction, we need
987 // to form it with a series of ADDri's. Do this by taking 8-bit chunks
989 unsigned ScratchReg = findScratchRegister(RS, &ARM::GPRRegClass, AFI);
991 // No register is "free". Scavenge a register.
992 ScratchReg = RS->scavengeRegister(&ARM::GPRRegClass, II, SPAdj);
993 emitARMRegPlusImmediate(MBB, II, ScratchReg, FrameReg,
994 isSub ? -Offset : Offset, TII);
995 MI.getOperand(i).ChangeToRegister(ScratchReg, false, false, true);
999 static unsigned estimateStackSize(MachineFunction &MF, MachineFrameInfo *MFI) {
1000 const MachineFrameInfo *FFI = MF.getFrameInfo();
1002 for (int i = FFI->getObjectIndexBegin(); i != 0; ++i) {
1003 int FixedOff = -FFI->getObjectOffset(i);
1004 if (FixedOff > Offset) Offset = FixedOff;
1006 for (unsigned i = 0, e = FFI->getObjectIndexEnd(); i != e; ++i) {
1007 Offset += FFI->getObjectSize(i);
1008 unsigned Align = FFI->getObjectAlignment(i);
1009 // Adjust to alignment boundary
1010 Offset = (Offset+Align-1)/Align*Align;
1012 return (unsigned)Offset;
1016 ARMRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
1017 RegScavenger *RS) const {
1018 // This tells PEI to spill the FP as if it is any other callee-save register
1019 // to take advantage the eliminateFrameIndex machinery. This also ensures it
1020 // is spilled in the order specified by getCalleeSavedRegs() to make it easier
1021 // to combine multiple loads / stores.
1022 bool CanEliminateFrame = true;
1023 bool CS1Spilled = false;
1024 bool LRSpilled = false;
1025 unsigned NumGPRSpills = 0;
1026 SmallVector<unsigned, 4> UnspilledCS1GPRs;
1027 SmallVector<unsigned, 4> UnspilledCS2GPRs;
1028 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1030 // Don't spill FP if the frame can be eliminated. This is determined
1031 // by scanning the callee-save registers to see if any is used.
1032 const unsigned *CSRegs = getCalleeSavedRegs();
1033 const TargetRegisterClass* const *CSRegClasses = getCalleeSavedRegClasses();
1034 for (unsigned i = 0; CSRegs[i]; ++i) {
1035 unsigned Reg = CSRegs[i];
1036 bool Spilled = false;
1037 if (MF.isPhysRegUsed(Reg)) {
1038 AFI->setCSRegisterIsSpilled(Reg);
1040 CanEliminateFrame = false;
1042 // Check alias registers too.
1043 for (const unsigned *Aliases = getAliasSet(Reg); *Aliases; ++Aliases) {
1044 if (MF.isPhysRegUsed(*Aliases)) {
1046 CanEliminateFrame = false;
1051 if (CSRegClasses[i] == &ARM::GPRRegClass) {
1055 if (!STI.isTargetDarwin()) {
1062 // Keep track if LR and any of R4, R5, R6, and R7 is spilled.
1077 if (!STI.isTargetDarwin()) {
1078 UnspilledCS1GPRs.push_back(Reg);
1088 UnspilledCS1GPRs.push_back(Reg);
1091 UnspilledCS2GPRs.push_back(Reg);
1098 bool ForceLRSpill = false;
1099 if (!LRSpilled && AFI->isThumbFunction()) {
1100 unsigned FnSize = ARM::GetFunctionSize(MF);
1101 // Force LR to be spilled if the Thumb function size is > 2048. This enables
1102 // use of BL to implement far jump. If it turns out that it's not needed
1103 // then the branch fix up path will undo it.
1104 if (FnSize >= (1 << 11)) {
1105 CanEliminateFrame = false;
1106 ForceLRSpill = true;
1110 bool ExtraCSSpill = false;
1111 if (!CanEliminateFrame || hasFP(MF)) {
1112 AFI->setHasStackFrame(true);
1114 // If LR is not spilled, but at least one of R4, R5, R6, and R7 is spilled.
1115 // Spill LR as well so we can fold BX_RET to the registers restore (LDM).
1116 if (!LRSpilled && CS1Spilled) {
1117 MF.setPhysRegUsed(ARM::LR);
1118 AFI->setCSRegisterIsSpilled(ARM::LR);
1120 UnspilledCS1GPRs.erase(std::find(UnspilledCS1GPRs.begin(),
1121 UnspilledCS1GPRs.end(), (unsigned)ARM::LR));
1122 ForceLRSpill = false;
1123 ExtraCSSpill = true;
1126 // Darwin ABI requires FP to point to the stack slot that contains the
1128 if (STI.isTargetDarwin() || hasFP(MF)) {
1129 MF.setPhysRegUsed(FramePtr);
1133 // If stack and double are 8-byte aligned and we are spilling an odd number
1134 // of GPRs. Spill one extra callee save GPR so we won't have to pad between
1135 // the integer and double callee save areas.
1136 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
1137 if (TargetAlign == 8 && (NumGPRSpills & 1)) {
1138 if (CS1Spilled && !UnspilledCS1GPRs.empty()) {
1139 for (unsigned i = 0, e = UnspilledCS1GPRs.size(); i != e; ++i) {
1140 unsigned Reg = UnspilledCS1GPRs[i];
1141 // Don't spiil high register if the function is thumb
1142 if (!AFI->isThumbFunction() || isLowRegister(Reg) || Reg == ARM::LR) {
1143 MF.setPhysRegUsed(Reg);
1144 AFI->setCSRegisterIsSpilled(Reg);
1145 if (!isReservedReg(MF, Reg))
1146 ExtraCSSpill = true;
1150 } else if (!UnspilledCS2GPRs.empty() &&
1151 !AFI->isThumbFunction()) {
1152 unsigned Reg = UnspilledCS2GPRs.front();
1153 MF.setPhysRegUsed(Reg);
1154 AFI->setCSRegisterIsSpilled(Reg);
1155 if (!isReservedReg(MF, Reg))
1156 ExtraCSSpill = true;
1160 // Estimate if we might need to scavenge a register at some point in order
1161 // to materialize a stack offset. If so, either spill one additiona
1162 // callee-saved register or reserve a special spill slot to facilitate
1163 // register scavenging.
1164 if (RS && !ExtraCSSpill && !AFI->isThumbFunction()) {
1165 MachineFrameInfo *MFI = MF.getFrameInfo();
1166 unsigned Size = estimateStackSize(MF, MFI);
1167 unsigned Limit = (1 << 12) - 1;
1168 for (MachineFunction::iterator BB = MF.begin(),E = MF.end();BB != E; ++BB)
1169 for (MachineBasicBlock::iterator I= BB->begin(); I != BB->end(); ++I) {
1170 for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i)
1171 if (I->getOperand(i).isFrameIndex()) {
1172 unsigned Opcode = I->getOpcode();
1173 const TargetInstrDescriptor &Desc = TII.get(Opcode);
1174 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
1175 if (AddrMode == ARMII::AddrMode3) {
1176 Limit = (1 << 8) - 1;
1177 goto DoneEstimating;
1178 } else if (AddrMode == ARMII::AddrMode5) {
1179 unsigned ThisLimit = ((1 << 8) - 1) * 4;
1180 if (ThisLimit < Limit)
1186 if (Size >= Limit) {
1187 // If any non-reserved CS register isn't spilled, just spill one or two
1188 // extra. That should take care of it!
1189 unsigned NumExtras = TargetAlign / 4;
1190 SmallVector<unsigned, 2> Extras;
1191 while (NumExtras && !UnspilledCS1GPRs.empty()) {
1192 unsigned Reg = UnspilledCS1GPRs.back();
1193 UnspilledCS1GPRs.pop_back();
1194 if (!isReservedReg(MF, Reg)) {
1195 Extras.push_back(Reg);
1199 while (NumExtras && !UnspilledCS2GPRs.empty()) {
1200 unsigned Reg = UnspilledCS2GPRs.back();
1201 UnspilledCS2GPRs.pop_back();
1202 if (!isReservedReg(MF, Reg)) {
1203 Extras.push_back(Reg);
1207 if (Extras.size() && NumExtras == 0) {
1208 for (unsigned i = 0, e = Extras.size(); i != e; ++i) {
1209 MF.setPhysRegUsed(Extras[i]);
1210 AFI->setCSRegisterIsSpilled(Extras[i]);
1213 // Reserve a slot closest to SP or frame pointer.
1214 const TargetRegisterClass *RC = &ARM::GPRRegClass;
1215 RS->setScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(),
1216 RC->getAlignment()));
1223 MF.setPhysRegUsed(ARM::LR);
1224 AFI->setCSRegisterIsSpilled(ARM::LR);
1225 AFI->setLRIsSpilledForFarJump(true);
1229 /// Move iterator pass the next bunch of callee save load / store ops for
1230 /// the particular spill area (1: integer area 1, 2: integer area 2,
1231 /// 3: fp area, 0: don't care).
1232 static void movePastCSLoadStoreOps(MachineBasicBlock &MBB,
1233 MachineBasicBlock::iterator &MBBI,
1234 int Opc, unsigned Area,
1235 const ARMSubtarget &STI) {
1236 while (MBBI != MBB.end() &&
1237 MBBI->getOpcode() == Opc && MBBI->getOperand(1).isFrameIndex()) {
1240 unsigned Category = 0;
1241 switch (MBBI->getOperand(0).getReg()) {
1242 case ARM::R4: case ARM::R5: case ARM::R6: case ARM::R7:
1246 case ARM::R8: case ARM::R9: case ARM::R10: case ARM::R11:
1247 Category = STI.isTargetDarwin() ? 2 : 1;
1249 case ARM::D8: case ARM::D9: case ARM::D10: case ARM::D11:
1250 case ARM::D12: case ARM::D13: case ARM::D14: case ARM::D15:
1257 if (Done || Category != Area)
1265 void ARMRegisterInfo::emitPrologue(MachineFunction &MF) const {
1266 MachineBasicBlock &MBB = MF.front();
1267 MachineBasicBlock::iterator MBBI = MBB.begin();
1268 MachineFrameInfo *MFI = MF.getFrameInfo();
1269 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1270 bool isThumb = AFI->isThumbFunction();
1271 unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
1272 unsigned NumBytes = MFI->getStackSize();
1273 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
1276 // Check if R3 is live in. It might have to be used as a scratch register.
1277 for (MachineFunction::livein_iterator I=MF.livein_begin(),E=MF.livein_end();
1279 if ((*I).first == ARM::R3) {
1280 AFI->setR3IsLiveIn(true);
1285 // Thumb add/sub sp, imm8 instructions implicitly multiply the offset by 4.
1286 NumBytes = (NumBytes + 3) & ~3;
1287 MFI->setStackSize(NumBytes);
1290 // Determine the sizes of each callee-save spill areas and record which frame
1291 // belongs to which callee-save spill areas.
1292 unsigned GPRCS1Size = 0, GPRCS2Size = 0, DPRCSSize = 0;
1293 int FramePtrSpillFI = 0;
1296 emitSPUpdate(MBB, MBBI, -VARegSaveSize, isThumb, TII);
1298 if (!AFI->hasStackFrame()) {
1300 emitSPUpdate(MBB, MBBI, -NumBytes, isThumb, TII);
1304 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1305 unsigned Reg = CSI[i].getReg();
1306 int FI = CSI[i].getFrameIdx();
1313 if (Reg == FramePtr)
1314 FramePtrSpillFI = FI;
1315 AFI->addGPRCalleeSavedArea1Frame(FI);
1322 if (Reg == FramePtr)
1323 FramePtrSpillFI = FI;
1324 if (STI.isTargetDarwin()) {
1325 AFI->addGPRCalleeSavedArea2Frame(FI);
1328 AFI->addGPRCalleeSavedArea1Frame(FI);
1333 AFI->addDPRCalleeSavedAreaFrame(FI);
1339 // Build the new SUBri to adjust SP for integer callee-save spill area 1.
1340 emitSPUpdate(MBB, MBBI, -GPRCS1Size, isThumb, TII);
1341 movePastCSLoadStoreOps(MBB, MBBI, ARM::STR, 1, STI);
1342 } else if (MBBI != MBB.end() && MBBI->getOpcode() == ARM::tPUSH)
1345 // Darwin ABI requires FP to point to the stack slot that contains the
1347 if (STI.isTargetDarwin() || hasFP(MF))
1348 BuildMI(MBB, MBBI, TII.get(isThumb ? ARM::tADDrSPi : ARM::ADDri), FramePtr)
1349 .addFrameIndex(FramePtrSpillFI).addImm(0);
1352 // Build the new SUBri to adjust SP for integer callee-save spill area 2.
1353 emitSPUpdate(MBB, MBBI, -GPRCS2Size, false, TII);
1355 // Build the new SUBri to adjust SP for FP callee-save spill area.
1356 movePastCSLoadStoreOps(MBB, MBBI, ARM::STR, 2, STI);
1357 emitSPUpdate(MBB, MBBI, -DPRCSSize, false, TII);
1360 // Determine starting offsets of spill areas.
1361 unsigned DPRCSOffset = NumBytes - (GPRCS1Size + GPRCS2Size + DPRCSSize);
1362 unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize;
1363 unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size;
1364 AFI->setFramePtrSpillOffset(MFI->getObjectOffset(FramePtrSpillFI) + NumBytes);
1365 AFI->setGPRCalleeSavedArea1Offset(GPRCS1Offset);
1366 AFI->setGPRCalleeSavedArea2Offset(GPRCS2Offset);
1367 AFI->setDPRCalleeSavedAreaOffset(DPRCSOffset);
1369 NumBytes = DPRCSOffset;
1371 // Insert it after all the callee-save spills.
1373 movePastCSLoadStoreOps(MBB, MBBI, ARM::FSTD, 3, STI);
1374 emitSPUpdate(MBB, MBBI, -NumBytes, isThumb, TII);
1377 if(STI.isTargetELF() && hasFP(MF)) {
1378 MFI->setOffsetAdjustment(MFI->getOffsetAdjustment() -
1379 AFI->getFramePtrSpillOffset());
1382 AFI->setGPRCalleeSavedArea1Size(GPRCS1Size);
1383 AFI->setGPRCalleeSavedArea2Size(GPRCS2Size);
1384 AFI->setDPRCalleeSavedAreaSize(DPRCSSize);
1387 static bool isCalleeSavedRegister(unsigned Reg, const unsigned *CSRegs) {
1388 for (unsigned i = 0; CSRegs[i]; ++i)
1389 if (Reg == CSRegs[i])
1394 static bool isCSRestore(MachineInstr *MI, const unsigned *CSRegs) {
1395 return ((MI->getOpcode() == ARM::FLDD ||
1396 MI->getOpcode() == ARM::LDR ||
1397 MI->getOpcode() == ARM::tRestore) &&
1398 MI->getOperand(1).isFrameIndex() &&
1399 isCalleeSavedRegister(MI->getOperand(0).getReg(), CSRegs));
1402 void ARMRegisterInfo::emitEpilogue(MachineFunction &MF,
1403 MachineBasicBlock &MBB) const {
1404 MachineBasicBlock::iterator MBBI = prior(MBB.end());
1405 assert((MBBI->getOpcode() == ARM::BX_RET ||
1406 MBBI->getOpcode() == ARM::tBX_RET ||
1407 MBBI->getOpcode() == ARM::tPOP_RET) &&
1408 "Can only insert epilog into returning blocks");
1410 MachineFrameInfo *MFI = MF.getFrameInfo();
1411 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1412 bool isThumb = AFI->isThumbFunction();
1413 unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
1414 int NumBytes = (int)MFI->getStackSize();
1415 if (!AFI->hasStackFrame()) {
1417 emitSPUpdate(MBB, MBBI, NumBytes, isThumb, TII);
1419 // Unwind MBBI to point to first LDR / FLDD.
1420 const unsigned *CSRegs = getCalleeSavedRegs();
1421 if (MBBI != MBB.begin()) {
1424 while (MBBI != MBB.begin() && isCSRestore(MBBI, CSRegs));
1425 if (!isCSRestore(MBBI, CSRegs))
1429 // Move SP to start of FP callee save spill area.
1430 NumBytes -= (AFI->getGPRCalleeSavedArea1Size() +
1431 AFI->getGPRCalleeSavedArea2Size() +
1432 AFI->getDPRCalleeSavedAreaSize());
1435 NumBytes = AFI->getFramePtrSpillOffset() - NumBytes;
1436 // Reset SP based on frame pointer only if the stack frame extends beyond
1437 // frame pointer stack slot or target is ELF and the function has FP.
1439 emitThumbRegPlusImmediate(MBB, MBBI, ARM::SP, FramePtr, -NumBytes, TII);
1441 BuildMI(MBB, MBBI, TII.get(ARM::tMOVr), ARM::SP).addReg(FramePtr);
1443 if (MBBI->getOpcode() == ARM::tBX_RET &&
1444 &MBB.front() != MBBI &&
1445 prior(MBBI)->getOpcode() == ARM::tPOP) {
1446 MachineBasicBlock::iterator PMBBI = prior(MBBI);
1447 emitSPUpdate(MBB, PMBBI, NumBytes, isThumb, TII);
1449 emitSPUpdate(MBB, MBBI, NumBytes, isThumb, TII);
1452 // Darwin ABI requires FP to point to the stack slot that contains the
1454 if ((STI.isTargetDarwin() && NumBytes) || hasFP(MF)) {
1455 NumBytes = AFI->getFramePtrSpillOffset() - NumBytes;
1456 // Reset SP based on frame pointer only if the stack frame extends beyond
1457 // frame pointer stack slot or target is ELF and the function has FP.
1458 if (AFI->getGPRCalleeSavedArea2Size() ||
1459 AFI->getDPRCalleeSavedAreaSize() ||
1460 AFI->getDPRCalleeSavedAreaOffset()||
1463 BuildMI(MBB, MBBI, TII.get(ARM::SUBri), ARM::SP).addReg(FramePtr)
1466 BuildMI(MBB, MBBI, TII.get(ARM::MOVr), ARM::SP).addReg(FramePtr);
1467 } else if (NumBytes) {
1468 emitSPUpdate(MBB, MBBI, NumBytes, false, TII);
1471 // Move SP to start of integer callee save spill area 2.
1472 movePastCSLoadStoreOps(MBB, MBBI, ARM::FLDD, 3, STI);
1473 emitSPUpdate(MBB, MBBI, AFI->getDPRCalleeSavedAreaSize(), false, TII);
1475 // Move SP to start of integer callee save spill area 1.
1476 movePastCSLoadStoreOps(MBB, MBBI, ARM::LDR, 2, STI);
1477 emitSPUpdate(MBB, MBBI, AFI->getGPRCalleeSavedArea2Size(), false, TII);
1479 // Move SP to SP upon entry to the function.
1480 movePastCSLoadStoreOps(MBB, MBBI, ARM::LDR, 1, STI);
1481 emitSPUpdate(MBB, MBBI, AFI->getGPRCalleeSavedArea1Size(), false, TII);
1485 if (VARegSaveSize) {
1487 // Epilogue for vararg functions: pop LR to R3 and branch off it.
1488 // FIXME: Verify this is still ok when R3 is no longer being reserved.
1489 BuildMI(MBB, MBBI, TII.get(ARM::tPOP)).addReg(ARM::R3);
1491 emitSPUpdate(MBB, MBBI, VARegSaveSize, isThumb, TII);
1494 BuildMI(MBB, MBBI, TII.get(ARM::tBX_RET_vararg)).addReg(ARM::R3);
1500 unsigned ARMRegisterInfo::getRARegister() const {
1504 unsigned ARMRegisterInfo::getFrameRegister(MachineFunction &MF) const {
1505 if (STI.isTargetDarwin() || hasFP(MF))
1506 return (STI.useThumbBacktraces() || STI.isThumb()) ? ARM::R7 : ARM::R11;
1511 unsigned ARMRegisterInfo::getEHExceptionRegister() const {
1512 assert(0 && "What is the exception register");
1516 unsigned ARMRegisterInfo::getEHHandlerRegister() const {
1517 assert(0 && "What is the exception handler register");
1521 #include "ARMGenRegisterInfo.inc"