1 //===-- ARM/ARMMCCodeEmitter.cpp - Convert ARM code to machine code -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the ARMMCCodeEmitter class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "arm-emitter"
16 #include "ARMAddressingModes.h"
17 #include "ARMFixupKinds.h"
18 #include "ARMInstrInfo.h"
19 #include "llvm/MC/MCCodeEmitter.h"
20 #include "llvm/MC/MCExpr.h"
21 #include "llvm/MC/MCInst.h"
22 #include "llvm/ADT/Statistic.h"
23 #include "llvm/Support/raw_ostream.h"
26 STATISTIC(MCNumEmitted, "Number of MC instructions emitted.");
27 STATISTIC(MCNumCPRelocations, "Number of constant pool relocations created.");
30 class ARMMCCodeEmitter : public MCCodeEmitter {
31 ARMMCCodeEmitter(const ARMMCCodeEmitter &); // DO NOT IMPLEMENT
32 void operator=(const ARMMCCodeEmitter &); // DO NOT IMPLEMENT
33 const TargetMachine &TM;
34 const TargetInstrInfo &TII;
38 ARMMCCodeEmitter(TargetMachine &tm, MCContext &ctx)
39 : TM(tm), TII(*TM.getInstrInfo()), Ctx(ctx) {
42 ~ARMMCCodeEmitter() {}
44 unsigned getNumFixupKinds() const { return 2; }
46 const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const {
47 const static MCFixupKindInfo Infos[] = {
48 { "fixup_arm_pcrel_12", 2, 12, MCFixupKindInfo::FKF_IsPCRel },
49 { "fixup_arm_vfp_pcrel_12", 3, 8, MCFixupKindInfo::FKF_IsPCRel },
52 if (Kind < FirstTargetFixupKind)
53 return MCCodeEmitter::getFixupKindInfo(Kind);
55 assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
57 return Infos[Kind - FirstTargetFixupKind];
59 unsigned getMachineSoImmOpValue(unsigned SoImm) const;
61 // getBinaryCodeForInstr - TableGen'erated function for getting the
62 // binary encoding for an instruction.
63 unsigned getBinaryCodeForInstr(const MCInst &MI,
64 SmallVectorImpl<MCFixup> &Fixups) const;
66 /// getMachineOpValue - Return binary encoding of operand. If the machine
67 /// operand requires relocation, record the relocation and return zero.
68 unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO,
69 SmallVectorImpl<MCFixup> &Fixups) const;
71 bool EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx,
72 unsigned &Reg, unsigned &Imm,
73 SmallVectorImpl<MCFixup> &Fixups) const;
75 /// getAddrModeImm12OpValue - Return encoding info for 'reg +/- imm12'
77 uint32_t getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx,
78 SmallVectorImpl<MCFixup> &Fixups) const;
80 /// getLdStSORegOpValue - Return encoding info for 'reg +/- reg shop imm'
81 /// operand as needed by load/store instructions.
82 uint32_t getLdStSORegOpValue(const MCInst &MI, unsigned OpIdx,
83 SmallVectorImpl<MCFixup> &Fixups) const;
85 /// getAddrMode5OpValue - Return encoding info for 'reg +/- imm8' operand.
86 uint32_t getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx,
87 SmallVectorImpl<MCFixup> &Fixups) const;
89 /// getCCOutOpValue - Return encoding of the 's' bit.
90 unsigned getCCOutOpValue(const MCInst &MI, unsigned Op,
91 SmallVectorImpl<MCFixup> &Fixups) const {
92 // The operand is either reg0 or CPSR. The 's' bit is encoded as '0' or
94 return MI.getOperand(Op).getReg() == ARM::CPSR;
97 /// getSOImmOpValue - Return an encoded 12-bit shifted-immediate value.
98 unsigned getSOImmOpValue(const MCInst &MI, unsigned Op,
99 SmallVectorImpl<MCFixup> &Fixups) const {
100 unsigned SoImm = MI.getOperand(Op).getImm();
101 int SoImmVal = ARM_AM::getSOImmVal(SoImm);
102 assert(SoImmVal != -1 && "Not a valid so_imm value!");
104 // Encode rotate_imm.
105 unsigned Binary = (ARM_AM::getSOImmValRot((unsigned)SoImmVal) >> 1)
106 << ARMII::SoRotImmShift;
109 Binary |= ARM_AM::getSOImmValImm((unsigned)SoImmVal);
113 /// getSORegOpValue - Return an encoded so_reg shifted register value.
114 unsigned getSORegOpValue(const MCInst &MI, unsigned Op,
115 SmallVectorImpl<MCFixup> &Fixups) const;
117 unsigned getRotImmOpValue(const MCInst &MI, unsigned Op,
118 SmallVectorImpl<MCFixup> &Fixups) const {
119 switch (MI.getOperand(Op).getImm()) {
120 default: assert (0 && "Not a valid rot_imm value!");
128 unsigned getImmMinusOneOpValue(const MCInst &MI, unsigned Op,
129 SmallVectorImpl<MCFixup> &Fixups) const {
130 return MI.getOperand(Op).getImm() - 1;
133 unsigned getNEONVcvtImm32OpValue(const MCInst &MI, unsigned Op,
134 SmallVectorImpl<MCFixup> &Fixups) const {
135 return 64 - MI.getOperand(Op).getImm();
138 unsigned getBitfieldInvertedMaskOpValue(const MCInst &MI, unsigned Op,
139 SmallVectorImpl<MCFixup> &Fixups) const;
141 unsigned getRegisterListOpValue(const MCInst &MI, unsigned Op,
142 SmallVectorImpl<MCFixup> &Fixups) const;
143 unsigned getAddrMode6AddressOpValue(const MCInst &MI, unsigned Op,
144 SmallVectorImpl<MCFixup> &Fixups) const;
145 unsigned getAddrMode6OffsetOpValue(const MCInst &MI, unsigned Op,
146 SmallVectorImpl<MCFixup> &Fixups) const;
148 void EmitByte(unsigned char C, raw_ostream &OS) const {
152 void EmitConstant(uint64_t Val, unsigned Size, raw_ostream &OS) const {
153 // Output the constant in little endian byte order.
154 for (unsigned i = 0; i != Size; ++i) {
155 EmitByte(Val & 255, OS);
160 void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
161 SmallVectorImpl<MCFixup> &Fixups) const;
164 } // end anonymous namespace
166 MCCodeEmitter *llvm::createARMMCCodeEmitter(const Target &, TargetMachine &TM,
168 return new ARMMCCodeEmitter(TM, Ctx);
171 /// getMachineOpValue - Return binary encoding of operand. If the machine
172 /// operand requires relocation, record the relocation and return zero.
173 unsigned ARMMCCodeEmitter::
174 getMachineOpValue(const MCInst &MI, const MCOperand &MO,
175 SmallVectorImpl<MCFixup> &Fixups) const {
177 unsigned Reg = MO.getReg();
178 unsigned RegNo = getARMRegisterNumbering(Reg);
180 // Q registers are encodes as 2x their register number.
184 case ARM::Q0: case ARM::Q1: case ARM::Q2: case ARM::Q3:
185 case ARM::Q4: case ARM::Q5: case ARM::Q6: case ARM::Q7:
186 case ARM::Q8: case ARM::Q9: case ARM::Q10: case ARM::Q11:
187 case ARM::Q12: case ARM::Q13: case ARM::Q14: case ARM::Q15:
190 } else if (MO.isImm()) {
191 return static_cast<unsigned>(MO.getImm());
192 } else if (MO.isFPImm()) {
193 return static_cast<unsigned>(APFloat(MO.getFPImm())
194 .bitcastToAPInt().getHiBits(32).getLimitedValue());
204 /// getAddrModeImmOpValue - Return encoding info for 'reg +/- imm' operand.
205 bool ARMMCCodeEmitter::
206 EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx, unsigned &Reg,
207 unsigned &Imm, SmallVectorImpl<MCFixup> &Fixups) const {
208 const MCOperand &MO = MI.getOperand(OpIdx);
209 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
211 Reg = getARMRegisterNumbering(MO.getReg());
213 int32_t SImm = MO1.getImm();
216 // Special value for #-0
217 if (SImm == INT32_MIN)
220 // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
230 /// getAddrModeImm12OpValue - Return encoding info for 'reg +/- imm12' operand.
231 uint32_t ARMMCCodeEmitter::
232 getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx,
233 SmallVectorImpl<MCFixup> &Fixups) const {
235 // {12} = (U)nsigned (add == '1', sub == '0')
239 // If The first operand isn't a register, we have a label reference.
240 const MCOperand &MO = MI.getOperand(OpIdx);
242 Reg = getARMRegisterNumbering(ARM::PC); // Rn is PC.
245 assert(MO.isExpr() && "Unexpected machine operand type!");
246 const MCExpr *Expr = MO.getExpr();
247 MCFixupKind Kind = MCFixupKind(ARM::fixup_arm_pcrel_12);
248 Fixups.push_back(MCFixup::Create(0, Expr, Kind));
250 ++MCNumCPRelocations;
252 isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm12, Fixups);
254 uint32_t Binary = Imm12 & 0xfff;
255 // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
258 Binary |= (Reg << 13);
262 uint32_t ARMMCCodeEmitter::
263 getLdStSORegOpValue(const MCInst &MI, unsigned OpIdx,
264 SmallVectorImpl<MCFixup> &Fixups) const {
265 const MCOperand &MO = MI.getOperand(OpIdx);
266 const MCOperand &MO1 = MI.getOperand(OpIdx+1);
267 const MCOperand &MO2 = MI.getOperand(OpIdx+2);
268 unsigned Rn = getARMRegisterNumbering(MO.getReg());
269 unsigned Rm = getARMRegisterNumbering(MO1.getReg());
270 ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(MO2.getImm());
271 unsigned ShImm = ARM_AM::getAM2Offset(MO2.getImm());
272 bool isAdd = ARM_AM::getAM2Op(MO2.getImm()) == ARM_AM::add;
279 default: llvm_unreachable("Unknown shift opc!");
280 case ARM_AM::no_shift:
281 assert(ShImm == 0 && "Non-zero shift amount with no shift type!");
283 case ARM_AM::lsl: SBits = 0x0; break;
284 case ARM_AM::lsr: SBits = 0x1; break;
285 case ARM_AM::asr: SBits = 0x2; break;
286 case ARM_AM::ror: SBits = 0x3; break;
298 Binary |= SBits << 5;
299 Binary |= ShImm << 7;
305 /// getAddrMode5OpValue - Return encoding info for 'reg +/- imm12' operand.
306 uint32_t ARMMCCodeEmitter::
307 getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx,
308 SmallVectorImpl<MCFixup> &Fixups) const {
310 // {8} = (U)nsigned (add == '1', sub == '0')
313 // If The first operand isn't a register, we have a label reference.
314 const MCOperand &MO = MI.getOperand(OpIdx);
316 Reg = getARMRegisterNumbering(ARM::PC); // Rn is PC.
319 assert(MO.isExpr() && "Unexpected machine operand type!");
320 const MCExpr *Expr = MO.getExpr();
321 MCFixupKind Kind = MCFixupKind(ARM::fixup_arm_vfp_pcrel_12);
322 Fixups.push_back(MCFixup::Create(0, Expr, Kind));
324 ++MCNumCPRelocations;
326 EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm8, Fixups);
328 uint32_t Binary = ARM_AM::getAM5Offset(Imm8);
329 // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
330 if (ARM_AM::getAM5Op(Imm8) == ARM_AM::add)
332 Binary |= (Reg << 9);
336 unsigned ARMMCCodeEmitter::
337 getSORegOpValue(const MCInst &MI, unsigned OpIdx,
338 SmallVectorImpl<MCFixup> &Fixups) const {
339 // Sub-operands are [reg, reg, imm]. The first register is Rm, the reg to be
340 // shifted. The second is either Rs, the amount to shift by, or reg0 in which
341 // case the imm contains the amount to shift by.
344 // {4} = 1 if reg shift, 0 if imm shift
352 const MCOperand &MO = MI.getOperand(OpIdx);
353 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
354 const MCOperand &MO2 = MI.getOperand(OpIdx + 2);
355 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm());
358 unsigned Binary = getARMRegisterNumbering(MO.getReg());
360 // Encode the shift opcode.
362 unsigned Rs = MO1.getReg();
364 // Set shift operand (bit[7:4]).
369 // RRX - 0110 and bit[11:8] clear.
371 default: llvm_unreachable("Unknown shift opc!");
372 case ARM_AM::lsl: SBits = 0x1; break;
373 case ARM_AM::lsr: SBits = 0x3; break;
374 case ARM_AM::asr: SBits = 0x5; break;
375 case ARM_AM::ror: SBits = 0x7; break;
376 case ARM_AM::rrx: SBits = 0x6; break;
379 // Set shift operand (bit[6:4]).
385 default: llvm_unreachable("Unknown shift opc!");
386 case ARM_AM::lsl: SBits = 0x0; break;
387 case ARM_AM::lsr: SBits = 0x2; break;
388 case ARM_AM::asr: SBits = 0x4; break;
389 case ARM_AM::ror: SBits = 0x6; break;
393 Binary |= SBits << 4;
394 if (SOpc == ARM_AM::rrx)
397 // Encode the shift operation Rs or shift_imm (except rrx).
399 // Encode Rs bit[11:8].
400 assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0);
401 return Binary | (getARMRegisterNumbering(Rs) << ARMII::RegRsShift);
404 // Encode shift_imm bit[11:7].
405 return Binary | ARM_AM::getSORegOffset(MO2.getImm()) << 7;
408 unsigned ARMMCCodeEmitter::
409 getBitfieldInvertedMaskOpValue(const MCInst &MI, unsigned Op,
410 SmallVectorImpl<MCFixup> &Fixups) const {
411 // 10 bits. lower 5 bits are are the lsb of the mask, high five bits are the
413 const MCOperand &MO = MI.getOperand(Op);
414 uint32_t v = ~MO.getImm();
415 uint32_t lsb = CountTrailingZeros_32(v);
416 uint32_t msb = (32 - CountLeadingZeros_32 (v)) - 1;
417 assert (v != 0 && lsb < 32 && msb < 32 && "Illegal bitfield mask!");
418 return lsb | (msb << 5);
421 unsigned ARMMCCodeEmitter::
422 getRegisterListOpValue(const MCInst &MI, unsigned Op,
423 SmallVectorImpl<MCFixup> &Fixups) const {
424 // Convert a list of GPRs into a bitfield (R0 -> bit 0). For each
425 // register in the list, set the corresponding bit.
427 for (unsigned i = Op, e = MI.getNumOperands(); i < e; ++i) {
428 unsigned regno = getARMRegisterNumbering(MI.getOperand(i).getReg());
429 Binary |= 1 << regno;
434 unsigned ARMMCCodeEmitter::
435 getAddrMode6AddressOpValue(const MCInst &MI, unsigned Op,
436 SmallVectorImpl<MCFixup> &Fixups) const {
437 const MCOperand &Reg = MI.getOperand(Op);
438 const MCOperand &Imm = MI.getOperand(Op + 1);
440 unsigned RegNo = getARMRegisterNumbering(Reg.getReg());
443 switch (Imm.getImm()) {
447 case 8: Align = 0x01; break;
448 case 16: Align = 0x02; break;
449 case 32: Align = 0x03; break;
452 return RegNo | (Align << 4);
455 unsigned ARMMCCodeEmitter::
456 getAddrMode6OffsetOpValue(const MCInst &MI, unsigned Op,
457 SmallVectorImpl<MCFixup> &Fixups) const {
458 const MCOperand &MO = MI.getOperand(Op);
459 if (MO.getReg() == 0) return 0x0D;
463 void ARMMCCodeEmitter::
464 EncodeInstruction(const MCInst &MI, raw_ostream &OS,
465 SmallVectorImpl<MCFixup> &Fixups) const {
466 // Pseudo instructions don't get encoded.
467 const TargetInstrDesc &Desc = TII.get(MI.getOpcode());
468 if ((Desc.TSFlags & ARMII::FormMask) == ARMII::Pseudo)
471 EmitConstant(getBinaryCodeForInstr(MI, Fixups), 4, OS);
472 ++MCNumEmitted; // Keep track of the # of mi's emitted.
475 #include "ARMGenMCCodeEmitter.inc"