1 //===-- ARM/ARMMCCodeEmitter.cpp - Convert ARM code to machine code -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the ARMMCCodeEmitter class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "arm-emitter"
16 #include "ARMAddressingModes.h"
17 #include "ARMInstrInfo.h"
18 #include "llvm/MC/MCCodeEmitter.h"
19 #include "llvm/MC/MCExpr.h"
20 #include "llvm/MC/MCInst.h"
21 #include "llvm/ADT/Statistic.h"
22 #include "llvm/Support/raw_ostream.h"
25 STATISTIC(MCNumEmitted, "Number of MC instructions emitted");
28 class ARMMCCodeEmitter : public MCCodeEmitter {
29 ARMMCCodeEmitter(const ARMMCCodeEmitter &); // DO NOT IMPLEMENT
30 void operator=(const ARMMCCodeEmitter &); // DO NOT IMPLEMENT
31 const TargetMachine &TM;
32 const TargetInstrInfo &TII;
36 ARMMCCodeEmitter(TargetMachine &tm, MCContext &ctx)
37 : TM(tm), TII(*TM.getInstrInfo()), Ctx(ctx) {
40 ~ARMMCCodeEmitter() {}
42 unsigned getMachineSoImmOpValue(unsigned SoImm) const;
44 // getBinaryCodeForInstr - TableGen'erated function for getting the
45 // binary encoding for an instruction.
46 unsigned getBinaryCodeForInstr(const MCInst &MI) const;
48 /// getMachineOpValue - Return binary encoding of operand. If the machine
49 /// operand requires relocation, record the relocation and return zero.
50 unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO) const;
52 /// getAddrModeImm12OpValue - Return encoding info for 'reg +/- imm12'
54 unsigned getAddrModeImm12OpValue(const MCInst &MI, unsigned Op) const;
56 /// getCCOutOpValue - Return encoding of the 's' bit.
57 unsigned getCCOutOpValue(const MCInst &MI, unsigned Op) const {
58 // The operand is either reg0 or CPSR. The 's' bit is encoded as '0' or
60 return MI.getOperand(Op).getReg() == ARM::CPSR;
63 /// getSOImmOpValue - Return an encoded 12-bit shifted-immediate value.
64 unsigned getSOImmOpValue(const MCInst &MI, unsigned Op) const {
65 unsigned SoImm = MI.getOperand(Op).getImm();
66 int SoImmVal = ARM_AM::getSOImmVal(SoImm);
67 assert(SoImmVal != -1 && "Not a valid so_imm value!");
70 unsigned Binary = (ARM_AM::getSOImmValRot((unsigned)SoImmVal) >> 1)
71 << ARMII::SoRotImmShift;
74 Binary |= ARM_AM::getSOImmValImm((unsigned)SoImmVal);
78 /// getSORegOpValue - Return an encoded so_reg shifted register value.
79 unsigned getSORegOpValue(const MCInst &MI, unsigned Op) const;
81 unsigned getRotImmOpValue(const MCInst &MI, unsigned Op) const {
82 switch (MI.getOperand(Op).getImm()) {
83 default: assert (0 && "Not a valid rot_imm value!");
91 unsigned getImmMinusOneOpValue(const MCInst &MI, unsigned Op) const {
92 return MI.getOperand(Op).getImm() - 1;
95 unsigned getNEONVcvtImm32OpValue(const MCInst &MI, unsigned Op) const {
96 return 64 - MI.getOperand(Op).getImm();
99 unsigned getBitfieldInvertedMaskOpValue(const MCInst &MI, unsigned Op) const;
101 unsigned getRegisterListOpValue(const MCInst &MI, unsigned Op) const;
104 unsigned getNumFixupKinds() const {
105 assert(0 && "ARMMCCodeEmitter::getNumFixupKinds() not yet implemented.");
109 const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const {
110 static MCFixupKindInfo rtn;
111 assert(0 && "ARMMCCodeEmitter::getFixupKindInfo() not yet implemented.");
115 void EmitByte(unsigned char C, unsigned &CurByte, raw_ostream &OS) const {
120 void EmitConstant(uint64_t Val, unsigned Size, unsigned &CurByte,
121 raw_ostream &OS) const {
122 // Output the constant in little endian byte order.
123 for (unsigned i = 0; i != Size; ++i) {
124 EmitByte(Val & 255, CurByte, OS);
129 void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
130 SmallVectorImpl<MCFixup> &Fixups) const;
133 } // end anonymous namespace
135 MCCodeEmitter *llvm::createARMMCCodeEmitter(const Target &,
138 return new ARMMCCodeEmitter(TM, Ctx);
141 /// getMachineOpValue - Return binary encoding of operand. If the machine
142 /// operand requires relocation, record the relocation and return zero.
143 unsigned ARMMCCodeEmitter::getMachineOpValue(const MCInst &MI,
144 const MCOperand &MO) const {
146 unsigned regno = getARMRegisterNumbering(MO.getReg());
148 // Q registers are encodes as 2x their register number.
149 switch (MO.getReg()) {
150 case ARM::Q0: case ARM::Q1: case ARM::Q2: case ARM::Q3:
151 case ARM::Q4: case ARM::Q5: case ARM::Q6: case ARM::Q7:
152 case ARM::Q8: case ARM::Q9: case ARM::Q10: case ARM::Q11:
153 case ARM::Q12: case ARM::Q13: case ARM::Q14: case ARM::Q15:
158 } else if (MO.isImm()) {
159 return static_cast<unsigned>(MO.getImm());
160 } else if (MO.isFPImm()) {
161 return static_cast<unsigned>(APFloat(MO.getFPImm())
162 .bitcastToAPInt().getHiBits(32).getLimitedValue());
172 /// getAddrModeImm12OpValue - Return encoding info for 'reg +/- imm12'
174 unsigned ARMMCCodeEmitter::getAddrModeImm12OpValue(const MCInst &MI,
175 unsigned OpIdx) const {
177 // {12} = (U)nsigned (add == '1', sub == '0')
179 const MCOperand &MO = MI.getOperand(OpIdx);
180 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
181 unsigned Reg = getARMRegisterNumbering(MO.getReg());
182 int32_t Imm12 = MO1.getImm();
183 bool isAdd = Imm12 >= 0;
184 // Special value for #-0
185 if (Imm12 == INT32_MIN)
187 // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
190 uint32_t Binary = Imm12 & 0xfff;
193 Binary |= (Reg << 13);
197 unsigned ARMMCCodeEmitter::getSORegOpValue(const MCInst &MI,
198 unsigned OpIdx) const {
199 // Sub-operands are [reg, reg, imm]. The first register is Rm, the reg
200 // to be shifted. The second is either Rs, the amount to shift by, or
201 // reg0 in which case the imm contains the amount to shift by.
203 // {4} = 1 if reg shift, 0 if imm shift
211 const MCOperand &MO = MI.getOperand(OpIdx);
212 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
213 const MCOperand &MO2 = MI.getOperand(OpIdx + 2);
214 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm());
217 unsigned Binary = getARMRegisterNumbering(MO.getReg());
219 // Encode the shift opcode.
221 unsigned Rs = MO1.getReg();
223 // Set shift operand (bit[7:4]).
228 // RRX - 0110 and bit[11:8] clear.
230 default: llvm_unreachable("Unknown shift opc!");
231 case ARM_AM::lsl: SBits = 0x1; break;
232 case ARM_AM::lsr: SBits = 0x3; break;
233 case ARM_AM::asr: SBits = 0x5; break;
234 case ARM_AM::ror: SBits = 0x7; break;
235 case ARM_AM::rrx: SBits = 0x6; break;
238 // Set shift operand (bit[6:4]).
244 default: llvm_unreachable("Unknown shift opc!");
245 case ARM_AM::lsl: SBits = 0x0; break;
246 case ARM_AM::lsr: SBits = 0x2; break;
247 case ARM_AM::asr: SBits = 0x4; break;
248 case ARM_AM::ror: SBits = 0x6; break;
251 Binary |= SBits << 4;
252 if (SOpc == ARM_AM::rrx)
255 // Encode the shift operation Rs or shift_imm (except rrx).
257 // Encode Rs bit[11:8].
258 assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0);
259 return Binary | (getARMRegisterNumbering(Rs) << ARMII::RegRsShift);
262 // Encode shift_imm bit[11:7].
263 return Binary | ARM_AM::getSORegOffset(MO2.getImm()) << 7;
266 unsigned ARMMCCodeEmitter::getBitfieldInvertedMaskOpValue(const MCInst &MI,
268 // 10 bits. lower 5 bits are are the lsb of the mask, high five bits are the
270 const MCOperand &MO = MI.getOperand(Op);
271 uint32_t v = ~MO.getImm();
272 uint32_t lsb = CountTrailingZeros_32(v);
273 uint32_t msb = (32 - CountLeadingZeros_32 (v)) - 1;
274 assert (v != 0 && lsb < 32 && msb < 32 && "Illegal bitfield mask!");
275 return lsb | (msb << 5);
278 unsigned ARMMCCodeEmitter::getRegisterListOpValue(const MCInst &MI,
280 // Convert a list of GPRs into a bitfield (R0 -> bit 0). For each
281 // register in the list, set the corresponding bit.
283 for (unsigned i = Op, e = MI.getNumOperands(); i < e; ++i) {
284 unsigned regno = getARMRegisterNumbering(MI.getOperand(i).getReg());
285 Binary |= 1 << regno;
290 void ARMMCCodeEmitter::
291 EncodeInstruction(const MCInst &MI, raw_ostream &OS,
292 SmallVectorImpl<MCFixup> &Fixups) const {
293 unsigned Opcode = MI.getOpcode();
294 const TargetInstrDesc &Desc = TII.get(Opcode);
295 uint64_t TSFlags = Desc.TSFlags;
296 // Keep track of the current byte being emitted.
297 unsigned CurByte = 0;
299 // Pseudo instructions don't get encoded.
300 if ((TSFlags & ARMII::FormMask) == ARMII::Pseudo)
303 ++MCNumEmitted; // Keep track of the # of mi's emitted
304 unsigned Value = getBinaryCodeForInstr(MI);
308 EmitConstant(Value, 4, CurByte, OS);
311 // FIXME: These #defines shouldn't be necessary. Instead, tblgen should
312 // be able to generate code emitter helpers for either variant, like it
313 // does for the AsmWriter.
314 #define ARMCodeEmitter ARMMCCodeEmitter
315 #define MachineInstr MCInst
316 #include "ARMGenCodeEmitter.inc"
317 #undef ARMCodeEmitter