1 //===-- ARM/ARMMCCodeEmitter.cpp - Convert ARM code to machine code -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the ARMMCCodeEmitter class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "mccodeemitter"
16 #include "ARMAddressingModes.h"
17 #include "ARMFixupKinds.h"
18 #include "ARMInstrInfo.h"
19 #include "llvm/MC/MCCodeEmitter.h"
20 #include "llvm/MC/MCExpr.h"
21 #include "llvm/MC/MCInst.h"
22 #include "llvm/ADT/Statistic.h"
23 #include "llvm/Support/raw_ostream.h"
26 STATISTIC(MCNumEmitted, "Number of MC instructions emitted.");
27 STATISTIC(MCNumCPRelocations, "Number of constant pool relocations created.");
30 class ARMMCCodeEmitter : public MCCodeEmitter {
31 ARMMCCodeEmitter(const ARMMCCodeEmitter &); // DO NOT IMPLEMENT
32 void operator=(const ARMMCCodeEmitter &); // DO NOT IMPLEMENT
33 const TargetMachine &TM;
34 const TargetInstrInfo &TII;
38 ARMMCCodeEmitter(TargetMachine &tm, MCContext &ctx)
39 : TM(tm), TII(*TM.getInstrInfo()), Ctx(ctx) {
42 ~ARMMCCodeEmitter() {}
44 unsigned getNumFixupKinds() const { return ARM::NumTargetFixupKinds; }
46 const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const {
47 const static MCFixupKindInfo Infos[] = {
48 // name offset bits flags
49 { "fixup_arm_pcrel_12", 2, 12, MCFixupKindInfo::FKF_IsPCRel },
50 { "fixup_arm_vfp_pcrel_12", 3, 8, MCFixupKindInfo::FKF_IsPCRel },
51 { "fixup_arm_branch", 1, 24, MCFixupKindInfo::FKF_IsPCRel },
54 if (Kind < FirstTargetFixupKind)
55 return MCCodeEmitter::getFixupKindInfo(Kind);
57 assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
59 return Infos[Kind - FirstTargetFixupKind];
61 unsigned getMachineSoImmOpValue(unsigned SoImm) const;
63 // getBinaryCodeForInstr - TableGen'erated function for getting the
64 // binary encoding for an instruction.
65 unsigned getBinaryCodeForInstr(const MCInst &MI,
66 SmallVectorImpl<MCFixup> &Fixups) const;
68 /// getMachineOpValue - Return binary encoding of operand. If the machine
69 /// operand requires relocation, record the relocation and return zero.
70 unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO,
71 SmallVectorImpl<MCFixup> &Fixups) const;
73 /// getMovtImmOpValue - Return the encoding for the movw/movt pair
74 uint32_t getMovtImmOpValue(const MCInst &MI, unsigned OpIdx,
75 SmallVectorImpl<MCFixup> &Fixups) const;
77 bool EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx,
78 unsigned &Reg, unsigned &Imm,
79 SmallVectorImpl<MCFixup> &Fixups) const;
81 /// getBranchTargetOpValue - Return encoding info for 24-bit immediate
83 uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
84 SmallVectorImpl<MCFixup> &Fixups) const;
86 /// getAddrModeImm12OpValue - Return encoding info for 'reg +/- imm12'
88 uint32_t getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx,
89 SmallVectorImpl<MCFixup> &Fixups) const;
91 /// getLdStSORegOpValue - Return encoding info for 'reg +/- reg shop imm'
92 /// operand as needed by load/store instructions.
93 uint32_t getLdStSORegOpValue(const MCInst &MI, unsigned OpIdx,
94 SmallVectorImpl<MCFixup> &Fixups) const;
96 /// getLdStmModeOpValue - Return encoding for load/store multiple mode.
97 uint32_t getLdStmModeOpValue(const MCInst &MI, unsigned OpIdx,
98 SmallVectorImpl<MCFixup> &Fixups) const {
99 ARM_AM::AMSubMode Mode = (ARM_AM::AMSubMode)MI.getOperand(OpIdx).getImm();
101 default: assert(0 && "Unknown addressing sub-mode!");
102 case ARM_AM::da: return 0;
103 case ARM_AM::ia: return 1;
104 case ARM_AM::db: return 2;
105 case ARM_AM::ib: return 3;
108 /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
110 unsigned getShiftOp(ARM_AM::ShiftOpc ShOpc) const {
112 default: llvm_unreachable("Unknown shift opc!");
113 case ARM_AM::no_shift:
114 case ARM_AM::lsl: return 0;
115 case ARM_AM::lsr: return 1;
116 case ARM_AM::asr: return 2;
118 case ARM_AM::rrx: return 3;
123 /// getAddrMode2OpValue - Return encoding for addrmode2 operands.
124 uint32_t getAddrMode2OpValue(const MCInst &MI, unsigned OpIdx,
125 SmallVectorImpl<MCFixup> &Fixups) const;
127 /// getAddrMode2OffsetOpValue - Return encoding for am2offset operands.
128 uint32_t getAddrMode2OffsetOpValue(const MCInst &MI, unsigned OpIdx,
129 SmallVectorImpl<MCFixup> &Fixups) const;
131 /// getAddrMode3OffsetOpValue - Return encoding for am3offset operands.
132 uint32_t getAddrMode3OffsetOpValue(const MCInst &MI, unsigned OpIdx,
133 SmallVectorImpl<MCFixup> &Fixups) const;
135 /// getAddrMode3OpValue - Return encoding for addrmode3 operands.
136 uint32_t getAddrMode3OpValue(const MCInst &MI, unsigned OpIdx,
137 SmallVectorImpl<MCFixup> &Fixups) const;
139 /// getAddrMode5OpValue - Return encoding info for 'reg +/- imm8' operand.
140 uint32_t getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx,
141 SmallVectorImpl<MCFixup> &Fixups) const;
143 /// getCCOutOpValue - Return encoding of the 's' bit.
144 unsigned getCCOutOpValue(const MCInst &MI, unsigned Op,
145 SmallVectorImpl<MCFixup> &Fixups) const {
146 // The operand is either reg0 or CPSR. The 's' bit is encoded as '0' or
148 return MI.getOperand(Op).getReg() == ARM::CPSR;
151 /// getSOImmOpValue - Return an encoded 12-bit shifted-immediate value.
152 unsigned getSOImmOpValue(const MCInst &MI, unsigned Op,
153 SmallVectorImpl<MCFixup> &Fixups) const {
154 unsigned SoImm = MI.getOperand(Op).getImm();
155 int SoImmVal = ARM_AM::getSOImmVal(SoImm);
156 assert(SoImmVal != -1 && "Not a valid so_imm value!");
158 // Encode rotate_imm.
159 unsigned Binary = (ARM_AM::getSOImmValRot((unsigned)SoImmVal) >> 1)
160 << ARMII::SoRotImmShift;
163 Binary |= ARM_AM::getSOImmValImm((unsigned)SoImmVal);
167 /// getT2SOImmOpValue - Return an encoded 12-bit shifted-immediate value.
168 unsigned getT2SOImmOpValue(const MCInst &MI, unsigned Op,
169 SmallVectorImpl<MCFixup> &Fixups) const {
170 unsigned SoImm = MI.getOperand(Op).getImm();
171 unsigned Encoded = ARM_AM::getT2SOImmVal(SoImm);
172 assert(Encoded != ~0U && "Not a Thumb2 so_imm value?");
176 unsigned getT2AddrModeSORegOpValue(const MCInst &MI, unsigned OpNum,
177 SmallVectorImpl<MCFixup> &Fixups) const;
178 unsigned getT2AddrModeImm8OpValue(const MCInst &MI, unsigned OpNum,
179 SmallVectorImpl<MCFixup> &Fixups) const;
180 unsigned getT2AddrModeImm8OffsetOpValue(const MCInst &MI, unsigned OpNum,
181 SmallVectorImpl<MCFixup> &Fixups) const;
182 unsigned getT2AddrModeImm12OpValue(const MCInst &MI, unsigned OpNum,
183 SmallVectorImpl<MCFixup> &Fixups) const;
185 /// getSORegOpValue - Return an encoded so_reg shifted register value.
186 unsigned getSORegOpValue(const MCInst &MI, unsigned Op,
187 SmallVectorImpl<MCFixup> &Fixups) const;
188 unsigned getT2SORegOpValue(const MCInst &MI, unsigned Op,
189 SmallVectorImpl<MCFixup> &Fixups) const;
191 unsigned getRotImmOpValue(const MCInst &MI, unsigned Op,
192 SmallVectorImpl<MCFixup> &Fixups) const {
193 switch (MI.getOperand(Op).getImm()) {
194 default: assert (0 && "Not a valid rot_imm value!");
202 unsigned getImmMinusOneOpValue(const MCInst &MI, unsigned Op,
203 SmallVectorImpl<MCFixup> &Fixups) const {
204 return MI.getOperand(Op).getImm() - 1;
207 unsigned getNEONVcvtImm32OpValue(const MCInst &MI, unsigned Op,
208 SmallVectorImpl<MCFixup> &Fixups) const {
209 return 64 - MI.getOperand(Op).getImm();
212 unsigned getBitfieldInvertedMaskOpValue(const MCInst &MI, unsigned Op,
213 SmallVectorImpl<MCFixup> &Fixups) const;
215 unsigned getRegisterListOpValue(const MCInst &MI, unsigned Op,
216 SmallVectorImpl<MCFixup> &Fixups) const;
217 unsigned getAddrMode6AddressOpValue(const MCInst &MI, unsigned Op,
218 SmallVectorImpl<MCFixup> &Fixups) const;
219 unsigned getAddrMode6DupAddressOpValue(const MCInst &MI, unsigned Op,
220 SmallVectorImpl<MCFixup> &Fixups) const;
221 unsigned getAddrMode6OffsetOpValue(const MCInst &MI, unsigned Op,
222 SmallVectorImpl<MCFixup> &Fixups) const;
224 unsigned NEONThumb2DataIPostEncoder(const MCInst &MI,
225 unsigned EncodedValue) const;
226 unsigned NEONThumb2LoadStorePostEncoder(const MCInst &MI,
227 unsigned EncodedValue) const;
228 unsigned NEONThumb2DupPostEncoder(const MCInst &MI,
229 unsigned EncodedValue) const;
231 void EmitByte(unsigned char C, raw_ostream &OS) const {
235 void EmitConstant(uint64_t Val, unsigned Size, raw_ostream &OS) const {
236 // Output the constant in little endian byte order.
237 for (unsigned i = 0; i != Size; ++i) {
238 EmitByte(Val & 255, OS);
243 void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
244 SmallVectorImpl<MCFixup> &Fixups) const;
247 } // end anonymous namespace
249 MCCodeEmitter *llvm::createARMMCCodeEmitter(const Target &, TargetMachine &TM,
251 return new ARMMCCodeEmitter(TM, Ctx);
254 /// NEONThumb2DataIPostEncoder - Post-process encoded NEON data-processing
255 /// instructions, and rewrite them to their Thumb2 form if we are currently in
257 unsigned ARMMCCodeEmitter::NEONThumb2DataIPostEncoder(const MCInst &MI,
258 unsigned EncodedValue) const {
259 const ARMSubtarget &Subtarget = TM.getSubtarget<ARMSubtarget>();
260 if (Subtarget.isThumb2()) {
261 // NEON Thumb2 data-processsing encodings are very simple: bit 24 is moved
262 // to bit 12 of the high half-word (i.e. bit 28), and bits 27-24 are
264 unsigned Bit24 = EncodedValue & 0x01000000;
265 unsigned Bit28 = Bit24 << 4;
266 EncodedValue &= 0xEFFFFFFF;
267 EncodedValue |= Bit28;
268 EncodedValue |= 0x0F000000;
274 /// NEONThumb2LoadStorePostEncoder - Post-process encoded NEON load/store
275 /// instructions, and rewrite them to their Thumb2 form if we are currently in
277 unsigned ARMMCCodeEmitter::NEONThumb2LoadStorePostEncoder(const MCInst &MI,
278 unsigned EncodedValue) const {
279 const ARMSubtarget &Subtarget = TM.getSubtarget<ARMSubtarget>();
280 if (Subtarget.isThumb2()) {
281 EncodedValue &= 0xF0FFFFFF;
282 EncodedValue |= 0x09000000;
288 /// NEONThumb2DupPostEncoder - Post-process encoded NEON vdup
289 /// instructions, and rewrite them to their Thumb2 form if we are currently in
291 unsigned ARMMCCodeEmitter::NEONThumb2DupPostEncoder(const MCInst &MI,
292 unsigned EncodedValue) const {
293 const ARMSubtarget &Subtarget = TM.getSubtarget<ARMSubtarget>();
294 if (Subtarget.isThumb2()) {
295 EncodedValue &= 0x00FFFFFF;
296 EncodedValue |= 0xEE000000;
304 /// getMachineOpValue - Return binary encoding of operand. If the machine
305 /// operand requires relocation, record the relocation and return zero.
306 unsigned ARMMCCodeEmitter::
307 getMachineOpValue(const MCInst &MI, const MCOperand &MO,
308 SmallVectorImpl<MCFixup> &Fixups) const {
310 unsigned Reg = MO.getReg();
311 unsigned RegNo = getARMRegisterNumbering(Reg);
313 // Q registers are encodes as 2x their register number.
317 case ARM::Q0: case ARM::Q1: case ARM::Q2: case ARM::Q3:
318 case ARM::Q4: case ARM::Q5: case ARM::Q6: case ARM::Q7:
319 case ARM::Q8: case ARM::Q9: case ARM::Q10: case ARM::Q11:
320 case ARM::Q12: case ARM::Q13: case ARM::Q14: case ARM::Q15:
323 } else if (MO.isImm()) {
324 return static_cast<unsigned>(MO.getImm());
325 } else if (MO.isFPImm()) {
326 return static_cast<unsigned>(APFloat(MO.getFPImm())
327 .bitcastToAPInt().getHiBits(32).getLimitedValue());
330 llvm_unreachable("Unable to encode MCOperand!");
334 /// getAddrModeImmOpValue - Return encoding info for 'reg +/- imm' operand.
335 bool ARMMCCodeEmitter::
336 EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx, unsigned &Reg,
337 unsigned &Imm, SmallVectorImpl<MCFixup> &Fixups) const {
338 const MCOperand &MO = MI.getOperand(OpIdx);
339 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
341 Reg = getARMRegisterNumbering(MO.getReg());
343 int32_t SImm = MO1.getImm();
346 // Special value for #-0
347 if (SImm == INT32_MIN)
350 // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
360 /// getBranchTargetOpValue - Return encoding info for 24-bit immediate
362 uint32_t ARMMCCodeEmitter::
363 getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
364 SmallVectorImpl<MCFixup> &Fixups) const {
365 const MCOperand &MO = MI.getOperand(OpIdx);
367 // If the destination is an immediate, we have nothing to do.
368 if (MO.isImm()) return MO.getImm();
369 assert (MO.isExpr() && "Unexpected branch target type!");
370 const MCExpr *Expr = MO.getExpr();
371 MCFixupKind Kind = MCFixupKind(ARM::fixup_arm_branch);
372 Fixups.push_back(MCFixup::Create(0, Expr, Kind));
374 // All of the information is in the fixup.
378 /// getAddrModeImm12OpValue - Return encoding info for 'reg +/- imm12' operand.
379 uint32_t ARMMCCodeEmitter::
380 getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx,
381 SmallVectorImpl<MCFixup> &Fixups) const {
383 // {12} = (U)nsigned (add == '1', sub == '0')
387 // If The first operand isn't a register, we have a label reference.
388 const MCOperand &MO = MI.getOperand(OpIdx);
390 Reg = getARMRegisterNumbering(ARM::PC); // Rn is PC.
393 assert(MO.isExpr() && "Unexpected machine operand type!");
394 const MCExpr *Expr = MO.getExpr();
395 MCFixupKind Kind = MCFixupKind(ARM::fixup_arm_pcrel_12);
396 Fixups.push_back(MCFixup::Create(0, Expr, Kind));
398 ++MCNumCPRelocations;
400 isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm12, Fixups);
402 uint32_t Binary = Imm12 & 0xfff;
403 // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
406 Binary |= (Reg << 13);
410 uint32_t ARMMCCodeEmitter::
411 getMovtImmOpValue(const MCInst &MI, unsigned OpIdx,
412 SmallVectorImpl<MCFixup> &Fixups) const {
413 // {20-16} = imm{15-12}
414 // {11-0} = imm{11-0}
415 const MCOperand &MO = MI.getOperand(OpIdx);
417 return static_cast<unsigned>(MO.getImm());
418 } else if (const MCSymbolRefExpr *Expr =
419 dyn_cast<MCSymbolRefExpr>(MO.getExpr())) {
421 switch (Expr->getKind()) {
422 default: assert(0 && "Unsupported ARMFixup");
423 case MCSymbolRefExpr::VK_ARM_HI16:
424 Kind = MCFixupKind(ARM::fixup_arm_movt_hi16);
426 case MCSymbolRefExpr::VK_ARM_LO16:
427 Kind = MCFixupKind(ARM::fixup_arm_movw_lo16);
430 Fixups.push_back(MCFixup::Create(0, Expr, Kind));
433 llvm_unreachable("Unsupported MCExpr type in MCOperand!");
437 uint32_t ARMMCCodeEmitter::
438 getLdStSORegOpValue(const MCInst &MI, unsigned OpIdx,
439 SmallVectorImpl<MCFixup> &Fixups) const {
440 const MCOperand &MO = MI.getOperand(OpIdx);
441 const MCOperand &MO1 = MI.getOperand(OpIdx+1);
442 const MCOperand &MO2 = MI.getOperand(OpIdx+2);
443 unsigned Rn = getARMRegisterNumbering(MO.getReg());
444 unsigned Rm = getARMRegisterNumbering(MO1.getReg());
445 unsigned ShImm = ARM_AM::getAM2Offset(MO2.getImm());
446 bool isAdd = ARM_AM::getAM2Op(MO2.getImm()) == ARM_AM::add;
447 ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(MO2.getImm());
448 unsigned SBits = getShiftOp(ShOp);
457 uint32_t Binary = Rm;
459 Binary |= SBits << 5;
460 Binary |= ShImm << 7;
466 uint32_t ARMMCCodeEmitter::
467 getAddrMode2OpValue(const MCInst &MI, unsigned OpIdx,
468 SmallVectorImpl<MCFixup> &Fixups) const {
470 // {13} 1 == imm12, 0 == Rm
473 const MCOperand &MO = MI.getOperand(OpIdx);
474 unsigned Rn = getARMRegisterNumbering(MO.getReg());
475 uint32_t Binary = getAddrMode2OffsetOpValue(MI, OpIdx + 1, Fixups);
480 uint32_t ARMMCCodeEmitter::
481 getAddrMode2OffsetOpValue(const MCInst &MI, unsigned OpIdx,
482 SmallVectorImpl<MCFixup> &Fixups) const {
483 // {13} 1 == imm12, 0 == Rm
486 const MCOperand &MO = MI.getOperand(OpIdx);
487 const MCOperand &MO1 = MI.getOperand(OpIdx+1);
488 unsigned Imm = MO1.getImm();
489 bool isAdd = ARM_AM::getAM2Op(Imm) == ARM_AM::add;
490 bool isReg = MO.getReg() != 0;
491 uint32_t Binary = ARM_AM::getAM2Offset(Imm);
492 // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm12
494 ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(Imm);
495 Binary <<= 7; // Shift amount is bits [11:7]
496 Binary |= getShiftOp(ShOp) << 5; // Shift type is bits [6:5]
497 Binary |= getARMRegisterNumbering(MO.getReg()); // Rm is bits [3:0]
499 return Binary | (isAdd << 12) | (isReg << 13);
502 uint32_t ARMMCCodeEmitter::
503 getAddrMode3OffsetOpValue(const MCInst &MI, unsigned OpIdx,
504 SmallVectorImpl<MCFixup> &Fixups) const {
505 // {9} 1 == imm8, 0 == Rm
509 const MCOperand &MO = MI.getOperand(OpIdx);
510 const MCOperand &MO1 = MI.getOperand(OpIdx+1);
511 unsigned Imm = MO1.getImm();
512 bool isAdd = ARM_AM::getAM3Op(Imm) == ARM_AM::add;
513 bool isImm = MO.getReg() == 0;
514 uint32_t Imm8 = ARM_AM::getAM3Offset(Imm);
515 // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm8
517 Imm8 = getARMRegisterNumbering(MO.getReg());
518 return Imm8 | (isAdd << 8) | (isImm << 9);
521 uint32_t ARMMCCodeEmitter::
522 getAddrMode3OpValue(const MCInst &MI, unsigned OpIdx,
523 SmallVectorImpl<MCFixup> &Fixups) const {
524 // {13} 1 == imm8, 0 == Rm
529 const MCOperand &MO = MI.getOperand(OpIdx);
530 const MCOperand &MO1 = MI.getOperand(OpIdx+1);
531 const MCOperand &MO2 = MI.getOperand(OpIdx+2);
532 unsigned Rn = getARMRegisterNumbering(MO.getReg());
533 unsigned Imm = MO2.getImm();
534 bool isAdd = ARM_AM::getAM3Op(Imm) == ARM_AM::add;
535 bool isImm = MO1.getReg() == 0;
536 uint32_t Imm8 = ARM_AM::getAM3Offset(Imm);
537 // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm8
539 Imm8 = getARMRegisterNumbering(MO1.getReg());
540 return (Rn << 9) | Imm8 | (isAdd << 8) | (isImm << 13);
543 /// getAddrMode5OpValue - Return encoding info for 'reg +/- imm12' operand.
544 uint32_t ARMMCCodeEmitter::
545 getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx,
546 SmallVectorImpl<MCFixup> &Fixups) const {
548 // {8} = (U)nsigned (add == '1', sub == '0')
551 // If The first operand isn't a register, we have a label reference.
552 const MCOperand &MO = MI.getOperand(OpIdx);
554 Reg = getARMRegisterNumbering(ARM::PC); // Rn is PC.
557 assert(MO.isExpr() && "Unexpected machine operand type!");
558 const MCExpr *Expr = MO.getExpr();
559 MCFixupKind Kind = MCFixupKind(ARM::fixup_arm_vfp_pcrel_12);
560 Fixups.push_back(MCFixup::Create(0, Expr, Kind));
562 ++MCNumCPRelocations;
564 EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm8, Fixups);
566 uint32_t Binary = ARM_AM::getAM5Offset(Imm8);
567 // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
568 if (ARM_AM::getAM5Op(Imm8) == ARM_AM::add)
570 Binary |= (Reg << 9);
574 unsigned ARMMCCodeEmitter::
575 getSORegOpValue(const MCInst &MI, unsigned OpIdx,
576 SmallVectorImpl<MCFixup> &Fixups) const {
577 // Sub-operands are [reg, reg, imm]. The first register is Rm, the reg to be
578 // shifted. The second is either Rs, the amount to shift by, or reg0 in which
579 // case the imm contains the amount to shift by.
582 // {4} = 1 if reg shift, 0 if imm shift
590 const MCOperand &MO = MI.getOperand(OpIdx);
591 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
592 const MCOperand &MO2 = MI.getOperand(OpIdx + 2);
593 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm());
596 unsigned Binary = getARMRegisterNumbering(MO.getReg());
598 // Encode the shift opcode.
600 unsigned Rs = MO1.getReg();
602 // Set shift operand (bit[7:4]).
607 // RRX - 0110 and bit[11:8] clear.
609 default: llvm_unreachable("Unknown shift opc!");
610 case ARM_AM::lsl: SBits = 0x1; break;
611 case ARM_AM::lsr: SBits = 0x3; break;
612 case ARM_AM::asr: SBits = 0x5; break;
613 case ARM_AM::ror: SBits = 0x7; break;
614 case ARM_AM::rrx: SBits = 0x6; break;
617 // Set shift operand (bit[6:4]).
623 default: llvm_unreachable("Unknown shift opc!");
624 case ARM_AM::lsl: SBits = 0x0; break;
625 case ARM_AM::lsr: SBits = 0x2; break;
626 case ARM_AM::asr: SBits = 0x4; break;
627 case ARM_AM::ror: SBits = 0x6; break;
631 Binary |= SBits << 4;
632 if (SOpc == ARM_AM::rrx)
635 // Encode the shift operation Rs or shift_imm (except rrx).
637 // Encode Rs bit[11:8].
638 assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0);
639 return Binary | (getARMRegisterNumbering(Rs) << ARMII::RegRsShift);
642 // Encode shift_imm bit[11:7].
643 return Binary | ARM_AM::getSORegOffset(MO2.getImm()) << 7;
646 unsigned ARMMCCodeEmitter::
647 getT2AddrModeSORegOpValue(const MCInst &MI, unsigned OpNum,
648 SmallVectorImpl<MCFixup> &Fixups) const {
649 const MCOperand &MO1 = MI.getOperand(OpNum);
650 const MCOperand &MO2 = MI.getOperand(OpNum+1);
651 const MCOperand &MO3 = MI.getOperand(OpNum+2);
653 // Encoded as [Rn, Rm, imm].
654 // FIXME: Needs fixup support.
655 unsigned Value = getARMRegisterNumbering(MO1.getReg());
657 Value |= getARMRegisterNumbering(MO2.getReg());
659 Value |= MO3.getImm();
664 unsigned ARMMCCodeEmitter::
665 getT2AddrModeImm8OpValue(const MCInst &MI, unsigned OpNum,
666 SmallVectorImpl<MCFixup> &Fixups) const {
667 const MCOperand &MO1 = MI.getOperand(OpNum);
668 const MCOperand &MO2 = MI.getOperand(OpNum+1);
670 // FIXME: Needs fixup support.
671 unsigned Value = getARMRegisterNumbering(MO1.getReg());
673 // Even though the immediate is 8 bits long, we need 9 bits in order
674 // to represent the (inverse of the) sign bit.
676 int32_t tmp = (int32_t)MO2.getImm();
680 Value |= 256; // Set the ADD bit
685 unsigned ARMMCCodeEmitter::
686 getT2AddrModeImm8OffsetOpValue(const MCInst &MI, unsigned OpNum,
687 SmallVectorImpl<MCFixup> &Fixups) const {
688 const MCOperand &MO1 = MI.getOperand(OpNum);
690 // FIXME: Needs fixup support.
692 int32_t tmp = (int32_t)MO1.getImm();
696 Value |= 256; // Set the ADD bit
701 unsigned ARMMCCodeEmitter::
702 getT2AddrModeImm12OpValue(const MCInst &MI, unsigned OpNum,
703 SmallVectorImpl<MCFixup> &Fixups) const {
704 const MCOperand &MO1 = MI.getOperand(OpNum);
705 const MCOperand &MO2 = MI.getOperand(OpNum+1);
707 // FIXME: Needs fixup support.
708 unsigned Value = getARMRegisterNumbering(MO1.getReg());
710 Value |= MO2.getImm() & 4095;
714 unsigned ARMMCCodeEmitter::
715 getT2SORegOpValue(const MCInst &MI, unsigned OpIdx,
716 SmallVectorImpl<MCFixup> &Fixups) const {
717 // Sub-operands are [reg, imm]. The first register is Rm, the reg to be
718 // shifted. The second is the amount to shift by.
725 const MCOperand &MO = MI.getOperand(OpIdx);
726 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
727 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO1.getImm());
730 unsigned Binary = getARMRegisterNumbering(MO.getReg());
732 // Encode the shift opcode.
734 // Set shift operand (bit[6:4]).
740 default: llvm_unreachable("Unknown shift opc!");
741 case ARM_AM::lsl: SBits = 0x0; break;
742 case ARM_AM::lsr: SBits = 0x2; break;
743 case ARM_AM::asr: SBits = 0x4; break;
744 case ARM_AM::ror: SBits = 0x6; break;
747 Binary |= SBits << 4;
748 if (SOpc == ARM_AM::rrx)
751 // Encode shift_imm bit[11:7].
752 return Binary | ARM_AM::getSORegOffset(MO1.getImm()) << 7;
755 unsigned ARMMCCodeEmitter::
756 getBitfieldInvertedMaskOpValue(const MCInst &MI, unsigned Op,
757 SmallVectorImpl<MCFixup> &Fixups) const {
758 // 10 bits. lower 5 bits are are the lsb of the mask, high five bits are the
760 const MCOperand &MO = MI.getOperand(Op);
761 uint32_t v = ~MO.getImm();
762 uint32_t lsb = CountTrailingZeros_32(v);
763 uint32_t msb = (32 - CountLeadingZeros_32 (v)) - 1;
764 assert (v != 0 && lsb < 32 && msb < 32 && "Illegal bitfield mask!");
765 return lsb | (msb << 5);
768 unsigned ARMMCCodeEmitter::
769 getRegisterListOpValue(const MCInst &MI, unsigned Op,
770 SmallVectorImpl<MCFixup> &Fixups) const {
773 // {7-0} = Number of registers
776 // {15-0} = Bitfield of GPRs.
777 unsigned Reg = MI.getOperand(Op).getReg();
778 bool SPRRegs = ARM::SPRRegClass.contains(Reg);
779 bool DPRRegs = ARM::DPRRegClass.contains(Reg);
783 if (SPRRegs || DPRRegs) {
785 unsigned RegNo = getARMRegisterNumbering(Reg);
786 unsigned NumRegs = (MI.getNumOperands() - Op) & 0xff;
787 Binary |= (RegNo & 0x1f) << 8;
791 Binary |= NumRegs * 2;
793 for (unsigned I = Op, E = MI.getNumOperands(); I < E; ++I) {
794 unsigned RegNo = getARMRegisterNumbering(MI.getOperand(I).getReg());
795 Binary |= 1 << RegNo;
802 /// getAddrMode6AddressOpValue - Encode an addrmode6 register number along
803 /// with the alignment operand.
804 unsigned ARMMCCodeEmitter::
805 getAddrMode6AddressOpValue(const MCInst &MI, unsigned Op,
806 SmallVectorImpl<MCFixup> &Fixups) const {
807 const MCOperand &Reg = MI.getOperand(Op);
808 const MCOperand &Imm = MI.getOperand(Op + 1);
810 unsigned RegNo = getARMRegisterNumbering(Reg.getReg());
813 switch (Imm.getImm()) {
817 case 8: Align = 0x01; break;
818 case 16: Align = 0x02; break;
819 case 32: Align = 0x03; break;
822 return RegNo | (Align << 4);
825 /// getAddrMode6DupAddressOpValue - Encode an addrmode6 register number and
826 /// alignment operand for use in VLD-dup instructions. This is the same as
827 /// getAddrMode6AddressOpValue except for the alignment encoding, which is
828 /// different for VLD4-dup.
829 unsigned ARMMCCodeEmitter::
830 getAddrMode6DupAddressOpValue(const MCInst &MI, unsigned Op,
831 SmallVectorImpl<MCFixup> &Fixups) const {
832 const MCOperand &Reg = MI.getOperand(Op);
833 const MCOperand &Imm = MI.getOperand(Op + 1);
835 unsigned RegNo = getARMRegisterNumbering(Reg.getReg());
838 switch (Imm.getImm()) {
842 case 8: Align = 0x01; break;
843 case 16: Align = 0x03; break;
846 return RegNo | (Align << 4);
849 unsigned ARMMCCodeEmitter::
850 getAddrMode6OffsetOpValue(const MCInst &MI, unsigned Op,
851 SmallVectorImpl<MCFixup> &Fixups) const {
852 const MCOperand &MO = MI.getOperand(Op);
853 if (MO.getReg() == 0) return 0x0D;
857 void ARMMCCodeEmitter::
858 EncodeInstruction(const MCInst &MI, raw_ostream &OS,
859 SmallVectorImpl<MCFixup> &Fixups) const {
860 // Pseudo instructions don't get encoded.
861 const TargetInstrDesc &Desc = TII.get(MI.getOpcode());
862 uint64_t TSFlags = Desc.TSFlags;
863 if ((TSFlags & ARMII::FormMask) == ARMII::Pseudo)
866 // Basic size info comes from the TSFlags field.
867 switch ((TSFlags & ARMII::SizeMask) >> ARMII::SizeShift) {
868 default: llvm_unreachable("Unexpected instruction size!");
869 case ARMII::Size2Bytes: Size = 2; break;
870 case ARMII::Size4Bytes: Size = 4; break;
872 EmitConstant(getBinaryCodeForInstr(MI, Fixups), Size, OS);
873 ++MCNumEmitted; // Keep track of the # of mi's emitted.
876 #include "ARMGenMCCodeEmitter.inc"