1 //===-- ARM/ARMMCCodeEmitter.cpp - Convert ARM code to machine code -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the ARMMCCodeEmitter class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "mccodeemitter"
16 #include "ARMAddressingModes.h"
17 #include "ARMFixupKinds.h"
18 #include "ARMInstrInfo.h"
19 #include "llvm/MC/MCCodeEmitter.h"
20 #include "llvm/MC/MCExpr.h"
21 #include "llvm/MC/MCInst.h"
22 #include "llvm/ADT/Statistic.h"
23 #include "llvm/Support/raw_ostream.h"
26 STATISTIC(MCNumEmitted, "Number of MC instructions emitted.");
27 STATISTIC(MCNumCPRelocations, "Number of constant pool relocations created.");
30 class ARMMCCodeEmitter : public MCCodeEmitter {
31 ARMMCCodeEmitter(const ARMMCCodeEmitter &); // DO NOT IMPLEMENT
32 void operator=(const ARMMCCodeEmitter &); // DO NOT IMPLEMENT
33 const TargetMachine &TM;
34 const TargetInstrInfo &TII;
38 ARMMCCodeEmitter(TargetMachine &tm, MCContext &ctx)
39 : TM(tm), TII(*TM.getInstrInfo()), Ctx(ctx) {
42 ~ARMMCCodeEmitter() {}
44 unsigned getMachineSoImmOpValue(unsigned SoImm) const;
46 // getBinaryCodeForInstr - TableGen'erated function for getting the
47 // binary encoding for an instruction.
48 unsigned getBinaryCodeForInstr(const MCInst &MI,
49 SmallVectorImpl<MCFixup> &Fixups) const;
51 /// getMachineOpValue - Return binary encoding of operand. If the machine
52 /// operand requires relocation, record the relocation and return zero.
53 unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO,
54 SmallVectorImpl<MCFixup> &Fixups) const;
56 /// getMovtImmOpValue - Return the encoding for the movw/movt pair
57 uint32_t getMovtImmOpValue(const MCInst &MI, unsigned OpIdx,
58 SmallVectorImpl<MCFixup> &Fixups) const;
60 bool EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx,
61 unsigned &Reg, unsigned &Imm,
62 SmallVectorImpl<MCFixup> &Fixups) const;
64 /// getThumbBLTargetOpValue - Return encoding info for Thumb immediate
66 uint32_t getThumbBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
67 SmallVectorImpl<MCFixup> &Fixups) const;
69 /// getThumbBLXTargetOpValue - Return encoding info for Thumb immediate
70 /// BLX branch target.
71 uint32_t getThumbBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
72 SmallVectorImpl<MCFixup> &Fixups) const;
74 /// getThumbBRTargetOpValue - Return encoding info for Thumb branch target.
75 uint32_t getThumbBRTargetOpValue(const MCInst &MI, unsigned OpIdx,
76 SmallVectorImpl<MCFixup> &Fixups) const;
78 /// getThumbBCCTargetOpValue - Return encoding info for Thumb branch target.
79 uint32_t getThumbBCCTargetOpValue(const MCInst &MI, unsigned OpIdx,
80 SmallVectorImpl<MCFixup> &Fixups) const;
82 /// getThumbCBTargetOpValue - Return encoding info for Thumb branch target.
83 uint32_t getThumbCBTargetOpValue(const MCInst &MI, unsigned OpIdx,
84 SmallVectorImpl<MCFixup> &Fixups) const;
86 /// getBranchTargetOpValue - Return encoding info for 24-bit immediate
88 uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
89 SmallVectorImpl<MCFixup> &Fixups) const;
91 /// getUnconditionalBranchTargetOpValue - Return encoding info for 24-bit
92 /// immediate Thumb2 direct branch target.
93 uint32_t getUnconditionalBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
94 SmallVectorImpl<MCFixup> &Fixups) const;
97 /// getAdrLabelOpValue - Return encoding info for 12-bit immediate
99 uint32_t getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
100 SmallVectorImpl<MCFixup> &Fixups) const;
101 uint32_t getThumbAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
102 SmallVectorImpl<MCFixup> &Fixups) const;
103 uint32_t getT2AdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
104 SmallVectorImpl<MCFixup> &Fixups) const;
107 /// getAddrModeImm12OpValue - Return encoding info for 'reg +/- imm12'
109 uint32_t getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx,
110 SmallVectorImpl<MCFixup> &Fixups) const;
112 /// getThumbAddrModeRegRegOpValue - Return encoding for 'reg + reg' operand.
113 uint32_t getThumbAddrModeRegRegOpValue(const MCInst &MI, unsigned OpIdx,
114 SmallVectorImpl<MCFixup> &Fixups)const;
116 /// getT2AddrModeImm8s4OpValue - Return encoding info for 'reg +/- imm8<<2'
118 uint32_t getT2AddrModeImm8s4OpValue(const MCInst &MI, unsigned OpIdx,
119 SmallVectorImpl<MCFixup> &Fixups) const;
122 /// getLdStSORegOpValue - Return encoding info for 'reg +/- reg shop imm'
123 /// operand as needed by load/store instructions.
124 uint32_t getLdStSORegOpValue(const MCInst &MI, unsigned OpIdx,
125 SmallVectorImpl<MCFixup> &Fixups) const;
127 /// getLdStmModeOpValue - Return encoding for load/store multiple mode.
128 uint32_t getLdStmModeOpValue(const MCInst &MI, unsigned OpIdx,
129 SmallVectorImpl<MCFixup> &Fixups) const {
130 ARM_AM::AMSubMode Mode = (ARM_AM::AMSubMode)MI.getOperand(OpIdx).getImm();
132 default: assert(0 && "Unknown addressing sub-mode!");
133 case ARM_AM::da: return 0;
134 case ARM_AM::ia: return 1;
135 case ARM_AM::db: return 2;
136 case ARM_AM::ib: return 3;
139 /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
141 unsigned getShiftOp(ARM_AM::ShiftOpc ShOpc) const {
143 default: llvm_unreachable("Unknown shift opc!");
144 case ARM_AM::no_shift:
145 case ARM_AM::lsl: return 0;
146 case ARM_AM::lsr: return 1;
147 case ARM_AM::asr: return 2;
149 case ARM_AM::rrx: return 3;
154 /// getAddrMode2OpValue - Return encoding for addrmode2 operands.
155 uint32_t getAddrMode2OpValue(const MCInst &MI, unsigned OpIdx,
156 SmallVectorImpl<MCFixup> &Fixups) const;
158 /// getAddrMode2OffsetOpValue - Return encoding for am2offset operands.
159 uint32_t getAddrMode2OffsetOpValue(const MCInst &MI, unsigned OpIdx,
160 SmallVectorImpl<MCFixup> &Fixups) const;
162 /// getAddrMode3OffsetOpValue - Return encoding for am3offset operands.
163 uint32_t getAddrMode3OffsetOpValue(const MCInst &MI, unsigned OpIdx,
164 SmallVectorImpl<MCFixup> &Fixups) const;
166 /// getAddrMode3OpValue - Return encoding for addrmode3 operands.
167 uint32_t getAddrMode3OpValue(const MCInst &MI, unsigned OpIdx,
168 SmallVectorImpl<MCFixup> &Fixups) const;
170 /// getAddrModeThumbSPOpValue - Return encoding info for 'reg +/- imm12'
172 uint32_t getAddrModeThumbSPOpValue(const MCInst &MI, unsigned OpIdx,
173 SmallVectorImpl<MCFixup> &Fixups) const;
175 /// getAddrModeISOpValue - Encode the t_addrmode_is# operands.
176 uint32_t getAddrModeISOpValue(const MCInst &MI, unsigned OpIdx,
177 SmallVectorImpl<MCFixup> &Fixups) const;
179 /// getAddrModePCOpValue - Return encoding for t_addrmode_pc operands.
180 uint32_t getAddrModePCOpValue(const MCInst &MI, unsigned OpIdx,
181 SmallVectorImpl<MCFixup> &Fixups) const;
183 /// getAddrMode5OpValue - Return encoding info for 'reg +/- imm8' operand.
184 uint32_t getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx,
185 SmallVectorImpl<MCFixup> &Fixups) const;
187 /// getCCOutOpValue - Return encoding of the 's' bit.
188 unsigned getCCOutOpValue(const MCInst &MI, unsigned Op,
189 SmallVectorImpl<MCFixup> &Fixups) const {
190 // The operand is either reg0 or CPSR. The 's' bit is encoded as '0' or
192 return MI.getOperand(Op).getReg() == ARM::CPSR;
195 /// getSOImmOpValue - Return an encoded 12-bit shifted-immediate value.
196 unsigned getSOImmOpValue(const MCInst &MI, unsigned Op,
197 SmallVectorImpl<MCFixup> &Fixups) const {
198 unsigned SoImm = MI.getOperand(Op).getImm();
199 int SoImmVal = ARM_AM::getSOImmVal(SoImm);
200 assert(SoImmVal != -1 && "Not a valid so_imm value!");
202 // Encode rotate_imm.
203 unsigned Binary = (ARM_AM::getSOImmValRot((unsigned)SoImmVal) >> 1)
204 << ARMII::SoRotImmShift;
207 Binary |= ARM_AM::getSOImmValImm((unsigned)SoImmVal);
211 /// getT2SOImmOpValue - Return an encoded 12-bit shifted-immediate value.
212 unsigned getT2SOImmOpValue(const MCInst &MI, unsigned Op,
213 SmallVectorImpl<MCFixup> &Fixups) const {
214 unsigned SoImm = MI.getOperand(Op).getImm();
215 unsigned Encoded = ARM_AM::getT2SOImmVal(SoImm);
216 assert(Encoded != ~0U && "Not a Thumb2 so_imm value?");
220 unsigned getT2AddrModeSORegOpValue(const MCInst &MI, unsigned OpNum,
221 SmallVectorImpl<MCFixup> &Fixups) const;
222 unsigned getT2AddrModeImm8OpValue(const MCInst &MI, unsigned OpNum,
223 SmallVectorImpl<MCFixup> &Fixups) const;
224 unsigned getT2AddrModeImm8OffsetOpValue(const MCInst &MI, unsigned OpNum,
225 SmallVectorImpl<MCFixup> &Fixups) const;
226 unsigned getT2AddrModeImm12OffsetOpValue(const MCInst &MI, unsigned OpNum,
227 SmallVectorImpl<MCFixup> &Fixups) const;
229 /// getSORegOpValue - Return an encoded so_reg shifted register value.
230 unsigned getSORegOpValue(const MCInst &MI, unsigned Op,
231 SmallVectorImpl<MCFixup> &Fixups) const;
232 unsigned getT2SORegOpValue(const MCInst &MI, unsigned Op,
233 SmallVectorImpl<MCFixup> &Fixups) const;
235 unsigned getRotImmOpValue(const MCInst &MI, unsigned Op,
236 SmallVectorImpl<MCFixup> &Fixups) const {
237 switch (MI.getOperand(Op).getImm()) {
238 default: assert (0 && "Not a valid rot_imm value!");
246 unsigned getImmMinusOneOpValue(const MCInst &MI, unsigned Op,
247 SmallVectorImpl<MCFixup> &Fixups) const {
248 return MI.getOperand(Op).getImm() - 1;
251 unsigned getNEONVcvtImm32OpValue(const MCInst &MI, unsigned Op,
252 SmallVectorImpl<MCFixup> &Fixups) const {
253 return 64 - MI.getOperand(Op).getImm();
256 unsigned getBitfieldInvertedMaskOpValue(const MCInst &MI, unsigned Op,
257 SmallVectorImpl<MCFixup> &Fixups) const;
259 unsigned getRegisterListOpValue(const MCInst &MI, unsigned Op,
260 SmallVectorImpl<MCFixup> &Fixups) const;
261 unsigned getAddrMode6AddressOpValue(const MCInst &MI, unsigned Op,
262 SmallVectorImpl<MCFixup> &Fixups) const;
263 unsigned getAddrMode6DupAddressOpValue(const MCInst &MI, unsigned Op,
264 SmallVectorImpl<MCFixup> &Fixups) const;
265 unsigned getAddrMode6OffsetOpValue(const MCInst &MI, unsigned Op,
266 SmallVectorImpl<MCFixup> &Fixups) const;
268 unsigned NEONThumb2DataIPostEncoder(const MCInst &MI,
269 unsigned EncodedValue) const;
270 unsigned NEONThumb2LoadStorePostEncoder(const MCInst &MI,
271 unsigned EncodedValue) const;
272 unsigned NEONThumb2DupPostEncoder(const MCInst &MI,
273 unsigned EncodedValue) const;
275 unsigned VFPThumb2PostEncoder(const MCInst &MI,
276 unsigned EncodedValue) const;
278 void EmitByte(unsigned char C, raw_ostream &OS) const {
282 void EmitConstant(uint64_t Val, unsigned Size, raw_ostream &OS) const {
283 // Output the constant in little endian byte order.
284 for (unsigned i = 0; i != Size; ++i) {
285 EmitByte(Val & 255, OS);
290 void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
291 SmallVectorImpl<MCFixup> &Fixups) const;
294 } // end anonymous namespace
296 MCCodeEmitter *llvm::createARMMCCodeEmitter(const Target &, TargetMachine &TM,
298 return new ARMMCCodeEmitter(TM, Ctx);
301 /// NEONThumb2DataIPostEncoder - Post-process encoded NEON data-processing
302 /// instructions, and rewrite them to their Thumb2 form if we are currently in
304 unsigned ARMMCCodeEmitter::NEONThumb2DataIPostEncoder(const MCInst &MI,
305 unsigned EncodedValue) const {
306 const ARMSubtarget &Subtarget = TM.getSubtarget<ARMSubtarget>();
307 if (Subtarget.isThumb2()) {
308 // NEON Thumb2 data-processsing encodings are very simple: bit 24 is moved
309 // to bit 12 of the high half-word (i.e. bit 28), and bits 27-24 are
311 unsigned Bit24 = EncodedValue & 0x01000000;
312 unsigned Bit28 = Bit24 << 4;
313 EncodedValue &= 0xEFFFFFFF;
314 EncodedValue |= Bit28;
315 EncodedValue |= 0x0F000000;
321 /// NEONThumb2LoadStorePostEncoder - Post-process encoded NEON load/store
322 /// instructions, and rewrite them to their Thumb2 form if we are currently in
324 unsigned ARMMCCodeEmitter::NEONThumb2LoadStorePostEncoder(const MCInst &MI,
325 unsigned EncodedValue) const {
326 const ARMSubtarget &Subtarget = TM.getSubtarget<ARMSubtarget>();
327 if (Subtarget.isThumb2()) {
328 EncodedValue &= 0xF0FFFFFF;
329 EncodedValue |= 0x09000000;
335 /// NEONThumb2DupPostEncoder - Post-process encoded NEON vdup
336 /// instructions, and rewrite them to their Thumb2 form if we are currently in
338 unsigned ARMMCCodeEmitter::NEONThumb2DupPostEncoder(const MCInst &MI,
339 unsigned EncodedValue) const {
340 const ARMSubtarget &Subtarget = TM.getSubtarget<ARMSubtarget>();
341 if (Subtarget.isThumb2()) {
342 EncodedValue &= 0x00FFFFFF;
343 EncodedValue |= 0xEE000000;
349 /// VFPThumb2PostEncoder - Post-process encoded VFP instructions and rewrite
350 /// them to their Thumb2 form if we are currently in Thumb2 mode.
351 unsigned ARMMCCodeEmitter::
352 VFPThumb2PostEncoder(const MCInst &MI, unsigned EncodedValue) const {
353 if (TM.getSubtarget<ARMSubtarget>().isThumb2()) {
354 EncodedValue &= 0x0FFFFFFF;
355 EncodedValue |= 0xE0000000;
360 /// getMachineOpValue - Return binary encoding of operand. If the machine
361 /// operand requires relocation, record the relocation and return zero.
362 unsigned ARMMCCodeEmitter::
363 getMachineOpValue(const MCInst &MI, const MCOperand &MO,
364 SmallVectorImpl<MCFixup> &Fixups) const {
366 unsigned Reg = MO.getReg();
367 unsigned RegNo = getARMRegisterNumbering(Reg);
369 // Q registers are encoded as 2x their register number.
373 case ARM::Q0: case ARM::Q1: case ARM::Q2: case ARM::Q3:
374 case ARM::Q4: case ARM::Q5: case ARM::Q6: case ARM::Q7:
375 case ARM::Q8: case ARM::Q9: case ARM::Q10: case ARM::Q11:
376 case ARM::Q12: case ARM::Q13: case ARM::Q14: case ARM::Q15:
379 } else if (MO.isImm()) {
380 return static_cast<unsigned>(MO.getImm());
381 } else if (MO.isFPImm()) {
382 return static_cast<unsigned>(APFloat(MO.getFPImm())
383 .bitcastToAPInt().getHiBits(32).getLimitedValue());
386 llvm_unreachable("Unable to encode MCOperand!");
390 /// getAddrModeImmOpValue - Return encoding info for 'reg +/- imm' operand.
391 bool ARMMCCodeEmitter::
392 EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx, unsigned &Reg,
393 unsigned &Imm, SmallVectorImpl<MCFixup> &Fixups) const {
394 const MCOperand &MO = MI.getOperand(OpIdx);
395 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
397 Reg = getARMRegisterNumbering(MO.getReg());
399 int32_t SImm = MO1.getImm();
402 // Special value for #-0
403 if (SImm == INT32_MIN)
406 // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
416 /// getBranchTargetOpValue - Helper function to get the branch target operand,
417 /// which is either an immediate or requires a fixup.
418 static uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
420 SmallVectorImpl<MCFixup> &Fixups) {
421 const MCOperand &MO = MI.getOperand(OpIdx);
423 // If the destination is an immediate, we have nothing to do.
424 if (MO.isImm()) return MO.getImm();
425 assert(MO.isExpr() && "Unexpected branch target type!");
426 const MCExpr *Expr = MO.getExpr();
427 MCFixupKind Kind = MCFixupKind(FixupKind);
428 Fixups.push_back(MCFixup::Create(0, Expr, Kind));
430 // All of the information is in the fixup.
434 /// getThumbBLTargetOpValue - Return encoding info for immediate branch target.
435 uint32_t ARMMCCodeEmitter::
436 getThumbBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
437 SmallVectorImpl<MCFixup> &Fixups) const {
438 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_bl, Fixups);
441 /// getThumbBLXTargetOpValue - Return encoding info for Thumb immediate
442 /// BLX branch target.
443 uint32_t ARMMCCodeEmitter::
444 getThumbBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
445 SmallVectorImpl<MCFixup> &Fixups) const {
446 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_blx, Fixups);
449 /// getThumbBRTargetOpValue - Return encoding info for Thumb branch target.
450 uint32_t ARMMCCodeEmitter::
451 getThumbBRTargetOpValue(const MCInst &MI, unsigned OpIdx,
452 SmallVectorImpl<MCFixup> &Fixups) const {
453 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_br, Fixups);
456 /// getThumbBCCTargetOpValue - Return encoding info for Thumb branch target.
457 uint32_t ARMMCCodeEmitter::
458 getThumbBCCTargetOpValue(const MCInst &MI, unsigned OpIdx,
459 SmallVectorImpl<MCFixup> &Fixups) const {
460 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_bcc, Fixups);
463 /// getThumbCBTargetOpValue - Return encoding info for Thumb branch target.
464 uint32_t ARMMCCodeEmitter::
465 getThumbCBTargetOpValue(const MCInst &MI, unsigned OpIdx,
466 SmallVectorImpl<MCFixup> &Fixups) const {
467 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_cb, Fixups);
470 /// getBranchTargetOpValue - Return encoding info for 24-bit immediate branch
472 uint32_t ARMMCCodeEmitter::
473 getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
474 SmallVectorImpl<MCFixup> &Fixups) const {
475 // FIXME: This really, really shouldn't use TargetMachine. We don't want
476 // coupling between MC and TM anywhere we can help it.
477 const ARMSubtarget &Subtarget = TM.getSubtarget<ARMSubtarget>();
478 if (Subtarget.isThumb2())
480 ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_condbranch, Fixups);
481 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_branch, Fixups);
484 /// getUnconditionalBranchTargetOpValue - Return encoding info for 24-bit
485 /// immediate branch target.
486 uint32_t ARMMCCodeEmitter::
487 getUnconditionalBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
488 SmallVectorImpl<MCFixup> &Fixups) const {
490 ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_uncondbranch, Fixups);
491 bool I = (Val & 0x800000);
492 bool J1 = (Val & 0x400000);
493 bool J2 = (Val & 0x200000);
507 /// getAdrLabelOpValue - Return encoding info for 12-bit immediate ADR label
509 uint32_t ARMMCCodeEmitter::
510 getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
511 SmallVectorImpl<MCFixup> &Fixups) const {
512 assert(MI.getOperand(OpIdx).isExpr() && "Unexpected adr target type!");
513 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_adr_pcrel_12,
517 /// getAdrLabelOpValue - Return encoding info for 12-bit immediate ADR label
519 uint32_t ARMMCCodeEmitter::
520 getT2AdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
521 SmallVectorImpl<MCFixup> &Fixups) const {
522 assert(MI.getOperand(OpIdx).isExpr() && "Unexpected adr target type!");
523 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_adr_pcrel_12,
527 /// getAdrLabelOpValue - Return encoding info for 8-bit immediate ADR label
529 uint32_t ARMMCCodeEmitter::
530 getThumbAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
531 SmallVectorImpl<MCFixup> &Fixups) const {
532 assert(MI.getOperand(OpIdx).isExpr() && "Unexpected adr target type!");
533 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_thumb_adr_pcrel_10,
537 /// getThumbAddrModeRegRegOpValue - Return encoding info for 'reg + reg'
539 uint32_t ARMMCCodeEmitter::
540 getThumbAddrModeRegRegOpValue(const MCInst &MI, unsigned OpIdx,
541 SmallVectorImpl<MCFixup> &) const {
545 const MCOperand &MO1 = MI.getOperand(OpIdx);
546 const MCOperand &MO2 = MI.getOperand(OpIdx + 1);
547 unsigned Rn = getARMRegisterNumbering(MO1.getReg());
548 unsigned Rm = getARMRegisterNumbering(MO2.getReg());
549 return (Rm << 3) | Rn;
552 /// getAddrModeImm12OpValue - Return encoding info for 'reg +/- imm12' operand.
553 uint32_t ARMMCCodeEmitter::
554 getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx,
555 SmallVectorImpl<MCFixup> &Fixups) const {
557 // {12} = (U)nsigned (add == '1', sub == '0')
561 // If The first operand isn't a register, we have a label reference.
562 const MCOperand &MO = MI.getOperand(OpIdx);
563 const MCOperand &MO2 = MI.getOperand(OpIdx+1);
564 if (!MO.isReg() || (MO.getReg() == ARM::PC && MO2.isExpr())) {
565 Reg = getARMRegisterNumbering(ARM::PC); // Rn is PC.
567 isAdd = false ; // 'U' bit is set as part of the fixup.
569 const MCExpr *Expr = 0;
573 Expr = MO2.getExpr();
575 const ARMSubtarget &Subtarget = TM.getSubtarget<ARMSubtarget>();
577 if (Subtarget.isThumb2())
578 Kind = MCFixupKind(ARM::fixup_t2_ldst_pcrel_12);
580 Kind = MCFixupKind(ARM::fixup_arm_ldst_pcrel_12);
581 Fixups.push_back(MCFixup::Create(0, Expr, Kind));
583 ++MCNumCPRelocations;
585 isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm12, Fixups);
587 uint32_t Binary = Imm12 & 0xfff;
588 // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
591 Binary |= (Reg << 13);
595 /// getT2AddrModeImm8s4OpValue - Return encoding info for
596 /// 'reg +/- imm8<<2' operand.
597 uint32_t ARMMCCodeEmitter::
598 getT2AddrModeImm8s4OpValue(const MCInst &MI, unsigned OpIdx,
599 SmallVectorImpl<MCFixup> &Fixups) const {
601 // {8} = (U)nsigned (add == '1', sub == '0')
605 // If The first operand isn't a register, we have a label reference.
606 const MCOperand &MO = MI.getOperand(OpIdx);
608 Reg = getARMRegisterNumbering(ARM::PC); // Rn is PC.
610 isAdd = false ; // 'U' bit is set as part of the fixup.
612 assert(MO.isExpr() && "Unexpected machine operand type!");
613 const MCExpr *Expr = MO.getExpr();
614 MCFixupKind Kind = MCFixupKind(ARM::fixup_arm_pcrel_10);
615 Fixups.push_back(MCFixup::Create(0, Expr, Kind));
617 ++MCNumCPRelocations;
619 isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm8, Fixups);
621 uint32_t Binary = (Imm8 >> 2) & 0xff;
622 // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
625 Binary |= (Reg << 9);
629 uint32_t ARMMCCodeEmitter::
630 getMovtImmOpValue(const MCInst &MI, unsigned OpIdx,
631 SmallVectorImpl<MCFixup> &Fixups) const {
632 // {20-16} = imm{15-12}
633 // {11-0} = imm{11-0}
634 const MCOperand &MO = MI.getOperand(OpIdx);
636 return static_cast<unsigned>(MO.getImm());
637 } else if (const MCSymbolRefExpr *Expr =
638 dyn_cast<MCSymbolRefExpr>(MO.getExpr())) {
640 switch (Expr->getKind()) {
641 default: assert(0 && "Unsupported ARMFixup");
642 case MCSymbolRefExpr::VK_ARM_HI16:
643 Kind = MCFixupKind(ARM::fixup_arm_movt_hi16);
645 case MCSymbolRefExpr::VK_ARM_LO16:
646 Kind = MCFixupKind(ARM::fixup_arm_movw_lo16);
649 Fixups.push_back(MCFixup::Create(0, Expr, Kind));
652 llvm_unreachable("Unsupported MCExpr type in MCOperand!");
656 uint32_t ARMMCCodeEmitter::
657 getLdStSORegOpValue(const MCInst &MI, unsigned OpIdx,
658 SmallVectorImpl<MCFixup> &Fixups) const {
659 const MCOperand &MO = MI.getOperand(OpIdx);
660 const MCOperand &MO1 = MI.getOperand(OpIdx+1);
661 const MCOperand &MO2 = MI.getOperand(OpIdx+2);
662 unsigned Rn = getARMRegisterNumbering(MO.getReg());
663 unsigned Rm = getARMRegisterNumbering(MO1.getReg());
664 unsigned ShImm = ARM_AM::getAM2Offset(MO2.getImm());
665 bool isAdd = ARM_AM::getAM2Op(MO2.getImm()) == ARM_AM::add;
666 ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(MO2.getImm());
667 unsigned SBits = getShiftOp(ShOp);
676 uint32_t Binary = Rm;
678 Binary |= SBits << 5;
679 Binary |= ShImm << 7;
685 uint32_t ARMMCCodeEmitter::
686 getAddrMode2OpValue(const MCInst &MI, unsigned OpIdx,
687 SmallVectorImpl<MCFixup> &Fixups) const {
689 // {13} 1 == imm12, 0 == Rm
692 const MCOperand &MO = MI.getOperand(OpIdx);
693 unsigned Rn = getARMRegisterNumbering(MO.getReg());
694 uint32_t Binary = getAddrMode2OffsetOpValue(MI, OpIdx + 1, Fixups);
699 uint32_t ARMMCCodeEmitter::
700 getAddrMode2OffsetOpValue(const MCInst &MI, unsigned OpIdx,
701 SmallVectorImpl<MCFixup> &Fixups) const {
702 // {13} 1 == imm12, 0 == Rm
705 const MCOperand &MO = MI.getOperand(OpIdx);
706 const MCOperand &MO1 = MI.getOperand(OpIdx+1);
707 unsigned Imm = MO1.getImm();
708 bool isAdd = ARM_AM::getAM2Op(Imm) == ARM_AM::add;
709 bool isReg = MO.getReg() != 0;
710 uint32_t Binary = ARM_AM::getAM2Offset(Imm);
711 // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm12
713 ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(Imm);
714 Binary <<= 7; // Shift amount is bits [11:7]
715 Binary |= getShiftOp(ShOp) << 5; // Shift type is bits [6:5]
716 Binary |= getARMRegisterNumbering(MO.getReg()); // Rm is bits [3:0]
718 return Binary | (isAdd << 12) | (isReg << 13);
721 uint32_t ARMMCCodeEmitter::
722 getAddrMode3OffsetOpValue(const MCInst &MI, unsigned OpIdx,
723 SmallVectorImpl<MCFixup> &Fixups) const {
724 // {9} 1 == imm8, 0 == Rm
728 const MCOperand &MO = MI.getOperand(OpIdx);
729 const MCOperand &MO1 = MI.getOperand(OpIdx+1);
730 unsigned Imm = MO1.getImm();
731 bool isAdd = ARM_AM::getAM3Op(Imm) == ARM_AM::add;
732 bool isImm = MO.getReg() == 0;
733 uint32_t Imm8 = ARM_AM::getAM3Offset(Imm);
734 // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm8
736 Imm8 = getARMRegisterNumbering(MO.getReg());
737 return Imm8 | (isAdd << 8) | (isImm << 9);
740 uint32_t ARMMCCodeEmitter::
741 getAddrMode3OpValue(const MCInst &MI, unsigned OpIdx,
742 SmallVectorImpl<MCFixup> &Fixups) const {
743 // {13} 1 == imm8, 0 == Rm
748 const MCOperand &MO = MI.getOperand(OpIdx);
749 const MCOperand &MO1 = MI.getOperand(OpIdx+1);
750 const MCOperand &MO2 = MI.getOperand(OpIdx+2);
751 unsigned Rn = getARMRegisterNumbering(MO.getReg());
752 unsigned Imm = MO2.getImm();
753 bool isAdd = ARM_AM::getAM3Op(Imm) == ARM_AM::add;
754 bool isImm = MO1.getReg() == 0;
755 uint32_t Imm8 = ARM_AM::getAM3Offset(Imm);
756 // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm8
758 Imm8 = getARMRegisterNumbering(MO1.getReg());
759 return (Rn << 9) | Imm8 | (isAdd << 8) | (isImm << 13);
762 /// getAddrModeThumbSPOpValue - Encode the t_addrmode_sp operands.
763 uint32_t ARMMCCodeEmitter::
764 getAddrModeThumbSPOpValue(const MCInst &MI, unsigned OpIdx,
765 SmallVectorImpl<MCFixup> &Fixups) const {
768 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
769 assert(MI.getOperand(OpIdx).getReg() == ARM::SP &&
770 "Unexpected base register!");
772 // The immediate is already shifted for the implicit zeroes, so no change
774 return MO1.getImm() & 0xff;
777 /// getAddrModeISOpValue - Encode the t_addrmode_is# operands.
778 uint32_t ARMMCCodeEmitter::
779 getAddrModeISOpValue(const MCInst &MI, unsigned OpIdx,
780 SmallVectorImpl<MCFixup> &Fixups) const {
784 const MCOperand &MO = MI.getOperand(OpIdx);
785 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
786 unsigned Rn = getARMRegisterNumbering(MO.getReg());
787 unsigned Imm5 = MO1.getImm();
788 return ((Imm5 & 0x1f) << 3) | Rn;
791 /// getAddrModePCOpValue - Return encoding for t_addrmode_pc operands.
792 uint32_t ARMMCCodeEmitter::
793 getAddrModePCOpValue(const MCInst &MI, unsigned OpIdx,
794 SmallVectorImpl<MCFixup> &Fixups) const {
795 return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_cp, Fixups);
798 /// getAddrMode5OpValue - Return encoding info for 'reg +/- imm10' operand.
799 uint32_t ARMMCCodeEmitter::
800 getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx,
801 SmallVectorImpl<MCFixup> &Fixups) const {
803 // {8} = (U)nsigned (add == '1', sub == '0')
807 // If The first operand isn't a register, we have a label reference.
808 const MCOperand &MO = MI.getOperand(OpIdx);
810 Reg = getARMRegisterNumbering(ARM::PC); // Rn is PC.
812 isAdd = false; // 'U' bit is handled as part of the fixup.
814 assert(MO.isExpr() && "Unexpected machine operand type!");
815 const MCExpr *Expr = MO.getExpr();
817 const ARMSubtarget &Subtarget = TM.getSubtarget<ARMSubtarget>();
818 if (Subtarget.isThumb2())
819 Kind = MCFixupKind(ARM::fixup_t2_pcrel_10);
821 Kind = MCFixupKind(ARM::fixup_arm_pcrel_10);
822 Fixups.push_back(MCFixup::Create(0, Expr, Kind));
824 ++MCNumCPRelocations;
826 EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm8, Fixups);
827 isAdd = ARM_AM::getAM5Op(Imm8) == ARM_AM::add;
830 uint32_t Binary = ARM_AM::getAM5Offset(Imm8);
831 // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
834 Binary |= (Reg << 9);
838 unsigned ARMMCCodeEmitter::
839 getSORegOpValue(const MCInst &MI, unsigned OpIdx,
840 SmallVectorImpl<MCFixup> &Fixups) const {
841 // Sub-operands are [reg, reg, imm]. The first register is Rm, the reg to be
842 // shifted. The second is either Rs, the amount to shift by, or reg0 in which
843 // case the imm contains the amount to shift by.
846 // {4} = 1 if reg shift, 0 if imm shift
854 const MCOperand &MO = MI.getOperand(OpIdx);
855 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
856 const MCOperand &MO2 = MI.getOperand(OpIdx + 2);
857 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm());
860 unsigned Binary = getARMRegisterNumbering(MO.getReg());
862 // Encode the shift opcode.
864 unsigned Rs = MO1.getReg();
866 // Set shift operand (bit[7:4]).
871 // RRX - 0110 and bit[11:8] clear.
873 default: llvm_unreachable("Unknown shift opc!");
874 case ARM_AM::lsl: SBits = 0x1; break;
875 case ARM_AM::lsr: SBits = 0x3; break;
876 case ARM_AM::asr: SBits = 0x5; break;
877 case ARM_AM::ror: SBits = 0x7; break;
878 case ARM_AM::rrx: SBits = 0x6; break;
881 // Set shift operand (bit[6:4]).
887 default: llvm_unreachable("Unknown shift opc!");
888 case ARM_AM::lsl: SBits = 0x0; break;
889 case ARM_AM::lsr: SBits = 0x2; break;
890 case ARM_AM::asr: SBits = 0x4; break;
891 case ARM_AM::ror: SBits = 0x6; break;
895 Binary |= SBits << 4;
896 if (SOpc == ARM_AM::rrx)
899 // Encode the shift operation Rs or shift_imm (except rrx).
901 // Encode Rs bit[11:8].
902 assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0);
903 return Binary | (getARMRegisterNumbering(Rs) << ARMII::RegRsShift);
906 // Encode shift_imm bit[11:7].
907 return Binary | ARM_AM::getSORegOffset(MO2.getImm()) << 7;
910 unsigned ARMMCCodeEmitter::
911 getT2AddrModeSORegOpValue(const MCInst &MI, unsigned OpNum,
912 SmallVectorImpl<MCFixup> &Fixups) const {
913 const MCOperand &MO1 = MI.getOperand(OpNum);
914 const MCOperand &MO2 = MI.getOperand(OpNum+1);
915 const MCOperand &MO3 = MI.getOperand(OpNum+2);
917 // Encoded as [Rn, Rm, imm].
918 // FIXME: Needs fixup support.
919 unsigned Value = getARMRegisterNumbering(MO1.getReg());
921 Value |= getARMRegisterNumbering(MO2.getReg());
923 Value |= MO3.getImm();
928 unsigned ARMMCCodeEmitter::
929 getT2AddrModeImm8OpValue(const MCInst &MI, unsigned OpNum,
930 SmallVectorImpl<MCFixup> &Fixups) const {
931 const MCOperand &MO1 = MI.getOperand(OpNum);
932 const MCOperand &MO2 = MI.getOperand(OpNum+1);
934 // FIXME: Needs fixup support.
935 unsigned Value = getARMRegisterNumbering(MO1.getReg());
937 // Even though the immediate is 8 bits long, we need 9 bits in order
938 // to represent the (inverse of the) sign bit.
940 int32_t tmp = (int32_t)MO2.getImm();
944 Value |= 256; // Set the ADD bit
949 unsigned ARMMCCodeEmitter::
950 getT2AddrModeImm8OffsetOpValue(const MCInst &MI, unsigned OpNum,
951 SmallVectorImpl<MCFixup> &Fixups) const {
952 const MCOperand &MO1 = MI.getOperand(OpNum);
954 // FIXME: Needs fixup support.
956 int32_t tmp = (int32_t)MO1.getImm();
960 Value |= 256; // Set the ADD bit
965 unsigned ARMMCCodeEmitter::
966 getT2AddrModeImm12OffsetOpValue(const MCInst &MI, unsigned OpNum,
967 SmallVectorImpl<MCFixup> &Fixups) const {
968 const MCOperand &MO1 = MI.getOperand(OpNum);
970 // FIXME: Needs fixup support.
972 int32_t tmp = (int32_t)MO1.getImm();
976 Value |= 4096; // Set the ADD bit
981 unsigned ARMMCCodeEmitter::
982 getT2SORegOpValue(const MCInst &MI, unsigned OpIdx,
983 SmallVectorImpl<MCFixup> &Fixups) const {
984 // Sub-operands are [reg, imm]. The first register is Rm, the reg to be
985 // shifted. The second is the amount to shift by.
992 const MCOperand &MO = MI.getOperand(OpIdx);
993 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
994 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO1.getImm());
997 unsigned Binary = getARMRegisterNumbering(MO.getReg());
999 // Encode the shift opcode.
1001 // Set shift operand (bit[6:4]).
1007 default: llvm_unreachable("Unknown shift opc!");
1008 case ARM_AM::lsl: SBits = 0x0; break;
1009 case ARM_AM::lsr: SBits = 0x2; break;
1010 case ARM_AM::asr: SBits = 0x4; break;
1011 case ARM_AM::ror: SBits = 0x6; break;
1014 Binary |= SBits << 4;
1015 if (SOpc == ARM_AM::rrx)
1018 // Encode shift_imm bit[11:7].
1019 return Binary | ARM_AM::getSORegOffset(MO1.getImm()) << 7;
1022 unsigned ARMMCCodeEmitter::
1023 getBitfieldInvertedMaskOpValue(const MCInst &MI, unsigned Op,
1024 SmallVectorImpl<MCFixup> &Fixups) const {
1025 // 10 bits. lower 5 bits are are the lsb of the mask, high five bits are the
1027 const MCOperand &MO = MI.getOperand(Op);
1028 uint32_t v = ~MO.getImm();
1029 uint32_t lsb = CountTrailingZeros_32(v);
1030 uint32_t msb = (32 - CountLeadingZeros_32 (v)) - 1;
1031 assert (v != 0 && lsb < 32 && msb < 32 && "Illegal bitfield mask!");
1032 return lsb | (msb << 5);
1035 unsigned ARMMCCodeEmitter::
1036 getRegisterListOpValue(const MCInst &MI, unsigned Op,
1037 SmallVectorImpl<MCFixup> &Fixups) const {
1040 // {7-0} = Number of registers
1043 // {15-0} = Bitfield of GPRs.
1044 unsigned Reg = MI.getOperand(Op).getReg();
1045 bool SPRRegs = ARM::SPRRegClass.contains(Reg);
1046 bool DPRRegs = ARM::DPRRegClass.contains(Reg);
1048 unsigned Binary = 0;
1050 if (SPRRegs || DPRRegs) {
1052 unsigned RegNo = getARMRegisterNumbering(Reg);
1053 unsigned NumRegs = (MI.getNumOperands() - Op) & 0xff;
1054 Binary |= (RegNo & 0x1f) << 8;
1058 Binary |= NumRegs * 2;
1060 for (unsigned I = Op, E = MI.getNumOperands(); I < E; ++I) {
1061 unsigned RegNo = getARMRegisterNumbering(MI.getOperand(I).getReg());
1062 Binary |= 1 << RegNo;
1069 /// getAddrMode6AddressOpValue - Encode an addrmode6 register number along
1070 /// with the alignment operand.
1071 unsigned ARMMCCodeEmitter::
1072 getAddrMode6AddressOpValue(const MCInst &MI, unsigned Op,
1073 SmallVectorImpl<MCFixup> &Fixups) const {
1074 const MCOperand &Reg = MI.getOperand(Op);
1075 const MCOperand &Imm = MI.getOperand(Op + 1);
1077 unsigned RegNo = getARMRegisterNumbering(Reg.getReg());
1080 switch (Imm.getImm()) {
1084 case 8: Align = 0x01; break;
1085 case 16: Align = 0x02; break;
1086 case 32: Align = 0x03; break;
1089 return RegNo | (Align << 4);
1092 /// getAddrMode6DupAddressOpValue - Encode an addrmode6 register number and
1093 /// alignment operand for use in VLD-dup instructions. This is the same as
1094 /// getAddrMode6AddressOpValue except for the alignment encoding, which is
1095 /// different for VLD4-dup.
1096 unsigned ARMMCCodeEmitter::
1097 getAddrMode6DupAddressOpValue(const MCInst &MI, unsigned Op,
1098 SmallVectorImpl<MCFixup> &Fixups) const {
1099 const MCOperand &Reg = MI.getOperand(Op);
1100 const MCOperand &Imm = MI.getOperand(Op + 1);
1102 unsigned RegNo = getARMRegisterNumbering(Reg.getReg());
1105 switch (Imm.getImm()) {
1109 case 8: Align = 0x01; break;
1110 case 16: Align = 0x03; break;
1113 return RegNo | (Align << 4);
1116 unsigned ARMMCCodeEmitter::
1117 getAddrMode6OffsetOpValue(const MCInst &MI, unsigned Op,
1118 SmallVectorImpl<MCFixup> &Fixups) const {
1119 const MCOperand &MO = MI.getOperand(Op);
1120 if (MO.getReg() == 0) return 0x0D;
1124 void ARMMCCodeEmitter::
1125 EncodeInstruction(const MCInst &MI, raw_ostream &OS,
1126 SmallVectorImpl<MCFixup> &Fixups) const {
1127 const ARMSubtarget &Subtarget = TM.getSubtarget<ARMSubtarget>();
1128 // Pseudo instructions don't get encoded.
1129 const TargetInstrDesc &Desc = TII.get(MI.getOpcode());
1130 uint64_t TSFlags = Desc.TSFlags;
1131 if ((TSFlags & ARMII::FormMask) == ARMII::Pseudo)
1134 // Basic size info comes from the TSFlags field.
1135 switch ((TSFlags & ARMII::SizeMask) >> ARMII::SizeShift) {
1136 default: llvm_unreachable("Unexpected instruction size!");
1137 case ARMII::Size2Bytes: Size = 2; break;
1138 case ARMII::Size4Bytes: Size = 4; break;
1140 uint32_t Binary = getBinaryCodeForInstr(MI, Fixups);
1141 // Thumb 32-bit wide instructions need to be have the high order halfword
1143 if (Subtarget.isThumb() && Size == 4) {
1144 EmitConstant(Binary >> 16, 2, OS);
1145 EmitConstant(Binary & 0xffff, 2, OS);
1147 EmitConstant(Binary, Size, OS);
1148 ++MCNumEmitted; // Keep track of the # of mi's emitted.
1151 #include "ARMGenMCCodeEmitter.inc"