1 //===-- ARMInstrVFP.td - VFP support for ARM ---------------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM VFP instruction set.
12 //===----------------------------------------------------------------------===//
14 def SDT_FTOI : SDTypeProfile<1, 1, [SDTCisVT<0, f32>, SDTCisFP<1>]>;
15 def SDT_ITOF : SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisVT<1, f32>]>;
16 def SDT_CMPFP0 : SDTypeProfile<0, 1, [SDTCisFP<0>]>;
17 def SDT_VMOVDRR : SDTypeProfile<1, 2, [SDTCisVT<0, f64>, SDTCisVT<1, i32>,
20 def arm_ftoui : SDNode<"ARMISD::FTOUI", SDT_FTOI>;
21 def arm_ftosi : SDNode<"ARMISD::FTOSI", SDT_FTOI>;
22 def arm_sitof : SDNode<"ARMISD::SITOF", SDT_ITOF>;
23 def arm_uitof : SDNode<"ARMISD::UITOF", SDT_ITOF>;
24 def arm_fmstat : SDNode<"ARMISD::FMSTAT", SDTNone, [SDNPInGlue, SDNPOutGlue]>;
25 def arm_cmpfp : SDNode<"ARMISD::CMPFP", SDT_ARMCmp, [SDNPOutGlue]>;
26 def arm_cmpfp0 : SDNode<"ARMISD::CMPFPw0", SDT_CMPFP0, [SDNPOutGlue]>;
27 def arm_fmdrr : SDNode<"ARMISD::VMOVDRR", SDT_VMOVDRR>;
30 //===----------------------------------------------------------------------===//
31 // Operand Definitions.
34 // 8-bit floating-point immediate encodings.
35 def FPImmOperand : AsmOperandClass {
37 let ParserMethod = "parseFPImm";
40 def vfp_f32imm : Operand<f32>,
41 PatLeaf<(f32 fpimm), [{
42 return ARM_AM::getFP32Imm(N->getValueAPF()) != -1;
43 }], SDNodeXForm<fpimm, [{
44 APFloat InVal = N->getValueAPF();
45 uint32_t enc = ARM_AM::getFP32Imm(InVal);
46 return CurDAG->getTargetConstant(enc, MVT::i32);
48 let PrintMethod = "printFPImmOperand";
49 let ParserMatchClass = FPImmOperand;
52 def vfp_f64imm : Operand<f64>,
53 PatLeaf<(f64 fpimm), [{
54 return ARM_AM::getFP64Imm(N->getValueAPF()) != -1;
55 }], SDNodeXForm<fpimm, [{
56 APFloat InVal = N->getValueAPF();
57 uint32_t enc = ARM_AM::getFP64Imm(InVal);
58 return CurDAG->getTargetConstant(enc, MVT::i32);
60 let PrintMethod = "printFPImmOperand";
61 let ParserMatchClass = FPImmOperand;
64 def alignedload32 : PatFrag<(ops node:$ptr), (load node:$ptr), [{
65 return cast<LoadSDNode>(N)->getAlignment() >= 4;
68 def alignedstore32 : PatFrag<(ops node:$val, node:$ptr),
69 (store node:$val, node:$ptr), [{
70 return cast<StoreSDNode>(N)->getAlignment() >= 4;
73 // The VCVT to/from fixed-point instructions encode the 'fbits' operand
74 // (the number of fixed bits) differently than it appears in the assembly
75 // source. It's encoded as "Size - fbits" where Size is the size of the
76 // fixed-point representation (32 or 16) and fbits is the value appearing
77 // in the assembly source, an integer in [0,16] or (0,32], depending on size.
78 def fbits32_asm_operand : AsmOperandClass { let Name = "FBits32"; }
79 def fbits32 : Operand<i32> {
80 let PrintMethod = "printFBits32";
81 let ParserMatchClass = fbits32_asm_operand;
84 def fbits16_asm_operand : AsmOperandClass { let Name = "FBits16"; }
85 def fbits16 : Operand<i32> {
86 let PrintMethod = "printFBits16";
87 let ParserMatchClass = fbits16_asm_operand;
90 //===----------------------------------------------------------------------===//
91 // Load / store Instructions.
94 let canFoldAsLoad = 1, isReMaterializable = 1 in {
96 def VLDRD : ADI5<0b1101, 0b01, (outs DPR:$Dd), (ins addrmode5:$addr),
97 IIC_fpLoad64, "vldr", "\t$Dd, $addr",
98 [(set DPR:$Dd, (f64 (alignedload32 addrmode5:$addr)))]>;
100 def VLDRS : ASI5<0b1101, 0b01, (outs SPR:$Sd), (ins addrmode5:$addr),
101 IIC_fpLoad32, "vldr", "\t$Sd, $addr",
102 [(set SPR:$Sd, (load addrmode5:$addr))]> {
103 // Some single precision VFP instructions may be executed on both NEON and VFP
105 let D = VFPNeonDomain;
108 } // End of 'let canFoldAsLoad = 1, isReMaterializable = 1 in'
110 def VSTRD : ADI5<0b1101, 0b00, (outs), (ins DPR:$Dd, addrmode5:$addr),
111 IIC_fpStore64, "vstr", "\t$Dd, $addr",
112 [(alignedstore32 (f64 DPR:$Dd), addrmode5:$addr)]>;
114 def VSTRS : ASI5<0b1101, 0b00, (outs), (ins SPR:$Sd, addrmode5:$addr),
115 IIC_fpStore32, "vstr", "\t$Sd, $addr",
116 [(store SPR:$Sd, addrmode5:$addr)]> {
117 // Some single precision VFP instructions may be executed on both NEON and VFP
119 let D = VFPNeonDomain;
122 //===----------------------------------------------------------------------===//
123 // Load / store multiple Instructions.
126 multiclass vfp_ldst_mult<string asm, bit L_bit,
127 InstrItinClass itin, InstrItinClass itin_upd> {
130 AXDI4<(outs), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs, variable_ops),
132 !strconcat(asm, "ia${p}\t$Rn, $regs"), "", []> {
133 let Inst{24-23} = 0b01; // Increment After
134 let Inst{21} = 0; // No writeback
135 let Inst{20} = L_bit;
138 AXDI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs,
140 IndexModeUpd, itin_upd,
141 !strconcat(asm, "ia${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
142 let Inst{24-23} = 0b01; // Increment After
143 let Inst{21} = 1; // Writeback
144 let Inst{20} = L_bit;
147 AXDI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs,
149 IndexModeUpd, itin_upd,
150 !strconcat(asm, "db${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
151 let Inst{24-23} = 0b10; // Decrement Before
152 let Inst{21} = 1; // Writeback
153 let Inst{20} = L_bit;
158 AXSI4<(outs), (ins GPR:$Rn, pred:$p, spr_reglist:$regs, variable_ops),
160 !strconcat(asm, "ia${p}\t$Rn, $regs"), "", []> {
161 let Inst{24-23} = 0b01; // Increment After
162 let Inst{21} = 0; // No writeback
163 let Inst{20} = L_bit;
165 // Some single precision VFP instructions may be executed on both NEON and
167 let D = VFPNeonDomain;
170 AXSI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, spr_reglist:$regs,
172 IndexModeUpd, itin_upd,
173 !strconcat(asm, "ia${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
174 let Inst{24-23} = 0b01; // Increment After
175 let Inst{21} = 1; // Writeback
176 let Inst{20} = L_bit;
178 // Some single precision VFP instructions may be executed on both NEON and
180 let D = VFPNeonDomain;
183 AXSI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, spr_reglist:$regs,
185 IndexModeUpd, itin_upd,
186 !strconcat(asm, "db${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
187 let Inst{24-23} = 0b10; // Decrement Before
188 let Inst{21} = 1; // Writeback
189 let Inst{20} = L_bit;
191 // Some single precision VFP instructions may be executed on both NEON and
193 let D = VFPNeonDomain;
197 let neverHasSideEffects = 1 in {
199 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
200 defm VLDM : vfp_ldst_mult<"vldm", 1, IIC_fpLoad_m, IIC_fpLoad_mu>;
202 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
203 defm VSTM : vfp_ldst_mult<"vstm", 0, IIC_fpStore_m, IIC_fpStore_mu>;
205 } // neverHasSideEffects
207 def : MnemonicAlias<"vldm", "vldmia">;
208 def : MnemonicAlias<"vstm", "vstmia">;
210 // FLDM/FSTM - Load / Store multiple single / double precision registers for
212 // These instructions are deprecated!
213 def : VFP2MnemonicAlias<"fldmias", "vldmia">;
214 def : VFP2MnemonicAlias<"fldmdbs", "vldmdb">;
215 def : VFP2MnemonicAlias<"fldmeas", "vldmdb">;
216 def : VFP2MnemonicAlias<"fldmfds", "vldmia">;
217 def : VFP2MnemonicAlias<"fldmiad", "vldmia">;
218 def : VFP2MnemonicAlias<"fldmdbd", "vldmdb">;
219 def : VFP2MnemonicAlias<"fldmead", "vldmdb">;
220 def : VFP2MnemonicAlias<"fldmfdd", "vldmia">;
222 def : VFP2MnemonicAlias<"fstmias", "vstmia">;
223 def : VFP2MnemonicAlias<"fstmdbs", "vstmdb">;
224 def : VFP2MnemonicAlias<"fstmeas", "vstmia">;
225 def : VFP2MnemonicAlias<"fstmfds", "vstmdb">;
226 def : VFP2MnemonicAlias<"fstmiad", "vstmia">;
227 def : VFP2MnemonicAlias<"fstmdbd", "vstmdb">;
228 def : VFP2MnemonicAlias<"fstmead", "vstmia">;
229 def : VFP2MnemonicAlias<"fstmfdd", "vstmdb">;
231 def : InstAlias<"vpush${p} $r", (VSTMDDB_UPD SP, pred:$p, dpr_reglist:$r)>,
233 def : InstAlias<"vpush${p} $r", (VSTMSDB_UPD SP, pred:$p, spr_reglist:$r)>,
235 def : InstAlias<"vpop${p} $r", (VLDMDIA_UPD SP, pred:$p, dpr_reglist:$r)>,
237 def : InstAlias<"vpop${p} $r", (VLDMSIA_UPD SP, pred:$p, spr_reglist:$r)>,
239 defm : VFPDTAnyInstAlias<"vpush${p}", "$r",
240 (VSTMSDB_UPD SP, pred:$p, spr_reglist:$r)>;
241 defm : VFPDTAnyInstAlias<"vpush${p}", "$r",
242 (VSTMDDB_UPD SP, pred:$p, dpr_reglist:$r)>;
243 defm : VFPDTAnyInstAlias<"vpop${p}", "$r",
244 (VLDMSIA_UPD SP, pred:$p, spr_reglist:$r)>;
245 defm : VFPDTAnyInstAlias<"vpop${p}", "$r",
246 (VLDMDIA_UPD SP, pred:$p, dpr_reglist:$r)>;
248 // FLDMX, FSTMX - Load and store multiple unknown precision registers for
250 // These instruction are deprecated so we don't want them to get selected.
251 multiclass vfp_ldstx_mult<string asm, bit L_bit> {
254 AXXI4<(outs), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs, variable_ops),
255 IndexModeNone, !strconcat(asm, "iax${p}\t$Rn, $regs"), "", []> {
256 let Inst{24-23} = 0b01; // Increment After
257 let Inst{21} = 0; // No writeback
258 let Inst{20} = L_bit;
261 AXXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs, variable_ops),
262 IndexModeUpd, !strconcat(asm, "iax${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
263 let Inst{24-23} = 0b01; // Increment After
264 let Inst{21} = 1; // Writeback
265 let Inst{20} = L_bit;
268 AXXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs, variable_ops),
269 IndexModeUpd, !strconcat(asm, "dbx${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
270 let Inst{24-23} = 0b10; // Decrement Before
271 let Inst{21} = 1; // Writeback
272 let Inst{20} = L_bit;
276 defm FLDM : vfp_ldstx_mult<"fldm", 1>;
277 defm FSTM : vfp_ldstx_mult<"fstm", 0>;
279 def : VFP2MnemonicAlias<"fldmeax", "fldmdbx">;
280 def : VFP2MnemonicAlias<"fldmfdx", "fldmiax">;
282 def : VFP2MnemonicAlias<"fstmeax", "fstmiax">;
283 def : VFP2MnemonicAlias<"fstmfdx", "fstmdbx">;
285 //===----------------------------------------------------------------------===//
286 // FP Binary Operations.
289 let TwoOperandAliasConstraint = "$Dn = $Dd" in
290 def VADDD : ADbI<0b11100, 0b11, 0, 0,
291 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
292 IIC_fpALU64, "vadd", ".f64\t$Dd, $Dn, $Dm",
293 [(set DPR:$Dd, (fadd DPR:$Dn, (f64 DPR:$Dm)))]>;
295 let TwoOperandAliasConstraint = "$Sn = $Sd" in
296 def VADDS : ASbIn<0b11100, 0b11, 0, 0,
297 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
298 IIC_fpALU32, "vadd", ".f32\t$Sd, $Sn, $Sm",
299 [(set SPR:$Sd, (fadd SPR:$Sn, SPR:$Sm))]> {
300 // Some single precision VFP instructions may be executed on both NEON and
301 // VFP pipelines on A8.
302 let D = VFPNeonA8Domain;
305 let TwoOperandAliasConstraint = "$Dn = $Dd" in
306 def VSUBD : ADbI<0b11100, 0b11, 1, 0,
307 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
308 IIC_fpALU64, "vsub", ".f64\t$Dd, $Dn, $Dm",
309 [(set DPR:$Dd, (fsub DPR:$Dn, (f64 DPR:$Dm)))]>;
311 let TwoOperandAliasConstraint = "$Sn = $Sd" in
312 def VSUBS : ASbIn<0b11100, 0b11, 1, 0,
313 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
314 IIC_fpALU32, "vsub", ".f32\t$Sd, $Sn, $Sm",
315 [(set SPR:$Sd, (fsub SPR:$Sn, SPR:$Sm))]> {
316 // Some single precision VFP instructions may be executed on both NEON and
317 // VFP pipelines on A8.
318 let D = VFPNeonA8Domain;
321 let TwoOperandAliasConstraint = "$Dn = $Dd" in
322 def VDIVD : ADbI<0b11101, 0b00, 0, 0,
323 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
324 IIC_fpDIV64, "vdiv", ".f64\t$Dd, $Dn, $Dm",
325 [(set DPR:$Dd, (fdiv DPR:$Dn, (f64 DPR:$Dm)))]>;
327 let TwoOperandAliasConstraint = "$Sn = $Sd" in
328 def VDIVS : ASbI<0b11101, 0b00, 0, 0,
329 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
330 IIC_fpDIV32, "vdiv", ".f32\t$Sd, $Sn, $Sm",
331 [(set SPR:$Sd, (fdiv SPR:$Sn, SPR:$Sm))]>;
333 let TwoOperandAliasConstraint = "$Dn = $Dd" in
334 def VMULD : ADbI<0b11100, 0b10, 0, 0,
335 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
336 IIC_fpMUL64, "vmul", ".f64\t$Dd, $Dn, $Dm",
337 [(set DPR:$Dd, (fmul DPR:$Dn, (f64 DPR:$Dm)))]>;
339 let TwoOperandAliasConstraint = "$Sn = $Sd" in
340 def VMULS : ASbIn<0b11100, 0b10, 0, 0,
341 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
342 IIC_fpMUL32, "vmul", ".f32\t$Sd, $Sn, $Sm",
343 [(set SPR:$Sd, (fmul SPR:$Sn, SPR:$Sm))]> {
344 // Some single precision VFP instructions may be executed on both NEON and
345 // VFP pipelines on A8.
346 let D = VFPNeonA8Domain;
349 def VNMULD : ADbI<0b11100, 0b10, 1, 0,
350 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
351 IIC_fpMUL64, "vnmul", ".f64\t$Dd, $Dn, $Dm",
352 [(set DPR:$Dd, (fneg (fmul DPR:$Dn, (f64 DPR:$Dm))))]>;
354 def VNMULS : ASbI<0b11100, 0b10, 1, 0,
355 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
356 IIC_fpMUL32, "vnmul", ".f32\t$Sd, $Sn, $Sm",
357 [(set SPR:$Sd, (fneg (fmul SPR:$Sn, SPR:$Sm)))]> {
358 // Some single precision VFP instructions may be executed on both NEON and
359 // VFP pipelines on A8.
360 let D = VFPNeonA8Domain;
363 multiclass vsel_inst<string op, bits<2> opc, int CC> {
364 let DecoderNamespace = "VFPV8", PostEncoderMethod = "",
365 Uses = [CPSR], AddedComplexity = 4 in {
366 def S : ASbInp<0b11100, opc, 0,
367 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
368 NoItinerary, !strconcat("vsel", op, ".f32\t$Sd, $Sn, $Sm"),
369 [(set SPR:$Sd, (ARMcmov SPR:$Sm, SPR:$Sn, CC))]>,
370 Requires<[HasFPARMv8]>;
372 def D : ADbInp<0b11100, opc, 0,
373 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
374 NoItinerary, !strconcat("vsel", op, ".f64\t$Dd, $Dn, $Dm"),
375 [(set DPR:$Dd, (ARMcmov (f64 DPR:$Dm), (f64 DPR:$Dn), CC))]>,
376 Requires<[HasFPARMv8, HasDPVFP]>;
380 // The CC constants here match ARMCC::CondCodes.
381 defm VSELGT : vsel_inst<"gt", 0b11, 12>;
382 defm VSELGE : vsel_inst<"ge", 0b10, 10>;
383 defm VSELEQ : vsel_inst<"eq", 0b00, 0>;
384 defm VSELVS : vsel_inst<"vs", 0b01, 6>;
386 multiclass vmaxmin_inst<string op, bit opc, SDNode SD> {
387 let DecoderNamespace = "VFPV8", PostEncoderMethod = "" in {
388 def S : ASbInp<0b11101, 0b00, opc,
389 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
390 NoItinerary, !strconcat(op, ".f32\t$Sd, $Sn, $Sm"),
391 [(set SPR:$Sd, (SD SPR:$Sn, SPR:$Sm))]>,
392 Requires<[HasFPARMv8]>;
394 def D : ADbInp<0b11101, 0b00, opc,
395 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
396 NoItinerary, !strconcat(op, ".f64\t$Dd, $Dn, $Dm"),
397 [(set DPR:$Dd, (f64 (SD (f64 DPR:$Dn), (f64 DPR:$Dm))))]>,
398 Requires<[HasFPARMv8, HasDPVFP]>;
402 defm VMAXNM : vmaxmin_inst<"vmaxnm", 0, ARMvmaxnm>;
403 defm VMINNM : vmaxmin_inst<"vminnm", 1, ARMvminnm>;
405 // Match reassociated forms only if not sign dependent rounding.
406 def : Pat<(fmul (fneg DPR:$a), (f64 DPR:$b)),
407 (VNMULD DPR:$a, DPR:$b)>,
408 Requires<[NoHonorSignDependentRounding,HasDPVFP]>;
409 def : Pat<(fmul (fneg SPR:$a), SPR:$b),
410 (VNMULS SPR:$a, SPR:$b)>, Requires<[NoHonorSignDependentRounding]>;
412 // These are encoded as unary instructions.
413 let Defs = [FPSCR_NZCV] in {
414 def VCMPED : ADuI<0b11101, 0b11, 0b0100, 0b11, 0,
415 (outs), (ins DPR:$Dd, DPR:$Dm),
416 IIC_fpCMP64, "vcmpe", ".f64\t$Dd, $Dm",
417 [(arm_cmpfp DPR:$Dd, (f64 DPR:$Dm))]>;
419 def VCMPES : ASuI<0b11101, 0b11, 0b0100, 0b11, 0,
420 (outs), (ins SPR:$Sd, SPR:$Sm),
421 IIC_fpCMP32, "vcmpe", ".f32\t$Sd, $Sm",
422 [(arm_cmpfp SPR:$Sd, SPR:$Sm)]> {
423 // Some single precision VFP instructions may be executed on both NEON and
424 // VFP pipelines on A8.
425 let D = VFPNeonA8Domain;
428 // FIXME: Verify encoding after integrated assembler is working.
429 def VCMPD : ADuI<0b11101, 0b11, 0b0100, 0b01, 0,
430 (outs), (ins DPR:$Dd, DPR:$Dm),
431 IIC_fpCMP64, "vcmp", ".f64\t$Dd, $Dm",
432 [/* For disassembly only; pattern left blank */]>;
434 def VCMPS : ASuI<0b11101, 0b11, 0b0100, 0b01, 0,
435 (outs), (ins SPR:$Sd, SPR:$Sm),
436 IIC_fpCMP32, "vcmp", ".f32\t$Sd, $Sm",
437 [/* For disassembly only; pattern left blank */]> {
438 // Some single precision VFP instructions may be executed on both NEON and
439 // VFP pipelines on A8.
440 let D = VFPNeonA8Domain;
442 } // Defs = [FPSCR_NZCV]
444 //===----------------------------------------------------------------------===//
445 // FP Unary Operations.
448 def VABSD : ADuI<0b11101, 0b11, 0b0000, 0b11, 0,
449 (outs DPR:$Dd), (ins DPR:$Dm),
450 IIC_fpUNA64, "vabs", ".f64\t$Dd, $Dm",
451 [(set DPR:$Dd, (fabs (f64 DPR:$Dm)))]>;
453 def VABSS : ASuIn<0b11101, 0b11, 0b0000, 0b11, 0,
454 (outs SPR:$Sd), (ins SPR:$Sm),
455 IIC_fpUNA32, "vabs", ".f32\t$Sd, $Sm",
456 [(set SPR:$Sd, (fabs SPR:$Sm))]> {
457 // Some single precision VFP instructions may be executed on both NEON and
458 // VFP pipelines on A8.
459 let D = VFPNeonA8Domain;
462 let Defs = [FPSCR_NZCV] in {
463 def VCMPEZD : ADuI<0b11101, 0b11, 0b0101, 0b11, 0,
464 (outs), (ins DPR:$Dd),
465 IIC_fpCMP64, "vcmpe", ".f64\t$Dd, #0",
466 [(arm_cmpfp0 (f64 DPR:$Dd))]> {
467 let Inst{3-0} = 0b0000;
471 def VCMPEZS : ASuI<0b11101, 0b11, 0b0101, 0b11, 0,
472 (outs), (ins SPR:$Sd),
473 IIC_fpCMP32, "vcmpe", ".f32\t$Sd, #0",
474 [(arm_cmpfp0 SPR:$Sd)]> {
475 let Inst{3-0} = 0b0000;
478 // Some single precision VFP instructions may be executed on both NEON and
479 // VFP pipelines on A8.
480 let D = VFPNeonA8Domain;
483 // FIXME: Verify encoding after integrated assembler is working.
484 def VCMPZD : ADuI<0b11101, 0b11, 0b0101, 0b01, 0,
485 (outs), (ins DPR:$Dd),
486 IIC_fpCMP64, "vcmp", ".f64\t$Dd, #0",
487 [/* For disassembly only; pattern left blank */]> {
488 let Inst{3-0} = 0b0000;
492 def VCMPZS : ASuI<0b11101, 0b11, 0b0101, 0b01, 0,
493 (outs), (ins SPR:$Sd),
494 IIC_fpCMP32, "vcmp", ".f32\t$Sd, #0",
495 [/* For disassembly only; pattern left blank */]> {
496 let Inst{3-0} = 0b0000;
499 // Some single precision VFP instructions may be executed on both NEON and
500 // VFP pipelines on A8.
501 let D = VFPNeonA8Domain;
503 } // Defs = [FPSCR_NZCV]
505 def VCVTDS : ASuI<0b11101, 0b11, 0b0111, 0b11, 0,
506 (outs DPR:$Dd), (ins SPR:$Sm),
507 IIC_fpCVTDS, "vcvt", ".f64.f32\t$Dd, $Sm",
508 [(set DPR:$Dd, (fextend SPR:$Sm))]> {
509 // Instruction operands.
513 // Encode instruction operands.
514 let Inst{3-0} = Sm{4-1};
516 let Inst{15-12} = Dd{3-0};
517 let Inst{22} = Dd{4};
519 let Predicates = [HasVFP2, HasDPVFP];
522 // Special case encoding: bits 11-8 is 0b1011.
523 def VCVTSD : VFPAI<(outs SPR:$Sd), (ins DPR:$Dm), VFPUnaryFrm,
524 IIC_fpCVTSD, "vcvt", ".f32.f64\t$Sd, $Dm",
525 [(set SPR:$Sd, (fround DPR:$Dm))]> {
526 // Instruction operands.
530 // Encode instruction operands.
531 let Inst{3-0} = Dm{3-0};
533 let Inst{15-12} = Sd{4-1};
534 let Inst{22} = Sd{0};
536 let Inst{27-23} = 0b11101;
537 let Inst{21-16} = 0b110111;
538 let Inst{11-8} = 0b1011;
539 let Inst{7-6} = 0b11;
542 let Predicates = [HasVFP2, HasDPVFP];
545 // Between half, single and double-precision. For disassembly only.
547 // FIXME: Verify encoding after integrated assembler is working.
548 def VCVTBHS: ASuI<0b11101, 0b11, 0b0010, 0b01, 0, (outs SPR:$Sd), (ins SPR:$Sm),
549 /* FIXME */ IIC_fpCVTSH, "vcvtb", ".f32.f16\t$Sd, $Sm",
550 [/* For disassembly only; pattern left blank */]>;
552 def VCVTBSH: ASuI<0b11101, 0b11, 0b0011, 0b01, 0, (outs SPR:$Sd), (ins SPR:$Sm),
553 /* FIXME */ IIC_fpCVTHS, "vcvtb", ".f16.f32\t$Sd, $Sm",
554 [/* For disassembly only; pattern left blank */]>;
556 def VCVTTHS: ASuI<0b11101, 0b11, 0b0010, 0b11, 0, (outs SPR:$Sd), (ins SPR:$Sm),
557 /* FIXME */ IIC_fpCVTSH, "vcvtt", ".f32.f16\t$Sd, $Sm",
558 [/* For disassembly only; pattern left blank */]>;
560 def VCVTTSH: ASuI<0b11101, 0b11, 0b0011, 0b11, 0, (outs SPR:$Sd), (ins SPR:$Sm),
561 /* FIXME */ IIC_fpCVTHS, "vcvtt", ".f16.f32\t$Sd, $Sm",
562 [/* For disassembly only; pattern left blank */]>;
564 def VCVTBHD : ADuI<0b11101, 0b11, 0b0010, 0b01, 0,
565 (outs DPR:$Dd), (ins SPR:$Sm),
566 NoItinerary, "vcvtb", ".f64.f16\t$Dd, $Sm",
567 []>, Requires<[HasFPARMv8, HasDPVFP]> {
568 // Instruction operands.
571 // Encode instruction operands.
572 let Inst{3-0} = Sm{4-1};
576 def VCVTBDH : ADuI<0b11101, 0b11, 0b0011, 0b01, 0,
577 (outs SPR:$Sd), (ins DPR:$Dm),
578 NoItinerary, "vcvtb", ".f16.f64\t$Sd, $Dm",
579 []>, Requires<[HasFPARMv8, HasDPVFP]> {
580 // Instruction operands.
584 // Encode instruction operands.
585 let Inst{3-0} = Dm{3-0};
587 let Inst{15-12} = Sd{4-1};
588 let Inst{22} = Sd{0};
591 def VCVTTHD : ADuI<0b11101, 0b11, 0b0010, 0b11, 0,
592 (outs DPR:$Dd), (ins SPR:$Sm),
593 NoItinerary, "vcvtt", ".f64.f16\t$Dd, $Sm",
594 []>, Requires<[HasFPARMv8, HasDPVFP]> {
595 // Instruction operands.
598 // Encode instruction operands.
599 let Inst{3-0} = Sm{4-1};
603 def VCVTTDH : ADuI<0b11101, 0b11, 0b0011, 0b11, 0,
604 (outs SPR:$Sd), (ins DPR:$Dm),
605 NoItinerary, "vcvtt", ".f16.f64\t$Sd, $Dm",
606 []>, Requires<[HasFPARMv8, HasDPVFP]> {
607 // Instruction operands.
611 // Encode instruction operands.
612 let Inst{15-12} = Sd{4-1};
613 let Inst{22} = Sd{0};
614 let Inst{3-0} = Dm{3-0};
618 def : Pat<(fp_to_f16 SPR:$a),
619 (i32 (COPY_TO_REGCLASS (VCVTBSH SPR:$a), GPR))>;
621 def : Pat<(fp_to_f16 (f64 DPR:$a)),
622 (i32 (COPY_TO_REGCLASS (VCVTBDH DPR:$a), GPR))>;
624 def : Pat<(f16_to_fp GPR:$a),
625 (VCVTBHS (COPY_TO_REGCLASS GPR:$a, SPR))>;
627 def : Pat<(f64 (f16_to_fp GPR:$a)),
628 (VCVTBHD (COPY_TO_REGCLASS GPR:$a, SPR))>;
631 multiclass vcvt_inst<string opc, bits<2> rm> {
632 let PostEncoderMethod = "", DecoderNamespace = "VFPV8" in {
633 def SS : ASuInp<0b11101, 0b11, 0b1100, 0b11, 0,
634 (outs SPR:$Sd), (ins SPR:$Sm),
635 NoItinerary, !strconcat("vcvt", opc, ".s32.f32\t$Sd, $Sm"),
636 []>, Requires<[HasFPARMv8]> {
637 let Inst{17-16} = rm;
640 def US : ASuInp<0b11101, 0b11, 0b1100, 0b01, 0,
641 (outs SPR:$Sd), (ins SPR:$Sm),
642 NoItinerary, !strconcat("vcvt", opc, ".u32.f32\t$Sd, $Sm"),
643 []>, Requires<[HasFPARMv8]> {
644 let Inst{17-16} = rm;
647 def SD : ASuInp<0b11101, 0b11, 0b1100, 0b11, 0,
648 (outs SPR:$Sd), (ins DPR:$Dm),
649 NoItinerary, !strconcat("vcvt", opc, ".s32.f64\t$Sd, $Dm"),
650 []>, Requires<[HasFPARMv8, HasDPVFP]> {
653 let Inst{17-16} = rm;
655 // Encode instruction operands
656 let Inst{3-0} = Dm{3-0};
661 def UD : ASuInp<0b11101, 0b11, 0b1100, 0b01, 0,
662 (outs SPR:$Sd), (ins DPR:$Dm),
663 NoItinerary, !strconcat("vcvt", opc, ".u32.f64\t$Sd, $Dm"),
664 []>, Requires<[HasFPARMv8, HasDPVFP]> {
667 let Inst{17-16} = rm;
669 // Encode instruction operands
670 let Inst{3-0} = Dm{3-0};
677 defm VCVTA : vcvt_inst<"a", 0b00>;
678 defm VCVTN : vcvt_inst<"n", 0b01>;
679 defm VCVTP : vcvt_inst<"p", 0b10>;
680 defm VCVTM : vcvt_inst<"m", 0b11>;
682 def VNEGD : ADuI<0b11101, 0b11, 0b0001, 0b01, 0,
683 (outs DPR:$Dd), (ins DPR:$Dm),
684 IIC_fpUNA64, "vneg", ".f64\t$Dd, $Dm",
685 [(set DPR:$Dd, (fneg (f64 DPR:$Dm)))]>;
687 def VNEGS : ASuIn<0b11101, 0b11, 0b0001, 0b01, 0,
688 (outs SPR:$Sd), (ins SPR:$Sm),
689 IIC_fpUNA32, "vneg", ".f32\t$Sd, $Sm",
690 [(set SPR:$Sd, (fneg SPR:$Sm))]> {
691 // Some single precision VFP instructions may be executed on both NEON and
692 // VFP pipelines on A8.
693 let D = VFPNeonA8Domain;
696 multiclass vrint_inst_zrx<string opc, bit op, bit op2, SDPatternOperator node> {
697 def S : ASuI<0b11101, 0b11, 0b0110, 0b11, 0,
698 (outs SPR:$Sd), (ins SPR:$Sm),
699 NoItinerary, !strconcat("vrint", opc), ".f32\t$Sd, $Sm",
700 [(set (f32 SPR:$Sd), (node (f32 SPR:$Sm)))]>,
701 Requires<[HasFPARMv8]> {
705 def D : ADuI<0b11101, 0b11, 0b0110, 0b11, 0,
706 (outs DPR:$Dd), (ins DPR:$Dm),
707 NoItinerary, !strconcat("vrint", opc), ".f64\t$Dd, $Dm",
708 [(set (f64 DPR:$Dd), (node (f64 DPR:$Dm)))]>,
709 Requires<[HasFPARMv8, HasDPVFP]> {
714 def : InstAlias<!strconcat("vrint", opc, "$p.f32.f32\t$Sd, $Sm"),
715 (!cast<Instruction>(NAME#"S") SPR:$Sd, SPR:$Sm, pred:$p)>,
716 Requires<[HasFPARMv8]>;
717 def : InstAlias<!strconcat("vrint", opc, "$p.f64.f64\t$Dd, $Dm"),
718 (!cast<Instruction>(NAME#"D") DPR:$Dd, DPR:$Dm, pred:$p)>,
719 Requires<[HasFPARMv8,HasDPVFP]>;
722 defm VRINTZ : vrint_inst_zrx<"z", 0, 1, ftrunc>;
723 defm VRINTR : vrint_inst_zrx<"r", 0, 0, fnearbyint>;
724 defm VRINTX : vrint_inst_zrx<"x", 1, 0, frint>;
726 multiclass vrint_inst_anpm<string opc, bits<2> rm,
727 SDPatternOperator node = null_frag> {
728 let PostEncoderMethod = "", DecoderNamespace = "VFPV8" in {
729 def S : ASuInp<0b11101, 0b11, 0b1000, 0b01, 0,
730 (outs SPR:$Sd), (ins SPR:$Sm),
731 NoItinerary, !strconcat("vrint", opc, ".f32\t$Sd, $Sm"),
732 [(set (f32 SPR:$Sd), (node (f32 SPR:$Sm)))]>,
733 Requires<[HasFPARMv8]> {
734 let Inst{17-16} = rm;
736 def D : ADuInp<0b11101, 0b11, 0b1000, 0b01, 0,
737 (outs DPR:$Dd), (ins DPR:$Dm),
738 NoItinerary, !strconcat("vrint", opc, ".f64\t$Dd, $Dm"),
739 [(set (f64 DPR:$Dd), (node (f64 DPR:$Dm)))]>,
740 Requires<[HasFPARMv8, HasDPVFP]> {
741 let Inst{17-16} = rm;
745 def : InstAlias<!strconcat("vrint", opc, ".f32.f32\t$Sd, $Sm"),
746 (!cast<Instruction>(NAME#"S") SPR:$Sd, SPR:$Sm)>,
747 Requires<[HasFPARMv8]>;
748 def : InstAlias<!strconcat("vrint", opc, ".f64.f64\t$Dd, $Dm"),
749 (!cast<Instruction>(NAME#"D") DPR:$Dd, DPR:$Dm)>,
750 Requires<[HasFPARMv8,HasDPVFP]>;
753 defm VRINTA : vrint_inst_anpm<"a", 0b00, frnd>;
754 defm VRINTN : vrint_inst_anpm<"n", 0b01>;
755 defm VRINTP : vrint_inst_anpm<"p", 0b10, fceil>;
756 defm VRINTM : vrint_inst_anpm<"m", 0b11, ffloor>;
758 def VSQRTD : ADuI<0b11101, 0b11, 0b0001, 0b11, 0,
759 (outs DPR:$Dd), (ins DPR:$Dm),
760 IIC_fpSQRT64, "vsqrt", ".f64\t$Dd, $Dm",
761 [(set DPR:$Dd, (fsqrt (f64 DPR:$Dm)))]>;
763 def VSQRTS : ASuI<0b11101, 0b11, 0b0001, 0b11, 0,
764 (outs SPR:$Sd), (ins SPR:$Sm),
765 IIC_fpSQRT32, "vsqrt", ".f32\t$Sd, $Sm",
766 [(set SPR:$Sd, (fsqrt SPR:$Sm))]>;
768 let neverHasSideEffects = 1 in {
769 def VMOVD : ADuI<0b11101, 0b11, 0b0000, 0b01, 0,
770 (outs DPR:$Dd), (ins DPR:$Dm),
771 IIC_fpUNA64, "vmov", ".f64\t$Dd, $Dm", []>;
773 def VMOVS : ASuI<0b11101, 0b11, 0b0000, 0b01, 0,
774 (outs SPR:$Sd), (ins SPR:$Sm),
775 IIC_fpUNA32, "vmov", ".f32\t$Sd, $Sm", []>;
776 } // neverHasSideEffects
778 //===----------------------------------------------------------------------===//
779 // FP <-> GPR Copies. Int <-> FP Conversions.
782 def VMOVRS : AVConv2I<0b11100001, 0b1010,
783 (outs GPR:$Rt), (ins SPR:$Sn),
784 IIC_fpMOVSI, "vmov", "\t$Rt, $Sn",
785 [(set GPR:$Rt, (bitconvert SPR:$Sn))]> {
786 // Instruction operands.
790 // Encode instruction operands.
791 let Inst{19-16} = Sn{4-1};
793 let Inst{15-12} = Rt;
795 let Inst{6-5} = 0b00;
796 let Inst{3-0} = 0b0000;
798 // Some single precision VFP instructions may be executed on both NEON and VFP
800 let D = VFPNeonDomain;
803 // Bitcast i32 -> f32. NEON prefers to use VMOVDRR.
804 def VMOVSR : AVConv4I<0b11100000, 0b1010,
805 (outs SPR:$Sn), (ins GPR:$Rt),
806 IIC_fpMOVIS, "vmov", "\t$Sn, $Rt",
807 [(set SPR:$Sn, (bitconvert GPR:$Rt))]>,
808 Requires<[HasVFP2, UseVMOVSR]> {
809 // Instruction operands.
813 // Encode instruction operands.
814 let Inst{19-16} = Sn{4-1};
816 let Inst{15-12} = Rt;
818 let Inst{6-5} = 0b00;
819 let Inst{3-0} = 0b0000;
821 // Some single precision VFP instructions may be executed on both NEON and VFP
823 let D = VFPNeonDomain;
826 let neverHasSideEffects = 1 in {
827 def VMOVRRD : AVConv3I<0b11000101, 0b1011,
828 (outs GPR:$Rt, GPR:$Rt2), (ins DPR:$Dm),
829 IIC_fpMOVDI, "vmov", "\t$Rt, $Rt2, $Dm",
830 [/* FIXME: Can't write pattern for multiple result instr*/]> {
831 // Instruction operands.
836 // Encode instruction operands.
837 let Inst{3-0} = Dm{3-0};
839 let Inst{15-12} = Rt;
840 let Inst{19-16} = Rt2;
842 let Inst{7-6} = 0b00;
844 // Some single precision VFP instructions may be executed on both NEON and VFP
846 let D = VFPNeonDomain;
848 // This instruction is equivalent to
849 // $Rt = EXTRACT_SUBREG $Dm, ssub_0
850 // $Rt2 = EXTRACT_SUBREG $Dm, ssub_1
851 let isExtractSubreg = 1;
854 def VMOVRRS : AVConv3I<0b11000101, 0b1010,
855 (outs GPR:$Rt, GPR:$Rt2), (ins SPR:$src1, SPR:$src2),
856 IIC_fpMOVDI, "vmov", "\t$Rt, $Rt2, $src1, $src2",
857 [/* For disassembly only; pattern left blank */]> {
862 // Encode instruction operands.
863 let Inst{3-0} = src1{4-1};
864 let Inst{5} = src1{0};
865 let Inst{15-12} = Rt;
866 let Inst{19-16} = Rt2;
868 let Inst{7-6} = 0b00;
870 // Some single precision VFP instructions may be executed on both NEON and VFP
872 let D = VFPNeonDomain;
873 let DecoderMethod = "DecodeVMOVRRS";
875 } // neverHasSideEffects
880 def VMOVDRR : AVConv5I<0b11000100, 0b1011,
881 (outs DPR:$Dm), (ins GPR:$Rt, GPR:$Rt2),
882 IIC_fpMOVID, "vmov", "\t$Dm, $Rt, $Rt2",
883 [(set DPR:$Dm, (arm_fmdrr GPR:$Rt, GPR:$Rt2))]> {
884 // Instruction operands.
889 // Encode instruction operands.
890 let Inst{3-0} = Dm{3-0};
892 let Inst{15-12} = Rt;
893 let Inst{19-16} = Rt2;
895 let Inst{7-6} = 0b00;
897 // Some single precision VFP instructions may be executed on both NEON and VFP
899 let D = VFPNeonDomain;
901 // This instruction is equivalent to
902 // $Dm = REG_SEQUENCE $Rt, ssub_0, $Rt2, ssub_1
903 let isRegSequence = 1;
906 let neverHasSideEffects = 1 in
907 def VMOVSRR : AVConv5I<0b11000100, 0b1010,
908 (outs SPR:$dst1, SPR:$dst2), (ins GPR:$src1, GPR:$src2),
909 IIC_fpMOVID, "vmov", "\t$dst1, $dst2, $src1, $src2",
910 [/* For disassembly only; pattern left blank */]> {
911 // Instruction operands.
916 // Encode instruction operands.
917 let Inst{3-0} = dst1{4-1};
918 let Inst{5} = dst1{0};
919 let Inst{15-12} = src1;
920 let Inst{19-16} = src2;
922 let Inst{7-6} = 0b00;
924 // Some single precision VFP instructions may be executed on both NEON and VFP
926 let D = VFPNeonDomain;
928 let DecoderMethod = "DecodeVMOVSRR";
934 // FMRX: SPR system reg -> GPR
936 // FMXR: GPR -> VFP system reg
941 class AVConv1IDs_Encode<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3,
942 bits<4> opcod4, dag oops, dag iops,
943 InstrItinClass itin, string opc, string asm,
945 : AVConv1I<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm,
947 // Instruction operands.
951 // Encode instruction operands.
952 let Inst{3-0} = Sm{4-1};
954 let Inst{15-12} = Dd{3-0};
955 let Inst{22} = Dd{4};
957 let Predicates = [HasVFP2, HasDPVFP];
960 class AVConv1InSs_Encode<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3,
961 bits<4> opcod4, dag oops, dag iops,InstrItinClass itin,
962 string opc, string asm, list<dag> pattern>
963 : AVConv1In<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm,
965 // Instruction operands.
969 // Encode instruction operands.
970 let Inst{3-0} = Sm{4-1};
972 let Inst{15-12} = Sd{4-1};
973 let Inst{22} = Sd{0};
976 def VSITOD : AVConv1IDs_Encode<0b11101, 0b11, 0b1000, 0b1011,
977 (outs DPR:$Dd), (ins SPR:$Sm),
978 IIC_fpCVTID, "vcvt", ".f64.s32\t$Dd, $Sm",
979 [(set DPR:$Dd, (f64 (arm_sitof SPR:$Sm)))]> {
980 let Inst{7} = 1; // s32
983 def VSITOS : AVConv1InSs_Encode<0b11101, 0b11, 0b1000, 0b1010,
984 (outs SPR:$Sd),(ins SPR:$Sm),
985 IIC_fpCVTIS, "vcvt", ".f32.s32\t$Sd, $Sm",
986 [(set SPR:$Sd, (arm_sitof SPR:$Sm))]> {
987 let Inst{7} = 1; // s32
989 // Some single precision VFP instructions may be executed on both NEON and
990 // VFP pipelines on A8.
991 let D = VFPNeonA8Domain;
994 def VUITOD : AVConv1IDs_Encode<0b11101, 0b11, 0b1000, 0b1011,
995 (outs DPR:$Dd), (ins SPR:$Sm),
996 IIC_fpCVTID, "vcvt", ".f64.u32\t$Dd, $Sm",
997 [(set DPR:$Dd, (f64 (arm_uitof SPR:$Sm)))]> {
998 let Inst{7} = 0; // u32
1001 def VUITOS : AVConv1InSs_Encode<0b11101, 0b11, 0b1000, 0b1010,
1002 (outs SPR:$Sd), (ins SPR:$Sm),
1003 IIC_fpCVTIS, "vcvt", ".f32.u32\t$Sd, $Sm",
1004 [(set SPR:$Sd, (arm_uitof SPR:$Sm))]> {
1005 let Inst{7} = 0; // u32
1007 // Some single precision VFP instructions may be executed on both NEON and
1008 // VFP pipelines on A8.
1009 let D = VFPNeonA8Domain;
1014 class AVConv1IsD_Encode<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3,
1015 bits<4> opcod4, dag oops, dag iops,
1016 InstrItinClass itin, string opc, string asm,
1018 : AVConv1I<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm,
1020 // Instruction operands.
1024 // Encode instruction operands.
1025 let Inst{3-0} = Dm{3-0};
1026 let Inst{5} = Dm{4};
1027 let Inst{15-12} = Sd{4-1};
1028 let Inst{22} = Sd{0};
1030 let Predicates = [HasVFP2, HasDPVFP];
1033 class AVConv1InsS_Encode<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3,
1034 bits<4> opcod4, dag oops, dag iops,
1035 InstrItinClass itin, string opc, string asm,
1037 : AVConv1In<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm,
1039 // Instruction operands.
1043 // Encode instruction operands.
1044 let Inst{3-0} = Sm{4-1};
1045 let Inst{5} = Sm{0};
1046 let Inst{15-12} = Sd{4-1};
1047 let Inst{22} = Sd{0};
1050 // Always set Z bit in the instruction, i.e. "round towards zero" variants.
1051 def VTOSIZD : AVConv1IsD_Encode<0b11101, 0b11, 0b1101, 0b1011,
1052 (outs SPR:$Sd), (ins DPR:$Dm),
1053 IIC_fpCVTDI, "vcvt", ".s32.f64\t$Sd, $Dm",
1054 [(set SPR:$Sd, (arm_ftosi (f64 DPR:$Dm)))]> {
1055 let Inst{7} = 1; // Z bit
1058 def VTOSIZS : AVConv1InsS_Encode<0b11101, 0b11, 0b1101, 0b1010,
1059 (outs SPR:$Sd), (ins SPR:$Sm),
1060 IIC_fpCVTSI, "vcvt", ".s32.f32\t$Sd, $Sm",
1061 [(set SPR:$Sd, (arm_ftosi SPR:$Sm))]> {
1062 let Inst{7} = 1; // Z bit
1064 // Some single precision VFP instructions may be executed on both NEON and
1065 // VFP pipelines on A8.
1066 let D = VFPNeonA8Domain;
1069 def VTOUIZD : AVConv1IsD_Encode<0b11101, 0b11, 0b1100, 0b1011,
1070 (outs SPR:$Sd), (ins DPR:$Dm),
1071 IIC_fpCVTDI, "vcvt", ".u32.f64\t$Sd, $Dm",
1072 [(set SPR:$Sd, (arm_ftoui (f64 DPR:$Dm)))]> {
1073 let Inst{7} = 1; // Z bit
1076 def VTOUIZS : AVConv1InsS_Encode<0b11101, 0b11, 0b1100, 0b1010,
1077 (outs SPR:$Sd), (ins SPR:$Sm),
1078 IIC_fpCVTSI, "vcvt", ".u32.f32\t$Sd, $Sm",
1079 [(set SPR:$Sd, (arm_ftoui SPR:$Sm))]> {
1080 let Inst{7} = 1; // Z bit
1082 // Some single precision VFP instructions may be executed on both NEON and
1083 // VFP pipelines on A8.
1084 let D = VFPNeonA8Domain;
1087 // And the Z bit '0' variants, i.e. use the rounding mode specified by FPSCR.
1088 let Uses = [FPSCR] in {
1089 // FIXME: Verify encoding after integrated assembler is working.
1090 def VTOSIRD : AVConv1IsD_Encode<0b11101, 0b11, 0b1101, 0b1011,
1091 (outs SPR:$Sd), (ins DPR:$Dm),
1092 IIC_fpCVTDI, "vcvtr", ".s32.f64\t$Sd, $Dm",
1093 [(set SPR:$Sd, (int_arm_vcvtr (f64 DPR:$Dm)))]>{
1094 let Inst{7} = 0; // Z bit
1097 def VTOSIRS : AVConv1InsS_Encode<0b11101, 0b11, 0b1101, 0b1010,
1098 (outs SPR:$Sd), (ins SPR:$Sm),
1099 IIC_fpCVTSI, "vcvtr", ".s32.f32\t$Sd, $Sm",
1100 [(set SPR:$Sd, (int_arm_vcvtr SPR:$Sm))]> {
1101 let Inst{7} = 0; // Z bit
1104 def VTOUIRD : AVConv1IsD_Encode<0b11101, 0b11, 0b1100, 0b1011,
1105 (outs SPR:$Sd), (ins DPR:$Dm),
1106 IIC_fpCVTDI, "vcvtr", ".u32.f64\t$Sd, $Dm",
1107 [(set SPR:$Sd, (int_arm_vcvtru(f64 DPR:$Dm)))]>{
1108 let Inst{7} = 0; // Z bit
1111 def VTOUIRS : AVConv1InsS_Encode<0b11101, 0b11, 0b1100, 0b1010,
1112 (outs SPR:$Sd), (ins SPR:$Sm),
1113 IIC_fpCVTSI, "vcvtr", ".u32.f32\t$Sd, $Sm",
1114 [(set SPR:$Sd, (int_arm_vcvtru SPR:$Sm))]> {
1115 let Inst{7} = 0; // Z bit
1119 // Convert between floating-point and fixed-point
1120 // Data type for fixed-point naming convention:
1121 // S16 (U=0, sx=0) -> SH
1122 // U16 (U=1, sx=0) -> UH
1123 // S32 (U=0, sx=1) -> SL
1124 // U32 (U=1, sx=1) -> UL
1126 let Constraints = "$a = $dst" in {
1128 // FP to Fixed-Point:
1130 // Single Precision register
1131 class AVConv1XInsS_Encode<bits<5> op1, bits<2> op2, bits<4> op3, bits<4> op4,
1132 bit op5, dag oops, dag iops, InstrItinClass itin,
1133 string opc, string asm, list<dag> pattern>
1134 : AVConv1XI<op1, op2, op3, op4, op5, oops, iops, itin, opc, asm, pattern>,
1135 Sched<[WriteCvtFP]> {
1137 // if dp_operation then UInt(D:Vd) else UInt(Vd:D);
1138 let Inst{22} = dst{0};
1139 let Inst{15-12} = dst{4-1};
1142 // Double Precision register
1143 class AVConv1XInsD_Encode<bits<5> op1, bits<2> op2, bits<4> op3, bits<4> op4,
1144 bit op5, dag oops, dag iops, InstrItinClass itin,
1145 string opc, string asm, list<dag> pattern>
1146 : AVConv1XI<op1, op2, op3, op4, op5, oops, iops, itin, opc, asm, pattern>,
1147 Sched<[WriteCvtFP]> {
1149 // if dp_operation then UInt(D:Vd) else UInt(Vd:D);
1150 let Inst{22} = dst{4};
1151 let Inst{15-12} = dst{3-0};
1153 let Predicates = [HasVFP2, HasDPVFP];
1156 def VTOSHS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1110, 0b1010, 0,
1157 (outs SPR:$dst), (ins SPR:$a, fbits16:$fbits),
1158 IIC_fpCVTSI, "vcvt", ".s16.f32\t$dst, $a, $fbits", []> {
1159 // Some single precision VFP instructions may be executed on both NEON and
1160 // VFP pipelines on A8.
1161 let D = VFPNeonA8Domain;
1164 def VTOUHS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1111, 0b1010, 0,
1165 (outs SPR:$dst), (ins SPR:$a, fbits16:$fbits),
1166 IIC_fpCVTSI, "vcvt", ".u16.f32\t$dst, $a, $fbits", []> {
1167 // Some single precision VFP instructions may be executed on both NEON and
1168 // VFP pipelines on A8.
1169 let D = VFPNeonA8Domain;
1172 def VTOSLS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1110, 0b1010, 1,
1173 (outs SPR:$dst), (ins SPR:$a, fbits32:$fbits),
1174 IIC_fpCVTSI, "vcvt", ".s32.f32\t$dst, $a, $fbits", []> {
1175 // Some single precision VFP instructions may be executed on both NEON and
1176 // VFP pipelines on A8.
1177 let D = VFPNeonA8Domain;
1180 def VTOULS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1111, 0b1010, 1,
1181 (outs SPR:$dst), (ins SPR:$a, fbits32:$fbits),
1182 IIC_fpCVTSI, "vcvt", ".u32.f32\t$dst, $a, $fbits", []> {
1183 // Some single precision VFP instructions may be executed on both NEON and
1184 // VFP pipelines on A8.
1185 let D = VFPNeonA8Domain;
1188 def VTOSHD : AVConv1XInsD_Encode<0b11101, 0b11, 0b1110, 0b1011, 0,
1189 (outs DPR:$dst), (ins DPR:$a, fbits16:$fbits),
1190 IIC_fpCVTDI, "vcvt", ".s16.f64\t$dst, $a, $fbits", []>;
1192 def VTOUHD : AVConv1XInsD_Encode<0b11101, 0b11, 0b1111, 0b1011, 0,
1193 (outs DPR:$dst), (ins DPR:$a, fbits16:$fbits),
1194 IIC_fpCVTDI, "vcvt", ".u16.f64\t$dst, $a, $fbits", []>;
1196 def VTOSLD : AVConv1XInsD_Encode<0b11101, 0b11, 0b1110, 0b1011, 1,
1197 (outs DPR:$dst), (ins DPR:$a, fbits32:$fbits),
1198 IIC_fpCVTDI, "vcvt", ".s32.f64\t$dst, $a, $fbits", []>;
1200 def VTOULD : AVConv1XInsD_Encode<0b11101, 0b11, 0b1111, 0b1011, 1,
1201 (outs DPR:$dst), (ins DPR:$a, fbits32:$fbits),
1202 IIC_fpCVTDI, "vcvt", ".u32.f64\t$dst, $a, $fbits", []>;
1204 // Fixed-Point to FP:
1206 def VSHTOS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1010, 0b1010, 0,
1207 (outs SPR:$dst), (ins SPR:$a, fbits16:$fbits),
1208 IIC_fpCVTIS, "vcvt", ".f32.s16\t$dst, $a, $fbits", []> {
1209 // Some single precision VFP instructions may be executed on both NEON and
1210 // VFP pipelines on A8.
1211 let D = VFPNeonA8Domain;
1214 def VUHTOS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1011, 0b1010, 0,
1215 (outs SPR:$dst), (ins SPR:$a, fbits16:$fbits),
1216 IIC_fpCVTIS, "vcvt", ".f32.u16\t$dst, $a, $fbits", []> {
1217 // Some single precision VFP instructions may be executed on both NEON and
1218 // VFP pipelines on A8.
1219 let D = VFPNeonA8Domain;
1222 def VSLTOS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1010, 0b1010, 1,
1223 (outs SPR:$dst), (ins SPR:$a, fbits32:$fbits),
1224 IIC_fpCVTIS, "vcvt", ".f32.s32\t$dst, $a, $fbits", []> {
1225 // Some single precision VFP instructions may be executed on both NEON and
1226 // VFP pipelines on A8.
1227 let D = VFPNeonA8Domain;
1230 def VULTOS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1011, 0b1010, 1,
1231 (outs SPR:$dst), (ins SPR:$a, fbits32:$fbits),
1232 IIC_fpCVTIS, "vcvt", ".f32.u32\t$dst, $a, $fbits", []> {
1233 // Some single precision VFP instructions may be executed on both NEON and
1234 // VFP pipelines on A8.
1235 let D = VFPNeonA8Domain;
1238 def VSHTOD : AVConv1XInsD_Encode<0b11101, 0b11, 0b1010, 0b1011, 0,
1239 (outs DPR:$dst), (ins DPR:$a, fbits16:$fbits),
1240 IIC_fpCVTID, "vcvt", ".f64.s16\t$dst, $a, $fbits", []>;
1242 def VUHTOD : AVConv1XInsD_Encode<0b11101, 0b11, 0b1011, 0b1011, 0,
1243 (outs DPR:$dst), (ins DPR:$a, fbits16:$fbits),
1244 IIC_fpCVTID, "vcvt", ".f64.u16\t$dst, $a, $fbits", []>;
1246 def VSLTOD : AVConv1XInsD_Encode<0b11101, 0b11, 0b1010, 0b1011, 1,
1247 (outs DPR:$dst), (ins DPR:$a, fbits32:$fbits),
1248 IIC_fpCVTID, "vcvt", ".f64.s32\t$dst, $a, $fbits", []>;
1250 def VULTOD : AVConv1XInsD_Encode<0b11101, 0b11, 0b1011, 0b1011, 1,
1251 (outs DPR:$dst), (ins DPR:$a, fbits32:$fbits),
1252 IIC_fpCVTID, "vcvt", ".f64.u32\t$dst, $a, $fbits", []>;
1254 } // End of 'let Constraints = "$a = $dst" in'
1256 //===----------------------------------------------------------------------===//
1257 // FP Multiply-Accumulate Operations.
1260 def VMLAD : ADbI<0b11100, 0b00, 0, 0,
1261 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
1262 IIC_fpMAC64, "vmla", ".f64\t$Dd, $Dn, $Dm",
1263 [(set DPR:$Dd, (fadd_mlx (fmul_su DPR:$Dn, DPR:$Dm),
1264 (f64 DPR:$Ddin)))]>,
1265 RegConstraint<"$Ddin = $Dd">,
1266 Requires<[HasVFP2,HasDPVFP,UseFPVMLx,DontUseFusedMAC]>;
1268 def VMLAS : ASbIn<0b11100, 0b00, 0, 0,
1269 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
1270 IIC_fpMAC32, "vmla", ".f32\t$Sd, $Sn, $Sm",
1271 [(set SPR:$Sd, (fadd_mlx (fmul_su SPR:$Sn, SPR:$Sm),
1273 RegConstraint<"$Sdin = $Sd">,
1274 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx,DontUseFusedMAC]> {
1275 // Some single precision VFP instructions may be executed on both NEON and
1276 // VFP pipelines on A8.
1277 let D = VFPNeonA8Domain;
1280 def : Pat<(fadd_mlx DPR:$dstin, (fmul_su DPR:$a, (f64 DPR:$b))),
1281 (VMLAD DPR:$dstin, DPR:$a, DPR:$b)>,
1282 Requires<[HasVFP2,HasDPVFP,UseFPVMLx,DontUseFusedMAC]>;
1283 def : Pat<(fadd_mlx SPR:$dstin, (fmul_su SPR:$a, SPR:$b)),
1284 (VMLAS SPR:$dstin, SPR:$a, SPR:$b)>,
1285 Requires<[HasVFP2,DontUseNEONForFP, UseFPVMLx,DontUseFusedMAC]>;
1287 def VMLSD : ADbI<0b11100, 0b00, 1, 0,
1288 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
1289 IIC_fpMAC64, "vmls", ".f64\t$Dd, $Dn, $Dm",
1290 [(set DPR:$Dd, (fadd_mlx (fneg (fmul_su DPR:$Dn,DPR:$Dm)),
1291 (f64 DPR:$Ddin)))]>,
1292 RegConstraint<"$Ddin = $Dd">,
1293 Requires<[HasVFP2,HasDPVFP,UseFPVMLx,DontUseFusedMAC]>;
1295 def VMLSS : ASbIn<0b11100, 0b00, 1, 0,
1296 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
1297 IIC_fpMAC32, "vmls", ".f32\t$Sd, $Sn, $Sm",
1298 [(set SPR:$Sd, (fadd_mlx (fneg (fmul_su SPR:$Sn, SPR:$Sm)),
1300 RegConstraint<"$Sdin = $Sd">,
1301 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx,DontUseFusedMAC]> {
1302 // Some single precision VFP instructions may be executed on both NEON and
1303 // VFP pipelines on A8.
1304 let D = VFPNeonA8Domain;
1307 def : Pat<(fsub_mlx DPR:$dstin, (fmul_su DPR:$a, (f64 DPR:$b))),
1308 (VMLSD DPR:$dstin, DPR:$a, DPR:$b)>,
1309 Requires<[HasVFP2,HasDPVFP,UseFPVMLx,DontUseFusedMAC]>;
1310 def : Pat<(fsub_mlx SPR:$dstin, (fmul_su SPR:$a, SPR:$b)),
1311 (VMLSS SPR:$dstin, SPR:$a, SPR:$b)>,
1312 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx,DontUseFusedMAC]>;
1314 def VNMLAD : ADbI<0b11100, 0b01, 1, 0,
1315 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
1316 IIC_fpMAC64, "vnmla", ".f64\t$Dd, $Dn, $Dm",
1317 [(set DPR:$Dd,(fsub_mlx (fneg (fmul_su DPR:$Dn,DPR:$Dm)),
1318 (f64 DPR:$Ddin)))]>,
1319 RegConstraint<"$Ddin = $Dd">,
1320 Requires<[HasVFP2,HasDPVFP,UseFPVMLx,DontUseFusedMAC]>;
1322 def VNMLAS : ASbI<0b11100, 0b01, 1, 0,
1323 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
1324 IIC_fpMAC32, "vnmla", ".f32\t$Sd, $Sn, $Sm",
1325 [(set SPR:$Sd, (fsub_mlx (fneg (fmul_su SPR:$Sn, SPR:$Sm)),
1327 RegConstraint<"$Sdin = $Sd">,
1328 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx,DontUseFusedMAC]> {
1329 // Some single precision VFP instructions may be executed on both NEON and
1330 // VFP pipelines on A8.
1331 let D = VFPNeonA8Domain;
1334 def : Pat<(fsub_mlx (fneg (fmul_su DPR:$a, (f64 DPR:$b))), DPR:$dstin),
1335 (VNMLAD DPR:$dstin, DPR:$a, DPR:$b)>,
1336 Requires<[HasVFP2,HasDPVFP,UseFPVMLx,DontUseFusedMAC]>;
1337 def : Pat<(fsub_mlx (fneg (fmul_su SPR:$a, SPR:$b)), SPR:$dstin),
1338 (VNMLAS SPR:$dstin, SPR:$a, SPR:$b)>,
1339 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx,DontUseFusedMAC]>;
1341 def VNMLSD : ADbI<0b11100, 0b01, 0, 0,
1342 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
1343 IIC_fpMAC64, "vnmls", ".f64\t$Dd, $Dn, $Dm",
1344 [(set DPR:$Dd, (fsub_mlx (fmul_su DPR:$Dn, DPR:$Dm),
1345 (f64 DPR:$Ddin)))]>,
1346 RegConstraint<"$Ddin = $Dd">,
1347 Requires<[HasVFP2,HasDPVFP,UseFPVMLx,DontUseFusedMAC]>;
1349 def VNMLSS : ASbI<0b11100, 0b01, 0, 0,
1350 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
1351 IIC_fpMAC32, "vnmls", ".f32\t$Sd, $Sn, $Sm",
1352 [(set SPR:$Sd, (fsub_mlx (fmul_su SPR:$Sn, SPR:$Sm), SPR:$Sdin))]>,
1353 RegConstraint<"$Sdin = $Sd">,
1354 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx,DontUseFusedMAC]> {
1355 // Some single precision VFP instructions may be executed on both NEON and
1356 // VFP pipelines on A8.
1357 let D = VFPNeonA8Domain;
1360 def : Pat<(fsub_mlx (fmul_su DPR:$a, (f64 DPR:$b)), DPR:$dstin),
1361 (VNMLSD DPR:$dstin, DPR:$a, DPR:$b)>,
1362 Requires<[HasVFP2,HasDPVFP,UseFPVMLx,DontUseFusedMAC]>;
1363 def : Pat<(fsub_mlx (fmul_su SPR:$a, SPR:$b), SPR:$dstin),
1364 (VNMLSS SPR:$dstin, SPR:$a, SPR:$b)>,
1365 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx,DontUseFusedMAC]>;
1367 //===----------------------------------------------------------------------===//
1368 // Fused FP Multiply-Accumulate Operations.
1370 def VFMAD : ADbI<0b11101, 0b10, 0, 0,
1371 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
1372 IIC_fpFMAC64, "vfma", ".f64\t$Dd, $Dn, $Dm",
1373 [(set DPR:$Dd, (fadd_mlx (fmul_su DPR:$Dn, DPR:$Dm),
1374 (f64 DPR:$Ddin)))]>,
1375 RegConstraint<"$Ddin = $Dd">,
1376 Requires<[HasVFP4,HasDPVFP,UseFusedMAC]>;
1378 def VFMAS : ASbIn<0b11101, 0b10, 0, 0,
1379 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
1380 IIC_fpFMAC32, "vfma", ".f32\t$Sd, $Sn, $Sm",
1381 [(set SPR:$Sd, (fadd_mlx (fmul_su SPR:$Sn, SPR:$Sm),
1383 RegConstraint<"$Sdin = $Sd">,
1384 Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]> {
1385 // Some single precision VFP instructions may be executed on both NEON and
1389 def : Pat<(fadd_mlx DPR:$dstin, (fmul_su DPR:$a, (f64 DPR:$b))),
1390 (VFMAD DPR:$dstin, DPR:$a, DPR:$b)>,
1391 Requires<[HasVFP4,HasDPVFP,UseFusedMAC]>;
1392 def : Pat<(fadd_mlx SPR:$dstin, (fmul_su SPR:$a, SPR:$b)),
1393 (VFMAS SPR:$dstin, SPR:$a, SPR:$b)>,
1394 Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]>;
1396 // Match @llvm.fma.* intrinsics
1397 // (fma x, y, z) -> (vfms z, x, y)
1398 def : Pat<(f64 (fma DPR:$Dn, DPR:$Dm, DPR:$Ddin)),
1399 (VFMAD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>,
1400 Requires<[HasVFP4,HasDPVFP]>;
1401 def : Pat<(f32 (fma SPR:$Sn, SPR:$Sm, SPR:$Sdin)),
1402 (VFMAS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
1403 Requires<[HasVFP4]>;
1405 def VFMSD : ADbI<0b11101, 0b10, 1, 0,
1406 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
1407 IIC_fpFMAC64, "vfms", ".f64\t$Dd, $Dn, $Dm",
1408 [(set DPR:$Dd, (fadd_mlx (fneg (fmul_su DPR:$Dn,DPR:$Dm)),
1409 (f64 DPR:$Ddin)))]>,
1410 RegConstraint<"$Ddin = $Dd">,
1411 Requires<[HasVFP4,HasDPVFP,UseFusedMAC]>;
1413 def VFMSS : ASbIn<0b11101, 0b10, 1, 0,
1414 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
1415 IIC_fpFMAC32, "vfms", ".f32\t$Sd, $Sn, $Sm",
1416 [(set SPR:$Sd, (fadd_mlx (fneg (fmul_su SPR:$Sn, SPR:$Sm)),
1418 RegConstraint<"$Sdin = $Sd">,
1419 Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]> {
1420 // Some single precision VFP instructions may be executed on both NEON and
1424 def : Pat<(fsub_mlx DPR:$dstin, (fmul_su DPR:$a, (f64 DPR:$b))),
1425 (VFMSD DPR:$dstin, DPR:$a, DPR:$b)>,
1426 Requires<[HasVFP4,HasDPVFP,UseFusedMAC]>;
1427 def : Pat<(fsub_mlx SPR:$dstin, (fmul_su SPR:$a, SPR:$b)),
1428 (VFMSS SPR:$dstin, SPR:$a, SPR:$b)>,
1429 Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]>;
1431 // Match @llvm.fma.* intrinsics
1432 // (fma (fneg x), y, z) -> (vfms z, x, y)
1433 def : Pat<(f64 (fma (fneg DPR:$Dn), DPR:$Dm, DPR:$Ddin)),
1434 (VFMSD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>,
1435 Requires<[HasVFP4,HasDPVFP]>;
1436 def : Pat<(f32 (fma (fneg SPR:$Sn), SPR:$Sm, SPR:$Sdin)),
1437 (VFMSS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
1438 Requires<[HasVFP4]>;
1439 // (fma x, (fneg y), z) -> (vfms z, x, y)
1440 def : Pat<(f64 (fma DPR:$Dn, (fneg DPR:$Dm), DPR:$Ddin)),
1441 (VFMSD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>,
1442 Requires<[HasVFP4,HasDPVFP]>;
1443 def : Pat<(f32 (fma SPR:$Sn, (fneg SPR:$Sm), SPR:$Sdin)),
1444 (VFMSS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
1445 Requires<[HasVFP4]>;
1447 def VFNMAD : ADbI<0b11101, 0b01, 1, 0,
1448 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
1449 IIC_fpFMAC64, "vfnma", ".f64\t$Dd, $Dn, $Dm",
1450 [(set DPR:$Dd,(fsub_mlx (fneg (fmul_su DPR:$Dn,DPR:$Dm)),
1451 (f64 DPR:$Ddin)))]>,
1452 RegConstraint<"$Ddin = $Dd">,
1453 Requires<[HasVFP4,HasDPVFP,UseFusedMAC]>;
1455 def VFNMAS : ASbI<0b11101, 0b01, 1, 0,
1456 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
1457 IIC_fpFMAC32, "vfnma", ".f32\t$Sd, $Sn, $Sm",
1458 [(set SPR:$Sd, (fsub_mlx (fneg (fmul_su SPR:$Sn, SPR:$Sm)),
1460 RegConstraint<"$Sdin = $Sd">,
1461 Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]> {
1462 // Some single precision VFP instructions may be executed on both NEON and
1466 def : Pat<(fsub_mlx (fneg (fmul_su DPR:$a, (f64 DPR:$b))), DPR:$dstin),
1467 (VFNMAD DPR:$dstin, DPR:$a, DPR:$b)>,
1468 Requires<[HasVFP4,HasDPVFP,UseFusedMAC]>;
1469 def : Pat<(fsub_mlx (fneg (fmul_su SPR:$a, SPR:$b)), SPR:$dstin),
1470 (VFNMAS SPR:$dstin, SPR:$a, SPR:$b)>,
1471 Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]>;
1473 // Match @llvm.fma.* intrinsics
1474 // (fneg (fma x, y, z)) -> (vfnma z, x, y)
1475 def : Pat<(fneg (fma (f64 DPR:$Dn), (f64 DPR:$Dm), (f64 DPR:$Ddin))),
1476 (VFNMAD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>,
1477 Requires<[HasVFP4,HasDPVFP]>;
1478 def : Pat<(fneg (fma (f32 SPR:$Sn), (f32 SPR:$Sm), (f32 SPR:$Sdin))),
1479 (VFNMAS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
1480 Requires<[HasVFP4]>;
1481 // (fma (fneg x), y, (fneg z)) -> (vfnma z, x, y)
1482 def : Pat<(f64 (fma (fneg DPR:$Dn), DPR:$Dm, (fneg DPR:$Ddin))),
1483 (VFNMAD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>,
1484 Requires<[HasVFP4,HasDPVFP]>;
1485 def : Pat<(f32 (fma (fneg SPR:$Sn), SPR:$Sm, (fneg SPR:$Sdin))),
1486 (VFNMAS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
1487 Requires<[HasVFP4]>;
1489 def VFNMSD : ADbI<0b11101, 0b01, 0, 0,
1490 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
1491 IIC_fpFMAC64, "vfnms", ".f64\t$Dd, $Dn, $Dm",
1492 [(set DPR:$Dd, (fsub_mlx (fmul_su DPR:$Dn, DPR:$Dm),
1493 (f64 DPR:$Ddin)))]>,
1494 RegConstraint<"$Ddin = $Dd">,
1495 Requires<[HasVFP4,HasDPVFP,UseFusedMAC]>;
1497 def VFNMSS : ASbI<0b11101, 0b01, 0, 0,
1498 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
1499 IIC_fpFMAC32, "vfnms", ".f32\t$Sd, $Sn, $Sm",
1500 [(set SPR:$Sd, (fsub_mlx (fmul_su SPR:$Sn, SPR:$Sm), SPR:$Sdin))]>,
1501 RegConstraint<"$Sdin = $Sd">,
1502 Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]> {
1503 // Some single precision VFP instructions may be executed on both NEON and
1507 def : Pat<(fsub_mlx (fmul_su DPR:$a, (f64 DPR:$b)), DPR:$dstin),
1508 (VFNMSD DPR:$dstin, DPR:$a, DPR:$b)>,
1509 Requires<[HasVFP4,HasDPVFP,UseFusedMAC]>;
1510 def : Pat<(fsub_mlx (fmul_su SPR:$a, SPR:$b), SPR:$dstin),
1511 (VFNMSS SPR:$dstin, SPR:$a, SPR:$b)>,
1512 Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]>;
1514 // Match @llvm.fma.* intrinsics
1516 // (fma x, y, (fneg z)) -> (vfnms z, x, y))
1517 def : Pat<(f64 (fma DPR:$Dn, DPR:$Dm, (fneg DPR:$Ddin))),
1518 (VFNMSD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>,
1519 Requires<[HasVFP4,HasDPVFP]>;
1520 def : Pat<(f32 (fma SPR:$Sn, SPR:$Sm, (fneg SPR:$Sdin))),
1521 (VFNMSS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
1522 Requires<[HasVFP4]>;
1523 // (fneg (fma (fneg x), y, z)) -> (vfnms z, x, y)
1524 def : Pat<(fneg (f64 (fma (fneg DPR:$Dn), DPR:$Dm, DPR:$Ddin))),
1525 (VFNMSD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>,
1526 Requires<[HasVFP4,HasDPVFP]>;
1527 def : Pat<(fneg (f32 (fma (fneg SPR:$Sn), SPR:$Sm, SPR:$Sdin))),
1528 (VFNMSS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
1529 Requires<[HasVFP4]>;
1530 // (fneg (fma x, (fneg y), z) -> (vfnms z, x, y)
1531 def : Pat<(fneg (f64 (fma DPR:$Dn, (fneg DPR:$Dm), DPR:$Ddin))),
1532 (VFNMSD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>,
1533 Requires<[HasVFP4,HasDPVFP]>;
1534 def : Pat<(fneg (f32 (fma SPR:$Sn, (fneg SPR:$Sm), SPR:$Sdin))),
1535 (VFNMSS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
1536 Requires<[HasVFP4]>;
1538 //===----------------------------------------------------------------------===//
1539 // FP Conditional moves.
1542 let neverHasSideEffects = 1 in {
1543 def VMOVDcc : PseudoInst<(outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm, cmovpred:$p),
1545 [(set (f64 DPR:$Dd),
1546 (ARMcmov DPR:$Dn, DPR:$Dm, cmovpred:$p))]>,
1547 RegConstraint<"$Dn = $Dd">, Requires<[HasVFP2,HasDPVFP]>;
1549 def VMOVScc : PseudoInst<(outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm, cmovpred:$p),
1551 [(set (f32 SPR:$Sd),
1552 (ARMcmov SPR:$Sn, SPR:$Sm, cmovpred:$p))]>,
1553 RegConstraint<"$Sn = $Sd">, Requires<[HasVFP2]>;
1554 } // neverHasSideEffects
1556 //===----------------------------------------------------------------------===//
1557 // Move from VFP System Register to ARM core register.
1560 class MovFromVFP<bits<4> opc19_16, dag oops, dag iops, string opc, string asm,
1562 VFPAI<oops, iops, VFPMiscFrm, IIC_fpSTAT, opc, asm, pattern> {
1564 // Instruction operand.
1567 let Inst{27-20} = 0b11101111;
1568 let Inst{19-16} = opc19_16;
1569 let Inst{15-12} = Rt;
1570 let Inst{11-8} = 0b1010;
1572 let Inst{6-5} = 0b00;
1574 let Inst{3-0} = 0b0000;
1577 // APSR is the application level alias of CPSR. This FPSCR N, Z, C, V flags
1579 let Defs = [CPSR], Uses = [FPSCR_NZCV], Rt = 0b1111 /* apsr_nzcv */ in
1580 def FMSTAT : MovFromVFP<0b0001 /* fpscr */, (outs), (ins),
1581 "vmrs", "\tAPSR_nzcv, fpscr", [(arm_fmstat)]>;
1583 // Application level FPSCR -> GPR
1584 let hasSideEffects = 1, Uses = [FPSCR] in
1585 def VMRS : MovFromVFP<0b0001 /* fpscr */, (outs GPR:$Rt), (ins),
1586 "vmrs", "\t$Rt, fpscr",
1587 [(set GPR:$Rt, (int_arm_get_fpscr))]>;
1589 // System level FPEXC, FPSID -> GPR
1590 let Uses = [FPSCR] in {
1591 def VMRS_FPEXC : MovFromVFP<0b1000 /* fpexc */, (outs GPR:$Rt), (ins),
1592 "vmrs", "\t$Rt, fpexc", []>;
1593 def VMRS_FPSID : MovFromVFP<0b0000 /* fpsid */, (outs GPR:$Rt), (ins),
1594 "vmrs", "\t$Rt, fpsid", []>;
1595 def VMRS_MVFR0 : MovFromVFP<0b0111 /* mvfr0 */, (outs GPR:$Rt), (ins),
1596 "vmrs", "\t$Rt, mvfr0", []>;
1597 def VMRS_MVFR1 : MovFromVFP<0b0110 /* mvfr1 */, (outs GPR:$Rt), (ins),
1598 "vmrs", "\t$Rt, mvfr1", []>;
1599 def VMRS_MVFR2 : MovFromVFP<0b0101 /* mvfr2 */, (outs GPR:$Rt), (ins),
1600 "vmrs", "\t$Rt, mvfr2", []>, Requires<[HasFPARMv8]>;
1601 def VMRS_FPINST : MovFromVFP<0b1001 /* fpinst */, (outs GPR:$Rt), (ins),
1602 "vmrs", "\t$Rt, fpinst", []>;
1603 def VMRS_FPINST2 : MovFromVFP<0b1010 /* fpinst2 */, (outs GPR:$Rt), (ins),
1604 "vmrs", "\t$Rt, fpinst2", []>;
1607 //===----------------------------------------------------------------------===//
1608 // Move from ARM core register to VFP System Register.
1611 class MovToVFP<bits<4> opc19_16, dag oops, dag iops, string opc, string asm,
1613 VFPAI<oops, iops, VFPMiscFrm, IIC_fpSTAT, opc, asm, pattern> {
1615 // Instruction operand.
1618 // Encode instruction operand.
1619 let Inst{15-12} = src;
1621 let Inst{27-20} = 0b11101110;
1622 let Inst{19-16} = opc19_16;
1623 let Inst{11-8} = 0b1010;
1628 let Defs = [FPSCR] in {
1629 // Application level GPR -> FPSCR
1630 def VMSR : MovToVFP<0b0001 /* fpscr */, (outs), (ins GPR:$src),
1631 "vmsr", "\tfpscr, $src", [(int_arm_set_fpscr GPR:$src)]>;
1632 // System level GPR -> FPEXC
1633 def VMSR_FPEXC : MovToVFP<0b1000 /* fpexc */, (outs), (ins GPR:$src),
1634 "vmsr", "\tfpexc, $src", []>;
1635 // System level GPR -> FPSID
1636 def VMSR_FPSID : MovToVFP<0b0000 /* fpsid */, (outs), (ins GPR:$src),
1637 "vmsr", "\tfpsid, $src", []>;
1639 def VMSR_FPINST : MovToVFP<0b1001 /* fpinst */, (outs), (ins GPR:$src),
1640 "vmsr", "\tfpinst, $src", []>;
1641 def VMSR_FPINST2 : MovToVFP<0b1010 /* fpinst2 */, (outs), (ins GPR:$src),
1642 "vmsr", "\tfpinst2, $src", []>;
1645 //===----------------------------------------------------------------------===//
1649 // Materialize FP immediates. VFP3 only.
1650 let isReMaterializable = 1 in {
1651 def FCONSTD : VFPAI<(outs DPR:$Dd), (ins vfp_f64imm:$imm),
1652 VFPMiscFrm, IIC_fpUNA64,
1653 "vmov", ".f64\t$Dd, $imm",
1654 [(set DPR:$Dd, vfp_f64imm:$imm)]>,
1655 Requires<[HasVFP3,HasDPVFP]> {
1659 let Inst{27-23} = 0b11101;
1660 let Inst{22} = Dd{4};
1661 let Inst{21-20} = 0b11;
1662 let Inst{19-16} = imm{7-4};
1663 let Inst{15-12} = Dd{3-0};
1664 let Inst{11-9} = 0b101;
1665 let Inst{8} = 1; // Double precision.
1666 let Inst{7-4} = 0b0000;
1667 let Inst{3-0} = imm{3-0};
1670 def FCONSTS : VFPAI<(outs SPR:$Sd), (ins vfp_f32imm:$imm),
1671 VFPMiscFrm, IIC_fpUNA32,
1672 "vmov", ".f32\t$Sd, $imm",
1673 [(set SPR:$Sd, vfp_f32imm:$imm)]>, Requires<[HasVFP3]> {
1677 let Inst{27-23} = 0b11101;
1678 let Inst{22} = Sd{0};
1679 let Inst{21-20} = 0b11;
1680 let Inst{19-16} = imm{7-4};
1681 let Inst{15-12} = Sd{4-1};
1682 let Inst{11-9} = 0b101;
1683 let Inst{8} = 0; // Single precision.
1684 let Inst{7-4} = 0b0000;
1685 let Inst{3-0} = imm{3-0};
1689 //===----------------------------------------------------------------------===//
1690 // Assembler aliases.
1692 // A few mnemonic aliases for pre-unifixed syntax. We don't guarantee to
1693 // support them all, but supporting at least some of the basics is
1694 // good to be friendly.
1695 def : VFP2MnemonicAlias<"flds", "vldr">;
1696 def : VFP2MnemonicAlias<"fldd", "vldr">;
1697 def : VFP2MnemonicAlias<"fmrs", "vmov">;
1698 def : VFP2MnemonicAlias<"fmsr", "vmov">;
1699 def : VFP2MnemonicAlias<"fsqrts", "vsqrt">;
1700 def : VFP2MnemonicAlias<"fsqrtd", "vsqrt">;
1701 def : VFP2MnemonicAlias<"fadds", "vadd.f32">;
1702 def : VFP2MnemonicAlias<"faddd", "vadd.f64">;
1703 def : VFP2MnemonicAlias<"fmrdd", "vmov">;
1704 def : VFP2MnemonicAlias<"fmrds", "vmov">;
1705 def : VFP2MnemonicAlias<"fmrrd", "vmov">;
1706 def : VFP2MnemonicAlias<"fmdrr", "vmov">;
1707 def : VFP2MnemonicAlias<"fmuls", "vmul.f32">;
1708 def : VFP2MnemonicAlias<"fmuld", "vmul.f64">;
1709 def : VFP2MnemonicAlias<"fnegs", "vneg.f32">;
1710 def : VFP2MnemonicAlias<"fnegd", "vneg.f64">;
1711 def : VFP2MnemonicAlias<"ftosizd", "vcvt.s32.f64">;
1712 def : VFP2MnemonicAlias<"ftosid", "vcvtr.s32.f64">;
1713 def : VFP2MnemonicAlias<"ftosizs", "vcvt.s32.f32">;
1714 def : VFP2MnemonicAlias<"ftosis", "vcvtr.s32.f32">;
1715 def : VFP2MnemonicAlias<"ftouizd", "vcvt.u32.f64">;
1716 def : VFP2MnemonicAlias<"ftouid", "vcvtr.u32.f64">;
1717 def : VFP2MnemonicAlias<"ftouizs", "vcvt.u32.f32">;
1718 def : VFP2MnemonicAlias<"ftouis", "vcvtr.u32.f32">;
1719 def : VFP2MnemonicAlias<"fsitod", "vcvt.f64.s32">;
1720 def : VFP2MnemonicAlias<"fsitos", "vcvt.f32.s32">;
1721 def : VFP2MnemonicAlias<"fuitod", "vcvt.f64.u32">;
1722 def : VFP2MnemonicAlias<"fuitos", "vcvt.f32.u32">;
1723 def : VFP2MnemonicAlias<"fsts", "vstr">;
1724 def : VFP2MnemonicAlias<"fstd", "vstr">;
1725 def : VFP2MnemonicAlias<"fmacd", "vmla.f64">;
1726 def : VFP2MnemonicAlias<"fmacs", "vmla.f32">;
1727 def : VFP2MnemonicAlias<"fcpys", "vmov.f32">;
1728 def : VFP2MnemonicAlias<"fcpyd", "vmov.f64">;
1729 def : VFP2MnemonicAlias<"fcmps", "vcmp.f32">;
1730 def : VFP2MnemonicAlias<"fcmpd", "vcmp.f64">;
1731 def : VFP2MnemonicAlias<"fdivs", "vdiv.f32">;
1732 def : VFP2MnemonicAlias<"fdivd", "vdiv.f64">;
1733 def : VFP2MnemonicAlias<"fmrx", "vmrs">;
1734 def : VFP2MnemonicAlias<"fmxr", "vmsr">;
1736 // Be friendly and accept the old form of zero-compare
1737 def : VFP2DPInstAlias<"fcmpzd${p} $val", (VCMPZD DPR:$val, pred:$p)>;
1738 def : VFP2InstAlias<"fcmpzs${p} $val", (VCMPZS SPR:$val, pred:$p)>;
1741 def : VFP2InstAlias<"fmstat${p}", (FMSTAT pred:$p)>;
1742 def : VFP2InstAlias<"fadds${p} $Sd, $Sn, $Sm",
1743 (VADDS SPR:$Sd, SPR:$Sn, SPR:$Sm, pred:$p)>;
1744 def : VFP2DPInstAlias<"faddd${p} $Dd, $Dn, $Dm",
1745 (VADDD DPR:$Dd, DPR:$Dn, DPR:$Dm, pred:$p)>;
1746 def : VFP2InstAlias<"fsubs${p} $Sd, $Sn, $Sm",
1747 (VSUBS SPR:$Sd, SPR:$Sn, SPR:$Sm, pred:$p)>;
1748 def : VFP2DPInstAlias<"fsubd${p} $Dd, $Dn, $Dm",
1749 (VSUBD DPR:$Dd, DPR:$Dn, DPR:$Dm, pred:$p)>;
1751 // No need for the size suffix on VSQRT. It's implied by the register classes.
1752 def : VFP2InstAlias<"vsqrt${p} $Sd, $Sm", (VSQRTS SPR:$Sd, SPR:$Sm, pred:$p)>;
1753 def : VFP2DPInstAlias<"vsqrt${p} $Dd, $Dm", (VSQRTD DPR:$Dd, DPR:$Dm, pred:$p)>;
1755 // VLDR/VSTR accept an optional type suffix.
1756 def : VFP2InstAlias<"vldr${p}.32 $Sd, $addr",
1757 (VLDRS SPR:$Sd, addrmode5:$addr, pred:$p)>;
1758 def : VFP2InstAlias<"vstr${p}.32 $Sd, $addr",
1759 (VSTRS SPR:$Sd, addrmode5:$addr, pred:$p)>;
1760 def : VFP2InstAlias<"vldr${p}.64 $Dd, $addr",
1761 (VLDRD DPR:$Dd, addrmode5:$addr, pred:$p)>;
1762 def : VFP2InstAlias<"vstr${p}.64 $Dd, $addr",
1763 (VSTRD DPR:$Dd, addrmode5:$addr, pred:$p)>;
1765 // VMOV can accept optional 32-bit or less data type suffix suffix.
1766 def : VFP2InstAlias<"vmov${p}.8 $Rt, $Sn",
1767 (VMOVRS GPR:$Rt, SPR:$Sn, pred:$p)>;
1768 def : VFP2InstAlias<"vmov${p}.16 $Rt, $Sn",
1769 (VMOVRS GPR:$Rt, SPR:$Sn, pred:$p)>;
1770 def : VFP2InstAlias<"vmov${p}.32 $Rt, $Sn",
1771 (VMOVRS GPR:$Rt, SPR:$Sn, pred:$p)>;
1772 def : VFP2InstAlias<"vmov${p}.8 $Sn, $Rt",
1773 (VMOVSR SPR:$Sn, GPR:$Rt, pred:$p)>;
1774 def : VFP2InstAlias<"vmov${p}.16 $Sn, $Rt",
1775 (VMOVSR SPR:$Sn, GPR:$Rt, pred:$p)>;
1776 def : VFP2InstAlias<"vmov${p}.32 $Sn, $Rt",
1777 (VMOVSR SPR:$Sn, GPR:$Rt, pred:$p)>;
1779 def : VFP2InstAlias<"vmov${p}.f64 $Rt, $Rt2, $Dn",
1780 (VMOVRRD GPR:$Rt, GPR:$Rt2, DPR:$Dn, pred:$p)>;
1781 def : VFP2InstAlias<"vmov${p}.f64 $Dn, $Rt, $Rt2",
1782 (VMOVDRR DPR:$Dn, GPR:$Rt, GPR:$Rt2, pred:$p)>;
1784 // VMOVS doesn't need the .f32 to disambiguate from the NEON encoding the way
1786 def : VFP2InstAlias<"vmov${p} $Sd, $Sm",
1787 (VMOVS SPR:$Sd, SPR:$Sm, pred:$p)>;
1789 // FCONSTD/FCONSTS alias for vmov.f64/vmov.f32
1790 // These aliases provide added functionality over vmov.f instructions by
1791 // allowing users to write assembly containing encoded floating point constants
1792 // (e.g. #0x70 vs #1.0). Without these alises there is no way for the
1793 // assembler to accept encoded fp constants (but the equivalent fp-literal is
1794 // accepted directly by vmovf).
1795 def : VFP3InstAlias<"fconstd${p} $Dd, $val",
1796 (FCONSTD DPR:$Dd, vfp_f64imm:$val, pred:$p)>;
1797 def : VFP3InstAlias<"fconsts${p} $Sd, $val",
1798 (FCONSTS SPR:$Sd, vfp_f32imm:$val, pred:$p)>;