1 //===- ARMInstrVFP.td - VFP support for ARM ----------------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM VFP instruction set.
12 //===----------------------------------------------------------------------===//
14 def SDT_FTOI : SDTypeProfile<1, 1, [SDTCisVT<0, f32>, SDTCisFP<1>]>;
15 def SDT_ITOF : SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisVT<1, f32>]>;
16 def SDT_CMPFP0 : SDTypeProfile<0, 1, [SDTCisFP<0>]>;
17 def SDT_VMOVDRR : SDTypeProfile<1, 2, [SDTCisVT<0, f64>, SDTCisVT<1, i32>,
20 def arm_ftoui : SDNode<"ARMISD::FTOUI", SDT_FTOI>;
21 def arm_ftosi : SDNode<"ARMISD::FTOSI", SDT_FTOI>;
22 def arm_sitof : SDNode<"ARMISD::SITOF", SDT_ITOF>;
23 def arm_uitof : SDNode<"ARMISD::UITOF", SDT_ITOF>;
24 def arm_fmstat : SDNode<"ARMISD::FMSTAT", SDTNone, [SDNPInFlag, SDNPOutFlag]>;
25 def arm_cmpfp : SDNode<"ARMISD::CMPFP", SDT_ARMCmp, [SDNPOutFlag]>;
26 def arm_cmpfp0 : SDNode<"ARMISD::CMPFPw0", SDT_CMPFP0, [SDNPOutFlag]>;
27 def arm_fmdrr : SDNode<"ARMISD::VMOVDRR", SDT_VMOVDRR>;
30 //===----------------------------------------------------------------------===//
31 // Operand Definitions.
34 def vfp_f32imm : Operand<f32>,
35 PatLeaf<(f32 fpimm), [{
36 return ARM::getVFPf32Imm(N->getValueAPF()) != -1;
38 let PrintMethod = "printVFPf32ImmOperand";
41 def vfp_f64imm : Operand<f64>,
42 PatLeaf<(f64 fpimm), [{
43 return ARM::getVFPf64Imm(N->getValueAPF()) != -1;
45 let PrintMethod = "printVFPf64ImmOperand";
49 //===----------------------------------------------------------------------===//
50 // Load / store Instructions.
53 let canFoldAsLoad = 1, isReMaterializable = 1 in {
54 def VLDRD : ADI5<0b1101, 0b01, (outs DPR:$Dd), (ins addrmode5:$addr),
55 IIC_fpLoad64, "vldr", ".64\t$Dd, $addr",
56 [(set DPR:$Dd, (f64 (load addrmode5:$addr)))]>;
58 def VLDRS : ASI5<0b1101, 0b01, (outs SPR:$dst), (ins addrmode5:$addr),
59 IIC_fpLoad32, "vldr", ".32\t$dst, $addr",
60 [(set SPR:$dst, (load addrmode5:$addr))]>;
63 def VSTRD : ADI5<0b1101, 0b00, (outs), (ins DPR:$src, addrmode5:$addr),
64 IIC_fpStore64, "vstr", ".64\t$src, $addr",
65 [(store (f64 DPR:$src), addrmode5:$addr)]>;
67 def VSTRS : ASI5<0b1101, 0b00, (outs), (ins SPR:$src, addrmode5:$addr),
68 IIC_fpStore32, "vstr", ".32\t$src, $addr",
69 [(store SPR:$src, addrmode5:$addr)]>;
71 //===----------------------------------------------------------------------===//
72 // Load / store multiple Instructions.
75 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1,
76 isCodeGenOnly = 1 in {
77 def VLDMD : AXDI4<(outs), (ins addrmode4:$addr, pred:$p, reglist:$dsts,
78 variable_ops), IndexModeNone, IIC_fpLoad_m,
79 "vldm${addr:submode}${p}\t$addr, $dsts", "", []> {
83 def VLDMS : AXSI4<(outs), (ins addrmode4:$addr, pred:$p, reglist:$dsts,
84 variable_ops), IndexModeNone, IIC_fpLoad_m,
85 "vldm${addr:submode}${p}\t$addr, $dsts", "", []> {
89 def VLDMD_UPD : AXDI4<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p,
90 reglist:$dsts, variable_ops),
91 IndexModeUpd, IIC_fpLoad_mu,
92 "vldm${addr:submode}${p}\t$addr!, $dsts",
93 "$addr.addr = $wb", []> {
97 def VLDMS_UPD : AXSI4<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p,
98 reglist:$dsts, variable_ops),
99 IndexModeUpd, IIC_fpLoad_mu,
100 "vldm${addr:submode}${p}\t$addr!, $dsts",
101 "$addr.addr = $wb", []> {
104 } // mayLoad, neverHasSideEffects, hasExtraDefRegAllocReq
106 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1,
107 isCodeGenOnly = 1 in {
108 def VSTMD : AXDI4<(outs), (ins addrmode4:$addr, pred:$p, reglist:$srcs,
109 variable_ops), IndexModeNone, IIC_fpStore_m,
110 "vstm${addr:submode}${p}\t$addr, $srcs", "", []> {
114 def VSTMS : AXSI4<(outs), (ins addrmode4:$addr, pred:$p, reglist:$srcs,
115 variable_ops), IndexModeNone, IIC_fpStore_m,
116 "vstm${addr:submode}${p}\t$addr, $srcs", "", []> {
120 def VSTMD_UPD : AXDI4<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p,
121 reglist:$srcs, variable_ops),
122 IndexModeUpd, IIC_fpStore_mu,
123 "vstm${addr:submode}${p}\t$addr!, $srcs",
124 "$addr.addr = $wb", []> {
128 def VSTMS_UPD : AXSI4<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p,
129 reglist:$srcs, variable_ops),
130 IndexModeUpd, IIC_fpStore_mu,
131 "vstm${addr:submode}${p}\t$addr!, $srcs",
132 "$addr.addr = $wb", []> {
135 } // mayStore, neverHasSideEffects, hasExtraSrcRegAllocReq
137 // FLDMX, FSTMX - mixing S/D registers for pre-armv6 cores
140 // FIXME: Can these be placed into the base class?
141 class ADbI_Encode<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops,
142 dag iops, InstrItinClass itin, string opc, string asm,
144 : ADbI<opcod1, opcod2, op6, op4, oops, iops, itin, opc, asm, pattern> {
145 // Instruction operands.
150 // Encode instruction operands.
151 let Inst{3-0} = Dm{3-0};
153 let Inst{19-16} = Dn{3-0};
155 let Inst{15-12} = Dd{3-0};
156 let Inst{22} = Dd{4};
159 class ADuI_Encode<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3,
160 bits<2> opcod4, bit opcod5, dag oops, dag iops,
161 InstrItinClass itin, string opc, string asm,
163 : ADuI<opcod1, opcod2, opcod3, opcod4, opcod5, oops, iops, itin, opc,
165 // Instruction operands.
169 // Encode instruction operands.
170 let Inst{3-0} = Dm{3-0};
172 let Inst{15-12} = Dd{3-0};
173 let Inst{22} = Dd{4};
176 class ASbI_Encode<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops,
177 dag iops, InstrItinClass itin, string opc, string asm,
179 : ASbI<opcod1, opcod2, op6, op4, oops, iops, itin, opc, asm, pattern> {
180 // Instruction operands.
185 // Encode instruction operands.
186 let Inst{3-0} = Sm{4-1};
188 let Inst{19-16} = Sn{4-1};
190 let Inst{15-12} = Sd{4-1};
191 let Inst{22} = Sd{0};
194 class ASbIn_Encode<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops,
195 dag iops, InstrItinClass itin, string opc, string asm,
197 : ASbIn<opcod1, opcod2, op6, op4, oops, iops, itin, opc, asm, pattern> {
198 // Instruction operands.
203 // Encode instruction operands.
204 let Inst{3-0} = Sm{4-1};
206 let Inst{19-16} = Sn{4-1};
208 let Inst{15-12} = Sd{4-1};
209 let Inst{22} = Sd{0};
212 class ASuI_Encode<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3,
213 bits<2> opcod4, bit opcod5, dag oops, dag iops,
214 InstrItinClass itin, string opc, string asm,
216 : ASuI<opcod1, opcod2, opcod3, opcod4, opcod5, oops, iops, itin, opc,
218 // Instruction operands.
222 // Encode instruction operands.
223 let Inst{3-0} = Sm{4-1};
225 let Inst{15-12} = Sd{4-1};
226 let Inst{22} = Sd{0};
229 class ASuIn_Encode<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3,
230 bits<2> opcod4, bit opcod5, dag oops, dag iops,
231 InstrItinClass itin, string opc, string asm,
233 : ASuIn<opcod1, opcod2, opcod3, opcod4, opcod5, oops, iops, itin, opc,
235 // Instruction operands.
239 // Encode instruction operands.
240 let Inst{3-0} = Sm{4-1};
242 let Inst{15-12} = Sd{4-1};
243 let Inst{22} = Sd{0};
246 //===----------------------------------------------------------------------===//
247 // FP Binary Operations.
250 def VADDD : ADbI_Encode<0b11100, 0b11, 0, 0,
251 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
252 IIC_fpALU64, "vadd", ".f64\t$Dd, $Dn, $Dm",
253 [(set DPR:$Dd, (fadd DPR:$Dn, (f64 DPR:$Dm)))]>;
255 def VADDS : ASbIn_Encode<0b11100, 0b11, 0, 0,
256 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
257 IIC_fpALU32, "vadd", ".f32\t$Sd, $Sn, $Sm",
258 [(set SPR:$Sd, (fadd SPR:$Sn, SPR:$Sm))]>;
260 def VSUBD : ADbI_Encode<0b11100, 0b11, 1, 0,
261 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
262 IIC_fpALU64, "vsub", ".f64\t$Dd, $Dn, $Dm",
263 [(set DPR:$Dd, (fsub DPR:$Dn, (f64 DPR:$Dm)))]>;
265 def VSUBS : ASbIn_Encode<0b11100, 0b11, 1, 0,
266 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
267 IIC_fpALU32, "vsub", ".f32\t$Sd, $Sn, $Sm",
268 [(set SPR:$Sd, (fsub SPR:$Sn, SPR:$Sm))]>;
270 def VDIVD : ADbI_Encode<0b11101, 0b00, 0, 0,
271 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
272 IIC_fpDIV64, "vdiv", ".f64\t$Dd, $Dn, $Dm",
273 [(set DPR:$Dd, (fdiv DPR:$Dn, (f64 DPR:$Dm)))]>;
275 def VDIVS : ASbI_Encode<0b11101, 0b00, 0, 0,
276 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
277 IIC_fpDIV32, "vdiv", ".f32\t$Sd, $Sn, $Sm",
278 [(set SPR:$Sd, (fdiv SPR:$Sn, SPR:$Sm))]>;
280 def VMULD : ADbI_Encode<0b11100, 0b10, 0, 0,
281 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
282 IIC_fpMUL64, "vmul", ".f64\t$Dd, $Dn, $Dm",
283 [(set DPR:$Dd, (fmul DPR:$Dn, (f64 DPR:$Dm)))]>;
285 def VMULS : ASbIn_Encode<0b11100, 0b10, 0, 0,
286 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
287 IIC_fpMUL32, "vmul", ".f32\t$Sd, $Sn, $Sm",
288 [(set SPR:$Sd, (fmul SPR:$Sn, SPR:$Sm))]>;
290 def VNMULD : ADbI_Encode<0b11100, 0b10, 1, 0,
291 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
292 IIC_fpMUL64, "vnmul", ".f64\t$Dd, $Dn, $Dm",
293 [(set DPR:$Dd, (fneg (fmul DPR:$Dn, (f64 DPR:$Dm))))]>;
295 def VNMULS : ASbI_Encode<0b11100, 0b10, 1, 0,
296 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
297 IIC_fpMUL32, "vnmul", ".f32\t$Sd, $Sn, $Sm",
298 [(set SPR:$Sd, (fneg (fmul SPR:$Sn, SPR:$Sm)))]>;
300 // Match reassociated forms only if not sign dependent rounding.
301 def : Pat<(fmul (fneg DPR:$a), (f64 DPR:$b)),
302 (VNMULD DPR:$a, DPR:$b)>, Requires<[NoHonorSignDependentRounding]>;
303 def : Pat<(fmul (fneg SPR:$a), SPR:$b),
304 (VNMULS SPR:$a, SPR:$b)>, Requires<[NoHonorSignDependentRounding]>;
306 // These are encoded as unary instructions.
307 let Defs = [FPSCR] in {
308 def VCMPED : ADuI_Encode<0b11101, 0b11, 0b0100, 0b11, 0,
309 (outs), (ins DPR:$Dd, DPR:$Dm),
310 IIC_fpCMP64, "vcmpe", ".f64\t$Dd, $Dm",
311 [(arm_cmpfp DPR:$Dd, (f64 DPR:$Dm))]>;
313 def VCMPES : ASuI_Encode<0b11101, 0b11, 0b0100, 0b11, 0,
314 (outs), (ins SPR:$Sd, SPR:$Sm),
315 IIC_fpCMP32, "vcmpe", ".f32\t$Sd, $Sm",
316 [(arm_cmpfp SPR:$Sd, SPR:$Sm)]>;
318 // FIXME: Verify encoding after integrated assembler is working.
319 def VCMPD : ADuI_Encode<0b11101, 0b11, 0b0100, 0b01, 0,
320 (outs), (ins DPR:$Dd, DPR:$Dm),
321 IIC_fpCMP64, "vcmp", ".f64\t$Dd, $Dm",
322 [/* For disassembly only; pattern left blank */]>;
324 def VCMPS : ASuI_Encode<0b11101, 0b11, 0b0100, 0b01, 0,
325 (outs), (ins SPR:$Sd, SPR:$Sm),
326 IIC_fpCMP32, "vcmp", ".f32\t$Sd, $Sm",
327 [/* For disassembly only; pattern left blank */]>;
330 //===----------------------------------------------------------------------===//
331 // FP Unary Operations.
334 def VABSD : ADuI_Encode<0b11101, 0b11, 0b0000, 0b11, 0,
335 (outs DPR:$Dd), (ins DPR:$Dm),
336 IIC_fpUNA64, "vabs", ".f64\t$Dd, $Dm",
337 [(set DPR:$Dd, (fabs (f64 DPR:$Dm)))]>;
339 def VABSS : ASuIn_Encode<0b11101, 0b11, 0b0000, 0b11, 0,
340 (outs SPR:$Sd), (ins SPR:$Sm),
341 IIC_fpUNA32, "vabs", ".f32\t$Sd, $Sm",
342 [(set SPR:$Sd, (fabs SPR:$Sm))]>;
344 let Defs = [FPSCR] in {
345 def VCMPEZD : ADuI_Encode<0b11101, 0b11, 0b0101, 0b11, 0,
346 (outs), (ins DPR:$Dd),
347 IIC_fpCMP64, "vcmpe", ".f64\t$Dd, #0",
348 [(arm_cmpfp0 (f64 DPR:$Dd))]> {
349 let Inst{3-0} = 0b0000;
353 def VCMPEZS : ASuI_Encode<0b11101, 0b11, 0b0101, 0b11, 0,
354 (outs), (ins SPR:$Sd),
355 IIC_fpCMP32, "vcmpe", ".f32\t$Sd, #0",
356 [(arm_cmpfp0 SPR:$Sd)]> {
357 let Inst{3-0} = 0b0000;
361 // FIXME: Verify encoding after integrated assembler is working.
362 def VCMPZD : ADuI_Encode<0b11101, 0b11, 0b0101, 0b01, 0,
363 (outs), (ins DPR:$Dd),
364 IIC_fpCMP64, "vcmp", ".f64\t$Dd, #0",
365 [/* For disassembly only; pattern left blank */]> {
366 let Inst{3-0} = 0b0000;
370 def VCMPZS : ASuI_Encode<0b11101, 0b11, 0b0101, 0b01, 0,
371 (outs), (ins SPR:$Sd),
372 IIC_fpCMP32, "vcmp", ".f32\t$Sd, #0",
373 [/* For disassembly only; pattern left blank */]> {
374 let Inst{3-0} = 0b0000;
379 def VCVTDS : ASuI<0b11101, 0b11, 0b0111, 0b11, 0,
380 (outs DPR:$Dd), (ins SPR:$Sm),
381 IIC_fpCVTDS, "vcvt", ".f64.f32\t$Dd, $Sm",
382 [(set DPR:$Dd, (fextend SPR:$Sm))]> {
383 // Instruction operands.
387 // Encode instruction operands.
388 let Inst{3-0} = Sm{4-1};
390 let Inst{15-12} = Dd{3-0};
391 let Inst{22} = Dd{4};
394 // Special case encoding: bits 11-8 is 0b1011.
395 def VCVTSD : VFPAI<(outs SPR:$Sd), (ins DPR:$Dm), VFPUnaryFrm,
396 IIC_fpCVTSD, "vcvt", ".f32.f64\t$Sd, $Dm",
397 [(set SPR:$Sd, (fround DPR:$Dm))]> {
398 // Instruction operands.
402 // Encode instruction operands.
403 let Inst{3-0} = Dm{3-0};
405 let Inst{15-12} = Sd{4-1};
406 let Inst{22} = Sd{0};
408 let Inst{27-23} = 0b11101;
409 let Inst{21-16} = 0b110111;
410 let Inst{11-8} = 0b1011;
411 let Inst{7-6} = 0b11;
415 // Between half-precision and single-precision. For disassembly only.
417 // FIXME: Verify encoding after integrated assembler is working.
418 def VCVTBSH: ASuI<0b11101, 0b11, 0b0010, 0b01, 0, (outs SPR:$dst), (ins SPR:$a),
419 /* FIXME */ IIC_fpCVTSH, "vcvtb", ".f32.f16\t$dst, $a",
420 [/* For disassembly only; pattern left blank */]>;
422 def : ARMPat<(f32_to_f16 SPR:$a),
423 (i32 (COPY_TO_REGCLASS (VCVTBSH SPR:$a), GPR))>;
425 def VCVTBHS: ASuI<0b11101, 0b11, 0b0011, 0b01, 0, (outs SPR:$dst), (ins SPR:$a),
426 /* FIXME */ IIC_fpCVTHS, "vcvtb", ".f16.f32\t$dst, $a",
427 [/* For disassembly only; pattern left blank */]>;
429 def : ARMPat<(f16_to_f32 GPR:$a),
430 (VCVTBHS (COPY_TO_REGCLASS GPR:$a, SPR))>;
432 def VCVTTSH: ASuI<0b11101, 0b11, 0b0010, 0b11, 0, (outs SPR:$dst), (ins SPR:$a),
433 /* FIXME */ IIC_fpCVTSH, "vcvtt", ".f32.f16\t$dst, $a",
434 [/* For disassembly only; pattern left blank */]>;
436 def VCVTTHS: ASuI<0b11101, 0b11, 0b0011, 0b11, 0, (outs SPR:$dst), (ins SPR:$a),
437 /* FIXME */ IIC_fpCVTHS, "vcvtt", ".f16.f32\t$dst, $a",
438 [/* For disassembly only; pattern left blank */]>;
440 def VNEGD : ADuI_Encode<0b11101, 0b11, 0b0001, 0b01, 0,
441 (outs DPR:$Dd), (ins DPR:$Dm),
442 IIC_fpUNA64, "vneg", ".f64\t$Dd, $Dm",
443 [(set DPR:$Dd, (fneg (f64 DPR:$Dm)))]>;
445 def VNEGS : ASuIn_Encode<0b11101, 0b11, 0b0001, 0b01, 0,
446 (outs SPR:$Sd), (ins SPR:$Sm),
447 IIC_fpUNA32, "vneg", ".f32\t$Sd, $Sm",
448 [(set SPR:$Sd, (fneg SPR:$Sm))]>;
450 def VSQRTD : ADuI_Encode<0b11101, 0b11, 0b0001, 0b11, 0,
451 (outs DPR:$Dd), (ins DPR:$Dm),
452 IIC_fpSQRT64, "vsqrt", ".f64\t$Dd, $Dm",
453 [(set DPR:$Dd, (fsqrt (f64 DPR:$Dm)))]>;
455 def VSQRTS : ASuI_Encode<0b11101, 0b11, 0b0001, 0b11, 0,
456 (outs SPR:$Sd), (ins SPR:$Sm),
457 IIC_fpSQRT32, "vsqrt", ".f32\t$Sd, $Sm",
458 [(set SPR:$Sd, (fsqrt SPR:$Sm))]>;
460 let neverHasSideEffects = 1 in {
461 def VMOVD : ADuI_Encode<0b11101, 0b11, 0b0000, 0b01, 0,
462 (outs DPR:$Dd), (ins DPR:$Dm),
463 IIC_fpUNA64, "vmov", ".f64\t$Dd, $Dm", []>;
465 def VMOVS : ASuI_Encode<0b11101, 0b11, 0b0000, 0b01, 0,
466 (outs SPR:$Sd), (ins SPR:$Sm),
467 IIC_fpUNA32, "vmov", ".f32\t$Sd, $Sm", []>;
468 } // neverHasSideEffects
470 //===----------------------------------------------------------------------===//
471 // FP <-> GPR Copies. Int <-> FP Conversions.
474 def VMOVRS : AVConv2I<0b11100001, 0b1010,
475 (outs GPR:$Rt), (ins SPR:$Sn),
476 IIC_fpMOVSI, "vmov", "\t$Rt, $Sn",
477 [(set GPR:$Rt, (bitconvert SPR:$Sn))]> {
478 // Instruction operands.
482 // Encode instruction operands.
483 let Inst{19-16} = Sn{4-1};
485 let Inst{15-12} = Rt;
487 let Inst{6-5} = 0b00;
488 let Inst{3-0} = 0b0000;
491 def VMOVSR : AVConv4I<0b11100000, 0b1010,
492 (outs SPR:$Sn), (ins GPR:$Rt),
493 IIC_fpMOVIS, "vmov", "\t$Sn, $Rt",
494 [(set SPR:$Sn, (bitconvert GPR:$Rt))]> {
495 // Instruction operands.
499 // Encode instruction operands.
500 let Inst{19-16} = Sn{4-1};
502 let Inst{15-12} = Rt;
504 let Inst{6-5} = 0b00;
505 let Inst{3-0} = 0b0000;
508 let neverHasSideEffects = 1 in {
509 def VMOVRRD : AVConv3I<0b11000101, 0b1011,
510 (outs GPR:$Rt, GPR:$Rt2), (ins DPR:$Dm),
511 IIC_fpMOVDI, "vmov", "\t$Rt, $Rt2, $Dm",
512 [/* FIXME: Can't write pattern for multiple result instr*/]> {
513 // Instruction operands.
518 // Encode instruction operands.
519 let Inst{3-0} = Dm{3-0};
521 let Inst{15-12} = Rt;
522 let Inst{19-16} = Rt2;
524 let Inst{7-6} = 0b00;
527 def VMOVRRS : AVConv3I<0b11000101, 0b1010,
528 (outs GPR:$wb, GPR:$dst2), (ins SPR:$src1, SPR:$src2),
529 IIC_fpMOVDI, "vmov", "\t$wb, $dst2, $src1, $src2",
530 [/* For disassembly only; pattern left blank */]> {
531 let Inst{7-6} = 0b00;
533 } // neverHasSideEffects
538 def VMOVDRR : AVConv5I<0b11000100, 0b1011,
539 (outs DPR:$Dm), (ins GPR:$Rt, GPR:$Rt2),
540 IIC_fpMOVID, "vmov", "\t$Dm, $Rt, $Rt2",
541 [(set DPR:$Dm, (arm_fmdrr GPR:$Rt, GPR:$Rt2))]> {
542 // Instruction operands.
547 // Encode instruction operands.
548 let Inst{3-0} = Dm{3-0};
550 let Inst{15-12} = Rt;
551 let Inst{19-16} = Rt2;
553 let Inst{7-6} = 0b00;
556 let neverHasSideEffects = 1 in
557 def VMOVSRR : AVConv5I<0b11000100, 0b1010,
558 (outs SPR:$dst1, SPR:$dst2), (ins GPR:$src1, GPR:$src2),
559 IIC_fpMOVID, "vmov", "\t$dst1, $dst2, $src1, $src2",
560 [/* For disassembly only; pattern left blank */]> {
561 let Inst{7-6} = 0b00;
567 // FMRX: SPR system reg -> GPR
569 // FMXR: GPR -> VFP system reg
574 class AVConv1IDs_Encode<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3,
575 bits<4> opcod4, dag oops, dag iops,
576 InstrItinClass itin, string opc, string asm,
578 : AVConv1I<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm,
580 // Instruction operands.
584 // Encode instruction operands.
585 let Inst{3-0} = Sm{4-1};
587 let Inst{15-12} = Dd{3-0};
588 let Inst{22} = Dd{4};
591 class AVConv1InSs_Encode<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3,
592 bits<4> opcod4, dag oops, dag iops,InstrItinClass itin,
593 string opc, string asm, list<dag> pattern>
594 : AVConv1In<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm,
596 // Instruction operands.
600 // Encode instruction operands.
601 let Inst{3-0} = Sm{4-1};
603 let Inst{15-12} = Sd{4-1};
604 let Inst{22} = Sd{0};
607 def VSITOD : AVConv1IDs_Encode<0b11101, 0b11, 0b1000, 0b1011,
608 (outs DPR:$Dd), (ins SPR:$Sm),
609 IIC_fpCVTID, "vcvt", ".f64.s32\t$Dd, $Sm",
610 [(set DPR:$Dd, (f64 (arm_sitof SPR:$Sm)))]> {
611 let Inst{7} = 1; // s32
614 def VSITOS : AVConv1InSs_Encode<0b11101, 0b11, 0b1000, 0b1010,
615 (outs SPR:$Sd),(ins SPR:$Sm),
616 IIC_fpCVTIS, "vcvt", ".f32.s32\t$Sd, $Sm",
617 [(set SPR:$Sd, (arm_sitof SPR:$Sm))]> {
618 let Inst{7} = 1; // s32
621 def VUITOD : AVConv1IDs_Encode<0b11101, 0b11, 0b1000, 0b1011,
622 (outs DPR:$Dd), (ins SPR:$Sm),
623 IIC_fpCVTID, "vcvt", ".f64.u32\t$Dd, $Sm",
624 [(set DPR:$Dd, (f64 (arm_uitof SPR:$Sm)))]> {
625 let Inst{7} = 0; // u32
628 def VUITOS : AVConv1InSs_Encode<0b11101, 0b11, 0b1000, 0b1010,
629 (outs SPR:$Sd), (ins SPR:$Sm),
630 IIC_fpCVTIS, "vcvt", ".f32.u32\t$Sd, $Sm",
631 [(set SPR:$Sd, (arm_uitof SPR:$Sm))]> {
632 let Inst{7} = 0; // u32
637 class AVConv1IsD_Encode<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3,
638 bits<4> opcod4, dag oops, dag iops,
639 InstrItinClass itin, string opc, string asm,
641 : AVConv1I<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm,
643 // Instruction operands.
647 // Encode instruction operands.
648 let Inst{3-0} = Dm{3-0};
650 let Inst{15-12} = Sd{4-1};
651 let Inst{22} = Sd{0};
654 class AVConv1InsS_Encode<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3,
655 bits<4> opcod4, dag oops, dag iops,
656 InstrItinClass itin, string opc, string asm,
658 : AVConv1In<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm,
660 // Instruction operands.
664 // Encode instruction operands.
665 let Inst{3-0} = Sm{4-1};
667 let Inst{15-12} = Sd{4-1};
668 let Inst{22} = Sd{0};
671 // Always set Z bit in the instruction, i.e. "round towards zero" variants.
672 def VTOSIZD : AVConv1IsD_Encode<0b11101, 0b11, 0b1101, 0b1011,
673 (outs SPR:$Sd), (ins DPR:$Dm),
674 IIC_fpCVTDI, "vcvt", ".s32.f64\t$Sd, $Dm",
675 [(set SPR:$Sd, (arm_ftosi (f64 DPR:$Dm)))]> {
676 let Inst{7} = 1; // Z bit
679 def VTOSIZS : AVConv1InsS_Encode<0b11101, 0b11, 0b1101, 0b1010,
680 (outs SPR:$Sd), (ins SPR:$Sm),
681 IIC_fpCVTSI, "vcvt", ".s32.f32\t$Sd, $Sm",
682 [(set SPR:$Sd, (arm_ftosi SPR:$Sm))]> {
683 let Inst{7} = 1; // Z bit
686 def VTOUIZD : AVConv1IsD_Encode<0b11101, 0b11, 0b1100, 0b1011,
687 (outs SPR:$Sd), (ins DPR:$Dm),
688 IIC_fpCVTDI, "vcvt", ".u32.f64\t$Sd, $Dm",
689 [(set SPR:$Sd, (arm_ftoui (f64 DPR:$Dm)))]> {
690 let Inst{7} = 1; // Z bit
693 def VTOUIZS : AVConv1InsS_Encode<0b11101, 0b11, 0b1100, 0b1010,
694 (outs SPR:$Sd), (ins SPR:$Sm),
695 IIC_fpCVTSI, "vcvt", ".u32.f32\t$Sd, $Sm",
696 [(set SPR:$Sd, (arm_ftoui SPR:$Sm))]> {
697 let Inst{7} = 1; // Z bit
700 // And the Z bit '0' variants, i.e. use the rounding mode specified by FPSCR.
701 // For disassembly only.
702 let Uses = [FPSCR] in {
703 // FIXME: Verify encoding after integrated assembler is working.
704 def VTOSIRD : AVConv1IsD_Encode<0b11101, 0b11, 0b1101, 0b1011,
705 (outs SPR:$Sd), (ins DPR:$Dm),
706 IIC_fpCVTDI, "vcvtr", ".s32.f64\t$Sd, $Dm",
707 [(set SPR:$Sd, (int_arm_vcvtr (f64 DPR:$Dm)))]>{
708 let Inst{7} = 0; // Z bit
711 def VTOSIRS : AVConv1InsS_Encode<0b11101, 0b11, 0b1101, 0b1010,
712 (outs SPR:$Sd), (ins SPR:$Sm),
713 IIC_fpCVTSI, "vcvtr", ".s32.f32\t$Sd, $Sm",
714 [(set SPR:$Sd, (int_arm_vcvtr SPR:$Sm))]> {
715 let Inst{7} = 0; // Z bit
718 def VTOUIRD : AVConv1IsD_Encode<0b11101, 0b11, 0b1100, 0b1011,
719 (outs SPR:$Sd), (ins DPR:$Dm),
720 IIC_fpCVTDI, "vcvtr", ".u32.f64\t$Sd, $Dm",
721 [(set SPR:$Sd, (int_arm_vcvtru(f64 DPR:$Dm)))]>{
722 let Inst{7} = 0; // Z bit
725 def VTOUIRS : AVConv1InsS_Encode<0b11101, 0b11, 0b1100, 0b1010,
726 (outs SPR:$Sd), (ins SPR:$Sm),
727 IIC_fpCVTSI, "vcvtr", ".u32.f32\t$Sd, $Sm",
728 [(set SPR:$Sd, (int_arm_vcvtru SPR:$Sm))]> {
729 let Inst{7} = 0; // Z bit
733 // Convert between floating-point and fixed-point
734 // Data type for fixed-point naming convention:
735 // S16 (U=0, sx=0) -> SH
736 // U16 (U=1, sx=0) -> UH
737 // S32 (U=0, sx=1) -> SL
738 // U32 (U=1, sx=1) -> UL
740 let Constraints = "$a = $dst" in {
742 // FP to Fixed-Point:
744 // FIXME: Marking these as codegen only seems wrong. They are real
746 let isCodeGenOnly = 1 in {
747 def VTOSHS : AVConv1XI<0b11101, 0b11, 0b1110, 0b1010, 0,
748 (outs SPR:$dst), (ins SPR:$a, i32imm:$fbits),
749 IIC_fpCVTSI, "vcvt", ".s16.f32\t$dst, $a, $fbits",
750 [/* For disassembly only; pattern left blank */]>;
752 def VTOUHS : AVConv1XI<0b11101, 0b11, 0b1111, 0b1010, 0,
753 (outs SPR:$dst), (ins SPR:$a, i32imm:$fbits),
754 IIC_fpCVTSI, "vcvt", ".u16.f32\t$dst, $a, $fbits",
755 [/* For disassembly only; pattern left blank */]>;
757 def VTOSLS : AVConv1XI<0b11101, 0b11, 0b1110, 0b1010, 1,
758 (outs SPR:$dst), (ins SPR:$a, i32imm:$fbits),
759 IIC_fpCVTSI, "vcvt", ".s32.f32\t$dst, $a, $fbits",
760 [/* For disassembly only; pattern left blank */]>;
762 def VTOULS : AVConv1XI<0b11101, 0b11, 0b1111, 0b1010, 1,
763 (outs SPR:$dst), (ins SPR:$a, i32imm:$fbits),
764 IIC_fpCVTSI, "vcvt", ".u32.f32\t$dst, $a, $fbits",
765 [/* For disassembly only; pattern left blank */]>;
767 def VTOSHD : AVConv1XI<0b11101, 0b11, 0b1110, 0b1011, 0,
768 (outs DPR:$dst), (ins DPR:$a, i32imm:$fbits),
769 IIC_fpCVTDI, "vcvt", ".s16.f64\t$dst, $a, $fbits",
770 [/* For disassembly only; pattern left blank */]>;
772 def VTOUHD : AVConv1XI<0b11101, 0b11, 0b1111, 0b1011, 0,
773 (outs DPR:$dst), (ins DPR:$a, i32imm:$fbits),
774 IIC_fpCVTDI, "vcvt", ".u16.f64\t$dst, $a, $fbits",
775 [/* For disassembly only; pattern left blank */]>;
777 def VTOSLD : AVConv1XI<0b11101, 0b11, 0b1110, 0b1011, 1,
778 (outs DPR:$dst), (ins DPR:$a, i32imm:$fbits),
779 IIC_fpCVTDI, "vcvt", ".s32.f64\t$dst, $a, $fbits",
780 [/* For disassembly only; pattern left blank */]>;
782 def VTOULD : AVConv1XI<0b11101, 0b11, 0b1111, 0b1011, 1,
783 (outs DPR:$dst), (ins DPR:$a, i32imm:$fbits),
784 IIC_fpCVTDI, "vcvt", ".u32.f64\t$dst, $a, $fbits",
785 [/* For disassembly only; pattern left blank */]>;
786 } // End of 'let isCodeGenOnly = 1 in'
788 // Fixed-Point to FP:
790 let isCodeGenOnly = 1 in {
791 def VSHTOS : AVConv1XI<0b11101, 0b11, 0b1010, 0b1010, 0,
792 (outs SPR:$dst), (ins SPR:$a, i32imm:$fbits),
793 IIC_fpCVTIS, "vcvt", ".f32.s16\t$dst, $a, $fbits",
794 [/* For disassembly only; pattern left blank */]>;
796 def VUHTOS : AVConv1XI<0b11101, 0b11, 0b1011, 0b1010, 0,
797 (outs SPR:$dst), (ins SPR:$a, i32imm:$fbits),
798 IIC_fpCVTIS, "vcvt", ".f32.u16\t$dst, $a, $fbits",
799 [/* For disassembly only; pattern left blank */]>;
801 def VSLTOS : AVConv1XI<0b11101, 0b11, 0b1010, 0b1010, 1,
802 (outs SPR:$dst), (ins SPR:$a, i32imm:$fbits),
803 IIC_fpCVTIS, "vcvt", ".f32.s32\t$dst, $a, $fbits",
804 [/* For disassembly only; pattern left blank */]>;
806 def VULTOS : AVConv1XI<0b11101, 0b11, 0b1011, 0b1010, 1,
807 (outs SPR:$dst), (ins SPR:$a, i32imm:$fbits),
808 IIC_fpCVTIS, "vcvt", ".f32.u32\t$dst, $a, $fbits",
809 [/* For disassembly only; pattern left blank */]>;
811 def VSHTOD : AVConv1XI<0b11101, 0b11, 0b1010, 0b1011, 0,
812 (outs DPR:$dst), (ins DPR:$a, i32imm:$fbits),
813 IIC_fpCVTID, "vcvt", ".f64.s16\t$dst, $a, $fbits",
814 [/* For disassembly only; pattern left blank */]>;
816 def VUHTOD : AVConv1XI<0b11101, 0b11, 0b1011, 0b1011, 0,
817 (outs DPR:$dst), (ins DPR:$a, i32imm:$fbits),
818 IIC_fpCVTID, "vcvt", ".f64.u16\t$dst, $a, $fbits",
819 [/* For disassembly only; pattern left blank */]>;
821 def VSLTOD : AVConv1XI<0b11101, 0b11, 0b1010, 0b1011, 1,
822 (outs DPR:$dst), (ins DPR:$a, i32imm:$fbits),
823 IIC_fpCVTID, "vcvt", ".f64.s32\t$dst, $a, $fbits",
824 [/* For disassembly only; pattern left blank */]>;
826 def VULTOD : AVConv1XI<0b11101, 0b11, 0b1011, 0b1011, 1,
827 (outs DPR:$dst), (ins DPR:$a, i32imm:$fbits),
828 IIC_fpCVTID, "vcvt", ".f64.u32\t$dst, $a, $fbits",
829 [/* For disassembly only; pattern left blank */]>;
830 } // End of 'let isCodeGenOnly = 1 in'
832 } // End of 'let Constraints = "$src = $dst" in'
834 //===----------------------------------------------------------------------===//
835 // FP FMA Operations.
838 class ADbI_vmlX_Encode<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4,
839 dag oops, dag iops, InstrItinClass itin, string opc,
840 string asm, list<dag> pattern>
841 : ADbI_vmlX<opcod1, opcod2, op6, op4, oops, iops, itin, opc, asm, pattern> {
842 // Instruction operands.
847 // Encode instruction operands.
848 let Inst{19-16} = Dn{3-0};
850 let Inst{15-12} = Dd{3-0};
851 let Inst{22} = Dd{4};
852 let Inst{3-0} = Dm{3-0};
856 def VMLAD : ADbI_vmlX_Encode<0b11100, 0b00, 0, 0,
857 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
858 IIC_fpMAC64, "vmla", ".f64\t$Dd, $Dn, $Dm",
859 [(set DPR:$Dd, (fadd (fmul DPR:$Dn, DPR:$Dm),
861 RegConstraint<"$Ddin = $Dd">;
863 def VMLAS : ASbIn_Encode<0b11100, 0b00, 0, 0,
864 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
865 IIC_fpMAC32, "vmla", ".f32\t$Sd, $Sn, $Sm",
866 [(set SPR:$Sd, (fadd (fmul SPR:$Sn, SPR:$Sm),
868 RegConstraint<"$Sdin = $Sd">;
870 def : Pat<(fadd DPR:$dstin, (fmul DPR:$a, (f64 DPR:$b))),
871 (VMLAD DPR:$dstin, DPR:$a, DPR:$b)>, Requires<[DontUseNEONForFP]>;
872 def : Pat<(fadd SPR:$dstin, (fmul SPR:$a, SPR:$b)),
873 (VMLAS SPR:$dstin, SPR:$a, SPR:$b)>, Requires<[DontUseNEONForFP]>;
875 def VMLSD : ADbI_vmlX_Encode<0b11100, 0b00, 1, 0,
876 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
877 IIC_fpMAC64, "vmls", ".f64\t$Dd, $Dn, $Dm",
878 [(set DPR:$Dd, (fadd (fneg (fmul DPR:$Dn,DPR:$Dm)),
880 RegConstraint<"$Ddin = $Dd">;
882 def VMLSS : ASbIn_Encode<0b11100, 0b00, 1, 0,
883 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
884 IIC_fpMAC32, "vmls", ".f32\t$Sd, $Sn, $Sm",
885 [(set SPR:$Sd, (fadd (fneg (fmul SPR:$Sn, SPR:$Sm)),
887 RegConstraint<"$Sdin = $Sd">;
889 def : Pat<(fsub DPR:$dstin, (fmul DPR:$a, (f64 DPR:$b))),
890 (VMLSD DPR:$dstin, DPR:$a, DPR:$b)>, Requires<[DontUseNEONForFP]>;
891 def : Pat<(fsub SPR:$dstin, (fmul SPR:$a, SPR:$b)),
892 (VMLSS SPR:$dstin, SPR:$a, SPR:$b)>, Requires<[DontUseNEONForFP]>;
894 def VNMLAD : ADbI_vmlX_Encode<0b11100, 0b01, 1, 0,
895 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
896 IIC_fpMAC64, "vnmla", ".f64\t$Dd, $Dn, $Dm",
897 [(set DPR:$Dd,(fsub (fneg (fmul DPR:$Dn,DPR:$Dm)),
899 RegConstraint<"$Ddin = $Dd">;
901 def VNMLAS : ASbI_Encode<0b11100, 0b01, 1, 0,
902 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
903 IIC_fpMAC32, "vnmla", ".f32\t$Sd, $Sn, $Sm",
904 [(set SPR:$Sd, (fsub (fneg (fmul SPR:$Sn, SPR:$Sm)),
906 RegConstraint<"$Sdin = $Sd">;
908 def : Pat<(fsub (fneg (fmul DPR:$a, (f64 DPR:$b))), DPR:$dstin),
909 (VNMLAD DPR:$dstin, DPR:$a, DPR:$b)>, Requires<[DontUseNEONForFP]>;
910 def : Pat<(fsub (fneg (fmul SPR:$a, SPR:$b)), SPR:$dstin),
911 (VNMLAS SPR:$dstin, SPR:$a, SPR:$b)>, Requires<[DontUseNEONForFP]>;
913 def VNMLSD : ADbI_vmlX_Encode<0b11100, 0b01, 0, 0,
914 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
915 IIC_fpMAC64, "vnmls", ".f64\t$Dd, $Dn, $Dm",
916 [(set DPR:$Dd, (fsub (fmul DPR:$Dn, DPR:$Dm),
918 RegConstraint<"$Ddin = $Dd">;
920 def VNMLSS : ASbI_Encode<0b11100, 0b01, 0, 0,
921 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
922 IIC_fpMAC32, "vnmls", ".f32\t$Sd, $Sn, $Sm",
923 [(set SPR:$Sd, (fsub (fmul SPR:$Sn, SPR:$Sm),
925 RegConstraint<"$Sdin = $Sd">;
927 def : Pat<(fsub (fmul DPR:$a, (f64 DPR:$b)), DPR:$dstin),
928 (VNMLSD DPR:$dstin, DPR:$a, DPR:$b)>, Requires<[DontUseNEONForFP]>;
929 def : Pat<(fsub (fmul SPR:$a, SPR:$b), SPR:$dstin),
930 (VNMLSS SPR:$dstin, SPR:$a, SPR:$b)>, Requires<[DontUseNEONForFP]>;
933 //===----------------------------------------------------------------------===//
934 // FP Conditional moves.
937 let neverHasSideEffects = 1 in {
938 def VMOVDcc : ADuI_Encode<0b11101, 0b11, 0b0000, 0b01, 0,
939 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
940 IIC_fpUNA64, "vmov", ".f64\t$Dd, $Dm",
941 [/*(set DPR:$Dd, (ARMcmov DPR:$Dn, DPR:$Dm, imm:$cc))*/]>,
942 RegConstraint<"$Dn = $Dd">;
944 def VMOVScc : ASuI_Encode<0b11101, 0b11, 0b0000, 0b01, 0,
945 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
946 IIC_fpUNA32, "vmov", ".f32\t$Sd, $Sm",
947 [/*(set SPR:$Sd, (ARMcmov SPR:$Sn, SPR:$Sm, imm:$cc))*/]>,
948 RegConstraint<"$Sn = $Sd">;
950 def VNEGDcc : ADuI_Encode<0b11101, 0b11, 0b0001, 0b01, 0,
951 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
952 IIC_fpUNA64, "vneg", ".f64\t$Dd, $Dm",
953 [/*(set DPR:$Dd, (ARMcneg DPR:$Dn, DPR:$Dm, imm:$cc))*/]>,
954 RegConstraint<"$Dn = $Dd">;
956 def VNEGScc : ASuI_Encode<0b11101, 0b11, 0b0001, 0b01, 0,
957 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
958 IIC_fpUNA32, "vneg", ".f32\t$Sd, $Sm",
959 [/*(set SPR:$Sd, (ARMcneg SPR:$Sn, SPR:$Sm, imm:$cc))*/]>,
960 RegConstraint<"$Sn = $Sd">;
961 } // neverHasSideEffects
963 //===----------------------------------------------------------------------===//
967 // APSR is the application level alias of CPSR. This FPSCR N, Z, C, V flags
969 let Defs = [CPSR], Uses = [FPSCR] in
970 def FMSTAT : VFPAI<(outs), (ins), VFPMiscFrm, IIC_fpSTAT, "vmrs",
971 "\tapsr_nzcv, fpscr",
973 let Inst{27-20} = 0b11101111;
974 let Inst{19-16} = 0b0001;
975 let Inst{15-12} = 0b1111;
976 let Inst{11-8} = 0b1010;
978 let Inst{6-5} = 0b00;
980 let Inst{3-0} = 0b0000;
984 let hasSideEffects = 1, Uses = [FPSCR] in
985 def VMRS : VFPAI<(outs GPR:$Rt), (ins), VFPMiscFrm, IIC_fpSTAT,
986 "vmrs", "\t$Rt, fpscr",
987 [(set GPR:$Rt, (int_arm_get_fpscr))]> {
988 // Instruction operand.
991 // Encode instruction operand.
992 let Inst{15-12} = Rt;
994 let Inst{27-20} = 0b11101111;
995 let Inst{19-16} = 0b0001;
996 let Inst{11-8} = 0b1010;
998 let Inst{6-5} = 0b00;
1000 let Inst{3-0} = 0b0000;
1003 let Defs = [FPSCR] in
1004 def VMSR : VFPAI<(outs), (ins GPR:$src), VFPMiscFrm, IIC_fpSTAT,
1005 "vmsr", "\tfpscr, $src",
1006 [(int_arm_set_fpscr GPR:$src)]> {
1007 // Instruction operand.
1010 // Encode instruction operand.
1011 let Inst{15-12} = src;
1013 let Inst{27-20} = 0b11101110;
1014 let Inst{19-16} = 0b0001;
1015 let Inst{11-8} = 0b1010;
1020 // Materialize FP immediates. VFP3 only.
1021 let isReMaterializable = 1 in {
1022 def FCONSTD : VFPAI<(outs DPR:$Dd), (ins vfp_f64imm:$imm),
1023 VFPMiscFrm, IIC_fpUNA64,
1024 "vmov", ".f64\t$Dd, $imm",
1025 [(set DPR:$Dd, vfp_f64imm:$imm)]>, Requires<[HasVFP3]> {
1026 // Instruction operands.
1030 // Encode instruction operands.
1031 let Inst{15-12} = Dd{3-0};
1032 let Inst{22} = Dd{4};
1033 let Inst{19} = imm{31};
1034 let Inst{18-16} = imm{22-20};
1035 let Inst{3-0} = imm{19-16};
1037 // Encode remaining instruction bits.
1038 let Inst{27-23} = 0b11101;
1039 let Inst{21-20} = 0b11;
1040 let Inst{11-9} = 0b101;
1041 let Inst{8} = 1; // Double precision.
1042 let Inst{7-4} = 0b0000;
1045 def FCONSTS : VFPAI<(outs SPR:$Sd), (ins vfp_f32imm:$imm),
1046 VFPMiscFrm, IIC_fpUNA32,
1047 "vmov", ".f32\t$Sd, $imm",
1048 [(set SPR:$Sd, vfp_f32imm:$imm)]>, Requires<[HasVFP3]> {
1049 // Instruction operands.
1053 // Encode instruction operands.
1054 let Inst{15-12} = Sd{4-1};
1055 let Inst{22} = Sd{0};
1056 let Inst{19} = imm{31}; // The immediate is handled as a double.
1057 let Inst{18-16} = imm{22-20};
1058 let Inst{3-0} = imm{19-16};
1060 // Encode remaining instruction bits.
1061 let Inst{27-23} = 0b11101;
1062 let Inst{21-20} = 0b11;
1063 let Inst{11-9} = 0b101;
1064 let Inst{8} = 0; // Single precision.
1065 let Inst{7-4} = 0b0000;