1 //===-- ARMInstrVFP.td - VFP support for ARM ---------------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM VFP instruction set.
12 //===----------------------------------------------------------------------===//
14 def SDT_FTOI : SDTypeProfile<1, 1, [SDTCisVT<0, f32>, SDTCisFP<1>]>;
15 def SDT_ITOF : SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisVT<1, f32>]>;
16 def SDT_CMPFP0 : SDTypeProfile<0, 1, [SDTCisFP<0>]>;
17 def SDT_VMOVDRR : SDTypeProfile<1, 2, [SDTCisVT<0, f64>, SDTCisVT<1, i32>,
20 def arm_ftoui : SDNode<"ARMISD::FTOUI", SDT_FTOI>;
21 def arm_ftosi : SDNode<"ARMISD::FTOSI", SDT_FTOI>;
22 def arm_sitof : SDNode<"ARMISD::SITOF", SDT_ITOF>;
23 def arm_uitof : SDNode<"ARMISD::UITOF", SDT_ITOF>;
24 def arm_fmstat : SDNode<"ARMISD::FMSTAT", SDTNone, [SDNPInGlue, SDNPOutGlue]>;
25 def arm_cmpfp : SDNode<"ARMISD::CMPFP", SDT_ARMCmp, [SDNPOutGlue]>;
26 def arm_cmpfp0 : SDNode<"ARMISD::CMPFPw0", SDT_CMPFP0, [SDNPOutGlue]>;
27 def arm_fmdrr : SDNode<"ARMISD::VMOVDRR", SDT_VMOVDRR>;
30 //===----------------------------------------------------------------------===//
31 // Operand Definitions.
34 // 8-bit floating-point immediate encodings.
35 def FPImmOperand : AsmOperandClass {
37 let ParserMethod = "parseFPImm";
40 def vfp_f32imm : Operand<f32>,
41 PatLeaf<(f32 fpimm), [{
42 return ARM_AM::getFP32Imm(N->getValueAPF()) != -1;
43 }], SDNodeXForm<fpimm, [{
44 APFloat InVal = N->getValueAPF();
45 uint32_t enc = ARM_AM::getFP32Imm(InVal);
46 return CurDAG->getTargetConstant(enc, MVT::i32);
48 let PrintMethod = "printFPImmOperand";
49 let ParserMatchClass = FPImmOperand;
52 def vfp_f64imm : Operand<f64>,
53 PatLeaf<(f64 fpimm), [{
54 return ARM_AM::getFP64Imm(N->getValueAPF()) != -1;
55 }], SDNodeXForm<fpimm, [{
56 APFloat InVal = N->getValueAPF();
57 uint32_t enc = ARM_AM::getFP64Imm(InVal);
58 return CurDAG->getTargetConstant(enc, MVT::i32);
60 let PrintMethod = "printFPImmOperand";
61 let ParserMatchClass = FPImmOperand;
64 def alignedload32 : PatFrag<(ops node:$ptr), (load node:$ptr), [{
65 return cast<LoadSDNode>(N)->getAlignment() >= 4;
68 def alignedstore32 : PatFrag<(ops node:$val, node:$ptr),
69 (store node:$val, node:$ptr), [{
70 return cast<StoreSDNode>(N)->getAlignment() >= 4;
73 // The VCVT to/from fixed-point instructions encode the 'fbits' operand
74 // (the number of fixed bits) differently than it appears in the assembly
75 // source. It's encoded as "Size - fbits" where Size is the size of the
76 // fixed-point representation (32 or 16) and fbits is the value appearing
77 // in the assembly source, an integer in [0,16] or (0,32], depending on size.
78 def fbits32_asm_operand : AsmOperandClass { let Name = "FBits32"; }
79 def fbits32 : Operand<i32> {
80 let PrintMethod = "printFBits32";
81 let ParserMatchClass = fbits32_asm_operand;
84 def fbits16_asm_operand : AsmOperandClass { let Name = "FBits16"; }
85 def fbits16 : Operand<i32> {
86 let PrintMethod = "printFBits16";
87 let ParserMatchClass = fbits16_asm_operand;
90 //===----------------------------------------------------------------------===//
91 // Load / store Instructions.
94 let canFoldAsLoad = 1, isReMaterializable = 1 in {
96 def VLDRD : ADI5<0b1101, 0b01, (outs DPR:$Dd), (ins addrmode5:$addr),
97 IIC_fpLoad64, "vldr", "\t$Dd, $addr",
98 [(set DPR:$Dd, (f64 (alignedload32 addrmode5:$addr)))]>;
100 def VLDRS : ASI5<0b1101, 0b01, (outs SPR:$Sd), (ins addrmode5:$addr),
101 IIC_fpLoad32, "vldr", "\t$Sd, $addr",
102 [(set SPR:$Sd, (load addrmode5:$addr))]> {
103 // Some single precision VFP instructions may be executed on both NEON and VFP
105 let D = VFPNeonDomain;
108 } // End of 'let canFoldAsLoad = 1, isReMaterializable = 1 in'
110 def VSTRD : ADI5<0b1101, 0b00, (outs), (ins DPR:$Dd, addrmode5:$addr),
111 IIC_fpStore64, "vstr", "\t$Dd, $addr",
112 [(alignedstore32 (f64 DPR:$Dd), addrmode5:$addr)]>;
114 def VSTRS : ASI5<0b1101, 0b00, (outs), (ins SPR:$Sd, addrmode5:$addr),
115 IIC_fpStore32, "vstr", "\t$Sd, $addr",
116 [(store SPR:$Sd, addrmode5:$addr)]> {
117 // Some single precision VFP instructions may be executed on both NEON and VFP
119 let D = VFPNeonDomain;
122 //===----------------------------------------------------------------------===//
123 // Load / store multiple Instructions.
126 multiclass vfp_ldst_mult<string asm, bit L_bit,
127 InstrItinClass itin, InstrItinClass itin_upd> {
130 AXDI4<(outs), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs, variable_ops),
132 !strconcat(asm, "ia${p}\t$Rn, $regs"), "", []> {
133 let Inst{24-23} = 0b01; // Increment After
134 let Inst{21} = 0; // No writeback
135 let Inst{20} = L_bit;
138 AXDI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs,
140 IndexModeUpd, itin_upd,
141 !strconcat(asm, "ia${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
142 let Inst{24-23} = 0b01; // Increment After
143 let Inst{21} = 1; // Writeback
144 let Inst{20} = L_bit;
147 AXDI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs,
149 IndexModeUpd, itin_upd,
150 !strconcat(asm, "db${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
151 let Inst{24-23} = 0b10; // Decrement Before
152 let Inst{21} = 1; // Writeback
153 let Inst{20} = L_bit;
158 AXSI4<(outs), (ins GPR:$Rn, pred:$p, spr_reglist:$regs, variable_ops),
160 !strconcat(asm, "ia${p}\t$Rn, $regs"), "", []> {
161 let Inst{24-23} = 0b01; // Increment After
162 let Inst{21} = 0; // No writeback
163 let Inst{20} = L_bit;
165 // Some single precision VFP instructions may be executed on both NEON and
167 let D = VFPNeonDomain;
170 AXSI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, spr_reglist:$regs,
172 IndexModeUpd, itin_upd,
173 !strconcat(asm, "ia${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
174 let Inst{24-23} = 0b01; // Increment After
175 let Inst{21} = 1; // Writeback
176 let Inst{20} = L_bit;
178 // Some single precision VFP instructions may be executed on both NEON and
180 let D = VFPNeonDomain;
183 AXSI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, spr_reglist:$regs,
185 IndexModeUpd, itin_upd,
186 !strconcat(asm, "db${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
187 let Inst{24-23} = 0b10; // Decrement Before
188 let Inst{21} = 1; // Writeback
189 let Inst{20} = L_bit;
191 // Some single precision VFP instructions may be executed on both NEON and
193 let D = VFPNeonDomain;
197 let neverHasSideEffects = 1 in {
199 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
200 defm VLDM : vfp_ldst_mult<"vldm", 1, IIC_fpLoad_m, IIC_fpLoad_mu>;
202 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
203 defm VSTM : vfp_ldst_mult<"vstm", 0, IIC_fpLoad_m, IIC_fpLoad_mu>;
205 } // neverHasSideEffects
207 def : MnemonicAlias<"vldm", "vldmia">;
208 def : MnemonicAlias<"vstm", "vstmia">;
210 def : InstAlias<"vpush${p} $r", (VSTMDDB_UPD SP, pred:$p, dpr_reglist:$r)>,
212 def : InstAlias<"vpush${p} $r", (VSTMSDB_UPD SP, pred:$p, spr_reglist:$r)>,
214 def : InstAlias<"vpop${p} $r", (VLDMDIA_UPD SP, pred:$p, dpr_reglist:$r)>,
216 def : InstAlias<"vpop${p} $r", (VLDMSIA_UPD SP, pred:$p, spr_reglist:$r)>,
218 defm : VFPDTAnyInstAlias<"vpush${p}", "$r",
219 (VSTMSDB_UPD SP, pred:$p, spr_reglist:$r)>;
220 defm : VFPDTAnyInstAlias<"vpush${p}", "$r",
221 (VSTMDDB_UPD SP, pred:$p, dpr_reglist:$r)>;
222 defm : VFPDTAnyInstAlias<"vpop${p}", "$r",
223 (VLDMSIA_UPD SP, pred:$p, spr_reglist:$r)>;
224 defm : VFPDTAnyInstAlias<"vpop${p}", "$r",
225 (VLDMDIA_UPD SP, pred:$p, dpr_reglist:$r)>;
227 // FLDMX, FSTMX - Load and store multiple unknown precision registers for
229 // These instruction are deprecated so we don't want them to get selected.
230 multiclass vfp_ldstx_mult<string asm, bit L_bit> {
233 AXXI4<(outs), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs, variable_ops),
234 IndexModeNone, !strconcat(asm, "iax${p}\t$Rn, $regs"), "", []> {
235 let Inst{24-23} = 0b01; // Increment After
236 let Inst{21} = 0; // No writeback
237 let Inst{20} = L_bit;
240 AXXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs, variable_ops),
241 IndexModeUpd, !strconcat(asm, "iax${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
242 let Inst{24-23} = 0b01; // Increment After
243 let Inst{21} = 1; // Writeback
244 let Inst{20} = L_bit;
247 AXXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs, variable_ops),
248 IndexModeUpd, !strconcat(asm, "dbx${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
249 let Inst{24-23} = 0b10; // Decrement Before
251 let Inst{20} = L_bit;
255 defm FLDM : vfp_ldstx_mult<"fldm", 1>;
256 defm FSTM : vfp_ldstx_mult<"fstm", 0>;
258 //===----------------------------------------------------------------------===//
259 // FP Binary Operations.
262 let TwoOperandAliasConstraint = "$Dn = $Dd" in
263 def VADDD : ADbI<0b11100, 0b11, 0, 0,
264 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
265 IIC_fpALU64, "vadd", ".f64\t$Dd, $Dn, $Dm",
266 [(set DPR:$Dd, (fadd DPR:$Dn, (f64 DPR:$Dm)))]>;
268 let TwoOperandAliasConstraint = "$Sn = $Sd" in
269 def VADDS : ASbIn<0b11100, 0b11, 0, 0,
270 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
271 IIC_fpALU32, "vadd", ".f32\t$Sd, $Sn, $Sm",
272 [(set SPR:$Sd, (fadd SPR:$Sn, SPR:$Sm))]> {
273 // Some single precision VFP instructions may be executed on both NEON and
274 // VFP pipelines on A8.
275 let D = VFPNeonA8Domain;
278 let TwoOperandAliasConstraint = "$Dn = $Dd" in
279 def VSUBD : ADbI<0b11100, 0b11, 1, 0,
280 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
281 IIC_fpALU64, "vsub", ".f64\t$Dd, $Dn, $Dm",
282 [(set DPR:$Dd, (fsub DPR:$Dn, (f64 DPR:$Dm)))]>;
284 let TwoOperandAliasConstraint = "$Sn = $Sd" in
285 def VSUBS : ASbIn<0b11100, 0b11, 1, 0,
286 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
287 IIC_fpALU32, "vsub", ".f32\t$Sd, $Sn, $Sm",
288 [(set SPR:$Sd, (fsub SPR:$Sn, SPR:$Sm))]> {
289 // Some single precision VFP instructions may be executed on both NEON and
290 // VFP pipelines on A8.
291 let D = VFPNeonA8Domain;
294 let TwoOperandAliasConstraint = "$Dn = $Dd" in
295 def VDIVD : ADbI<0b11101, 0b00, 0, 0,
296 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
297 IIC_fpDIV64, "vdiv", ".f64\t$Dd, $Dn, $Dm",
298 [(set DPR:$Dd, (fdiv DPR:$Dn, (f64 DPR:$Dm)))]>;
300 let TwoOperandAliasConstraint = "$Sn = $Sd" in
301 def VDIVS : ASbI<0b11101, 0b00, 0, 0,
302 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
303 IIC_fpDIV32, "vdiv", ".f32\t$Sd, $Sn, $Sm",
304 [(set SPR:$Sd, (fdiv SPR:$Sn, SPR:$Sm))]>;
306 let TwoOperandAliasConstraint = "$Dn = $Dd" in
307 def VMULD : ADbI<0b11100, 0b10, 0, 0,
308 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
309 IIC_fpMUL64, "vmul", ".f64\t$Dd, $Dn, $Dm",
310 [(set DPR:$Dd, (fmul DPR:$Dn, (f64 DPR:$Dm)))]>;
312 let TwoOperandAliasConstraint = "$Sn = $Sd" in
313 def VMULS : ASbIn<0b11100, 0b10, 0, 0,
314 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
315 IIC_fpMUL32, "vmul", ".f32\t$Sd, $Sn, $Sm",
316 [(set SPR:$Sd, (fmul SPR:$Sn, SPR:$Sm))]> {
317 // Some single precision VFP instructions may be executed on both NEON and
318 // VFP pipelines on A8.
319 let D = VFPNeonA8Domain;
322 def VNMULD : ADbI<0b11100, 0b10, 1, 0,
323 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
324 IIC_fpMUL64, "vnmul", ".f64\t$Dd, $Dn, $Dm",
325 [(set DPR:$Dd, (fneg (fmul DPR:$Dn, (f64 DPR:$Dm))))]>;
327 def VNMULS : ASbI<0b11100, 0b10, 1, 0,
328 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
329 IIC_fpMUL32, "vnmul", ".f32\t$Sd, $Sn, $Sm",
330 [(set SPR:$Sd, (fneg (fmul SPR:$Sn, SPR:$Sm)))]> {
331 // Some single precision VFP instructions may be executed on both NEON and
332 // VFP pipelines on A8.
333 let D = VFPNeonA8Domain;
336 multiclass vsel_inst<string op, bits<2> opc> {
337 let DecoderNamespace = "VFPV8", PostEncoderMethod = "" in {
338 def S : ASbInp<0b11100, opc, 0,
339 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
340 NoItinerary, !strconcat("vsel", op, ".f32\t$Sd, $Sn, $Sm"),
341 []>, Requires<[HasV8FP]>;
343 def D : ADbInp<0b11100, opc, 0,
344 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
345 NoItinerary, !strconcat("vsel", op, ".f64\t$Dd, $Dn, $Dm"),
346 []>, Requires<[HasV8FP]>;
350 defm VSELGT : vsel_inst<"gt", 0b11>;
351 defm VSELGE : vsel_inst<"ge", 0b10>;
352 defm VSELEQ : vsel_inst<"eq", 0b00>;
353 defm VSELVS : vsel_inst<"vs", 0b01>;
355 multiclass vmaxmin_inst<string op, bit opc> {
356 let DecoderNamespace = "VFPV8", PostEncoderMethod = "" in {
357 def S : ASbInp<0b11101, 0b00, opc,
358 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
359 NoItinerary, !strconcat(op, ".f32\t$Sd, $Sn, $Sm"),
360 []>, Requires<[HasV8FP]>;
362 def D : ADbInp<0b11101, 0b00, opc,
363 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
364 NoItinerary, !strconcat(op, ".f64\t$Dd, $Dn, $Dm"),
365 []>, Requires<[HasV8FP]>;
369 defm VMAXNM : vmaxmin_inst<"vmaxnm", 0>;
370 defm VMINNM : vmaxmin_inst<"vminnm", 1>;
372 // Match reassociated forms only if not sign dependent rounding.
373 def : Pat<(fmul (fneg DPR:$a), (f64 DPR:$b)),
374 (VNMULD DPR:$a, DPR:$b)>, Requires<[NoHonorSignDependentRounding]>;
375 def : Pat<(fmul (fneg SPR:$a), SPR:$b),
376 (VNMULS SPR:$a, SPR:$b)>, Requires<[NoHonorSignDependentRounding]>;
378 // These are encoded as unary instructions.
379 let Defs = [FPSCR_NZCV] in {
380 def VCMPED : ADuI<0b11101, 0b11, 0b0100, 0b11, 0,
381 (outs), (ins DPR:$Dd, DPR:$Dm),
382 IIC_fpCMP64, "vcmpe", ".f64\t$Dd, $Dm",
383 [(arm_cmpfp DPR:$Dd, (f64 DPR:$Dm))]>;
385 def VCMPES : ASuI<0b11101, 0b11, 0b0100, 0b11, 0,
386 (outs), (ins SPR:$Sd, SPR:$Sm),
387 IIC_fpCMP32, "vcmpe", ".f32\t$Sd, $Sm",
388 [(arm_cmpfp SPR:$Sd, SPR:$Sm)]> {
389 // Some single precision VFP instructions may be executed on both NEON and
390 // VFP pipelines on A8.
391 let D = VFPNeonA8Domain;
394 // FIXME: Verify encoding after integrated assembler is working.
395 def VCMPD : ADuI<0b11101, 0b11, 0b0100, 0b01, 0,
396 (outs), (ins DPR:$Dd, DPR:$Dm),
397 IIC_fpCMP64, "vcmp", ".f64\t$Dd, $Dm",
398 [/* For disassembly only; pattern left blank */]>;
400 def VCMPS : ASuI<0b11101, 0b11, 0b0100, 0b01, 0,
401 (outs), (ins SPR:$Sd, SPR:$Sm),
402 IIC_fpCMP32, "vcmp", ".f32\t$Sd, $Sm",
403 [/* For disassembly only; pattern left blank */]> {
404 // Some single precision VFP instructions may be executed on both NEON and
405 // VFP pipelines on A8.
406 let D = VFPNeonA8Domain;
408 } // Defs = [FPSCR_NZCV]
410 //===----------------------------------------------------------------------===//
411 // FP Unary Operations.
414 def VABSD : ADuI<0b11101, 0b11, 0b0000, 0b11, 0,
415 (outs DPR:$Dd), (ins DPR:$Dm),
416 IIC_fpUNA64, "vabs", ".f64\t$Dd, $Dm",
417 [(set DPR:$Dd, (fabs (f64 DPR:$Dm)))]>;
419 def VABSS : ASuIn<0b11101, 0b11, 0b0000, 0b11, 0,
420 (outs SPR:$Sd), (ins SPR:$Sm),
421 IIC_fpUNA32, "vabs", ".f32\t$Sd, $Sm",
422 [(set SPR:$Sd, (fabs SPR:$Sm))]> {
423 // Some single precision VFP instructions may be executed on both NEON and
424 // VFP pipelines on A8.
425 let D = VFPNeonA8Domain;
428 let Defs = [FPSCR_NZCV] in {
429 def VCMPEZD : ADuI<0b11101, 0b11, 0b0101, 0b11, 0,
430 (outs), (ins DPR:$Dd),
431 IIC_fpCMP64, "vcmpe", ".f64\t$Dd, #0",
432 [(arm_cmpfp0 (f64 DPR:$Dd))]> {
433 let Inst{3-0} = 0b0000;
437 def VCMPEZS : ASuI<0b11101, 0b11, 0b0101, 0b11, 0,
438 (outs), (ins SPR:$Sd),
439 IIC_fpCMP32, "vcmpe", ".f32\t$Sd, #0",
440 [(arm_cmpfp0 SPR:$Sd)]> {
441 let Inst{3-0} = 0b0000;
444 // Some single precision VFP instructions may be executed on both NEON and
445 // VFP pipelines on A8.
446 let D = VFPNeonA8Domain;
449 // FIXME: Verify encoding after integrated assembler is working.
450 def VCMPZD : ADuI<0b11101, 0b11, 0b0101, 0b01, 0,
451 (outs), (ins DPR:$Dd),
452 IIC_fpCMP64, "vcmp", ".f64\t$Dd, #0",
453 [/* For disassembly only; pattern left blank */]> {
454 let Inst{3-0} = 0b0000;
458 def VCMPZS : ASuI<0b11101, 0b11, 0b0101, 0b01, 0,
459 (outs), (ins SPR:$Sd),
460 IIC_fpCMP32, "vcmp", ".f32\t$Sd, #0",
461 [/* For disassembly only; pattern left blank */]> {
462 let Inst{3-0} = 0b0000;
465 // Some single precision VFP instructions may be executed on both NEON and
466 // VFP pipelines on A8.
467 let D = VFPNeonA8Domain;
469 } // Defs = [FPSCR_NZCV]
471 def VCVTDS : ASuI<0b11101, 0b11, 0b0111, 0b11, 0,
472 (outs DPR:$Dd), (ins SPR:$Sm),
473 IIC_fpCVTDS, "vcvt", ".f64.f32\t$Dd, $Sm",
474 [(set DPR:$Dd, (fextend SPR:$Sm))]> {
475 // Instruction operands.
479 // Encode instruction operands.
480 let Inst{3-0} = Sm{4-1};
482 let Inst{15-12} = Dd{3-0};
483 let Inst{22} = Dd{4};
486 // Special case encoding: bits 11-8 is 0b1011.
487 def VCVTSD : VFPAI<(outs SPR:$Sd), (ins DPR:$Dm), VFPUnaryFrm,
488 IIC_fpCVTSD, "vcvt", ".f32.f64\t$Sd, $Dm",
489 [(set SPR:$Sd, (fround DPR:$Dm))]> {
490 // Instruction operands.
494 // Encode instruction operands.
495 let Inst{3-0} = Dm{3-0};
497 let Inst{15-12} = Sd{4-1};
498 let Inst{22} = Sd{0};
500 let Inst{27-23} = 0b11101;
501 let Inst{21-16} = 0b110111;
502 let Inst{11-8} = 0b1011;
503 let Inst{7-6} = 0b11;
507 // Between half, single and double-precision. For disassembly only.
509 // FIXME: Verify encoding after integrated assembler is working.
510 def VCVTBHS: ASuI<0b11101, 0b11, 0b0010, 0b01, 0, (outs SPR:$Sd), (ins SPR:$Sm),
511 /* FIXME */ IIC_fpCVTSH, "vcvtb", ".f32.f16\t$Sd, $Sm",
512 [/* For disassembly only; pattern left blank */]>;
514 def VCVTBSH: ASuI<0b11101, 0b11, 0b0011, 0b01, 0, (outs SPR:$Sd), (ins SPR:$Sm),
515 /* FIXME */ IIC_fpCVTHS, "vcvtb", ".f16.f32\t$Sd, $Sm",
516 [/* For disassembly only; pattern left blank */]>;
518 def : Pat<(f32_to_f16 SPR:$a),
519 (i32 (COPY_TO_REGCLASS (VCVTBSH SPR:$a), GPR))>;
521 def : Pat<(f16_to_f32 GPR:$a),
522 (VCVTBHS (COPY_TO_REGCLASS GPR:$a, SPR))>;
524 def VCVTTHS: ASuI<0b11101, 0b11, 0b0010, 0b11, 0, (outs SPR:$Sd), (ins SPR:$Sm),
525 /* FIXME */ IIC_fpCVTSH, "vcvtt", ".f32.f16\t$Sd, $Sm",
526 [/* For disassembly only; pattern left blank */]>;
528 def VCVTTSH: ASuI<0b11101, 0b11, 0b0011, 0b11, 0, (outs SPR:$Sd), (ins SPR:$Sm),
529 /* FIXME */ IIC_fpCVTHS, "vcvtt", ".f16.f32\t$Sd, $Sm",
530 [/* For disassembly only; pattern left blank */]>;
532 def VCVTBHD : ADuI<0b11101, 0b11, 0b0010, 0b01, 0,
533 (outs DPR:$Dd), (ins SPR:$Sm),
534 NoItinerary, "vcvtb", ".f64.f16\t$Dd, $Sm",
535 []>, Requires<[HasV8FP]> {
536 // Instruction operands.
539 // Encode instruction operands.
540 let Inst{3-0} = Sm{4-1};
544 def VCVTBDH : ADuI<0b11101, 0b11, 0b0011, 0b01, 0,
545 (outs SPR:$Sd), (ins DPR:$Dm),
546 NoItinerary, "vcvtb", ".f16.f64\t$Sd, $Dm",
547 []>, Requires<[HasV8FP]> {
548 // Instruction operands.
552 // Encode instruction operands.
553 let Inst{3-0} = Dm{3-0};
555 let Inst{15-12} = Sd{4-1};
556 let Inst{22} = Sd{0};
559 def VCVTTHD : ADuI<0b11101, 0b11, 0b0010, 0b11, 0,
560 (outs DPR:$Dd), (ins SPR:$Sm),
561 NoItinerary, "vcvtt", ".f64.f16\t$Dd, $Sm",
562 []>, Requires<[HasV8FP]> {
563 // Instruction operands.
566 // Encode instruction operands.
567 let Inst{3-0} = Sm{4-1};
571 def VCVTTDH : ADuI<0b11101, 0b11, 0b0011, 0b11, 0,
572 (outs SPR:$Sd), (ins DPR:$Dm),
573 NoItinerary, "vcvtt", ".f16.f64\t$Sd, $Dm",
574 []>, Requires<[HasV8FP]> {
575 // Instruction operands.
579 // Encode instruction operands.
580 let Inst{15-12} = Sd{4-1};
581 let Inst{22} = Sd{0};
582 let Inst{3-0} = Dm{3-0};
586 multiclass vcvt_inst<string opc, bits<2> rm> {
587 let PostEncoderMethod = "" in {
588 def SS : ASuInp<0b11101, 0b11, 0b1100, 0b11, 0,
589 (outs SPR:$Sd), (ins SPR:$Sm),
590 NoItinerary, !strconcat("vcvt", opc, ".s32.f32\t$Sd, $Sm"),
591 []>, Requires<[HasV8FP]> {
592 let Inst{17-16} = rm;
595 def US : ASuInp<0b11101, 0b11, 0b1100, 0b01, 0,
596 (outs SPR:$Sd), (ins SPR:$Sm),
597 NoItinerary, !strconcat("vcvt", opc, ".u32.f32\t$Sd, $Sm"),
598 []>, Requires<[HasV8FP]> {
599 let Inst{17-16} = rm;
602 def SD : ASuInp<0b11101, 0b11, 0b1100, 0b11, 0,
603 (outs SPR:$Sd), (ins DPR:$Dm),
604 NoItinerary, !strconcat("vcvt", opc, ".s32.f64\t$Sd, $Dm"),
605 []>, Requires<[HasV8FP]> {
608 let Inst{17-16} = rm;
610 // Encode instruction operands
611 let Inst{3-0} = Dm{3-0};
616 def UD : ASuInp<0b11101, 0b11, 0b1100, 0b01, 0,
617 (outs SPR:$Sd), (ins DPR:$Dm),
618 NoItinerary, !strconcat("vcvt", opc, ".u32.f64\t$Sd, $Dm"),
619 []>, Requires<[HasV8FP]> {
622 let Inst{17-16} = rm;
624 // Encode instruction operands
625 let Inst{3-0} = Dm{3-0};
632 defm VCVTA : vcvt_inst<"a", 0b00>;
633 defm VCVTN : vcvt_inst<"n", 0b01>;
634 defm VCVTP : vcvt_inst<"p", 0b10>;
635 defm VCVTM : vcvt_inst<"m", 0b11>;
637 def VNEGD : ADuI<0b11101, 0b11, 0b0001, 0b01, 0,
638 (outs DPR:$Dd), (ins DPR:$Dm),
639 IIC_fpUNA64, "vneg", ".f64\t$Dd, $Dm",
640 [(set DPR:$Dd, (fneg (f64 DPR:$Dm)))]>;
642 def VNEGS : ASuIn<0b11101, 0b11, 0b0001, 0b01, 0,
643 (outs SPR:$Sd), (ins SPR:$Sm),
644 IIC_fpUNA32, "vneg", ".f32\t$Sd, $Sm",
645 [(set SPR:$Sd, (fneg SPR:$Sm))]> {
646 // Some single precision VFP instructions may be executed on both NEON and
647 // VFP pipelines on A8.
648 let D = VFPNeonA8Domain;
651 multiclass vrint_inst_zrx<string opc, bit op, bit op2> {
652 def S : ASuI<0b11101, 0b11, 0b0110, 0b11, 0,
653 (outs SPR:$Sd), (ins SPR:$Sm),
654 NoItinerary, !strconcat("vrint", opc), ".f32\t$Sd, $Sm",
655 []>, Requires<[HasV8FP]> {
659 def D : ADuI<0b11101, 0b11, 0b0110, 0b11, 0,
660 (outs DPR:$Dd), (ins DPR:$Dm),
661 NoItinerary, !strconcat("vrint", opc), ".f64\t$Dd, $Dm",
662 []>, Requires<[HasV8FP]> {
668 defm VRINTZ : vrint_inst_zrx<"z", 0, 1>;
669 defm VRINTR : vrint_inst_zrx<"r", 0, 0>;
670 defm VRINTX : vrint_inst_zrx<"x", 1, 0>;
672 def VSQRTD : ADuI<0b11101, 0b11, 0b0001, 0b11, 0,
673 (outs DPR:$Dd), (ins DPR:$Dm),
674 IIC_fpSQRT64, "vsqrt", ".f64\t$Dd, $Dm",
675 [(set DPR:$Dd, (fsqrt (f64 DPR:$Dm)))]>;
677 def VSQRTS : ASuI<0b11101, 0b11, 0b0001, 0b11, 0,
678 (outs SPR:$Sd), (ins SPR:$Sm),
679 IIC_fpSQRT32, "vsqrt", ".f32\t$Sd, $Sm",
680 [(set SPR:$Sd, (fsqrt SPR:$Sm))]>;
682 let neverHasSideEffects = 1 in {
683 def VMOVD : ADuI<0b11101, 0b11, 0b0000, 0b01, 0,
684 (outs DPR:$Dd), (ins DPR:$Dm),
685 IIC_fpUNA64, "vmov", ".f64\t$Dd, $Dm", []>;
687 def VMOVS : ASuI<0b11101, 0b11, 0b0000, 0b01, 0,
688 (outs SPR:$Sd), (ins SPR:$Sm),
689 IIC_fpUNA32, "vmov", ".f32\t$Sd, $Sm", []>;
690 } // neverHasSideEffects
692 //===----------------------------------------------------------------------===//
693 // FP <-> GPR Copies. Int <-> FP Conversions.
696 def VMOVRS : AVConv2I<0b11100001, 0b1010,
697 (outs GPR:$Rt), (ins SPR:$Sn),
698 IIC_fpMOVSI, "vmov", "\t$Rt, $Sn",
699 [(set GPR:$Rt, (bitconvert SPR:$Sn))]> {
700 // Instruction operands.
704 // Encode instruction operands.
705 let Inst{19-16} = Sn{4-1};
707 let Inst{15-12} = Rt;
709 let Inst{6-5} = 0b00;
710 let Inst{3-0} = 0b0000;
712 // Some single precision VFP instructions may be executed on both NEON and VFP
714 let D = VFPNeonDomain;
717 // Bitcast i32 -> f32. NEON prefers to use VMOVDRR.
718 def VMOVSR : AVConv4I<0b11100000, 0b1010,
719 (outs SPR:$Sn), (ins GPR:$Rt),
720 IIC_fpMOVIS, "vmov", "\t$Sn, $Rt",
721 [(set SPR:$Sn, (bitconvert GPR:$Rt))]>,
722 Requires<[HasVFP2, UseVMOVSR]> {
723 // Instruction operands.
727 // Encode instruction operands.
728 let Inst{19-16} = Sn{4-1};
730 let Inst{15-12} = Rt;
732 let Inst{6-5} = 0b00;
733 let Inst{3-0} = 0b0000;
735 // Some single precision VFP instructions may be executed on both NEON and VFP
737 let D = VFPNeonDomain;
740 let neverHasSideEffects = 1 in {
741 def VMOVRRD : AVConv3I<0b11000101, 0b1011,
742 (outs GPR:$Rt, GPR:$Rt2), (ins DPR:$Dm),
743 IIC_fpMOVDI, "vmov", "\t$Rt, $Rt2, $Dm",
744 [/* FIXME: Can't write pattern for multiple result instr*/]> {
745 // Instruction operands.
750 // Encode instruction operands.
751 let Inst{3-0} = Dm{3-0};
753 let Inst{15-12} = Rt;
754 let Inst{19-16} = Rt2;
756 let Inst{7-6} = 0b00;
758 // Some single precision VFP instructions may be executed on both NEON and VFP
760 let D = VFPNeonDomain;
763 def VMOVRRS : AVConv3I<0b11000101, 0b1010,
764 (outs GPR:$Rt, GPR:$Rt2), (ins SPR:$src1, SPR:$src2),
765 IIC_fpMOVDI, "vmov", "\t$Rt, $Rt2, $src1, $src2",
766 [/* For disassembly only; pattern left blank */]> {
771 // Encode instruction operands.
772 let Inst{3-0} = src1{4-1};
773 let Inst{5} = src1{0};
774 let Inst{15-12} = Rt;
775 let Inst{19-16} = Rt2;
777 let Inst{7-6} = 0b00;
779 // Some single precision VFP instructions may be executed on both NEON and VFP
781 let D = VFPNeonDomain;
782 let DecoderMethod = "DecodeVMOVRRS";
784 } // neverHasSideEffects
789 def VMOVDRR : AVConv5I<0b11000100, 0b1011,
790 (outs DPR:$Dm), (ins GPR:$Rt, GPR:$Rt2),
791 IIC_fpMOVID, "vmov", "\t$Dm, $Rt, $Rt2",
792 [(set DPR:$Dm, (arm_fmdrr GPR:$Rt, GPR:$Rt2))]> {
793 // Instruction operands.
798 // Encode instruction operands.
799 let Inst{3-0} = Dm{3-0};
801 let Inst{15-12} = Rt;
802 let Inst{19-16} = Rt2;
804 let Inst{7-6} = 0b00;
806 // Some single precision VFP instructions may be executed on both NEON and VFP
808 let D = VFPNeonDomain;
811 let neverHasSideEffects = 1 in
812 def VMOVSRR : AVConv5I<0b11000100, 0b1010,
813 (outs SPR:$dst1, SPR:$dst2), (ins GPR:$src1, GPR:$src2),
814 IIC_fpMOVID, "vmov", "\t$dst1, $dst2, $src1, $src2",
815 [/* For disassembly only; pattern left blank */]> {
816 // Instruction operands.
821 // Encode instruction operands.
822 let Inst{3-0} = dst1{4-1};
823 let Inst{5} = dst1{0};
824 let Inst{15-12} = src1;
825 let Inst{19-16} = src2;
827 let Inst{7-6} = 0b00;
829 // Some single precision VFP instructions may be executed on both NEON and VFP
831 let D = VFPNeonDomain;
833 let DecoderMethod = "DecodeVMOVSRR";
839 // FMRX: SPR system reg -> GPR
841 // FMXR: GPR -> VFP system reg
846 class AVConv1IDs_Encode<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3,
847 bits<4> opcod4, dag oops, dag iops,
848 InstrItinClass itin, string opc, string asm,
850 : AVConv1I<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm,
852 // Instruction operands.
856 // Encode instruction operands.
857 let Inst{3-0} = Sm{4-1};
859 let Inst{15-12} = Dd{3-0};
860 let Inst{22} = Dd{4};
863 class AVConv1InSs_Encode<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3,
864 bits<4> opcod4, dag oops, dag iops,InstrItinClass itin,
865 string opc, string asm, list<dag> pattern>
866 : AVConv1In<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm,
868 // Instruction operands.
872 // Encode instruction operands.
873 let Inst{3-0} = Sm{4-1};
875 let Inst{15-12} = Sd{4-1};
876 let Inst{22} = Sd{0};
879 def VSITOD : AVConv1IDs_Encode<0b11101, 0b11, 0b1000, 0b1011,
880 (outs DPR:$Dd), (ins SPR:$Sm),
881 IIC_fpCVTID, "vcvt", ".f64.s32\t$Dd, $Sm",
882 [(set DPR:$Dd, (f64 (arm_sitof SPR:$Sm)))]> {
883 let Inst{7} = 1; // s32
886 def VSITOS : AVConv1InSs_Encode<0b11101, 0b11, 0b1000, 0b1010,
887 (outs SPR:$Sd),(ins SPR:$Sm),
888 IIC_fpCVTIS, "vcvt", ".f32.s32\t$Sd, $Sm",
889 [(set SPR:$Sd, (arm_sitof SPR:$Sm))]> {
890 let Inst{7} = 1; // s32
892 // Some single precision VFP instructions may be executed on both NEON and
893 // VFP pipelines on A8.
894 let D = VFPNeonA8Domain;
897 def VUITOD : AVConv1IDs_Encode<0b11101, 0b11, 0b1000, 0b1011,
898 (outs DPR:$Dd), (ins SPR:$Sm),
899 IIC_fpCVTID, "vcvt", ".f64.u32\t$Dd, $Sm",
900 [(set DPR:$Dd, (f64 (arm_uitof SPR:$Sm)))]> {
901 let Inst{7} = 0; // u32
904 def VUITOS : AVConv1InSs_Encode<0b11101, 0b11, 0b1000, 0b1010,
905 (outs SPR:$Sd), (ins SPR:$Sm),
906 IIC_fpCVTIS, "vcvt", ".f32.u32\t$Sd, $Sm",
907 [(set SPR:$Sd, (arm_uitof SPR:$Sm))]> {
908 let Inst{7} = 0; // u32
910 // Some single precision VFP instructions may be executed on both NEON and
911 // VFP pipelines on A8.
912 let D = VFPNeonA8Domain;
917 class AVConv1IsD_Encode<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3,
918 bits<4> opcod4, dag oops, dag iops,
919 InstrItinClass itin, string opc, string asm,
921 : AVConv1I<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm,
923 // Instruction operands.
927 // Encode instruction operands.
928 let Inst{3-0} = Dm{3-0};
930 let Inst{15-12} = Sd{4-1};
931 let Inst{22} = Sd{0};
934 class AVConv1InsS_Encode<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3,
935 bits<4> opcod4, dag oops, dag iops,
936 InstrItinClass itin, string opc, string asm,
938 : AVConv1In<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm,
940 // Instruction operands.
944 // Encode instruction operands.
945 let Inst{3-0} = Sm{4-1};
947 let Inst{15-12} = Sd{4-1};
948 let Inst{22} = Sd{0};
951 // Always set Z bit in the instruction, i.e. "round towards zero" variants.
952 def VTOSIZD : AVConv1IsD_Encode<0b11101, 0b11, 0b1101, 0b1011,
953 (outs SPR:$Sd), (ins DPR:$Dm),
954 IIC_fpCVTDI, "vcvt", ".s32.f64\t$Sd, $Dm",
955 [(set SPR:$Sd, (arm_ftosi (f64 DPR:$Dm)))]> {
956 let Inst{7} = 1; // Z bit
959 def VTOSIZS : AVConv1InsS_Encode<0b11101, 0b11, 0b1101, 0b1010,
960 (outs SPR:$Sd), (ins SPR:$Sm),
961 IIC_fpCVTSI, "vcvt", ".s32.f32\t$Sd, $Sm",
962 [(set SPR:$Sd, (arm_ftosi SPR:$Sm))]> {
963 let Inst{7} = 1; // Z bit
965 // Some single precision VFP instructions may be executed on both NEON and
966 // VFP pipelines on A8.
967 let D = VFPNeonA8Domain;
970 def VTOUIZD : AVConv1IsD_Encode<0b11101, 0b11, 0b1100, 0b1011,
971 (outs SPR:$Sd), (ins DPR:$Dm),
972 IIC_fpCVTDI, "vcvt", ".u32.f64\t$Sd, $Dm",
973 [(set SPR:$Sd, (arm_ftoui (f64 DPR:$Dm)))]> {
974 let Inst{7} = 1; // Z bit
977 def VTOUIZS : AVConv1InsS_Encode<0b11101, 0b11, 0b1100, 0b1010,
978 (outs SPR:$Sd), (ins SPR:$Sm),
979 IIC_fpCVTSI, "vcvt", ".u32.f32\t$Sd, $Sm",
980 [(set SPR:$Sd, (arm_ftoui SPR:$Sm))]> {
981 let Inst{7} = 1; // Z bit
983 // Some single precision VFP instructions may be executed on both NEON and
984 // VFP pipelines on A8.
985 let D = VFPNeonA8Domain;
988 // And the Z bit '0' variants, i.e. use the rounding mode specified by FPSCR.
989 let Uses = [FPSCR] in {
990 // FIXME: Verify encoding after integrated assembler is working.
991 def VTOSIRD : AVConv1IsD_Encode<0b11101, 0b11, 0b1101, 0b1011,
992 (outs SPR:$Sd), (ins DPR:$Dm),
993 IIC_fpCVTDI, "vcvtr", ".s32.f64\t$Sd, $Dm",
994 [(set SPR:$Sd, (int_arm_vcvtr (f64 DPR:$Dm)))]>{
995 let Inst{7} = 0; // Z bit
998 def VTOSIRS : AVConv1InsS_Encode<0b11101, 0b11, 0b1101, 0b1010,
999 (outs SPR:$Sd), (ins SPR:$Sm),
1000 IIC_fpCVTSI, "vcvtr", ".s32.f32\t$Sd, $Sm",
1001 [(set SPR:$Sd, (int_arm_vcvtr SPR:$Sm))]> {
1002 let Inst{7} = 0; // Z bit
1005 def VTOUIRD : AVConv1IsD_Encode<0b11101, 0b11, 0b1100, 0b1011,
1006 (outs SPR:$Sd), (ins DPR:$Dm),
1007 IIC_fpCVTDI, "vcvtr", ".u32.f64\t$Sd, $Dm",
1008 [(set SPR:$Sd, (int_arm_vcvtru(f64 DPR:$Dm)))]>{
1009 let Inst{7} = 0; // Z bit
1012 def VTOUIRS : AVConv1InsS_Encode<0b11101, 0b11, 0b1100, 0b1010,
1013 (outs SPR:$Sd), (ins SPR:$Sm),
1014 IIC_fpCVTSI, "vcvtr", ".u32.f32\t$Sd, $Sm",
1015 [(set SPR:$Sd, (int_arm_vcvtru SPR:$Sm))]> {
1016 let Inst{7} = 0; // Z bit
1020 // Convert between floating-point and fixed-point
1021 // Data type for fixed-point naming convention:
1022 // S16 (U=0, sx=0) -> SH
1023 // U16 (U=1, sx=0) -> UH
1024 // S32 (U=0, sx=1) -> SL
1025 // U32 (U=1, sx=1) -> UL
1027 let Constraints = "$a = $dst" in {
1029 // FP to Fixed-Point:
1031 // Single Precision register
1032 class AVConv1XInsS_Encode<bits<5> op1, bits<2> op2, bits<4> op3, bits<4> op4,
1033 bit op5, dag oops, dag iops, InstrItinClass itin,
1034 string opc, string asm, list<dag> pattern>
1035 : AVConv1XI<op1, op2, op3, op4, op5, oops, iops, itin, opc, asm, pattern>,
1036 Sched<[WriteCvtFP]> {
1038 // if dp_operation then UInt(D:Vd) else UInt(Vd:D);
1039 let Inst{22} = dst{0};
1040 let Inst{15-12} = dst{4-1};
1043 // Double Precision register
1044 class AVConv1XInsD_Encode<bits<5> op1, bits<2> op2, bits<4> op3, bits<4> op4,
1045 bit op5, dag oops, dag iops, InstrItinClass itin,
1046 string opc, string asm, list<dag> pattern>
1047 : AVConv1XI<op1, op2, op3, op4, op5, oops, iops, itin, opc, asm, pattern>,
1048 Sched<[WriteCvtFP]> {
1050 // if dp_operation then UInt(D:Vd) else UInt(Vd:D);
1051 let Inst{22} = dst{4};
1052 let Inst{15-12} = dst{3-0};
1055 def VTOSHS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1110, 0b1010, 0,
1056 (outs SPR:$dst), (ins SPR:$a, fbits16:$fbits),
1057 IIC_fpCVTSI, "vcvt", ".s16.f32\t$dst, $a, $fbits", []> {
1058 // Some single precision VFP instructions may be executed on both NEON and
1059 // VFP pipelines on A8.
1060 let D = VFPNeonA8Domain;
1063 def VTOUHS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1111, 0b1010, 0,
1064 (outs SPR:$dst), (ins SPR:$a, fbits16:$fbits),
1065 IIC_fpCVTSI, "vcvt", ".u16.f32\t$dst, $a, $fbits", []> {
1066 // Some single precision VFP instructions may be executed on both NEON and
1067 // VFP pipelines on A8.
1068 let D = VFPNeonA8Domain;
1071 def VTOSLS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1110, 0b1010, 1,
1072 (outs SPR:$dst), (ins SPR:$a, fbits32:$fbits),
1073 IIC_fpCVTSI, "vcvt", ".s32.f32\t$dst, $a, $fbits", []> {
1074 // Some single precision VFP instructions may be executed on both NEON and
1075 // VFP pipelines on A8.
1076 let D = VFPNeonA8Domain;
1079 def VTOULS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1111, 0b1010, 1,
1080 (outs SPR:$dst), (ins SPR:$a, fbits32:$fbits),
1081 IIC_fpCVTSI, "vcvt", ".u32.f32\t$dst, $a, $fbits", []> {
1082 // Some single precision VFP instructions may be executed on both NEON and
1083 // VFP pipelines on A8.
1084 let D = VFPNeonA8Domain;
1087 def VTOSHD : AVConv1XInsD_Encode<0b11101, 0b11, 0b1110, 0b1011, 0,
1088 (outs DPR:$dst), (ins DPR:$a, fbits16:$fbits),
1089 IIC_fpCVTDI, "vcvt", ".s16.f64\t$dst, $a, $fbits", []>;
1091 def VTOUHD : AVConv1XInsD_Encode<0b11101, 0b11, 0b1111, 0b1011, 0,
1092 (outs DPR:$dst), (ins DPR:$a, fbits16:$fbits),
1093 IIC_fpCVTDI, "vcvt", ".u16.f64\t$dst, $a, $fbits", []>;
1095 def VTOSLD : AVConv1XInsD_Encode<0b11101, 0b11, 0b1110, 0b1011, 1,
1096 (outs DPR:$dst), (ins DPR:$a, fbits32:$fbits),
1097 IIC_fpCVTDI, "vcvt", ".s32.f64\t$dst, $a, $fbits", []>;
1099 def VTOULD : AVConv1XInsD_Encode<0b11101, 0b11, 0b1111, 0b1011, 1,
1100 (outs DPR:$dst), (ins DPR:$a, fbits32:$fbits),
1101 IIC_fpCVTDI, "vcvt", ".u32.f64\t$dst, $a, $fbits", []>;
1103 // Fixed-Point to FP:
1105 def VSHTOS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1010, 0b1010, 0,
1106 (outs SPR:$dst), (ins SPR:$a, fbits16:$fbits),
1107 IIC_fpCVTIS, "vcvt", ".f32.s16\t$dst, $a, $fbits", []> {
1108 // Some single precision VFP instructions may be executed on both NEON and
1109 // VFP pipelines on A8.
1110 let D = VFPNeonA8Domain;
1113 def VUHTOS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1011, 0b1010, 0,
1114 (outs SPR:$dst), (ins SPR:$a, fbits16:$fbits),
1115 IIC_fpCVTIS, "vcvt", ".f32.u16\t$dst, $a, $fbits", []> {
1116 // Some single precision VFP instructions may be executed on both NEON and
1117 // VFP pipelines on A8.
1118 let D = VFPNeonA8Domain;
1121 def VSLTOS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1010, 0b1010, 1,
1122 (outs SPR:$dst), (ins SPR:$a, fbits32:$fbits),
1123 IIC_fpCVTIS, "vcvt", ".f32.s32\t$dst, $a, $fbits", []> {
1124 // Some single precision VFP instructions may be executed on both NEON and
1125 // VFP pipelines on A8.
1126 let D = VFPNeonA8Domain;
1129 def VULTOS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1011, 0b1010, 1,
1130 (outs SPR:$dst), (ins SPR:$a, fbits32:$fbits),
1131 IIC_fpCVTIS, "vcvt", ".f32.u32\t$dst, $a, $fbits", []> {
1132 // Some single precision VFP instructions may be executed on both NEON and
1133 // VFP pipelines on A8.
1134 let D = VFPNeonA8Domain;
1137 def VSHTOD : AVConv1XInsD_Encode<0b11101, 0b11, 0b1010, 0b1011, 0,
1138 (outs DPR:$dst), (ins DPR:$a, fbits16:$fbits),
1139 IIC_fpCVTID, "vcvt", ".f64.s16\t$dst, $a, $fbits", []>;
1141 def VUHTOD : AVConv1XInsD_Encode<0b11101, 0b11, 0b1011, 0b1011, 0,
1142 (outs DPR:$dst), (ins DPR:$a, fbits16:$fbits),
1143 IIC_fpCVTID, "vcvt", ".f64.u16\t$dst, $a, $fbits", []>;
1145 def VSLTOD : AVConv1XInsD_Encode<0b11101, 0b11, 0b1010, 0b1011, 1,
1146 (outs DPR:$dst), (ins DPR:$a, fbits32:$fbits),
1147 IIC_fpCVTID, "vcvt", ".f64.s32\t$dst, $a, $fbits", []>;
1149 def VULTOD : AVConv1XInsD_Encode<0b11101, 0b11, 0b1011, 0b1011, 1,
1150 (outs DPR:$dst), (ins DPR:$a, fbits32:$fbits),
1151 IIC_fpCVTID, "vcvt", ".f64.u32\t$dst, $a, $fbits", []>;
1153 } // End of 'let Constraints = "$a = $dst" in'
1155 //===----------------------------------------------------------------------===//
1156 // FP Multiply-Accumulate Operations.
1159 def VMLAD : ADbI<0b11100, 0b00, 0, 0,
1160 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
1161 IIC_fpMAC64, "vmla", ".f64\t$Dd, $Dn, $Dm",
1162 [(set DPR:$Dd, (fadd_mlx (fmul_su DPR:$Dn, DPR:$Dm),
1163 (f64 DPR:$Ddin)))]>,
1164 RegConstraint<"$Ddin = $Dd">,
1165 Requires<[HasVFP2,UseFPVMLx,DontUseFusedMAC]>;
1167 def VMLAS : ASbIn<0b11100, 0b00, 0, 0,
1168 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
1169 IIC_fpMAC32, "vmla", ".f32\t$Sd, $Sn, $Sm",
1170 [(set SPR:$Sd, (fadd_mlx (fmul_su SPR:$Sn, SPR:$Sm),
1172 RegConstraint<"$Sdin = $Sd">,
1173 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx,DontUseFusedMAC]> {
1174 // Some single precision VFP instructions may be executed on both NEON and
1175 // VFP pipelines on A8.
1176 let D = VFPNeonA8Domain;
1179 def : Pat<(fadd_mlx DPR:$dstin, (fmul_su DPR:$a, (f64 DPR:$b))),
1180 (VMLAD DPR:$dstin, DPR:$a, DPR:$b)>,
1181 Requires<[HasVFP2,UseFPVMLx,DontUseFusedMAC]>;
1182 def : Pat<(fadd_mlx SPR:$dstin, (fmul_su SPR:$a, SPR:$b)),
1183 (VMLAS SPR:$dstin, SPR:$a, SPR:$b)>,
1184 Requires<[HasVFP2,DontUseNEONForFP, UseFPVMLx,DontUseFusedMAC]>;
1186 def VMLSD : ADbI<0b11100, 0b00, 1, 0,
1187 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
1188 IIC_fpMAC64, "vmls", ".f64\t$Dd, $Dn, $Dm",
1189 [(set DPR:$Dd, (fadd_mlx (fneg (fmul_su DPR:$Dn,DPR:$Dm)),
1190 (f64 DPR:$Ddin)))]>,
1191 RegConstraint<"$Ddin = $Dd">,
1192 Requires<[HasVFP2,UseFPVMLx,DontUseFusedMAC]>;
1194 def VMLSS : ASbIn<0b11100, 0b00, 1, 0,
1195 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
1196 IIC_fpMAC32, "vmls", ".f32\t$Sd, $Sn, $Sm",
1197 [(set SPR:$Sd, (fadd_mlx (fneg (fmul_su SPR:$Sn, SPR:$Sm)),
1199 RegConstraint<"$Sdin = $Sd">,
1200 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx,DontUseFusedMAC]> {
1201 // Some single precision VFP instructions may be executed on both NEON and
1202 // VFP pipelines on A8.
1203 let D = VFPNeonA8Domain;
1206 def : Pat<(fsub_mlx DPR:$dstin, (fmul_su DPR:$a, (f64 DPR:$b))),
1207 (VMLSD DPR:$dstin, DPR:$a, DPR:$b)>,
1208 Requires<[HasVFP2,UseFPVMLx,DontUseFusedMAC]>;
1209 def : Pat<(fsub_mlx SPR:$dstin, (fmul_su SPR:$a, SPR:$b)),
1210 (VMLSS SPR:$dstin, SPR:$a, SPR:$b)>,
1211 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx,DontUseFusedMAC]>;
1213 def VNMLAD : ADbI<0b11100, 0b01, 1, 0,
1214 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
1215 IIC_fpMAC64, "vnmla", ".f64\t$Dd, $Dn, $Dm",
1216 [(set DPR:$Dd,(fsub_mlx (fneg (fmul_su DPR:$Dn,DPR:$Dm)),
1217 (f64 DPR:$Ddin)))]>,
1218 RegConstraint<"$Ddin = $Dd">,
1219 Requires<[HasVFP2,UseFPVMLx,DontUseFusedMAC]>;
1221 def VNMLAS : ASbI<0b11100, 0b01, 1, 0,
1222 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
1223 IIC_fpMAC32, "vnmla", ".f32\t$Sd, $Sn, $Sm",
1224 [(set SPR:$Sd, (fsub_mlx (fneg (fmul_su SPR:$Sn, SPR:$Sm)),
1226 RegConstraint<"$Sdin = $Sd">,
1227 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx,DontUseFusedMAC]> {
1228 // Some single precision VFP instructions may be executed on both NEON and
1229 // VFP pipelines on A8.
1230 let D = VFPNeonA8Domain;
1233 def : Pat<(fsub_mlx (fneg (fmul_su DPR:$a, (f64 DPR:$b))), DPR:$dstin),
1234 (VNMLAD DPR:$dstin, DPR:$a, DPR:$b)>,
1235 Requires<[HasVFP2,UseFPVMLx,DontUseFusedMAC]>;
1236 def : Pat<(fsub_mlx (fneg (fmul_su SPR:$a, SPR:$b)), SPR:$dstin),
1237 (VNMLAS SPR:$dstin, SPR:$a, SPR:$b)>,
1238 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx,DontUseFusedMAC]>;
1240 def VNMLSD : ADbI<0b11100, 0b01, 0, 0,
1241 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
1242 IIC_fpMAC64, "vnmls", ".f64\t$Dd, $Dn, $Dm",
1243 [(set DPR:$Dd, (fsub_mlx (fmul_su DPR:$Dn, DPR:$Dm),
1244 (f64 DPR:$Ddin)))]>,
1245 RegConstraint<"$Ddin = $Dd">,
1246 Requires<[HasVFP2,UseFPVMLx,DontUseFusedMAC]>;
1248 def VNMLSS : ASbI<0b11100, 0b01, 0, 0,
1249 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
1250 IIC_fpMAC32, "vnmls", ".f32\t$Sd, $Sn, $Sm",
1251 [(set SPR:$Sd, (fsub_mlx (fmul_su SPR:$Sn, SPR:$Sm), SPR:$Sdin))]>,
1252 RegConstraint<"$Sdin = $Sd">,
1253 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx,DontUseFusedMAC]> {
1254 // Some single precision VFP instructions may be executed on both NEON and
1255 // VFP pipelines on A8.
1256 let D = VFPNeonA8Domain;
1259 def : Pat<(fsub_mlx (fmul_su DPR:$a, (f64 DPR:$b)), DPR:$dstin),
1260 (VNMLSD DPR:$dstin, DPR:$a, DPR:$b)>,
1261 Requires<[HasVFP2,UseFPVMLx,DontUseFusedMAC]>;
1262 def : Pat<(fsub_mlx (fmul_su SPR:$a, SPR:$b), SPR:$dstin),
1263 (VNMLSS SPR:$dstin, SPR:$a, SPR:$b)>,
1264 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx,DontUseFusedMAC]>;
1266 //===----------------------------------------------------------------------===//
1267 // Fused FP Multiply-Accumulate Operations.
1269 def VFMAD : ADbI<0b11101, 0b10, 0, 0,
1270 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
1271 IIC_fpFMAC64, "vfma", ".f64\t$Dd, $Dn, $Dm",
1272 [(set DPR:$Dd, (fadd_mlx (fmul_su DPR:$Dn, DPR:$Dm),
1273 (f64 DPR:$Ddin)))]>,
1274 RegConstraint<"$Ddin = $Dd">,
1275 Requires<[HasVFP4,UseFusedMAC]>;
1277 def VFMAS : ASbIn<0b11101, 0b10, 0, 0,
1278 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
1279 IIC_fpFMAC32, "vfma", ".f32\t$Sd, $Sn, $Sm",
1280 [(set SPR:$Sd, (fadd_mlx (fmul_su SPR:$Sn, SPR:$Sm),
1282 RegConstraint<"$Sdin = $Sd">,
1283 Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]> {
1284 // Some single precision VFP instructions may be executed on both NEON and
1288 def : Pat<(fadd_mlx DPR:$dstin, (fmul_su DPR:$a, (f64 DPR:$b))),
1289 (VFMAD DPR:$dstin, DPR:$a, DPR:$b)>,
1290 Requires<[HasVFP4,UseFusedMAC]>;
1291 def : Pat<(fadd_mlx SPR:$dstin, (fmul_su SPR:$a, SPR:$b)),
1292 (VFMAS SPR:$dstin, SPR:$a, SPR:$b)>,
1293 Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]>;
1295 // Match @llvm.fma.* intrinsics
1296 // (fma x, y, z) -> (vfms z, x, y)
1297 def : Pat<(f64 (fma DPR:$Dn, DPR:$Dm, DPR:$Ddin)),
1298 (VFMAD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>,
1299 Requires<[HasVFP4]>;
1300 def : Pat<(f32 (fma SPR:$Sn, SPR:$Sm, SPR:$Sdin)),
1301 (VFMAS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
1302 Requires<[HasVFP4]>;
1304 def VFMSD : ADbI<0b11101, 0b10, 1, 0,
1305 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
1306 IIC_fpFMAC64, "vfms", ".f64\t$Dd, $Dn, $Dm",
1307 [(set DPR:$Dd, (fadd_mlx (fneg (fmul_su DPR:$Dn,DPR:$Dm)),
1308 (f64 DPR:$Ddin)))]>,
1309 RegConstraint<"$Ddin = $Dd">,
1310 Requires<[HasVFP4,UseFusedMAC]>;
1312 def VFMSS : ASbIn<0b11101, 0b10, 1, 0,
1313 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
1314 IIC_fpFMAC32, "vfms", ".f32\t$Sd, $Sn, $Sm",
1315 [(set SPR:$Sd, (fadd_mlx (fneg (fmul_su SPR:$Sn, SPR:$Sm)),
1317 RegConstraint<"$Sdin = $Sd">,
1318 Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]> {
1319 // Some single precision VFP instructions may be executed on both NEON and
1323 def : Pat<(fsub_mlx DPR:$dstin, (fmul_su DPR:$a, (f64 DPR:$b))),
1324 (VFMSD DPR:$dstin, DPR:$a, DPR:$b)>,
1325 Requires<[HasVFP4,UseFusedMAC]>;
1326 def : Pat<(fsub_mlx SPR:$dstin, (fmul_su SPR:$a, SPR:$b)),
1327 (VFMSS SPR:$dstin, SPR:$a, SPR:$b)>,
1328 Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]>;
1330 // Match @llvm.fma.* intrinsics
1331 // (fma (fneg x), y, z) -> (vfms z, x, y)
1332 def : Pat<(f64 (fma (fneg DPR:$Dn), DPR:$Dm, DPR:$Ddin)),
1333 (VFMSD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>,
1334 Requires<[HasVFP4]>;
1335 def : Pat<(f32 (fma (fneg SPR:$Sn), SPR:$Sm, SPR:$Sdin)),
1336 (VFMSS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
1337 Requires<[HasVFP4]>;
1338 // (fma x, (fneg y), z) -> (vfms z, x, y)
1339 def : Pat<(f64 (fma DPR:$Dn, (fneg DPR:$Dm), DPR:$Ddin)),
1340 (VFMSD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>,
1341 Requires<[HasVFP4]>;
1342 def : Pat<(f32 (fma SPR:$Sn, (fneg SPR:$Sm), SPR:$Sdin)),
1343 (VFMSS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
1344 Requires<[HasVFP4]>;
1346 def VFNMAD : ADbI<0b11101, 0b01, 1, 0,
1347 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
1348 IIC_fpFMAC64, "vfnma", ".f64\t$Dd, $Dn, $Dm",
1349 [(set DPR:$Dd,(fsub_mlx (fneg (fmul_su DPR:$Dn,DPR:$Dm)),
1350 (f64 DPR:$Ddin)))]>,
1351 RegConstraint<"$Ddin = $Dd">,
1352 Requires<[HasVFP4,UseFusedMAC]>;
1354 def VFNMAS : ASbI<0b11101, 0b01, 1, 0,
1355 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
1356 IIC_fpFMAC32, "vfnma", ".f32\t$Sd, $Sn, $Sm",
1357 [(set SPR:$Sd, (fsub_mlx (fneg (fmul_su SPR:$Sn, SPR:$Sm)),
1359 RegConstraint<"$Sdin = $Sd">,
1360 Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]> {
1361 // Some single precision VFP instructions may be executed on both NEON and
1365 def : Pat<(fsub_mlx (fneg (fmul_su DPR:$a, (f64 DPR:$b))), DPR:$dstin),
1366 (VFNMAD DPR:$dstin, DPR:$a, DPR:$b)>,
1367 Requires<[HasVFP4,UseFusedMAC]>;
1368 def : Pat<(fsub_mlx (fneg (fmul_su SPR:$a, SPR:$b)), SPR:$dstin),
1369 (VFNMAS SPR:$dstin, SPR:$a, SPR:$b)>,
1370 Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]>;
1372 // Match @llvm.fma.* intrinsics
1373 // (fneg (fma x, y, z)) -> (vfnma z, x, y)
1374 def : Pat<(fneg (fma (f64 DPR:$Dn), (f64 DPR:$Dm), (f64 DPR:$Ddin))),
1375 (VFNMAD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>,
1376 Requires<[HasVFP4]>;
1377 def : Pat<(fneg (fma (f32 SPR:$Sn), (f32 SPR:$Sm), (f32 SPR:$Sdin))),
1378 (VFNMAS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
1379 Requires<[HasVFP4]>;
1380 // (fma (fneg x), y, (fneg z)) -> (vfnma z, x, y)
1381 def : Pat<(f64 (fma (fneg DPR:$Dn), DPR:$Dm, (fneg DPR:$Ddin))),
1382 (VFNMAD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>,
1383 Requires<[HasVFP4]>;
1384 def : Pat<(f32 (fma (fneg SPR:$Sn), SPR:$Sm, (fneg SPR:$Sdin))),
1385 (VFNMAS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
1386 Requires<[HasVFP4]>;
1388 def VFNMSD : ADbI<0b11101, 0b01, 0, 0,
1389 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
1390 IIC_fpFMAC64, "vfnms", ".f64\t$Dd, $Dn, $Dm",
1391 [(set DPR:$Dd, (fsub_mlx (fmul_su DPR:$Dn, DPR:$Dm),
1392 (f64 DPR:$Ddin)))]>,
1393 RegConstraint<"$Ddin = $Dd">,
1394 Requires<[HasVFP4,UseFusedMAC]>;
1396 def VFNMSS : ASbI<0b11101, 0b01, 0, 0,
1397 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
1398 IIC_fpFMAC32, "vfnms", ".f32\t$Sd, $Sn, $Sm",
1399 [(set SPR:$Sd, (fsub_mlx (fmul_su SPR:$Sn, SPR:$Sm), SPR:$Sdin))]>,
1400 RegConstraint<"$Sdin = $Sd">,
1401 Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]> {
1402 // Some single precision VFP instructions may be executed on both NEON and
1406 def : Pat<(fsub_mlx (fmul_su DPR:$a, (f64 DPR:$b)), DPR:$dstin),
1407 (VFNMSD DPR:$dstin, DPR:$a, DPR:$b)>,
1408 Requires<[HasVFP4,UseFusedMAC]>;
1409 def : Pat<(fsub_mlx (fmul_su SPR:$a, SPR:$b), SPR:$dstin),
1410 (VFNMSS SPR:$dstin, SPR:$a, SPR:$b)>,
1411 Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]>;
1413 // Match @llvm.fma.* intrinsics
1415 // (fma x, y, (fneg z)) -> (vfnms z, x, y))
1416 def : Pat<(f64 (fma DPR:$Dn, DPR:$Dm, (fneg DPR:$Ddin))),
1417 (VFNMSD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>,
1418 Requires<[HasVFP4]>;
1419 def : Pat<(f32 (fma SPR:$Sn, SPR:$Sm, (fneg SPR:$Sdin))),
1420 (VFNMSS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
1421 Requires<[HasVFP4]>;
1422 // (fneg (fma (fneg x), y, z)) -> (vfnms z, x, y)
1423 def : Pat<(fneg (f64 (fma (fneg DPR:$Dn), DPR:$Dm, DPR:$Ddin))),
1424 (VFNMSD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>,
1425 Requires<[HasVFP4]>;
1426 def : Pat<(fneg (f32 (fma (fneg SPR:$Sn), SPR:$Sm, SPR:$Sdin))),
1427 (VFNMSS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
1428 Requires<[HasVFP4]>;
1429 // (fneg (fma x, (fneg y), z) -> (vfnms z, x, y)
1430 def : Pat<(fneg (f64 (fma DPR:$Dn, (fneg DPR:$Dm), DPR:$Ddin))),
1431 (VFNMSD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>,
1432 Requires<[HasVFP4]>;
1433 def : Pat<(fneg (f32 (fma SPR:$Sn, (fneg SPR:$Sm), SPR:$Sdin))),
1434 (VFNMSS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
1435 Requires<[HasVFP4]>;
1437 //===----------------------------------------------------------------------===//
1438 // FP Conditional moves.
1441 let neverHasSideEffects = 1 in {
1442 def VMOVDcc : ARMPseudoInst<(outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm, pred:$p),
1444 [/*(set DPR:$Dd, (ARMcmov DPR:$Dn, DPR:$Dm, imm:$cc))*/]>,
1445 RegConstraint<"$Dn = $Dd">;
1447 def VMOVScc : ARMPseudoInst<(outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm, pred:$p),
1449 [/*(set SPR:$Sd, (ARMcmov SPR:$Sn, SPR:$Sm, imm:$cc))*/]>,
1450 RegConstraint<"$Sn = $Sd">;
1451 } // neverHasSideEffects
1453 //===----------------------------------------------------------------------===//
1454 // Move from VFP System Register to ARM core register.
1457 class MovFromVFP<bits<4> opc19_16, dag oops, dag iops, string opc, string asm,
1459 VFPAI<oops, iops, VFPMiscFrm, IIC_fpSTAT, opc, asm, pattern> {
1461 // Instruction operand.
1464 let Inst{27-20} = 0b11101111;
1465 let Inst{19-16} = opc19_16;
1466 let Inst{15-12} = Rt;
1467 let Inst{11-8} = 0b1010;
1469 let Inst{6-5} = 0b00;
1471 let Inst{3-0} = 0b0000;
1474 // APSR is the application level alias of CPSR. This FPSCR N, Z, C, V flags
1476 let Defs = [CPSR], Uses = [FPSCR_NZCV], Rt = 0b1111 /* apsr_nzcv */ in
1477 def FMSTAT : MovFromVFP<0b0001 /* fpscr */, (outs), (ins),
1478 "vmrs", "\tAPSR_nzcv, fpscr", [(arm_fmstat)]>;
1480 // Application level FPSCR -> GPR
1481 let hasSideEffects = 1, Uses = [FPSCR] in
1482 def VMRS : MovFromVFP<0b0001 /* fpscr */, (outs GPR:$Rt), (ins),
1483 "vmrs", "\t$Rt, fpscr",
1484 [(set GPR:$Rt, (int_arm_get_fpscr))]>;
1486 // System level FPEXC, FPSID -> GPR
1487 let Uses = [FPSCR] in {
1488 def VMRS_FPEXC : MovFromVFP<0b1000 /* fpexc */, (outs GPR:$Rt), (ins),
1489 "vmrs", "\t$Rt, fpexc", []>;
1490 def VMRS_FPSID : MovFromVFP<0b0000 /* fpsid */, (outs GPR:$Rt), (ins),
1491 "vmrs", "\t$Rt, fpsid", []>;
1492 def VMRS_MVFR0 : MovFromVFP<0b0111 /* mvfr0 */, (outs GPR:$Rt), (ins),
1493 "vmrs", "\t$Rt, mvfr0", []>;
1494 def VMRS_MVFR1 : MovFromVFP<0b0110 /* mvfr1 */, (outs GPR:$Rt), (ins),
1495 "vmrs", "\t$Rt, mvfr1", []>;
1496 def VMRS_FPINST : MovFromVFP<0b1001 /* fpinst */, (outs GPR:$Rt), (ins),
1497 "vmrs", "\t$Rt, fpinst", []>;
1498 def VMRS_FPINST2 : MovFromVFP<0b1010 /* fpinst2 */, (outs GPR:$Rt), (ins),
1499 "vmrs", "\t$Rt, fpinst2", []>;
1502 //===----------------------------------------------------------------------===//
1503 // Move from ARM core register to VFP System Register.
1506 class MovToVFP<bits<4> opc19_16, dag oops, dag iops, string opc, string asm,
1508 VFPAI<oops, iops, VFPMiscFrm, IIC_fpSTAT, opc, asm, pattern> {
1510 // Instruction operand.
1513 // Encode instruction operand.
1514 let Inst{15-12} = src;
1516 let Inst{27-20} = 0b11101110;
1517 let Inst{19-16} = opc19_16;
1518 let Inst{11-8} = 0b1010;
1523 let Defs = [FPSCR] in {
1524 // Application level GPR -> FPSCR
1525 def VMSR : MovToVFP<0b0001 /* fpscr */, (outs), (ins GPR:$src),
1526 "vmsr", "\tfpscr, $src", [(int_arm_set_fpscr GPR:$src)]>;
1527 // System level GPR -> FPEXC
1528 def VMSR_FPEXC : MovToVFP<0b1000 /* fpexc */, (outs), (ins GPR:$src),
1529 "vmsr", "\tfpexc, $src", []>;
1530 // System level GPR -> FPSID
1531 def VMSR_FPSID : MovToVFP<0b0000 /* fpsid */, (outs), (ins GPR:$src),
1532 "vmsr", "\tfpsid, $src", []>;
1534 def VMSR_FPINST : MovToVFP<0b1001 /* fpinst */, (outs), (ins GPR:$src),
1535 "vmsr", "\tfpinst, $src", []>;
1536 def VMSR_FPINST2 : MovToVFP<0b1010 /* fpinst2 */, (outs), (ins GPR:$src),
1537 "vmsr", "\tfpinst2, $src", []>;
1540 //===----------------------------------------------------------------------===//
1544 // Materialize FP immediates. VFP3 only.
1545 let isReMaterializable = 1 in {
1546 def FCONSTD : VFPAI<(outs DPR:$Dd), (ins vfp_f64imm:$imm),
1547 VFPMiscFrm, IIC_fpUNA64,
1548 "vmov", ".f64\t$Dd, $imm",
1549 [(set DPR:$Dd, vfp_f64imm:$imm)]>, Requires<[HasVFP3]> {
1553 let Inst{27-23} = 0b11101;
1554 let Inst{22} = Dd{4};
1555 let Inst{21-20} = 0b11;
1556 let Inst{19-16} = imm{7-4};
1557 let Inst{15-12} = Dd{3-0};
1558 let Inst{11-9} = 0b101;
1559 let Inst{8} = 1; // Double precision.
1560 let Inst{7-4} = 0b0000;
1561 let Inst{3-0} = imm{3-0};
1564 def FCONSTS : VFPAI<(outs SPR:$Sd), (ins vfp_f32imm:$imm),
1565 VFPMiscFrm, IIC_fpUNA32,
1566 "vmov", ".f32\t$Sd, $imm",
1567 [(set SPR:$Sd, vfp_f32imm:$imm)]>, Requires<[HasVFP3]> {
1571 let Inst{27-23} = 0b11101;
1572 let Inst{22} = Sd{0};
1573 let Inst{21-20} = 0b11;
1574 let Inst{19-16} = imm{7-4};
1575 let Inst{15-12} = Sd{4-1};
1576 let Inst{11-9} = 0b101;
1577 let Inst{8} = 0; // Single precision.
1578 let Inst{7-4} = 0b0000;
1579 let Inst{3-0} = imm{3-0};
1583 //===----------------------------------------------------------------------===//
1584 // Assembler aliases.
1586 // A few mnemnoic aliases for pre-unifixed syntax. We don't guarantee to
1587 // support them all, but supporting at least some of the basics is
1588 // good to be friendly.
1589 def : VFP2MnemonicAlias<"flds", "vldr">;
1590 def : VFP2MnemonicAlias<"fldd", "vldr">;
1591 def : VFP2MnemonicAlias<"fmrs", "vmov">;
1592 def : VFP2MnemonicAlias<"fmsr", "vmov">;
1593 def : VFP2MnemonicAlias<"fsqrts", "vsqrt">;
1594 def : VFP2MnemonicAlias<"fsqrtd", "vsqrt">;
1595 def : VFP2MnemonicAlias<"fadds", "vadd.f32">;
1596 def : VFP2MnemonicAlias<"faddd", "vadd.f64">;
1597 def : VFP2MnemonicAlias<"fmrdd", "vmov">;
1598 def : VFP2MnemonicAlias<"fmrds", "vmov">;
1599 def : VFP2MnemonicAlias<"fmrrd", "vmov">;
1600 def : VFP2MnemonicAlias<"fmdrr", "vmov">;
1601 def : VFP2MnemonicAlias<"fmuls", "vmul.f32">;
1602 def : VFP2MnemonicAlias<"fmuld", "vmul.f64">;
1603 def : VFP2MnemonicAlias<"fnegs", "vneg.f32">;
1604 def : VFP2MnemonicAlias<"fnegd", "vneg.f64">;
1605 def : VFP2MnemonicAlias<"ftosizd", "vcvt.s32.f64">;
1606 def : VFP2MnemonicAlias<"ftosid", "vcvtr.s32.f64">;
1607 def : VFP2MnemonicAlias<"ftosizs", "vcvt.s32.f32">;
1608 def : VFP2MnemonicAlias<"ftosis", "vcvtr.s32.f32">;
1609 def : VFP2MnemonicAlias<"ftouizd", "vcvt.u32.f64">;
1610 def : VFP2MnemonicAlias<"ftouid", "vcvtr.u32.f64">;
1611 def : VFP2MnemonicAlias<"ftouizs", "vcvt.u32.f32">;
1612 def : VFP2MnemonicAlias<"ftouis", "vcvtr.u32.f32">;
1613 def : VFP2MnemonicAlias<"fsitod", "vcvt.f64.s32">;
1614 def : VFP2MnemonicAlias<"fsitos", "vcvt.f32.s32">;
1615 def : VFP2MnemonicAlias<"fuitod", "vcvt.f64.u32">;
1616 def : VFP2MnemonicAlias<"fuitos", "vcvt.f32.u32">;
1617 def : VFP2MnemonicAlias<"fsts", "vstr">;
1618 def : VFP2MnemonicAlias<"fstd", "vstr">;
1619 def : VFP2MnemonicAlias<"fmacd", "vmla.f64">;
1620 def : VFP2MnemonicAlias<"fmacs", "vmla.f32">;
1621 def : VFP2MnemonicAlias<"fcpys", "vmov.f32">;
1622 def : VFP2MnemonicAlias<"fcpyd", "vmov.f64">;
1623 def : VFP2MnemonicAlias<"fcmps", "vcmp.f32">;
1624 def : VFP2MnemonicAlias<"fcmpd", "vcmp.f64">;
1625 def : VFP2MnemonicAlias<"fdivs", "vdiv.f32">;
1626 def : VFP2MnemonicAlias<"fdivd", "vdiv.f64">;
1627 def : VFP2MnemonicAlias<"fmrx", "vmrs">;
1628 def : VFP2MnemonicAlias<"fmxr", "vmsr">;
1630 // Be friendly and accept the old form of zero-compare
1631 def : VFP2InstAlias<"fcmpzd${p} $val", (VCMPZD DPR:$val, pred:$p)>;
1632 def : VFP2InstAlias<"fcmpzs${p} $val", (VCMPZS SPR:$val, pred:$p)>;
1635 def : VFP2InstAlias<"fmstat${p}", (FMSTAT pred:$p)>;
1636 def : VFP2InstAlias<"fadds${p} $Sd, $Sn, $Sm",
1637 (VADDS SPR:$Sd, SPR:$Sn, SPR:$Sm, pred:$p)>;
1638 def : VFP2InstAlias<"faddd${p} $Dd, $Dn, $Dm",
1639 (VADDD DPR:$Dd, DPR:$Dn, DPR:$Dm, pred:$p)>;
1640 def : VFP2InstAlias<"fsubs${p} $Sd, $Sn, $Sm",
1641 (VSUBS SPR:$Sd, SPR:$Sn, SPR:$Sm, pred:$p)>;
1642 def : VFP2InstAlias<"fsubd${p} $Dd, $Dn, $Dm",
1643 (VSUBD DPR:$Dd, DPR:$Dn, DPR:$Dm, pred:$p)>;
1645 // No need for the size suffix on VSQRT. It's implied by the register classes.
1646 def : VFP2InstAlias<"vsqrt${p} $Sd, $Sm", (VSQRTS SPR:$Sd, SPR:$Sm, pred:$p)>;
1647 def : VFP2InstAlias<"vsqrt${p} $Dd, $Dm", (VSQRTD DPR:$Dd, DPR:$Dm, pred:$p)>;
1649 // VLDR/VSTR accept an optional type suffix.
1650 def : VFP2InstAlias<"vldr${p}.32 $Sd, $addr",
1651 (VLDRS SPR:$Sd, addrmode5:$addr, pred:$p)>;
1652 def : VFP2InstAlias<"vstr${p}.32 $Sd, $addr",
1653 (VSTRS SPR:$Sd, addrmode5:$addr, pred:$p)>;
1654 def : VFP2InstAlias<"vldr${p}.64 $Dd, $addr",
1655 (VLDRD DPR:$Dd, addrmode5:$addr, pred:$p)>;
1656 def : VFP2InstAlias<"vstr${p}.64 $Dd, $addr",
1657 (VSTRD DPR:$Dd, addrmode5:$addr, pred:$p)>;
1659 // VMOV can accept optional 32-bit or less data type suffix suffix.
1660 def : VFP2InstAlias<"vmov${p}.8 $Rt, $Sn",
1661 (VMOVRS GPR:$Rt, SPR:$Sn, pred:$p)>;
1662 def : VFP2InstAlias<"vmov${p}.16 $Rt, $Sn",
1663 (VMOVRS GPR:$Rt, SPR:$Sn, pred:$p)>;
1664 def : VFP2InstAlias<"vmov${p}.32 $Rt, $Sn",
1665 (VMOVRS GPR:$Rt, SPR:$Sn, pred:$p)>;
1666 def : VFP2InstAlias<"vmov${p}.8 $Sn, $Rt",
1667 (VMOVSR SPR:$Sn, GPR:$Rt, pred:$p)>;
1668 def : VFP2InstAlias<"vmov${p}.16 $Sn, $Rt",
1669 (VMOVSR SPR:$Sn, GPR:$Rt, pred:$p)>;
1670 def : VFP2InstAlias<"vmov${p}.32 $Sn, $Rt",
1671 (VMOVSR SPR:$Sn, GPR:$Rt, pred:$p)>;
1673 def : VFP2InstAlias<"vmov${p}.f64 $Rt, $Rt2, $Dn",
1674 (VMOVRRD GPR:$Rt, GPR:$Rt2, DPR:$Dn, pred:$p)>;
1675 def : VFP2InstAlias<"vmov${p}.f64 $Dn, $Rt, $Rt2",
1676 (VMOVDRR DPR:$Dn, GPR:$Rt, GPR:$Rt2, pred:$p)>;
1678 // VMOVS doesn't need the .f32 to disambiguate from the NEON encoding the way
1680 def : VFP2InstAlias<"vmov${p} $Sd, $Sm",
1681 (VMOVS SPR:$Sd, SPR:$Sm, pred:$p)>;