1 //===-- ARMInstrVFP.td - VFP support for ARM ---------------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM VFP instruction set.
12 //===----------------------------------------------------------------------===//
14 def SDT_FTOI : SDTypeProfile<1, 1, [SDTCisVT<0, f32>, SDTCisFP<1>]>;
15 def SDT_ITOF : SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisVT<1, f32>]>;
16 def SDT_CMPFP0 : SDTypeProfile<0, 1, [SDTCisFP<0>]>;
17 def SDT_VMOVDRR : SDTypeProfile<1, 2, [SDTCisVT<0, f64>, SDTCisVT<1, i32>,
20 def arm_ftoui : SDNode<"ARMISD::FTOUI", SDT_FTOI>;
21 def arm_ftosi : SDNode<"ARMISD::FTOSI", SDT_FTOI>;
22 def arm_sitof : SDNode<"ARMISD::SITOF", SDT_ITOF>;
23 def arm_uitof : SDNode<"ARMISD::UITOF", SDT_ITOF>;
24 def arm_fmstat : SDNode<"ARMISD::FMSTAT", SDTNone, [SDNPInGlue, SDNPOutGlue]>;
25 def arm_cmpfp : SDNode<"ARMISD::CMPFP", SDT_ARMCmp, [SDNPOutGlue]>;
26 def arm_cmpfp0 : SDNode<"ARMISD::CMPFPw0", SDT_CMPFP0, [SDNPOutGlue]>;
27 def arm_fmdrr : SDNode<"ARMISD::VMOVDRR", SDT_VMOVDRR>;
30 //===----------------------------------------------------------------------===//
31 // Operand Definitions.
34 // 8-bit floating-point immediate encodings.
35 def FPImmOperand : AsmOperandClass {
37 let ParserMethod = "parseFPImm";
40 def vfp_f32imm : Operand<f32>,
41 PatLeaf<(f32 fpimm), [{
42 return ARM_AM::getFP32Imm(N->getValueAPF()) != -1;
43 }], SDNodeXForm<fpimm, [{
44 APFloat InVal = N->getValueAPF();
45 uint32_t enc = ARM_AM::getFP32Imm(InVal);
46 return CurDAG->getTargetConstant(enc, MVT::i32);
48 let PrintMethod = "printFPImmOperand";
49 let ParserMatchClass = FPImmOperand;
52 def vfp_f64imm : Operand<f64>,
53 PatLeaf<(f64 fpimm), [{
54 return ARM_AM::getFP64Imm(N->getValueAPF()) != -1;
55 }], SDNodeXForm<fpimm, [{
56 APFloat InVal = N->getValueAPF();
57 uint32_t enc = ARM_AM::getFP64Imm(InVal);
58 return CurDAG->getTargetConstant(enc, MVT::i32);
60 let PrintMethod = "printFPImmOperand";
61 let ParserMatchClass = FPImmOperand;
64 def alignedload32 : PatFrag<(ops node:$ptr), (load node:$ptr), [{
65 return cast<LoadSDNode>(N)->getAlignment() >= 4;
68 def alignedstore32 : PatFrag<(ops node:$val, node:$ptr),
69 (store node:$val, node:$ptr), [{
70 return cast<StoreSDNode>(N)->getAlignment() >= 4;
73 // The VCVT to/from fixed-point instructions encode the 'fbits' operand
74 // (the number of fixed bits) differently than it appears in the assembly
75 // source. It's encoded as "Size - fbits" where Size is the size of the
76 // fixed-point representation (32 or 16) and fbits is the value appearing
77 // in the assembly source, an integer in [0,16] or (0,32], depending on size.
78 def fbits32_asm_operand : AsmOperandClass { let Name = "FBits32"; }
79 def fbits32 : Operand<i32> {
80 let PrintMethod = "printFBits32";
81 let ParserMatchClass = fbits32_asm_operand;
84 def fbits16_asm_operand : AsmOperandClass { let Name = "FBits16"; }
85 def fbits16 : Operand<i32> {
86 let PrintMethod = "printFBits16";
87 let ParserMatchClass = fbits16_asm_operand;
90 //===----------------------------------------------------------------------===//
91 // Load / store Instructions.
94 let canFoldAsLoad = 1, isReMaterializable = 1 in {
96 def VLDRD : ADI5<0b1101, 0b01, (outs DPR:$Dd), (ins addrmode5:$addr),
97 IIC_fpLoad64, "vldr", "\t$Dd, $addr",
98 [(set DPR:$Dd, (f64 (alignedload32 addrmode5:$addr)))]>;
100 def VLDRS : ASI5<0b1101, 0b01, (outs SPR:$Sd), (ins addrmode5:$addr),
101 IIC_fpLoad32, "vldr", "\t$Sd, $addr",
102 [(set SPR:$Sd, (load addrmode5:$addr))]> {
103 // Some single precision VFP instructions may be executed on both NEON and VFP
105 let D = VFPNeonDomain;
108 } // End of 'let canFoldAsLoad = 1, isReMaterializable = 1 in'
110 def VSTRD : ADI5<0b1101, 0b00, (outs), (ins DPR:$Dd, addrmode5:$addr),
111 IIC_fpStore64, "vstr", "\t$Dd, $addr",
112 [(alignedstore32 (f64 DPR:$Dd), addrmode5:$addr)]>;
114 def VSTRS : ASI5<0b1101, 0b00, (outs), (ins SPR:$Sd, addrmode5:$addr),
115 IIC_fpStore32, "vstr", "\t$Sd, $addr",
116 [(store SPR:$Sd, addrmode5:$addr)]> {
117 // Some single precision VFP instructions may be executed on both NEON and VFP
119 let D = VFPNeonDomain;
122 //===----------------------------------------------------------------------===//
123 // Load / store multiple Instructions.
126 multiclass vfp_ldst_mult<string asm, bit L_bit,
127 InstrItinClass itin, InstrItinClass itin_upd> {
130 AXDI4<(outs), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs, variable_ops),
132 !strconcat(asm, "ia${p}\t$Rn, $regs"), "", []> {
133 let Inst{24-23} = 0b01; // Increment After
134 let Inst{21} = 0; // No writeback
135 let Inst{20} = L_bit;
138 AXDI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs,
140 IndexModeUpd, itin_upd,
141 !strconcat(asm, "ia${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
142 let Inst{24-23} = 0b01; // Increment After
143 let Inst{21} = 1; // Writeback
144 let Inst{20} = L_bit;
147 AXDI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs,
149 IndexModeUpd, itin_upd,
150 !strconcat(asm, "db${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
151 let Inst{24-23} = 0b10; // Decrement Before
152 let Inst{21} = 1; // Writeback
153 let Inst{20} = L_bit;
158 AXSI4<(outs), (ins GPR:$Rn, pred:$p, spr_reglist:$regs, variable_ops),
160 !strconcat(asm, "ia${p}\t$Rn, $regs"), "", []> {
161 let Inst{24-23} = 0b01; // Increment After
162 let Inst{21} = 0; // No writeback
163 let Inst{20} = L_bit;
165 // Some single precision VFP instructions may be executed on both NEON and
167 let D = VFPNeonDomain;
170 AXSI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, spr_reglist:$regs,
172 IndexModeUpd, itin_upd,
173 !strconcat(asm, "ia${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
174 let Inst{24-23} = 0b01; // Increment After
175 let Inst{21} = 1; // Writeback
176 let Inst{20} = L_bit;
178 // Some single precision VFP instructions may be executed on both NEON and
180 let D = VFPNeonDomain;
183 AXSI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, spr_reglist:$regs,
185 IndexModeUpd, itin_upd,
186 !strconcat(asm, "db${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
187 let Inst{24-23} = 0b10; // Decrement Before
188 let Inst{21} = 1; // Writeback
189 let Inst{20} = L_bit;
191 // Some single precision VFP instructions may be executed on both NEON and
193 let D = VFPNeonDomain;
197 let neverHasSideEffects = 1 in {
199 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
200 defm VLDM : vfp_ldst_mult<"vldm", 1, IIC_fpLoad_m, IIC_fpLoad_mu>;
202 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
203 defm VSTM : vfp_ldst_mult<"vstm", 0, IIC_fpStore_m, IIC_fpStore_mu>;
205 } // neverHasSideEffects
207 def : MnemonicAlias<"vldm", "vldmia">;
208 def : MnemonicAlias<"vstm", "vstmia">;
210 // FLDM/FSTM - Load / Store multiple single / double precision registers for
212 // These instructions are deprecated!
213 def : VFP2MnemonicAlias<"fldmias", "vldmia">;
214 def : VFP2MnemonicAlias<"fldmdbs", "vldmdb">;
215 def : VFP2MnemonicAlias<"fldmeas", "vldmdb">;
216 def : VFP2MnemonicAlias<"fldmfds", "vldmia">;
217 def : VFP2MnemonicAlias<"fldmiad", "vldmia">;
218 def : VFP2MnemonicAlias<"fldmdbd", "vldmdb">;
219 def : VFP2MnemonicAlias<"fldmead", "vldmdb">;
220 def : VFP2MnemonicAlias<"fldmfdd", "vldmia">;
222 def : VFP2MnemonicAlias<"fstmias", "vstmia">;
223 def : VFP2MnemonicAlias<"fstmdbs", "vstmdb">;
224 def : VFP2MnemonicAlias<"fstmeas", "vstmia">;
225 def : VFP2MnemonicAlias<"fstmfds", "vstmdb">;
226 def : VFP2MnemonicAlias<"fstmiad", "vstmia">;
227 def : VFP2MnemonicAlias<"fstmdbd", "vstmdb">;
228 def : VFP2MnemonicAlias<"fstmead", "vstmia">;
229 def : VFP2MnemonicAlias<"fstmfdd", "vstmdb">;
231 def : InstAlias<"vpush${p} $r", (VSTMDDB_UPD SP, pred:$p, dpr_reglist:$r)>,
233 def : InstAlias<"vpush${p} $r", (VSTMSDB_UPD SP, pred:$p, spr_reglist:$r)>,
235 def : InstAlias<"vpop${p} $r", (VLDMDIA_UPD SP, pred:$p, dpr_reglist:$r)>,
237 def : InstAlias<"vpop${p} $r", (VLDMSIA_UPD SP, pred:$p, spr_reglist:$r)>,
239 defm : VFPDTAnyInstAlias<"vpush${p}", "$r",
240 (VSTMSDB_UPD SP, pred:$p, spr_reglist:$r)>;
241 defm : VFPDTAnyInstAlias<"vpush${p}", "$r",
242 (VSTMDDB_UPD SP, pred:$p, dpr_reglist:$r)>;
243 defm : VFPDTAnyInstAlias<"vpop${p}", "$r",
244 (VLDMSIA_UPD SP, pred:$p, spr_reglist:$r)>;
245 defm : VFPDTAnyInstAlias<"vpop${p}", "$r",
246 (VLDMDIA_UPD SP, pred:$p, dpr_reglist:$r)>;
248 // FLDMX, FSTMX - Load and store multiple unknown precision registers for
250 // These instruction are deprecated so we don't want them to get selected.
251 multiclass vfp_ldstx_mult<string asm, bit L_bit> {
254 AXXI4<(outs), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs, variable_ops),
255 IndexModeNone, !strconcat(asm, "iax${p}\t$Rn, $regs"), "", []> {
256 let Inst{24-23} = 0b01; // Increment After
257 let Inst{21} = 0; // No writeback
258 let Inst{20} = L_bit;
261 AXXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs, variable_ops),
262 IndexModeUpd, !strconcat(asm, "iax${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
263 let Inst{24-23} = 0b01; // Increment After
264 let Inst{21} = 1; // Writeback
265 let Inst{20} = L_bit;
268 AXXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs, variable_ops),
269 IndexModeUpd, !strconcat(asm, "dbx${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
270 let Inst{24-23} = 0b10; // Decrement Before
271 let Inst{21} = 1; // Writeback
272 let Inst{20} = L_bit;
276 defm FLDM : vfp_ldstx_mult<"fldm", 1>;
277 defm FSTM : vfp_ldstx_mult<"fstm", 0>;
279 def : VFP2MnemonicAlias<"fldmeax", "fldmdbx">;
280 def : VFP2MnemonicAlias<"fldmfdx", "fldmiax">;
282 def : VFP2MnemonicAlias<"fstmeax", "fstmiax">;
283 def : VFP2MnemonicAlias<"fstmfdx", "fstmdbx">;
285 //===----------------------------------------------------------------------===//
286 // FP Binary Operations.
289 let TwoOperandAliasConstraint = "$Dn = $Dd" in
290 def VADDD : ADbI<0b11100, 0b11, 0, 0,
291 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
292 IIC_fpALU64, "vadd", ".f64\t$Dd, $Dn, $Dm",
293 [(set DPR:$Dd, (fadd DPR:$Dn, (f64 DPR:$Dm)))]>;
295 let TwoOperandAliasConstraint = "$Sn = $Sd" in
296 def VADDS : ASbIn<0b11100, 0b11, 0, 0,
297 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
298 IIC_fpALU32, "vadd", ".f32\t$Sd, $Sn, $Sm",
299 [(set SPR:$Sd, (fadd SPR:$Sn, SPR:$Sm))]> {
300 // Some single precision VFP instructions may be executed on both NEON and
301 // VFP pipelines on A8.
302 let D = VFPNeonA8Domain;
305 let TwoOperandAliasConstraint = "$Dn = $Dd" in
306 def VSUBD : ADbI<0b11100, 0b11, 1, 0,
307 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
308 IIC_fpALU64, "vsub", ".f64\t$Dd, $Dn, $Dm",
309 [(set DPR:$Dd, (fsub DPR:$Dn, (f64 DPR:$Dm)))]>;
311 let TwoOperandAliasConstraint = "$Sn = $Sd" in
312 def VSUBS : ASbIn<0b11100, 0b11, 1, 0,
313 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
314 IIC_fpALU32, "vsub", ".f32\t$Sd, $Sn, $Sm",
315 [(set SPR:$Sd, (fsub SPR:$Sn, SPR:$Sm))]> {
316 // Some single precision VFP instructions may be executed on both NEON and
317 // VFP pipelines on A8.
318 let D = VFPNeonA8Domain;
321 let TwoOperandAliasConstraint = "$Dn = $Dd" in
322 def VDIVD : ADbI<0b11101, 0b00, 0, 0,
323 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
324 IIC_fpDIV64, "vdiv", ".f64\t$Dd, $Dn, $Dm",
325 [(set DPR:$Dd, (fdiv DPR:$Dn, (f64 DPR:$Dm)))]>;
327 let TwoOperandAliasConstraint = "$Sn = $Sd" in
328 def VDIVS : ASbI<0b11101, 0b00, 0, 0,
329 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
330 IIC_fpDIV32, "vdiv", ".f32\t$Sd, $Sn, $Sm",
331 [(set SPR:$Sd, (fdiv SPR:$Sn, SPR:$Sm))]>;
333 let TwoOperandAliasConstraint = "$Dn = $Dd" in
334 def VMULD : ADbI<0b11100, 0b10, 0, 0,
335 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
336 IIC_fpMUL64, "vmul", ".f64\t$Dd, $Dn, $Dm",
337 [(set DPR:$Dd, (fmul DPR:$Dn, (f64 DPR:$Dm)))]>;
339 let TwoOperandAliasConstraint = "$Sn = $Sd" in
340 def VMULS : ASbIn<0b11100, 0b10, 0, 0,
341 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
342 IIC_fpMUL32, "vmul", ".f32\t$Sd, $Sn, $Sm",
343 [(set SPR:$Sd, (fmul SPR:$Sn, SPR:$Sm))]> {
344 // Some single precision VFP instructions may be executed on both NEON and
345 // VFP pipelines on A8.
346 let D = VFPNeonA8Domain;
349 def VNMULD : ADbI<0b11100, 0b10, 1, 0,
350 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
351 IIC_fpMUL64, "vnmul", ".f64\t$Dd, $Dn, $Dm",
352 [(set DPR:$Dd, (fneg (fmul DPR:$Dn, (f64 DPR:$Dm))))]>;
354 def VNMULS : ASbI<0b11100, 0b10, 1, 0,
355 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
356 IIC_fpMUL32, "vnmul", ".f32\t$Sd, $Sn, $Sm",
357 [(set SPR:$Sd, (fneg (fmul SPR:$Sn, SPR:$Sm)))]> {
358 // Some single precision VFP instructions may be executed on both NEON and
359 // VFP pipelines on A8.
360 let D = VFPNeonA8Domain;
363 multiclass vsel_inst<string op, bits<2> opc, int CC> {
364 let DecoderNamespace = "VFPV8", PostEncoderMethod = "",
365 Uses = [CPSR], AddedComplexity = 4 in {
366 def S : ASbInp<0b11100, opc, 0,
367 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
368 NoItinerary, !strconcat("vsel", op, ".f32\t$Sd, $Sn, $Sm"),
369 [(set SPR:$Sd, (ARMcmov SPR:$Sm, SPR:$Sn, CC))]>,
370 Requires<[HasFPARMv8]>;
372 def D : ADbInp<0b11100, opc, 0,
373 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
374 NoItinerary, !strconcat("vsel", op, ".f64\t$Dd, $Dn, $Dm"),
375 [(set DPR:$Dd, (ARMcmov (f64 DPR:$Dm), (f64 DPR:$Dn), CC))]>,
376 Requires<[HasFPARMv8, HasDPVFP]>;
380 // The CC constants here match ARMCC::CondCodes.
381 defm VSELGT : vsel_inst<"gt", 0b11, 12>;
382 defm VSELGE : vsel_inst<"ge", 0b10, 10>;
383 defm VSELEQ : vsel_inst<"eq", 0b00, 0>;
384 defm VSELVS : vsel_inst<"vs", 0b01, 6>;
386 multiclass vmaxmin_inst<string op, bit opc, SDNode SD> {
387 let DecoderNamespace = "VFPV8", PostEncoderMethod = "" in {
388 def S : ASbInp<0b11101, 0b00, opc,
389 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
390 NoItinerary, !strconcat(op, ".f32\t$Sd, $Sn, $Sm"),
391 [(set SPR:$Sd, (SD SPR:$Sn, SPR:$Sm))]>,
392 Requires<[HasFPARMv8]>;
394 def D : ADbInp<0b11101, 0b00, opc,
395 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
396 NoItinerary, !strconcat(op, ".f64\t$Dd, $Dn, $Dm"),
397 [(set DPR:$Dd, (f64 (SD (f64 DPR:$Dn), (f64 DPR:$Dm))))]>,
398 Requires<[HasFPARMv8, HasDPVFP]>;
402 defm VMAXNM : vmaxmin_inst<"vmaxnm", 0, ARMvmaxnm>;
403 defm VMINNM : vmaxmin_inst<"vminnm", 1, ARMvminnm>;
405 // Match reassociated forms only if not sign dependent rounding.
406 def : Pat<(fmul (fneg DPR:$a), (f64 DPR:$b)),
407 (VNMULD DPR:$a, DPR:$b)>,
408 Requires<[NoHonorSignDependentRounding,HasDPVFP]>;
409 def : Pat<(fmul (fneg SPR:$a), SPR:$b),
410 (VNMULS SPR:$a, SPR:$b)>, Requires<[NoHonorSignDependentRounding]>;
412 // These are encoded as unary instructions.
413 let Defs = [FPSCR_NZCV] in {
414 def VCMPED : ADuI<0b11101, 0b11, 0b0100, 0b11, 0,
415 (outs), (ins DPR:$Dd, DPR:$Dm),
416 IIC_fpCMP64, "vcmpe", ".f64\t$Dd, $Dm",
417 [(arm_cmpfp DPR:$Dd, (f64 DPR:$Dm))]>;
419 def VCMPES : ASuI<0b11101, 0b11, 0b0100, 0b11, 0,
420 (outs), (ins SPR:$Sd, SPR:$Sm),
421 IIC_fpCMP32, "vcmpe", ".f32\t$Sd, $Sm",
422 [(arm_cmpfp SPR:$Sd, SPR:$Sm)]> {
423 // Some single precision VFP instructions may be executed on both NEON and
424 // VFP pipelines on A8.
425 let D = VFPNeonA8Domain;
428 // FIXME: Verify encoding after integrated assembler is working.
429 def VCMPD : ADuI<0b11101, 0b11, 0b0100, 0b01, 0,
430 (outs), (ins DPR:$Dd, DPR:$Dm),
431 IIC_fpCMP64, "vcmp", ".f64\t$Dd, $Dm",
432 [/* For disassembly only; pattern left blank */]>;
434 def VCMPS : ASuI<0b11101, 0b11, 0b0100, 0b01, 0,
435 (outs), (ins SPR:$Sd, SPR:$Sm),
436 IIC_fpCMP32, "vcmp", ".f32\t$Sd, $Sm",
437 [/* For disassembly only; pattern left blank */]> {
438 // Some single precision VFP instructions may be executed on both NEON and
439 // VFP pipelines on A8.
440 let D = VFPNeonA8Domain;
442 } // Defs = [FPSCR_NZCV]
444 //===----------------------------------------------------------------------===//
445 // FP Unary Operations.
448 def VABSD : ADuI<0b11101, 0b11, 0b0000, 0b11, 0,
449 (outs DPR:$Dd), (ins DPR:$Dm),
450 IIC_fpUNA64, "vabs", ".f64\t$Dd, $Dm",
451 [(set DPR:$Dd, (fabs (f64 DPR:$Dm)))]>;
453 def VABSS : ASuIn<0b11101, 0b11, 0b0000, 0b11, 0,
454 (outs SPR:$Sd), (ins SPR:$Sm),
455 IIC_fpUNA32, "vabs", ".f32\t$Sd, $Sm",
456 [(set SPR:$Sd, (fabs SPR:$Sm))]> {
457 // Some single precision VFP instructions may be executed on both NEON and
458 // VFP pipelines on A8.
459 let D = VFPNeonA8Domain;
462 let Defs = [FPSCR_NZCV] in {
463 def VCMPEZD : ADuI<0b11101, 0b11, 0b0101, 0b11, 0,
464 (outs), (ins DPR:$Dd),
465 IIC_fpCMP64, "vcmpe", ".f64\t$Dd, #0",
466 [(arm_cmpfp0 (f64 DPR:$Dd))]> {
467 let Inst{3-0} = 0b0000;
471 def VCMPEZS : ASuI<0b11101, 0b11, 0b0101, 0b11, 0,
472 (outs), (ins SPR:$Sd),
473 IIC_fpCMP32, "vcmpe", ".f32\t$Sd, #0",
474 [(arm_cmpfp0 SPR:$Sd)]> {
475 let Inst{3-0} = 0b0000;
478 // Some single precision VFP instructions may be executed on both NEON and
479 // VFP pipelines on A8.
480 let D = VFPNeonA8Domain;
483 // FIXME: Verify encoding after integrated assembler is working.
484 def VCMPZD : ADuI<0b11101, 0b11, 0b0101, 0b01, 0,
485 (outs), (ins DPR:$Dd),
486 IIC_fpCMP64, "vcmp", ".f64\t$Dd, #0",
487 [/* For disassembly only; pattern left blank */]> {
488 let Inst{3-0} = 0b0000;
492 def VCMPZS : ASuI<0b11101, 0b11, 0b0101, 0b01, 0,
493 (outs), (ins SPR:$Sd),
494 IIC_fpCMP32, "vcmp", ".f32\t$Sd, #0",
495 [/* For disassembly only; pattern left blank */]> {
496 let Inst{3-0} = 0b0000;
499 // Some single precision VFP instructions may be executed on both NEON and
500 // VFP pipelines on A8.
501 let D = VFPNeonA8Domain;
503 } // Defs = [FPSCR_NZCV]
505 def VCVTDS : ASuI<0b11101, 0b11, 0b0111, 0b11, 0,
506 (outs DPR:$Dd), (ins SPR:$Sm),
507 IIC_fpCVTDS, "vcvt", ".f64.f32\t$Dd, $Sm",
508 [(set DPR:$Dd, (fextend SPR:$Sm))]> {
509 // Instruction operands.
513 // Encode instruction operands.
514 let Inst{3-0} = Sm{4-1};
516 let Inst{15-12} = Dd{3-0};
517 let Inst{22} = Dd{4};
520 // Special case encoding: bits 11-8 is 0b1011.
521 def VCVTSD : VFPAI<(outs SPR:$Sd), (ins DPR:$Dm), VFPUnaryFrm,
522 IIC_fpCVTSD, "vcvt", ".f32.f64\t$Sd, $Dm",
523 [(set SPR:$Sd, (fround DPR:$Dm))]> {
524 // Instruction operands.
528 // Encode instruction operands.
529 let Inst{3-0} = Dm{3-0};
531 let Inst{15-12} = Sd{4-1};
532 let Inst{22} = Sd{0};
534 let Inst{27-23} = 0b11101;
535 let Inst{21-16} = 0b110111;
536 let Inst{11-8} = 0b1011;
537 let Inst{7-6} = 0b11;
540 let Predicates = [HasVFP2, HasDPVFP];
543 // Between half, single and double-precision. For disassembly only.
545 // FIXME: Verify encoding after integrated assembler is working.
546 def VCVTBHS: ASuI<0b11101, 0b11, 0b0010, 0b01, 0, (outs SPR:$Sd), (ins SPR:$Sm),
547 /* FIXME */ IIC_fpCVTSH, "vcvtb", ".f32.f16\t$Sd, $Sm",
548 [/* For disassembly only; pattern left blank */]>;
550 def VCVTBSH: ASuI<0b11101, 0b11, 0b0011, 0b01, 0, (outs SPR:$Sd), (ins SPR:$Sm),
551 /* FIXME */ IIC_fpCVTHS, "vcvtb", ".f16.f32\t$Sd, $Sm",
552 [/* For disassembly only; pattern left blank */]>;
554 def VCVTTHS: ASuI<0b11101, 0b11, 0b0010, 0b11, 0, (outs SPR:$Sd), (ins SPR:$Sm),
555 /* FIXME */ IIC_fpCVTSH, "vcvtt", ".f32.f16\t$Sd, $Sm",
556 [/* For disassembly only; pattern left blank */]>;
558 def VCVTTSH: ASuI<0b11101, 0b11, 0b0011, 0b11, 0, (outs SPR:$Sd), (ins SPR:$Sm),
559 /* FIXME */ IIC_fpCVTHS, "vcvtt", ".f16.f32\t$Sd, $Sm",
560 [/* For disassembly only; pattern left blank */]>;
562 def VCVTBHD : ADuI<0b11101, 0b11, 0b0010, 0b01, 0,
563 (outs DPR:$Dd), (ins SPR:$Sm),
564 NoItinerary, "vcvtb", ".f64.f16\t$Dd, $Sm",
565 []>, Requires<[HasFPARMv8, HasDPVFP]> {
566 // Instruction operands.
569 // Encode instruction operands.
570 let Inst{3-0} = Sm{4-1};
574 def VCVTBDH : ADuI<0b11101, 0b11, 0b0011, 0b01, 0,
575 (outs SPR:$Sd), (ins DPR:$Dm),
576 NoItinerary, "vcvtb", ".f16.f64\t$Sd, $Dm",
577 []>, Requires<[HasFPARMv8, HasDPVFP]> {
578 // Instruction operands.
582 // Encode instruction operands.
583 let Inst{3-0} = Dm{3-0};
585 let Inst{15-12} = Sd{4-1};
586 let Inst{22} = Sd{0};
589 def VCVTTHD : ADuI<0b11101, 0b11, 0b0010, 0b11, 0,
590 (outs DPR:$Dd), (ins SPR:$Sm),
591 NoItinerary, "vcvtt", ".f64.f16\t$Dd, $Sm",
592 []>, Requires<[HasFPARMv8, HasDPVFP]> {
593 // Instruction operands.
596 // Encode instruction operands.
597 let Inst{3-0} = Sm{4-1};
601 def VCVTTDH : ADuI<0b11101, 0b11, 0b0011, 0b11, 0,
602 (outs SPR:$Sd), (ins DPR:$Dm),
603 NoItinerary, "vcvtt", ".f16.f64\t$Sd, $Dm",
604 []>, Requires<[HasFPARMv8, HasDPVFP]> {
605 // Instruction operands.
609 // Encode instruction operands.
610 let Inst{15-12} = Sd{4-1};
611 let Inst{22} = Sd{0};
612 let Inst{3-0} = Dm{3-0};
616 def : Pat<(fp_to_f16 SPR:$a),
617 (i32 (COPY_TO_REGCLASS (VCVTBSH SPR:$a), GPR))>;
619 def : Pat<(fp_to_f16 (f64 DPR:$a)),
620 (i32 (COPY_TO_REGCLASS (VCVTBDH DPR:$a), GPR))>;
622 def : Pat<(f16_to_fp GPR:$a),
623 (VCVTBHS (COPY_TO_REGCLASS GPR:$a, SPR))>;
625 def : Pat<(f64 (f16_to_fp GPR:$a)),
626 (VCVTBHD (COPY_TO_REGCLASS GPR:$a, SPR))>;
629 multiclass vcvt_inst<string opc, bits<2> rm> {
630 let PostEncoderMethod = "", DecoderNamespace = "VFPV8" in {
631 def SS : ASuInp<0b11101, 0b11, 0b1100, 0b11, 0,
632 (outs SPR:$Sd), (ins SPR:$Sm),
633 NoItinerary, !strconcat("vcvt", opc, ".s32.f32\t$Sd, $Sm"),
634 []>, Requires<[HasFPARMv8]> {
635 let Inst{17-16} = rm;
638 def US : ASuInp<0b11101, 0b11, 0b1100, 0b01, 0,
639 (outs SPR:$Sd), (ins SPR:$Sm),
640 NoItinerary, !strconcat("vcvt", opc, ".u32.f32\t$Sd, $Sm"),
641 []>, Requires<[HasFPARMv8]> {
642 let Inst{17-16} = rm;
645 def SD : ASuInp<0b11101, 0b11, 0b1100, 0b11, 0,
646 (outs SPR:$Sd), (ins DPR:$Dm),
647 NoItinerary, !strconcat("vcvt", opc, ".s32.f64\t$Sd, $Dm"),
648 []>, Requires<[HasFPARMv8, HasDPVFP]> {
651 let Inst{17-16} = rm;
653 // Encode instruction operands
654 let Inst{3-0} = Dm{3-0};
659 def UD : ASuInp<0b11101, 0b11, 0b1100, 0b01, 0,
660 (outs SPR:$Sd), (ins DPR:$Dm),
661 NoItinerary, !strconcat("vcvt", opc, ".u32.f64\t$Sd, $Dm"),
662 []>, Requires<[HasFPARMv8, HasDPVFP]> {
665 let Inst{17-16} = rm;
667 // Encode instruction operands
668 let Inst{3-0} = Dm{3-0};
675 defm VCVTA : vcvt_inst<"a", 0b00>;
676 defm VCVTN : vcvt_inst<"n", 0b01>;
677 defm VCVTP : vcvt_inst<"p", 0b10>;
678 defm VCVTM : vcvt_inst<"m", 0b11>;
680 def VNEGD : ADuI<0b11101, 0b11, 0b0001, 0b01, 0,
681 (outs DPR:$Dd), (ins DPR:$Dm),
682 IIC_fpUNA64, "vneg", ".f64\t$Dd, $Dm",
683 [(set DPR:$Dd, (fneg (f64 DPR:$Dm)))]>;
685 def VNEGS : ASuIn<0b11101, 0b11, 0b0001, 0b01, 0,
686 (outs SPR:$Sd), (ins SPR:$Sm),
687 IIC_fpUNA32, "vneg", ".f32\t$Sd, $Sm",
688 [(set SPR:$Sd, (fneg SPR:$Sm))]> {
689 // Some single precision VFP instructions may be executed on both NEON and
690 // VFP pipelines on A8.
691 let D = VFPNeonA8Domain;
694 multiclass vrint_inst_zrx<string opc, bit op, bit op2> {
695 def S : ASuI<0b11101, 0b11, 0b0110, 0b11, 0,
696 (outs SPR:$Sd), (ins SPR:$Sm),
697 NoItinerary, !strconcat("vrint", opc), ".f32\t$Sd, $Sm",
698 []>, Requires<[HasFPARMv8]> {
702 def D : ADuI<0b11101, 0b11, 0b0110, 0b11, 0,
703 (outs DPR:$Dd), (ins DPR:$Dm),
704 NoItinerary, !strconcat("vrint", opc), ".f64\t$Dd, $Dm",
705 []>, Requires<[HasFPARMv8, HasDPVFP]> {
710 def : InstAlias<!strconcat("vrint", opc, "$p.f32.f32\t$Sd, $Sm"),
711 (!cast<Instruction>(NAME#"S") SPR:$Sd, SPR:$Sm, pred:$p)>,
712 Requires<[HasFPARMv8]>;
713 def : InstAlias<!strconcat("vrint", opc, "$p.f64.f64\t$Dd, $Dm"),
714 (!cast<Instruction>(NAME#"D") DPR:$Dd, DPR:$Dm, pred:$p)>,
715 Requires<[HasFPARMv8,HasDPVFP]>;
718 defm VRINTZ : vrint_inst_zrx<"z", 0, 1>;
719 defm VRINTR : vrint_inst_zrx<"r", 0, 0>;
720 defm VRINTX : vrint_inst_zrx<"x", 1, 0>;
722 multiclass vrint_inst_anpm<string opc, bits<2> rm> {
723 let PostEncoderMethod = "", DecoderNamespace = "VFPV8" in {
724 def S : ASuInp<0b11101, 0b11, 0b1000, 0b01, 0,
725 (outs SPR:$Sd), (ins SPR:$Sm),
726 NoItinerary, !strconcat("vrint", opc, ".f32\t$Sd, $Sm"),
727 []>, Requires<[HasFPARMv8]> {
728 let Inst{17-16} = rm;
730 def D : ADuInp<0b11101, 0b11, 0b1000, 0b01, 0,
731 (outs DPR:$Dd), (ins DPR:$Dm),
732 NoItinerary, !strconcat("vrint", opc, ".f64\t$Dd, $Dm"),
733 []>, Requires<[HasFPARMv8, HasDPVFP]> {
734 let Inst{17-16} = rm;
738 def : InstAlias<!strconcat("vrint", opc, ".f32.f32\t$Sd, $Sm"),
739 (!cast<Instruction>(NAME#"S") SPR:$Sd, SPR:$Sm)>,
740 Requires<[HasFPARMv8]>;
741 def : InstAlias<!strconcat("vrint", opc, ".f64.f64\t$Dd, $Dm"),
742 (!cast<Instruction>(NAME#"D") DPR:$Dd, DPR:$Dm)>,
743 Requires<[HasFPARMv8,HasDPVFP]>;
746 defm VRINTA : vrint_inst_anpm<"a", 0b00>;
747 defm VRINTN : vrint_inst_anpm<"n", 0b01>;
748 defm VRINTP : vrint_inst_anpm<"p", 0b10>;
749 defm VRINTM : vrint_inst_anpm<"m", 0b11>;
751 def VSQRTD : ADuI<0b11101, 0b11, 0b0001, 0b11, 0,
752 (outs DPR:$Dd), (ins DPR:$Dm),
753 IIC_fpSQRT64, "vsqrt", ".f64\t$Dd, $Dm",
754 [(set DPR:$Dd, (fsqrt (f64 DPR:$Dm)))]>;
756 def VSQRTS : ASuI<0b11101, 0b11, 0b0001, 0b11, 0,
757 (outs SPR:$Sd), (ins SPR:$Sm),
758 IIC_fpSQRT32, "vsqrt", ".f32\t$Sd, $Sm",
759 [(set SPR:$Sd, (fsqrt SPR:$Sm))]>;
761 let neverHasSideEffects = 1 in {
762 def VMOVD : ADuI<0b11101, 0b11, 0b0000, 0b01, 0,
763 (outs DPR:$Dd), (ins DPR:$Dm),
764 IIC_fpUNA64, "vmov", ".f64\t$Dd, $Dm", []>;
766 def VMOVS : ASuI<0b11101, 0b11, 0b0000, 0b01, 0,
767 (outs SPR:$Sd), (ins SPR:$Sm),
768 IIC_fpUNA32, "vmov", ".f32\t$Sd, $Sm", []>;
769 } // neverHasSideEffects
771 //===----------------------------------------------------------------------===//
772 // FP <-> GPR Copies. Int <-> FP Conversions.
775 def VMOVRS : AVConv2I<0b11100001, 0b1010,
776 (outs GPR:$Rt), (ins SPR:$Sn),
777 IIC_fpMOVSI, "vmov", "\t$Rt, $Sn",
778 [(set GPR:$Rt, (bitconvert SPR:$Sn))]> {
779 // Instruction operands.
783 // Encode instruction operands.
784 let Inst{19-16} = Sn{4-1};
786 let Inst{15-12} = Rt;
788 let Inst{6-5} = 0b00;
789 let Inst{3-0} = 0b0000;
791 // Some single precision VFP instructions may be executed on both NEON and VFP
793 let D = VFPNeonDomain;
796 // Bitcast i32 -> f32. NEON prefers to use VMOVDRR.
797 def VMOVSR : AVConv4I<0b11100000, 0b1010,
798 (outs SPR:$Sn), (ins GPR:$Rt),
799 IIC_fpMOVIS, "vmov", "\t$Sn, $Rt",
800 [(set SPR:$Sn, (bitconvert GPR:$Rt))]>,
801 Requires<[HasVFP2, UseVMOVSR]> {
802 // Instruction operands.
806 // Encode instruction operands.
807 let Inst{19-16} = Sn{4-1};
809 let Inst{15-12} = Rt;
811 let Inst{6-5} = 0b00;
812 let Inst{3-0} = 0b0000;
814 // Some single precision VFP instructions may be executed on both NEON and VFP
816 let D = VFPNeonDomain;
819 let neverHasSideEffects = 1 in {
820 def VMOVRRD : AVConv3I<0b11000101, 0b1011,
821 (outs GPR:$Rt, GPR:$Rt2), (ins DPR:$Dm),
822 IIC_fpMOVDI, "vmov", "\t$Rt, $Rt2, $Dm",
823 [/* FIXME: Can't write pattern for multiple result instr*/]> {
824 // Instruction operands.
829 // Encode instruction operands.
830 let Inst{3-0} = Dm{3-0};
832 let Inst{15-12} = Rt;
833 let Inst{19-16} = Rt2;
835 let Inst{7-6} = 0b00;
837 // Some single precision VFP instructions may be executed on both NEON and VFP
839 let D = VFPNeonDomain;
842 def VMOVRRS : AVConv3I<0b11000101, 0b1010,
843 (outs GPR:$Rt, GPR:$Rt2), (ins SPR:$src1, SPR:$src2),
844 IIC_fpMOVDI, "vmov", "\t$Rt, $Rt2, $src1, $src2",
845 [/* For disassembly only; pattern left blank */]> {
850 // Encode instruction operands.
851 let Inst{3-0} = src1{4-1};
852 let Inst{5} = src1{0};
853 let Inst{15-12} = Rt;
854 let Inst{19-16} = Rt2;
856 let Inst{7-6} = 0b00;
858 // Some single precision VFP instructions may be executed on both NEON and VFP
860 let D = VFPNeonDomain;
861 let DecoderMethod = "DecodeVMOVRRS";
863 } // neverHasSideEffects
868 def VMOVDRR : AVConv5I<0b11000100, 0b1011,
869 (outs DPR:$Dm), (ins GPR:$Rt, GPR:$Rt2),
870 IIC_fpMOVID, "vmov", "\t$Dm, $Rt, $Rt2",
871 [(set DPR:$Dm, (arm_fmdrr GPR:$Rt, GPR:$Rt2))]> {
872 // Instruction operands.
877 // Encode instruction operands.
878 let Inst{3-0} = Dm{3-0};
880 let Inst{15-12} = Rt;
881 let Inst{19-16} = Rt2;
883 let Inst{7-6} = 0b00;
885 // Some single precision VFP instructions may be executed on both NEON and VFP
887 let D = VFPNeonDomain;
889 // This instruction is equivalent to
890 // $Dm = REG_SEQUENCE $Rt, ssub_0, $Rt2, ssub_1
891 let isRegSequence = 1;
894 let neverHasSideEffects = 1 in
895 def VMOVSRR : AVConv5I<0b11000100, 0b1010,
896 (outs SPR:$dst1, SPR:$dst2), (ins GPR:$src1, GPR:$src2),
897 IIC_fpMOVID, "vmov", "\t$dst1, $dst2, $src1, $src2",
898 [/* For disassembly only; pattern left blank */]> {
899 // Instruction operands.
904 // Encode instruction operands.
905 let Inst{3-0} = dst1{4-1};
906 let Inst{5} = dst1{0};
907 let Inst{15-12} = src1;
908 let Inst{19-16} = src2;
910 let Inst{7-6} = 0b00;
912 // Some single precision VFP instructions may be executed on both NEON and VFP
914 let D = VFPNeonDomain;
916 let DecoderMethod = "DecodeVMOVSRR";
922 // FMRX: SPR system reg -> GPR
924 // FMXR: GPR -> VFP system reg
929 class AVConv1IDs_Encode<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3,
930 bits<4> opcod4, dag oops, dag iops,
931 InstrItinClass itin, string opc, string asm,
933 : AVConv1I<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm,
935 // Instruction operands.
939 // Encode instruction operands.
940 let Inst{3-0} = Sm{4-1};
942 let Inst{15-12} = Dd{3-0};
943 let Inst{22} = Dd{4};
945 let Predicates = [HasVFP2, HasDPVFP];
948 class AVConv1InSs_Encode<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3,
949 bits<4> opcod4, dag oops, dag iops,InstrItinClass itin,
950 string opc, string asm, list<dag> pattern>
951 : AVConv1In<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm,
953 // Instruction operands.
957 // Encode instruction operands.
958 let Inst{3-0} = Sm{4-1};
960 let Inst{15-12} = Sd{4-1};
961 let Inst{22} = Sd{0};
964 def VSITOD : AVConv1IDs_Encode<0b11101, 0b11, 0b1000, 0b1011,
965 (outs DPR:$Dd), (ins SPR:$Sm),
966 IIC_fpCVTID, "vcvt", ".f64.s32\t$Dd, $Sm",
967 [(set DPR:$Dd, (f64 (arm_sitof SPR:$Sm)))]> {
968 let Inst{7} = 1; // s32
971 def VSITOS : AVConv1InSs_Encode<0b11101, 0b11, 0b1000, 0b1010,
972 (outs SPR:$Sd),(ins SPR:$Sm),
973 IIC_fpCVTIS, "vcvt", ".f32.s32\t$Sd, $Sm",
974 [(set SPR:$Sd, (arm_sitof SPR:$Sm))]> {
975 let Inst{7} = 1; // s32
977 // Some single precision VFP instructions may be executed on both NEON and
978 // VFP pipelines on A8.
979 let D = VFPNeonA8Domain;
982 def VUITOD : AVConv1IDs_Encode<0b11101, 0b11, 0b1000, 0b1011,
983 (outs DPR:$Dd), (ins SPR:$Sm),
984 IIC_fpCVTID, "vcvt", ".f64.u32\t$Dd, $Sm",
985 [(set DPR:$Dd, (f64 (arm_uitof SPR:$Sm)))]> {
986 let Inst{7} = 0; // u32
989 def VUITOS : AVConv1InSs_Encode<0b11101, 0b11, 0b1000, 0b1010,
990 (outs SPR:$Sd), (ins SPR:$Sm),
991 IIC_fpCVTIS, "vcvt", ".f32.u32\t$Sd, $Sm",
992 [(set SPR:$Sd, (arm_uitof SPR:$Sm))]> {
993 let Inst{7} = 0; // u32
995 // Some single precision VFP instructions may be executed on both NEON and
996 // VFP pipelines on A8.
997 let D = VFPNeonA8Domain;
1002 class AVConv1IsD_Encode<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3,
1003 bits<4> opcod4, dag oops, dag iops,
1004 InstrItinClass itin, string opc, string asm,
1006 : AVConv1I<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm,
1008 // Instruction operands.
1012 // Encode instruction operands.
1013 let Inst{3-0} = Dm{3-0};
1014 let Inst{5} = Dm{4};
1015 let Inst{15-12} = Sd{4-1};
1016 let Inst{22} = Sd{0};
1018 let Predicates = [HasVFP2, HasDPVFP];
1021 class AVConv1InsS_Encode<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3,
1022 bits<4> opcod4, dag oops, dag iops,
1023 InstrItinClass itin, string opc, string asm,
1025 : AVConv1In<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm,
1027 // Instruction operands.
1031 // Encode instruction operands.
1032 let Inst{3-0} = Sm{4-1};
1033 let Inst{5} = Sm{0};
1034 let Inst{15-12} = Sd{4-1};
1035 let Inst{22} = Sd{0};
1038 // Always set Z bit in the instruction, i.e. "round towards zero" variants.
1039 def VTOSIZD : AVConv1IsD_Encode<0b11101, 0b11, 0b1101, 0b1011,
1040 (outs SPR:$Sd), (ins DPR:$Dm),
1041 IIC_fpCVTDI, "vcvt", ".s32.f64\t$Sd, $Dm",
1042 [(set SPR:$Sd, (arm_ftosi (f64 DPR:$Dm)))]> {
1043 let Inst{7} = 1; // Z bit
1046 def VTOSIZS : AVConv1InsS_Encode<0b11101, 0b11, 0b1101, 0b1010,
1047 (outs SPR:$Sd), (ins SPR:$Sm),
1048 IIC_fpCVTSI, "vcvt", ".s32.f32\t$Sd, $Sm",
1049 [(set SPR:$Sd, (arm_ftosi SPR:$Sm))]> {
1050 let Inst{7} = 1; // Z bit
1052 // Some single precision VFP instructions may be executed on both NEON and
1053 // VFP pipelines on A8.
1054 let D = VFPNeonA8Domain;
1057 def VTOUIZD : AVConv1IsD_Encode<0b11101, 0b11, 0b1100, 0b1011,
1058 (outs SPR:$Sd), (ins DPR:$Dm),
1059 IIC_fpCVTDI, "vcvt", ".u32.f64\t$Sd, $Dm",
1060 [(set SPR:$Sd, (arm_ftoui (f64 DPR:$Dm)))]> {
1061 let Inst{7} = 1; // Z bit
1064 def VTOUIZS : AVConv1InsS_Encode<0b11101, 0b11, 0b1100, 0b1010,
1065 (outs SPR:$Sd), (ins SPR:$Sm),
1066 IIC_fpCVTSI, "vcvt", ".u32.f32\t$Sd, $Sm",
1067 [(set SPR:$Sd, (arm_ftoui SPR:$Sm))]> {
1068 let Inst{7} = 1; // Z bit
1070 // Some single precision VFP instructions may be executed on both NEON and
1071 // VFP pipelines on A8.
1072 let D = VFPNeonA8Domain;
1075 // And the Z bit '0' variants, i.e. use the rounding mode specified by FPSCR.
1076 let Uses = [FPSCR] in {
1077 // FIXME: Verify encoding after integrated assembler is working.
1078 def VTOSIRD : AVConv1IsD_Encode<0b11101, 0b11, 0b1101, 0b1011,
1079 (outs SPR:$Sd), (ins DPR:$Dm),
1080 IIC_fpCVTDI, "vcvtr", ".s32.f64\t$Sd, $Dm",
1081 [(set SPR:$Sd, (int_arm_vcvtr (f64 DPR:$Dm)))]>{
1082 let Inst{7} = 0; // Z bit
1085 def VTOSIRS : AVConv1InsS_Encode<0b11101, 0b11, 0b1101, 0b1010,
1086 (outs SPR:$Sd), (ins SPR:$Sm),
1087 IIC_fpCVTSI, "vcvtr", ".s32.f32\t$Sd, $Sm",
1088 [(set SPR:$Sd, (int_arm_vcvtr SPR:$Sm))]> {
1089 let Inst{7} = 0; // Z bit
1092 def VTOUIRD : AVConv1IsD_Encode<0b11101, 0b11, 0b1100, 0b1011,
1093 (outs SPR:$Sd), (ins DPR:$Dm),
1094 IIC_fpCVTDI, "vcvtr", ".u32.f64\t$Sd, $Dm",
1095 [(set SPR:$Sd, (int_arm_vcvtru(f64 DPR:$Dm)))]>{
1096 let Inst{7} = 0; // Z bit
1099 def VTOUIRS : AVConv1InsS_Encode<0b11101, 0b11, 0b1100, 0b1010,
1100 (outs SPR:$Sd), (ins SPR:$Sm),
1101 IIC_fpCVTSI, "vcvtr", ".u32.f32\t$Sd, $Sm",
1102 [(set SPR:$Sd, (int_arm_vcvtru SPR:$Sm))]> {
1103 let Inst{7} = 0; // Z bit
1107 // Convert between floating-point and fixed-point
1108 // Data type for fixed-point naming convention:
1109 // S16 (U=0, sx=0) -> SH
1110 // U16 (U=1, sx=0) -> UH
1111 // S32 (U=0, sx=1) -> SL
1112 // U32 (U=1, sx=1) -> UL
1114 let Constraints = "$a = $dst" in {
1116 // FP to Fixed-Point:
1118 // Single Precision register
1119 class AVConv1XInsS_Encode<bits<5> op1, bits<2> op2, bits<4> op3, bits<4> op4,
1120 bit op5, dag oops, dag iops, InstrItinClass itin,
1121 string opc, string asm, list<dag> pattern>
1122 : AVConv1XI<op1, op2, op3, op4, op5, oops, iops, itin, opc, asm, pattern>,
1123 Sched<[WriteCvtFP]> {
1125 // if dp_operation then UInt(D:Vd) else UInt(Vd:D);
1126 let Inst{22} = dst{0};
1127 let Inst{15-12} = dst{4-1};
1130 // Double Precision register
1131 class AVConv1XInsD_Encode<bits<5> op1, bits<2> op2, bits<4> op3, bits<4> op4,
1132 bit op5, dag oops, dag iops, InstrItinClass itin,
1133 string opc, string asm, list<dag> pattern>
1134 : AVConv1XI<op1, op2, op3, op4, op5, oops, iops, itin, opc, asm, pattern>,
1135 Sched<[WriteCvtFP]> {
1137 // if dp_operation then UInt(D:Vd) else UInt(Vd:D);
1138 let Inst{22} = dst{4};
1139 let Inst{15-12} = dst{3-0};
1141 let Predicates = [HasVFP2, HasDPVFP];
1144 def VTOSHS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1110, 0b1010, 0,
1145 (outs SPR:$dst), (ins SPR:$a, fbits16:$fbits),
1146 IIC_fpCVTSI, "vcvt", ".s16.f32\t$dst, $a, $fbits", []> {
1147 // Some single precision VFP instructions may be executed on both NEON and
1148 // VFP pipelines on A8.
1149 let D = VFPNeonA8Domain;
1152 def VTOUHS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1111, 0b1010, 0,
1153 (outs SPR:$dst), (ins SPR:$a, fbits16:$fbits),
1154 IIC_fpCVTSI, "vcvt", ".u16.f32\t$dst, $a, $fbits", []> {
1155 // Some single precision VFP instructions may be executed on both NEON and
1156 // VFP pipelines on A8.
1157 let D = VFPNeonA8Domain;
1160 def VTOSLS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1110, 0b1010, 1,
1161 (outs SPR:$dst), (ins SPR:$a, fbits32:$fbits),
1162 IIC_fpCVTSI, "vcvt", ".s32.f32\t$dst, $a, $fbits", []> {
1163 // Some single precision VFP instructions may be executed on both NEON and
1164 // VFP pipelines on A8.
1165 let D = VFPNeonA8Domain;
1168 def VTOULS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1111, 0b1010, 1,
1169 (outs SPR:$dst), (ins SPR:$a, fbits32:$fbits),
1170 IIC_fpCVTSI, "vcvt", ".u32.f32\t$dst, $a, $fbits", []> {
1171 // Some single precision VFP instructions may be executed on both NEON and
1172 // VFP pipelines on A8.
1173 let D = VFPNeonA8Domain;
1176 def VTOSHD : AVConv1XInsD_Encode<0b11101, 0b11, 0b1110, 0b1011, 0,
1177 (outs DPR:$dst), (ins DPR:$a, fbits16:$fbits),
1178 IIC_fpCVTDI, "vcvt", ".s16.f64\t$dst, $a, $fbits", []>;
1180 def VTOUHD : AVConv1XInsD_Encode<0b11101, 0b11, 0b1111, 0b1011, 0,
1181 (outs DPR:$dst), (ins DPR:$a, fbits16:$fbits),
1182 IIC_fpCVTDI, "vcvt", ".u16.f64\t$dst, $a, $fbits", []>;
1184 def VTOSLD : AVConv1XInsD_Encode<0b11101, 0b11, 0b1110, 0b1011, 1,
1185 (outs DPR:$dst), (ins DPR:$a, fbits32:$fbits),
1186 IIC_fpCVTDI, "vcvt", ".s32.f64\t$dst, $a, $fbits", []>;
1188 def VTOULD : AVConv1XInsD_Encode<0b11101, 0b11, 0b1111, 0b1011, 1,
1189 (outs DPR:$dst), (ins DPR:$a, fbits32:$fbits),
1190 IIC_fpCVTDI, "vcvt", ".u32.f64\t$dst, $a, $fbits", []>;
1192 // Fixed-Point to FP:
1194 def VSHTOS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1010, 0b1010, 0,
1195 (outs SPR:$dst), (ins SPR:$a, fbits16:$fbits),
1196 IIC_fpCVTIS, "vcvt", ".f32.s16\t$dst, $a, $fbits", []> {
1197 // Some single precision VFP instructions may be executed on both NEON and
1198 // VFP pipelines on A8.
1199 let D = VFPNeonA8Domain;
1202 def VUHTOS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1011, 0b1010, 0,
1203 (outs SPR:$dst), (ins SPR:$a, fbits16:$fbits),
1204 IIC_fpCVTIS, "vcvt", ".f32.u16\t$dst, $a, $fbits", []> {
1205 // Some single precision VFP instructions may be executed on both NEON and
1206 // VFP pipelines on A8.
1207 let D = VFPNeonA8Domain;
1210 def VSLTOS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1010, 0b1010, 1,
1211 (outs SPR:$dst), (ins SPR:$a, fbits32:$fbits),
1212 IIC_fpCVTIS, "vcvt", ".f32.s32\t$dst, $a, $fbits", []> {
1213 // Some single precision VFP instructions may be executed on both NEON and
1214 // VFP pipelines on A8.
1215 let D = VFPNeonA8Domain;
1218 def VULTOS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1011, 0b1010, 1,
1219 (outs SPR:$dst), (ins SPR:$a, fbits32:$fbits),
1220 IIC_fpCVTIS, "vcvt", ".f32.u32\t$dst, $a, $fbits", []> {
1221 // Some single precision VFP instructions may be executed on both NEON and
1222 // VFP pipelines on A8.
1223 let D = VFPNeonA8Domain;
1226 def VSHTOD : AVConv1XInsD_Encode<0b11101, 0b11, 0b1010, 0b1011, 0,
1227 (outs DPR:$dst), (ins DPR:$a, fbits16:$fbits),
1228 IIC_fpCVTID, "vcvt", ".f64.s16\t$dst, $a, $fbits", []>;
1230 def VUHTOD : AVConv1XInsD_Encode<0b11101, 0b11, 0b1011, 0b1011, 0,
1231 (outs DPR:$dst), (ins DPR:$a, fbits16:$fbits),
1232 IIC_fpCVTID, "vcvt", ".f64.u16\t$dst, $a, $fbits", []>;
1234 def VSLTOD : AVConv1XInsD_Encode<0b11101, 0b11, 0b1010, 0b1011, 1,
1235 (outs DPR:$dst), (ins DPR:$a, fbits32:$fbits),
1236 IIC_fpCVTID, "vcvt", ".f64.s32\t$dst, $a, $fbits", []>;
1238 def VULTOD : AVConv1XInsD_Encode<0b11101, 0b11, 0b1011, 0b1011, 1,
1239 (outs DPR:$dst), (ins DPR:$a, fbits32:$fbits),
1240 IIC_fpCVTID, "vcvt", ".f64.u32\t$dst, $a, $fbits", []>;
1242 } // End of 'let Constraints = "$a = $dst" in'
1244 //===----------------------------------------------------------------------===//
1245 // FP Multiply-Accumulate Operations.
1248 def VMLAD : ADbI<0b11100, 0b00, 0, 0,
1249 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
1250 IIC_fpMAC64, "vmla", ".f64\t$Dd, $Dn, $Dm",
1251 [(set DPR:$Dd, (fadd_mlx (fmul_su DPR:$Dn, DPR:$Dm),
1252 (f64 DPR:$Ddin)))]>,
1253 RegConstraint<"$Ddin = $Dd">,
1254 Requires<[HasVFP2,HasDPVFP,UseFPVMLx,DontUseFusedMAC]>;
1256 def VMLAS : ASbIn<0b11100, 0b00, 0, 0,
1257 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
1258 IIC_fpMAC32, "vmla", ".f32\t$Sd, $Sn, $Sm",
1259 [(set SPR:$Sd, (fadd_mlx (fmul_su SPR:$Sn, SPR:$Sm),
1261 RegConstraint<"$Sdin = $Sd">,
1262 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx,DontUseFusedMAC]> {
1263 // Some single precision VFP instructions may be executed on both NEON and
1264 // VFP pipelines on A8.
1265 let D = VFPNeonA8Domain;
1268 def : Pat<(fadd_mlx DPR:$dstin, (fmul_su DPR:$a, (f64 DPR:$b))),
1269 (VMLAD DPR:$dstin, DPR:$a, DPR:$b)>,
1270 Requires<[HasVFP2,HasDPVFP,UseFPVMLx,DontUseFusedMAC]>;
1271 def : Pat<(fadd_mlx SPR:$dstin, (fmul_su SPR:$a, SPR:$b)),
1272 (VMLAS SPR:$dstin, SPR:$a, SPR:$b)>,
1273 Requires<[HasVFP2,DontUseNEONForFP, UseFPVMLx,DontUseFusedMAC]>;
1275 def VMLSD : ADbI<0b11100, 0b00, 1, 0,
1276 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
1277 IIC_fpMAC64, "vmls", ".f64\t$Dd, $Dn, $Dm",
1278 [(set DPR:$Dd, (fadd_mlx (fneg (fmul_su DPR:$Dn,DPR:$Dm)),
1279 (f64 DPR:$Ddin)))]>,
1280 RegConstraint<"$Ddin = $Dd">,
1281 Requires<[HasVFP2,HasDPVFP,UseFPVMLx,DontUseFusedMAC]>;
1283 def VMLSS : ASbIn<0b11100, 0b00, 1, 0,
1284 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
1285 IIC_fpMAC32, "vmls", ".f32\t$Sd, $Sn, $Sm",
1286 [(set SPR:$Sd, (fadd_mlx (fneg (fmul_su SPR:$Sn, SPR:$Sm)),
1288 RegConstraint<"$Sdin = $Sd">,
1289 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx,DontUseFusedMAC]> {
1290 // Some single precision VFP instructions may be executed on both NEON and
1291 // VFP pipelines on A8.
1292 let D = VFPNeonA8Domain;
1295 def : Pat<(fsub_mlx DPR:$dstin, (fmul_su DPR:$a, (f64 DPR:$b))),
1296 (VMLSD DPR:$dstin, DPR:$a, DPR:$b)>,
1297 Requires<[HasVFP2,HasDPVFP,UseFPVMLx,DontUseFusedMAC]>;
1298 def : Pat<(fsub_mlx SPR:$dstin, (fmul_su SPR:$a, SPR:$b)),
1299 (VMLSS SPR:$dstin, SPR:$a, SPR:$b)>,
1300 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx,DontUseFusedMAC]>;
1302 def VNMLAD : ADbI<0b11100, 0b01, 1, 0,
1303 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
1304 IIC_fpMAC64, "vnmla", ".f64\t$Dd, $Dn, $Dm",
1305 [(set DPR:$Dd,(fsub_mlx (fneg (fmul_su DPR:$Dn,DPR:$Dm)),
1306 (f64 DPR:$Ddin)))]>,
1307 RegConstraint<"$Ddin = $Dd">,
1308 Requires<[HasVFP2,HasDPVFP,UseFPVMLx,DontUseFusedMAC]>;
1310 def VNMLAS : ASbI<0b11100, 0b01, 1, 0,
1311 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
1312 IIC_fpMAC32, "vnmla", ".f32\t$Sd, $Sn, $Sm",
1313 [(set SPR:$Sd, (fsub_mlx (fneg (fmul_su SPR:$Sn, SPR:$Sm)),
1315 RegConstraint<"$Sdin = $Sd">,
1316 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx,DontUseFusedMAC]> {
1317 // Some single precision VFP instructions may be executed on both NEON and
1318 // VFP pipelines on A8.
1319 let D = VFPNeonA8Domain;
1322 def : Pat<(fsub_mlx (fneg (fmul_su DPR:$a, (f64 DPR:$b))), DPR:$dstin),
1323 (VNMLAD DPR:$dstin, DPR:$a, DPR:$b)>,
1324 Requires<[HasVFP2,HasDPVFP,UseFPVMLx,DontUseFusedMAC]>;
1325 def : Pat<(fsub_mlx (fneg (fmul_su SPR:$a, SPR:$b)), SPR:$dstin),
1326 (VNMLAS SPR:$dstin, SPR:$a, SPR:$b)>,
1327 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx,DontUseFusedMAC]>;
1329 def VNMLSD : ADbI<0b11100, 0b01, 0, 0,
1330 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
1331 IIC_fpMAC64, "vnmls", ".f64\t$Dd, $Dn, $Dm",
1332 [(set DPR:$Dd, (fsub_mlx (fmul_su DPR:$Dn, DPR:$Dm),
1333 (f64 DPR:$Ddin)))]>,
1334 RegConstraint<"$Ddin = $Dd">,
1335 Requires<[HasVFP2,HasDPVFP,UseFPVMLx,DontUseFusedMAC]>;
1337 def VNMLSS : ASbI<0b11100, 0b01, 0, 0,
1338 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
1339 IIC_fpMAC32, "vnmls", ".f32\t$Sd, $Sn, $Sm",
1340 [(set SPR:$Sd, (fsub_mlx (fmul_su SPR:$Sn, SPR:$Sm), SPR:$Sdin))]>,
1341 RegConstraint<"$Sdin = $Sd">,
1342 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx,DontUseFusedMAC]> {
1343 // Some single precision VFP instructions may be executed on both NEON and
1344 // VFP pipelines on A8.
1345 let D = VFPNeonA8Domain;
1348 def : Pat<(fsub_mlx (fmul_su DPR:$a, (f64 DPR:$b)), DPR:$dstin),
1349 (VNMLSD DPR:$dstin, DPR:$a, DPR:$b)>,
1350 Requires<[HasVFP2,HasDPVFP,UseFPVMLx,DontUseFusedMAC]>;
1351 def : Pat<(fsub_mlx (fmul_su SPR:$a, SPR:$b), SPR:$dstin),
1352 (VNMLSS SPR:$dstin, SPR:$a, SPR:$b)>,
1353 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx,DontUseFusedMAC]>;
1355 //===----------------------------------------------------------------------===//
1356 // Fused FP Multiply-Accumulate Operations.
1358 def VFMAD : ADbI<0b11101, 0b10, 0, 0,
1359 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
1360 IIC_fpFMAC64, "vfma", ".f64\t$Dd, $Dn, $Dm",
1361 [(set DPR:$Dd, (fadd_mlx (fmul_su DPR:$Dn, DPR:$Dm),
1362 (f64 DPR:$Ddin)))]>,
1363 RegConstraint<"$Ddin = $Dd">,
1364 Requires<[HasVFP4,HasDPVFP,UseFusedMAC]>;
1366 def VFMAS : ASbIn<0b11101, 0b10, 0, 0,
1367 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
1368 IIC_fpFMAC32, "vfma", ".f32\t$Sd, $Sn, $Sm",
1369 [(set SPR:$Sd, (fadd_mlx (fmul_su SPR:$Sn, SPR:$Sm),
1371 RegConstraint<"$Sdin = $Sd">,
1372 Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]> {
1373 // Some single precision VFP instructions may be executed on both NEON and
1377 def : Pat<(fadd_mlx DPR:$dstin, (fmul_su DPR:$a, (f64 DPR:$b))),
1378 (VFMAD DPR:$dstin, DPR:$a, DPR:$b)>,
1379 Requires<[HasVFP4,HasDPVFP,UseFusedMAC]>;
1380 def : Pat<(fadd_mlx SPR:$dstin, (fmul_su SPR:$a, SPR:$b)),
1381 (VFMAS SPR:$dstin, SPR:$a, SPR:$b)>,
1382 Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]>;
1384 // Match @llvm.fma.* intrinsics
1385 // (fma x, y, z) -> (vfms z, x, y)
1386 def : Pat<(f64 (fma DPR:$Dn, DPR:$Dm, DPR:$Ddin)),
1387 (VFMAD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>,
1388 Requires<[HasVFP4,HasDPVFP]>;
1389 def : Pat<(f32 (fma SPR:$Sn, SPR:$Sm, SPR:$Sdin)),
1390 (VFMAS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
1391 Requires<[HasVFP4]>;
1393 def VFMSD : ADbI<0b11101, 0b10, 1, 0,
1394 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
1395 IIC_fpFMAC64, "vfms", ".f64\t$Dd, $Dn, $Dm",
1396 [(set DPR:$Dd, (fadd_mlx (fneg (fmul_su DPR:$Dn,DPR:$Dm)),
1397 (f64 DPR:$Ddin)))]>,
1398 RegConstraint<"$Ddin = $Dd">,
1399 Requires<[HasVFP4,HasDPVFP,UseFusedMAC]>;
1401 def VFMSS : ASbIn<0b11101, 0b10, 1, 0,
1402 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
1403 IIC_fpFMAC32, "vfms", ".f32\t$Sd, $Sn, $Sm",
1404 [(set SPR:$Sd, (fadd_mlx (fneg (fmul_su SPR:$Sn, SPR:$Sm)),
1406 RegConstraint<"$Sdin = $Sd">,
1407 Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]> {
1408 // Some single precision VFP instructions may be executed on both NEON and
1412 def : Pat<(fsub_mlx DPR:$dstin, (fmul_su DPR:$a, (f64 DPR:$b))),
1413 (VFMSD DPR:$dstin, DPR:$a, DPR:$b)>,
1414 Requires<[HasVFP4,HasDPVFP,UseFusedMAC]>;
1415 def : Pat<(fsub_mlx SPR:$dstin, (fmul_su SPR:$a, SPR:$b)),
1416 (VFMSS SPR:$dstin, SPR:$a, SPR:$b)>,
1417 Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]>;
1419 // Match @llvm.fma.* intrinsics
1420 // (fma (fneg x), y, z) -> (vfms z, x, y)
1421 def : Pat<(f64 (fma (fneg DPR:$Dn), DPR:$Dm, DPR:$Ddin)),
1422 (VFMSD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>,
1423 Requires<[HasVFP4,HasDPVFP]>;
1424 def : Pat<(f32 (fma (fneg SPR:$Sn), SPR:$Sm, SPR:$Sdin)),
1425 (VFMSS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
1426 Requires<[HasVFP4]>;
1427 // (fma x, (fneg y), z) -> (vfms z, x, y)
1428 def : Pat<(f64 (fma DPR:$Dn, (fneg DPR:$Dm), DPR:$Ddin)),
1429 (VFMSD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>,
1430 Requires<[HasVFP4,HasDPVFP]>;
1431 def : Pat<(f32 (fma SPR:$Sn, (fneg SPR:$Sm), SPR:$Sdin)),
1432 (VFMSS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
1433 Requires<[HasVFP4]>;
1435 def VFNMAD : ADbI<0b11101, 0b01, 1, 0,
1436 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
1437 IIC_fpFMAC64, "vfnma", ".f64\t$Dd, $Dn, $Dm",
1438 [(set DPR:$Dd,(fsub_mlx (fneg (fmul_su DPR:$Dn,DPR:$Dm)),
1439 (f64 DPR:$Ddin)))]>,
1440 RegConstraint<"$Ddin = $Dd">,
1441 Requires<[HasVFP4,HasDPVFP,UseFusedMAC]>;
1443 def VFNMAS : ASbI<0b11101, 0b01, 1, 0,
1444 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
1445 IIC_fpFMAC32, "vfnma", ".f32\t$Sd, $Sn, $Sm",
1446 [(set SPR:$Sd, (fsub_mlx (fneg (fmul_su SPR:$Sn, SPR:$Sm)),
1448 RegConstraint<"$Sdin = $Sd">,
1449 Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]> {
1450 // Some single precision VFP instructions may be executed on both NEON and
1454 def : Pat<(fsub_mlx (fneg (fmul_su DPR:$a, (f64 DPR:$b))), DPR:$dstin),
1455 (VFNMAD DPR:$dstin, DPR:$a, DPR:$b)>,
1456 Requires<[HasVFP4,HasDPVFP,UseFusedMAC]>;
1457 def : Pat<(fsub_mlx (fneg (fmul_su SPR:$a, SPR:$b)), SPR:$dstin),
1458 (VFNMAS SPR:$dstin, SPR:$a, SPR:$b)>,
1459 Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]>;
1461 // Match @llvm.fma.* intrinsics
1462 // (fneg (fma x, y, z)) -> (vfnma z, x, y)
1463 def : Pat<(fneg (fma (f64 DPR:$Dn), (f64 DPR:$Dm), (f64 DPR:$Ddin))),
1464 (VFNMAD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>,
1465 Requires<[HasVFP4,HasDPVFP]>;
1466 def : Pat<(fneg (fma (f32 SPR:$Sn), (f32 SPR:$Sm), (f32 SPR:$Sdin))),
1467 (VFNMAS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
1468 Requires<[HasVFP4]>;
1469 // (fma (fneg x), y, (fneg z)) -> (vfnma z, x, y)
1470 def : Pat<(f64 (fma (fneg DPR:$Dn), DPR:$Dm, (fneg DPR:$Ddin))),
1471 (VFNMAD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>,
1472 Requires<[HasVFP4,HasDPVFP]>;
1473 def : Pat<(f32 (fma (fneg SPR:$Sn), SPR:$Sm, (fneg SPR:$Sdin))),
1474 (VFNMAS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
1475 Requires<[HasVFP4]>;
1477 def VFNMSD : ADbI<0b11101, 0b01, 0, 0,
1478 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
1479 IIC_fpFMAC64, "vfnms", ".f64\t$Dd, $Dn, $Dm",
1480 [(set DPR:$Dd, (fsub_mlx (fmul_su DPR:$Dn, DPR:$Dm),
1481 (f64 DPR:$Ddin)))]>,
1482 RegConstraint<"$Ddin = $Dd">,
1483 Requires<[HasVFP4,HasDPVFP,UseFusedMAC]>;
1485 def VFNMSS : ASbI<0b11101, 0b01, 0, 0,
1486 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
1487 IIC_fpFMAC32, "vfnms", ".f32\t$Sd, $Sn, $Sm",
1488 [(set SPR:$Sd, (fsub_mlx (fmul_su SPR:$Sn, SPR:$Sm), SPR:$Sdin))]>,
1489 RegConstraint<"$Sdin = $Sd">,
1490 Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]> {
1491 // Some single precision VFP instructions may be executed on both NEON and
1495 def : Pat<(fsub_mlx (fmul_su DPR:$a, (f64 DPR:$b)), DPR:$dstin),
1496 (VFNMSD DPR:$dstin, DPR:$a, DPR:$b)>,
1497 Requires<[HasVFP4,HasDPVFP,UseFusedMAC]>;
1498 def : Pat<(fsub_mlx (fmul_su SPR:$a, SPR:$b), SPR:$dstin),
1499 (VFNMSS SPR:$dstin, SPR:$a, SPR:$b)>,
1500 Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]>;
1502 // Match @llvm.fma.* intrinsics
1504 // (fma x, y, (fneg z)) -> (vfnms z, x, y))
1505 def : Pat<(f64 (fma DPR:$Dn, DPR:$Dm, (fneg DPR:$Ddin))),
1506 (VFNMSD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>,
1507 Requires<[HasVFP4,HasDPVFP]>;
1508 def : Pat<(f32 (fma SPR:$Sn, SPR:$Sm, (fneg SPR:$Sdin))),
1509 (VFNMSS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
1510 Requires<[HasVFP4]>;
1511 // (fneg (fma (fneg x), y, z)) -> (vfnms z, x, y)
1512 def : Pat<(fneg (f64 (fma (fneg DPR:$Dn), DPR:$Dm, DPR:$Ddin))),
1513 (VFNMSD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>,
1514 Requires<[HasVFP4,HasDPVFP]>;
1515 def : Pat<(fneg (f32 (fma (fneg SPR:$Sn), SPR:$Sm, SPR:$Sdin))),
1516 (VFNMSS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
1517 Requires<[HasVFP4]>;
1518 // (fneg (fma x, (fneg y), z) -> (vfnms z, x, y)
1519 def : Pat<(fneg (f64 (fma DPR:$Dn, (fneg DPR:$Dm), DPR:$Ddin))),
1520 (VFNMSD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>,
1521 Requires<[HasVFP4,HasDPVFP]>;
1522 def : Pat<(fneg (f32 (fma SPR:$Sn, (fneg SPR:$Sm), SPR:$Sdin))),
1523 (VFNMSS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
1524 Requires<[HasVFP4]>;
1526 //===----------------------------------------------------------------------===//
1527 // FP Conditional moves.
1530 let neverHasSideEffects = 1 in {
1531 def VMOVDcc : PseudoInst<(outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm, cmovpred:$p),
1533 [(set (f64 DPR:$Dd),
1534 (ARMcmov DPR:$Dn, DPR:$Dm, cmovpred:$p))]>,
1535 RegConstraint<"$Dn = $Dd">, Requires<[HasVFP2,HasDPVFP]>;
1537 def VMOVScc : PseudoInst<(outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm, cmovpred:$p),
1539 [(set (f32 SPR:$Sd),
1540 (ARMcmov SPR:$Sn, SPR:$Sm, cmovpred:$p))]>,
1541 RegConstraint<"$Sn = $Sd">, Requires<[HasVFP2]>;
1542 } // neverHasSideEffects
1544 //===----------------------------------------------------------------------===//
1545 // Move from VFP System Register to ARM core register.
1548 class MovFromVFP<bits<4> opc19_16, dag oops, dag iops, string opc, string asm,
1550 VFPAI<oops, iops, VFPMiscFrm, IIC_fpSTAT, opc, asm, pattern> {
1552 // Instruction operand.
1555 let Inst{27-20} = 0b11101111;
1556 let Inst{19-16} = opc19_16;
1557 let Inst{15-12} = Rt;
1558 let Inst{11-8} = 0b1010;
1560 let Inst{6-5} = 0b00;
1562 let Inst{3-0} = 0b0000;
1565 // APSR is the application level alias of CPSR. This FPSCR N, Z, C, V flags
1567 let Defs = [CPSR], Uses = [FPSCR_NZCV], Rt = 0b1111 /* apsr_nzcv */ in
1568 def FMSTAT : MovFromVFP<0b0001 /* fpscr */, (outs), (ins),
1569 "vmrs", "\tAPSR_nzcv, fpscr", [(arm_fmstat)]>;
1571 // Application level FPSCR -> GPR
1572 let hasSideEffects = 1, Uses = [FPSCR] in
1573 def VMRS : MovFromVFP<0b0001 /* fpscr */, (outs GPR:$Rt), (ins),
1574 "vmrs", "\t$Rt, fpscr",
1575 [(set GPR:$Rt, (int_arm_get_fpscr))]>;
1577 // System level FPEXC, FPSID -> GPR
1578 let Uses = [FPSCR] in {
1579 def VMRS_FPEXC : MovFromVFP<0b1000 /* fpexc */, (outs GPR:$Rt), (ins),
1580 "vmrs", "\t$Rt, fpexc", []>;
1581 def VMRS_FPSID : MovFromVFP<0b0000 /* fpsid */, (outs GPR:$Rt), (ins),
1582 "vmrs", "\t$Rt, fpsid", []>;
1583 def VMRS_MVFR0 : MovFromVFP<0b0111 /* mvfr0 */, (outs GPR:$Rt), (ins),
1584 "vmrs", "\t$Rt, mvfr0", []>;
1585 def VMRS_MVFR1 : MovFromVFP<0b0110 /* mvfr1 */, (outs GPR:$Rt), (ins),
1586 "vmrs", "\t$Rt, mvfr1", []>;
1587 def VMRS_MVFR2 : MovFromVFP<0b0101 /* mvfr2 */, (outs GPR:$Rt), (ins),
1588 "vmrs", "\t$Rt, mvfr2", []>, Requires<[HasFPARMv8]>;
1589 def VMRS_FPINST : MovFromVFP<0b1001 /* fpinst */, (outs GPR:$Rt), (ins),
1590 "vmrs", "\t$Rt, fpinst", []>;
1591 def VMRS_FPINST2 : MovFromVFP<0b1010 /* fpinst2 */, (outs GPR:$Rt), (ins),
1592 "vmrs", "\t$Rt, fpinst2", []>;
1595 //===----------------------------------------------------------------------===//
1596 // Move from ARM core register to VFP System Register.
1599 class MovToVFP<bits<4> opc19_16, dag oops, dag iops, string opc, string asm,
1601 VFPAI<oops, iops, VFPMiscFrm, IIC_fpSTAT, opc, asm, pattern> {
1603 // Instruction operand.
1606 // Encode instruction operand.
1607 let Inst{15-12} = src;
1609 let Inst{27-20} = 0b11101110;
1610 let Inst{19-16} = opc19_16;
1611 let Inst{11-8} = 0b1010;
1616 let Defs = [FPSCR] in {
1617 // Application level GPR -> FPSCR
1618 def VMSR : MovToVFP<0b0001 /* fpscr */, (outs), (ins GPR:$src),
1619 "vmsr", "\tfpscr, $src", [(int_arm_set_fpscr GPR:$src)]>;
1620 // System level GPR -> FPEXC
1621 def VMSR_FPEXC : MovToVFP<0b1000 /* fpexc */, (outs), (ins GPR:$src),
1622 "vmsr", "\tfpexc, $src", []>;
1623 // System level GPR -> FPSID
1624 def VMSR_FPSID : MovToVFP<0b0000 /* fpsid */, (outs), (ins GPR:$src),
1625 "vmsr", "\tfpsid, $src", []>;
1627 def VMSR_FPINST : MovToVFP<0b1001 /* fpinst */, (outs), (ins GPR:$src),
1628 "vmsr", "\tfpinst, $src", []>;
1629 def VMSR_FPINST2 : MovToVFP<0b1010 /* fpinst2 */, (outs), (ins GPR:$src),
1630 "vmsr", "\tfpinst2, $src", []>;
1633 //===----------------------------------------------------------------------===//
1637 // Materialize FP immediates. VFP3 only.
1638 let isReMaterializable = 1 in {
1639 def FCONSTD : VFPAI<(outs DPR:$Dd), (ins vfp_f64imm:$imm),
1640 VFPMiscFrm, IIC_fpUNA64,
1641 "vmov", ".f64\t$Dd, $imm",
1642 [(set DPR:$Dd, vfp_f64imm:$imm)]>,
1643 Requires<[HasVFP3,HasDPVFP]> {
1647 let Inst{27-23} = 0b11101;
1648 let Inst{22} = Dd{4};
1649 let Inst{21-20} = 0b11;
1650 let Inst{19-16} = imm{7-4};
1651 let Inst{15-12} = Dd{3-0};
1652 let Inst{11-9} = 0b101;
1653 let Inst{8} = 1; // Double precision.
1654 let Inst{7-4} = 0b0000;
1655 let Inst{3-0} = imm{3-0};
1658 def FCONSTS : VFPAI<(outs SPR:$Sd), (ins vfp_f32imm:$imm),
1659 VFPMiscFrm, IIC_fpUNA32,
1660 "vmov", ".f32\t$Sd, $imm",
1661 [(set SPR:$Sd, vfp_f32imm:$imm)]>, Requires<[HasVFP3]> {
1665 let Inst{27-23} = 0b11101;
1666 let Inst{22} = Sd{0};
1667 let Inst{21-20} = 0b11;
1668 let Inst{19-16} = imm{7-4};
1669 let Inst{15-12} = Sd{4-1};
1670 let Inst{11-9} = 0b101;
1671 let Inst{8} = 0; // Single precision.
1672 let Inst{7-4} = 0b0000;
1673 let Inst{3-0} = imm{3-0};
1677 //===----------------------------------------------------------------------===//
1678 // Assembler aliases.
1680 // A few mnemonic aliases for pre-unifixed syntax. We don't guarantee to
1681 // support them all, but supporting at least some of the basics is
1682 // good to be friendly.
1683 def : VFP2MnemonicAlias<"flds", "vldr">;
1684 def : VFP2MnemonicAlias<"fldd", "vldr">;
1685 def : VFP2MnemonicAlias<"fmrs", "vmov">;
1686 def : VFP2MnemonicAlias<"fmsr", "vmov">;
1687 def : VFP2MnemonicAlias<"fsqrts", "vsqrt">;
1688 def : VFP2MnemonicAlias<"fsqrtd", "vsqrt">;
1689 def : VFP2MnemonicAlias<"fadds", "vadd.f32">;
1690 def : VFP2MnemonicAlias<"faddd", "vadd.f64">;
1691 def : VFP2MnemonicAlias<"fmrdd", "vmov">;
1692 def : VFP2MnemonicAlias<"fmrds", "vmov">;
1693 def : VFP2MnemonicAlias<"fmrrd", "vmov">;
1694 def : VFP2MnemonicAlias<"fmdrr", "vmov">;
1695 def : VFP2MnemonicAlias<"fmuls", "vmul.f32">;
1696 def : VFP2MnemonicAlias<"fmuld", "vmul.f64">;
1697 def : VFP2MnemonicAlias<"fnegs", "vneg.f32">;
1698 def : VFP2MnemonicAlias<"fnegd", "vneg.f64">;
1699 def : VFP2MnemonicAlias<"ftosizd", "vcvt.s32.f64">;
1700 def : VFP2MnemonicAlias<"ftosid", "vcvtr.s32.f64">;
1701 def : VFP2MnemonicAlias<"ftosizs", "vcvt.s32.f32">;
1702 def : VFP2MnemonicAlias<"ftosis", "vcvtr.s32.f32">;
1703 def : VFP2MnemonicAlias<"ftouizd", "vcvt.u32.f64">;
1704 def : VFP2MnemonicAlias<"ftouid", "vcvtr.u32.f64">;
1705 def : VFP2MnemonicAlias<"ftouizs", "vcvt.u32.f32">;
1706 def : VFP2MnemonicAlias<"ftouis", "vcvtr.u32.f32">;
1707 def : VFP2MnemonicAlias<"fsitod", "vcvt.f64.s32">;
1708 def : VFP2MnemonicAlias<"fsitos", "vcvt.f32.s32">;
1709 def : VFP2MnemonicAlias<"fuitod", "vcvt.f64.u32">;
1710 def : VFP2MnemonicAlias<"fuitos", "vcvt.f32.u32">;
1711 def : VFP2MnemonicAlias<"fsts", "vstr">;
1712 def : VFP2MnemonicAlias<"fstd", "vstr">;
1713 def : VFP2MnemonicAlias<"fmacd", "vmla.f64">;
1714 def : VFP2MnemonicAlias<"fmacs", "vmla.f32">;
1715 def : VFP2MnemonicAlias<"fcpys", "vmov.f32">;
1716 def : VFP2MnemonicAlias<"fcpyd", "vmov.f64">;
1717 def : VFP2MnemonicAlias<"fcmps", "vcmp.f32">;
1718 def : VFP2MnemonicAlias<"fcmpd", "vcmp.f64">;
1719 def : VFP2MnemonicAlias<"fdivs", "vdiv.f32">;
1720 def : VFP2MnemonicAlias<"fdivd", "vdiv.f64">;
1721 def : VFP2MnemonicAlias<"fmrx", "vmrs">;
1722 def : VFP2MnemonicAlias<"fmxr", "vmsr">;
1724 // Be friendly and accept the old form of zero-compare
1725 def : VFP2DPInstAlias<"fcmpzd${p} $val", (VCMPZD DPR:$val, pred:$p)>;
1726 def : VFP2InstAlias<"fcmpzs${p} $val", (VCMPZS SPR:$val, pred:$p)>;
1729 def : VFP2InstAlias<"fmstat${p}", (FMSTAT pred:$p)>;
1730 def : VFP2InstAlias<"fadds${p} $Sd, $Sn, $Sm",
1731 (VADDS SPR:$Sd, SPR:$Sn, SPR:$Sm, pred:$p)>;
1732 def : VFP2DPInstAlias<"faddd${p} $Dd, $Dn, $Dm",
1733 (VADDD DPR:$Dd, DPR:$Dn, DPR:$Dm, pred:$p)>;
1734 def : VFP2InstAlias<"fsubs${p} $Sd, $Sn, $Sm",
1735 (VSUBS SPR:$Sd, SPR:$Sn, SPR:$Sm, pred:$p)>;
1736 def : VFP2DPInstAlias<"fsubd${p} $Dd, $Dn, $Dm",
1737 (VSUBD DPR:$Dd, DPR:$Dn, DPR:$Dm, pred:$p)>;
1739 // No need for the size suffix on VSQRT. It's implied by the register classes.
1740 def : VFP2InstAlias<"vsqrt${p} $Sd, $Sm", (VSQRTS SPR:$Sd, SPR:$Sm, pred:$p)>;
1741 def : VFP2DPInstAlias<"vsqrt${p} $Dd, $Dm", (VSQRTD DPR:$Dd, DPR:$Dm, pred:$p)>;
1743 // VLDR/VSTR accept an optional type suffix.
1744 def : VFP2InstAlias<"vldr${p}.32 $Sd, $addr",
1745 (VLDRS SPR:$Sd, addrmode5:$addr, pred:$p)>;
1746 def : VFP2InstAlias<"vstr${p}.32 $Sd, $addr",
1747 (VSTRS SPR:$Sd, addrmode5:$addr, pred:$p)>;
1748 def : VFP2InstAlias<"vldr${p}.64 $Dd, $addr",
1749 (VLDRD DPR:$Dd, addrmode5:$addr, pred:$p)>;
1750 def : VFP2InstAlias<"vstr${p}.64 $Dd, $addr",
1751 (VSTRD DPR:$Dd, addrmode5:$addr, pred:$p)>;
1753 // VMOV can accept optional 32-bit or less data type suffix suffix.
1754 def : VFP2InstAlias<"vmov${p}.8 $Rt, $Sn",
1755 (VMOVRS GPR:$Rt, SPR:$Sn, pred:$p)>;
1756 def : VFP2InstAlias<"vmov${p}.16 $Rt, $Sn",
1757 (VMOVRS GPR:$Rt, SPR:$Sn, pred:$p)>;
1758 def : VFP2InstAlias<"vmov${p}.32 $Rt, $Sn",
1759 (VMOVRS GPR:$Rt, SPR:$Sn, pred:$p)>;
1760 def : VFP2InstAlias<"vmov${p}.8 $Sn, $Rt",
1761 (VMOVSR SPR:$Sn, GPR:$Rt, pred:$p)>;
1762 def : VFP2InstAlias<"vmov${p}.16 $Sn, $Rt",
1763 (VMOVSR SPR:$Sn, GPR:$Rt, pred:$p)>;
1764 def : VFP2InstAlias<"vmov${p}.32 $Sn, $Rt",
1765 (VMOVSR SPR:$Sn, GPR:$Rt, pred:$p)>;
1767 def : VFP2InstAlias<"vmov${p}.f64 $Rt, $Rt2, $Dn",
1768 (VMOVRRD GPR:$Rt, GPR:$Rt2, DPR:$Dn, pred:$p)>;
1769 def : VFP2InstAlias<"vmov${p}.f64 $Dn, $Rt, $Rt2",
1770 (VMOVDRR DPR:$Dn, GPR:$Rt, GPR:$Rt2, pred:$p)>;
1772 // VMOVS doesn't need the .f32 to disambiguate from the NEON encoding the way
1774 def : VFP2InstAlias<"vmov${p} $Sd, $Sm",
1775 (VMOVS SPR:$Sd, SPR:$Sm, pred:$p)>;
1777 // FCONSTD/FCONSTS alias for vmov.f64/vmov.f32
1778 // These aliases provide added functionality over vmov.f instructions by
1779 // allowing users to write assembly containing encoded floating point constants
1780 // (e.g. #0x70 vs #1.0). Without these alises there is no way for the
1781 // assembler to accept encoded fp constants (but the equivalent fp-literal is
1782 // accepted directly by vmovf).
1783 def : VFP3InstAlias<"fconstd${p} $Dd, $val",
1784 (FCONSTD DPR:$Dd, vfp_f64imm:$val, pred:$p)>;
1785 def : VFP3InstAlias<"fconsts${p} $Sd, $val",
1786 (FCONSTS SPR:$Sd, vfp_f32imm:$val, pred:$p)>;