1 //===-- ARMInstrThumb2.td - Thumb2 support for ARM ---------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Thumb2 instruction set.
12 //===----------------------------------------------------------------------===//
14 // IT block predicate field
15 def it_pred_asmoperand : AsmOperandClass {
16 let Name = "ITCondCode";
17 let ParserMethod = "parseITCondCode";
19 def it_pred : Operand<i32> {
20 let PrintMethod = "printMandatoryPredicateOperand";
21 let ParserMatchClass = it_pred_asmoperand;
24 // IT block condition mask
25 def it_mask_asmoperand : AsmOperandClass { let Name = "ITMask"; }
26 def it_mask : Operand<i32> {
27 let PrintMethod = "printThumbITMask";
28 let ParserMatchClass = it_mask_asmoperand;
31 // t2_shift_imm: An integer that encodes a shift amount and the type of shift
32 // (asr or lsl). The 6-bit immediate encodes as:
35 // {4-0} imm5 shift amount.
36 // asr #32 not allowed
37 def t2_shift_imm : Operand<i32> {
38 let PrintMethod = "printShiftImmOperand";
39 let ParserMatchClass = ShifterImmAsmOperand;
40 let DecoderMethod = "DecodeT2ShifterImmOperand";
43 // Shifted operands. No register controlled shifts for Thumb2.
44 // Note: We do not support rrx shifted operands yet.
45 def t2_so_reg : Operand<i32>, // reg imm
46 ComplexPattern<i32, 2, "SelectT2ShifterOperandReg",
48 let EncoderMethod = "getT2SORegOpValue";
49 let PrintMethod = "printT2SOOperand";
50 let DecoderMethod = "DecodeSORegImmOperand";
51 let ParserMatchClass = ShiftedImmAsmOperand;
52 let MIOperandInfo = (ops rGPR, i32imm);
55 // t2_so_imm_not_XFORM - Return the complement of a t2_so_imm value
56 def t2_so_imm_not_XFORM : SDNodeXForm<imm, [{
57 return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), MVT::i32);
60 // t2_so_imm_neg_XFORM - Return the negation of a t2_so_imm value
61 def t2_so_imm_neg_XFORM : SDNodeXForm<imm, [{
62 return CurDAG->getTargetConstant(-((int)N->getZExtValue()), MVT::i32);
65 // so_imm_notSext_XFORM - Return a so_imm value packed into the format
66 // described for so_imm_notSext def below, with sign extension from 16
68 def t2_so_imm_notSext16_XFORM : SDNodeXForm<imm, [{
69 APInt apIntN = N->getAPIntValue();
70 unsigned N16bitSignExt = apIntN.trunc(16).sext(32).getZExtValue();
71 return CurDAG->getTargetConstant(~N16bitSignExt, MVT::i32);
74 // t2_so_imm - Match a 32-bit immediate operand, which is an
75 // 8-bit immediate rotated by an arbitrary number of bits, or an 8-bit
76 // immediate splatted into multiple bytes of the word.
77 def t2_so_imm_asmoperand : ImmAsmOperand { let Name = "T2SOImm"; }
78 def t2_so_imm : Operand<i32>, ImmLeaf<i32, [{
79 return ARM_AM::getT2SOImmVal(Imm) != -1;
81 let ParserMatchClass = t2_so_imm_asmoperand;
82 let EncoderMethod = "getT2SOImmOpValue";
83 let DecoderMethod = "DecodeT2SOImm";
86 // t2_so_imm_not - Match an immediate that is a complement
88 // Note: this pattern doesn't require an encoder method and such, as it's
89 // only used on aliases (Pat<> and InstAlias<>). The actual encoding
90 // is handled by the destination instructions, which use t2_so_imm.
91 def t2_so_imm_not_asmoperand : AsmOperandClass { let Name = "T2SOImmNot"; }
92 def t2_so_imm_not : Operand<i32>, PatLeaf<(imm), [{
93 return ARM_AM::getT2SOImmVal(~((uint32_t)N->getZExtValue())) != -1;
94 }], t2_so_imm_not_XFORM> {
95 let ParserMatchClass = t2_so_imm_not_asmoperand;
98 // t2_so_imm_notSext - match an immediate that is a complement of a t2_so_imm
99 // if the upper 16 bits are zero.
100 def t2_so_imm_notSext : Operand<i32>, PatLeaf<(imm), [{
101 APInt apIntN = N->getAPIntValue();
102 if (!apIntN.isIntN(16)) return false;
103 unsigned N16bitSignExt = apIntN.trunc(16).sext(32).getZExtValue();
104 return ARM_AM::getT2SOImmVal(~N16bitSignExt) != -1;
105 }], t2_so_imm_notSext16_XFORM> {
106 let ParserMatchClass = t2_so_imm_not_asmoperand;
109 // t2_so_imm_neg - Match an immediate that is a negation of a t2_so_imm.
110 def t2_so_imm_neg_asmoperand : AsmOperandClass { let Name = "T2SOImmNeg"; }
111 def t2_so_imm_neg : Operand<i32>, PatLeaf<(imm), [{
112 int64_t Value = -(int)N->getZExtValue();
113 return Value && ARM_AM::getT2SOImmVal(Value) != -1;
114 }], t2_so_imm_neg_XFORM> {
115 let ParserMatchClass = t2_so_imm_neg_asmoperand;
118 /// imm0_4095 predicate - True if the 32-bit immediate is in the range [0.4095].
119 def imm0_4095_asmoperand: ImmAsmOperand { let Name = "Imm0_4095"; }
120 def imm0_4095 : Operand<i32>, ImmLeaf<i32, [{
121 return Imm >= 0 && Imm < 4096;
123 let ParserMatchClass = imm0_4095_asmoperand;
126 def imm0_4095_neg_asmoperand: AsmOperandClass { let Name = "Imm0_4095Neg"; }
127 def imm0_4095_neg : Operand<i32>, PatLeaf<(i32 imm), [{
128 return (uint32_t)(-N->getZExtValue()) < 4096;
130 let ParserMatchClass = imm0_4095_neg_asmoperand;
133 def imm0_255_neg : PatLeaf<(i32 imm), [{
134 return (uint32_t)(-N->getZExtValue()) < 255;
137 def imm0_255_not : PatLeaf<(i32 imm), [{
138 return (uint32_t)(~N->getZExtValue()) < 255;
141 def lo5AllOne : PatLeaf<(i32 imm), [{
142 // Returns true if all low 5-bits are 1.
143 return (((uint32_t)N->getZExtValue()) & 0x1FUL) == 0x1FUL;
146 // Define Thumb2 specific addressing modes.
148 // t2addrmode_imm12 := reg + imm12
149 def t2addrmode_imm12_asmoperand : AsmOperandClass {let Name="MemUImm12Offset";}
150 def t2addrmode_imm12 : Operand<i32>,
151 ComplexPattern<i32, 2, "SelectT2AddrModeImm12", []> {
152 let PrintMethod = "printAddrModeImm12Operand";
153 let EncoderMethod = "getAddrModeImm12OpValue";
154 let DecoderMethod = "DecodeT2AddrModeImm12";
155 let ParserMatchClass = t2addrmode_imm12_asmoperand;
156 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
159 // t2ldrlabel := imm12
160 def t2ldrlabel : Operand<i32> {
161 let EncoderMethod = "getAddrModeImm12OpValue";
162 let PrintMethod = "printT2LdrLabelOperand";
165 def t2ldr_pcrel_imm12_asmoperand : AsmOperandClass {let Name = "MemPCRelImm12";}
166 def t2ldr_pcrel_imm12 : Operand<i32> {
167 let ParserMatchClass = t2ldr_pcrel_imm12_asmoperand;
168 // used for assembler pseudo instruction and maps to t2ldrlabel, so
169 // doesn't need encoder or print methods of its own.
172 // ADR instruction labels.
173 def t2adrlabel : Operand<i32> {
174 let EncoderMethod = "getT2AdrLabelOpValue";
175 let PrintMethod = "printAdrLabelOperand";
179 // t2addrmode_posimm8 := reg + imm8
180 def MemPosImm8OffsetAsmOperand : AsmOperandClass {let Name="MemPosImm8Offset";}
181 def t2addrmode_posimm8 : Operand<i32> {
182 let PrintMethod = "printT2AddrModeImm8Operand";
183 let EncoderMethod = "getT2AddrModeImm8OpValue";
184 let DecoderMethod = "DecodeT2AddrModeImm8";
185 let ParserMatchClass = MemPosImm8OffsetAsmOperand;
186 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
189 // t2addrmode_negimm8 := reg - imm8
190 def MemNegImm8OffsetAsmOperand : AsmOperandClass {let Name="MemNegImm8Offset";}
191 def t2addrmode_negimm8 : Operand<i32>,
192 ComplexPattern<i32, 2, "SelectT2AddrModeImm8", []> {
193 let PrintMethod = "printT2AddrModeImm8Operand";
194 let EncoderMethod = "getT2AddrModeImm8OpValue";
195 let DecoderMethod = "DecodeT2AddrModeImm8";
196 let ParserMatchClass = MemNegImm8OffsetAsmOperand;
197 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
200 // t2addrmode_imm8 := reg +/- imm8
201 def MemImm8OffsetAsmOperand : AsmOperandClass { let Name = "MemImm8Offset"; }
202 def t2addrmode_imm8 : Operand<i32>,
203 ComplexPattern<i32, 2, "SelectT2AddrModeImm8", []> {
204 let PrintMethod = "printT2AddrModeImm8Operand";
205 let EncoderMethod = "getT2AddrModeImm8OpValue";
206 let DecoderMethod = "DecodeT2AddrModeImm8";
207 let ParserMatchClass = MemImm8OffsetAsmOperand;
208 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
211 def t2am_imm8_offset : Operand<i32>,
212 ComplexPattern<i32, 1, "SelectT2AddrModeImm8Offset",
213 [], [SDNPWantRoot]> {
214 let PrintMethod = "printT2AddrModeImm8OffsetOperand";
215 let EncoderMethod = "getT2AddrModeImm8OffsetOpValue";
216 let DecoderMethod = "DecodeT2Imm8";
219 // t2addrmode_imm8s4 := reg +/- (imm8 << 2)
220 def MemImm8s4OffsetAsmOperand : AsmOperandClass {let Name = "MemImm8s4Offset";}
221 def t2addrmode_imm8s4 : Operand<i32> {
222 let PrintMethod = "printT2AddrModeImm8s4Operand";
223 let EncoderMethod = "getT2AddrModeImm8s4OpValue";
224 let DecoderMethod = "DecodeT2AddrModeImm8s4";
225 let ParserMatchClass = MemImm8s4OffsetAsmOperand;
226 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
229 def t2am_imm8s4_offset_asmoperand : AsmOperandClass { let Name = "Imm8s4"; }
230 def t2am_imm8s4_offset : Operand<i32> {
231 let PrintMethod = "printT2AddrModeImm8s4OffsetOperand";
232 let EncoderMethod = "getT2Imm8s4OpValue";
233 let DecoderMethod = "DecodeT2Imm8S4";
236 // t2addrmode_imm0_1020s4 := reg + (imm8 << 2)
237 def MemImm0_1020s4OffsetAsmOperand : AsmOperandClass {
238 let Name = "MemImm0_1020s4Offset";
240 def t2addrmode_imm0_1020s4 : Operand<i32> {
241 let PrintMethod = "printT2AddrModeImm0_1020s4Operand";
242 let EncoderMethod = "getT2AddrModeImm0_1020s4OpValue";
243 let DecoderMethod = "DecodeT2AddrModeImm0_1020s4";
244 let ParserMatchClass = MemImm0_1020s4OffsetAsmOperand;
245 let MIOperandInfo = (ops GPRnopc:$base, i32imm:$offsimm);
248 // t2addrmode_so_reg := reg + (reg << imm2)
249 def t2addrmode_so_reg_asmoperand : AsmOperandClass {let Name="T2MemRegOffset";}
250 def t2addrmode_so_reg : Operand<i32>,
251 ComplexPattern<i32, 3, "SelectT2AddrModeSoReg", []> {
252 let PrintMethod = "printT2AddrModeSoRegOperand";
253 let EncoderMethod = "getT2AddrModeSORegOpValue";
254 let DecoderMethod = "DecodeT2AddrModeSOReg";
255 let ParserMatchClass = t2addrmode_so_reg_asmoperand;
256 let MIOperandInfo = (ops GPR:$base, rGPR:$offsreg, i32imm:$offsimm);
259 // Addresses for the TBB/TBH instructions.
260 def addrmode_tbb_asmoperand : AsmOperandClass { let Name = "MemTBB"; }
261 def addrmode_tbb : Operand<i32> {
262 let PrintMethod = "printAddrModeTBB";
263 let ParserMatchClass = addrmode_tbb_asmoperand;
264 let MIOperandInfo = (ops GPR:$Rn, rGPR:$Rm);
266 def addrmode_tbh_asmoperand : AsmOperandClass { let Name = "MemTBH"; }
267 def addrmode_tbh : Operand<i32> {
268 let PrintMethod = "printAddrModeTBH";
269 let ParserMatchClass = addrmode_tbh_asmoperand;
270 let MIOperandInfo = (ops GPR:$Rn, rGPR:$Rm);
273 //===----------------------------------------------------------------------===//
274 // Multiclass helpers...
278 class T2OneRegImm<dag oops, dag iops, InstrItinClass itin,
279 string opc, string asm, list<dag> pattern>
280 : T2I<oops, iops, itin, opc, asm, pattern> {
285 let Inst{26} = imm{11};
286 let Inst{14-12} = imm{10-8};
287 let Inst{7-0} = imm{7-0};
291 class T2sOneRegImm<dag oops, dag iops, InstrItinClass itin,
292 string opc, string asm, list<dag> pattern>
293 : T2sI<oops, iops, itin, opc, asm, pattern> {
299 let Inst{26} = imm{11};
300 let Inst{14-12} = imm{10-8};
301 let Inst{7-0} = imm{7-0};
304 class T2OneRegCmpImm<dag oops, dag iops, InstrItinClass itin,
305 string opc, string asm, list<dag> pattern>
306 : T2I<oops, iops, itin, opc, asm, pattern> {
310 let Inst{19-16} = Rn;
311 let Inst{26} = imm{11};
312 let Inst{14-12} = imm{10-8};
313 let Inst{7-0} = imm{7-0};
317 class T2OneRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
318 string opc, string asm, list<dag> pattern>
319 : T2I<oops, iops, itin, opc, asm, pattern> {
324 let Inst{3-0} = ShiftedRm{3-0};
325 let Inst{5-4} = ShiftedRm{6-5};
326 let Inst{14-12} = ShiftedRm{11-9};
327 let Inst{7-6} = ShiftedRm{8-7};
330 class T2sOneRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
331 string opc, string asm, list<dag> pattern>
332 : T2sI<oops, iops, itin, opc, asm, pattern> {
337 let Inst{3-0} = ShiftedRm{3-0};
338 let Inst{5-4} = ShiftedRm{6-5};
339 let Inst{14-12} = ShiftedRm{11-9};
340 let Inst{7-6} = ShiftedRm{8-7};
343 class T2OneRegCmpShiftedReg<dag oops, dag iops, InstrItinClass itin,
344 string opc, string asm, list<dag> pattern>
345 : T2I<oops, iops, itin, opc, asm, pattern> {
349 let Inst{19-16} = Rn;
350 let Inst{3-0} = ShiftedRm{3-0};
351 let Inst{5-4} = ShiftedRm{6-5};
352 let Inst{14-12} = ShiftedRm{11-9};
353 let Inst{7-6} = ShiftedRm{8-7};
356 class T2TwoReg<dag oops, dag iops, InstrItinClass itin,
357 string opc, string asm, list<dag> pattern>
358 : T2I<oops, iops, itin, opc, asm, pattern> {
366 class T2sTwoReg<dag oops, dag iops, InstrItinClass itin,
367 string opc, string asm, list<dag> pattern>
368 : T2sI<oops, iops, itin, opc, asm, pattern> {
376 class T2TwoRegCmp<dag oops, dag iops, InstrItinClass itin,
377 string opc, string asm, list<dag> pattern>
378 : T2I<oops, iops, itin, opc, asm, pattern> {
382 let Inst{19-16} = Rn;
387 class T2TwoRegImm<dag oops, dag iops, InstrItinClass itin,
388 string opc, string asm, list<dag> pattern>
389 : T2I<oops, iops, itin, opc, asm, pattern> {
395 let Inst{19-16} = Rn;
396 let Inst{26} = imm{11};
397 let Inst{14-12} = imm{10-8};
398 let Inst{7-0} = imm{7-0};
401 class T2sTwoRegImm<dag oops, dag iops, InstrItinClass itin,
402 string opc, string asm, list<dag> pattern>
403 : T2sI<oops, iops, itin, opc, asm, pattern> {
409 let Inst{19-16} = Rn;
410 let Inst{26} = imm{11};
411 let Inst{14-12} = imm{10-8};
412 let Inst{7-0} = imm{7-0};
415 class T2TwoRegShiftImm<dag oops, dag iops, InstrItinClass itin,
416 string opc, string asm, list<dag> pattern>
417 : T2I<oops, iops, itin, opc, asm, pattern> {
424 let Inst{14-12} = imm{4-2};
425 let Inst{7-6} = imm{1-0};
428 class T2sTwoRegShiftImm<dag oops, dag iops, InstrItinClass itin,
429 string opc, string asm, list<dag> pattern>
430 : T2sI<oops, iops, itin, opc, asm, pattern> {
437 let Inst{14-12} = imm{4-2};
438 let Inst{7-6} = imm{1-0};
441 class T2ThreeReg<dag oops, dag iops, InstrItinClass itin,
442 string opc, string asm, list<dag> pattern>
443 : T2I<oops, iops, itin, opc, asm, pattern> {
449 let Inst{19-16} = Rn;
453 class T2sThreeReg<dag oops, dag iops, InstrItinClass itin,
454 string opc, string asm, list<dag> pattern>
455 : T2sI<oops, iops, itin, opc, asm, pattern> {
461 let Inst{19-16} = Rn;
465 class T2TwoRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
466 string opc, string asm, list<dag> pattern>
467 : T2I<oops, iops, itin, opc, asm, pattern> {
473 let Inst{19-16} = Rn;
474 let Inst{3-0} = ShiftedRm{3-0};
475 let Inst{5-4} = ShiftedRm{6-5};
476 let Inst{14-12} = ShiftedRm{11-9};
477 let Inst{7-6} = ShiftedRm{8-7};
480 class T2sTwoRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
481 string opc, string asm, list<dag> pattern>
482 : T2sI<oops, iops, itin, opc, asm, pattern> {
488 let Inst{19-16} = Rn;
489 let Inst{3-0} = ShiftedRm{3-0};
490 let Inst{5-4} = ShiftedRm{6-5};
491 let Inst{14-12} = ShiftedRm{11-9};
492 let Inst{7-6} = ShiftedRm{8-7};
495 class T2FourReg<dag oops, dag iops, InstrItinClass itin,
496 string opc, string asm, list<dag> pattern>
497 : T2I<oops, iops, itin, opc, asm, pattern> {
503 let Inst{19-16} = Rn;
504 let Inst{15-12} = Ra;
509 class T2MulLong<bits<3> opc22_20, bits<4> opc7_4,
510 dag oops, dag iops, InstrItinClass itin,
511 string opc, string asm, list<dag> pattern>
512 : T2I<oops, iops, itin, opc, asm, pattern> {
518 let Inst{31-23} = 0b111110111;
519 let Inst{22-20} = opc22_20;
520 let Inst{19-16} = Rn;
521 let Inst{15-12} = RdLo;
522 let Inst{11-8} = RdHi;
523 let Inst{7-4} = opc7_4;
526 class T2MlaLong<bits<3> opc22_20, bits<4> opc7_4,
527 dag oops, dag iops, InstrItinClass itin,
528 string opc, string asm, list<dag> pattern>
529 : T2I<oops, iops, itin, opc, asm, pattern> {
535 let Inst{31-23} = 0b111110111;
536 let Inst{22-20} = opc22_20;
537 let Inst{19-16} = Rn;
538 let Inst{15-12} = RdLo;
539 let Inst{11-8} = RdHi;
540 let Inst{7-4} = opc7_4;
545 /// T2I_bin_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a
546 /// binary operation that produces a value. These are predicable and can be
547 /// changed to modify CPSR.
548 multiclass T2I_bin_irs<bits<4> opcod, string opc,
549 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
550 PatFrag opnode, bit Commutable = 0,
553 def ri : T2sTwoRegImm<
554 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm), iii,
555 opc, "\t$Rd, $Rn, $imm",
556 [(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_imm:$imm))]> {
557 let Inst{31-27} = 0b11110;
559 let Inst{24-21} = opcod;
563 def rr : T2sThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), iir,
564 opc, !strconcat(wide, "\t$Rd, $Rn, $Rm"),
565 [(set rGPR:$Rd, (opnode rGPR:$Rn, rGPR:$Rm))]> {
566 let isCommutable = Commutable;
567 let Inst{31-27} = 0b11101;
568 let Inst{26-25} = 0b01;
569 let Inst{24-21} = opcod;
570 let Inst{14-12} = 0b000; // imm3
571 let Inst{7-6} = 0b00; // imm2
572 let Inst{5-4} = 0b00; // type
575 def rs : T2sTwoRegShiftedReg<
576 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm), iis,
577 opc, !strconcat(wide, "\t$Rd, $Rn, $ShiftedRm"),
578 [(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_reg:$ShiftedRm))]> {
579 let Inst{31-27} = 0b11101;
580 let Inst{26-25} = 0b01;
581 let Inst{24-21} = opcod;
583 // Assembly aliases for optional destination operand when it's the same
584 // as the source operand.
585 def : t2InstAlias<!strconcat(opc, "${s}${p} $Rdn, $imm"),
586 (!cast<Instruction>(NAME#"ri") rGPR:$Rdn, rGPR:$Rdn,
587 t2_so_imm:$imm, pred:$p,
589 def : t2InstAlias<!strconcat(opc, "${s}${p}", wide, " $Rdn, $Rm"),
590 (!cast<Instruction>(NAME#"rr") rGPR:$Rdn, rGPR:$Rdn,
593 def : t2InstAlias<!strconcat(opc, "${s}${p}", wide, " $Rdn, $shift"),
594 (!cast<Instruction>(NAME#"rs") rGPR:$Rdn, rGPR:$Rdn,
595 t2_so_reg:$shift, pred:$p,
599 /// T2I_bin_w_irs - Same as T2I_bin_irs except these operations need
600 // the ".w" suffix to indicate that they are wide.
601 multiclass T2I_bin_w_irs<bits<4> opcod, string opc,
602 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
603 PatFrag opnode, bit Commutable = 0> :
604 T2I_bin_irs<opcod, opc, iii, iir, iis, opnode, Commutable, ".w"> {
605 // Assembler aliases w/ the ".w" suffix.
606 def : t2InstAlias<!strconcat(opc, "${s}${p}.w", " $Rd, $Rn, $imm"),
607 (!cast<Instruction>(NAME#"ri") rGPR:$Rd, rGPR:$Rn, t2_so_imm:$imm, pred:$p,
609 // Assembler aliases w/o the ".w" suffix.
610 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rd, $Rn, $Rm"),
611 (!cast<Instruction>(NAME#"rr") rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, pred:$p,
613 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rd, $Rn, $shift"),
614 (!cast<Instruction>(NAME#"rs") rGPR:$Rd, rGPR:$Rn, t2_so_reg:$shift,
615 pred:$p, cc_out:$s)>;
617 // and with the optional destination operand, too.
618 def : t2InstAlias<!strconcat(opc, "${s}${p}.w", " $Rdn, $imm"),
619 (!cast<Instruction>(NAME#"ri") rGPR:$Rdn, rGPR:$Rdn, t2_so_imm:$imm,
620 pred:$p, cc_out:$s)>;
621 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rdn, $Rm"),
622 (!cast<Instruction>(NAME#"rr") rGPR:$Rdn, rGPR:$Rdn, rGPR:$Rm, pred:$p,
624 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rdn, $shift"),
625 (!cast<Instruction>(NAME#"rs") rGPR:$Rdn, rGPR:$Rdn, t2_so_reg:$shift,
626 pred:$p, cc_out:$s)>;
629 /// T2I_rbin_is - Same as T2I_bin_irs except the order of operands are
630 /// reversed. The 'rr' form is only defined for the disassembler; for codegen
631 /// it is equivalent to the T2I_bin_irs counterpart.
632 multiclass T2I_rbin_irs<bits<4> opcod, string opc, PatFrag opnode> {
634 def ri : T2sTwoRegImm<
635 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm), IIC_iALUi,
636 opc, ".w\t$Rd, $Rn, $imm",
637 [(set rGPR:$Rd, (opnode t2_so_imm:$imm, rGPR:$Rn))]> {
638 let Inst{31-27} = 0b11110;
640 let Inst{24-21} = opcod;
644 def rr : T2sThreeReg<
645 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUr,
646 opc, "\t$Rd, $Rn, $Rm",
647 [/* For disassembly only; pattern left blank */]> {
648 let Inst{31-27} = 0b11101;
649 let Inst{26-25} = 0b01;
650 let Inst{24-21} = opcod;
651 let Inst{14-12} = 0b000; // imm3
652 let Inst{7-6} = 0b00; // imm2
653 let Inst{5-4} = 0b00; // type
656 def rs : T2sTwoRegShiftedReg<
657 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm),
658 IIC_iALUsir, opc, "\t$Rd, $Rn, $ShiftedRm",
659 [(set rGPR:$Rd, (opnode t2_so_reg:$ShiftedRm, rGPR:$Rn))]> {
660 let Inst{31-27} = 0b11101;
661 let Inst{26-25} = 0b01;
662 let Inst{24-21} = opcod;
666 /// T2I_bin_s_irs - Similar to T2I_bin_irs except it sets the 's' bit so the
667 /// instruction modifies the CPSR register.
669 /// These opcodes will be converted to the real non-S opcodes by
670 /// AdjustInstrPostInstrSelection after giving then an optional CPSR operand.
671 let hasPostISelHook = 1, Defs = [CPSR] in {
672 multiclass T2I_bin_s_irs<InstrItinClass iii, InstrItinClass iir,
673 InstrItinClass iis, PatFrag opnode,
674 bit Commutable = 0> {
676 def ri : t2PseudoInst<(outs rGPR:$Rd),
677 (ins GPRnopc:$Rn, t2_so_imm:$imm, pred:$p),
679 [(set rGPR:$Rd, CPSR, (opnode GPRnopc:$Rn,
682 def rr : t2PseudoInst<(outs rGPR:$Rd), (ins GPRnopc:$Rn, rGPR:$Rm, pred:$p),
684 [(set rGPR:$Rd, CPSR, (opnode GPRnopc:$Rn,
686 let isCommutable = Commutable;
689 def rs : t2PseudoInst<(outs rGPR:$Rd),
690 (ins GPRnopc:$Rn, t2_so_reg:$ShiftedRm, pred:$p),
692 [(set rGPR:$Rd, CPSR, (opnode GPRnopc:$Rn,
693 t2_so_reg:$ShiftedRm))]>;
697 /// T2I_rbin_s_is - Same as T2I_bin_s_irs, except selection DAG
698 /// operands are reversed.
699 let hasPostISelHook = 1, Defs = [CPSR] in {
700 multiclass T2I_rbin_s_is<PatFrag opnode> {
702 def ri : t2PseudoInst<(outs rGPR:$Rd),
703 (ins rGPR:$Rn, t2_so_imm:$imm, pred:$p),
705 [(set rGPR:$Rd, CPSR, (opnode t2_so_imm:$imm,
708 def rs : t2PseudoInst<(outs rGPR:$Rd),
709 (ins rGPR:$Rn, t2_so_reg:$ShiftedRm, pred:$p),
711 [(set rGPR:$Rd, CPSR, (opnode t2_so_reg:$ShiftedRm,
716 /// T2I_bin_ii12rs - Defines a set of (op reg, {so_imm|imm0_4095|r|so_reg})
717 /// patterns for a binary operation that produces a value.
718 multiclass T2I_bin_ii12rs<bits<3> op23_21, string opc, PatFrag opnode,
719 bit Commutable = 0> {
721 // The register-immediate version is re-materializable. This is useful
722 // in particular for taking the address of a local.
723 let isReMaterializable = 1 in {
724 def ri : T2sTwoRegImm<
725 (outs GPRnopc:$Rd), (ins GPRnopc:$Rn, t2_so_imm:$imm), IIC_iALUi,
726 opc, ".w\t$Rd, $Rn, $imm",
727 [(set GPRnopc:$Rd, (opnode GPRnopc:$Rn, t2_so_imm:$imm))]> {
728 let Inst{31-27} = 0b11110;
731 let Inst{23-21} = op23_21;
737 (outs GPRnopc:$Rd), (ins GPR:$Rn, imm0_4095:$imm), IIC_iALUi,
738 !strconcat(opc, "w"), "\t$Rd, $Rn, $imm",
739 [(set GPRnopc:$Rd, (opnode GPR:$Rn, imm0_4095:$imm))]> {
743 let Inst{31-27} = 0b11110;
744 let Inst{26} = imm{11};
745 let Inst{25-24} = 0b10;
746 let Inst{23-21} = op23_21;
747 let Inst{20} = 0; // The S bit.
748 let Inst{19-16} = Rn;
750 let Inst{14-12} = imm{10-8};
752 let Inst{7-0} = imm{7-0};
755 def rr : T2sThreeReg<(outs GPRnopc:$Rd), (ins GPRnopc:$Rn, rGPR:$Rm),
756 IIC_iALUr, opc, ".w\t$Rd, $Rn, $Rm",
757 [(set GPRnopc:$Rd, (opnode GPRnopc:$Rn, rGPR:$Rm))]> {
758 let isCommutable = Commutable;
759 let Inst{31-27} = 0b11101;
760 let Inst{26-25} = 0b01;
762 let Inst{23-21} = op23_21;
763 let Inst{14-12} = 0b000; // imm3
764 let Inst{7-6} = 0b00; // imm2
765 let Inst{5-4} = 0b00; // type
768 def rs : T2sTwoRegShiftedReg<
769 (outs GPRnopc:$Rd), (ins GPRnopc:$Rn, t2_so_reg:$ShiftedRm),
770 IIC_iALUsi, opc, ".w\t$Rd, $Rn, $ShiftedRm",
771 [(set GPRnopc:$Rd, (opnode GPRnopc:$Rn, t2_so_reg:$ShiftedRm))]> {
772 let Inst{31-27} = 0b11101;
773 let Inst{26-25} = 0b01;
775 let Inst{23-21} = op23_21;
779 /// T2I_adde_sube_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns
780 /// for a binary operation that produces a value and use the carry
781 /// bit. It's not predicable.
782 let Defs = [CPSR], Uses = [CPSR] in {
783 multiclass T2I_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
784 bit Commutable = 0> {
786 def ri : T2sTwoRegImm<(outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm),
787 IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
788 [(set rGPR:$Rd, CPSR, (opnode rGPR:$Rn, t2_so_imm:$imm, CPSR))]>,
789 Requires<[IsThumb2]> {
790 let Inst{31-27} = 0b11110;
792 let Inst{24-21} = opcod;
796 def rr : T2sThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUr,
797 opc, ".w\t$Rd, $Rn, $Rm",
798 [(set rGPR:$Rd, CPSR, (opnode rGPR:$Rn, rGPR:$Rm, CPSR))]>,
799 Requires<[IsThumb2]> {
800 let isCommutable = Commutable;
801 let Inst{31-27} = 0b11101;
802 let Inst{26-25} = 0b01;
803 let Inst{24-21} = opcod;
804 let Inst{14-12} = 0b000; // imm3
805 let Inst{7-6} = 0b00; // imm2
806 let Inst{5-4} = 0b00; // type
809 def rs : T2sTwoRegShiftedReg<
810 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm),
811 IIC_iALUsi, opc, ".w\t$Rd, $Rn, $ShiftedRm",
812 [(set rGPR:$Rd, CPSR, (opnode rGPR:$Rn, t2_so_reg:$ShiftedRm, CPSR))]>,
813 Requires<[IsThumb2]> {
814 let Inst{31-27} = 0b11101;
815 let Inst{26-25} = 0b01;
816 let Inst{24-21} = opcod;
821 /// T2I_sh_ir - Defines a set of (op reg, {so_imm|r}) patterns for a shift /
822 // rotate operation that produces a value.
823 multiclass T2I_sh_ir<bits<2> opcod, string opc, Operand ty, PatFrag opnode> {
825 def ri : T2sTwoRegShiftImm<
826 (outs rGPR:$Rd), (ins rGPR:$Rm, ty:$imm), IIC_iMOVsi,
827 opc, ".w\t$Rd, $Rm, $imm",
828 [(set rGPR:$Rd, (opnode rGPR:$Rm, (i32 ty:$imm)))]> {
829 let Inst{31-27} = 0b11101;
830 let Inst{26-21} = 0b010010;
831 let Inst{19-16} = 0b1111; // Rn
832 let Inst{5-4} = opcod;
835 def rr : T2sThreeReg<
836 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMOVsr,
837 opc, ".w\t$Rd, $Rn, $Rm",
838 [(set rGPR:$Rd, (opnode rGPR:$Rn, rGPR:$Rm))]> {
839 let Inst{31-27} = 0b11111;
840 let Inst{26-23} = 0b0100;
841 let Inst{22-21} = opcod;
842 let Inst{15-12} = 0b1111;
843 let Inst{7-4} = 0b0000;
846 // Optional destination register
847 def : t2InstAlias<!strconcat(opc, "${s}${p}", ".w $Rdn, $imm"),
848 (!cast<Instruction>(NAME#"ri") rGPR:$Rdn, rGPR:$Rdn, ty:$imm, pred:$p,
850 def : t2InstAlias<!strconcat(opc, "${s}${p}", ".w $Rdn, $Rm"),
851 (!cast<Instruction>(NAME#"rr") rGPR:$Rdn, rGPR:$Rdn, rGPR:$Rm, pred:$p,
854 // Assembler aliases w/o the ".w" suffix.
855 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rd, $Rn, $imm"),
856 (!cast<Instruction>(NAME#"ri") rGPR:$Rd, rGPR:$Rn, ty:$imm, pred:$p,
858 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rd, $Rn, $Rm"),
859 (!cast<Instruction>(NAME#"rr") rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, pred:$p,
862 // and with the optional destination operand, too.
863 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rdn, $imm"),
864 (!cast<Instruction>(NAME#"ri") rGPR:$Rdn, rGPR:$Rdn, ty:$imm, pred:$p,
866 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rdn, $Rm"),
867 (!cast<Instruction>(NAME#"rr") rGPR:$Rdn, rGPR:$Rdn, rGPR:$Rm, pred:$p,
871 /// T2I_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
872 /// patterns. Similar to T2I_bin_irs except the instruction does not produce
873 /// a explicit result, only implicitly set CPSR.
874 multiclass T2I_cmp_irs<bits<4> opcod, string opc,
875 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
877 let isCompare = 1, Defs = [CPSR] in {
879 def ri : T2OneRegCmpImm<
880 (outs), (ins GPRnopc:$Rn, t2_so_imm:$imm), iii,
881 opc, ".w\t$Rn, $imm",
882 [(opnode GPRnopc:$Rn, t2_so_imm:$imm)]> {
883 let Inst{31-27} = 0b11110;
885 let Inst{24-21} = opcod;
886 let Inst{20} = 1; // The S bit.
888 let Inst{11-8} = 0b1111; // Rd
891 def rr : T2TwoRegCmp<
892 (outs), (ins GPRnopc:$Rn, rGPR:$Rm), iir,
894 [(opnode GPRnopc:$Rn, rGPR:$Rm)]> {
895 let Inst{31-27} = 0b11101;
896 let Inst{26-25} = 0b01;
897 let Inst{24-21} = opcod;
898 let Inst{20} = 1; // The S bit.
899 let Inst{14-12} = 0b000; // imm3
900 let Inst{11-8} = 0b1111; // Rd
901 let Inst{7-6} = 0b00; // imm2
902 let Inst{5-4} = 0b00; // type
905 def rs : T2OneRegCmpShiftedReg<
906 (outs), (ins GPRnopc:$Rn, t2_so_reg:$ShiftedRm), iis,
907 opc, ".w\t$Rn, $ShiftedRm",
908 [(opnode GPRnopc:$Rn, t2_so_reg:$ShiftedRm)]> {
909 let Inst{31-27} = 0b11101;
910 let Inst{26-25} = 0b01;
911 let Inst{24-21} = opcod;
912 let Inst{20} = 1; // The S bit.
913 let Inst{11-8} = 0b1111; // Rd
917 // Assembler aliases w/o the ".w" suffix.
918 // No alias here for 'rr' version as not all instantiations of this
919 // multiclass want one (CMP in particular, does not).
920 def : t2InstAlias<!strconcat(opc, "${p}", " $Rn, $imm"),
921 (!cast<Instruction>(NAME#"ri") GPRnopc:$Rn, t2_so_imm:$imm, pred:$p)>;
922 def : t2InstAlias<!strconcat(opc, "${p}", " $Rn, $shift"),
923 (!cast<Instruction>(NAME#"rs") GPRnopc:$Rn, t2_so_reg:$shift, pred:$p)>;
926 /// T2I_ld - Defines a set of (op r, {imm12|imm8|so_reg}) load patterns.
927 multiclass T2I_ld<bit signed, bits<2> opcod, string opc,
928 InstrItinClass iii, InstrItinClass iis, RegisterClass target,
930 def i12 : T2Ii12<(outs target:$Rt), (ins t2addrmode_imm12:$addr), iii,
931 opc, ".w\t$Rt, $addr",
932 [(set target:$Rt, (opnode t2addrmode_imm12:$addr))]> {
935 let Inst{31-25} = 0b1111100;
936 let Inst{24} = signed;
938 let Inst{22-21} = opcod;
939 let Inst{20} = 1; // load
940 let Inst{19-16} = addr{16-13}; // Rn
941 let Inst{15-12} = Rt;
942 let Inst{11-0} = addr{11-0}; // imm
944 def i8 : T2Ii8 <(outs target:$Rt), (ins t2addrmode_negimm8:$addr), iii,
946 [(set target:$Rt, (opnode t2addrmode_negimm8:$addr))]> {
949 let Inst{31-27} = 0b11111;
950 let Inst{26-25} = 0b00;
951 let Inst{24} = signed;
953 let Inst{22-21} = opcod;
954 let Inst{20} = 1; // load
955 let Inst{19-16} = addr{12-9}; // Rn
956 let Inst{15-12} = Rt;
958 // Offset: index==TRUE, wback==FALSE
959 let Inst{10} = 1; // The P bit.
960 let Inst{9} = addr{8}; // U
961 let Inst{8} = 0; // The W bit.
962 let Inst{7-0} = addr{7-0}; // imm
964 def s : T2Iso <(outs target:$Rt), (ins t2addrmode_so_reg:$addr), iis,
965 opc, ".w\t$Rt, $addr",
966 [(set target:$Rt, (opnode t2addrmode_so_reg:$addr))]> {
967 let Inst{31-27} = 0b11111;
968 let Inst{26-25} = 0b00;
969 let Inst{24} = signed;
971 let Inst{22-21} = opcod;
972 let Inst{20} = 1; // load
973 let Inst{11-6} = 0b000000;
976 let Inst{15-12} = Rt;
979 let Inst{19-16} = addr{9-6}; // Rn
980 let Inst{3-0} = addr{5-2}; // Rm
981 let Inst{5-4} = addr{1-0}; // imm
983 let DecoderMethod = "DecodeT2LoadShift";
986 // pci variant is very similar to i12, but supports negative offsets
988 def pci : T2Ipc <(outs target:$Rt), (ins t2ldrlabel:$addr), iii,
989 opc, ".w\t$Rt, $addr",
990 [(set target:$Rt, (opnode (ARMWrapper tconstpool:$addr)))]> {
991 let isReMaterializable = 1;
992 let Inst{31-27} = 0b11111;
993 let Inst{26-25} = 0b00;
994 let Inst{24} = signed;
995 let Inst{23} = ?; // add = (U == '1')
996 let Inst{22-21} = opcod;
997 let Inst{20} = 1; // load
998 let Inst{19-16} = 0b1111; // Rn
1001 let Inst{15-12} = Rt{3-0};
1002 let Inst{11-0} = addr{11-0};
1006 /// T2I_st - Defines a set of (op r, {imm12|imm8|so_reg}) store patterns.
1007 multiclass T2I_st<bits<2> opcod, string opc,
1008 InstrItinClass iii, InstrItinClass iis, RegisterClass target,
1010 def i12 : T2Ii12<(outs), (ins target:$Rt, t2addrmode_imm12:$addr), iii,
1011 opc, ".w\t$Rt, $addr",
1012 [(opnode target:$Rt, t2addrmode_imm12:$addr)]> {
1013 let Inst{31-27} = 0b11111;
1014 let Inst{26-23} = 0b0001;
1015 let Inst{22-21} = opcod;
1016 let Inst{20} = 0; // !load
1019 let Inst{15-12} = Rt;
1022 let addr{12} = 1; // add = TRUE
1023 let Inst{19-16} = addr{16-13}; // Rn
1024 let Inst{23} = addr{12}; // U
1025 let Inst{11-0} = addr{11-0}; // imm
1027 def i8 : T2Ii8 <(outs), (ins target:$Rt, t2addrmode_negimm8:$addr), iii,
1028 opc, "\t$Rt, $addr",
1029 [(opnode target:$Rt, t2addrmode_negimm8:$addr)]> {
1030 let Inst{31-27} = 0b11111;
1031 let Inst{26-23} = 0b0000;
1032 let Inst{22-21} = opcod;
1033 let Inst{20} = 0; // !load
1035 // Offset: index==TRUE, wback==FALSE
1036 let Inst{10} = 1; // The P bit.
1037 let Inst{8} = 0; // The W bit.
1040 let Inst{15-12} = Rt;
1043 let Inst{19-16} = addr{12-9}; // Rn
1044 let Inst{9} = addr{8}; // U
1045 let Inst{7-0} = addr{7-0}; // imm
1047 def s : T2Iso <(outs), (ins target:$Rt, t2addrmode_so_reg:$addr), iis,
1048 opc, ".w\t$Rt, $addr",
1049 [(opnode target:$Rt, t2addrmode_so_reg:$addr)]> {
1050 let Inst{31-27} = 0b11111;
1051 let Inst{26-23} = 0b0000;
1052 let Inst{22-21} = opcod;
1053 let Inst{20} = 0; // !load
1054 let Inst{11-6} = 0b000000;
1057 let Inst{15-12} = Rt;
1060 let Inst{19-16} = addr{9-6}; // Rn
1061 let Inst{3-0} = addr{5-2}; // Rm
1062 let Inst{5-4} = addr{1-0}; // imm
1066 /// T2I_ext_rrot - A unary operation with two forms: one whose operand is a
1067 /// register and one whose operand is a register rotated by 8/16/24.
1068 class T2I_ext_rrot<bits<3> opcod, string opc, PatFrag opnode>
1069 : T2TwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm, rot_imm:$rot), IIC_iEXTr,
1070 opc, ".w\t$Rd, $Rm$rot",
1071 [(set rGPR:$Rd, (opnode (rotr rGPR:$Rm, rot_imm:$rot)))]>,
1072 Requires<[IsThumb2]> {
1073 let Inst{31-27} = 0b11111;
1074 let Inst{26-23} = 0b0100;
1075 let Inst{22-20} = opcod;
1076 let Inst{19-16} = 0b1111; // Rn
1077 let Inst{15-12} = 0b1111;
1081 let Inst{5-4} = rot{1-0}; // rotate
1084 // UXTB16 - Requres T2ExtractPack, does not need the .w qualifier.
1085 class T2I_ext_rrot_uxtb16<bits<3> opcod, string opc, PatFrag opnode>
1086 : T2TwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm, rot_imm:$rot),
1087 IIC_iEXTr, opc, "\t$Rd, $Rm$rot",
1088 [(set rGPR:$Rd, (opnode (rotr rGPR:$Rm, rot_imm:$rot)))]>,
1089 Requires<[HasT2ExtractPack, IsThumb2]> {
1091 let Inst{31-27} = 0b11111;
1092 let Inst{26-23} = 0b0100;
1093 let Inst{22-20} = opcod;
1094 let Inst{19-16} = 0b1111; // Rn
1095 let Inst{15-12} = 0b1111;
1097 let Inst{5-4} = rot;
1100 // SXTB16 - Requres T2ExtractPack, does not need the .w qualifier, no pattern
1102 class T2I_ext_rrot_sxtb16<bits<3> opcod, string opc>
1103 : T2TwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm, rot_imm:$rot), IIC_iEXTr,
1104 opc, "\t$Rd, $Rm$rot", []>,
1105 Requires<[IsThumb2, HasT2ExtractPack]> {
1107 let Inst{31-27} = 0b11111;
1108 let Inst{26-23} = 0b0100;
1109 let Inst{22-20} = opcod;
1110 let Inst{19-16} = 0b1111; // Rn
1111 let Inst{15-12} = 0b1111;
1113 let Inst{5-4} = rot;
1116 /// T2I_exta_rrot - A binary operation with two forms: one whose operand is a
1117 /// register and one whose operand is a register rotated by 8/16/24.
1118 class T2I_exta_rrot<bits<3> opcod, string opc, PatFrag opnode>
1119 : T2ThreeReg<(outs rGPR:$Rd),
1120 (ins rGPR:$Rn, rGPR:$Rm, rot_imm:$rot),
1121 IIC_iEXTAsr, opc, "\t$Rd, $Rn, $Rm$rot",
1122 [(set rGPR:$Rd, (opnode rGPR:$Rn, (rotr rGPR:$Rm,rot_imm:$rot)))]>,
1123 Requires<[HasT2ExtractPack, IsThumb2]> {
1125 let Inst{31-27} = 0b11111;
1126 let Inst{26-23} = 0b0100;
1127 let Inst{22-20} = opcod;
1128 let Inst{15-12} = 0b1111;
1130 let Inst{5-4} = rot;
1133 class T2I_exta_rrot_np<bits<3> opcod, string opc>
1134 : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm,rot_imm:$rot),
1135 IIC_iEXTAsr, opc, "\t$Rd, $Rn, $Rm$rot", []> {
1137 let Inst{31-27} = 0b11111;
1138 let Inst{26-23} = 0b0100;
1139 let Inst{22-20} = opcod;
1140 let Inst{15-12} = 0b1111;
1142 let Inst{5-4} = rot;
1145 //===----------------------------------------------------------------------===//
1147 //===----------------------------------------------------------------------===//
1149 //===----------------------------------------------------------------------===//
1150 // Miscellaneous Instructions.
1153 class T2PCOneRegImm<dag oops, dag iops, InstrItinClass itin,
1154 string asm, list<dag> pattern>
1155 : T2XI<oops, iops, itin, asm, pattern> {
1159 let Inst{11-8} = Rd;
1160 let Inst{26} = label{11};
1161 let Inst{14-12} = label{10-8};
1162 let Inst{7-0} = label{7-0};
1165 // LEApcrel - Load a pc-relative address into a register without offending the
1167 def t2ADR : T2PCOneRegImm<(outs rGPR:$Rd),
1168 (ins t2adrlabel:$addr, pred:$p),
1169 IIC_iALUi, "adr{$p}.w\t$Rd, $addr", []> {
1170 let Inst{31-27} = 0b11110;
1171 let Inst{25-24} = 0b10;
1172 // Inst{23:21} = '11' (add = FALSE) or '00' (add = TRUE)
1175 let Inst{19-16} = 0b1111; // Rn
1180 let Inst{11-8} = Rd;
1181 let Inst{23} = addr{12};
1182 let Inst{21} = addr{12};
1183 let Inst{26} = addr{11};
1184 let Inst{14-12} = addr{10-8};
1185 let Inst{7-0} = addr{7-0};
1187 let DecoderMethod = "DecodeT2Adr";
1190 let neverHasSideEffects = 1, isReMaterializable = 1 in
1191 def t2LEApcrel : t2PseudoInst<(outs rGPR:$Rd), (ins i32imm:$label, pred:$p),
1193 def t2LEApcrelJT : t2PseudoInst<(outs rGPR:$Rd),
1194 (ins i32imm:$label, nohash_imm:$id, pred:$p),
1199 //===----------------------------------------------------------------------===//
1200 // Load / store Instructions.
1204 let canFoldAsLoad = 1, isReMaterializable = 1 in
1205 defm t2LDR : T2I_ld<0, 0b10, "ldr", IIC_iLoad_i, IIC_iLoad_si, GPR,
1206 UnOpFrag<(load node:$Src)>>;
1208 // Loads with zero extension
1209 defm t2LDRH : T2I_ld<0, 0b01, "ldrh", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
1210 rGPR, UnOpFrag<(zextloadi16 node:$Src)>>;
1211 defm t2LDRB : T2I_ld<0, 0b00, "ldrb", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
1212 rGPR, UnOpFrag<(zextloadi8 node:$Src)>>;
1214 // Loads with sign extension
1215 defm t2LDRSH : T2I_ld<1, 0b01, "ldrsh", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
1216 rGPR, UnOpFrag<(sextloadi16 node:$Src)>>;
1217 defm t2LDRSB : T2I_ld<1, 0b00, "ldrsb", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
1218 rGPR, UnOpFrag<(sextloadi8 node:$Src)>>;
1220 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
1222 def t2LDRDi8 : T2Ii8s4<1, 0, 1, (outs rGPR:$Rt, rGPR:$Rt2),
1223 (ins t2addrmode_imm8s4:$addr),
1224 IIC_iLoad_d_i, "ldrd", "\t$Rt, $Rt2, $addr", "", []>;
1225 } // mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1
1227 // zextload i1 -> zextload i8
1228 def : T2Pat<(zextloadi1 t2addrmode_imm12:$addr),
1229 (t2LDRBi12 t2addrmode_imm12:$addr)>;
1230 def : T2Pat<(zextloadi1 t2addrmode_negimm8:$addr),
1231 (t2LDRBi8 t2addrmode_negimm8:$addr)>;
1232 def : T2Pat<(zextloadi1 t2addrmode_so_reg:$addr),
1233 (t2LDRBs t2addrmode_so_reg:$addr)>;
1234 def : T2Pat<(zextloadi1 (ARMWrapper tconstpool:$addr)),
1235 (t2LDRBpci tconstpool:$addr)>;
1237 // extload -> zextload
1238 // FIXME: Reduce the number of patterns by legalizing extload to zextload
1240 def : T2Pat<(extloadi1 t2addrmode_imm12:$addr),
1241 (t2LDRBi12 t2addrmode_imm12:$addr)>;
1242 def : T2Pat<(extloadi1 t2addrmode_negimm8:$addr),
1243 (t2LDRBi8 t2addrmode_negimm8:$addr)>;
1244 def : T2Pat<(extloadi1 t2addrmode_so_reg:$addr),
1245 (t2LDRBs t2addrmode_so_reg:$addr)>;
1246 def : T2Pat<(extloadi1 (ARMWrapper tconstpool:$addr)),
1247 (t2LDRBpci tconstpool:$addr)>;
1249 def : T2Pat<(extloadi8 t2addrmode_imm12:$addr),
1250 (t2LDRBi12 t2addrmode_imm12:$addr)>;
1251 def : T2Pat<(extloadi8 t2addrmode_negimm8:$addr),
1252 (t2LDRBi8 t2addrmode_negimm8:$addr)>;
1253 def : T2Pat<(extloadi8 t2addrmode_so_reg:$addr),
1254 (t2LDRBs t2addrmode_so_reg:$addr)>;
1255 def : T2Pat<(extloadi8 (ARMWrapper tconstpool:$addr)),
1256 (t2LDRBpci tconstpool:$addr)>;
1258 def : T2Pat<(extloadi16 t2addrmode_imm12:$addr),
1259 (t2LDRHi12 t2addrmode_imm12:$addr)>;
1260 def : T2Pat<(extloadi16 t2addrmode_negimm8:$addr),
1261 (t2LDRHi8 t2addrmode_negimm8:$addr)>;
1262 def : T2Pat<(extloadi16 t2addrmode_so_reg:$addr),
1263 (t2LDRHs t2addrmode_so_reg:$addr)>;
1264 def : T2Pat<(extloadi16 (ARMWrapper tconstpool:$addr)),
1265 (t2LDRHpci tconstpool:$addr)>;
1267 // FIXME: The destination register of the loads and stores can't be PC, but
1268 // can be SP. We need another regclass (similar to rGPR) to represent
1269 // that. Not a pressing issue since these are selected manually,
1274 let mayLoad = 1, neverHasSideEffects = 1 in {
1275 def t2LDR_PRE : T2Ipreldst<0, 0b10, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1276 (ins t2addrmode_imm8:$addr),
1277 AddrModeT2_i8, IndexModePre, IIC_iLoad_iu,
1278 "ldr", "\t$Rt, $addr!", "$addr.base = $Rn_wb",
1280 let AsmMatchConverter = "cvtLdWriteBackRegT2AddrModeImm8";
1283 def t2LDR_POST : T2Ipostldst<0, 0b10, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1284 (ins addr_offset_none:$Rn, t2am_imm8_offset:$offset),
1285 AddrModeT2_i8, IndexModePost, IIC_iLoad_iu,
1286 "ldr", "\t$Rt, $Rn$offset", "$Rn = $Rn_wb", []>;
1288 def t2LDRB_PRE : T2Ipreldst<0, 0b00, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1289 (ins t2addrmode_imm8:$addr),
1290 AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
1291 "ldrb", "\t$Rt, $addr!", "$addr.base = $Rn_wb",
1293 let AsmMatchConverter = "cvtLdWriteBackRegT2AddrModeImm8";
1295 def t2LDRB_POST : T2Ipostldst<0, 0b00, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1296 (ins addr_offset_none:$Rn, t2am_imm8_offset:$offset),
1297 AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
1298 "ldrb", "\t$Rt, $Rn$offset", "$Rn = $Rn_wb", []>;
1300 def t2LDRH_PRE : T2Ipreldst<0, 0b01, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1301 (ins t2addrmode_imm8:$addr),
1302 AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
1303 "ldrh", "\t$Rt, $addr!", "$addr.base = $Rn_wb",
1305 let AsmMatchConverter = "cvtLdWriteBackRegT2AddrModeImm8";
1307 def t2LDRH_POST : T2Ipostldst<0, 0b01, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1308 (ins addr_offset_none:$Rn, t2am_imm8_offset:$offset),
1309 AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
1310 "ldrh", "\t$Rt, $Rn$offset", "$Rn = $Rn_wb", []>;
1312 def t2LDRSB_PRE : T2Ipreldst<1, 0b00, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1313 (ins t2addrmode_imm8:$addr),
1314 AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
1315 "ldrsb", "\t$Rt, $addr!", "$addr.base = $Rn_wb",
1317 let AsmMatchConverter = "cvtLdWriteBackRegT2AddrModeImm8";
1319 def t2LDRSB_POST : T2Ipostldst<1, 0b00, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1320 (ins addr_offset_none:$Rn, t2am_imm8_offset:$offset),
1321 AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
1322 "ldrsb", "\t$Rt, $Rn$offset", "$Rn = $Rn_wb", []>;
1324 def t2LDRSH_PRE : T2Ipreldst<1, 0b01, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1325 (ins t2addrmode_imm8:$addr),
1326 AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
1327 "ldrsh", "\t$Rt, $addr!", "$addr.base = $Rn_wb",
1329 let AsmMatchConverter = "cvtLdWriteBackRegT2AddrModeImm8";
1331 def t2LDRSH_POST : T2Ipostldst<1, 0b01, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1332 (ins addr_offset_none:$Rn, t2am_imm8_offset:$offset),
1333 AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
1334 "ldrsh", "\t$Rt, $Rn$offset", "$Rn = $Rn_wb", []>;
1335 } // mayLoad = 1, neverHasSideEffects = 1
1337 // LDRT, LDRBT, LDRHT, LDRSBT, LDRSHT all have offset mode (PUW=0b110).
1338 // Ref: A8.6.57 LDR (immediate, Thumb) Encoding T4
1339 class T2IldT<bit signed, bits<2> type, string opc, InstrItinClass ii>
1340 : T2Ii8<(outs rGPR:$Rt), (ins t2addrmode_posimm8:$addr), ii, opc,
1341 "\t$Rt, $addr", []> {
1344 let Inst{31-27} = 0b11111;
1345 let Inst{26-25} = 0b00;
1346 let Inst{24} = signed;
1348 let Inst{22-21} = type;
1349 let Inst{20} = 1; // load
1350 let Inst{19-16} = addr{12-9};
1351 let Inst{15-12} = Rt;
1353 let Inst{10-8} = 0b110; // PUW.
1354 let Inst{7-0} = addr{7-0};
1357 def t2LDRT : T2IldT<0, 0b10, "ldrt", IIC_iLoad_i>;
1358 def t2LDRBT : T2IldT<0, 0b00, "ldrbt", IIC_iLoad_bh_i>;
1359 def t2LDRHT : T2IldT<0, 0b01, "ldrht", IIC_iLoad_bh_i>;
1360 def t2LDRSBT : T2IldT<1, 0b00, "ldrsbt", IIC_iLoad_bh_i>;
1361 def t2LDRSHT : T2IldT<1, 0b01, "ldrsht", IIC_iLoad_bh_i>;
1364 defm t2STR :T2I_st<0b10,"str", IIC_iStore_i, IIC_iStore_si, GPR,
1365 BinOpFrag<(store node:$LHS, node:$RHS)>>;
1366 defm t2STRB:T2I_st<0b00,"strb", IIC_iStore_bh_i, IIC_iStore_bh_si,
1367 rGPR, BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
1368 defm t2STRH:T2I_st<0b01,"strh", IIC_iStore_bh_i, IIC_iStore_bh_si,
1369 rGPR, BinOpFrag<(truncstorei16 node:$LHS, node:$RHS)>>;
1372 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in
1373 def t2STRDi8 : T2Ii8s4<1, 0, 0, (outs),
1374 (ins GPR:$Rt, GPR:$Rt2, t2addrmode_imm8s4:$addr),
1375 IIC_iStore_d_r, "strd", "\t$Rt, $Rt2, $addr", "", []>;
1379 let mayStore = 1, neverHasSideEffects = 1 in {
1380 def t2STR_PRE : T2Ipreldst<0, 0b10, 0, 1, (outs GPRnopc:$Rn_wb),
1381 (ins GPRnopc:$Rt, t2addrmode_imm8:$addr),
1382 AddrModeT2_i8, IndexModePre, IIC_iStore_iu,
1383 "str", "\t$Rt, $addr!",
1384 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> {
1385 let AsmMatchConverter = "cvtStWriteBackRegT2AddrModeImm8";
1387 def t2STRH_PRE : T2Ipreldst<0, 0b01, 0, 1, (outs GPRnopc:$Rn_wb),
1388 (ins rGPR:$Rt, t2addrmode_imm8:$addr),
1389 AddrModeT2_i8, IndexModePre, IIC_iStore_iu,
1390 "strh", "\t$Rt, $addr!",
1391 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> {
1392 let AsmMatchConverter = "cvtStWriteBackRegT2AddrModeImm8";
1395 def t2STRB_PRE : T2Ipreldst<0, 0b00, 0, 1, (outs GPRnopc:$Rn_wb),
1396 (ins rGPR:$Rt, t2addrmode_imm8:$addr),
1397 AddrModeT2_i8, IndexModePre, IIC_iStore_bh_iu,
1398 "strb", "\t$Rt, $addr!",
1399 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> {
1400 let AsmMatchConverter = "cvtStWriteBackRegT2AddrModeImm8";
1402 } // mayStore = 1, neverHasSideEffects = 1
1404 def t2STR_POST : T2Ipostldst<0, 0b10, 0, 0, (outs GPRnopc:$Rn_wb),
1405 (ins GPRnopc:$Rt, addr_offset_none:$Rn,
1406 t2am_imm8_offset:$offset),
1407 AddrModeT2_i8, IndexModePost, IIC_iStore_iu,
1408 "str", "\t$Rt, $Rn$offset",
1409 "$Rn = $Rn_wb,@earlyclobber $Rn_wb",
1410 [(set GPRnopc:$Rn_wb,
1411 (post_store GPRnopc:$Rt, addr_offset_none:$Rn,
1412 t2am_imm8_offset:$offset))]>;
1414 def t2STRH_POST : T2Ipostldst<0, 0b01, 0, 0, (outs GPRnopc:$Rn_wb),
1415 (ins rGPR:$Rt, addr_offset_none:$Rn,
1416 t2am_imm8_offset:$offset),
1417 AddrModeT2_i8, IndexModePost, IIC_iStore_bh_iu,
1418 "strh", "\t$Rt, $Rn$offset",
1419 "$Rn = $Rn_wb,@earlyclobber $Rn_wb",
1420 [(set GPRnopc:$Rn_wb,
1421 (post_truncsti16 rGPR:$Rt, addr_offset_none:$Rn,
1422 t2am_imm8_offset:$offset))]>;
1424 def t2STRB_POST : T2Ipostldst<0, 0b00, 0, 0, (outs GPRnopc:$Rn_wb),
1425 (ins rGPR:$Rt, addr_offset_none:$Rn,
1426 t2am_imm8_offset:$offset),
1427 AddrModeT2_i8, IndexModePost, IIC_iStore_bh_iu,
1428 "strb", "\t$Rt, $Rn$offset",
1429 "$Rn = $Rn_wb,@earlyclobber $Rn_wb",
1430 [(set GPRnopc:$Rn_wb,
1431 (post_truncsti8 rGPR:$Rt, addr_offset_none:$Rn,
1432 t2am_imm8_offset:$offset))]>;
1434 // Pseudo-instructions for pattern matching the pre-indexed stores. We can't
1435 // put the patterns on the instruction definitions directly as ISel wants
1436 // the address base and offset to be separate operands, not a single
1437 // complex operand like we represent the instructions themselves. The
1438 // pseudos map between the two.
1439 let usesCustomInserter = 1,
1440 Constraints = "$Rn = $Rn_wb,@earlyclobber $Rn_wb" in {
1441 def t2STR_preidx: t2PseudoInst<(outs GPRnopc:$Rn_wb),
1442 (ins rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$offset, pred:$p),
1444 [(set GPRnopc:$Rn_wb,
1445 (pre_store rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$offset))]>;
1446 def t2STRB_preidx: t2PseudoInst<(outs GPRnopc:$Rn_wb),
1447 (ins rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$offset, pred:$p),
1449 [(set GPRnopc:$Rn_wb,
1450 (pre_truncsti8 rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$offset))]>;
1451 def t2STRH_preidx: t2PseudoInst<(outs GPRnopc:$Rn_wb),
1452 (ins rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$offset, pred:$p),
1454 [(set GPRnopc:$Rn_wb,
1455 (pre_truncsti16 rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$offset))]>;
1458 // STRT, STRBT, STRHT all have offset mode (PUW=0b110) and are for disassembly
1460 // Ref: A8.6.193 STR (immediate, Thumb) Encoding T4
1461 class T2IstT<bits<2> type, string opc, InstrItinClass ii>
1462 : T2Ii8<(outs rGPR:$Rt), (ins t2addrmode_imm8:$addr), ii, opc,
1463 "\t$Rt, $addr", []> {
1464 let Inst{31-27} = 0b11111;
1465 let Inst{26-25} = 0b00;
1466 let Inst{24} = 0; // not signed
1468 let Inst{22-21} = type;
1469 let Inst{20} = 0; // store
1471 let Inst{10-8} = 0b110; // PUW
1475 let Inst{15-12} = Rt;
1476 let Inst{19-16} = addr{12-9};
1477 let Inst{7-0} = addr{7-0};
1480 def t2STRT : T2IstT<0b10, "strt", IIC_iStore_i>;
1481 def t2STRBT : T2IstT<0b00, "strbt", IIC_iStore_bh_i>;
1482 def t2STRHT : T2IstT<0b01, "strht", IIC_iStore_bh_i>;
1484 // ldrd / strd pre / post variants
1485 // For disassembly only.
1487 def t2LDRD_PRE : T2Ii8s4<1, 1, 1, (outs rGPR:$Rt, rGPR:$Rt2, GPR:$wb),
1488 (ins t2addrmode_imm8s4:$addr), IIC_iLoad_d_ru,
1489 "ldrd", "\t$Rt, $Rt2, $addr!", "$addr.base = $wb", []> {
1490 let AsmMatchConverter = "cvtT2LdrdPre";
1491 let DecoderMethod = "DecodeT2LDRDPreInstruction";
1494 def t2LDRD_POST : T2Ii8s4post<0, 1, 1, (outs rGPR:$Rt, rGPR:$Rt2, GPR:$wb),
1495 (ins addr_offset_none:$addr, t2am_imm8s4_offset:$imm),
1496 IIC_iLoad_d_ru, "ldrd", "\t$Rt, $Rt2, $addr$imm",
1497 "$addr.base = $wb", []>;
1499 def t2STRD_PRE : T2Ii8s4<1, 1, 0, (outs GPR:$wb),
1500 (ins rGPR:$Rt, rGPR:$Rt2, t2addrmode_imm8s4:$addr),
1501 IIC_iStore_d_ru, "strd", "\t$Rt, $Rt2, $addr!",
1502 "$addr.base = $wb", []> {
1503 let AsmMatchConverter = "cvtT2StrdPre";
1504 let DecoderMethod = "DecodeT2STRDPreInstruction";
1507 def t2STRD_POST : T2Ii8s4post<0, 1, 0, (outs GPR:$wb),
1508 (ins rGPR:$Rt, rGPR:$Rt2, addr_offset_none:$addr,
1509 t2am_imm8s4_offset:$imm),
1510 IIC_iStore_d_ru, "strd", "\t$Rt, $Rt2, $addr$imm",
1511 "$addr.base = $wb", []>;
1513 // T2Ipl (Preload Data/Instruction) signals the memory system of possible future
1514 // data/instruction access.
1515 // instr_write is inverted for Thumb mode: (prefetch 3) -> (preload 0),
1516 // (prefetch 1) -> (preload 2), (prefetch 2) -> (preload 1).
1517 multiclass T2Ipl<bits<1> write, bits<1> instr, string opc> {
1519 def i12 : T2Ii12<(outs), (ins t2addrmode_imm12:$addr), IIC_Preload, opc,
1521 [(ARMPreload t2addrmode_imm12:$addr, (i32 write), (i32 instr))]> {
1522 let Inst{31-25} = 0b1111100;
1523 let Inst{24} = instr;
1525 let Inst{21} = write;
1527 let Inst{15-12} = 0b1111;
1530 let addr{12} = 1; // add = TRUE
1531 let Inst{19-16} = addr{16-13}; // Rn
1532 let Inst{23} = addr{12}; // U
1533 let Inst{11-0} = addr{11-0}; // imm12
1536 def i8 : T2Ii8<(outs), (ins t2addrmode_negimm8:$addr), IIC_Preload, opc,
1538 [(ARMPreload t2addrmode_negimm8:$addr, (i32 write), (i32 instr))]> {
1539 let Inst{31-25} = 0b1111100;
1540 let Inst{24} = instr;
1541 let Inst{23} = 0; // U = 0
1543 let Inst{21} = write;
1545 let Inst{15-12} = 0b1111;
1546 let Inst{11-8} = 0b1100;
1549 let Inst{19-16} = addr{12-9}; // Rn
1550 let Inst{7-0} = addr{7-0}; // imm8
1553 def s : T2Iso<(outs), (ins t2addrmode_so_reg:$addr), IIC_Preload, opc,
1555 [(ARMPreload t2addrmode_so_reg:$addr, (i32 write), (i32 instr))]> {
1556 let Inst{31-25} = 0b1111100;
1557 let Inst{24} = instr;
1558 let Inst{23} = 0; // add = TRUE for T1
1560 let Inst{21} = write;
1562 let Inst{15-12} = 0b1111;
1563 let Inst{11-6} = 0000000;
1566 let Inst{19-16} = addr{9-6}; // Rn
1567 let Inst{3-0} = addr{5-2}; // Rm
1568 let Inst{5-4} = addr{1-0}; // imm2
1570 let DecoderMethod = "DecodeT2LoadShift";
1572 // FIXME: We should have a separate 'pci' variant here. As-is we represent
1573 // it via the i12 variant, which it's related to, but that means we can
1574 // represent negative immediates, which aren't legal for anything except
1575 // the 'pci' case (Rn == 15).
1578 defm t2PLD : T2Ipl<0, 0, "pld">, Requires<[IsThumb2]>;
1579 defm t2PLDW : T2Ipl<1, 0, "pldw">, Requires<[IsThumb2,HasV7,HasMP]>;
1580 defm t2PLI : T2Ipl<0, 1, "pli">, Requires<[IsThumb2,HasV7]>;
1582 //===----------------------------------------------------------------------===//
1583 // Load / store multiple Instructions.
1586 multiclass thumb2_ld_mult<string asm, InstrItinClass itin,
1587 InstrItinClass itin_upd, bit L_bit> {
1589 T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1590 itin, !strconcat(asm, "${p}.w\t$Rn, $regs"), []> {
1594 let Inst{31-27} = 0b11101;
1595 let Inst{26-25} = 0b00;
1596 let Inst{24-23} = 0b01; // Increment After
1598 let Inst{21} = 0; // No writeback
1599 let Inst{20} = L_bit;
1600 let Inst{19-16} = Rn;
1601 let Inst{15-0} = regs;
1604 T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1605 itin_upd, !strconcat(asm, "${p}.w\t$Rn!, $regs"), "$Rn = $wb", []> {
1609 let Inst{31-27} = 0b11101;
1610 let Inst{26-25} = 0b00;
1611 let Inst{24-23} = 0b01; // Increment After
1613 let Inst{21} = 1; // Writeback
1614 let Inst{20} = L_bit;
1615 let Inst{19-16} = Rn;
1616 let Inst{15-0} = regs;
1619 T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1620 itin, !strconcat(asm, "db${p}\t$Rn, $regs"), []> {
1624 let Inst{31-27} = 0b11101;
1625 let Inst{26-25} = 0b00;
1626 let Inst{24-23} = 0b10; // Decrement Before
1628 let Inst{21} = 0; // No writeback
1629 let Inst{20} = L_bit;
1630 let Inst{19-16} = Rn;
1631 let Inst{15-0} = regs;
1634 T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1635 itin_upd, !strconcat(asm, "db${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
1639 let Inst{31-27} = 0b11101;
1640 let Inst{26-25} = 0b00;
1641 let Inst{24-23} = 0b10; // Decrement Before
1643 let Inst{21} = 1; // Writeback
1644 let Inst{20} = L_bit;
1645 let Inst{19-16} = Rn;
1646 let Inst{15-0} = regs;
1650 let neverHasSideEffects = 1 in {
1652 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
1653 defm t2LDM : thumb2_ld_mult<"ldm", IIC_iLoad_m, IIC_iLoad_mu, 1>;
1655 multiclass thumb2_st_mult<string asm, InstrItinClass itin,
1656 InstrItinClass itin_upd, bit L_bit> {
1658 T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1659 itin, !strconcat(asm, "${p}.w\t$Rn, $regs"), []> {
1663 let Inst{31-27} = 0b11101;
1664 let Inst{26-25} = 0b00;
1665 let Inst{24-23} = 0b01; // Increment After
1667 let Inst{21} = 0; // No writeback
1668 let Inst{20} = L_bit;
1669 let Inst{19-16} = Rn;
1671 let Inst{14} = regs{14};
1673 let Inst{12-0} = regs{12-0};
1676 T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1677 itin_upd, !strconcat(asm, "${p}.w\t$Rn!, $regs"), "$Rn = $wb", []> {
1681 let Inst{31-27} = 0b11101;
1682 let Inst{26-25} = 0b00;
1683 let Inst{24-23} = 0b01; // Increment After
1685 let Inst{21} = 1; // Writeback
1686 let Inst{20} = L_bit;
1687 let Inst{19-16} = Rn;
1689 let Inst{14} = regs{14};
1691 let Inst{12-0} = regs{12-0};
1694 T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1695 itin, !strconcat(asm, "db${p}\t$Rn, $regs"), []> {
1699 let Inst{31-27} = 0b11101;
1700 let Inst{26-25} = 0b00;
1701 let Inst{24-23} = 0b10; // Decrement Before
1703 let Inst{21} = 0; // No writeback
1704 let Inst{20} = L_bit;
1705 let Inst{19-16} = Rn;
1707 let Inst{14} = regs{14};
1709 let Inst{12-0} = regs{12-0};
1712 T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1713 itin_upd, !strconcat(asm, "db${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
1717 let Inst{31-27} = 0b11101;
1718 let Inst{26-25} = 0b00;
1719 let Inst{24-23} = 0b10; // Decrement Before
1721 let Inst{21} = 1; // Writeback
1722 let Inst{20} = L_bit;
1723 let Inst{19-16} = Rn;
1725 let Inst{14} = regs{14};
1727 let Inst{12-0} = regs{12-0};
1732 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
1733 defm t2STM : thumb2_st_mult<"stm", IIC_iStore_m, IIC_iStore_mu, 0>;
1735 } // neverHasSideEffects
1738 //===----------------------------------------------------------------------===//
1739 // Move Instructions.
1742 let neverHasSideEffects = 1 in
1743 def t2MOVr : T2sTwoReg<(outs GPRnopc:$Rd), (ins GPR:$Rm), IIC_iMOVr,
1744 "mov", ".w\t$Rd, $Rm", []> {
1745 let Inst{31-27} = 0b11101;
1746 let Inst{26-25} = 0b01;
1747 let Inst{24-21} = 0b0010;
1748 let Inst{19-16} = 0b1111; // Rn
1749 let Inst{14-12} = 0b000;
1750 let Inst{7-4} = 0b0000;
1752 def : t2InstAlias<"mov${p}.w $Rd, $Rm", (t2MOVr GPRnopc:$Rd, GPR:$Rm,
1753 pred:$p, zero_reg)>;
1754 def : t2InstAlias<"movs${p}.w $Rd, $Rm", (t2MOVr GPRnopc:$Rd, GPR:$Rm,
1756 def : t2InstAlias<"movs${p} $Rd, $Rm", (t2MOVr GPRnopc:$Rd, GPR:$Rm,
1759 // AddedComplexity to ensure isel tries t2MOVi before t2MOVi16.
1760 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1,
1761 AddedComplexity = 1 in
1762 def t2MOVi : T2sOneRegImm<(outs rGPR:$Rd), (ins t2_so_imm:$imm), IIC_iMOVi,
1763 "mov", ".w\t$Rd, $imm",
1764 [(set rGPR:$Rd, t2_so_imm:$imm)]> {
1765 let Inst{31-27} = 0b11110;
1767 let Inst{24-21} = 0b0010;
1768 let Inst{19-16} = 0b1111; // Rn
1772 // cc_out is handled as part of the explicit mnemonic in the parser for 'mov'.
1773 // Use aliases to get that to play nice here.
1774 def : t2InstAlias<"movs${p}.w $Rd, $imm", (t2MOVi rGPR:$Rd, t2_so_imm:$imm,
1776 def : t2InstAlias<"movs${p} $Rd, $imm", (t2MOVi rGPR:$Rd, t2_so_imm:$imm,
1779 def : t2InstAlias<"mov${p}.w $Rd, $imm", (t2MOVi rGPR:$Rd, t2_so_imm:$imm,
1780 pred:$p, zero_reg)>;
1781 def : t2InstAlias<"mov${p} $Rd, $imm", (t2MOVi rGPR:$Rd, t2_so_imm:$imm,
1782 pred:$p, zero_reg)>;
1784 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
1785 def t2MOVi16 : T2I<(outs rGPR:$Rd), (ins imm0_65535_expr:$imm), IIC_iMOVi,
1786 "movw", "\t$Rd, $imm",
1787 [(set rGPR:$Rd, imm0_65535:$imm)]> {
1788 let Inst{31-27} = 0b11110;
1790 let Inst{24-21} = 0b0010;
1791 let Inst{20} = 0; // The S bit.
1797 let Inst{11-8} = Rd;
1798 let Inst{19-16} = imm{15-12};
1799 let Inst{26} = imm{11};
1800 let Inst{14-12} = imm{10-8};
1801 let Inst{7-0} = imm{7-0};
1802 let DecoderMethod = "DecodeT2MOVTWInstruction";
1805 def t2MOVi16_ga_pcrel : PseudoInst<(outs rGPR:$Rd),
1806 (ins i32imm:$addr, pclabel:$id), IIC_iMOVi, []>;
1808 let Constraints = "$src = $Rd" in {
1809 def t2MOVTi16 : T2I<(outs rGPR:$Rd),
1810 (ins rGPR:$src, imm0_65535_expr:$imm), IIC_iMOVi,
1811 "movt", "\t$Rd, $imm",
1813 (or (and rGPR:$src, 0xffff), lo16AllZero:$imm))]> {
1814 let Inst{31-27} = 0b11110;
1816 let Inst{24-21} = 0b0110;
1817 let Inst{20} = 0; // The S bit.
1823 let Inst{11-8} = Rd;
1824 let Inst{19-16} = imm{15-12};
1825 let Inst{26} = imm{11};
1826 let Inst{14-12} = imm{10-8};
1827 let Inst{7-0} = imm{7-0};
1828 let DecoderMethod = "DecodeT2MOVTWInstruction";
1831 def t2MOVTi16_ga_pcrel : PseudoInst<(outs rGPR:$Rd),
1832 (ins rGPR:$src, i32imm:$addr, pclabel:$id), IIC_iMOVi, []>;
1835 def : T2Pat<(or rGPR:$src, 0xffff0000), (t2MOVTi16 rGPR:$src, 0xffff)>;
1837 //===----------------------------------------------------------------------===//
1838 // Extend Instructions.
1843 def t2SXTB : T2I_ext_rrot<0b100, "sxtb",
1844 UnOpFrag<(sext_inreg node:$Src, i8)>>;
1845 def t2SXTH : T2I_ext_rrot<0b000, "sxth",
1846 UnOpFrag<(sext_inreg node:$Src, i16)>>;
1847 def t2SXTB16 : T2I_ext_rrot_sxtb16<0b010, "sxtb16">;
1849 def t2SXTAB : T2I_exta_rrot<0b100, "sxtab",
1850 BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
1851 def t2SXTAH : T2I_exta_rrot<0b000, "sxtah",
1852 BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
1853 def t2SXTAB16 : T2I_exta_rrot_np<0b010, "sxtab16">;
1857 let AddedComplexity = 16 in {
1858 def t2UXTB : T2I_ext_rrot<0b101, "uxtb",
1859 UnOpFrag<(and node:$Src, 0x000000FF)>>;
1860 def t2UXTH : T2I_ext_rrot<0b001, "uxth",
1861 UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
1862 def t2UXTB16 : T2I_ext_rrot_uxtb16<0b011, "uxtb16",
1863 UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
1865 // FIXME: This pattern incorrectly assumes the shl operator is a rotate.
1866 // The transformation should probably be done as a combiner action
1867 // instead so we can include a check for masking back in the upper
1868 // eight bits of the source into the lower eight bits of the result.
1869 //def : T2Pat<(and (shl rGPR:$Src, (i32 8)), 0xFF00FF),
1870 // (t2UXTB16 rGPR:$Src, 3)>,
1871 // Requires<[HasT2ExtractPack, IsThumb2]>;
1872 def : T2Pat<(and (srl rGPR:$Src, (i32 8)), 0xFF00FF),
1873 (t2UXTB16 rGPR:$Src, 1)>,
1874 Requires<[HasT2ExtractPack, IsThumb2]>;
1876 def t2UXTAB : T2I_exta_rrot<0b101, "uxtab",
1877 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
1878 def t2UXTAH : T2I_exta_rrot<0b001, "uxtah",
1879 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
1880 def t2UXTAB16 : T2I_exta_rrot_np<0b011, "uxtab16">;
1883 //===----------------------------------------------------------------------===//
1884 // Arithmetic Instructions.
1887 defm t2ADD : T2I_bin_ii12rs<0b000, "add",
1888 BinOpFrag<(add node:$LHS, node:$RHS)>, 1>;
1889 defm t2SUB : T2I_bin_ii12rs<0b101, "sub",
1890 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
1892 // ADD and SUB with 's' bit set. No 12-bit immediate (T4) variants.
1894 // Currently, t2ADDS/t2SUBS are pseudo opcodes that exist only in the
1895 // selection DAG. They are "lowered" to real t2ADD/t2SUB opcodes by
1896 // AdjustInstrPostInstrSelection where we determine whether or not to
1897 // set the "s" bit based on CPSR liveness.
1899 // FIXME: Eliminate t2ADDS/t2SUBS pseudo opcodes after adding tablegen
1900 // support for an optional CPSR definition that corresponds to the DAG
1901 // node's second value. We can then eliminate the implicit def of CPSR.
1902 defm t2ADDS : T2I_bin_s_irs <IIC_iALUi, IIC_iALUr, IIC_iALUsi,
1903 BinOpFrag<(ARMaddc node:$LHS, node:$RHS)>, 1>;
1904 defm t2SUBS : T2I_bin_s_irs <IIC_iALUi, IIC_iALUr, IIC_iALUsi,
1905 BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>;
1907 let hasPostISelHook = 1 in {
1908 defm t2ADC : T2I_adde_sube_irs<0b1010, "adc",
1909 BinOpWithFlagFrag<(ARMadde node:$LHS, node:$RHS, node:$FLAG)>, 1>;
1910 defm t2SBC : T2I_adde_sube_irs<0b1011, "sbc",
1911 BinOpWithFlagFrag<(ARMsube node:$LHS, node:$RHS, node:$FLAG)>>;
1915 defm t2RSB : T2I_rbin_irs <0b1110, "rsb",
1916 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
1918 // FIXME: Eliminate them if we can write def : Pat patterns which defines
1919 // CPSR and the implicit def of CPSR is not needed.
1920 defm t2RSBS : T2I_rbin_s_is <BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>;
1922 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
1923 // The assume-no-carry-in form uses the negation of the input since add/sub
1924 // assume opposite meanings of the carry flag (i.e., carry == !borrow).
1925 // See the definition of AddWithCarry() in the ARM ARM A2.2.1 for the gory
1927 // The AddedComplexity preferences the first variant over the others since
1928 // it can be shrunk to a 16-bit wide encoding, while the others cannot.
1929 let AddedComplexity = 1 in
1930 def : T2Pat<(add GPR:$src, imm0_255_neg:$imm),
1931 (t2SUBri GPR:$src, imm0_255_neg:$imm)>;
1932 def : T2Pat<(add GPR:$src, t2_so_imm_neg:$imm),
1933 (t2SUBri GPR:$src, t2_so_imm_neg:$imm)>;
1934 def : T2Pat<(add GPR:$src, imm0_4095_neg:$imm),
1935 (t2SUBri12 GPR:$src, imm0_4095_neg:$imm)>;
1936 def : T2Pat<(add GPR:$src, imm0_65535_neg:$imm),
1937 (t2SUBrr GPR:$src, (t2MOVi16 (imm_neg_XFORM imm:$imm)))>;
1939 let AddedComplexity = 1 in
1940 def : T2Pat<(ARMaddc rGPR:$src, imm0_255_neg:$imm),
1941 (t2SUBSri rGPR:$src, imm0_255_neg:$imm)>;
1942 def : T2Pat<(ARMaddc rGPR:$src, t2_so_imm_neg:$imm),
1943 (t2SUBSri rGPR:$src, t2_so_imm_neg:$imm)>;
1944 def : T2Pat<(ARMaddc rGPR:$src, imm0_65535_neg:$imm),
1945 (t2SUBSrr rGPR:$src, (t2MOVi16 (imm_neg_XFORM imm:$imm)))>;
1946 // The with-carry-in form matches bitwise not instead of the negation.
1947 // Effectively, the inverse interpretation of the carry flag already accounts
1948 // for part of the negation.
1949 let AddedComplexity = 1 in
1950 def : T2Pat<(ARMadde rGPR:$src, imm0_255_not:$imm, CPSR),
1951 (t2SBCri rGPR:$src, imm0_255_not:$imm)>;
1952 def : T2Pat<(ARMadde rGPR:$src, t2_so_imm_not:$imm, CPSR),
1953 (t2SBCri rGPR:$src, t2_so_imm_not:$imm)>;
1954 def : T2Pat<(ARMadde rGPR:$src, imm0_65535_neg:$imm, CPSR),
1955 (t2SBCrr rGPR:$src, (t2MOVi16 (imm_neg_XFORM imm:$imm)))>;
1957 // Select Bytes -- for disassembly only
1959 def t2SEL : T2ThreeReg<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
1960 NoItinerary, "sel", "\t$Rd, $Rn, $Rm", []>,
1961 Requires<[IsThumb2, HasThumb2DSP]> {
1962 let Inst{31-27} = 0b11111;
1963 let Inst{26-24} = 0b010;
1965 let Inst{22-20} = 0b010;
1966 let Inst{15-12} = 0b1111;
1968 let Inst{6-4} = 0b000;
1971 // A6.3.13, A6.3.14, A6.3.15 Parallel addition and subtraction (signed/unsigned)
1972 // And Miscellaneous operations -- for disassembly only
1973 class T2I_pam<bits<3> op22_20, bits<4> op7_4, string opc,
1974 list<dag> pat = [/* For disassembly only; pattern left blank */],
1975 dag iops = (ins rGPR:$Rn, rGPR:$Rm),
1976 string asm = "\t$Rd, $Rn, $Rm">
1977 : T2I<(outs rGPR:$Rd), iops, NoItinerary, opc, asm, pat>,
1978 Requires<[IsThumb2, HasThumb2DSP]> {
1979 let Inst{31-27} = 0b11111;
1980 let Inst{26-23} = 0b0101;
1981 let Inst{22-20} = op22_20;
1982 let Inst{15-12} = 0b1111;
1983 let Inst{7-4} = op7_4;
1989 let Inst{11-8} = Rd;
1990 let Inst{19-16} = Rn;
1994 // Saturating add/subtract -- for disassembly only
1996 def t2QADD : T2I_pam<0b000, 0b1000, "qadd",
1997 [(set rGPR:$Rd, (int_arm_qadd rGPR:$Rn, rGPR:$Rm))],
1998 (ins rGPR:$Rm, rGPR:$Rn), "\t$Rd, $Rm, $Rn">;
1999 def t2QADD16 : T2I_pam<0b001, 0b0001, "qadd16">;
2000 def t2QADD8 : T2I_pam<0b000, 0b0001, "qadd8">;
2001 def t2QASX : T2I_pam<0b010, 0b0001, "qasx">;
2002 def t2QDADD : T2I_pam<0b000, 0b1001, "qdadd", [],
2003 (ins rGPR:$Rm, rGPR:$Rn), "\t$Rd, $Rm, $Rn">;
2004 def t2QDSUB : T2I_pam<0b000, 0b1011, "qdsub", [],
2005 (ins rGPR:$Rm, rGPR:$Rn), "\t$Rd, $Rm, $Rn">;
2006 def t2QSAX : T2I_pam<0b110, 0b0001, "qsax">;
2007 def t2QSUB : T2I_pam<0b000, 0b1010, "qsub",
2008 [(set rGPR:$Rd, (int_arm_qsub rGPR:$Rn, rGPR:$Rm))],
2009 (ins rGPR:$Rm, rGPR:$Rn), "\t$Rd, $Rm, $Rn">;
2010 def t2QSUB16 : T2I_pam<0b101, 0b0001, "qsub16">;
2011 def t2QSUB8 : T2I_pam<0b100, 0b0001, "qsub8">;
2012 def t2UQADD16 : T2I_pam<0b001, 0b0101, "uqadd16">;
2013 def t2UQADD8 : T2I_pam<0b000, 0b0101, "uqadd8">;
2014 def t2UQASX : T2I_pam<0b010, 0b0101, "uqasx">;
2015 def t2UQSAX : T2I_pam<0b110, 0b0101, "uqsax">;
2016 def t2UQSUB16 : T2I_pam<0b101, 0b0101, "uqsub16">;
2017 def t2UQSUB8 : T2I_pam<0b100, 0b0101, "uqsub8">;
2019 // Signed/Unsigned add/subtract -- for disassembly only
2021 def t2SASX : T2I_pam<0b010, 0b0000, "sasx">;
2022 def t2SADD16 : T2I_pam<0b001, 0b0000, "sadd16">;
2023 def t2SADD8 : T2I_pam<0b000, 0b0000, "sadd8">;
2024 def t2SSAX : T2I_pam<0b110, 0b0000, "ssax">;
2025 def t2SSUB16 : T2I_pam<0b101, 0b0000, "ssub16">;
2026 def t2SSUB8 : T2I_pam<0b100, 0b0000, "ssub8">;
2027 def t2UASX : T2I_pam<0b010, 0b0100, "uasx">;
2028 def t2UADD16 : T2I_pam<0b001, 0b0100, "uadd16">;
2029 def t2UADD8 : T2I_pam<0b000, 0b0100, "uadd8">;
2030 def t2USAX : T2I_pam<0b110, 0b0100, "usax">;
2031 def t2USUB16 : T2I_pam<0b101, 0b0100, "usub16">;
2032 def t2USUB8 : T2I_pam<0b100, 0b0100, "usub8">;
2034 // Signed/Unsigned halving add/subtract -- for disassembly only
2036 def t2SHASX : T2I_pam<0b010, 0b0010, "shasx">;
2037 def t2SHADD16 : T2I_pam<0b001, 0b0010, "shadd16">;
2038 def t2SHADD8 : T2I_pam<0b000, 0b0010, "shadd8">;
2039 def t2SHSAX : T2I_pam<0b110, 0b0010, "shsax">;
2040 def t2SHSUB16 : T2I_pam<0b101, 0b0010, "shsub16">;
2041 def t2SHSUB8 : T2I_pam<0b100, 0b0010, "shsub8">;
2042 def t2UHASX : T2I_pam<0b010, 0b0110, "uhasx">;
2043 def t2UHADD16 : T2I_pam<0b001, 0b0110, "uhadd16">;
2044 def t2UHADD8 : T2I_pam<0b000, 0b0110, "uhadd8">;
2045 def t2UHSAX : T2I_pam<0b110, 0b0110, "uhsax">;
2046 def t2UHSUB16 : T2I_pam<0b101, 0b0110, "uhsub16">;
2047 def t2UHSUB8 : T2I_pam<0b100, 0b0110, "uhsub8">;
2049 // Helper class for disassembly only
2050 // A6.3.16 & A6.3.17
2051 // T2Imac - Thumb2 multiply [accumulate, and absolute difference] instructions.
2052 class T2ThreeReg_mac<bit long, bits<3> op22_20, bits<4> op7_4, dag oops,
2053 dag iops, InstrItinClass itin, string opc, string asm, list<dag> pattern>
2054 : T2ThreeReg<oops, iops, itin, opc, asm, pattern> {
2055 let Inst{31-27} = 0b11111;
2056 let Inst{26-24} = 0b011;
2057 let Inst{23} = long;
2058 let Inst{22-20} = op22_20;
2059 let Inst{7-4} = op7_4;
2062 class T2FourReg_mac<bit long, bits<3> op22_20, bits<4> op7_4, dag oops,
2063 dag iops, InstrItinClass itin, string opc, string asm, list<dag> pattern>
2064 : T2FourReg<oops, iops, itin, opc, asm, pattern> {
2065 let Inst{31-27} = 0b11111;
2066 let Inst{26-24} = 0b011;
2067 let Inst{23} = long;
2068 let Inst{22-20} = op22_20;
2069 let Inst{7-4} = op7_4;
2072 // Unsigned Sum of Absolute Differences [and Accumulate].
2073 def t2USAD8 : T2ThreeReg_mac<0, 0b111, 0b0000, (outs rGPR:$Rd),
2074 (ins rGPR:$Rn, rGPR:$Rm),
2075 NoItinerary, "usad8", "\t$Rd, $Rn, $Rm", []>,
2076 Requires<[IsThumb2, HasThumb2DSP]> {
2077 let Inst{15-12} = 0b1111;
2079 def t2USADA8 : T2FourReg_mac<0, 0b111, 0b0000, (outs rGPR:$Rd),
2080 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), NoItinerary,
2081 "usada8", "\t$Rd, $Rn, $Rm, $Ra", []>,
2082 Requires<[IsThumb2, HasThumb2DSP]>;
2084 // Signed/Unsigned saturate.
2085 class T2SatI<dag oops, dag iops, InstrItinClass itin,
2086 string opc, string asm, list<dag> pattern>
2087 : T2I<oops, iops, itin, opc, asm, pattern> {
2093 let Inst{11-8} = Rd;
2094 let Inst{19-16} = Rn;
2095 let Inst{4-0} = sat_imm;
2096 let Inst{21} = sh{5};
2097 let Inst{14-12} = sh{4-2};
2098 let Inst{7-6} = sh{1-0};
2103 (ins imm1_32:$sat_imm, rGPR:$Rn, t2_shift_imm:$sh),
2104 NoItinerary, "ssat", "\t$Rd, $sat_imm, $Rn$sh", []> {
2105 let Inst{31-27} = 0b11110;
2106 let Inst{25-22} = 0b1100;
2112 def t2SSAT16: T2SatI<
2113 (outs rGPR:$Rd), (ins imm1_16:$sat_imm, rGPR:$Rn), NoItinerary,
2114 "ssat16", "\t$Rd, $sat_imm, $Rn", []>,
2115 Requires<[IsThumb2, HasThumb2DSP]> {
2116 let Inst{31-27} = 0b11110;
2117 let Inst{25-22} = 0b1100;
2120 let Inst{21} = 1; // sh = '1'
2121 let Inst{14-12} = 0b000; // imm3 = '000'
2122 let Inst{7-6} = 0b00; // imm2 = '00'
2123 let Inst{5-4} = 0b00;
2128 (ins imm0_31:$sat_imm, rGPR:$Rn, t2_shift_imm:$sh),
2129 NoItinerary, "usat", "\t$Rd, $sat_imm, $Rn$sh", []> {
2130 let Inst{31-27} = 0b11110;
2131 let Inst{25-22} = 0b1110;
2136 def t2USAT16: T2SatI<(outs rGPR:$Rd), (ins imm0_15:$sat_imm, rGPR:$Rn),
2138 "usat16", "\t$Rd, $sat_imm, $Rn", []>,
2139 Requires<[IsThumb2, HasThumb2DSP]> {
2140 let Inst{31-22} = 0b1111001110;
2143 let Inst{21} = 1; // sh = '1'
2144 let Inst{14-12} = 0b000; // imm3 = '000'
2145 let Inst{7-6} = 0b00; // imm2 = '00'
2146 let Inst{5-4} = 0b00;
2149 def : T2Pat<(int_arm_ssat GPR:$a, imm:$pos), (t2SSAT imm:$pos, GPR:$a, 0)>;
2150 def : T2Pat<(int_arm_usat GPR:$a, imm:$pos), (t2USAT imm:$pos, GPR:$a, 0)>;
2152 //===----------------------------------------------------------------------===//
2153 // Shift and rotate Instructions.
2156 defm t2LSL : T2I_sh_ir<0b00, "lsl", imm0_31,
2157 BinOpFrag<(shl node:$LHS, node:$RHS)>>;
2158 defm t2LSR : T2I_sh_ir<0b01, "lsr", imm_sr,
2159 BinOpFrag<(srl node:$LHS, node:$RHS)>>;
2160 defm t2ASR : T2I_sh_ir<0b10, "asr", imm_sr,
2161 BinOpFrag<(sra node:$LHS, node:$RHS)>>;
2162 defm t2ROR : T2I_sh_ir<0b11, "ror", imm0_31,
2163 BinOpFrag<(rotr node:$LHS, node:$RHS)>>;
2165 // (rotr x, (and y, 0x...1f)) ==> (ROR x, y)
2166 def : T2Pat<(rotr rGPR:$lhs, (and rGPR:$rhs, lo5AllOne)),
2167 (t2RORrr rGPR:$lhs, rGPR:$rhs)>;
2169 let Uses = [CPSR] in {
2170 def t2RRX : T2sTwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iMOVsi,
2171 "rrx", "\t$Rd, $Rm",
2172 [(set rGPR:$Rd, (ARMrrx rGPR:$Rm))]> {
2173 let Inst{31-27} = 0b11101;
2174 let Inst{26-25} = 0b01;
2175 let Inst{24-21} = 0b0010;
2176 let Inst{19-16} = 0b1111; // Rn
2177 let Inst{14-12} = 0b000;
2178 let Inst{7-4} = 0b0011;
2182 let isCodeGenOnly = 1, Defs = [CPSR] in {
2183 def t2MOVsrl_flag : T2TwoRegShiftImm<
2184 (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iMOVsi,
2185 "lsrs", ".w\t$Rd, $Rm, #1",
2186 [(set rGPR:$Rd, (ARMsrl_flag rGPR:$Rm))]> {
2187 let Inst{31-27} = 0b11101;
2188 let Inst{26-25} = 0b01;
2189 let Inst{24-21} = 0b0010;
2190 let Inst{20} = 1; // The S bit.
2191 let Inst{19-16} = 0b1111; // Rn
2192 let Inst{5-4} = 0b01; // Shift type.
2193 // Shift amount = Inst{14-12:7-6} = 1.
2194 let Inst{14-12} = 0b000;
2195 let Inst{7-6} = 0b01;
2197 def t2MOVsra_flag : T2TwoRegShiftImm<
2198 (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iMOVsi,
2199 "asrs", ".w\t$Rd, $Rm, #1",
2200 [(set rGPR:$Rd, (ARMsra_flag rGPR:$Rm))]> {
2201 let Inst{31-27} = 0b11101;
2202 let Inst{26-25} = 0b01;
2203 let Inst{24-21} = 0b0010;
2204 let Inst{20} = 1; // The S bit.
2205 let Inst{19-16} = 0b1111; // Rn
2206 let Inst{5-4} = 0b10; // Shift type.
2207 // Shift amount = Inst{14-12:7-6} = 1.
2208 let Inst{14-12} = 0b000;
2209 let Inst{7-6} = 0b01;
2213 //===----------------------------------------------------------------------===//
2214 // Bitwise Instructions.
2217 defm t2AND : T2I_bin_w_irs<0b0000, "and",
2218 IIC_iBITi, IIC_iBITr, IIC_iBITsi,
2219 BinOpFrag<(and node:$LHS, node:$RHS)>, 1>;
2220 defm t2ORR : T2I_bin_w_irs<0b0010, "orr",
2221 IIC_iBITi, IIC_iBITr, IIC_iBITsi,
2222 BinOpFrag<(or node:$LHS, node:$RHS)>, 1>;
2223 defm t2EOR : T2I_bin_w_irs<0b0100, "eor",
2224 IIC_iBITi, IIC_iBITr, IIC_iBITsi,
2225 BinOpFrag<(xor node:$LHS, node:$RHS)>, 1>;
2227 defm t2BIC : T2I_bin_w_irs<0b0001, "bic",
2228 IIC_iBITi, IIC_iBITr, IIC_iBITsi,
2229 BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
2231 class T2BitFI<dag oops, dag iops, InstrItinClass itin,
2232 string opc, string asm, list<dag> pattern>
2233 : T2I<oops, iops, itin, opc, asm, pattern> {
2238 let Inst{11-8} = Rd;
2239 let Inst{4-0} = msb{4-0};
2240 let Inst{14-12} = lsb{4-2};
2241 let Inst{7-6} = lsb{1-0};
2244 class T2TwoRegBitFI<dag oops, dag iops, InstrItinClass itin,
2245 string opc, string asm, list<dag> pattern>
2246 : T2BitFI<oops, iops, itin, opc, asm, pattern> {
2249 let Inst{19-16} = Rn;
2252 let Constraints = "$src = $Rd" in
2253 def t2BFC : T2BitFI<(outs rGPR:$Rd), (ins rGPR:$src, bf_inv_mask_imm:$imm),
2254 IIC_iUNAsi, "bfc", "\t$Rd, $imm",
2255 [(set rGPR:$Rd, (and rGPR:$src, bf_inv_mask_imm:$imm))]> {
2256 let Inst{31-27} = 0b11110;
2257 let Inst{26} = 0; // should be 0.
2259 let Inst{24-20} = 0b10110;
2260 let Inst{19-16} = 0b1111; // Rn
2262 let Inst{5} = 0; // should be 0.
2265 let msb{4-0} = imm{9-5};
2266 let lsb{4-0} = imm{4-0};
2269 def t2SBFX: T2TwoRegBitFI<
2270 (outs rGPR:$Rd), (ins rGPR:$Rn, imm0_31:$lsb, imm1_32:$msb),
2271 IIC_iUNAsi, "sbfx", "\t$Rd, $Rn, $lsb, $msb", []> {
2272 let Inst{31-27} = 0b11110;
2274 let Inst{24-20} = 0b10100;
2278 def t2UBFX: T2TwoRegBitFI<
2279 (outs rGPR:$Rd), (ins rGPR:$Rn, imm0_31:$lsb, imm1_32:$msb),
2280 IIC_iUNAsi, "ubfx", "\t$Rd, $Rn, $lsb, $msb", []> {
2281 let Inst{31-27} = 0b11110;
2283 let Inst{24-20} = 0b11100;
2287 // A8.6.18 BFI - Bitfield insert (Encoding T1)
2288 let Constraints = "$src = $Rd" in {
2289 def t2BFI : T2TwoRegBitFI<(outs rGPR:$Rd),
2290 (ins rGPR:$src, rGPR:$Rn, bf_inv_mask_imm:$imm),
2291 IIC_iBITi, "bfi", "\t$Rd, $Rn, $imm",
2292 [(set rGPR:$Rd, (ARMbfi rGPR:$src, rGPR:$Rn,
2293 bf_inv_mask_imm:$imm))]> {
2294 let Inst{31-27} = 0b11110;
2295 let Inst{26} = 0; // should be 0.
2297 let Inst{24-20} = 0b10110;
2299 let Inst{5} = 0; // should be 0.
2302 let msb{4-0} = imm{9-5};
2303 let lsb{4-0} = imm{4-0};
2307 defm t2ORN : T2I_bin_irs<0b0011, "orn",
2308 IIC_iBITi, IIC_iBITr, IIC_iBITsi,
2309 BinOpFrag<(or node:$LHS, (not node:$RHS))>, 0, "">;
2311 /// T2I_un_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a
2312 /// unary operation that produces a value. These are predicable and can be
2313 /// changed to modify CPSR.
2314 multiclass T2I_un_irs<bits<4> opcod, string opc,
2315 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
2316 PatFrag opnode, bit Cheap = 0, bit ReMat = 0> {
2318 def i : T2sOneRegImm<(outs rGPR:$Rd), (ins t2_so_imm:$imm), iii,
2320 [(set rGPR:$Rd, (opnode t2_so_imm:$imm))]> {
2321 let isAsCheapAsAMove = Cheap;
2322 let isReMaterializable = ReMat;
2323 let Inst{31-27} = 0b11110;
2325 let Inst{24-21} = opcod;
2326 let Inst{19-16} = 0b1111; // Rn
2330 def r : T2sTwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm), iir,
2331 opc, ".w\t$Rd, $Rm",
2332 [(set rGPR:$Rd, (opnode rGPR:$Rm))]> {
2333 let Inst{31-27} = 0b11101;
2334 let Inst{26-25} = 0b01;
2335 let Inst{24-21} = opcod;
2336 let Inst{19-16} = 0b1111; // Rn
2337 let Inst{14-12} = 0b000; // imm3
2338 let Inst{7-6} = 0b00; // imm2
2339 let Inst{5-4} = 0b00; // type
2342 def s : T2sOneRegShiftedReg<(outs rGPR:$Rd), (ins t2_so_reg:$ShiftedRm), iis,
2343 opc, ".w\t$Rd, $ShiftedRm",
2344 [(set rGPR:$Rd, (opnode t2_so_reg:$ShiftedRm))]> {
2345 let Inst{31-27} = 0b11101;
2346 let Inst{26-25} = 0b01;
2347 let Inst{24-21} = opcod;
2348 let Inst{19-16} = 0b1111; // Rn
2352 // Prefer over of t2EORri ra, rb, -1 because mvn has 16-bit version
2353 let AddedComplexity = 1 in
2354 defm t2MVN : T2I_un_irs <0b0011, "mvn",
2355 IIC_iMVNi, IIC_iMVNr, IIC_iMVNsi,
2356 UnOpFrag<(not node:$Src)>, 1, 1>;
2358 let AddedComplexity = 1 in
2359 def : T2Pat<(and rGPR:$src, t2_so_imm_not:$imm),
2360 (t2BICri rGPR:$src, t2_so_imm_not:$imm)>;
2362 // top16Zero - answer true if the upper 16 bits of $src are 0, false otherwise
2363 def top16Zero: PatLeaf<(i32 rGPR:$src), [{
2364 return CurDAG->MaskedValueIsZero(SDValue(N,0), APInt::getHighBitsSet(32, 16));
2367 // so_imm_notSext is needed instead of so_imm_not, as the value of imm
2368 // will match the extended, not the original bitWidth for $src.
2369 def : T2Pat<(and top16Zero:$src, t2_so_imm_notSext:$imm),
2370 (t2BICri rGPR:$src, t2_so_imm_notSext:$imm)>;
2373 // FIXME: Disable this pattern on Darwin to workaround an assembler bug.
2374 def : T2Pat<(or rGPR:$src, t2_so_imm_not:$imm),
2375 (t2ORNri rGPR:$src, t2_so_imm_not:$imm)>,
2376 Requires<[IsThumb2]>;
2378 def : T2Pat<(t2_so_imm_not:$src),
2379 (t2MVNi t2_so_imm_not:$src)>;
2381 //===----------------------------------------------------------------------===//
2382 // Multiply Instructions.
2384 let isCommutable = 1 in
2385 def t2MUL: T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL32,
2386 "mul", "\t$Rd, $Rn, $Rm",
2387 [(set rGPR:$Rd, (mul rGPR:$Rn, rGPR:$Rm))]> {
2388 let Inst{31-27} = 0b11111;
2389 let Inst{26-23} = 0b0110;
2390 let Inst{22-20} = 0b000;
2391 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2392 let Inst{7-4} = 0b0000; // Multiply
2395 def t2MLA: T2FourReg<
2396 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2397 "mla", "\t$Rd, $Rn, $Rm, $Ra",
2398 [(set rGPR:$Rd, (add (mul rGPR:$Rn, rGPR:$Rm), rGPR:$Ra))]> {
2399 let Inst{31-27} = 0b11111;
2400 let Inst{26-23} = 0b0110;
2401 let Inst{22-20} = 0b000;
2402 let Inst{7-4} = 0b0000; // Multiply
2405 def t2MLS: T2FourReg<
2406 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2407 "mls", "\t$Rd, $Rn, $Rm, $Ra",
2408 [(set rGPR:$Rd, (sub rGPR:$Ra, (mul rGPR:$Rn, rGPR:$Rm)))]> {
2409 let Inst{31-27} = 0b11111;
2410 let Inst{26-23} = 0b0110;
2411 let Inst{22-20} = 0b000;
2412 let Inst{7-4} = 0b0001; // Multiply and Subtract
2415 // Extra precision multiplies with low / high results
2416 let neverHasSideEffects = 1 in {
2417 let isCommutable = 1 in {
2418 def t2SMULL : T2MulLong<0b000, 0b0000,
2419 (outs rGPR:$RdLo, rGPR:$RdHi),
2420 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL64,
2421 "smull", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2423 def t2UMULL : T2MulLong<0b010, 0b0000,
2424 (outs rGPR:$RdLo, rGPR:$RdHi),
2425 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL64,
2426 "umull", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2429 // Multiply + accumulate
2430 def t2SMLAL : T2MlaLong<0b100, 0b0000,
2431 (outs rGPR:$RdLo, rGPR:$RdHi, rGPR:$RLo, rGPR:$RHi),
2432 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMAC64,
2433 "smlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
2434 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">;
2436 def t2UMLAL : T2MlaLong<0b110, 0b0000,
2437 (outs rGPR:$RdLo, rGPR:$RdHi, rGPR:$RLo, rGPR:$RHi),
2438 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMAC64,
2439 "umlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
2440 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">;
2442 def t2UMAAL : T2MulLong<0b110, 0b0110,
2443 (outs rGPR:$RdLo, rGPR:$RdHi),
2444 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMAC64,
2445 "umaal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
2446 Requires<[IsThumb2, HasThumb2DSP]>;
2447 } // neverHasSideEffects
2449 // Rounding variants of the below included for disassembly only
2451 // Most significant word multiply
2452 def t2SMMUL : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL32,
2453 "smmul", "\t$Rd, $Rn, $Rm",
2454 [(set rGPR:$Rd, (mulhs rGPR:$Rn, rGPR:$Rm))]>,
2455 Requires<[IsThumb2, HasThumb2DSP]> {
2456 let Inst{31-27} = 0b11111;
2457 let Inst{26-23} = 0b0110;
2458 let Inst{22-20} = 0b101;
2459 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2460 let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
2463 def t2SMMULR : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL32,
2464 "smmulr", "\t$Rd, $Rn, $Rm", []>,
2465 Requires<[IsThumb2, HasThumb2DSP]> {
2466 let Inst{31-27} = 0b11111;
2467 let Inst{26-23} = 0b0110;
2468 let Inst{22-20} = 0b101;
2469 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2470 let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1)
2473 def t2SMMLA : T2FourReg<
2474 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2475 "smmla", "\t$Rd, $Rn, $Rm, $Ra",
2476 [(set rGPR:$Rd, (add (mulhs rGPR:$Rm, rGPR:$Rn), rGPR:$Ra))]>,
2477 Requires<[IsThumb2, HasThumb2DSP]> {
2478 let Inst{31-27} = 0b11111;
2479 let Inst{26-23} = 0b0110;
2480 let Inst{22-20} = 0b101;
2481 let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
2484 def t2SMMLAR: T2FourReg<
2485 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2486 "smmlar", "\t$Rd, $Rn, $Rm, $Ra", []>,
2487 Requires<[IsThumb2, HasThumb2DSP]> {
2488 let Inst{31-27} = 0b11111;
2489 let Inst{26-23} = 0b0110;
2490 let Inst{22-20} = 0b101;
2491 let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1)
2494 def t2SMMLS: T2FourReg<
2495 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2496 "smmls", "\t$Rd, $Rn, $Rm, $Ra",
2497 [(set rGPR:$Rd, (sub rGPR:$Ra, (mulhs rGPR:$Rn, rGPR:$Rm)))]>,
2498 Requires<[IsThumb2, HasThumb2DSP]> {
2499 let Inst{31-27} = 0b11111;
2500 let Inst{26-23} = 0b0110;
2501 let Inst{22-20} = 0b110;
2502 let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
2505 def t2SMMLSR:T2FourReg<
2506 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2507 "smmlsr", "\t$Rd, $Rn, $Rm, $Ra", []>,
2508 Requires<[IsThumb2, HasThumb2DSP]> {
2509 let Inst{31-27} = 0b11111;
2510 let Inst{26-23} = 0b0110;
2511 let Inst{22-20} = 0b110;
2512 let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1)
2515 multiclass T2I_smul<string opc, PatFrag opnode> {
2516 def BB : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2517 !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm",
2518 [(set rGPR:$Rd, (opnode (sext_inreg rGPR:$Rn, i16),
2519 (sext_inreg rGPR:$Rm, i16)))]>,
2520 Requires<[IsThumb2, HasThumb2DSP]> {
2521 let Inst{31-27} = 0b11111;
2522 let Inst{26-23} = 0b0110;
2523 let Inst{22-20} = 0b001;
2524 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2525 let Inst{7-6} = 0b00;
2526 let Inst{5-4} = 0b00;
2529 def BT : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2530 !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm",
2531 [(set rGPR:$Rd, (opnode (sext_inreg rGPR:$Rn, i16),
2532 (sra rGPR:$Rm, (i32 16))))]>,
2533 Requires<[IsThumb2, HasThumb2DSP]> {
2534 let Inst{31-27} = 0b11111;
2535 let Inst{26-23} = 0b0110;
2536 let Inst{22-20} = 0b001;
2537 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2538 let Inst{7-6} = 0b00;
2539 let Inst{5-4} = 0b01;
2542 def TB : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2543 !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm",
2544 [(set rGPR:$Rd, (opnode (sra rGPR:$Rn, (i32 16)),
2545 (sext_inreg rGPR:$Rm, i16)))]>,
2546 Requires<[IsThumb2, HasThumb2DSP]> {
2547 let Inst{31-27} = 0b11111;
2548 let Inst{26-23} = 0b0110;
2549 let Inst{22-20} = 0b001;
2550 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2551 let Inst{7-6} = 0b00;
2552 let Inst{5-4} = 0b10;
2555 def TT : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2556 !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm",
2557 [(set rGPR:$Rd, (opnode (sra rGPR:$Rn, (i32 16)),
2558 (sra rGPR:$Rm, (i32 16))))]>,
2559 Requires<[IsThumb2, HasThumb2DSP]> {
2560 let Inst{31-27} = 0b11111;
2561 let Inst{26-23} = 0b0110;
2562 let Inst{22-20} = 0b001;
2563 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2564 let Inst{7-6} = 0b00;
2565 let Inst{5-4} = 0b11;
2568 def WB : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2569 !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm",
2570 [(set rGPR:$Rd, (sra (opnode rGPR:$Rn,
2571 (sext_inreg rGPR:$Rm, i16)), (i32 16)))]>,
2572 Requires<[IsThumb2, HasThumb2DSP]> {
2573 let Inst{31-27} = 0b11111;
2574 let Inst{26-23} = 0b0110;
2575 let Inst{22-20} = 0b011;
2576 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2577 let Inst{7-6} = 0b00;
2578 let Inst{5-4} = 0b00;
2581 def WT : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2582 !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm",
2583 [(set rGPR:$Rd, (sra (opnode rGPR:$Rn,
2584 (sra rGPR:$Rm, (i32 16))), (i32 16)))]>,
2585 Requires<[IsThumb2, HasThumb2DSP]> {
2586 let Inst{31-27} = 0b11111;
2587 let Inst{26-23} = 0b0110;
2588 let Inst{22-20} = 0b011;
2589 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2590 let Inst{7-6} = 0b00;
2591 let Inst{5-4} = 0b01;
2596 multiclass T2I_smla<string opc, PatFrag opnode> {
2598 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2599 !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm, $Ra",
2600 [(set rGPR:$Rd, (add rGPR:$Ra,
2601 (opnode (sext_inreg rGPR:$Rn, i16),
2602 (sext_inreg rGPR:$Rm, i16))))]>,
2603 Requires<[IsThumb2, HasThumb2DSP]> {
2604 let Inst{31-27} = 0b11111;
2605 let Inst{26-23} = 0b0110;
2606 let Inst{22-20} = 0b001;
2607 let Inst{7-6} = 0b00;
2608 let Inst{5-4} = 0b00;
2612 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2613 !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm, $Ra",
2614 [(set rGPR:$Rd, (add rGPR:$Ra, (opnode (sext_inreg rGPR:$Rn, i16),
2615 (sra rGPR:$Rm, (i32 16)))))]>,
2616 Requires<[IsThumb2, HasThumb2DSP]> {
2617 let Inst{31-27} = 0b11111;
2618 let Inst{26-23} = 0b0110;
2619 let Inst{22-20} = 0b001;
2620 let Inst{7-6} = 0b00;
2621 let Inst{5-4} = 0b01;
2625 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2626 !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm, $Ra",
2627 [(set rGPR:$Rd, (add rGPR:$Ra, (opnode (sra rGPR:$Rn, (i32 16)),
2628 (sext_inreg rGPR:$Rm, i16))))]>,
2629 Requires<[IsThumb2, HasThumb2DSP]> {
2630 let Inst{31-27} = 0b11111;
2631 let Inst{26-23} = 0b0110;
2632 let Inst{22-20} = 0b001;
2633 let Inst{7-6} = 0b00;
2634 let Inst{5-4} = 0b10;
2638 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2639 !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm, $Ra",
2640 [(set rGPR:$Rd, (add rGPR:$Ra, (opnode (sra rGPR:$Rn, (i32 16)),
2641 (sra rGPR:$Rm, (i32 16)))))]>,
2642 Requires<[IsThumb2, HasThumb2DSP]> {
2643 let Inst{31-27} = 0b11111;
2644 let Inst{26-23} = 0b0110;
2645 let Inst{22-20} = 0b001;
2646 let Inst{7-6} = 0b00;
2647 let Inst{5-4} = 0b11;
2651 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2652 !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm, $Ra",
2653 [(set rGPR:$Rd, (add rGPR:$Ra, (sra (opnode rGPR:$Rn,
2654 (sext_inreg rGPR:$Rm, i16)), (i32 16))))]>,
2655 Requires<[IsThumb2, HasThumb2DSP]> {
2656 let Inst{31-27} = 0b11111;
2657 let Inst{26-23} = 0b0110;
2658 let Inst{22-20} = 0b011;
2659 let Inst{7-6} = 0b00;
2660 let Inst{5-4} = 0b00;
2664 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2665 !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm, $Ra",
2666 [(set rGPR:$Rd, (add rGPR:$Ra, (sra (opnode rGPR:$Rn,
2667 (sra rGPR:$Rm, (i32 16))), (i32 16))))]>,
2668 Requires<[IsThumb2, HasThumb2DSP]> {
2669 let Inst{31-27} = 0b11111;
2670 let Inst{26-23} = 0b0110;
2671 let Inst{22-20} = 0b011;
2672 let Inst{7-6} = 0b00;
2673 let Inst{5-4} = 0b01;
2677 defm t2SMUL : T2I_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
2678 defm t2SMLA : T2I_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
2680 // Halfword multiple accumulate long: SMLAL<x><y>
2681 def t2SMLALBB : T2FourReg_mac<1, 0b100, 0b1000, (outs rGPR:$Ra,rGPR:$Rd),
2682 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlalbb", "\t$Ra, $Rd, $Rn, $Rm",
2683 [/* For disassembly only; pattern left blank */]>,
2684 Requires<[IsThumb2, HasThumb2DSP]>;
2685 def t2SMLALBT : T2FourReg_mac<1, 0b100, 0b1001, (outs rGPR:$Ra,rGPR:$Rd),
2686 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlalbt", "\t$Ra, $Rd, $Rn, $Rm",
2687 [/* For disassembly only; pattern left blank */]>,
2688 Requires<[IsThumb2, HasThumb2DSP]>;
2689 def t2SMLALTB : T2FourReg_mac<1, 0b100, 0b1010, (outs rGPR:$Ra,rGPR:$Rd),
2690 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlaltb", "\t$Ra, $Rd, $Rn, $Rm",
2691 [/* For disassembly only; pattern left blank */]>,
2692 Requires<[IsThumb2, HasThumb2DSP]>;
2693 def t2SMLALTT : T2FourReg_mac<1, 0b100, 0b1011, (outs rGPR:$Ra,rGPR:$Rd),
2694 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlaltt", "\t$Ra, $Rd, $Rn, $Rm",
2695 [/* For disassembly only; pattern left blank */]>,
2696 Requires<[IsThumb2, HasThumb2DSP]>;
2698 // Dual halfword multiple: SMUAD, SMUSD, SMLAD, SMLSD, SMLALD, SMLSLD
2699 def t2SMUAD: T2ThreeReg_mac<
2700 0, 0b010, 0b0000, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
2701 IIC_iMAC32, "smuad", "\t$Rd, $Rn, $Rm", []>,
2702 Requires<[IsThumb2, HasThumb2DSP]> {
2703 let Inst{15-12} = 0b1111;
2705 def t2SMUADX:T2ThreeReg_mac<
2706 0, 0b010, 0b0001, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
2707 IIC_iMAC32, "smuadx", "\t$Rd, $Rn, $Rm", []>,
2708 Requires<[IsThumb2, HasThumb2DSP]> {
2709 let Inst{15-12} = 0b1111;
2711 def t2SMUSD: T2ThreeReg_mac<
2712 0, 0b100, 0b0000, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
2713 IIC_iMAC32, "smusd", "\t$Rd, $Rn, $Rm", []>,
2714 Requires<[IsThumb2, HasThumb2DSP]> {
2715 let Inst{15-12} = 0b1111;
2717 def t2SMUSDX:T2ThreeReg_mac<
2718 0, 0b100, 0b0001, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
2719 IIC_iMAC32, "smusdx", "\t$Rd, $Rn, $Rm", []>,
2720 Requires<[IsThumb2, HasThumb2DSP]> {
2721 let Inst{15-12} = 0b1111;
2723 def t2SMLAD : T2FourReg_mac<
2724 0, 0b010, 0b0000, (outs rGPR:$Rd),
2725 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smlad",
2726 "\t$Rd, $Rn, $Rm, $Ra", []>,
2727 Requires<[IsThumb2, HasThumb2DSP]>;
2728 def t2SMLADX : T2FourReg_mac<
2729 0, 0b010, 0b0001, (outs rGPR:$Rd),
2730 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smladx",
2731 "\t$Rd, $Rn, $Rm, $Ra", []>,
2732 Requires<[IsThumb2, HasThumb2DSP]>;
2733 def t2SMLSD : T2FourReg_mac<0, 0b100, 0b0000, (outs rGPR:$Rd),
2734 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smlsd",
2735 "\t$Rd, $Rn, $Rm, $Ra", []>,
2736 Requires<[IsThumb2, HasThumb2DSP]>;
2737 def t2SMLSDX : T2FourReg_mac<0, 0b100, 0b0001, (outs rGPR:$Rd),
2738 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smlsdx",
2739 "\t$Rd, $Rn, $Rm, $Ra", []>,
2740 Requires<[IsThumb2, HasThumb2DSP]>;
2741 def t2SMLALD : T2FourReg_mac<1, 0b100, 0b1100, (outs rGPR:$Ra,rGPR:$Rd),
2742 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMAC64, "smlald",
2743 "\t$Ra, $Rd, $Rn, $Rm", []>,
2744 Requires<[IsThumb2, HasThumb2DSP]>;
2745 def t2SMLALDX : T2FourReg_mac<1, 0b100, 0b1101, (outs rGPR:$Ra,rGPR:$Rd),
2746 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlaldx",
2747 "\t$Ra, $Rd, $Rn, $Rm", []>,
2748 Requires<[IsThumb2, HasThumb2DSP]>;
2749 def t2SMLSLD : T2FourReg_mac<1, 0b101, 0b1100, (outs rGPR:$Ra,rGPR:$Rd),
2750 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlsld",
2751 "\t$Ra, $Rd, $Rn, $Rm", []>,
2752 Requires<[IsThumb2, HasThumb2DSP]>;
2753 def t2SMLSLDX : T2FourReg_mac<1, 0b101, 0b1101, (outs rGPR:$Ra,rGPR:$Rd),
2754 (ins rGPR:$Rm,rGPR:$Rn), IIC_iMAC64, "smlsldx",
2755 "\t$Ra, $Rd, $Rn, $Rm", []>,
2756 Requires<[IsThumb2, HasThumb2DSP]>;
2758 //===----------------------------------------------------------------------===//
2759 // Division Instructions.
2760 // Signed and unsigned division on v7-M
2762 def t2SDIV : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUi,
2763 "sdiv", "\t$Rd, $Rn, $Rm",
2764 [(set rGPR:$Rd, (sdiv rGPR:$Rn, rGPR:$Rm))]>,
2765 Requires<[HasDivide, IsThumb2]> {
2766 let Inst{31-27} = 0b11111;
2767 let Inst{26-21} = 0b011100;
2769 let Inst{15-12} = 0b1111;
2770 let Inst{7-4} = 0b1111;
2773 def t2UDIV : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUi,
2774 "udiv", "\t$Rd, $Rn, $Rm",
2775 [(set rGPR:$Rd, (udiv rGPR:$Rn, rGPR:$Rm))]>,
2776 Requires<[HasDivide, IsThumb2]> {
2777 let Inst{31-27} = 0b11111;
2778 let Inst{26-21} = 0b011101;
2780 let Inst{15-12} = 0b1111;
2781 let Inst{7-4} = 0b1111;
2784 //===----------------------------------------------------------------------===//
2785 // Misc. Arithmetic Instructions.
2788 class T2I_misc<bits<2> op1, bits<2> op2, dag oops, dag iops,
2789 InstrItinClass itin, string opc, string asm, list<dag> pattern>
2790 : T2ThreeReg<oops, iops, itin, opc, asm, pattern> {
2791 let Inst{31-27} = 0b11111;
2792 let Inst{26-22} = 0b01010;
2793 let Inst{21-20} = op1;
2794 let Inst{15-12} = 0b1111;
2795 let Inst{7-6} = 0b10;
2796 let Inst{5-4} = op2;
2800 def t2CLZ : T2I_misc<0b11, 0b00, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2801 "clz", "\t$Rd, $Rm", [(set rGPR:$Rd, (ctlz rGPR:$Rm))]>;
2803 def t2RBIT : T2I_misc<0b01, 0b10, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2804 "rbit", "\t$Rd, $Rm",
2805 [(set rGPR:$Rd, (ARMrbit rGPR:$Rm))]>;
2807 def t2REV : T2I_misc<0b01, 0b00, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2808 "rev", ".w\t$Rd, $Rm", [(set rGPR:$Rd, (bswap rGPR:$Rm))]>;
2810 def t2REV16 : T2I_misc<0b01, 0b01, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2811 "rev16", ".w\t$Rd, $Rm",
2812 [(set rGPR:$Rd, (rotr (bswap rGPR:$Rm), (i32 16)))]>;
2814 def t2REVSH : T2I_misc<0b01, 0b11, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2815 "revsh", ".w\t$Rd, $Rm",
2816 [(set rGPR:$Rd, (sra (bswap rGPR:$Rm), (i32 16)))]>;
2818 def : T2Pat<(or (sra (shl rGPR:$Rm, (i32 24)), (i32 16)),
2819 (and (srl rGPR:$Rm, (i32 8)), 0xFF)),
2820 (t2REVSH rGPR:$Rm)>;
2822 def t2PKHBT : T2ThreeReg<
2823 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, pkh_lsl_amt:$sh),
2824 IIC_iBITsi, "pkhbt", "\t$Rd, $Rn, $Rm$sh",
2825 [(set rGPR:$Rd, (or (and rGPR:$Rn, 0xFFFF),
2826 (and (shl rGPR:$Rm, pkh_lsl_amt:$sh),
2828 Requires<[HasT2ExtractPack, IsThumb2]> {
2829 let Inst{31-27} = 0b11101;
2830 let Inst{26-25} = 0b01;
2831 let Inst{24-20} = 0b01100;
2832 let Inst{5} = 0; // BT form
2836 let Inst{14-12} = sh{4-2};
2837 let Inst{7-6} = sh{1-0};
2840 // Alternate cases for PKHBT where identities eliminate some nodes.
2841 def : T2Pat<(or (and rGPR:$src1, 0xFFFF), (and rGPR:$src2, 0xFFFF0000)),
2842 (t2PKHBT rGPR:$src1, rGPR:$src2, 0)>,
2843 Requires<[HasT2ExtractPack, IsThumb2]>;
2844 def : T2Pat<(or (and rGPR:$src1, 0xFFFF), (shl rGPR:$src2, imm16_31:$sh)),
2845 (t2PKHBT rGPR:$src1, rGPR:$src2, imm16_31:$sh)>,
2846 Requires<[HasT2ExtractPack, IsThumb2]>;
2848 // Note: Shifts of 1-15 bits will be transformed to srl instead of sra and
2849 // will match the pattern below.
2850 def t2PKHTB : T2ThreeReg<
2851 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, pkh_asr_amt:$sh),
2852 IIC_iBITsi, "pkhtb", "\t$Rd, $Rn, $Rm$sh",
2853 [(set rGPR:$Rd, (or (and rGPR:$Rn, 0xFFFF0000),
2854 (and (sra rGPR:$Rm, pkh_asr_amt:$sh),
2856 Requires<[HasT2ExtractPack, IsThumb2]> {
2857 let Inst{31-27} = 0b11101;
2858 let Inst{26-25} = 0b01;
2859 let Inst{24-20} = 0b01100;
2860 let Inst{5} = 1; // TB form
2864 let Inst{14-12} = sh{4-2};
2865 let Inst{7-6} = sh{1-0};
2868 // Alternate cases for PKHTB where identities eliminate some nodes. Note that
2869 // a shift amount of 0 is *not legal* here, it is PKHBT instead.
2870 def : T2Pat<(or (and rGPR:$src1, 0xFFFF0000), (srl rGPR:$src2, imm16_31:$sh)),
2871 (t2PKHTB rGPR:$src1, rGPR:$src2, imm16_31:$sh)>,
2872 Requires<[HasT2ExtractPack, IsThumb2]>;
2873 def : T2Pat<(or (and rGPR:$src1, 0xFFFF0000),
2874 (and (srl rGPR:$src2, imm1_15:$sh), 0xFFFF)),
2875 (t2PKHTB rGPR:$src1, rGPR:$src2, imm1_15:$sh)>,
2876 Requires<[HasT2ExtractPack, IsThumb2]>;
2878 //===----------------------------------------------------------------------===//
2879 // Comparison Instructions...
2881 defm t2CMP : T2I_cmp_irs<0b1101, "cmp",
2882 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsi,
2883 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
2885 def : T2Pat<(ARMcmpZ GPRnopc:$lhs, t2_so_imm:$imm),
2886 (t2CMPri GPRnopc:$lhs, t2_so_imm:$imm)>;
2887 def : T2Pat<(ARMcmpZ GPRnopc:$lhs, rGPR:$rhs),
2888 (t2CMPrr GPRnopc:$lhs, rGPR:$rhs)>;
2889 def : T2Pat<(ARMcmpZ GPRnopc:$lhs, t2_so_reg:$rhs),
2890 (t2CMPrs GPRnopc:$lhs, t2_so_reg:$rhs)>;
2892 let isCompare = 1, Defs = [CPSR] in {
2894 def t2CMNri : T2OneRegCmpImm<
2895 (outs), (ins GPRnopc:$Rn, t2_so_imm:$imm), IIC_iCMPi,
2896 "cmn", ".w\t$Rn, $imm",
2897 [(ARMcmn GPRnopc:$Rn, (ineg t2_so_imm:$imm))]> {
2898 let Inst{31-27} = 0b11110;
2900 let Inst{24-21} = 0b1000;
2901 let Inst{20} = 1; // The S bit.
2903 let Inst{11-8} = 0b1111; // Rd
2906 def t2CMNzrr : T2TwoRegCmp<
2907 (outs), (ins GPRnopc:$Rn, rGPR:$Rm), IIC_iCMPr,
2908 "cmn", ".w\t$Rn, $Rm",
2909 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>
2910 GPRnopc:$Rn, rGPR:$Rm)]> {
2911 let Inst{31-27} = 0b11101;
2912 let Inst{26-25} = 0b01;
2913 let Inst{24-21} = 0b1000;
2914 let Inst{20} = 1; // The S bit.
2915 let Inst{14-12} = 0b000; // imm3
2916 let Inst{11-8} = 0b1111; // Rd
2917 let Inst{7-6} = 0b00; // imm2
2918 let Inst{5-4} = 0b00; // type
2921 def t2CMNzrs : T2OneRegCmpShiftedReg<
2922 (outs), (ins GPRnopc:$Rn, t2_so_reg:$ShiftedRm), IIC_iCMPsi,
2923 "cmn", ".w\t$Rn, $ShiftedRm",
2924 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>
2925 GPRnopc:$Rn, t2_so_reg:$ShiftedRm)]> {
2926 let Inst{31-27} = 0b11101;
2927 let Inst{26-25} = 0b01;
2928 let Inst{24-21} = 0b1000;
2929 let Inst{20} = 1; // The S bit.
2930 let Inst{11-8} = 0b1111; // Rd
2934 // Assembler aliases w/o the ".w" suffix.
2935 // No alias here for 'rr' version as not all instantiations of this multiclass
2936 // want one (CMP in particular, does not).
2937 def : t2InstAlias<"cmn${p} $Rn, $imm",
2938 (t2CMNri GPRnopc:$Rn, t2_so_imm:$imm, pred:$p)>;
2939 def : t2InstAlias<"cmn${p} $Rn, $shift",
2940 (t2CMNzrs GPRnopc:$Rn, t2_so_reg:$shift, pred:$p)>;
2942 def : T2Pat<(ARMcmp GPR:$src, t2_so_imm_neg:$imm),
2943 (t2CMNri GPR:$src, t2_so_imm_neg:$imm)>;
2945 def : T2Pat<(ARMcmpZ GPRnopc:$src, t2_so_imm_neg:$imm),
2946 (t2CMNri GPRnopc:$src, t2_so_imm_neg:$imm)>;
2948 defm t2TST : T2I_cmp_irs<0b0000, "tst",
2949 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsi,
2950 BinOpFrag<(ARMcmpZ (and_su node:$LHS, node:$RHS), 0)>>;
2951 defm t2TEQ : T2I_cmp_irs<0b0100, "teq",
2952 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsi,
2953 BinOpFrag<(ARMcmpZ (xor_su node:$LHS, node:$RHS), 0)>>;
2955 // Conditional moves
2956 // FIXME: should be able to write a pattern for ARMcmov, but can't use
2957 // a two-value operand where a dag node expects two operands. :(
2958 let neverHasSideEffects = 1 in {
2960 let isCommutable = 1 in
2961 def t2MOVCCr : t2PseudoInst<(outs rGPR:$Rd),
2962 (ins rGPR:$false, rGPR:$Rm, pred:$p),
2964 [/*(set rGPR:$Rd, (ARMcmov rGPR:$false, rGPR:$Rm, imm:$cc, CCR:$ccr))*/]>,
2965 RegConstraint<"$false = $Rd">;
2967 let isMoveImm = 1 in
2968 def t2MOVCCi : t2PseudoInst<(outs rGPR:$Rd),
2969 (ins rGPR:$false, t2_so_imm:$imm, pred:$p),
2971 [/*(set rGPR:$Rd,(ARMcmov rGPR:$false,t2_so_imm:$imm, imm:$cc, CCR:$ccr))*/]>,
2972 RegConstraint<"$false = $Rd">;
2974 // FIXME: Pseudo-ize these. For now, just mark codegen only.
2975 let isCodeGenOnly = 1 in {
2976 let isMoveImm = 1 in
2977 def t2MOVCCi16 : T2I<(outs rGPR:$Rd), (ins rGPR:$false, imm0_65535_expr:$imm),
2979 "movw", "\t$Rd, $imm", []>,
2980 RegConstraint<"$false = $Rd"> {
2981 let Inst{31-27} = 0b11110;
2983 let Inst{24-21} = 0b0010;
2984 let Inst{20} = 0; // The S bit.
2990 let Inst{11-8} = Rd;
2991 let Inst{19-16} = imm{15-12};
2992 let Inst{26} = imm{11};
2993 let Inst{14-12} = imm{10-8};
2994 let Inst{7-0} = imm{7-0};
2997 let isMoveImm = 1 in
2998 def t2MOVCCi32imm : PseudoInst<(outs rGPR:$dst),
2999 (ins rGPR:$false, i32imm:$src, pred:$p),
3000 IIC_iCMOVix2, []>, RegConstraint<"$false = $dst">;
3002 let isMoveImm = 1 in
3003 def t2MVNCCi : T2OneRegImm<(outs rGPR:$Rd), (ins rGPR:$false, t2_so_imm:$imm),
3004 IIC_iCMOVi, "mvn", "\t$Rd, $imm",
3005 [/*(set rGPR:$Rd,(ARMcmov rGPR:$false,t2_so_imm_not:$imm,
3006 imm:$cc, CCR:$ccr))*/]>,
3007 RegConstraint<"$false = $Rd"> {
3008 let Inst{31-27} = 0b11110;
3010 let Inst{24-21} = 0b0011;
3011 let Inst{20} = 0; // The S bit.
3012 let Inst{19-16} = 0b1111; // Rn
3016 class T2I_movcc_sh<bits<2> opcod, dag oops, dag iops, InstrItinClass itin,
3017 string opc, string asm, list<dag> pattern>
3018 : T2TwoRegShiftImm<oops, iops, itin, opc, asm, pattern> {
3019 let Inst{31-27} = 0b11101;
3020 let Inst{26-25} = 0b01;
3021 let Inst{24-21} = 0b0010;
3022 let Inst{20} = 0; // The S bit.
3023 let Inst{19-16} = 0b1111; // Rn
3024 let Inst{5-4} = opcod; // Shift type.
3026 def t2MOVCClsl : T2I_movcc_sh<0b00, (outs rGPR:$Rd),
3027 (ins rGPR:$false, rGPR:$Rm, i32imm:$imm),
3028 IIC_iCMOVsi, "lsl", ".w\t$Rd, $Rm, $imm", []>,
3029 RegConstraint<"$false = $Rd">;
3030 def t2MOVCClsr : T2I_movcc_sh<0b01, (outs rGPR:$Rd),
3031 (ins rGPR:$false, rGPR:$Rm, i32imm:$imm),
3032 IIC_iCMOVsi, "lsr", ".w\t$Rd, $Rm, $imm", []>,
3033 RegConstraint<"$false = $Rd">;
3034 def t2MOVCCasr : T2I_movcc_sh<0b10, (outs rGPR:$Rd),
3035 (ins rGPR:$false, rGPR:$Rm, i32imm:$imm),
3036 IIC_iCMOVsi, "asr", ".w\t$Rd, $Rm, $imm", []>,
3037 RegConstraint<"$false = $Rd">;
3038 def t2MOVCCror : T2I_movcc_sh<0b11, (outs rGPR:$Rd),
3039 (ins rGPR:$false, rGPR:$Rm, i32imm:$imm),
3040 IIC_iCMOVsi, "ror", ".w\t$Rd, $Rm, $imm", []>,
3041 RegConstraint<"$false = $Rd">;
3042 } // isCodeGenOnly = 1
3044 multiclass T2I_bincc_irs<Instruction iri, Instruction irr, Instruction irs,
3045 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis> {
3047 def ri : t2PseudoExpand<(outs rGPR:$Rd),
3048 (ins rGPR:$Rn, t2_so_imm:$imm, pred:$p, cc_out:$s),
3050 (iri rGPR:$Rd, rGPR:$Rn, t2_so_imm:$imm, pred:$p, cc_out:$s)>,
3051 RegConstraint<"$Rn = $Rd">;
3053 def rr : t2PseudoExpand<(outs rGPR:$Rd),
3054 (ins rGPR:$Rn, rGPR:$Rm, pred:$p, cc_out:$s),
3056 (irr rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, pred:$p, cc_out:$s)>,
3057 RegConstraint<"$Rn = $Rd">;
3059 def rs : t2PseudoExpand<(outs rGPR:$Rd),
3060 (ins rGPR:$Rn, t2_so_reg:$ShiftedRm, pred:$p, cc_out:$s),
3062 (irs rGPR:$Rd, rGPR:$Rn, t2_so_reg:$ShiftedRm, pred:$p, cc_out:$s)>,
3063 RegConstraint<"$Rn = $Rd">;
3066 defm t2ANDCC : T2I_bincc_irs<t2ANDri, t2ANDrr, t2ANDrs,
3067 IIC_iBITi, IIC_iBITr, IIC_iBITsi>;
3068 defm t2ORRCC : T2I_bincc_irs<t2ORRri, t2ORRrr, t2ORRrs,
3069 IIC_iBITi, IIC_iBITr, IIC_iBITsi>;
3070 defm t2EORCC : T2I_bincc_irs<t2EORri, t2EORrr, t2EORrs,
3071 IIC_iBITi, IIC_iBITr, IIC_iBITsi>;
3072 } // neverHasSideEffects
3074 //===----------------------------------------------------------------------===//
3075 // Atomic operations intrinsics
3078 // memory barriers protect the atomic sequences
3079 let hasSideEffects = 1 in {
3080 def t2DMB : AInoP<(outs), (ins memb_opt:$opt), ThumbFrm, NoItinerary,
3081 "dmb", "\t$opt", [(ARMMemBarrier (i32 imm:$opt))]>,
3082 Requires<[IsThumb, HasDB]> {
3084 let Inst{31-4} = 0xf3bf8f5;
3085 let Inst{3-0} = opt;
3089 def t2DSB : AInoP<(outs), (ins memb_opt:$opt), ThumbFrm, NoItinerary,
3090 "dsb", "\t$opt", []>,
3091 Requires<[IsThumb, HasDB]> {
3093 let Inst{31-4} = 0xf3bf8f4;
3094 let Inst{3-0} = opt;
3097 def t2ISB : AInoP<(outs), (ins memb_opt:$opt), ThumbFrm, NoItinerary,
3099 []>, Requires<[IsThumb, HasDB]> {
3101 let Inst{31-4} = 0xf3bf8f6;
3102 let Inst{3-0} = opt;
3105 class T2I_ldrex<bits<2> opcod, dag oops, dag iops, AddrMode am, int sz,
3106 InstrItinClass itin, string opc, string asm, string cstr,
3107 list<dag> pattern, bits<4> rt2 = 0b1111>
3108 : Thumb2I<oops, iops, am, sz, itin, opc, asm, cstr, pattern> {
3109 let Inst{31-27} = 0b11101;
3110 let Inst{26-20} = 0b0001101;
3111 let Inst{11-8} = rt2;
3112 let Inst{7-6} = 0b01;
3113 let Inst{5-4} = opcod;
3114 let Inst{3-0} = 0b1111;
3118 let Inst{19-16} = addr;
3119 let Inst{15-12} = Rt;
3121 class T2I_strex<bits<2> opcod, dag oops, dag iops, AddrMode am, int sz,
3122 InstrItinClass itin, string opc, string asm, string cstr,
3123 list<dag> pattern, bits<4> rt2 = 0b1111>
3124 : Thumb2I<oops, iops, am, sz, itin, opc, asm, cstr, pattern> {
3125 let Inst{31-27} = 0b11101;
3126 let Inst{26-20} = 0b0001100;
3127 let Inst{11-8} = rt2;
3128 let Inst{7-6} = 0b01;
3129 let Inst{5-4} = opcod;
3135 let Inst{19-16} = addr;
3136 let Inst{15-12} = Rt;
3139 let mayLoad = 1 in {
3140 def t2LDREXB : T2I_ldrex<0b00, (outs rGPR:$Rt), (ins addr_offset_none:$addr),
3141 AddrModeNone, 4, NoItinerary,
3142 "ldrexb", "\t$Rt, $addr", "", []>;
3143 def t2LDREXH : T2I_ldrex<0b01, (outs rGPR:$Rt), (ins addr_offset_none:$addr),
3144 AddrModeNone, 4, NoItinerary,
3145 "ldrexh", "\t$Rt, $addr", "", []>;
3146 def t2LDREX : Thumb2I<(outs rGPR:$Rt), (ins t2addrmode_imm0_1020s4:$addr),
3147 AddrModeNone, 4, NoItinerary,
3148 "ldrex", "\t$Rt, $addr", "", []> {
3151 let Inst{31-27} = 0b11101;
3152 let Inst{26-20} = 0b0000101;
3153 let Inst{19-16} = addr{11-8};
3154 let Inst{15-12} = Rt;
3155 let Inst{11-8} = 0b1111;
3156 let Inst{7-0} = addr{7-0};
3158 let hasExtraDefRegAllocReq = 1 in
3159 def t2LDREXD : T2I_ldrex<0b11, (outs rGPR:$Rt, rGPR:$Rt2),
3160 (ins addr_offset_none:$addr),
3161 AddrModeNone, 4, NoItinerary,
3162 "ldrexd", "\t$Rt, $Rt2, $addr", "",
3165 let Inst{11-8} = Rt2;
3169 let mayStore = 1, Constraints = "@earlyclobber $Rd" in {
3170 def t2STREXB : T2I_strex<0b00, (outs rGPR:$Rd),
3171 (ins rGPR:$Rt, addr_offset_none:$addr),
3172 AddrModeNone, 4, NoItinerary,
3173 "strexb", "\t$Rd, $Rt, $addr", "", []>;
3174 def t2STREXH : T2I_strex<0b01, (outs rGPR:$Rd),
3175 (ins rGPR:$Rt, addr_offset_none:$addr),
3176 AddrModeNone, 4, NoItinerary,
3177 "strexh", "\t$Rd, $Rt, $addr", "", []>;
3178 def t2STREX : Thumb2I<(outs rGPR:$Rd), (ins rGPR:$Rt,
3179 t2addrmode_imm0_1020s4:$addr),
3180 AddrModeNone, 4, NoItinerary,
3181 "strex", "\t$Rd, $Rt, $addr", "",
3186 let Inst{31-27} = 0b11101;
3187 let Inst{26-20} = 0b0000100;
3188 let Inst{19-16} = addr{11-8};
3189 let Inst{15-12} = Rt;
3190 let Inst{11-8} = Rd;
3191 let Inst{7-0} = addr{7-0};
3193 let hasExtraSrcRegAllocReq = 1 in
3194 def t2STREXD : T2I_strex<0b11, (outs rGPR:$Rd),
3195 (ins rGPR:$Rt, rGPR:$Rt2, addr_offset_none:$addr),
3196 AddrModeNone, 4, NoItinerary,
3197 "strexd", "\t$Rd, $Rt, $Rt2, $addr", "", [],
3200 let Inst{11-8} = Rt2;
3204 def t2CLREX : T2I<(outs), (ins), NoItinerary, "clrex", "", []>,
3205 Requires<[IsThumb2, HasV7]> {
3206 let Inst{31-16} = 0xf3bf;
3207 let Inst{15-14} = 0b10;
3210 let Inst{11-8} = 0b1111;
3211 let Inst{7-4} = 0b0010;
3212 let Inst{3-0} = 0b1111;
3215 //===----------------------------------------------------------------------===//
3216 // SJLJ Exception handling intrinsics
3217 // eh_sjlj_setjmp() is an instruction sequence to store the return
3218 // address and save #0 in R0 for the non-longjmp case.
3219 // Since by its nature we may be coming from some other function to get
3220 // here, and we're using the stack frame for the containing function to
3221 // save/restore registers, we can't keep anything live in regs across
3222 // the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
3223 // when we get here from a longjmp(). We force everything out of registers
3224 // except for our own input by listing the relevant registers in Defs. By
3225 // doing so, we also cause the prologue/epilogue code to actively preserve
3226 // all of the callee-saved resgisters, which is exactly what we want.
3227 // $val is a scratch register for our use.
3229 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR,
3230 Q0, Q1, Q2, Q3, Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15],
3231 hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1,
3232 usesCustomInserter = 1 in {
3233 def t2Int_eh_sjlj_setjmp : Thumb2XI<(outs), (ins tGPR:$src, tGPR:$val),
3234 AddrModeNone, 0, NoItinerary, "", "",
3235 [(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>,
3236 Requires<[IsThumb2, HasVFP2]>;
3240 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR ],
3241 hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1,
3242 usesCustomInserter = 1 in {
3243 def t2Int_eh_sjlj_setjmp_nofp : Thumb2XI<(outs), (ins tGPR:$src, tGPR:$val),
3244 AddrModeNone, 0, NoItinerary, "", "",
3245 [(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>,
3246 Requires<[IsThumb2, NoVFP]>;
3250 //===----------------------------------------------------------------------===//
3251 // Control-Flow Instructions
3254 // FIXME: remove when we have a way to marking a MI with these properties.
3255 // FIXME: Should pc be an implicit operand like PICADD, etc?
3256 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
3257 hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in
3258 def t2LDMIA_RET: t2PseudoExpand<(outs GPR:$wb), (ins GPR:$Rn, pred:$p,
3259 reglist:$regs, variable_ops),
3260 4, IIC_iLoad_mBr, [],
3261 (t2LDMIA_UPD GPR:$wb, GPR:$Rn, pred:$p, reglist:$regs)>,
3262 RegConstraint<"$Rn = $wb">;
3264 let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
3265 let isPredicable = 1 in
3266 def t2B : T2I<(outs), (ins uncondbrtarget:$target), IIC_Br,
3268 [(br bb:$target)]> {
3269 let Inst{31-27} = 0b11110;
3270 let Inst{15-14} = 0b10;
3274 let Inst{26} = target{19};
3275 let Inst{11} = target{18};
3276 let Inst{13} = target{17};
3277 let Inst{21-16} = target{16-11};
3278 let Inst{10-0} = target{10-0};
3279 let DecoderMethod = "DecodeT2BInstruction";
3282 let isNotDuplicable = 1, isIndirectBranch = 1 in {
3283 def t2BR_JT : t2PseudoInst<(outs),
3284 (ins GPR:$target, GPR:$index, i32imm:$jt, i32imm:$id),
3286 [(ARMbr2jt GPR:$target, GPR:$index, tjumptable:$jt, imm:$id)]>;
3288 // FIXME: Add a non-pc based case that can be predicated.
3289 def t2TBB_JT : t2PseudoInst<(outs),
3290 (ins GPR:$index, i32imm:$jt, i32imm:$id), 0, IIC_Br, []>;
3292 def t2TBH_JT : t2PseudoInst<(outs),
3293 (ins GPR:$index, i32imm:$jt, i32imm:$id), 0, IIC_Br, []>;
3295 def t2TBB : T2I<(outs), (ins addrmode_tbb:$addr), IIC_Br,
3296 "tbb", "\t$addr", []> {
3299 let Inst{31-20} = 0b111010001101;
3300 let Inst{19-16} = Rn;
3301 let Inst{15-5} = 0b11110000000;
3302 let Inst{4} = 0; // B form
3305 let DecoderMethod = "DecodeThumbTableBranch";
3308 def t2TBH : T2I<(outs), (ins addrmode_tbh:$addr), IIC_Br,
3309 "tbh", "\t$addr", []> {
3312 let Inst{31-20} = 0b111010001101;
3313 let Inst{19-16} = Rn;
3314 let Inst{15-5} = 0b11110000000;
3315 let Inst{4} = 1; // H form
3318 let DecoderMethod = "DecodeThumbTableBranch";
3320 } // isNotDuplicable, isIndirectBranch
3322 } // isBranch, isTerminator, isBarrier
3324 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
3325 // a two-value operand where a dag node expects ", "two operands. :(
3326 let isBranch = 1, isTerminator = 1 in
3327 def t2Bcc : T2I<(outs), (ins brtarget:$target), IIC_Br,
3329 [/*(ARMbrcond bb:$target, imm:$cc)*/]> {
3330 let Inst{31-27} = 0b11110;
3331 let Inst{15-14} = 0b10;
3335 let Inst{25-22} = p;
3338 let Inst{26} = target{20};
3339 let Inst{11} = target{19};
3340 let Inst{13} = target{18};
3341 let Inst{21-16} = target{17-12};
3342 let Inst{10-0} = target{11-1};
3344 let DecoderMethod = "DecodeThumb2BCCInstruction";
3347 // Tail calls. The IOS version of thumb tail calls uses a t2 branch, so
3349 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in {
3352 def tTAILJMPd: tPseudoExpand<(outs),
3353 (ins uncondbrtarget:$dst, pred:$p),
3355 (t2B uncondbrtarget:$dst, pred:$p)>,
3356 Requires<[IsThumb2, IsIOS]>;
3359 let isCall = 1, Defs = [LR], Uses = [SP] in {
3360 // mov lr, pc; b if callee is marked noreturn to avoid confusing the
3361 // return stack predictor.
3362 def t2BMOVPCB_CALL : tPseudoInst<(outs),
3363 (ins t_bltarget:$func),
3364 6, IIC_Br, [(ARMcall_nolink tglobaladdr:$func)]>,
3365 Requires<[IsThumb]>;
3369 def : T2Pat<(ARMcall_nolink texternalsym:$func),
3370 (t2BMOVPCB_CALL texternalsym:$func)>,
3371 Requires<[IsThumb]>;
3374 let Defs = [ITSTATE] in
3375 def t2IT : Thumb2XI<(outs), (ins it_pred:$cc, it_mask:$mask),
3376 AddrModeNone, 2, IIC_iALUx,
3377 "it$mask\t$cc", "", []> {
3378 // 16-bit instruction.
3379 let Inst{31-16} = 0x0000;
3380 let Inst{15-8} = 0b10111111;
3385 let Inst{3-0} = mask;
3387 let DecoderMethod = "DecodeIT";
3390 // Branch and Exchange Jazelle -- for disassembly only
3392 def t2BXJ : T2I<(outs), (ins rGPR:$func), NoItinerary, "bxj", "\t$func", []> {
3394 let Inst{31-27} = 0b11110;
3396 let Inst{25-20} = 0b111100;
3397 let Inst{19-16} = func;
3398 let Inst{15-0} = 0b1000111100000000;
3401 // Compare and branch on zero / non-zero
3402 let isBranch = 1, isTerminator = 1 in {
3403 def tCBZ : T1I<(outs), (ins tGPR:$Rn, t_cbtarget:$target), IIC_Br,
3404 "cbz\t$Rn, $target", []>,
3405 T1Misc<{0,0,?,1,?,?,?}>,
3406 Requires<[IsThumb2]> {
3410 let Inst{9} = target{5};
3411 let Inst{7-3} = target{4-0};
3415 def tCBNZ : T1I<(outs), (ins tGPR:$Rn, t_cbtarget:$target), IIC_Br,
3416 "cbnz\t$Rn, $target", []>,
3417 T1Misc<{1,0,?,1,?,?,?}>,
3418 Requires<[IsThumb2]> {
3422 let Inst{9} = target{5};
3423 let Inst{7-3} = target{4-0};
3429 // Change Processor State is a system instruction.
3430 // FIXME: Since the asm parser has currently no clean way to handle optional
3431 // operands, create 3 versions of the same instruction. Once there's a clean
3432 // framework to represent optional operands, change this behavior.
3433 class t2CPS<dag iops, string asm_op> : T2XI<(outs), iops, NoItinerary,
3434 !strconcat("cps", asm_op), []> {
3440 let Inst{31-27} = 0b11110;
3442 let Inst{25-20} = 0b111010;
3443 let Inst{19-16} = 0b1111;
3444 let Inst{15-14} = 0b10;
3446 let Inst{10-9} = imod;
3448 let Inst{7-5} = iflags;
3449 let Inst{4-0} = mode;
3450 let DecoderMethod = "DecodeT2CPSInstruction";
3454 def t2CPS3p : t2CPS<(ins imod_op:$imod, iflags_op:$iflags, i32imm:$mode),
3455 "$imod.w\t$iflags, $mode">;
3456 let mode = 0, M = 0 in
3457 def t2CPS2p : t2CPS<(ins imod_op:$imod, iflags_op:$iflags),
3458 "$imod.w\t$iflags">;
3459 let imod = 0, iflags = 0, M = 1 in
3460 def t2CPS1p : t2CPS<(ins imm0_31:$mode), "\t$mode">;
3462 // A6.3.4 Branches and miscellaneous control
3463 // Table A6-14 Change Processor State, and hint instructions
3464 def t2HINT : T2I<(outs), (ins imm0_255:$imm), NoItinerary, "hint", "\t$imm",[]>{
3466 let Inst{31-8} = 0b111100111010111110000000;
3467 let Inst{7-0} = imm;
3470 def : t2InstAlias<"hint$p.w $imm", (t2HINT imm0_255:$imm, pred:$p)>;
3471 def : t2InstAlias<"nop$p.w", (t2HINT 0, pred:$p)>;
3472 def : t2InstAlias<"yield$p.w", (t2HINT 1, pred:$p)>;
3473 def : t2InstAlias<"wfe$p.w", (t2HINT 2, pred:$p)>;
3474 def : t2InstAlias<"wfi$p.w", (t2HINT 3, pred:$p)>;
3475 def : t2InstAlias<"sev$p.w", (t2HINT 4, pred:$p)>;
3477 def t2DBG : T2I<(outs), (ins imm0_15:$opt), NoItinerary, "dbg", "\t$opt", []> {
3479 let Inst{31-20} = 0b111100111010;
3480 let Inst{19-16} = 0b1111;
3481 let Inst{15-8} = 0b10000000;
3482 let Inst{7-4} = 0b1111;
3483 let Inst{3-0} = opt;
3486 // Secure Monitor Call is a system instruction.
3487 // Option = Inst{19-16}
3488 def t2SMC : T2I<(outs), (ins imm0_15:$opt), NoItinerary, "smc", "\t$opt", []> {
3489 let Inst{31-27} = 0b11110;
3490 let Inst{26-20} = 0b1111111;
3491 let Inst{15-12} = 0b1000;
3494 let Inst{19-16} = opt;
3497 class T2SRS<bits<2> Op, bit W, dag oops, dag iops, InstrItinClass itin,
3498 string opc, string asm, list<dag> pattern>
3499 : T2I<oops, iops, itin, opc, asm, pattern> {
3501 let Inst{31-25} = 0b1110100;
3502 let Inst{24-23} = Op;
3505 let Inst{20-16} = 0b01101;
3506 let Inst{15-5} = 0b11000000000;
3507 let Inst{4-0} = mode{4-0};
3510 // Store Return State is a system instruction.
3511 def t2SRSDB_UPD : T2SRS<0b00, 1, (outs), (ins imm0_31:$mode), NoItinerary,
3512 "srsdb", "\tsp!, $mode", []>;
3513 def t2SRSDB : T2SRS<0b00, 0, (outs), (ins imm0_31:$mode), NoItinerary,
3514 "srsdb","\tsp, $mode", []>;
3515 def t2SRSIA_UPD : T2SRS<0b11, 1, (outs), (ins imm0_31:$mode), NoItinerary,
3516 "srsia","\tsp!, $mode", []>;
3517 def t2SRSIA : T2SRS<0b11, 0, (outs), (ins imm0_31:$mode), NoItinerary,
3518 "srsia","\tsp, $mode", []>;
3520 // Return From Exception is a system instruction.
3521 class T2RFE<bits<12> op31_20, dag oops, dag iops, InstrItinClass itin,
3522 string opc, string asm, list<dag> pattern>
3523 : T2I<oops, iops, itin, opc, asm, pattern> {
3524 let Inst{31-20} = op31_20{11-0};
3527 let Inst{19-16} = Rn;
3528 let Inst{15-0} = 0xc000;
3531 def t2RFEDBW : T2RFE<0b111010000011,
3532 (outs), (ins GPR:$Rn), NoItinerary, "rfedb", "\t$Rn!",
3533 [/* For disassembly only; pattern left blank */]>;
3534 def t2RFEDB : T2RFE<0b111010000001,
3535 (outs), (ins GPR:$Rn), NoItinerary, "rfedb", "\t$Rn",
3536 [/* For disassembly only; pattern left blank */]>;
3537 def t2RFEIAW : T2RFE<0b111010011011,
3538 (outs), (ins GPR:$Rn), NoItinerary, "rfeia", "\t$Rn!",
3539 [/* For disassembly only; pattern left blank */]>;
3540 def t2RFEIA : T2RFE<0b111010011001,
3541 (outs), (ins GPR:$Rn), NoItinerary, "rfeia", "\t$Rn",
3542 [/* For disassembly only; pattern left blank */]>;
3544 //===----------------------------------------------------------------------===//
3545 // Non-Instruction Patterns
3548 // 32-bit immediate using movw + movt.
3549 // This is a single pseudo instruction to make it re-materializable.
3550 // FIXME: Remove this when we can do generalized remat.
3551 let isReMaterializable = 1, isMoveImm = 1 in
3552 def t2MOVi32imm : PseudoInst<(outs rGPR:$dst), (ins i32imm:$src), IIC_iMOVix2,
3553 [(set rGPR:$dst, (i32 imm:$src))]>,
3554 Requires<[IsThumb, HasV6T2]>;
3556 // Pseudo instruction that combines movw + movt + add pc (if pic).
3557 // It also makes it possible to rematerialize the instructions.
3558 // FIXME: Remove this when we can do generalized remat and when machine licm
3559 // can properly the instructions.
3560 let isReMaterializable = 1 in {
3561 def t2MOV_ga_pcrel : PseudoInst<(outs rGPR:$dst), (ins i32imm:$addr),
3563 [(set rGPR:$dst, (ARMWrapperPIC tglobaladdr:$addr))]>,
3564 Requires<[IsThumb2, UseMovt]>;
3566 def t2MOV_ga_dyn : PseudoInst<(outs rGPR:$dst), (ins i32imm:$addr),
3568 [(set rGPR:$dst, (ARMWrapperDYN tglobaladdr:$addr))]>,
3569 Requires<[IsThumb2, UseMovt]>;
3572 // ConstantPool, GlobalAddress, and JumpTable
3573 def : T2Pat<(ARMWrapper tglobaladdr :$dst), (t2LEApcrel tglobaladdr :$dst)>,
3574 Requires<[IsThumb2, DontUseMovt]>;
3575 def : T2Pat<(ARMWrapper tconstpool :$dst), (t2LEApcrel tconstpool :$dst)>;
3576 def : T2Pat<(ARMWrapper tglobaladdr :$dst), (t2MOVi32imm tglobaladdr :$dst)>,
3577 Requires<[IsThumb2, UseMovt]>;
3579 def : T2Pat<(ARMWrapperJT tjumptable:$dst, imm:$id),
3580 (t2LEApcrelJT tjumptable:$dst, imm:$id)>;
3582 // Pseudo instruction that combines ldr from constpool and add pc. This should
3583 // be expanded into two instructions late to allow if-conversion and
3585 let canFoldAsLoad = 1, isReMaterializable = 1 in
3586 def t2LDRpci_pic : PseudoInst<(outs rGPR:$dst), (ins i32imm:$addr, pclabel:$cp),
3588 [(set rGPR:$dst, (ARMpic_add (load (ARMWrapper tconstpool:$addr)),
3590 Requires<[IsThumb2]>;
3592 // Pseudo isntruction that combines movs + predicated rsbmi
3593 // to implement integer ABS
3594 let usesCustomInserter = 1, Defs = [CPSR] in {
3595 def t2ABS : PseudoInst<(outs rGPR:$dst), (ins rGPR:$src),
3596 NoItinerary, []>, Requires<[IsThumb2]>;
3599 //===----------------------------------------------------------------------===//
3600 // Coprocessor load/store -- for disassembly only
3602 class T2CI<bits<4> op31_28, dag oops, dag iops, string opc, string asm>
3603 : T2I<oops, iops, NoItinerary, opc, asm, []> {
3604 let Inst{31-28} = op31_28;
3605 let Inst{27-25} = 0b110;
3608 multiclass t2LdStCop<bits<4> op31_28, bit load, bit Dbit, string asm> {
3609 def _OFFSET : T2CI<op31_28,
3610 (outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr),
3611 asm, "\t$cop, $CRd, $addr"> {
3615 let Inst{24} = 1; // P = 1
3616 let Inst{23} = addr{8};
3617 let Inst{22} = Dbit;
3618 let Inst{21} = 0; // W = 0
3619 let Inst{20} = load;
3620 let Inst{19-16} = addr{12-9};
3621 let Inst{15-12} = CRd;
3622 let Inst{11-8} = cop;
3623 let Inst{7-0} = addr{7-0};
3624 let DecoderMethod = "DecodeCopMemInstruction";
3626 def _PRE : T2CI<op31_28,
3627 (outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr),
3628 asm, "\t$cop, $CRd, $addr!"> {
3632 let Inst{24} = 1; // P = 1
3633 let Inst{23} = addr{8};
3634 let Inst{22} = Dbit;
3635 let Inst{21} = 1; // W = 1
3636 let Inst{20} = load;
3637 let Inst{19-16} = addr{12-9};
3638 let Inst{15-12} = CRd;
3639 let Inst{11-8} = cop;
3640 let Inst{7-0} = addr{7-0};
3641 let DecoderMethod = "DecodeCopMemInstruction";
3643 def _POST: T2CI<op31_28,
3644 (outs), (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
3645 postidx_imm8s4:$offset),
3646 asm, "\t$cop, $CRd, $addr, $offset"> {
3651 let Inst{24} = 0; // P = 0
3652 let Inst{23} = offset{8};
3653 let Inst{22} = Dbit;
3654 let Inst{21} = 1; // W = 1
3655 let Inst{20} = load;
3656 let Inst{19-16} = addr;
3657 let Inst{15-12} = CRd;
3658 let Inst{11-8} = cop;
3659 let Inst{7-0} = offset{7-0};
3660 let DecoderMethod = "DecodeCopMemInstruction";
3662 def _OPTION : T2CI<op31_28, (outs),
3663 (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
3664 coproc_option_imm:$option),
3665 asm, "\t$cop, $CRd, $addr, $option"> {
3670 let Inst{24} = 0; // P = 0
3671 let Inst{23} = 1; // U = 1
3672 let Inst{22} = Dbit;
3673 let Inst{21} = 0; // W = 0
3674 let Inst{20} = load;
3675 let Inst{19-16} = addr;
3676 let Inst{15-12} = CRd;
3677 let Inst{11-8} = cop;
3678 let Inst{7-0} = option;
3679 let DecoderMethod = "DecodeCopMemInstruction";
3683 defm t2LDC : t2LdStCop<0b1110, 1, 0, "ldc">;
3684 defm t2LDCL : t2LdStCop<0b1110, 1, 1, "ldcl">;
3685 defm t2STC : t2LdStCop<0b1110, 0, 0, "stc">;
3686 defm t2STCL : t2LdStCop<0b1110, 0, 1, "stcl">;
3687 defm t2LDC2 : t2LdStCop<0b1111, 1, 0, "ldc2">;
3688 defm t2LDC2L : t2LdStCop<0b1111, 1, 1, "ldc2l">;
3689 defm t2STC2 : t2LdStCop<0b1111, 0, 0, "stc2">;
3690 defm t2STC2L : t2LdStCop<0b1111, 0, 1, "stc2l">;
3693 //===----------------------------------------------------------------------===//
3694 // Move between special register and ARM core register -- for disassembly only
3696 // Move to ARM core register from Special Register
3700 // A/R class can only move from CPSR or SPSR.
3701 def t2MRS_AR : T2I<(outs GPR:$Rd), (ins), NoItinerary, "mrs", "\t$Rd, apsr",
3702 []>, Requires<[IsThumb2,IsARClass]> {
3704 let Inst{31-12} = 0b11110011111011111000;
3705 let Inst{11-8} = Rd;
3706 let Inst{7-0} = 0b0000;
3709 def : t2InstAlias<"mrs${p} $Rd, cpsr", (t2MRS_AR GPR:$Rd, pred:$p)>;
3711 def t2MRSsys_AR: T2I<(outs GPR:$Rd), (ins), NoItinerary, "mrs", "\t$Rd, spsr",
3712 []>, Requires<[IsThumb2,IsARClass]> {
3714 let Inst{31-12} = 0b11110011111111111000;
3715 let Inst{11-8} = Rd;
3716 let Inst{7-0} = 0b0000;
3721 // This MRS has a mask field in bits 7-0 and can take more values than
3722 // the A/R class (a full msr_mask).
3723 def t2MRS_M : T2I<(outs rGPR:$Rd), (ins msr_mask:$mask), NoItinerary,
3724 "mrs", "\t$Rd, $mask", []>,
3725 Requires<[IsThumb,IsMClass]> {
3728 let Inst{31-12} = 0b11110011111011111000;
3729 let Inst{11-8} = Rd;
3730 let Inst{19-16} = 0b1111;
3731 let Inst{7-0} = mask;
3735 // Move from ARM core register to Special Register
3739 // No need to have both system and application versions, the encodings are the
3740 // same and the assembly parser has no way to distinguish between them. The mask
3741 // operand contains the special register (R Bit) in bit 4 and bits 3-0 contains
3742 // the mask with the fields to be accessed in the special register.
3743 def t2MSR_AR : T2I<(outs), (ins msr_mask:$mask, rGPR:$Rn),
3744 NoItinerary, "msr", "\t$mask, $Rn", []>,
3745 Requires<[IsThumb2,IsARClass]> {
3748 let Inst{31-21} = 0b11110011100;
3749 let Inst{20} = mask{4}; // R Bit
3750 let Inst{19-16} = Rn;
3751 let Inst{15-12} = 0b1000;
3752 let Inst{11-8} = mask{3-0};
3758 // Move from ARM core register to Special Register
3759 def t2MSR_M : T2I<(outs), (ins msr_mask:$SYSm, rGPR:$Rn),
3760 NoItinerary, "msr", "\t$SYSm, $Rn", []>,
3761 Requires<[IsThumb,IsMClass]> {
3764 let Inst{31-21} = 0b11110011100;
3766 let Inst{19-16} = Rn;
3767 let Inst{15-12} = 0b1000;
3768 let Inst{11-0} = SYSm;
3772 //===----------------------------------------------------------------------===//
3773 // Move between coprocessor and ARM core register
3776 class t2MovRCopro<bits<4> Op, string opc, bit direction, dag oops, dag iops,
3778 : T2Cop<Op, oops, iops,
3779 !strconcat(opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2"),
3781 let Inst{27-24} = 0b1110;
3782 let Inst{20} = direction;
3792 let Inst{15-12} = Rt;
3793 let Inst{11-8} = cop;
3794 let Inst{23-21} = opc1;
3795 let Inst{7-5} = opc2;
3796 let Inst{3-0} = CRm;
3797 let Inst{19-16} = CRn;
3800 class t2MovRRCopro<bits<4> Op, string opc, bit direction,
3801 list<dag> pattern = []>
3803 (ins p_imm:$cop, imm0_15:$opc1, GPR:$Rt, GPR:$Rt2, c_imm:$CRm),
3804 !strconcat(opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm"), pattern> {
3805 let Inst{27-24} = 0b1100;
3806 let Inst{23-21} = 0b010;
3807 let Inst{20} = direction;
3815 let Inst{15-12} = Rt;
3816 let Inst{19-16} = Rt2;
3817 let Inst{11-8} = cop;
3818 let Inst{7-4} = opc1;
3819 let Inst{3-0} = CRm;
3822 /* from ARM core register to coprocessor */
3823 def t2MCR : t2MovRCopro<0b1110, "mcr", 0,
3825 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
3826 c_imm:$CRm, imm0_7:$opc2),
3827 [(int_arm_mcr imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
3828 imm:$CRm, imm:$opc2)]>;
3829 def : t2InstAlias<"mcr $cop, $opc1, $Rt, $CRn, $CRm",
3830 (t2MCR p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
3832 def t2MCR2 : t2MovRCopro<0b1111, "mcr2", 0,
3833 (outs), (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
3834 c_imm:$CRm, imm0_7:$opc2),
3835 [(int_arm_mcr2 imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
3836 imm:$CRm, imm:$opc2)]>;
3837 def : t2InstAlias<"mcr2 $cop, $opc1, $Rt, $CRn, $CRm",
3838 (t2MCR2 p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
3841 /* from coprocessor to ARM core register */
3842 def t2MRC : t2MovRCopro<0b1110, "mrc", 1,
3843 (outs GPR:$Rt), (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
3844 c_imm:$CRm, imm0_7:$opc2), []>;
3845 def : t2InstAlias<"mrc $cop, $opc1, $Rt, $CRn, $CRm",
3846 (t2MRC GPR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
3849 def t2MRC2 : t2MovRCopro<0b1111, "mrc2", 1,
3850 (outs GPR:$Rt), (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
3851 c_imm:$CRm, imm0_7:$opc2), []>;
3852 def : t2InstAlias<"mrc2 $cop, $opc1, $Rt, $CRn, $CRm",
3853 (t2MRC2 GPR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
3856 def : T2v6Pat<(int_arm_mrc imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2),
3857 (t2MRC imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
3859 def : T2v6Pat<(int_arm_mrc2 imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2),
3860 (t2MRC2 imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
3863 /* from ARM core register to coprocessor */
3864 def t2MCRR : t2MovRRCopro<0b1110, "mcrr", 0,
3865 [(int_arm_mcrr imm:$cop, imm:$opc1, GPR:$Rt, GPR:$Rt2,
3867 def t2MCRR2 : t2MovRRCopro<0b1111, "mcrr2", 0,
3868 [(int_arm_mcrr2 imm:$cop, imm:$opc1, GPR:$Rt,
3869 GPR:$Rt2, imm:$CRm)]>;
3870 /* from coprocessor to ARM core register */
3871 def t2MRRC : t2MovRRCopro<0b1110, "mrrc", 1>;
3873 def t2MRRC2 : t2MovRRCopro<0b1111, "mrrc2", 1>;
3875 //===----------------------------------------------------------------------===//
3876 // Other Coprocessor Instructions.
3879 def tCDP : T2Cop<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1,
3880 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
3881 "cdp\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
3882 [(int_arm_cdp imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
3883 imm:$CRm, imm:$opc2)]> {
3884 let Inst{27-24} = 0b1110;
3893 let Inst{3-0} = CRm;
3895 let Inst{7-5} = opc2;
3896 let Inst{11-8} = cop;
3897 let Inst{15-12} = CRd;
3898 let Inst{19-16} = CRn;
3899 let Inst{23-20} = opc1;
3902 def t2CDP2 : T2Cop<0b1111, (outs), (ins p_imm:$cop, imm0_15:$opc1,
3903 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
3904 "cdp2\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
3905 [(int_arm_cdp2 imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
3906 imm:$CRm, imm:$opc2)]> {
3907 let Inst{27-24} = 0b1110;
3916 let Inst{3-0} = CRm;
3918 let Inst{7-5} = opc2;
3919 let Inst{11-8} = cop;
3920 let Inst{15-12} = CRd;
3921 let Inst{19-16} = CRn;
3922 let Inst{23-20} = opc1;
3927 //===----------------------------------------------------------------------===//
3928 // Non-Instruction Patterns
3931 // SXT/UXT with no rotate
3932 let AddedComplexity = 16 in {
3933 def : T2Pat<(and rGPR:$Rm, 0x000000FF), (t2UXTB rGPR:$Rm, 0)>,
3934 Requires<[IsThumb2]>;
3935 def : T2Pat<(and rGPR:$Rm, 0x0000FFFF), (t2UXTH rGPR:$Rm, 0)>,
3936 Requires<[IsThumb2]>;
3937 def : T2Pat<(and rGPR:$Rm, 0x00FF00FF), (t2UXTB16 rGPR:$Rm, 0)>,
3938 Requires<[HasT2ExtractPack, IsThumb2]>;
3939 def : T2Pat<(add rGPR:$Rn, (and rGPR:$Rm, 0x00FF)),
3940 (t2UXTAB rGPR:$Rn, rGPR:$Rm, 0)>,
3941 Requires<[HasT2ExtractPack, IsThumb2]>;
3942 def : T2Pat<(add rGPR:$Rn, (and rGPR:$Rm, 0xFFFF)),
3943 (t2UXTAH rGPR:$Rn, rGPR:$Rm, 0)>,
3944 Requires<[HasT2ExtractPack, IsThumb2]>;
3947 def : T2Pat<(sext_inreg rGPR:$Src, i8), (t2SXTB rGPR:$Src, 0)>,
3948 Requires<[IsThumb2]>;
3949 def : T2Pat<(sext_inreg rGPR:$Src, i16), (t2SXTH rGPR:$Src, 0)>,
3950 Requires<[IsThumb2]>;
3951 def : T2Pat<(add rGPR:$Rn, (sext_inreg rGPR:$Rm, i8)),
3952 (t2SXTAB rGPR:$Rn, rGPR:$Rm, 0)>,
3953 Requires<[HasT2ExtractPack, IsThumb2]>;
3954 def : T2Pat<(add rGPR:$Rn, (sext_inreg rGPR:$Rm, i16)),
3955 (t2SXTAH rGPR:$Rn, rGPR:$Rm, 0)>,
3956 Requires<[HasT2ExtractPack, IsThumb2]>;
3958 // Atomic load/store patterns
3959 def : T2Pat<(atomic_load_8 t2addrmode_imm12:$addr),
3960 (t2LDRBi12 t2addrmode_imm12:$addr)>;
3961 def : T2Pat<(atomic_load_8 t2addrmode_negimm8:$addr),
3962 (t2LDRBi8 t2addrmode_negimm8:$addr)>;
3963 def : T2Pat<(atomic_load_8 t2addrmode_so_reg:$addr),
3964 (t2LDRBs t2addrmode_so_reg:$addr)>;
3965 def : T2Pat<(atomic_load_16 t2addrmode_imm12:$addr),
3966 (t2LDRHi12 t2addrmode_imm12:$addr)>;
3967 def : T2Pat<(atomic_load_16 t2addrmode_negimm8:$addr),
3968 (t2LDRHi8 t2addrmode_negimm8:$addr)>;
3969 def : T2Pat<(atomic_load_16 t2addrmode_so_reg:$addr),
3970 (t2LDRHs t2addrmode_so_reg:$addr)>;
3971 def : T2Pat<(atomic_load_32 t2addrmode_imm12:$addr),
3972 (t2LDRi12 t2addrmode_imm12:$addr)>;
3973 def : T2Pat<(atomic_load_32 t2addrmode_negimm8:$addr),
3974 (t2LDRi8 t2addrmode_negimm8:$addr)>;
3975 def : T2Pat<(atomic_load_32 t2addrmode_so_reg:$addr),
3976 (t2LDRs t2addrmode_so_reg:$addr)>;
3977 def : T2Pat<(atomic_store_8 t2addrmode_imm12:$addr, GPR:$val),
3978 (t2STRBi12 GPR:$val, t2addrmode_imm12:$addr)>;
3979 def : T2Pat<(atomic_store_8 t2addrmode_negimm8:$addr, GPR:$val),
3980 (t2STRBi8 GPR:$val, t2addrmode_negimm8:$addr)>;
3981 def : T2Pat<(atomic_store_8 t2addrmode_so_reg:$addr, GPR:$val),
3982 (t2STRBs GPR:$val, t2addrmode_so_reg:$addr)>;
3983 def : T2Pat<(atomic_store_16 t2addrmode_imm12:$addr, GPR:$val),
3984 (t2STRHi12 GPR:$val, t2addrmode_imm12:$addr)>;
3985 def : T2Pat<(atomic_store_16 t2addrmode_negimm8:$addr, GPR:$val),
3986 (t2STRHi8 GPR:$val, t2addrmode_negimm8:$addr)>;
3987 def : T2Pat<(atomic_store_16 t2addrmode_so_reg:$addr, GPR:$val),
3988 (t2STRHs GPR:$val, t2addrmode_so_reg:$addr)>;
3989 def : T2Pat<(atomic_store_32 t2addrmode_imm12:$addr, GPR:$val),
3990 (t2STRi12 GPR:$val, t2addrmode_imm12:$addr)>;
3991 def : T2Pat<(atomic_store_32 t2addrmode_negimm8:$addr, GPR:$val),
3992 (t2STRi8 GPR:$val, t2addrmode_negimm8:$addr)>;
3993 def : T2Pat<(atomic_store_32 t2addrmode_so_reg:$addr, GPR:$val),
3994 (t2STRs GPR:$val, t2addrmode_so_reg:$addr)>;
3997 //===----------------------------------------------------------------------===//
3998 // Assembler aliases
4001 // Aliases for ADC without the ".w" optional width specifier.
4002 def : t2InstAlias<"adc${s}${p} $Rd, $Rn, $Rm",
4003 (t2ADCrr rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, pred:$p, cc_out:$s)>;
4004 def : t2InstAlias<"adc${s}${p} $Rd, $Rn, $ShiftedRm",
4005 (t2ADCrs rGPR:$Rd, rGPR:$Rn, t2_so_reg:$ShiftedRm,
4006 pred:$p, cc_out:$s)>;
4008 // Aliases for SBC without the ".w" optional width specifier.
4009 def : t2InstAlias<"sbc${s}${p} $Rd, $Rn, $Rm",
4010 (t2SBCrr rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, pred:$p, cc_out:$s)>;
4011 def : t2InstAlias<"sbc${s}${p} $Rd, $Rn, $ShiftedRm",
4012 (t2SBCrs rGPR:$Rd, rGPR:$Rn, t2_so_reg:$ShiftedRm,
4013 pred:$p, cc_out:$s)>;
4015 // Aliases for ADD without the ".w" optional width specifier.
4016 def : t2InstAlias<"add${s}${p} $Rd, $Rn, $imm",
4017 (t2ADDri GPRnopc:$Rd, GPRnopc:$Rn, t2_so_imm:$imm, pred:$p, cc_out:$s)>;
4018 def : t2InstAlias<"add${p} $Rd, $Rn, $imm",
4019 (t2ADDri12 GPRnopc:$Rd, GPR:$Rn, imm0_4095:$imm, pred:$p)>;
4020 def : t2InstAlias<"add${s}${p} $Rd, $Rn, $Rm",
4021 (t2ADDrr GPRnopc:$Rd, GPRnopc:$Rn, rGPR:$Rm, pred:$p, cc_out:$s)>;
4022 def : t2InstAlias<"add${s}${p} $Rd, $Rn, $ShiftedRm",
4023 (t2ADDrs GPRnopc:$Rd, GPRnopc:$Rn, t2_so_reg:$ShiftedRm,
4024 pred:$p, cc_out:$s)>;
4025 // ... and with the destination and source register combined.
4026 def : t2InstAlias<"add${s}${p} $Rdn, $imm",
4027 (t2ADDri GPRnopc:$Rdn, GPRnopc:$Rdn, t2_so_imm:$imm, pred:$p, cc_out:$s)>;
4028 def : t2InstAlias<"add${p} $Rdn, $imm",
4029 (t2ADDri12 GPRnopc:$Rdn, GPRnopc:$Rdn, imm0_4095:$imm, pred:$p)>;
4030 def : t2InstAlias<"add${s}${p} $Rdn, $Rm",
4031 (t2ADDrr GPRnopc:$Rdn, GPRnopc:$Rdn, rGPR:$Rm, pred:$p, cc_out:$s)>;
4032 def : t2InstAlias<"add${s}${p} $Rdn, $ShiftedRm",
4033 (t2ADDrs GPRnopc:$Rdn, GPRnopc:$Rdn, t2_so_reg:$ShiftedRm,
4034 pred:$p, cc_out:$s)>;
4036 // add w/ negative immediates is just a sub.
4037 def : t2InstAlias<"add${s}${p} $Rd, $Rn, $imm",
4038 (t2SUBri GPRnopc:$Rd, GPRnopc:$Rn, t2_so_imm_neg:$imm, pred:$p,
4040 def : t2InstAlias<"add${p} $Rd, $Rn, $imm",
4041 (t2SUBri12 GPRnopc:$Rd, GPR:$Rn, imm0_4095_neg:$imm, pred:$p)>;
4042 def : t2InstAlias<"add${s}${p} $Rdn, $imm",
4043 (t2SUBri GPRnopc:$Rdn, GPRnopc:$Rdn, t2_so_imm_neg:$imm, pred:$p,
4045 def : t2InstAlias<"add${p} $Rdn, $imm",
4046 (t2SUBri12 GPRnopc:$Rdn, GPRnopc:$Rdn, imm0_4095_neg:$imm, pred:$p)>;
4048 def : t2InstAlias<"add${s}${p}.w $Rd, $Rn, $imm",
4049 (t2SUBri GPRnopc:$Rd, GPRnopc:$Rn, t2_so_imm_neg:$imm, pred:$p,
4051 def : t2InstAlias<"addw${p} $Rd, $Rn, $imm",
4052 (t2SUBri12 GPRnopc:$Rd, GPR:$Rn, imm0_4095_neg:$imm, pred:$p)>;
4053 def : t2InstAlias<"add${s}${p}.w $Rdn, $imm",
4054 (t2SUBri GPRnopc:$Rdn, GPRnopc:$Rdn, t2_so_imm_neg:$imm, pred:$p,
4056 def : t2InstAlias<"addw${p} $Rdn, $imm",
4057 (t2SUBri12 GPRnopc:$Rdn, GPRnopc:$Rdn, imm0_4095_neg:$imm, pred:$p)>;
4060 // Aliases for SUB without the ".w" optional width specifier.
4061 def : t2InstAlias<"sub${s}${p} $Rd, $Rn, $imm",
4062 (t2SUBri GPRnopc:$Rd, GPRnopc:$Rn, t2_so_imm:$imm, pred:$p, cc_out:$s)>;
4063 def : t2InstAlias<"sub${p} $Rd, $Rn, $imm",
4064 (t2SUBri12 GPRnopc:$Rd, GPR:$Rn, imm0_4095:$imm, pred:$p)>;
4065 def : t2InstAlias<"sub${s}${p} $Rd, $Rn, $Rm",
4066 (t2SUBrr GPRnopc:$Rd, GPRnopc:$Rn, rGPR:$Rm, pred:$p, cc_out:$s)>;
4067 def : t2InstAlias<"sub${s}${p} $Rd, $Rn, $ShiftedRm",
4068 (t2SUBrs GPRnopc:$Rd, GPRnopc:$Rn, t2_so_reg:$ShiftedRm,
4069 pred:$p, cc_out:$s)>;
4070 // ... and with the destination and source register combined.
4071 def : t2InstAlias<"sub${s}${p} $Rdn, $imm",
4072 (t2SUBri GPRnopc:$Rdn, GPRnopc:$Rdn, t2_so_imm:$imm, pred:$p, cc_out:$s)>;
4073 def : t2InstAlias<"sub${p} $Rdn, $imm",
4074 (t2SUBri12 GPRnopc:$Rdn, GPRnopc:$Rdn, imm0_4095:$imm, pred:$p)>;
4075 def : t2InstAlias<"sub${s}${p}.w $Rdn, $Rm",
4076 (t2SUBrr GPRnopc:$Rdn, GPRnopc:$Rdn, rGPR:$Rm, pred:$p, cc_out:$s)>;
4077 def : t2InstAlias<"sub${s}${p} $Rdn, $Rm",
4078 (t2SUBrr GPRnopc:$Rdn, GPRnopc:$Rdn, rGPR:$Rm, pred:$p, cc_out:$s)>;
4079 def : t2InstAlias<"sub${s}${p} $Rdn, $ShiftedRm",
4080 (t2SUBrs GPRnopc:$Rdn, GPRnopc:$Rdn, t2_so_reg:$ShiftedRm,
4081 pred:$p, cc_out:$s)>;
4083 // Alias for compares without the ".w" optional width specifier.
4084 def : t2InstAlias<"cmn${p} $Rn, $Rm",
4085 (t2CMNzrr GPRnopc:$Rn, rGPR:$Rm, pred:$p)>;
4086 def : t2InstAlias<"teq${p} $Rn, $Rm",
4087 (t2TEQrr GPRnopc:$Rn, rGPR:$Rm, pred:$p)>;
4088 def : t2InstAlias<"tst${p} $Rn, $Rm",
4089 (t2TSTrr GPRnopc:$Rn, rGPR:$Rm, pred:$p)>;
4092 def : InstAlias<"dmb", (t2DMB 0xf)>, Requires<[IsThumb, HasDB]>;
4093 def : InstAlias<"dsb", (t2DSB 0xf)>, Requires<[IsThumb, HasDB]>;
4094 def : InstAlias<"isb", (t2ISB 0xf)>, Requires<[IsThumb, HasDB]>;
4096 // Alias for LDR, LDRB, LDRH, LDRSB, and LDRSH without the ".w" optional
4098 def : t2InstAlias<"ldr${p} $Rt, $addr",
4099 (t2LDRi12 GPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
4100 def : t2InstAlias<"ldrb${p} $Rt, $addr",
4101 (t2LDRBi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
4102 def : t2InstAlias<"ldrh${p} $Rt, $addr",
4103 (t2LDRHi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
4104 def : t2InstAlias<"ldrsb${p} $Rt, $addr",
4105 (t2LDRSBi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
4106 def : t2InstAlias<"ldrsh${p} $Rt, $addr",
4107 (t2LDRSHi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
4109 def : t2InstAlias<"ldr${p} $Rt, $addr",
4110 (t2LDRs GPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
4111 def : t2InstAlias<"ldrb${p} $Rt, $addr",
4112 (t2LDRBs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
4113 def : t2InstAlias<"ldrh${p} $Rt, $addr",
4114 (t2LDRHs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
4115 def : t2InstAlias<"ldrsb${p} $Rt, $addr",
4116 (t2LDRSBs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
4117 def : t2InstAlias<"ldrsh${p} $Rt, $addr",
4118 (t2LDRSHs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
4120 def : t2InstAlias<"ldr${p} $Rt, $addr",
4121 (t2LDRpci GPR:$Rt, t2ldrlabel:$addr, pred:$p)>;
4122 def : t2InstAlias<"ldrb${p} $Rt, $addr",
4123 (t2LDRBpci rGPR:$Rt, t2ldrlabel:$addr, pred:$p)>;
4124 def : t2InstAlias<"ldrh${p} $Rt, $addr",
4125 (t2LDRHpci rGPR:$Rt, t2ldrlabel:$addr, pred:$p)>;
4126 def : t2InstAlias<"ldrsb${p} $Rt, $addr",
4127 (t2LDRSBpci rGPR:$Rt, t2ldrlabel:$addr, pred:$p)>;
4128 def : t2InstAlias<"ldrsh${p} $Rt, $addr",
4129 (t2LDRSHpci rGPR:$Rt, t2ldrlabel:$addr, pred:$p)>;
4131 // Alias for MVN with(out) the ".w" optional width specifier.
4132 def : t2InstAlias<"mvn${s}${p}.w $Rd, $imm",
4133 (t2MVNi rGPR:$Rd, t2_so_imm:$imm, pred:$p, cc_out:$s)>;
4134 def : t2InstAlias<"mvn${s}${p} $Rd, $Rm",
4135 (t2MVNr rGPR:$Rd, rGPR:$Rm, pred:$p, cc_out:$s)>;
4136 def : t2InstAlias<"mvn${s}${p} $Rd, $ShiftedRm",
4137 (t2MVNs rGPR:$Rd, t2_so_reg:$ShiftedRm, pred:$p, cc_out:$s)>;
4139 // PKHBT/PKHTB with default shift amount. PKHTB is equivalent to PKHBT when the
4140 // shift amount is zero (i.e., unspecified).
4141 def : InstAlias<"pkhbt${p} $Rd, $Rn, $Rm",
4142 (t2PKHBT rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>,
4143 Requires<[HasT2ExtractPack, IsThumb2]>;
4144 def : InstAlias<"pkhtb${p} $Rd, $Rn, $Rm",
4145 (t2PKHBT rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>,
4146 Requires<[HasT2ExtractPack, IsThumb2]>;
4148 // PUSH/POP aliases for STM/LDM
4149 def : t2InstAlias<"push${p}.w $regs", (t2STMDB_UPD SP, pred:$p, reglist:$regs)>;
4150 def : t2InstAlias<"push${p} $regs", (t2STMDB_UPD SP, pred:$p, reglist:$regs)>;
4151 def : t2InstAlias<"pop${p}.w $regs", (t2LDMIA_UPD SP, pred:$p, reglist:$regs)>;
4152 def : t2InstAlias<"pop${p} $regs", (t2LDMIA_UPD SP, pred:$p, reglist:$regs)>;
4154 // STMIA/STMIA_UPD aliases w/o the optional .w suffix
4155 def : t2InstAlias<"stm${p} $Rn, $regs",
4156 (t2STMIA GPR:$Rn, pred:$p, reglist:$regs)>;
4157 def : t2InstAlias<"stm${p} $Rn!, $regs",
4158 (t2STMIA_UPD GPR:$Rn, pred:$p, reglist:$regs)>;
4160 // LDMIA/LDMIA_UPD aliases w/o the optional .w suffix
4161 def : t2InstAlias<"ldm${p} $Rn, $regs",
4162 (t2LDMIA GPR:$Rn, pred:$p, reglist:$regs)>;
4163 def : t2InstAlias<"ldm${p} $Rn!, $regs",
4164 (t2LDMIA_UPD GPR:$Rn, pred:$p, reglist:$regs)>;
4166 // STMDB/STMDB_UPD aliases w/ the optional .w suffix
4167 def : t2InstAlias<"stmdb${p}.w $Rn, $regs",
4168 (t2STMDB GPR:$Rn, pred:$p, reglist:$regs)>;
4169 def : t2InstAlias<"stmdb${p}.w $Rn!, $regs",
4170 (t2STMDB_UPD GPR:$Rn, pred:$p, reglist:$regs)>;
4172 // LDMDB/LDMDB_UPD aliases w/ the optional .w suffix
4173 def : t2InstAlias<"ldmdb${p}.w $Rn, $regs",
4174 (t2LDMDB GPR:$Rn, pred:$p, reglist:$regs)>;
4175 def : t2InstAlias<"ldmdb${p}.w $Rn!, $regs",
4176 (t2LDMDB_UPD GPR:$Rn, pred:$p, reglist:$regs)>;
4178 // Alias for REV/REV16/REVSH without the ".w" optional width specifier.
4179 def : t2InstAlias<"rev${p} $Rd, $Rm", (t2REV rGPR:$Rd, rGPR:$Rm, pred:$p)>;
4180 def : t2InstAlias<"rev16${p} $Rd, $Rm", (t2REV16 rGPR:$Rd, rGPR:$Rm, pred:$p)>;
4181 def : t2InstAlias<"revsh${p} $Rd, $Rm", (t2REVSH rGPR:$Rd, rGPR:$Rm, pred:$p)>;
4184 // Alias for RSB without the ".w" optional width specifier, and with optional
4185 // implied destination register.
4186 def : t2InstAlias<"rsb${s}${p} $Rd, $Rn, $imm",
4187 (t2RSBri rGPR:$Rd, rGPR:$Rn, t2_so_imm:$imm, pred:$p, cc_out:$s)>;
4188 def : t2InstAlias<"rsb${s}${p} $Rdn, $imm",
4189 (t2RSBri rGPR:$Rdn, rGPR:$Rdn, t2_so_imm:$imm, pred:$p, cc_out:$s)>;
4190 def : t2InstAlias<"rsb${s}${p} $Rdn, $Rm",
4191 (t2RSBrr rGPR:$Rdn, rGPR:$Rdn, rGPR:$Rm, pred:$p, cc_out:$s)>;
4192 def : t2InstAlias<"rsb${s}${p} $Rdn, $ShiftedRm",
4193 (t2RSBrs rGPR:$Rdn, rGPR:$Rdn, t2_so_reg:$ShiftedRm, pred:$p,
4196 // SSAT/USAT optional shift operand.
4197 def : t2InstAlias<"ssat${p} $Rd, $sat_imm, $Rn",
4198 (t2SSAT rGPR:$Rd, imm1_32:$sat_imm, rGPR:$Rn, 0, pred:$p)>;
4199 def : t2InstAlias<"usat${p} $Rd, $sat_imm, $Rn",
4200 (t2USAT rGPR:$Rd, imm0_31:$sat_imm, rGPR:$Rn, 0, pred:$p)>;
4202 // STM w/o the .w suffix.
4203 def : t2InstAlias<"stm${p} $Rn, $regs",
4204 (t2STMIA GPR:$Rn, pred:$p, reglist:$regs)>;
4206 // Alias for STR, STRB, and STRH without the ".w" optional
4208 def : t2InstAlias<"str${p} $Rt, $addr",
4209 (t2STRi12 GPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
4210 def : t2InstAlias<"strb${p} $Rt, $addr",
4211 (t2STRBi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
4212 def : t2InstAlias<"strh${p} $Rt, $addr",
4213 (t2STRHi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
4215 def : t2InstAlias<"str${p} $Rt, $addr",
4216 (t2STRs GPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
4217 def : t2InstAlias<"strb${p} $Rt, $addr",
4218 (t2STRBs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
4219 def : t2InstAlias<"strh${p} $Rt, $addr",
4220 (t2STRHs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
4222 // Extend instruction optional rotate operand.
4223 def : t2InstAlias<"sxtab${p} $Rd, $Rn, $Rm",
4224 (t2SXTAB rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>;
4225 def : t2InstAlias<"sxtah${p} $Rd, $Rn, $Rm",
4226 (t2SXTAH rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>;
4227 def : t2InstAlias<"sxtab16${p} $Rd, $Rn, $Rm",
4228 (t2SXTAB16 rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>;
4230 def : t2InstAlias<"sxtb${p} $Rd, $Rm",
4231 (t2SXTB rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
4232 def : t2InstAlias<"sxtb16${p} $Rd, $Rm",
4233 (t2SXTB16 rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
4234 def : t2InstAlias<"sxth${p} $Rd, $Rm",
4235 (t2SXTH rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
4236 def : t2InstAlias<"sxtb${p}.w $Rd, $Rm",
4237 (t2SXTB rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
4238 def : t2InstAlias<"sxth${p}.w $Rd, $Rm",
4239 (t2SXTH rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
4241 def : t2InstAlias<"uxtab${p} $Rd, $Rn, $Rm",
4242 (t2UXTAB rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>;
4243 def : t2InstAlias<"uxtah${p} $Rd, $Rn, $Rm",
4244 (t2UXTAH rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>;
4245 def : t2InstAlias<"uxtab16${p} $Rd, $Rn, $Rm",
4246 (t2UXTAB16 rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>;
4247 def : t2InstAlias<"uxtb${p} $Rd, $Rm",
4248 (t2UXTB rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
4249 def : t2InstAlias<"uxtb16${p} $Rd, $Rm",
4250 (t2UXTB16 rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
4251 def : t2InstAlias<"uxth${p} $Rd, $Rm",
4252 (t2UXTH rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
4254 def : t2InstAlias<"uxtb${p}.w $Rd, $Rm",
4255 (t2UXTB rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
4256 def : t2InstAlias<"uxth${p}.w $Rd, $Rm",
4257 (t2UXTH rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
4259 // Extend instruction w/o the ".w" optional width specifier.
4260 def : t2InstAlias<"uxtb${p} $Rd, $Rm$rot",
4261 (t2UXTB rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>;
4262 def : t2InstAlias<"uxtb16${p} $Rd, $Rm$rot",
4263 (t2UXTB16 rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>;
4264 def : t2InstAlias<"uxth${p} $Rd, $Rm$rot",
4265 (t2UXTH rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>;
4267 def : t2InstAlias<"sxtb${p} $Rd, $Rm$rot",
4268 (t2SXTB rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>;
4269 def : t2InstAlias<"sxtb16${p} $Rd, $Rm$rot",
4270 (t2SXTB16 rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>;
4271 def : t2InstAlias<"sxth${p} $Rd, $Rm$rot",
4272 (t2SXTH rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>;
4275 // "mov Rd, t2_so_imm_not" can be handled via "mvn" in assembly, just like
4277 def : t2InstAlias<"mov${p} $Rd, $imm",
4278 (t2MVNi rGPR:$Rd, t2_so_imm_not:$imm, pred:$p, zero_reg)>;
4279 def : t2InstAlias<"mvn${p} $Rd, $imm",
4280 (t2MOVi rGPR:$Rd, t2_so_imm_not:$imm, pred:$p, zero_reg)>;
4281 // Same for AND <--> BIC
4282 def : t2InstAlias<"bic${s}${p} $Rd, $Rn, $imm",
4283 (t2ANDri rGPR:$Rd, rGPR:$Rn, so_imm_not:$imm,
4284 pred:$p, cc_out:$s)>;
4285 def : t2InstAlias<"bic${s}${p} $Rdn, $imm",
4286 (t2ANDri rGPR:$Rdn, rGPR:$Rdn, so_imm_not:$imm,
4287 pred:$p, cc_out:$s)>;
4288 def : t2InstAlias<"and${s}${p} $Rd, $Rn, $imm",
4289 (t2BICri rGPR:$Rd, rGPR:$Rn, so_imm_not:$imm,
4290 pred:$p, cc_out:$s)>;
4291 def : t2InstAlias<"and${s}${p} $Rdn, $imm",
4292 (t2BICri rGPR:$Rdn, rGPR:$Rdn, so_imm_not:$imm,
4293 pred:$p, cc_out:$s)>;
4294 // Likewise, "add Rd, t2_so_imm_neg" -> sub
4295 def : t2InstAlias<"add${s}${p} $Rd, $Rn, $imm",
4296 (t2SUBri GPRnopc:$Rd, GPRnopc:$Rn, t2_so_imm_neg:$imm,
4297 pred:$p, cc_out:$s)>;
4298 def : t2InstAlias<"add${s}${p} $Rd, $imm",
4299 (t2SUBri GPRnopc:$Rd, GPRnopc:$Rd, t2_so_imm_neg:$imm,
4300 pred:$p, cc_out:$s)>;
4301 // Same for CMP <--> CMN via t2_so_imm_neg
4302 def : t2InstAlias<"cmp${p} $Rd, $imm",
4303 (t2CMNri rGPR:$Rd, t2_so_imm_neg:$imm, pred:$p)>;
4304 def : t2InstAlias<"cmn${p} $Rd, $imm",
4305 (t2CMPri rGPR:$Rd, t2_so_imm_neg:$imm, pred:$p)>;
4308 // Wide 'mul' encoding can be specified with only two operands.
4309 def : t2InstAlias<"mul${p} $Rn, $Rm",
4310 (t2MUL rGPR:$Rn, rGPR:$Rm, rGPR:$Rn, pred:$p)>;
4312 // "neg" is and alias for "rsb rd, rn, #0"
4313 def : t2InstAlias<"neg${s}${p} $Rd, $Rm",
4314 (t2RSBri rGPR:$Rd, rGPR:$Rm, 0, pred:$p, cc_out:$s)>;
4316 // MOV so_reg assembler pseudos. InstAlias isn't expressive enough for
4317 // these, unfortunately.
4318 def t2MOVsi: t2AsmPseudo<"mov${p} $Rd, $shift",
4319 (ins rGPR:$Rd, t2_so_reg:$shift, pred:$p)>;
4320 def t2MOVSsi: t2AsmPseudo<"movs${p} $Rd, $shift",
4321 (ins rGPR:$Rd, t2_so_reg:$shift, pred:$p)>;
4323 def t2MOVsr: t2AsmPseudo<"mov${p} $Rd, $shift",
4324 (ins rGPR:$Rd, so_reg_reg:$shift, pred:$p)>;
4325 def t2MOVSsr: t2AsmPseudo<"movs${p} $Rd, $shift",
4326 (ins rGPR:$Rd, so_reg_reg:$shift, pred:$p)>;
4328 // ADR w/o the .w suffix
4329 def : t2InstAlias<"adr${p} $Rd, $addr",
4330 (t2ADR rGPR:$Rd, t2adrlabel:$addr, pred:$p)>;
4332 // LDR(literal) w/ alternate [pc, #imm] syntax.
4333 def t2LDRpcrel : t2AsmPseudo<"ldr${p} $Rt, $addr",
4334 (ins GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>;
4335 def t2LDRBpcrel : t2AsmPseudo<"ldrb${p} $Rt, $addr",
4336 (ins GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>;
4337 def t2LDRHpcrel : t2AsmPseudo<"ldrh${p} $Rt, $addr",
4338 (ins GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>;
4339 def t2LDRSBpcrel : t2AsmPseudo<"ldrsb${p} $Rt, $addr",
4340 (ins GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>;
4341 def t2LDRSHpcrel : t2AsmPseudo<"ldrsh${p} $Rt, $addr",
4342 (ins GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>;
4343 // Version w/ the .w suffix.
4344 def : t2InstAlias<"ldr${p}.w $Rt, $addr",
4345 (t2LDRpcrel GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>;
4346 def : t2InstAlias<"ldrb${p}.w $Rt, $addr",
4347 (t2LDRBpcrel GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>;
4348 def : t2InstAlias<"ldrh${p}.w $Rt, $addr",
4349 (t2LDRHpcrel GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>;
4350 def : t2InstAlias<"ldrsb${p}.w $Rt, $addr",
4351 (t2LDRSBpcrel GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>;
4352 def : t2InstAlias<"ldrsh${p}.w $Rt, $addr",
4353 (t2LDRSHpcrel GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>;
4355 def : t2InstAlias<"add${p} $Rd, pc, $imm",
4356 (t2ADR rGPR:$Rd, imm0_4095:$imm, pred:$p)>;