1 //===- ARMInstrThumb2.td - Thumb2 support for ARM -------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Thumb2 instruction set.
12 //===----------------------------------------------------------------------===//
14 // IT block predicate field
15 def it_pred_asmoperand : AsmOperandClass {
16 let Name = "ITCondCode";
17 let ParserMethod = "parseITCondCode";
19 def it_pred : Operand<i32> {
20 let PrintMethod = "printMandatoryPredicateOperand";
21 let ParserMatchClass = it_pred_asmoperand;
24 // IT block condition mask
25 def it_mask_asmoperand : AsmOperandClass { let Name = "ITMask"; }
26 def it_mask : Operand<i32> {
27 let PrintMethod = "printThumbITMask";
28 let ParserMatchClass = it_mask_asmoperand;
31 // t2_shift_imm: An integer that encodes a shift amount and the type of shift
32 // (asr or lsl). The 6-bit immediate encodes as:
35 // {4-0} imm5 shift amount.
36 // asr #32 not allowed
37 def t2_shift_imm : Operand<i32> {
38 let PrintMethod = "printShiftImmOperand";
39 let ParserMatchClass = ShifterImmAsmOperand;
40 let DecoderMethod = "DecodeT2ShifterImmOperand";
43 // Shifted operands. No register controlled shifts for Thumb2.
44 // Note: We do not support rrx shifted operands yet.
45 def t2_so_reg : Operand<i32>, // reg imm
46 ComplexPattern<i32, 2, "SelectT2ShifterOperandReg",
48 let EncoderMethod = "getT2SORegOpValue";
49 let PrintMethod = "printT2SOOperand";
50 let DecoderMethod = "DecodeSORegImmOperand";
51 let ParserMatchClass = ShiftedImmAsmOperand;
52 let MIOperandInfo = (ops rGPR, i32imm);
55 // t2_so_imm_not_XFORM - Return the complement of a t2_so_imm value
56 def t2_so_imm_not_XFORM : SDNodeXForm<imm, [{
57 return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), MVT::i32);
60 // t2_so_imm_neg_XFORM - Return the negation of a t2_so_imm value
61 def t2_so_imm_neg_XFORM : SDNodeXForm<imm, [{
62 return CurDAG->getTargetConstant(-((int)N->getZExtValue()), MVT::i32);
65 // t2_so_imm - Match a 32-bit immediate operand, which is an
66 // 8-bit immediate rotated by an arbitrary number of bits, or an 8-bit
67 // immediate splatted into multiple bytes of the word.
68 def t2_so_imm_asmoperand : ImmAsmOperand { let Name = "T2SOImm"; }
69 def t2_so_imm : Operand<i32>, ImmLeaf<i32, [{
70 return ARM_AM::getT2SOImmVal(Imm) != -1;
72 let ParserMatchClass = t2_so_imm_asmoperand;
73 let EncoderMethod = "getT2SOImmOpValue";
74 let DecoderMethod = "DecodeT2SOImm";
77 // t2_so_imm_not - Match an immediate that is a complement
79 // Note: this pattern doesn't require an encoder method and such, as it's
80 // only used on aliases (Pat<> and InstAlias<>). The actual encoding
81 // is handled by the destination instructions, which use t2_so_imm.
82 def t2_so_imm_not_asmoperand : AsmOperandClass { let Name = "T2SOImmNot"; }
83 def t2_so_imm_not : Operand<i32>, PatLeaf<(imm), [{
84 return ARM_AM::getT2SOImmVal(~((uint32_t)N->getZExtValue())) != -1;
85 }], t2_so_imm_not_XFORM> {
86 let ParserMatchClass = t2_so_imm_not_asmoperand;
89 // t2_so_imm_neg - Match an immediate that is a negation of a t2_so_imm.
90 def t2_so_imm_neg_asmoperand : AsmOperandClass { let Name = "T2SOImmNeg"; }
91 def t2_so_imm_neg : Operand<i32>, PatLeaf<(imm), [{
92 return ARM_AM::getT2SOImmVal(-((uint32_t)N->getZExtValue())) != -1;
93 }], t2_so_imm_neg_XFORM> {
94 let ParserMatchClass = t2_so_imm_neg_asmoperand;
97 /// imm0_4095 predicate - True if the 32-bit immediate is in the range [0.4095].
98 def imm0_4095 : Operand<i32>,
100 return Imm >= 0 && Imm < 4096;
103 def imm0_4095_neg : PatLeaf<(i32 imm), [{
104 return (uint32_t)(-N->getZExtValue()) < 4096;
107 def imm0_255_neg : PatLeaf<(i32 imm), [{
108 return (uint32_t)(-N->getZExtValue()) < 255;
111 def imm0_255_not : PatLeaf<(i32 imm), [{
112 return (uint32_t)(~N->getZExtValue()) < 255;
115 def lo5AllOne : PatLeaf<(i32 imm), [{
116 // Returns true if all low 5-bits are 1.
117 return (((uint32_t)N->getZExtValue()) & 0x1FUL) == 0x1FUL;
120 // Define Thumb2 specific addressing modes.
122 // t2addrmode_imm12 := reg + imm12
123 def t2addrmode_imm12_asmoperand : AsmOperandClass {let Name="MemUImm12Offset";}
124 def t2addrmode_imm12 : Operand<i32>,
125 ComplexPattern<i32, 2, "SelectT2AddrModeImm12", []> {
126 let PrintMethod = "printAddrModeImm12Operand";
127 let EncoderMethod = "getAddrModeImm12OpValue";
128 let DecoderMethod = "DecodeT2AddrModeImm12";
129 let ParserMatchClass = t2addrmode_imm12_asmoperand;
130 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
133 // t2ldrlabel := imm12
134 def t2ldrlabel : Operand<i32> {
135 let EncoderMethod = "getAddrModeImm12OpValue";
136 let PrintMethod = "printT2LdrLabelOperand";
140 // ADR instruction labels.
141 def t2adrlabel : Operand<i32> {
142 let EncoderMethod = "getT2AdrLabelOpValue";
146 // t2addrmode_posimm8 := reg + imm8
147 def MemPosImm8OffsetAsmOperand : AsmOperandClass {let Name="MemPosImm8Offset";}
148 def t2addrmode_posimm8 : Operand<i32> {
149 let PrintMethod = "printT2AddrModeImm8Operand";
150 let EncoderMethod = "getT2AddrModeImm8OpValue";
151 let DecoderMethod = "DecodeT2AddrModeImm8";
152 let ParserMatchClass = MemPosImm8OffsetAsmOperand;
153 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
156 // t2addrmode_negimm8 := reg - imm8
157 def MemNegImm8OffsetAsmOperand : AsmOperandClass {let Name="MemNegImm8Offset";}
158 def t2addrmode_negimm8 : Operand<i32>,
159 ComplexPattern<i32, 2, "SelectT2AddrModeImm8", []> {
160 let PrintMethod = "printT2AddrModeImm8Operand";
161 let EncoderMethod = "getT2AddrModeImm8OpValue";
162 let DecoderMethod = "DecodeT2AddrModeImm8";
163 let ParserMatchClass = MemNegImm8OffsetAsmOperand;
164 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
167 // t2addrmode_imm8 := reg +/- imm8
168 def MemImm8OffsetAsmOperand : AsmOperandClass { let Name = "MemImm8Offset"; }
169 def t2addrmode_imm8 : Operand<i32>,
170 ComplexPattern<i32, 2, "SelectT2AddrModeImm8", []> {
171 let PrintMethod = "printT2AddrModeImm8Operand";
172 let EncoderMethod = "getT2AddrModeImm8OpValue";
173 let DecoderMethod = "DecodeT2AddrModeImm8";
174 let ParserMatchClass = MemImm8OffsetAsmOperand;
175 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
178 def t2am_imm8_offset : Operand<i32>,
179 ComplexPattern<i32, 1, "SelectT2AddrModeImm8Offset",
180 [], [SDNPWantRoot]> {
181 let PrintMethod = "printT2AddrModeImm8OffsetOperand";
182 let EncoderMethod = "getT2AddrModeImm8OffsetOpValue";
183 let DecoderMethod = "DecodeT2Imm8";
186 // t2addrmode_imm8s4 := reg +/- (imm8 << 2)
187 def MemImm8s4OffsetAsmOperand : AsmOperandClass {let Name = "MemImm8s4Offset";}
188 def t2addrmode_imm8s4 : Operand<i32> {
189 let PrintMethod = "printT2AddrModeImm8s4Operand";
190 let EncoderMethod = "getT2AddrModeImm8s4OpValue";
191 let DecoderMethod = "DecodeT2AddrModeImm8s4";
192 let ParserMatchClass = MemImm8s4OffsetAsmOperand;
193 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
196 def t2am_imm8s4_offset_asmoperand : AsmOperandClass { let Name = "Imm8s4"; }
197 def t2am_imm8s4_offset : Operand<i32> {
198 let PrintMethod = "printT2AddrModeImm8s4OffsetOperand";
199 let EncoderMethod = "getT2Imm8s4OpValue";
200 let DecoderMethod = "DecodeT2Imm8S4";
203 // t2addrmode_imm0_1020s4 := reg + (imm8 << 2)
204 def MemImm0_1020s4OffsetAsmOperand : AsmOperandClass {
205 let Name = "MemImm0_1020s4Offset";
207 def t2addrmode_imm0_1020s4 : Operand<i32> {
208 let PrintMethod = "printT2AddrModeImm0_1020s4Operand";
209 let EncoderMethod = "getT2AddrModeImm0_1020s4OpValue";
210 let DecoderMethod = "DecodeT2AddrModeImm0_1020s4";
211 let ParserMatchClass = MemImm0_1020s4OffsetAsmOperand;
212 let MIOperandInfo = (ops GPRnopc:$base, i32imm:$offsimm);
215 // t2addrmode_so_reg := reg + (reg << imm2)
216 def t2addrmode_so_reg_asmoperand : AsmOperandClass {let Name="T2MemRegOffset";}
217 def t2addrmode_so_reg : Operand<i32>,
218 ComplexPattern<i32, 3, "SelectT2AddrModeSoReg", []> {
219 let PrintMethod = "printT2AddrModeSoRegOperand";
220 let EncoderMethod = "getT2AddrModeSORegOpValue";
221 let DecoderMethod = "DecodeT2AddrModeSOReg";
222 let ParserMatchClass = t2addrmode_so_reg_asmoperand;
223 let MIOperandInfo = (ops GPR:$base, rGPR:$offsreg, i32imm:$offsimm);
226 // Addresses for the TBB/TBH instructions.
227 def addrmode_tbb_asmoperand : AsmOperandClass { let Name = "MemTBB"; }
228 def addrmode_tbb : Operand<i32> {
229 let PrintMethod = "printAddrModeTBB";
230 let ParserMatchClass = addrmode_tbb_asmoperand;
231 let MIOperandInfo = (ops GPR:$Rn, rGPR:$Rm);
233 def addrmode_tbh_asmoperand : AsmOperandClass { let Name = "MemTBH"; }
234 def addrmode_tbh : Operand<i32> {
235 let PrintMethod = "printAddrModeTBH";
236 let ParserMatchClass = addrmode_tbh_asmoperand;
237 let MIOperandInfo = (ops GPR:$Rn, rGPR:$Rm);
240 //===----------------------------------------------------------------------===//
241 // Multiclass helpers...
245 class T2OneRegImm<dag oops, dag iops, InstrItinClass itin,
246 string opc, string asm, list<dag> pattern>
247 : T2I<oops, iops, itin, opc, asm, pattern> {
252 let Inst{26} = imm{11};
253 let Inst{14-12} = imm{10-8};
254 let Inst{7-0} = imm{7-0};
258 class T2sOneRegImm<dag oops, dag iops, InstrItinClass itin,
259 string opc, string asm, list<dag> pattern>
260 : T2sI<oops, iops, itin, opc, asm, pattern> {
266 let Inst{26} = imm{11};
267 let Inst{14-12} = imm{10-8};
268 let Inst{7-0} = imm{7-0};
271 class T2OneRegCmpImm<dag oops, dag iops, InstrItinClass itin,
272 string opc, string asm, list<dag> pattern>
273 : T2I<oops, iops, itin, opc, asm, pattern> {
277 let Inst{19-16} = Rn;
278 let Inst{26} = imm{11};
279 let Inst{14-12} = imm{10-8};
280 let Inst{7-0} = imm{7-0};
284 class T2OneRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
285 string opc, string asm, list<dag> pattern>
286 : T2I<oops, iops, itin, opc, asm, pattern> {
291 let Inst{3-0} = ShiftedRm{3-0};
292 let Inst{5-4} = ShiftedRm{6-5};
293 let Inst{14-12} = ShiftedRm{11-9};
294 let Inst{7-6} = ShiftedRm{8-7};
297 class T2sOneRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
298 string opc, string asm, list<dag> pattern>
299 : T2sI<oops, iops, itin, opc, asm, pattern> {
304 let Inst{3-0} = ShiftedRm{3-0};
305 let Inst{5-4} = ShiftedRm{6-5};
306 let Inst{14-12} = ShiftedRm{11-9};
307 let Inst{7-6} = ShiftedRm{8-7};
310 class T2OneRegCmpShiftedReg<dag oops, dag iops, InstrItinClass itin,
311 string opc, string asm, list<dag> pattern>
312 : T2I<oops, iops, itin, opc, asm, pattern> {
316 let Inst{19-16} = Rn;
317 let Inst{3-0} = ShiftedRm{3-0};
318 let Inst{5-4} = ShiftedRm{6-5};
319 let Inst{14-12} = ShiftedRm{11-9};
320 let Inst{7-6} = ShiftedRm{8-7};
323 class T2TwoReg<dag oops, dag iops, InstrItinClass itin,
324 string opc, string asm, list<dag> pattern>
325 : T2I<oops, iops, itin, opc, asm, pattern> {
333 class T2sTwoReg<dag oops, dag iops, InstrItinClass itin,
334 string opc, string asm, list<dag> pattern>
335 : T2sI<oops, iops, itin, opc, asm, pattern> {
343 class T2TwoRegCmp<dag oops, dag iops, InstrItinClass itin,
344 string opc, string asm, list<dag> pattern>
345 : T2I<oops, iops, itin, opc, asm, pattern> {
349 let Inst{19-16} = Rn;
354 class T2TwoRegImm<dag oops, dag iops, InstrItinClass itin,
355 string opc, string asm, list<dag> pattern>
356 : T2I<oops, iops, itin, opc, asm, pattern> {
362 let Inst{19-16} = Rn;
363 let Inst{26} = imm{11};
364 let Inst{14-12} = imm{10-8};
365 let Inst{7-0} = imm{7-0};
368 class T2sTwoRegImm<dag oops, dag iops, InstrItinClass itin,
369 string opc, string asm, list<dag> pattern>
370 : T2sI<oops, iops, itin, opc, asm, pattern> {
376 let Inst{19-16} = Rn;
377 let Inst{26} = imm{11};
378 let Inst{14-12} = imm{10-8};
379 let Inst{7-0} = imm{7-0};
382 class T2TwoRegShiftImm<dag oops, dag iops, InstrItinClass itin,
383 string opc, string asm, list<dag> pattern>
384 : T2I<oops, iops, itin, opc, asm, pattern> {
391 let Inst{14-12} = imm{4-2};
392 let Inst{7-6} = imm{1-0};
395 class T2sTwoRegShiftImm<dag oops, dag iops, InstrItinClass itin,
396 string opc, string asm, list<dag> pattern>
397 : T2sI<oops, iops, itin, opc, asm, pattern> {
404 let Inst{14-12} = imm{4-2};
405 let Inst{7-6} = imm{1-0};
408 class T2ThreeReg<dag oops, dag iops, InstrItinClass itin,
409 string opc, string asm, list<dag> pattern>
410 : T2I<oops, iops, itin, opc, asm, pattern> {
416 let Inst{19-16} = Rn;
420 class T2sThreeReg<dag oops, dag iops, InstrItinClass itin,
421 string opc, string asm, list<dag> pattern>
422 : T2sI<oops, iops, itin, opc, asm, pattern> {
428 let Inst{19-16} = Rn;
432 class T2TwoRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
433 string opc, string asm, list<dag> pattern>
434 : T2I<oops, iops, itin, opc, asm, pattern> {
440 let Inst{19-16} = Rn;
441 let Inst{3-0} = ShiftedRm{3-0};
442 let Inst{5-4} = ShiftedRm{6-5};
443 let Inst{14-12} = ShiftedRm{11-9};
444 let Inst{7-6} = ShiftedRm{8-7};
447 class T2sTwoRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
448 string opc, string asm, list<dag> pattern>
449 : T2sI<oops, iops, itin, opc, asm, pattern> {
455 let Inst{19-16} = Rn;
456 let Inst{3-0} = ShiftedRm{3-0};
457 let Inst{5-4} = ShiftedRm{6-5};
458 let Inst{14-12} = ShiftedRm{11-9};
459 let Inst{7-6} = ShiftedRm{8-7};
462 class T2FourReg<dag oops, dag iops, InstrItinClass itin,
463 string opc, string asm, list<dag> pattern>
464 : T2I<oops, iops, itin, opc, asm, pattern> {
470 let Inst{19-16} = Rn;
471 let Inst{15-12} = Ra;
476 class T2MulLong<bits<3> opc22_20, bits<4> opc7_4,
477 dag oops, dag iops, InstrItinClass itin,
478 string opc, string asm, list<dag> pattern>
479 : T2I<oops, iops, itin, opc, asm, pattern> {
485 let Inst{31-23} = 0b111110111;
486 let Inst{22-20} = opc22_20;
487 let Inst{19-16} = Rn;
488 let Inst{15-12} = RdLo;
489 let Inst{11-8} = RdHi;
490 let Inst{7-4} = opc7_4;
495 /// T2I_bin_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a
496 /// binary operation that produces a value. These are predicable and can be
497 /// changed to modify CPSR.
498 multiclass T2I_bin_irs<bits<4> opcod, string opc,
499 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
500 PatFrag opnode, string baseOpc, bit Commutable = 0,
503 def ri : T2sTwoRegImm<
504 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm), iii,
505 opc, "\t$Rd, $Rn, $imm",
506 [(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_imm:$imm))]> {
507 let Inst{31-27} = 0b11110;
509 let Inst{24-21} = opcod;
513 def rr : T2sThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), iir,
514 opc, !strconcat(wide, "\t$Rd, $Rn, $Rm"),
515 [(set rGPR:$Rd, (opnode rGPR:$Rn, rGPR:$Rm))]> {
516 let isCommutable = Commutable;
517 let Inst{31-27} = 0b11101;
518 let Inst{26-25} = 0b01;
519 let Inst{24-21} = opcod;
520 let Inst{14-12} = 0b000; // imm3
521 let Inst{7-6} = 0b00; // imm2
522 let Inst{5-4} = 0b00; // type
525 def rs : T2sTwoRegShiftedReg<
526 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm), iis,
527 opc, !strconcat(wide, "\t$Rd, $Rn, $ShiftedRm"),
528 [(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_reg:$ShiftedRm))]> {
529 let Inst{31-27} = 0b11101;
530 let Inst{26-25} = 0b01;
531 let Inst{24-21} = opcod;
533 // Assembly aliases for optional destination operand when it's the same
534 // as the source operand.
535 def : t2InstAlias<!strconcat(opc, "${s}${p} $Rdn, $imm"),
536 (!cast<Instruction>(!strconcat(baseOpc, "ri")) rGPR:$Rdn, rGPR:$Rdn,
537 t2_so_imm:$imm, pred:$p,
539 def : t2InstAlias<!strconcat(opc, "${s}${p}", wide, " $Rdn, $Rm"),
540 (!cast<Instruction>(!strconcat(baseOpc, "rr")) rGPR:$Rdn, rGPR:$Rdn,
543 def : t2InstAlias<!strconcat(opc, "${s}${p}", wide, " $Rdn, $shift"),
544 (!cast<Instruction>(!strconcat(baseOpc, "rs")) rGPR:$Rdn, rGPR:$Rdn,
545 t2_so_reg:$shift, pred:$p,
549 /// T2I_bin_w_irs - Same as T2I_bin_irs except these operations need
550 // the ".w" suffix to indicate that they are wide.
551 multiclass T2I_bin_w_irs<bits<4> opcod, string opc,
552 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
553 PatFrag opnode, string baseOpc, bit Commutable = 0> :
554 T2I_bin_irs<opcod, opc, iii, iir, iis, opnode, baseOpc, Commutable, ".w"> {
555 // Assembler aliases w/o the ".w" suffix.
556 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rd, $Rn, $Rm"),
557 (!cast<Instruction>(!strconcat(baseOpc, "rr")) rGPR:$Rd, rGPR:$Rn,
560 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rd, $Rn, $shift"),
561 (!cast<Instruction>(!strconcat(baseOpc, "rs")) rGPR:$Rd, rGPR:$Rn,
562 t2_so_reg:$shift, pred:$p,
565 // and with the optional destination operand, too.
566 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rdn, $Rm"),
567 (!cast<Instruction>(!strconcat(baseOpc, "rr")) rGPR:$Rdn, rGPR:$Rdn,
570 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rdn, $shift"),
571 (!cast<Instruction>(!strconcat(baseOpc, "rs")) rGPR:$Rdn, rGPR:$Rdn,
572 t2_so_reg:$shift, pred:$p,
576 /// T2I_rbin_is - Same as T2I_bin_irs except the order of operands are
577 /// reversed. The 'rr' form is only defined for the disassembler; for codegen
578 /// it is equivalent to the T2I_bin_irs counterpart.
579 multiclass T2I_rbin_irs<bits<4> opcod, string opc, PatFrag opnode> {
581 def ri : T2sTwoRegImm<
582 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm), IIC_iALUi,
583 opc, ".w\t$Rd, $Rn, $imm",
584 [(set rGPR:$Rd, (opnode t2_so_imm:$imm, rGPR:$Rn))]> {
585 let Inst{31-27} = 0b11110;
587 let Inst{24-21} = opcod;
591 def rr : T2sThreeReg<
592 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUr,
593 opc, "\t$Rd, $Rn, $Rm",
594 [/* For disassembly only; pattern left blank */]> {
595 let Inst{31-27} = 0b11101;
596 let Inst{26-25} = 0b01;
597 let Inst{24-21} = opcod;
598 let Inst{14-12} = 0b000; // imm3
599 let Inst{7-6} = 0b00; // imm2
600 let Inst{5-4} = 0b00; // type
603 def rs : T2sTwoRegShiftedReg<
604 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm),
605 IIC_iALUsir, opc, "\t$Rd, $Rn, $ShiftedRm",
606 [(set rGPR:$Rd, (opnode t2_so_reg:$ShiftedRm, rGPR:$Rn))]> {
607 let Inst{31-27} = 0b11101;
608 let Inst{26-25} = 0b01;
609 let Inst{24-21} = opcod;
613 /// T2I_bin_s_irs - Similar to T2I_bin_irs except it sets the 's' bit so the
614 /// instruction modifies the CPSR register.
616 /// These opcodes will be converted to the real non-S opcodes by
617 /// AdjustInstrPostInstrSelection after giving then an optional CPSR operand.
618 let hasPostISelHook = 1, Defs = [CPSR] in {
619 multiclass T2I_bin_s_irs<InstrItinClass iii, InstrItinClass iir,
620 InstrItinClass iis, PatFrag opnode,
621 bit Commutable = 0> {
623 def ri : t2PseudoInst<(outs rGPR:$Rd),
624 (ins GPRnopc:$Rn, t2_so_imm:$imm, pred:$p),
626 [(set rGPR:$Rd, CPSR, (opnode GPRnopc:$Rn,
629 def rr : t2PseudoInst<(outs rGPR:$Rd), (ins GPRnopc:$Rn, rGPR:$Rm, pred:$p),
631 [(set rGPR:$Rd, CPSR, (opnode GPRnopc:$Rn,
633 let isCommutable = Commutable;
636 def rs : t2PseudoInst<(outs rGPR:$Rd),
637 (ins GPRnopc:$Rn, t2_so_reg:$ShiftedRm, pred:$p),
639 [(set rGPR:$Rd, CPSR, (opnode GPRnopc:$Rn,
640 t2_so_reg:$ShiftedRm))]>;
644 /// T2I_rbin_s_is - Same as T2I_bin_s_irs, except selection DAG
645 /// operands are reversed.
646 let hasPostISelHook = 1, Defs = [CPSR] in {
647 multiclass T2I_rbin_s_is<PatFrag opnode> {
649 def ri : t2PseudoInst<(outs rGPR:$Rd),
650 (ins GPRnopc:$Rn, t2_so_imm:$imm, pred:$p),
652 [(set rGPR:$Rd, CPSR, (opnode t2_so_imm:$imm,
655 def rs : t2PseudoInst<(outs rGPR:$Rd),
656 (ins GPRnopc:$Rn, t2_so_reg:$ShiftedRm, pred:$p),
658 [(set rGPR:$Rd, CPSR, (opnode t2_so_reg:$ShiftedRm,
663 /// T2I_bin_ii12rs - Defines a set of (op reg, {so_imm|imm0_4095|r|so_reg})
664 /// patterns for a binary operation that produces a value.
665 multiclass T2I_bin_ii12rs<bits<3> op23_21, string opc, PatFrag opnode,
666 bit Commutable = 0> {
668 // The register-immediate version is re-materializable. This is useful
669 // in particular for taking the address of a local.
670 let isReMaterializable = 1 in {
671 def ri : T2sTwoRegImm<
672 (outs GPRnopc:$Rd), (ins GPRnopc:$Rn, t2_so_imm:$imm), IIC_iALUi,
673 opc, ".w\t$Rd, $Rn, $imm",
674 [(set GPRnopc:$Rd, (opnode GPRnopc:$Rn, t2_so_imm:$imm))]> {
675 let Inst{31-27} = 0b11110;
678 let Inst{23-21} = op23_21;
684 (outs GPRnopc:$Rd), (ins GPR:$Rn, imm0_4095:$imm), IIC_iALUi,
685 !strconcat(opc, "w"), "\t$Rd, $Rn, $imm",
686 [(set GPRnopc:$Rd, (opnode GPR:$Rn, imm0_4095:$imm))]> {
690 let Inst{31-27} = 0b11110;
691 let Inst{26} = imm{11};
692 let Inst{25-24} = 0b10;
693 let Inst{23-21} = op23_21;
694 let Inst{20} = 0; // The S bit.
695 let Inst{19-16} = Rn;
697 let Inst{14-12} = imm{10-8};
699 let Inst{7-0} = imm{7-0};
702 def rr : T2sThreeReg<(outs GPRnopc:$Rd), (ins GPRnopc:$Rn, rGPR:$Rm),
703 IIC_iALUr, opc, ".w\t$Rd, $Rn, $Rm",
704 [(set GPRnopc:$Rd, (opnode GPRnopc:$Rn, rGPR:$Rm))]> {
705 let isCommutable = Commutable;
706 let Inst{31-27} = 0b11101;
707 let Inst{26-25} = 0b01;
709 let Inst{23-21} = op23_21;
710 let Inst{14-12} = 0b000; // imm3
711 let Inst{7-6} = 0b00; // imm2
712 let Inst{5-4} = 0b00; // type
715 def rs : T2sTwoRegShiftedReg<
716 (outs GPRnopc:$Rd), (ins GPRnopc:$Rn, t2_so_reg:$ShiftedRm),
717 IIC_iALUsi, opc, ".w\t$Rd, $Rn, $ShiftedRm",
718 [(set GPRnopc:$Rd, (opnode GPRnopc:$Rn, t2_so_reg:$ShiftedRm))]> {
719 let Inst{31-27} = 0b11101;
720 let Inst{26-25} = 0b01;
722 let Inst{23-21} = op23_21;
726 /// T2I_adde_sube_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns
727 /// for a binary operation that produces a value and use the carry
728 /// bit. It's not predicable.
729 let Defs = [CPSR], Uses = [CPSR] in {
730 multiclass T2I_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
731 bit Commutable = 0> {
733 def ri : T2sTwoRegImm<(outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm),
734 IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
735 [(set rGPR:$Rd, CPSR, (opnode rGPR:$Rn, t2_so_imm:$imm, CPSR))]>,
736 Requires<[IsThumb2]> {
737 let Inst{31-27} = 0b11110;
739 let Inst{24-21} = opcod;
743 def rr : T2sThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUr,
744 opc, ".w\t$Rd, $Rn, $Rm",
745 [(set rGPR:$Rd, CPSR, (opnode rGPR:$Rn, rGPR:$Rm, CPSR))]>,
746 Requires<[IsThumb2]> {
747 let isCommutable = Commutable;
748 let Inst{31-27} = 0b11101;
749 let Inst{26-25} = 0b01;
750 let Inst{24-21} = opcod;
751 let Inst{14-12} = 0b000; // imm3
752 let Inst{7-6} = 0b00; // imm2
753 let Inst{5-4} = 0b00; // type
756 def rs : T2sTwoRegShiftedReg<
757 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm),
758 IIC_iALUsi, opc, ".w\t$Rd, $Rn, $ShiftedRm",
759 [(set rGPR:$Rd, CPSR, (opnode rGPR:$Rn, t2_so_reg:$ShiftedRm, CPSR))]>,
760 Requires<[IsThumb2]> {
761 let Inst{31-27} = 0b11101;
762 let Inst{26-25} = 0b01;
763 let Inst{24-21} = opcod;
768 /// T2I_sh_ir - Defines a set of (op reg, {so_imm|r}) patterns for a shift /
769 // rotate operation that produces a value.
770 multiclass T2I_sh_ir<bits<2> opcod, string opc, Operand ty, PatFrag opnode,
773 def ri : T2sTwoRegShiftImm<
774 (outs rGPR:$Rd), (ins rGPR:$Rm, ty:$imm), IIC_iMOVsi,
775 opc, ".w\t$Rd, $Rm, $imm",
776 [(set rGPR:$Rd, (opnode rGPR:$Rm, (i32 ty:$imm)))]> {
777 let Inst{31-27} = 0b11101;
778 let Inst{26-21} = 0b010010;
779 let Inst{19-16} = 0b1111; // Rn
780 let Inst{5-4} = opcod;
783 def rr : T2sThreeReg<
784 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMOVsr,
785 opc, ".w\t$Rd, $Rn, $Rm",
786 [(set rGPR:$Rd, (opnode rGPR:$Rn, rGPR:$Rm))]> {
787 let Inst{31-27} = 0b11111;
788 let Inst{26-23} = 0b0100;
789 let Inst{22-21} = opcod;
790 let Inst{15-12} = 0b1111;
791 let Inst{7-4} = 0b0000;
794 // Optional destination register
795 def : t2InstAlias<!strconcat(opc, "${s}${p}", ".w $Rdn, $imm"),
796 (!cast<Instruction>(!strconcat(baseOpc, "ri")) rGPR:$Rdn, rGPR:$Rdn,
799 def : t2InstAlias<!strconcat(opc, "${s}${p}", ".w $Rdn, $Rm"),
800 (!cast<Instruction>(!strconcat(baseOpc, "rr")) rGPR:$Rdn, rGPR:$Rdn,
804 // Assembler aliases w/o the ".w" suffix.
805 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rd, $Rn, $imm"),
806 (!cast<Instruction>(!strconcat(baseOpc, "ri")) rGPR:$Rd, rGPR:$Rn,
809 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rd, $Rn, $Rm"),
810 (!cast<Instruction>(!strconcat(baseOpc, "rr")) rGPR:$Rd, rGPR:$Rn,
814 // and with the optional destination operand, too.
815 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rdn, $imm"),
816 (!cast<Instruction>(!strconcat(baseOpc, "ri")) rGPR:$Rdn, rGPR:$Rdn,
819 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rdn, $Rm"),
820 (!cast<Instruction>(!strconcat(baseOpc, "rr")) rGPR:$Rdn, rGPR:$Rdn,
825 /// T2I_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
826 /// patterns. Similar to T2I_bin_irs except the instruction does not produce
827 /// a explicit result, only implicitly set CPSR.
828 multiclass T2I_cmp_irs<bits<4> opcod, string opc,
829 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
830 PatFrag opnode, string baseOpc> {
831 let isCompare = 1, Defs = [CPSR] in {
833 def ri : T2OneRegCmpImm<
834 (outs), (ins GPRnopc:$Rn, t2_so_imm:$imm), iii,
835 opc, ".w\t$Rn, $imm",
836 [(opnode GPRnopc:$Rn, t2_so_imm:$imm)]> {
837 let Inst{31-27} = 0b11110;
839 let Inst{24-21} = opcod;
840 let Inst{20} = 1; // The S bit.
842 let Inst{11-8} = 0b1111; // Rd
845 def rr : T2TwoRegCmp<
846 (outs), (ins GPRnopc:$Rn, rGPR:$Rm), iir,
848 [(opnode GPRnopc:$Rn, rGPR:$Rm)]> {
849 let Inst{31-27} = 0b11101;
850 let Inst{26-25} = 0b01;
851 let Inst{24-21} = opcod;
852 let Inst{20} = 1; // The S bit.
853 let Inst{14-12} = 0b000; // imm3
854 let Inst{11-8} = 0b1111; // Rd
855 let Inst{7-6} = 0b00; // imm2
856 let Inst{5-4} = 0b00; // type
859 def rs : T2OneRegCmpShiftedReg<
860 (outs), (ins GPRnopc:$Rn, t2_so_reg:$ShiftedRm), iis,
861 opc, ".w\t$Rn, $ShiftedRm",
862 [(opnode GPRnopc:$Rn, t2_so_reg:$ShiftedRm)]> {
863 let Inst{31-27} = 0b11101;
864 let Inst{26-25} = 0b01;
865 let Inst{24-21} = opcod;
866 let Inst{20} = 1; // The S bit.
867 let Inst{11-8} = 0b1111; // Rd
871 // Assembler aliases w/o the ".w" suffix.
872 // No alias here for 'rr' version as not all instantiations of this
873 // multiclass want one (CMP in particular, does not).
874 def : t2InstAlias<!strconcat(opc, "${p}", " $Rn, $imm"),
875 (!cast<Instruction>(!strconcat(baseOpc, "ri")) GPRnopc:$Rn,
876 t2_so_imm:$imm, pred:$p)>;
877 def : t2InstAlias<!strconcat(opc, "${p}", " $Rn, $shift"),
878 (!cast<Instruction>(!strconcat(baseOpc, "rs")) GPRnopc:$Rn,
883 /// T2I_ld - Defines a set of (op r, {imm12|imm8|so_reg}) load patterns.
884 multiclass T2I_ld<bit signed, bits<2> opcod, string opc,
885 InstrItinClass iii, InstrItinClass iis, RegisterClass target,
887 def i12 : T2Ii12<(outs target:$Rt), (ins t2addrmode_imm12:$addr), iii,
888 opc, ".w\t$Rt, $addr",
889 [(set target:$Rt, (opnode t2addrmode_imm12:$addr))]> {
892 let Inst{31-25} = 0b1111100;
893 let Inst{24} = signed;
895 let Inst{22-21} = opcod;
896 let Inst{20} = 1; // load
897 let Inst{19-16} = addr{16-13}; // Rn
898 let Inst{15-12} = Rt;
899 let Inst{11-0} = addr{11-0}; // imm
901 def i8 : T2Ii8 <(outs target:$Rt), (ins t2addrmode_negimm8:$addr), iii,
903 [(set target:$Rt, (opnode t2addrmode_negimm8:$addr))]> {
906 let Inst{31-27} = 0b11111;
907 let Inst{26-25} = 0b00;
908 let Inst{24} = signed;
910 let Inst{22-21} = opcod;
911 let Inst{20} = 1; // load
912 let Inst{19-16} = addr{12-9}; // Rn
913 let Inst{15-12} = Rt;
915 // Offset: index==TRUE, wback==FALSE
916 let Inst{10} = 1; // The P bit.
917 let Inst{9} = addr{8}; // U
918 let Inst{8} = 0; // The W bit.
919 let Inst{7-0} = addr{7-0}; // imm
921 def s : T2Iso <(outs target:$Rt), (ins t2addrmode_so_reg:$addr), iis,
922 opc, ".w\t$Rt, $addr",
923 [(set target:$Rt, (opnode t2addrmode_so_reg:$addr))]> {
924 let Inst{31-27} = 0b11111;
925 let Inst{26-25} = 0b00;
926 let Inst{24} = signed;
928 let Inst{22-21} = opcod;
929 let Inst{20} = 1; // load
930 let Inst{11-6} = 0b000000;
933 let Inst{15-12} = Rt;
936 let Inst{19-16} = addr{9-6}; // Rn
937 let Inst{3-0} = addr{5-2}; // Rm
938 let Inst{5-4} = addr{1-0}; // imm
940 let DecoderMethod = "DecodeT2LoadShift";
943 // pci variant is very similar to i12, but supports negative offsets
945 def pci : T2Ipc <(outs target:$Rt), (ins t2ldrlabel:$addr), iii,
946 opc, ".w\t$Rt, $addr",
947 [(set target:$Rt, (opnode (ARMWrapper tconstpool:$addr)))]> {
948 let isReMaterializable = 1;
949 let Inst{31-27} = 0b11111;
950 let Inst{26-25} = 0b00;
951 let Inst{24} = signed;
952 let Inst{23} = ?; // add = (U == '1')
953 let Inst{22-21} = opcod;
954 let Inst{20} = 1; // load
955 let Inst{19-16} = 0b1111; // Rn
958 let Inst{15-12} = Rt{3-0};
959 let Inst{11-0} = addr{11-0};
963 /// T2I_st - Defines a set of (op r, {imm12|imm8|so_reg}) store patterns.
964 multiclass T2I_st<bits<2> opcod, string opc,
965 InstrItinClass iii, InstrItinClass iis, RegisterClass target,
967 def i12 : T2Ii12<(outs), (ins target:$Rt, t2addrmode_imm12:$addr), iii,
968 opc, ".w\t$Rt, $addr",
969 [(opnode target:$Rt, t2addrmode_imm12:$addr)]> {
970 let Inst{31-27} = 0b11111;
971 let Inst{26-23} = 0b0001;
972 let Inst{22-21} = opcod;
973 let Inst{20} = 0; // !load
976 let Inst{15-12} = Rt;
979 let addr{12} = 1; // add = TRUE
980 let Inst{19-16} = addr{16-13}; // Rn
981 let Inst{23} = addr{12}; // U
982 let Inst{11-0} = addr{11-0}; // imm
984 def i8 : T2Ii8 <(outs), (ins target:$Rt, t2addrmode_negimm8:$addr), iii,
986 [(opnode target:$Rt, t2addrmode_negimm8:$addr)]> {
987 let Inst{31-27} = 0b11111;
988 let Inst{26-23} = 0b0000;
989 let Inst{22-21} = opcod;
990 let Inst{20} = 0; // !load
992 // Offset: index==TRUE, wback==FALSE
993 let Inst{10} = 1; // The P bit.
994 let Inst{8} = 0; // The W bit.
997 let Inst{15-12} = Rt;
1000 let Inst{19-16} = addr{12-9}; // Rn
1001 let Inst{9} = addr{8}; // U
1002 let Inst{7-0} = addr{7-0}; // imm
1004 def s : T2Iso <(outs), (ins target:$Rt, t2addrmode_so_reg:$addr), iis,
1005 opc, ".w\t$Rt, $addr",
1006 [(opnode target:$Rt, t2addrmode_so_reg:$addr)]> {
1007 let Inst{31-27} = 0b11111;
1008 let Inst{26-23} = 0b0000;
1009 let Inst{22-21} = opcod;
1010 let Inst{20} = 0; // !load
1011 let Inst{11-6} = 0b000000;
1014 let Inst{15-12} = Rt;
1017 let Inst{19-16} = addr{9-6}; // Rn
1018 let Inst{3-0} = addr{5-2}; // Rm
1019 let Inst{5-4} = addr{1-0}; // imm
1023 /// T2I_ext_rrot - A unary operation with two forms: one whose operand is a
1024 /// register and one whose operand is a register rotated by 8/16/24.
1025 class T2I_ext_rrot<bits<3> opcod, string opc, PatFrag opnode>
1026 : T2TwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm, rot_imm:$rot), IIC_iEXTr,
1027 opc, ".w\t$Rd, $Rm$rot",
1028 [(set rGPR:$Rd, (opnode (rotr rGPR:$Rm, rot_imm:$rot)))]>,
1029 Requires<[IsThumb2]> {
1030 let Inst{31-27} = 0b11111;
1031 let Inst{26-23} = 0b0100;
1032 let Inst{22-20} = opcod;
1033 let Inst{19-16} = 0b1111; // Rn
1034 let Inst{15-12} = 0b1111;
1038 let Inst{5-4} = rot{1-0}; // rotate
1041 // UXTB16 - Requres T2ExtractPack, does not need the .w qualifier.
1042 class T2I_ext_rrot_uxtb16<bits<3> opcod, string opc, PatFrag opnode>
1043 : T2TwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm, rot_imm:$rot),
1044 IIC_iEXTr, opc, "\t$Rd, $Rm$rot",
1045 [(set rGPR:$Rd, (opnode (rotr rGPR:$Rm, rot_imm:$rot)))]>,
1046 Requires<[HasT2ExtractPack, IsThumb2]> {
1048 let Inst{31-27} = 0b11111;
1049 let Inst{26-23} = 0b0100;
1050 let Inst{22-20} = opcod;
1051 let Inst{19-16} = 0b1111; // Rn
1052 let Inst{15-12} = 0b1111;
1054 let Inst{5-4} = rot;
1057 // SXTB16 - Requres T2ExtractPack, does not need the .w qualifier, no pattern
1059 class T2I_ext_rrot_sxtb16<bits<3> opcod, string opc>
1060 : T2TwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm, rot_imm:$rot), IIC_iEXTr,
1061 opc, "\t$Rd, $Rm$rot", []>,
1062 Requires<[IsThumb2, HasT2ExtractPack]> {
1064 let Inst{31-27} = 0b11111;
1065 let Inst{26-23} = 0b0100;
1066 let Inst{22-20} = opcod;
1067 let Inst{19-16} = 0b1111; // Rn
1068 let Inst{15-12} = 0b1111;
1070 let Inst{5-4} = rot;
1073 /// T2I_exta_rrot - A binary operation with two forms: one whose operand is a
1074 /// register and one whose operand is a register rotated by 8/16/24.
1075 class T2I_exta_rrot<bits<3> opcod, string opc, PatFrag opnode>
1076 : T2ThreeReg<(outs rGPR:$Rd),
1077 (ins rGPR:$Rn, rGPR:$Rm, rot_imm:$rot),
1078 IIC_iEXTAsr, opc, "\t$Rd, $Rn, $Rm$rot",
1079 [(set rGPR:$Rd, (opnode rGPR:$Rn, (rotr rGPR:$Rm,rot_imm:$rot)))]>,
1080 Requires<[HasT2ExtractPack, IsThumb2]> {
1082 let Inst{31-27} = 0b11111;
1083 let Inst{26-23} = 0b0100;
1084 let Inst{22-20} = opcod;
1085 let Inst{15-12} = 0b1111;
1087 let Inst{5-4} = rot;
1090 class T2I_exta_rrot_np<bits<3> opcod, string opc>
1091 : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm,rot_imm:$rot),
1092 IIC_iEXTAsr, opc, "\t$Rd, $Rn, $Rm$rot", []> {
1094 let Inst{31-27} = 0b11111;
1095 let Inst{26-23} = 0b0100;
1096 let Inst{22-20} = opcod;
1097 let Inst{15-12} = 0b1111;
1099 let Inst{5-4} = rot;
1102 //===----------------------------------------------------------------------===//
1104 //===----------------------------------------------------------------------===//
1106 //===----------------------------------------------------------------------===//
1107 // Miscellaneous Instructions.
1110 class T2PCOneRegImm<dag oops, dag iops, InstrItinClass itin,
1111 string asm, list<dag> pattern>
1112 : T2XI<oops, iops, itin, asm, pattern> {
1116 let Inst{11-8} = Rd;
1117 let Inst{26} = label{11};
1118 let Inst{14-12} = label{10-8};
1119 let Inst{7-0} = label{7-0};
1122 // LEApcrel - Load a pc-relative address into a register without offending the
1124 def t2ADR : T2PCOneRegImm<(outs rGPR:$Rd),
1125 (ins t2adrlabel:$addr, pred:$p),
1126 IIC_iALUi, "adr{$p}.w\t$Rd, $addr", []> {
1127 let Inst{31-27} = 0b11110;
1128 let Inst{25-24} = 0b10;
1129 // Inst{23:21} = '11' (add = FALSE) or '00' (add = TRUE)
1132 let Inst{19-16} = 0b1111; // Rn
1137 let Inst{11-8} = Rd;
1138 let Inst{23} = addr{12};
1139 let Inst{21} = addr{12};
1140 let Inst{26} = addr{11};
1141 let Inst{14-12} = addr{10-8};
1142 let Inst{7-0} = addr{7-0};
1144 let DecoderMethod = "DecodeT2Adr";
1147 let neverHasSideEffects = 1, isReMaterializable = 1 in
1148 def t2LEApcrel : t2PseudoInst<(outs rGPR:$Rd), (ins i32imm:$label, pred:$p),
1150 def t2LEApcrelJT : t2PseudoInst<(outs rGPR:$Rd),
1151 (ins i32imm:$label, nohash_imm:$id, pred:$p),
1156 //===----------------------------------------------------------------------===//
1157 // Load / store Instructions.
1161 let canFoldAsLoad = 1, isReMaterializable = 1 in
1162 defm t2LDR : T2I_ld<0, 0b10, "ldr", IIC_iLoad_i, IIC_iLoad_si, GPR,
1163 UnOpFrag<(load node:$Src)>>;
1165 // Loads with zero extension
1166 defm t2LDRH : T2I_ld<0, 0b01, "ldrh", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
1167 rGPR, UnOpFrag<(zextloadi16 node:$Src)>>;
1168 defm t2LDRB : T2I_ld<0, 0b00, "ldrb", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
1169 rGPR, UnOpFrag<(zextloadi8 node:$Src)>>;
1171 // Loads with sign extension
1172 defm t2LDRSH : T2I_ld<1, 0b01, "ldrsh", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
1173 rGPR, UnOpFrag<(sextloadi16 node:$Src)>>;
1174 defm t2LDRSB : T2I_ld<1, 0b00, "ldrsb", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
1175 rGPR, UnOpFrag<(sextloadi8 node:$Src)>>;
1177 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
1179 def t2LDRDi8 : T2Ii8s4<1, 0, 1, (outs rGPR:$Rt, rGPR:$Rt2),
1180 (ins t2addrmode_imm8s4:$addr),
1181 IIC_iLoad_d_i, "ldrd", "\t$Rt, $Rt2, $addr", "", []>;
1182 } // mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1
1184 // zextload i1 -> zextload i8
1185 def : T2Pat<(zextloadi1 t2addrmode_imm12:$addr),
1186 (t2LDRBi12 t2addrmode_imm12:$addr)>;
1187 def : T2Pat<(zextloadi1 t2addrmode_negimm8:$addr),
1188 (t2LDRBi8 t2addrmode_negimm8:$addr)>;
1189 def : T2Pat<(zextloadi1 t2addrmode_so_reg:$addr),
1190 (t2LDRBs t2addrmode_so_reg:$addr)>;
1191 def : T2Pat<(zextloadi1 (ARMWrapper tconstpool:$addr)),
1192 (t2LDRBpci tconstpool:$addr)>;
1194 // extload -> zextload
1195 // FIXME: Reduce the number of patterns by legalizing extload to zextload
1197 def : T2Pat<(extloadi1 t2addrmode_imm12:$addr),
1198 (t2LDRBi12 t2addrmode_imm12:$addr)>;
1199 def : T2Pat<(extloadi1 t2addrmode_negimm8:$addr),
1200 (t2LDRBi8 t2addrmode_negimm8:$addr)>;
1201 def : T2Pat<(extloadi1 t2addrmode_so_reg:$addr),
1202 (t2LDRBs t2addrmode_so_reg:$addr)>;
1203 def : T2Pat<(extloadi1 (ARMWrapper tconstpool:$addr)),
1204 (t2LDRBpci tconstpool:$addr)>;
1206 def : T2Pat<(extloadi8 t2addrmode_imm12:$addr),
1207 (t2LDRBi12 t2addrmode_imm12:$addr)>;
1208 def : T2Pat<(extloadi8 t2addrmode_negimm8:$addr),
1209 (t2LDRBi8 t2addrmode_negimm8:$addr)>;
1210 def : T2Pat<(extloadi8 t2addrmode_so_reg:$addr),
1211 (t2LDRBs t2addrmode_so_reg:$addr)>;
1212 def : T2Pat<(extloadi8 (ARMWrapper tconstpool:$addr)),
1213 (t2LDRBpci tconstpool:$addr)>;
1215 def : T2Pat<(extloadi16 t2addrmode_imm12:$addr),
1216 (t2LDRHi12 t2addrmode_imm12:$addr)>;
1217 def : T2Pat<(extloadi16 t2addrmode_negimm8:$addr),
1218 (t2LDRHi8 t2addrmode_negimm8:$addr)>;
1219 def : T2Pat<(extloadi16 t2addrmode_so_reg:$addr),
1220 (t2LDRHs t2addrmode_so_reg:$addr)>;
1221 def : T2Pat<(extloadi16 (ARMWrapper tconstpool:$addr)),
1222 (t2LDRHpci tconstpool:$addr)>;
1224 // FIXME: The destination register of the loads and stores can't be PC, but
1225 // can be SP. We need another regclass (similar to rGPR) to represent
1226 // that. Not a pressing issue since these are selected manually,
1231 let mayLoad = 1, neverHasSideEffects = 1 in {
1232 def t2LDR_PRE : T2Ipreldst<0, 0b10, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1233 (ins t2addrmode_imm8:$addr),
1234 AddrModeT2_i8, IndexModePre, IIC_iLoad_iu,
1235 "ldr", "\t$Rt, $addr!", "$addr.base = $Rn_wb",
1237 let AsmMatchConverter = "cvtLdWriteBackRegT2AddrModeImm8";
1240 def t2LDR_POST : T2Ipostldst<0, 0b10, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1241 (ins addr_offset_none:$Rn, t2am_imm8_offset:$offset),
1242 AddrModeT2_i8, IndexModePost, IIC_iLoad_iu,
1243 "ldr", "\t$Rt, $Rn$offset", "$Rn = $Rn_wb", []>;
1245 def t2LDRB_PRE : T2Ipreldst<0, 0b00, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1246 (ins t2addrmode_imm8:$addr),
1247 AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
1248 "ldrb", "\t$Rt, $addr!", "$addr.base = $Rn_wb",
1250 let AsmMatchConverter = "cvtLdWriteBackRegT2AddrModeImm8";
1252 def t2LDRB_POST : T2Ipostldst<0, 0b00, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1253 (ins addr_offset_none:$Rn, t2am_imm8_offset:$offset),
1254 AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
1255 "ldrb", "\t$Rt, $Rn$offset", "$Rn = $Rn_wb", []>;
1257 def t2LDRH_PRE : T2Ipreldst<0, 0b01, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1258 (ins t2addrmode_imm8:$addr),
1259 AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
1260 "ldrh", "\t$Rt, $addr!", "$addr.base = $Rn_wb",
1262 let AsmMatchConverter = "cvtLdWriteBackRegT2AddrModeImm8";
1264 def t2LDRH_POST : T2Ipostldst<0, 0b01, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1265 (ins addr_offset_none:$Rn, t2am_imm8_offset:$offset),
1266 AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
1267 "ldrh", "\t$Rt, $Rn$offset", "$Rn = $Rn_wb", []>;
1269 def t2LDRSB_PRE : T2Ipreldst<1, 0b00, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1270 (ins t2addrmode_imm8:$addr),
1271 AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
1272 "ldrsb", "\t$Rt, $addr!", "$addr.base = $Rn_wb",
1274 let AsmMatchConverter = "cvtLdWriteBackRegT2AddrModeImm8";
1276 def t2LDRSB_POST : T2Ipostldst<1, 0b00, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1277 (ins addr_offset_none:$Rn, t2am_imm8_offset:$offset),
1278 AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
1279 "ldrsb", "\t$Rt, $Rn$offset", "$Rn = $Rn_wb", []>;
1281 def t2LDRSH_PRE : T2Ipreldst<1, 0b01, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1282 (ins t2addrmode_imm8:$addr),
1283 AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
1284 "ldrsh", "\t$Rt, $addr!", "$addr.base = $Rn_wb",
1286 let AsmMatchConverter = "cvtLdWriteBackRegT2AddrModeImm8";
1288 def t2LDRSH_POST : T2Ipostldst<1, 0b01, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1289 (ins addr_offset_none:$Rn, t2am_imm8_offset:$offset),
1290 AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
1291 "ldrsh", "\t$Rt, $Rn$offset", "$Rn = $Rn_wb", []>;
1292 } // mayLoad = 1, neverHasSideEffects = 1
1294 // LDRT, LDRBT, LDRHT, LDRSBT, LDRSHT all have offset mode (PUW=0b110).
1295 // Ref: A8.6.57 LDR (immediate, Thumb) Encoding T4
1296 class T2IldT<bit signed, bits<2> type, string opc, InstrItinClass ii>
1297 : T2Ii8<(outs rGPR:$Rt), (ins t2addrmode_posimm8:$addr), ii, opc,
1298 "\t$Rt, $addr", []> {
1301 let Inst{31-27} = 0b11111;
1302 let Inst{26-25} = 0b00;
1303 let Inst{24} = signed;
1305 let Inst{22-21} = type;
1306 let Inst{20} = 1; // load
1307 let Inst{19-16} = addr{12-9};
1308 let Inst{15-12} = Rt;
1310 let Inst{10-8} = 0b110; // PUW.
1311 let Inst{7-0} = addr{7-0};
1314 def t2LDRT : T2IldT<0, 0b10, "ldrt", IIC_iLoad_i>;
1315 def t2LDRBT : T2IldT<0, 0b00, "ldrbt", IIC_iLoad_bh_i>;
1316 def t2LDRHT : T2IldT<0, 0b01, "ldrht", IIC_iLoad_bh_i>;
1317 def t2LDRSBT : T2IldT<1, 0b00, "ldrsbt", IIC_iLoad_bh_i>;
1318 def t2LDRSHT : T2IldT<1, 0b01, "ldrsht", IIC_iLoad_bh_i>;
1321 defm t2STR :T2I_st<0b10,"str", IIC_iStore_i, IIC_iStore_si, GPR,
1322 BinOpFrag<(store node:$LHS, node:$RHS)>>;
1323 defm t2STRB:T2I_st<0b00,"strb", IIC_iStore_bh_i, IIC_iStore_bh_si,
1324 rGPR, BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
1325 defm t2STRH:T2I_st<0b01,"strh", IIC_iStore_bh_i, IIC_iStore_bh_si,
1326 rGPR, BinOpFrag<(truncstorei16 node:$LHS, node:$RHS)>>;
1329 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in
1330 def t2STRDi8 : T2Ii8s4<1, 0, 0, (outs),
1331 (ins GPR:$Rt, GPR:$Rt2, t2addrmode_imm8s4:$addr),
1332 IIC_iStore_d_r, "strd", "\t$Rt, $Rt2, $addr", "", []>;
1336 let mayStore = 1, neverHasSideEffects = 1 in {
1337 def t2STR_PRE : T2Ipreldst<0, 0b10, 0, 1, (outs GPRnopc:$Rn_wb),
1338 (ins GPRnopc:$Rt, t2addrmode_imm8:$addr),
1339 AddrModeT2_i8, IndexModePre, IIC_iStore_iu,
1340 "str", "\t$Rt, $addr!",
1341 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> {
1342 let AsmMatchConverter = "cvtStWriteBackRegT2AddrModeImm8";
1344 def t2STRH_PRE : T2Ipreldst<0, 0b01, 0, 1, (outs GPRnopc:$Rn_wb),
1345 (ins rGPR:$Rt, t2addrmode_imm8:$addr),
1346 AddrModeT2_i8, IndexModePre, IIC_iStore_iu,
1347 "strh", "\t$Rt, $addr!",
1348 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> {
1349 let AsmMatchConverter = "cvtStWriteBackRegT2AddrModeImm8";
1352 def t2STRB_PRE : T2Ipreldst<0, 0b00, 0, 1, (outs GPRnopc:$Rn_wb),
1353 (ins rGPR:$Rt, t2addrmode_imm8:$addr),
1354 AddrModeT2_i8, IndexModePre, IIC_iStore_bh_iu,
1355 "strb", "\t$Rt, $addr!",
1356 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> {
1357 let AsmMatchConverter = "cvtStWriteBackRegT2AddrModeImm8";
1359 } // mayStore = 1, neverHasSideEffects = 1
1361 def t2STR_POST : T2Ipostldst<0, 0b10, 0, 0, (outs GPRnopc:$Rn_wb),
1362 (ins GPRnopc:$Rt, addr_offset_none:$Rn,
1363 t2am_imm8_offset:$offset),
1364 AddrModeT2_i8, IndexModePost, IIC_iStore_iu,
1365 "str", "\t$Rt, $Rn$offset",
1366 "$Rn = $Rn_wb,@earlyclobber $Rn_wb",
1367 [(set GPRnopc:$Rn_wb,
1368 (post_store GPRnopc:$Rt, addr_offset_none:$Rn,
1369 t2am_imm8_offset:$offset))]>;
1371 def t2STRH_POST : T2Ipostldst<0, 0b01, 0, 0, (outs GPRnopc:$Rn_wb),
1372 (ins rGPR:$Rt, addr_offset_none:$Rn,
1373 t2am_imm8_offset:$offset),
1374 AddrModeT2_i8, IndexModePost, IIC_iStore_bh_iu,
1375 "strh", "\t$Rt, $Rn$offset",
1376 "$Rn = $Rn_wb,@earlyclobber $Rn_wb",
1377 [(set GPRnopc:$Rn_wb,
1378 (post_truncsti16 rGPR:$Rt, addr_offset_none:$Rn,
1379 t2am_imm8_offset:$offset))]>;
1381 def t2STRB_POST : T2Ipostldst<0, 0b00, 0, 0, (outs GPRnopc:$Rn_wb),
1382 (ins rGPR:$Rt, addr_offset_none:$Rn,
1383 t2am_imm8_offset:$offset),
1384 AddrModeT2_i8, IndexModePost, IIC_iStore_bh_iu,
1385 "strb", "\t$Rt, $Rn$offset",
1386 "$Rn = $Rn_wb,@earlyclobber $Rn_wb",
1387 [(set GPRnopc:$Rn_wb,
1388 (post_truncsti8 rGPR:$Rt, addr_offset_none:$Rn,
1389 t2am_imm8_offset:$offset))]>;
1391 // Pseudo-instructions for pattern matching the pre-indexed stores. We can't
1392 // put the patterns on the instruction definitions directly as ISel wants
1393 // the address base and offset to be separate operands, not a single
1394 // complex operand like we represent the instructions themselves. The
1395 // pseudos map between the two.
1396 let usesCustomInserter = 1,
1397 Constraints = "$Rn = $Rn_wb,@earlyclobber $Rn_wb" in {
1398 def t2STR_preidx: t2PseudoInst<(outs GPRnopc:$Rn_wb),
1399 (ins rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$offset, pred:$p),
1401 [(set GPRnopc:$Rn_wb,
1402 (pre_store rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$offset))]>;
1403 def t2STRB_preidx: t2PseudoInst<(outs GPRnopc:$Rn_wb),
1404 (ins rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$offset, pred:$p),
1406 [(set GPRnopc:$Rn_wb,
1407 (pre_truncsti8 rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$offset))]>;
1408 def t2STRH_preidx: t2PseudoInst<(outs GPRnopc:$Rn_wb),
1409 (ins rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$offset, pred:$p),
1411 [(set GPRnopc:$Rn_wb,
1412 (pre_truncsti16 rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$offset))]>;
1415 // STRT, STRBT, STRHT all have offset mode (PUW=0b110) and are for disassembly
1417 // Ref: A8.6.193 STR (immediate, Thumb) Encoding T4
1418 class T2IstT<bits<2> type, string opc, InstrItinClass ii>
1419 : T2Ii8<(outs rGPR:$Rt), (ins t2addrmode_imm8:$addr), ii, opc,
1420 "\t$Rt, $addr", []> {
1421 let Inst{31-27} = 0b11111;
1422 let Inst{26-25} = 0b00;
1423 let Inst{24} = 0; // not signed
1425 let Inst{22-21} = type;
1426 let Inst{20} = 0; // store
1428 let Inst{10-8} = 0b110; // PUW
1432 let Inst{15-12} = Rt;
1433 let Inst{19-16} = addr{12-9};
1434 let Inst{7-0} = addr{7-0};
1437 def t2STRT : T2IstT<0b10, "strt", IIC_iStore_i>;
1438 def t2STRBT : T2IstT<0b00, "strbt", IIC_iStore_bh_i>;
1439 def t2STRHT : T2IstT<0b01, "strht", IIC_iStore_bh_i>;
1441 // ldrd / strd pre / post variants
1442 // For disassembly only.
1444 def t2LDRD_PRE : T2Ii8s4<1, 1, 1, (outs rGPR:$Rt, rGPR:$Rt2, GPR:$wb),
1445 (ins t2addrmode_imm8s4:$addr), IIC_iLoad_d_ru,
1446 "ldrd", "\t$Rt, $Rt2, $addr!", "$addr.base = $wb", []> {
1447 let AsmMatchConverter = "cvtT2LdrdPre";
1448 let DecoderMethod = "DecodeT2LDRDPreInstruction";
1451 def t2LDRD_POST : T2Ii8s4post<0, 1, 1, (outs rGPR:$Rt, rGPR:$Rt2, GPR:$wb),
1452 (ins addr_offset_none:$addr, t2am_imm8s4_offset:$imm),
1453 IIC_iLoad_d_ru, "ldrd", "\t$Rt, $Rt2, $addr$imm",
1454 "$addr.base = $wb", []>;
1456 def t2STRD_PRE : T2Ii8s4<1, 1, 0, (outs GPR:$wb),
1457 (ins rGPR:$Rt, rGPR:$Rt2, t2addrmode_imm8s4:$addr),
1458 IIC_iStore_d_ru, "strd", "\t$Rt, $Rt2, $addr!",
1459 "$addr.base = $wb", []> {
1460 let AsmMatchConverter = "cvtT2StrdPre";
1461 let DecoderMethod = "DecodeT2STRDPreInstruction";
1464 def t2STRD_POST : T2Ii8s4post<0, 1, 0, (outs GPR:$wb),
1465 (ins rGPR:$Rt, rGPR:$Rt2, addr_offset_none:$addr,
1466 t2am_imm8s4_offset:$imm),
1467 IIC_iStore_d_ru, "strd", "\t$Rt, $Rt2, $addr$imm",
1468 "$addr.base = $wb", []>;
1470 // T2Ipl (Preload Data/Instruction) signals the memory system of possible future
1471 // data/instruction access.
1472 // instr_write is inverted for Thumb mode: (prefetch 3) -> (preload 0),
1473 // (prefetch 1) -> (preload 2), (prefetch 2) -> (preload 1).
1474 multiclass T2Ipl<bits<1> write, bits<1> instr, string opc> {
1476 def i12 : T2Ii12<(outs), (ins t2addrmode_imm12:$addr), IIC_Preload, opc,
1478 [(ARMPreload t2addrmode_imm12:$addr, (i32 write), (i32 instr))]> {
1479 let Inst{31-25} = 0b1111100;
1480 let Inst{24} = instr;
1482 let Inst{21} = write;
1484 let Inst{15-12} = 0b1111;
1487 let addr{12} = 1; // add = TRUE
1488 let Inst{19-16} = addr{16-13}; // Rn
1489 let Inst{23} = addr{12}; // U
1490 let Inst{11-0} = addr{11-0}; // imm12
1493 def i8 : T2Ii8<(outs), (ins t2addrmode_negimm8:$addr), IIC_Preload, opc,
1495 [(ARMPreload t2addrmode_negimm8:$addr, (i32 write), (i32 instr))]> {
1496 let Inst{31-25} = 0b1111100;
1497 let Inst{24} = instr;
1498 let Inst{23} = 0; // U = 0
1500 let Inst{21} = write;
1502 let Inst{15-12} = 0b1111;
1503 let Inst{11-8} = 0b1100;
1506 let Inst{19-16} = addr{12-9}; // Rn
1507 let Inst{7-0} = addr{7-0}; // imm8
1510 def s : T2Iso<(outs), (ins t2addrmode_so_reg:$addr), IIC_Preload, opc,
1512 [(ARMPreload t2addrmode_so_reg:$addr, (i32 write), (i32 instr))]> {
1513 let Inst{31-25} = 0b1111100;
1514 let Inst{24} = instr;
1515 let Inst{23} = 0; // add = TRUE for T1
1517 let Inst{21} = write;
1519 let Inst{15-12} = 0b1111;
1520 let Inst{11-6} = 0000000;
1523 let Inst{19-16} = addr{9-6}; // Rn
1524 let Inst{3-0} = addr{5-2}; // Rm
1525 let Inst{5-4} = addr{1-0}; // imm2
1527 let DecoderMethod = "DecodeT2LoadShift";
1529 // FIXME: We should have a separate 'pci' variant here. As-is we represent
1530 // it via the i12 variant, which it's related to, but that means we can
1531 // represent negative immediates, which aren't legal for anything except
1532 // the 'pci' case (Rn == 15).
1535 defm t2PLD : T2Ipl<0, 0, "pld">, Requires<[IsThumb2]>;
1536 defm t2PLDW : T2Ipl<1, 0, "pldw">, Requires<[IsThumb2,HasV7,HasMP]>;
1537 defm t2PLI : T2Ipl<0, 1, "pli">, Requires<[IsThumb2,HasV7]>;
1539 //===----------------------------------------------------------------------===//
1540 // Load / store multiple Instructions.
1543 multiclass thumb2_ld_mult<string asm, InstrItinClass itin,
1544 InstrItinClass itin_upd, bit L_bit> {
1546 T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1547 itin, !strconcat(asm, "${p}.w\t$Rn, $regs"), []> {
1551 let Inst{31-27} = 0b11101;
1552 let Inst{26-25} = 0b00;
1553 let Inst{24-23} = 0b01; // Increment After
1555 let Inst{21} = 0; // No writeback
1556 let Inst{20} = L_bit;
1557 let Inst{19-16} = Rn;
1558 let Inst{15-0} = regs;
1561 T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1562 itin_upd, !strconcat(asm, "${p}.w\t$Rn!, $regs"), "$Rn = $wb", []> {
1566 let Inst{31-27} = 0b11101;
1567 let Inst{26-25} = 0b00;
1568 let Inst{24-23} = 0b01; // Increment After
1570 let Inst{21} = 1; // Writeback
1571 let Inst{20} = L_bit;
1572 let Inst{19-16} = Rn;
1573 let Inst{15-0} = regs;
1576 T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1577 itin, !strconcat(asm, "db${p}\t$Rn, $regs"), []> {
1581 let Inst{31-27} = 0b11101;
1582 let Inst{26-25} = 0b00;
1583 let Inst{24-23} = 0b10; // Decrement Before
1585 let Inst{21} = 0; // No writeback
1586 let Inst{20} = L_bit;
1587 let Inst{19-16} = Rn;
1588 let Inst{15-0} = regs;
1591 T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1592 itin_upd, !strconcat(asm, "db${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
1596 let Inst{31-27} = 0b11101;
1597 let Inst{26-25} = 0b00;
1598 let Inst{24-23} = 0b10; // Decrement Before
1600 let Inst{21} = 1; // Writeback
1601 let Inst{20} = L_bit;
1602 let Inst{19-16} = Rn;
1603 let Inst{15-0} = regs;
1607 let neverHasSideEffects = 1 in {
1609 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
1610 defm t2LDM : thumb2_ld_mult<"ldm", IIC_iLoad_m, IIC_iLoad_mu, 1>;
1612 multiclass thumb2_st_mult<string asm, InstrItinClass itin,
1613 InstrItinClass itin_upd, bit L_bit> {
1615 T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1616 itin, !strconcat(asm, "${p}.w\t$Rn, $regs"), []> {
1620 let Inst{31-27} = 0b11101;
1621 let Inst{26-25} = 0b00;
1622 let Inst{24-23} = 0b01; // Increment After
1624 let Inst{21} = 0; // No writeback
1625 let Inst{20} = L_bit;
1626 let Inst{19-16} = Rn;
1628 let Inst{14} = regs{14};
1630 let Inst{12-0} = regs{12-0};
1633 T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1634 itin_upd, !strconcat(asm, "${p}.w\t$Rn!, $regs"), "$Rn = $wb", []> {
1638 let Inst{31-27} = 0b11101;
1639 let Inst{26-25} = 0b00;
1640 let Inst{24-23} = 0b01; // Increment After
1642 let Inst{21} = 1; // Writeback
1643 let Inst{20} = L_bit;
1644 let Inst{19-16} = Rn;
1646 let Inst{14} = regs{14};
1648 let Inst{12-0} = regs{12-0};
1651 T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1652 itin, !strconcat(asm, "db${p}\t$Rn, $regs"), []> {
1656 let Inst{31-27} = 0b11101;
1657 let Inst{26-25} = 0b00;
1658 let Inst{24-23} = 0b10; // Decrement Before
1660 let Inst{21} = 0; // No writeback
1661 let Inst{20} = L_bit;
1662 let Inst{19-16} = Rn;
1664 let Inst{14} = regs{14};
1666 let Inst{12-0} = regs{12-0};
1669 T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1670 itin_upd, !strconcat(asm, "db${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
1674 let Inst{31-27} = 0b11101;
1675 let Inst{26-25} = 0b00;
1676 let Inst{24-23} = 0b10; // Decrement Before
1678 let Inst{21} = 1; // Writeback
1679 let Inst{20} = L_bit;
1680 let Inst{19-16} = Rn;
1682 let Inst{14} = regs{14};
1684 let Inst{12-0} = regs{12-0};
1689 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
1690 defm t2STM : thumb2_st_mult<"stm", IIC_iStore_m, IIC_iStore_mu, 0>;
1692 } // neverHasSideEffects
1695 //===----------------------------------------------------------------------===//
1696 // Move Instructions.
1699 let neverHasSideEffects = 1 in
1700 def t2MOVr : T2sTwoReg<(outs GPRnopc:$Rd), (ins GPR:$Rm), IIC_iMOVr,
1701 "mov", ".w\t$Rd, $Rm", []> {
1702 let Inst{31-27} = 0b11101;
1703 let Inst{26-25} = 0b01;
1704 let Inst{24-21} = 0b0010;
1705 let Inst{19-16} = 0b1111; // Rn
1706 let Inst{14-12} = 0b000;
1707 let Inst{7-4} = 0b0000;
1709 def : t2InstAlias<"mov${p}.w $Rd, $Rm", (t2MOVr GPRnopc:$Rd, GPR:$Rm,
1710 pred:$p, zero_reg)>;
1711 def : t2InstAlias<"movs${p}.w $Rd, $Rm", (t2MOVr GPRnopc:$Rd, GPR:$Rm,
1713 def : t2InstAlias<"movs${p} $Rd, $Rm", (t2MOVr GPRnopc:$Rd, GPR:$Rm,
1716 // AddedComplexity to ensure isel tries t2MOVi before t2MOVi16.
1717 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1,
1718 AddedComplexity = 1 in
1719 def t2MOVi : T2sOneRegImm<(outs rGPR:$Rd), (ins t2_so_imm:$imm), IIC_iMOVi,
1720 "mov", ".w\t$Rd, $imm",
1721 [(set rGPR:$Rd, t2_so_imm:$imm)]> {
1722 let Inst{31-27} = 0b11110;
1724 let Inst{24-21} = 0b0010;
1725 let Inst{19-16} = 0b1111; // Rn
1729 // cc_out is handled as part of the explicit mnemonic in the parser for 'mov'.
1730 // Use aliases to get that to play nice here.
1731 def : t2InstAlias<"movs${p}.w $Rd, $imm", (t2MOVi rGPR:$Rd, t2_so_imm:$imm,
1733 def : t2InstAlias<"movs${p} $Rd, $imm", (t2MOVi rGPR:$Rd, t2_so_imm:$imm,
1736 def : t2InstAlias<"mov${p}.w $Rd, $imm", (t2MOVi rGPR:$Rd, t2_so_imm:$imm,
1737 pred:$p, zero_reg)>;
1738 def : t2InstAlias<"mov${p} $Rd, $imm", (t2MOVi rGPR:$Rd, t2_so_imm:$imm,
1739 pred:$p, zero_reg)>;
1741 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
1742 def t2MOVi16 : T2I<(outs rGPR:$Rd), (ins imm0_65535_expr:$imm), IIC_iMOVi,
1743 "movw", "\t$Rd, $imm",
1744 [(set rGPR:$Rd, imm0_65535:$imm)]> {
1745 let Inst{31-27} = 0b11110;
1747 let Inst{24-21} = 0b0010;
1748 let Inst{20} = 0; // The S bit.
1754 let Inst{11-8} = Rd;
1755 let Inst{19-16} = imm{15-12};
1756 let Inst{26} = imm{11};
1757 let Inst{14-12} = imm{10-8};
1758 let Inst{7-0} = imm{7-0};
1759 let DecoderMethod = "DecodeT2MOVTWInstruction";
1762 def t2MOVi16_ga_pcrel : PseudoInst<(outs rGPR:$Rd),
1763 (ins i32imm:$addr, pclabel:$id), IIC_iMOVi, []>;
1765 let Constraints = "$src = $Rd" in {
1766 def t2MOVTi16 : T2I<(outs rGPR:$Rd),
1767 (ins rGPR:$src, imm0_65535_expr:$imm), IIC_iMOVi,
1768 "movt", "\t$Rd, $imm",
1770 (or (and rGPR:$src, 0xffff), lo16AllZero:$imm))]> {
1771 let Inst{31-27} = 0b11110;
1773 let Inst{24-21} = 0b0110;
1774 let Inst{20} = 0; // The S bit.
1780 let Inst{11-8} = Rd;
1781 let Inst{19-16} = imm{15-12};
1782 let Inst{26} = imm{11};
1783 let Inst{14-12} = imm{10-8};
1784 let Inst{7-0} = imm{7-0};
1785 let DecoderMethod = "DecodeT2MOVTWInstruction";
1788 def t2MOVTi16_ga_pcrel : PseudoInst<(outs rGPR:$Rd),
1789 (ins rGPR:$src, i32imm:$addr, pclabel:$id), IIC_iMOVi, []>;
1792 def : T2Pat<(or rGPR:$src, 0xffff0000), (t2MOVTi16 rGPR:$src, 0xffff)>;
1794 //===----------------------------------------------------------------------===//
1795 // Extend Instructions.
1800 def t2SXTB : T2I_ext_rrot<0b100, "sxtb",
1801 UnOpFrag<(sext_inreg node:$Src, i8)>>;
1802 def t2SXTH : T2I_ext_rrot<0b000, "sxth",
1803 UnOpFrag<(sext_inreg node:$Src, i16)>>;
1804 def t2SXTB16 : T2I_ext_rrot_sxtb16<0b010, "sxtb16">;
1806 def t2SXTAB : T2I_exta_rrot<0b100, "sxtab",
1807 BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
1808 def t2SXTAH : T2I_exta_rrot<0b000, "sxtah",
1809 BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
1810 def t2SXTAB16 : T2I_exta_rrot_np<0b010, "sxtab16">;
1814 let AddedComplexity = 16 in {
1815 def t2UXTB : T2I_ext_rrot<0b101, "uxtb",
1816 UnOpFrag<(and node:$Src, 0x000000FF)>>;
1817 def t2UXTH : T2I_ext_rrot<0b001, "uxth",
1818 UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
1819 def t2UXTB16 : T2I_ext_rrot_uxtb16<0b011, "uxtb16",
1820 UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
1822 // FIXME: This pattern incorrectly assumes the shl operator is a rotate.
1823 // The transformation should probably be done as a combiner action
1824 // instead so we can include a check for masking back in the upper
1825 // eight bits of the source into the lower eight bits of the result.
1826 //def : T2Pat<(and (shl rGPR:$Src, (i32 8)), 0xFF00FF),
1827 // (t2UXTB16 rGPR:$Src, 3)>,
1828 // Requires<[HasT2ExtractPack, IsThumb2]>;
1829 def : T2Pat<(and (srl rGPR:$Src, (i32 8)), 0xFF00FF),
1830 (t2UXTB16 rGPR:$Src, 1)>,
1831 Requires<[HasT2ExtractPack, IsThumb2]>;
1833 def t2UXTAB : T2I_exta_rrot<0b101, "uxtab",
1834 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
1835 def t2UXTAH : T2I_exta_rrot<0b001, "uxtah",
1836 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
1837 def t2UXTAB16 : T2I_exta_rrot_np<0b011, "uxtab16">;
1840 //===----------------------------------------------------------------------===//
1841 // Arithmetic Instructions.
1844 defm t2ADD : T2I_bin_ii12rs<0b000, "add",
1845 BinOpFrag<(add node:$LHS, node:$RHS)>, 1>;
1846 defm t2SUB : T2I_bin_ii12rs<0b101, "sub",
1847 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
1849 // ADD and SUB with 's' bit set. No 12-bit immediate (T4) variants.
1851 // Currently, t2ADDS/t2SUBS are pseudo opcodes that exist only in the
1852 // selection DAG. They are "lowered" to real t2ADD/t2SUB opcodes by
1853 // AdjustInstrPostInstrSelection where we determine whether or not to
1854 // set the "s" bit based on CPSR liveness.
1856 // FIXME: Eliminate t2ADDS/t2SUBS pseudo opcodes after adding tablegen
1857 // support for an optional CPSR definition that corresponds to the DAG
1858 // node's second value. We can then eliminate the implicit def of CPSR.
1859 defm t2ADDS : T2I_bin_s_irs <IIC_iALUi, IIC_iALUr, IIC_iALUsi,
1860 BinOpFrag<(ARMaddc node:$LHS, node:$RHS)>, 1>;
1861 defm t2SUBS : T2I_bin_s_irs <IIC_iALUi, IIC_iALUr, IIC_iALUsi,
1862 BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>;
1864 let hasPostISelHook = 1 in {
1865 defm t2ADC : T2I_adde_sube_irs<0b1010, "adc",
1866 BinOpWithFlagFrag<(ARMadde node:$LHS, node:$RHS, node:$FLAG)>, 1>;
1867 defm t2SBC : T2I_adde_sube_irs<0b1011, "sbc",
1868 BinOpWithFlagFrag<(ARMsube node:$LHS, node:$RHS, node:$FLAG)>>;
1872 defm t2RSB : T2I_rbin_irs <0b1110, "rsb",
1873 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
1875 // FIXME: Eliminate them if we can write def : Pat patterns which defines
1876 // CPSR and the implicit def of CPSR is not needed.
1877 defm t2RSBS : T2I_rbin_s_is <BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>;
1879 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
1880 // The assume-no-carry-in form uses the negation of the input since add/sub
1881 // assume opposite meanings of the carry flag (i.e., carry == !borrow).
1882 // See the definition of AddWithCarry() in the ARM ARM A2.2.1 for the gory
1884 // The AddedComplexity preferences the first variant over the others since
1885 // it can be shrunk to a 16-bit wide encoding, while the others cannot.
1886 let AddedComplexity = 1 in
1887 def : T2Pat<(add GPR:$src, imm0_255_neg:$imm),
1888 (t2SUBri GPR:$src, imm0_255_neg:$imm)>;
1889 def : T2Pat<(add GPR:$src, t2_so_imm_neg:$imm),
1890 (t2SUBri GPR:$src, t2_so_imm_neg:$imm)>;
1891 def : T2Pat<(add GPR:$src, imm0_4095_neg:$imm),
1892 (t2SUBri12 GPR:$src, imm0_4095_neg:$imm)>;
1893 let AddedComplexity = 1 in
1894 def : T2Pat<(ARMaddc rGPR:$src, imm0_255_neg:$imm),
1895 (t2SUBSri rGPR:$src, imm0_255_neg:$imm)>;
1896 def : T2Pat<(ARMaddc rGPR:$src, t2_so_imm_neg:$imm),
1897 (t2SUBSri rGPR:$src, t2_so_imm_neg:$imm)>;
1898 // The with-carry-in form matches bitwise not instead of the negation.
1899 // Effectively, the inverse interpretation of the carry flag already accounts
1900 // for part of the negation.
1901 let AddedComplexity = 1 in
1902 def : T2Pat<(ARMadde rGPR:$src, imm0_255_not:$imm, CPSR),
1903 (t2SBCri rGPR:$src, imm0_255_not:$imm)>;
1904 def : T2Pat<(ARMadde rGPR:$src, t2_so_imm_not:$imm, CPSR),
1905 (t2SBCri rGPR:$src, t2_so_imm_not:$imm)>;
1907 // Select Bytes -- for disassembly only
1909 def t2SEL : T2ThreeReg<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
1910 NoItinerary, "sel", "\t$Rd, $Rn, $Rm", []>,
1911 Requires<[IsThumb2, HasThumb2DSP]> {
1912 let Inst{31-27} = 0b11111;
1913 let Inst{26-24} = 0b010;
1915 let Inst{22-20} = 0b010;
1916 let Inst{15-12} = 0b1111;
1918 let Inst{6-4} = 0b000;
1921 // A6.3.13, A6.3.14, A6.3.15 Parallel addition and subtraction (signed/unsigned)
1922 // And Miscellaneous operations -- for disassembly only
1923 class T2I_pam<bits<3> op22_20, bits<4> op7_4, string opc,
1924 list<dag> pat = [/* For disassembly only; pattern left blank */],
1925 dag iops = (ins rGPR:$Rn, rGPR:$Rm),
1926 string asm = "\t$Rd, $Rn, $Rm">
1927 : T2I<(outs rGPR:$Rd), iops, NoItinerary, opc, asm, pat>,
1928 Requires<[IsThumb2, HasThumb2DSP]> {
1929 let Inst{31-27} = 0b11111;
1930 let Inst{26-23} = 0b0101;
1931 let Inst{22-20} = op22_20;
1932 let Inst{15-12} = 0b1111;
1933 let Inst{7-4} = op7_4;
1939 let Inst{11-8} = Rd;
1940 let Inst{19-16} = Rn;
1944 // Saturating add/subtract -- for disassembly only
1946 def t2QADD : T2I_pam<0b000, 0b1000, "qadd",
1947 [(set rGPR:$Rd, (int_arm_qadd rGPR:$Rn, rGPR:$Rm))],
1948 (ins rGPR:$Rm, rGPR:$Rn), "\t$Rd, $Rm, $Rn">;
1949 def t2QADD16 : T2I_pam<0b001, 0b0001, "qadd16">;
1950 def t2QADD8 : T2I_pam<0b000, 0b0001, "qadd8">;
1951 def t2QASX : T2I_pam<0b010, 0b0001, "qasx">;
1952 def t2QDADD : T2I_pam<0b000, 0b1001, "qdadd", [],
1953 (ins rGPR:$Rm, rGPR:$Rn), "\t$Rd, $Rm, $Rn">;
1954 def t2QDSUB : T2I_pam<0b000, 0b1011, "qdsub", [],
1955 (ins rGPR:$Rm, rGPR:$Rn), "\t$Rd, $Rm, $Rn">;
1956 def t2QSAX : T2I_pam<0b110, 0b0001, "qsax">;
1957 def t2QSUB : T2I_pam<0b000, 0b1010, "qsub",
1958 [(set rGPR:$Rd, (int_arm_qsub rGPR:$Rn, rGPR:$Rm))],
1959 (ins rGPR:$Rm, rGPR:$Rn), "\t$Rd, $Rm, $Rn">;
1960 def t2QSUB16 : T2I_pam<0b101, 0b0001, "qsub16">;
1961 def t2QSUB8 : T2I_pam<0b100, 0b0001, "qsub8">;
1962 def t2UQADD16 : T2I_pam<0b001, 0b0101, "uqadd16">;
1963 def t2UQADD8 : T2I_pam<0b000, 0b0101, "uqadd8">;
1964 def t2UQASX : T2I_pam<0b010, 0b0101, "uqasx">;
1965 def t2UQSAX : T2I_pam<0b110, 0b0101, "uqsax">;
1966 def t2UQSUB16 : T2I_pam<0b101, 0b0101, "uqsub16">;
1967 def t2UQSUB8 : T2I_pam<0b100, 0b0101, "uqsub8">;
1969 // Signed/Unsigned add/subtract -- for disassembly only
1971 def t2SASX : T2I_pam<0b010, 0b0000, "sasx">;
1972 def t2SADD16 : T2I_pam<0b001, 0b0000, "sadd16">;
1973 def t2SADD8 : T2I_pam<0b000, 0b0000, "sadd8">;
1974 def t2SSAX : T2I_pam<0b110, 0b0000, "ssax">;
1975 def t2SSUB16 : T2I_pam<0b101, 0b0000, "ssub16">;
1976 def t2SSUB8 : T2I_pam<0b100, 0b0000, "ssub8">;
1977 def t2UASX : T2I_pam<0b010, 0b0100, "uasx">;
1978 def t2UADD16 : T2I_pam<0b001, 0b0100, "uadd16">;
1979 def t2UADD8 : T2I_pam<0b000, 0b0100, "uadd8">;
1980 def t2USAX : T2I_pam<0b110, 0b0100, "usax">;
1981 def t2USUB16 : T2I_pam<0b101, 0b0100, "usub16">;
1982 def t2USUB8 : T2I_pam<0b100, 0b0100, "usub8">;
1984 // Signed/Unsigned halving add/subtract -- for disassembly only
1986 def t2SHASX : T2I_pam<0b010, 0b0010, "shasx">;
1987 def t2SHADD16 : T2I_pam<0b001, 0b0010, "shadd16">;
1988 def t2SHADD8 : T2I_pam<0b000, 0b0010, "shadd8">;
1989 def t2SHSAX : T2I_pam<0b110, 0b0010, "shsax">;
1990 def t2SHSUB16 : T2I_pam<0b101, 0b0010, "shsub16">;
1991 def t2SHSUB8 : T2I_pam<0b100, 0b0010, "shsub8">;
1992 def t2UHASX : T2I_pam<0b010, 0b0110, "uhasx">;
1993 def t2UHADD16 : T2I_pam<0b001, 0b0110, "uhadd16">;
1994 def t2UHADD8 : T2I_pam<0b000, 0b0110, "uhadd8">;
1995 def t2UHSAX : T2I_pam<0b110, 0b0110, "uhsax">;
1996 def t2UHSUB16 : T2I_pam<0b101, 0b0110, "uhsub16">;
1997 def t2UHSUB8 : T2I_pam<0b100, 0b0110, "uhsub8">;
1999 // Helper class for disassembly only
2000 // A6.3.16 & A6.3.17
2001 // T2Imac - Thumb2 multiply [accumulate, and absolute difference] instructions.
2002 class T2ThreeReg_mac<bit long, bits<3> op22_20, bits<4> op7_4, dag oops,
2003 dag iops, InstrItinClass itin, string opc, string asm, list<dag> pattern>
2004 : T2ThreeReg<oops, iops, itin, opc, asm, pattern> {
2005 let Inst{31-27} = 0b11111;
2006 let Inst{26-24} = 0b011;
2007 let Inst{23} = long;
2008 let Inst{22-20} = op22_20;
2009 let Inst{7-4} = op7_4;
2012 class T2FourReg_mac<bit long, bits<3> op22_20, bits<4> op7_4, dag oops,
2013 dag iops, InstrItinClass itin, string opc, string asm, list<dag> pattern>
2014 : T2FourReg<oops, iops, itin, opc, asm, pattern> {
2015 let Inst{31-27} = 0b11111;
2016 let Inst{26-24} = 0b011;
2017 let Inst{23} = long;
2018 let Inst{22-20} = op22_20;
2019 let Inst{7-4} = op7_4;
2022 // Unsigned Sum of Absolute Differences [and Accumulate].
2023 def t2USAD8 : T2ThreeReg_mac<0, 0b111, 0b0000, (outs rGPR:$Rd),
2024 (ins rGPR:$Rn, rGPR:$Rm),
2025 NoItinerary, "usad8", "\t$Rd, $Rn, $Rm", []>,
2026 Requires<[IsThumb2, HasThumb2DSP]> {
2027 let Inst{15-12} = 0b1111;
2029 def t2USADA8 : T2FourReg_mac<0, 0b111, 0b0000, (outs rGPR:$Rd),
2030 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), NoItinerary,
2031 "usada8", "\t$Rd, $Rn, $Rm, $Ra", []>,
2032 Requires<[IsThumb2, HasThumb2DSP]>;
2034 // Signed/Unsigned saturate.
2035 class T2SatI<dag oops, dag iops, InstrItinClass itin,
2036 string opc, string asm, list<dag> pattern>
2037 : T2I<oops, iops, itin, opc, asm, pattern> {
2043 let Inst{11-8} = Rd;
2044 let Inst{19-16} = Rn;
2045 let Inst{4-0} = sat_imm;
2046 let Inst{21} = sh{5};
2047 let Inst{14-12} = sh{4-2};
2048 let Inst{7-6} = sh{1-0};
2053 (ins imm1_32:$sat_imm, rGPR:$Rn, t2_shift_imm:$sh),
2054 NoItinerary, "ssat", "\t$Rd, $sat_imm, $Rn$sh", []> {
2055 let Inst{31-27} = 0b11110;
2056 let Inst{25-22} = 0b1100;
2062 def t2SSAT16: T2SatI<
2063 (outs rGPR:$Rd), (ins imm1_16:$sat_imm, rGPR:$Rn), NoItinerary,
2064 "ssat16", "\t$Rd, $sat_imm, $Rn", []>,
2065 Requires<[IsThumb2, HasThumb2DSP]> {
2066 let Inst{31-27} = 0b11110;
2067 let Inst{25-22} = 0b1100;
2070 let Inst{21} = 1; // sh = '1'
2071 let Inst{14-12} = 0b000; // imm3 = '000'
2072 let Inst{7-6} = 0b00; // imm2 = '00'
2073 let Inst{5-4} = 0b00;
2078 (ins imm0_31:$sat_imm, rGPR:$Rn, t2_shift_imm:$sh),
2079 NoItinerary, "usat", "\t$Rd, $sat_imm, $Rn$sh", []> {
2080 let Inst{31-27} = 0b11110;
2081 let Inst{25-22} = 0b1110;
2086 def t2USAT16: T2SatI<(outs rGPR:$Rd), (ins imm0_15:$sat_imm, rGPR:$Rn),
2088 "usat16", "\t$Rd, $sat_imm, $Rn", []>,
2089 Requires<[IsThumb2, HasThumb2DSP]> {
2090 let Inst{31-22} = 0b1111001110;
2093 let Inst{21} = 1; // sh = '1'
2094 let Inst{14-12} = 0b000; // imm3 = '000'
2095 let Inst{7-6} = 0b00; // imm2 = '00'
2096 let Inst{5-4} = 0b00;
2099 def : T2Pat<(int_arm_ssat GPR:$a, imm:$pos), (t2SSAT imm:$pos, GPR:$a, 0)>;
2100 def : T2Pat<(int_arm_usat GPR:$a, imm:$pos), (t2USAT imm:$pos, GPR:$a, 0)>;
2102 //===----------------------------------------------------------------------===//
2103 // Shift and rotate Instructions.
2106 defm t2LSL : T2I_sh_ir<0b00, "lsl", imm0_31,
2107 BinOpFrag<(shl node:$LHS, node:$RHS)>, "t2LSL">;
2108 defm t2LSR : T2I_sh_ir<0b01, "lsr", imm_sr,
2109 BinOpFrag<(srl node:$LHS, node:$RHS)>, "t2LSR">;
2110 defm t2ASR : T2I_sh_ir<0b10, "asr", imm_sr,
2111 BinOpFrag<(sra node:$LHS, node:$RHS)>, "t2ASR">;
2112 defm t2ROR : T2I_sh_ir<0b11, "ror", imm0_31,
2113 BinOpFrag<(rotr node:$LHS, node:$RHS)>, "t2ROR">;
2115 // (rotr x, (and y, 0x...1f)) ==> (ROR x, y)
2116 def : Pat<(rotr rGPR:$lhs, (and rGPR:$rhs, lo5AllOne)),
2117 (t2RORrr rGPR:$lhs, rGPR:$rhs)>;
2119 let Uses = [CPSR] in {
2120 def t2RRX : T2sTwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iMOVsi,
2121 "rrx", "\t$Rd, $Rm",
2122 [(set rGPR:$Rd, (ARMrrx rGPR:$Rm))]> {
2123 let Inst{31-27} = 0b11101;
2124 let Inst{26-25} = 0b01;
2125 let Inst{24-21} = 0b0010;
2126 let Inst{19-16} = 0b1111; // Rn
2127 let Inst{14-12} = 0b000;
2128 let Inst{7-4} = 0b0011;
2132 let isCodeGenOnly = 1, Defs = [CPSR] in {
2133 def t2MOVsrl_flag : T2TwoRegShiftImm<
2134 (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iMOVsi,
2135 "lsrs", ".w\t$Rd, $Rm, #1",
2136 [(set rGPR:$Rd, (ARMsrl_flag rGPR:$Rm))]> {
2137 let Inst{31-27} = 0b11101;
2138 let Inst{26-25} = 0b01;
2139 let Inst{24-21} = 0b0010;
2140 let Inst{20} = 1; // The S bit.
2141 let Inst{19-16} = 0b1111; // Rn
2142 let Inst{5-4} = 0b01; // Shift type.
2143 // Shift amount = Inst{14-12:7-6} = 1.
2144 let Inst{14-12} = 0b000;
2145 let Inst{7-6} = 0b01;
2147 def t2MOVsra_flag : T2TwoRegShiftImm<
2148 (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iMOVsi,
2149 "asrs", ".w\t$Rd, $Rm, #1",
2150 [(set rGPR:$Rd, (ARMsra_flag rGPR:$Rm))]> {
2151 let Inst{31-27} = 0b11101;
2152 let Inst{26-25} = 0b01;
2153 let Inst{24-21} = 0b0010;
2154 let Inst{20} = 1; // The S bit.
2155 let Inst{19-16} = 0b1111; // Rn
2156 let Inst{5-4} = 0b10; // Shift type.
2157 // Shift amount = Inst{14-12:7-6} = 1.
2158 let Inst{14-12} = 0b000;
2159 let Inst{7-6} = 0b01;
2163 //===----------------------------------------------------------------------===//
2164 // Bitwise Instructions.
2167 defm t2AND : T2I_bin_w_irs<0b0000, "and",
2168 IIC_iBITi, IIC_iBITr, IIC_iBITsi,
2169 BinOpFrag<(and node:$LHS, node:$RHS)>, "t2AND", 1>;
2170 defm t2ORR : T2I_bin_w_irs<0b0010, "orr",
2171 IIC_iBITi, IIC_iBITr, IIC_iBITsi,
2172 BinOpFrag<(or node:$LHS, node:$RHS)>, "t2ORR", 1>;
2173 defm t2EOR : T2I_bin_w_irs<0b0100, "eor",
2174 IIC_iBITi, IIC_iBITr, IIC_iBITsi,
2175 BinOpFrag<(xor node:$LHS, node:$RHS)>, "t2EOR", 1>;
2177 defm t2BIC : T2I_bin_w_irs<0b0001, "bic",
2178 IIC_iBITi, IIC_iBITr, IIC_iBITsi,
2179 BinOpFrag<(and node:$LHS, (not node:$RHS))>,
2182 class T2BitFI<dag oops, dag iops, InstrItinClass itin,
2183 string opc, string asm, list<dag> pattern>
2184 : T2I<oops, iops, itin, opc, asm, pattern> {
2189 let Inst{11-8} = Rd;
2190 let Inst{4-0} = msb{4-0};
2191 let Inst{14-12} = lsb{4-2};
2192 let Inst{7-6} = lsb{1-0};
2195 class T2TwoRegBitFI<dag oops, dag iops, InstrItinClass itin,
2196 string opc, string asm, list<dag> pattern>
2197 : T2BitFI<oops, iops, itin, opc, asm, pattern> {
2200 let Inst{19-16} = Rn;
2203 let Constraints = "$src = $Rd" in
2204 def t2BFC : T2BitFI<(outs rGPR:$Rd), (ins rGPR:$src, bf_inv_mask_imm:$imm),
2205 IIC_iUNAsi, "bfc", "\t$Rd, $imm",
2206 [(set rGPR:$Rd, (and rGPR:$src, bf_inv_mask_imm:$imm))]> {
2207 let Inst{31-27} = 0b11110;
2208 let Inst{26} = 0; // should be 0.
2210 let Inst{24-20} = 0b10110;
2211 let Inst{19-16} = 0b1111; // Rn
2213 let Inst{5} = 0; // should be 0.
2216 let msb{4-0} = imm{9-5};
2217 let lsb{4-0} = imm{4-0};
2220 def t2SBFX: T2TwoRegBitFI<
2221 (outs rGPR:$Rd), (ins rGPR:$Rn, imm0_31:$lsb, imm1_32:$msb),
2222 IIC_iUNAsi, "sbfx", "\t$Rd, $Rn, $lsb, $msb", []> {
2223 let Inst{31-27} = 0b11110;
2225 let Inst{24-20} = 0b10100;
2229 def t2UBFX: T2TwoRegBitFI<
2230 (outs rGPR:$Rd), (ins rGPR:$Rn, imm0_31:$lsb, imm1_32:$msb),
2231 IIC_iUNAsi, "ubfx", "\t$Rd, $Rn, $lsb, $msb", []> {
2232 let Inst{31-27} = 0b11110;
2234 let Inst{24-20} = 0b11100;
2238 // A8.6.18 BFI - Bitfield insert (Encoding T1)
2239 let Constraints = "$src = $Rd" in {
2240 def t2BFI : T2TwoRegBitFI<(outs rGPR:$Rd),
2241 (ins rGPR:$src, rGPR:$Rn, bf_inv_mask_imm:$imm),
2242 IIC_iBITi, "bfi", "\t$Rd, $Rn, $imm",
2243 [(set rGPR:$Rd, (ARMbfi rGPR:$src, rGPR:$Rn,
2244 bf_inv_mask_imm:$imm))]> {
2245 let Inst{31-27} = 0b11110;
2246 let Inst{26} = 0; // should be 0.
2248 let Inst{24-20} = 0b10110;
2250 let Inst{5} = 0; // should be 0.
2253 let msb{4-0} = imm{9-5};
2254 let lsb{4-0} = imm{4-0};
2258 defm t2ORN : T2I_bin_irs<0b0011, "orn",
2259 IIC_iBITi, IIC_iBITr, IIC_iBITsi,
2260 BinOpFrag<(or node:$LHS, (not node:$RHS))>,
2263 /// T2I_un_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a
2264 /// unary operation that produces a value. These are predicable and can be
2265 /// changed to modify CPSR.
2266 multiclass T2I_un_irs<bits<4> opcod, string opc,
2267 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
2268 PatFrag opnode, bit Cheap = 0, bit ReMat = 0> {
2270 def i : T2sOneRegImm<(outs rGPR:$Rd), (ins t2_so_imm:$imm), iii,
2272 [(set rGPR:$Rd, (opnode t2_so_imm:$imm))]> {
2273 let isAsCheapAsAMove = Cheap;
2274 let isReMaterializable = ReMat;
2275 let Inst{31-27} = 0b11110;
2277 let Inst{24-21} = opcod;
2278 let Inst{19-16} = 0b1111; // Rn
2282 def r : T2sTwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm), iir,
2283 opc, ".w\t$Rd, $Rm",
2284 [(set rGPR:$Rd, (opnode rGPR:$Rm))]> {
2285 let Inst{31-27} = 0b11101;
2286 let Inst{26-25} = 0b01;
2287 let Inst{24-21} = opcod;
2288 let Inst{19-16} = 0b1111; // Rn
2289 let Inst{14-12} = 0b000; // imm3
2290 let Inst{7-6} = 0b00; // imm2
2291 let Inst{5-4} = 0b00; // type
2294 def s : T2sOneRegShiftedReg<(outs rGPR:$Rd), (ins t2_so_reg:$ShiftedRm), iis,
2295 opc, ".w\t$Rd, $ShiftedRm",
2296 [(set rGPR:$Rd, (opnode t2_so_reg:$ShiftedRm))]> {
2297 let Inst{31-27} = 0b11101;
2298 let Inst{26-25} = 0b01;
2299 let Inst{24-21} = opcod;
2300 let Inst{19-16} = 0b1111; // Rn
2304 // Prefer over of t2EORri ra, rb, -1 because mvn has 16-bit version
2305 let AddedComplexity = 1 in
2306 defm t2MVN : T2I_un_irs <0b0011, "mvn",
2307 IIC_iMVNi, IIC_iMVNr, IIC_iMVNsi,
2308 UnOpFrag<(not node:$Src)>, 1, 1>;
2310 let AddedComplexity = 1 in
2311 def : T2Pat<(and rGPR:$src, t2_so_imm_not:$imm),
2312 (t2BICri rGPR:$src, t2_so_imm_not:$imm)>;
2314 // FIXME: Disable this pattern on Darwin to workaround an assembler bug.
2315 def : T2Pat<(or rGPR:$src, t2_so_imm_not:$imm),
2316 (t2ORNri rGPR:$src, t2_so_imm_not:$imm)>,
2317 Requires<[IsThumb2]>;
2319 def : T2Pat<(t2_so_imm_not:$src),
2320 (t2MVNi t2_so_imm_not:$src)>;
2322 //===----------------------------------------------------------------------===//
2323 // Multiply Instructions.
2325 let isCommutable = 1 in
2326 def t2MUL: T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL32,
2327 "mul", "\t$Rd, $Rn, $Rm",
2328 [(set rGPR:$Rd, (mul rGPR:$Rn, rGPR:$Rm))]> {
2329 let Inst{31-27} = 0b11111;
2330 let Inst{26-23} = 0b0110;
2331 let Inst{22-20} = 0b000;
2332 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2333 let Inst{7-4} = 0b0000; // Multiply
2336 def t2MLA: T2FourReg<
2337 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2338 "mla", "\t$Rd, $Rn, $Rm, $Ra",
2339 [(set rGPR:$Rd, (add (mul rGPR:$Rn, rGPR:$Rm), rGPR:$Ra))]> {
2340 let Inst{31-27} = 0b11111;
2341 let Inst{26-23} = 0b0110;
2342 let Inst{22-20} = 0b000;
2343 let Inst{7-4} = 0b0000; // Multiply
2346 def t2MLS: T2FourReg<
2347 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2348 "mls", "\t$Rd, $Rn, $Rm, $Ra",
2349 [(set rGPR:$Rd, (sub rGPR:$Ra, (mul rGPR:$Rn, rGPR:$Rm)))]> {
2350 let Inst{31-27} = 0b11111;
2351 let Inst{26-23} = 0b0110;
2352 let Inst{22-20} = 0b000;
2353 let Inst{7-4} = 0b0001; // Multiply and Subtract
2356 // Extra precision multiplies with low / high results
2357 let neverHasSideEffects = 1 in {
2358 let isCommutable = 1 in {
2359 def t2SMULL : T2MulLong<0b000, 0b0000,
2360 (outs rGPR:$RdLo, rGPR:$RdHi),
2361 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL64,
2362 "smull", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2364 def t2UMULL : T2MulLong<0b010, 0b0000,
2365 (outs rGPR:$RdLo, rGPR:$RdHi),
2366 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL64,
2367 "umull", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2370 // Multiply + accumulate
2371 def t2SMLAL : T2MulLong<0b100, 0b0000,
2372 (outs rGPR:$RdLo, rGPR:$RdHi),
2373 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMAC64,
2374 "smlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2376 def t2UMLAL : T2MulLong<0b110, 0b0000,
2377 (outs rGPR:$RdLo, rGPR:$RdHi),
2378 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMAC64,
2379 "umlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2381 def t2UMAAL : T2MulLong<0b110, 0b0110,
2382 (outs rGPR:$RdLo, rGPR:$RdHi),
2383 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMAC64,
2384 "umaal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
2385 Requires<[IsThumb2, HasThumb2DSP]>;
2386 } // neverHasSideEffects
2388 // Rounding variants of the below included for disassembly only
2390 // Most significant word multiply
2391 def t2SMMUL : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL32,
2392 "smmul", "\t$Rd, $Rn, $Rm",
2393 [(set rGPR:$Rd, (mulhs rGPR:$Rn, rGPR:$Rm))]>,
2394 Requires<[IsThumb2, HasThumb2DSP]> {
2395 let Inst{31-27} = 0b11111;
2396 let Inst{26-23} = 0b0110;
2397 let Inst{22-20} = 0b101;
2398 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2399 let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
2402 def t2SMMULR : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL32,
2403 "smmulr", "\t$Rd, $Rn, $Rm", []>,
2404 Requires<[IsThumb2, HasThumb2DSP]> {
2405 let Inst{31-27} = 0b11111;
2406 let Inst{26-23} = 0b0110;
2407 let Inst{22-20} = 0b101;
2408 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2409 let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1)
2412 def t2SMMLA : T2FourReg<
2413 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2414 "smmla", "\t$Rd, $Rn, $Rm, $Ra",
2415 [(set rGPR:$Rd, (add (mulhs rGPR:$Rm, rGPR:$Rn), rGPR:$Ra))]>,
2416 Requires<[IsThumb2, HasThumb2DSP]> {
2417 let Inst{31-27} = 0b11111;
2418 let Inst{26-23} = 0b0110;
2419 let Inst{22-20} = 0b101;
2420 let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
2423 def t2SMMLAR: T2FourReg<
2424 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2425 "smmlar", "\t$Rd, $Rn, $Rm, $Ra", []>,
2426 Requires<[IsThumb2, HasThumb2DSP]> {
2427 let Inst{31-27} = 0b11111;
2428 let Inst{26-23} = 0b0110;
2429 let Inst{22-20} = 0b101;
2430 let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1)
2433 def t2SMMLS: T2FourReg<
2434 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2435 "smmls", "\t$Rd, $Rn, $Rm, $Ra",
2436 [(set rGPR:$Rd, (sub rGPR:$Ra, (mulhs rGPR:$Rn, rGPR:$Rm)))]>,
2437 Requires<[IsThumb2, HasThumb2DSP]> {
2438 let Inst{31-27} = 0b11111;
2439 let Inst{26-23} = 0b0110;
2440 let Inst{22-20} = 0b110;
2441 let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
2444 def t2SMMLSR:T2FourReg<
2445 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2446 "smmlsr", "\t$Rd, $Rn, $Rm, $Ra", []>,
2447 Requires<[IsThumb2, HasThumb2DSP]> {
2448 let Inst{31-27} = 0b11111;
2449 let Inst{26-23} = 0b0110;
2450 let Inst{22-20} = 0b110;
2451 let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1)
2454 multiclass T2I_smul<string opc, PatFrag opnode> {
2455 def BB : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2456 !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm",
2457 [(set rGPR:$Rd, (opnode (sext_inreg rGPR:$Rn, i16),
2458 (sext_inreg rGPR:$Rm, i16)))]>,
2459 Requires<[IsThumb2, HasThumb2DSP]> {
2460 let Inst{31-27} = 0b11111;
2461 let Inst{26-23} = 0b0110;
2462 let Inst{22-20} = 0b001;
2463 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2464 let Inst{7-6} = 0b00;
2465 let Inst{5-4} = 0b00;
2468 def BT : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2469 !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm",
2470 [(set rGPR:$Rd, (opnode (sext_inreg rGPR:$Rn, i16),
2471 (sra rGPR:$Rm, (i32 16))))]>,
2472 Requires<[IsThumb2, HasThumb2DSP]> {
2473 let Inst{31-27} = 0b11111;
2474 let Inst{26-23} = 0b0110;
2475 let Inst{22-20} = 0b001;
2476 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2477 let Inst{7-6} = 0b00;
2478 let Inst{5-4} = 0b01;
2481 def TB : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2482 !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm",
2483 [(set rGPR:$Rd, (opnode (sra rGPR:$Rn, (i32 16)),
2484 (sext_inreg rGPR:$Rm, i16)))]>,
2485 Requires<[IsThumb2, HasThumb2DSP]> {
2486 let Inst{31-27} = 0b11111;
2487 let Inst{26-23} = 0b0110;
2488 let Inst{22-20} = 0b001;
2489 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2490 let Inst{7-6} = 0b00;
2491 let Inst{5-4} = 0b10;
2494 def TT : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2495 !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm",
2496 [(set rGPR:$Rd, (opnode (sra rGPR:$Rn, (i32 16)),
2497 (sra rGPR:$Rm, (i32 16))))]>,
2498 Requires<[IsThumb2, HasThumb2DSP]> {
2499 let Inst{31-27} = 0b11111;
2500 let Inst{26-23} = 0b0110;
2501 let Inst{22-20} = 0b001;
2502 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2503 let Inst{7-6} = 0b00;
2504 let Inst{5-4} = 0b11;
2507 def WB : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2508 !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm",
2509 [(set rGPR:$Rd, (sra (opnode rGPR:$Rn,
2510 (sext_inreg rGPR:$Rm, i16)), (i32 16)))]>,
2511 Requires<[IsThumb2, HasThumb2DSP]> {
2512 let Inst{31-27} = 0b11111;
2513 let Inst{26-23} = 0b0110;
2514 let Inst{22-20} = 0b011;
2515 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2516 let Inst{7-6} = 0b00;
2517 let Inst{5-4} = 0b00;
2520 def WT : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2521 !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm",
2522 [(set rGPR:$Rd, (sra (opnode rGPR:$Rn,
2523 (sra rGPR:$Rm, (i32 16))), (i32 16)))]>,
2524 Requires<[IsThumb2, HasThumb2DSP]> {
2525 let Inst{31-27} = 0b11111;
2526 let Inst{26-23} = 0b0110;
2527 let Inst{22-20} = 0b011;
2528 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2529 let Inst{7-6} = 0b00;
2530 let Inst{5-4} = 0b01;
2535 multiclass T2I_smla<string opc, PatFrag opnode> {
2537 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2538 !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm, $Ra",
2539 [(set rGPR:$Rd, (add rGPR:$Ra,
2540 (opnode (sext_inreg rGPR:$Rn, i16),
2541 (sext_inreg rGPR:$Rm, i16))))]>,
2542 Requires<[IsThumb2, HasThumb2DSP]> {
2543 let Inst{31-27} = 0b11111;
2544 let Inst{26-23} = 0b0110;
2545 let Inst{22-20} = 0b001;
2546 let Inst{7-6} = 0b00;
2547 let Inst{5-4} = 0b00;
2551 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2552 !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm, $Ra",
2553 [(set rGPR:$Rd, (add rGPR:$Ra, (opnode (sext_inreg rGPR:$Rn, i16),
2554 (sra rGPR:$Rm, (i32 16)))))]>,
2555 Requires<[IsThumb2, HasThumb2DSP]> {
2556 let Inst{31-27} = 0b11111;
2557 let Inst{26-23} = 0b0110;
2558 let Inst{22-20} = 0b001;
2559 let Inst{7-6} = 0b00;
2560 let Inst{5-4} = 0b01;
2564 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2565 !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm, $Ra",
2566 [(set rGPR:$Rd, (add rGPR:$Ra, (opnode (sra rGPR:$Rn, (i32 16)),
2567 (sext_inreg rGPR:$Rm, i16))))]>,
2568 Requires<[IsThumb2, HasThumb2DSP]> {
2569 let Inst{31-27} = 0b11111;
2570 let Inst{26-23} = 0b0110;
2571 let Inst{22-20} = 0b001;
2572 let Inst{7-6} = 0b00;
2573 let Inst{5-4} = 0b10;
2577 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2578 !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm, $Ra",
2579 [(set rGPR:$Rd, (add rGPR:$Ra, (opnode (sra rGPR:$Rn, (i32 16)),
2580 (sra rGPR:$Rm, (i32 16)))))]>,
2581 Requires<[IsThumb2, HasThumb2DSP]> {
2582 let Inst{31-27} = 0b11111;
2583 let Inst{26-23} = 0b0110;
2584 let Inst{22-20} = 0b001;
2585 let Inst{7-6} = 0b00;
2586 let Inst{5-4} = 0b11;
2590 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2591 !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm, $Ra",
2592 [(set rGPR:$Rd, (add rGPR:$Ra, (sra (opnode rGPR:$Rn,
2593 (sext_inreg rGPR:$Rm, i16)), (i32 16))))]>,
2594 Requires<[IsThumb2, HasThumb2DSP]> {
2595 let Inst{31-27} = 0b11111;
2596 let Inst{26-23} = 0b0110;
2597 let Inst{22-20} = 0b011;
2598 let Inst{7-6} = 0b00;
2599 let Inst{5-4} = 0b00;
2603 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2604 !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm, $Ra",
2605 [(set rGPR:$Rd, (add rGPR:$Ra, (sra (opnode rGPR:$Rn,
2606 (sra rGPR:$Rm, (i32 16))), (i32 16))))]>,
2607 Requires<[IsThumb2, HasThumb2DSP]> {
2608 let Inst{31-27} = 0b11111;
2609 let Inst{26-23} = 0b0110;
2610 let Inst{22-20} = 0b011;
2611 let Inst{7-6} = 0b00;
2612 let Inst{5-4} = 0b01;
2616 defm t2SMUL : T2I_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
2617 defm t2SMLA : T2I_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
2619 // Halfword multiple accumulate long: SMLAL<x><y>
2620 def t2SMLALBB : T2FourReg_mac<1, 0b100, 0b1000, (outs rGPR:$Ra,rGPR:$Rd),
2621 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlalbb", "\t$Ra, $Rd, $Rn, $Rm",
2622 [/* For disassembly only; pattern left blank */]>,
2623 Requires<[IsThumb2, HasThumb2DSP]>;
2624 def t2SMLALBT : T2FourReg_mac<1, 0b100, 0b1001, (outs rGPR:$Ra,rGPR:$Rd),
2625 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlalbt", "\t$Ra, $Rd, $Rn, $Rm",
2626 [/* For disassembly only; pattern left blank */]>,
2627 Requires<[IsThumb2, HasThumb2DSP]>;
2628 def t2SMLALTB : T2FourReg_mac<1, 0b100, 0b1010, (outs rGPR:$Ra,rGPR:$Rd),
2629 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlaltb", "\t$Ra, $Rd, $Rn, $Rm",
2630 [/* For disassembly only; pattern left blank */]>,
2631 Requires<[IsThumb2, HasThumb2DSP]>;
2632 def t2SMLALTT : T2FourReg_mac<1, 0b100, 0b1011, (outs rGPR:$Ra,rGPR:$Rd),
2633 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlaltt", "\t$Ra, $Rd, $Rn, $Rm",
2634 [/* For disassembly only; pattern left blank */]>,
2635 Requires<[IsThumb2, HasThumb2DSP]>;
2637 // Dual halfword multiple: SMUAD, SMUSD, SMLAD, SMLSD, SMLALD, SMLSLD
2638 def t2SMUAD: T2ThreeReg_mac<
2639 0, 0b010, 0b0000, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
2640 IIC_iMAC32, "smuad", "\t$Rd, $Rn, $Rm", []>,
2641 Requires<[IsThumb2, HasThumb2DSP]> {
2642 let Inst{15-12} = 0b1111;
2644 def t2SMUADX:T2ThreeReg_mac<
2645 0, 0b010, 0b0001, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
2646 IIC_iMAC32, "smuadx", "\t$Rd, $Rn, $Rm", []>,
2647 Requires<[IsThumb2, HasThumb2DSP]> {
2648 let Inst{15-12} = 0b1111;
2650 def t2SMUSD: T2ThreeReg_mac<
2651 0, 0b100, 0b0000, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
2652 IIC_iMAC32, "smusd", "\t$Rd, $Rn, $Rm", []>,
2653 Requires<[IsThumb2, HasThumb2DSP]> {
2654 let Inst{15-12} = 0b1111;
2656 def t2SMUSDX:T2ThreeReg_mac<
2657 0, 0b100, 0b0001, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
2658 IIC_iMAC32, "smusdx", "\t$Rd, $Rn, $Rm", []>,
2659 Requires<[IsThumb2, HasThumb2DSP]> {
2660 let Inst{15-12} = 0b1111;
2662 def t2SMLAD : T2FourReg_mac<
2663 0, 0b010, 0b0000, (outs rGPR:$Rd),
2664 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smlad",
2665 "\t$Rd, $Rn, $Rm, $Ra", []>,
2666 Requires<[IsThumb2, HasThumb2DSP]>;
2667 def t2SMLADX : T2FourReg_mac<
2668 0, 0b010, 0b0001, (outs rGPR:$Rd),
2669 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smladx",
2670 "\t$Rd, $Rn, $Rm, $Ra", []>,
2671 Requires<[IsThumb2, HasThumb2DSP]>;
2672 def t2SMLSD : T2FourReg_mac<0, 0b100, 0b0000, (outs rGPR:$Rd),
2673 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smlsd",
2674 "\t$Rd, $Rn, $Rm, $Ra", []>,
2675 Requires<[IsThumb2, HasThumb2DSP]>;
2676 def t2SMLSDX : T2FourReg_mac<0, 0b100, 0b0001, (outs rGPR:$Rd),
2677 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smlsdx",
2678 "\t$Rd, $Rn, $Rm, $Ra", []>,
2679 Requires<[IsThumb2, HasThumb2DSP]>;
2680 def t2SMLALD : T2FourReg_mac<1, 0b100, 0b1100, (outs rGPR:$Ra,rGPR:$Rd),
2681 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMAC64, "smlald",
2682 "\t$Ra, $Rd, $Rn, $Rm", []>,
2683 Requires<[IsThumb2, HasThumb2DSP]>;
2684 def t2SMLALDX : T2FourReg_mac<1, 0b100, 0b1101, (outs rGPR:$Ra,rGPR:$Rd),
2685 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlaldx",
2686 "\t$Ra, $Rd, $Rn, $Rm", []>,
2687 Requires<[IsThumb2, HasThumb2DSP]>;
2688 def t2SMLSLD : T2FourReg_mac<1, 0b101, 0b1100, (outs rGPR:$Ra,rGPR:$Rd),
2689 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlsld",
2690 "\t$Ra, $Rd, $Rn, $Rm", []>,
2691 Requires<[IsThumb2, HasThumb2DSP]>;
2692 def t2SMLSLDX : T2FourReg_mac<1, 0b101, 0b1101, (outs rGPR:$Ra,rGPR:$Rd),
2693 (ins rGPR:$Rm,rGPR:$Rn), IIC_iMAC64, "smlsldx",
2694 "\t$Ra, $Rd, $Rn, $Rm", []>,
2695 Requires<[IsThumb2, HasThumb2DSP]>;
2697 //===----------------------------------------------------------------------===//
2698 // Division Instructions.
2699 // Signed and unsigned division on v7-M
2701 def t2SDIV : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUi,
2702 "sdiv", "\t$Rd, $Rn, $Rm",
2703 [(set rGPR:$Rd, (sdiv rGPR:$Rn, rGPR:$Rm))]>,
2704 Requires<[HasDivide, IsThumb2]> {
2705 let Inst{31-27} = 0b11111;
2706 let Inst{26-21} = 0b011100;
2708 let Inst{15-12} = 0b1111;
2709 let Inst{7-4} = 0b1111;
2712 def t2UDIV : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUi,
2713 "udiv", "\t$Rd, $Rn, $Rm",
2714 [(set rGPR:$Rd, (udiv rGPR:$Rn, rGPR:$Rm))]>,
2715 Requires<[HasDivide, IsThumb2]> {
2716 let Inst{31-27} = 0b11111;
2717 let Inst{26-21} = 0b011101;
2719 let Inst{15-12} = 0b1111;
2720 let Inst{7-4} = 0b1111;
2723 //===----------------------------------------------------------------------===//
2724 // Misc. Arithmetic Instructions.
2727 class T2I_misc<bits<2> op1, bits<2> op2, dag oops, dag iops,
2728 InstrItinClass itin, string opc, string asm, list<dag> pattern>
2729 : T2ThreeReg<oops, iops, itin, opc, asm, pattern> {
2730 let Inst{31-27} = 0b11111;
2731 let Inst{26-22} = 0b01010;
2732 let Inst{21-20} = op1;
2733 let Inst{15-12} = 0b1111;
2734 let Inst{7-6} = 0b10;
2735 let Inst{5-4} = op2;
2739 def t2CLZ : T2I_misc<0b11, 0b00, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2740 "clz", "\t$Rd, $Rm", [(set rGPR:$Rd, (ctlz rGPR:$Rm))]>;
2742 def t2RBIT : T2I_misc<0b01, 0b10, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2743 "rbit", "\t$Rd, $Rm",
2744 [(set rGPR:$Rd, (ARMrbit rGPR:$Rm))]>;
2746 def t2REV : T2I_misc<0b01, 0b00, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2747 "rev", ".w\t$Rd, $Rm", [(set rGPR:$Rd, (bswap rGPR:$Rm))]>;
2749 def t2REV16 : T2I_misc<0b01, 0b01, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2750 "rev16", ".w\t$Rd, $Rm",
2751 [(set rGPR:$Rd, (rotr (bswap rGPR:$Rm), (i32 16)))]>;
2753 def t2REVSH : T2I_misc<0b01, 0b11, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2754 "revsh", ".w\t$Rd, $Rm",
2755 [(set rGPR:$Rd, (sra (bswap rGPR:$Rm), (i32 16)))]>;
2757 def : T2Pat<(or (sra (shl rGPR:$Rm, (i32 24)), (i32 16)),
2758 (and (srl rGPR:$Rm, (i32 8)), 0xFF)),
2759 (t2REVSH rGPR:$Rm)>;
2761 def t2PKHBT : T2ThreeReg<
2762 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, pkh_lsl_amt:$sh),
2763 IIC_iBITsi, "pkhbt", "\t$Rd, $Rn, $Rm$sh",
2764 [(set rGPR:$Rd, (or (and rGPR:$Rn, 0xFFFF),
2765 (and (shl rGPR:$Rm, pkh_lsl_amt:$sh),
2767 Requires<[HasT2ExtractPack, IsThumb2]> {
2768 let Inst{31-27} = 0b11101;
2769 let Inst{26-25} = 0b01;
2770 let Inst{24-20} = 0b01100;
2771 let Inst{5} = 0; // BT form
2775 let Inst{14-12} = sh{4-2};
2776 let Inst{7-6} = sh{1-0};
2779 // Alternate cases for PKHBT where identities eliminate some nodes.
2780 def : T2Pat<(or (and rGPR:$src1, 0xFFFF), (and rGPR:$src2, 0xFFFF0000)),
2781 (t2PKHBT rGPR:$src1, rGPR:$src2, 0)>,
2782 Requires<[HasT2ExtractPack, IsThumb2]>;
2783 def : T2Pat<(or (and rGPR:$src1, 0xFFFF), (shl rGPR:$src2, imm16_31:$sh)),
2784 (t2PKHBT rGPR:$src1, rGPR:$src2, imm16_31:$sh)>,
2785 Requires<[HasT2ExtractPack, IsThumb2]>;
2787 // Note: Shifts of 1-15 bits will be transformed to srl instead of sra and
2788 // will match the pattern below.
2789 def t2PKHTB : T2ThreeReg<
2790 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, pkh_asr_amt:$sh),
2791 IIC_iBITsi, "pkhtb", "\t$Rd, $Rn, $Rm$sh",
2792 [(set rGPR:$Rd, (or (and rGPR:$Rn, 0xFFFF0000),
2793 (and (sra rGPR:$Rm, pkh_asr_amt:$sh),
2795 Requires<[HasT2ExtractPack, IsThumb2]> {
2796 let Inst{31-27} = 0b11101;
2797 let Inst{26-25} = 0b01;
2798 let Inst{24-20} = 0b01100;
2799 let Inst{5} = 1; // TB form
2803 let Inst{14-12} = sh{4-2};
2804 let Inst{7-6} = sh{1-0};
2807 // Alternate cases for PKHTB where identities eliminate some nodes. Note that
2808 // a shift amount of 0 is *not legal* here, it is PKHBT instead.
2809 def : T2Pat<(or (and rGPR:$src1, 0xFFFF0000), (srl rGPR:$src2, imm16_31:$sh)),
2810 (t2PKHTB rGPR:$src1, rGPR:$src2, imm16_31:$sh)>,
2811 Requires<[HasT2ExtractPack, IsThumb2]>;
2812 def : T2Pat<(or (and rGPR:$src1, 0xFFFF0000),
2813 (and (srl rGPR:$src2, imm1_15:$sh), 0xFFFF)),
2814 (t2PKHTB rGPR:$src1, rGPR:$src2, imm1_15:$sh)>,
2815 Requires<[HasT2ExtractPack, IsThumb2]>;
2817 //===----------------------------------------------------------------------===//
2818 // Comparison Instructions...
2820 defm t2CMP : T2I_cmp_irs<0b1101, "cmp",
2821 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsi,
2822 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>, "t2CMP">;
2824 def : T2Pat<(ARMcmpZ GPRnopc:$lhs, t2_so_imm:$imm),
2825 (t2CMPri GPRnopc:$lhs, t2_so_imm:$imm)>;
2826 def : T2Pat<(ARMcmpZ GPRnopc:$lhs, rGPR:$rhs),
2827 (t2CMPrr GPRnopc:$lhs, rGPR:$rhs)>;
2828 def : T2Pat<(ARMcmpZ GPRnopc:$lhs, t2_so_reg:$rhs),
2829 (t2CMPrs GPRnopc:$lhs, t2_so_reg:$rhs)>;
2831 //FIXME: Disable CMN, as CCodes are backwards from compare expectations
2832 // Compare-to-zero still works out, just not the relationals
2833 //defm t2CMN : T2I_cmp_irs<0b1000, "cmn",
2834 // BinOpFrag<(ARMcmp node:$LHS,(ineg node:$RHS))>>;
2835 defm t2CMNz : T2I_cmp_irs<0b1000, "cmn",
2836 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsi,
2837 BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>,
2840 //def : T2Pat<(ARMcmp GPR:$src, t2_so_imm_neg:$imm),
2841 // (t2CMNri GPR:$src, t2_so_imm_neg:$imm)>;
2843 def : T2Pat<(ARMcmpZ GPRnopc:$src, t2_so_imm_neg:$imm),
2844 (t2CMNzri GPRnopc:$src, t2_so_imm_neg:$imm)>;
2846 defm t2TST : T2I_cmp_irs<0b0000, "tst",
2847 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsi,
2848 BinOpFrag<(ARMcmpZ (and_su node:$LHS, node:$RHS), 0)>,
2850 defm t2TEQ : T2I_cmp_irs<0b0100, "teq",
2851 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsi,
2852 BinOpFrag<(ARMcmpZ (xor_su node:$LHS, node:$RHS), 0)>,
2855 // Conditional moves
2856 // FIXME: should be able to write a pattern for ARMcmov, but can't use
2857 // a two-value operand where a dag node expects two operands. :(
2858 let neverHasSideEffects = 1 in {
2859 def t2MOVCCr : t2PseudoInst<(outs rGPR:$Rd),
2860 (ins rGPR:$false, rGPR:$Rm, pred:$p),
2862 [/*(set rGPR:$Rd, (ARMcmov rGPR:$false, rGPR:$Rm, imm:$cc, CCR:$ccr))*/]>,
2863 RegConstraint<"$false = $Rd">;
2865 let isMoveImm = 1 in
2866 def t2MOVCCi : t2PseudoInst<(outs rGPR:$Rd),
2867 (ins rGPR:$false, t2_so_imm:$imm, pred:$p),
2869 [/*(set rGPR:$Rd,(ARMcmov rGPR:$false,t2_so_imm:$imm, imm:$cc, CCR:$ccr))*/]>,
2870 RegConstraint<"$false = $Rd">;
2872 // FIXME: Pseudo-ize these. For now, just mark codegen only.
2873 let isCodeGenOnly = 1 in {
2874 let isMoveImm = 1 in
2875 def t2MOVCCi16 : T2I<(outs rGPR:$Rd), (ins rGPR:$false, imm0_65535_expr:$imm),
2877 "movw", "\t$Rd, $imm", []>,
2878 RegConstraint<"$false = $Rd"> {
2879 let Inst{31-27} = 0b11110;
2881 let Inst{24-21} = 0b0010;
2882 let Inst{20} = 0; // The S bit.
2888 let Inst{11-8} = Rd;
2889 let Inst{19-16} = imm{15-12};
2890 let Inst{26} = imm{11};
2891 let Inst{14-12} = imm{10-8};
2892 let Inst{7-0} = imm{7-0};
2895 let isMoveImm = 1 in
2896 def t2MOVCCi32imm : PseudoInst<(outs rGPR:$dst),
2897 (ins rGPR:$false, i32imm:$src, pred:$p),
2898 IIC_iCMOVix2, []>, RegConstraint<"$false = $dst">;
2900 let isMoveImm = 1 in
2901 def t2MVNCCi : T2OneRegImm<(outs rGPR:$Rd), (ins rGPR:$false, t2_so_imm:$imm),
2902 IIC_iCMOVi, "mvn", "\t$Rd, $imm",
2903 [/*(set rGPR:$Rd,(ARMcmov rGPR:$false,t2_so_imm_not:$imm,
2904 imm:$cc, CCR:$ccr))*/]>,
2905 RegConstraint<"$false = $Rd"> {
2906 let Inst{31-27} = 0b11110;
2908 let Inst{24-21} = 0b0011;
2909 let Inst{20} = 0; // The S bit.
2910 let Inst{19-16} = 0b1111; // Rn
2914 class T2I_movcc_sh<bits<2> opcod, dag oops, dag iops, InstrItinClass itin,
2915 string opc, string asm, list<dag> pattern>
2916 : T2TwoRegShiftImm<oops, iops, itin, opc, asm, pattern> {
2917 let Inst{31-27} = 0b11101;
2918 let Inst{26-25} = 0b01;
2919 let Inst{24-21} = 0b0010;
2920 let Inst{20} = 0; // The S bit.
2921 let Inst{19-16} = 0b1111; // Rn
2922 let Inst{5-4} = opcod; // Shift type.
2924 def t2MOVCClsl : T2I_movcc_sh<0b00, (outs rGPR:$Rd),
2925 (ins rGPR:$false, rGPR:$Rm, i32imm:$imm),
2926 IIC_iCMOVsi, "lsl", ".w\t$Rd, $Rm, $imm", []>,
2927 RegConstraint<"$false = $Rd">;
2928 def t2MOVCClsr : T2I_movcc_sh<0b01, (outs rGPR:$Rd),
2929 (ins rGPR:$false, rGPR:$Rm, i32imm:$imm),
2930 IIC_iCMOVsi, "lsr", ".w\t$Rd, $Rm, $imm", []>,
2931 RegConstraint<"$false = $Rd">;
2932 def t2MOVCCasr : T2I_movcc_sh<0b10, (outs rGPR:$Rd),
2933 (ins rGPR:$false, rGPR:$Rm, i32imm:$imm),
2934 IIC_iCMOVsi, "asr", ".w\t$Rd, $Rm, $imm", []>,
2935 RegConstraint<"$false = $Rd">;
2936 def t2MOVCCror : T2I_movcc_sh<0b11, (outs rGPR:$Rd),
2937 (ins rGPR:$false, rGPR:$Rm, i32imm:$imm),
2938 IIC_iCMOVsi, "ror", ".w\t$Rd, $Rm, $imm", []>,
2939 RegConstraint<"$false = $Rd">;
2940 } // isCodeGenOnly = 1
2941 } // neverHasSideEffects
2943 //===----------------------------------------------------------------------===//
2944 // Atomic operations intrinsics
2947 // memory barriers protect the atomic sequences
2948 let hasSideEffects = 1 in {
2949 def t2DMB : AInoP<(outs), (ins memb_opt:$opt), ThumbFrm, NoItinerary,
2950 "dmb", "\t$opt", [(ARMMemBarrier (i32 imm:$opt))]>,
2951 Requires<[IsThumb, HasDB]> {
2953 let Inst{31-4} = 0xf3bf8f5;
2954 let Inst{3-0} = opt;
2958 def t2DSB : AInoP<(outs), (ins memb_opt:$opt), ThumbFrm, NoItinerary,
2959 "dsb", "\t$opt", []>,
2960 Requires<[IsThumb, HasDB]> {
2962 let Inst{31-4} = 0xf3bf8f4;
2963 let Inst{3-0} = opt;
2966 def t2ISB : AInoP<(outs), (ins memb_opt:$opt), ThumbFrm, NoItinerary,
2968 []>, Requires<[IsThumb2, HasDB]> {
2970 let Inst{31-4} = 0xf3bf8f6;
2971 let Inst{3-0} = opt;
2974 class T2I_ldrex<bits<2> opcod, dag oops, dag iops, AddrMode am, int sz,
2975 InstrItinClass itin, string opc, string asm, string cstr,
2976 list<dag> pattern, bits<4> rt2 = 0b1111>
2977 : Thumb2I<oops, iops, am, sz, itin, opc, asm, cstr, pattern> {
2978 let Inst{31-27} = 0b11101;
2979 let Inst{26-20} = 0b0001101;
2980 let Inst{11-8} = rt2;
2981 let Inst{7-6} = 0b01;
2982 let Inst{5-4} = opcod;
2983 let Inst{3-0} = 0b1111;
2987 let Inst{19-16} = addr;
2988 let Inst{15-12} = Rt;
2990 class T2I_strex<bits<2> opcod, dag oops, dag iops, AddrMode am, int sz,
2991 InstrItinClass itin, string opc, string asm, string cstr,
2992 list<dag> pattern, bits<4> rt2 = 0b1111>
2993 : Thumb2I<oops, iops, am, sz, itin, opc, asm, cstr, pattern> {
2994 let Inst{31-27} = 0b11101;
2995 let Inst{26-20} = 0b0001100;
2996 let Inst{11-8} = rt2;
2997 let Inst{7-6} = 0b01;
2998 let Inst{5-4} = opcod;
3004 let Inst{19-16} = addr;
3005 let Inst{15-12} = Rt;
3008 let mayLoad = 1 in {
3009 def t2LDREXB : T2I_ldrex<0b00, (outs rGPR:$Rt), (ins addr_offset_none:$addr),
3010 AddrModeNone, 4, NoItinerary,
3011 "ldrexb", "\t$Rt, $addr", "", []>;
3012 def t2LDREXH : T2I_ldrex<0b01, (outs rGPR:$Rt), (ins addr_offset_none:$addr),
3013 AddrModeNone, 4, NoItinerary,
3014 "ldrexh", "\t$Rt, $addr", "", []>;
3015 def t2LDREX : Thumb2I<(outs rGPR:$Rt), (ins t2addrmode_imm0_1020s4:$addr),
3016 AddrModeNone, 4, NoItinerary,
3017 "ldrex", "\t$Rt, $addr", "", []> {
3020 let Inst{31-27} = 0b11101;
3021 let Inst{26-20} = 0b0000101;
3022 let Inst{19-16} = addr{11-8};
3023 let Inst{15-12} = Rt;
3024 let Inst{11-8} = 0b1111;
3025 let Inst{7-0} = addr{7-0};
3027 let hasExtraDefRegAllocReq = 1 in
3028 def t2LDREXD : T2I_ldrex<0b11, (outs rGPR:$Rt, rGPR:$Rt2),
3029 (ins addr_offset_none:$addr),
3030 AddrModeNone, 4, NoItinerary,
3031 "ldrexd", "\t$Rt, $Rt2, $addr", "",
3034 let Inst{11-8} = Rt2;
3038 let mayStore = 1, Constraints = "@earlyclobber $Rd" in {
3039 def t2STREXB : T2I_strex<0b00, (outs rGPR:$Rd),
3040 (ins rGPR:$Rt, addr_offset_none:$addr),
3041 AddrModeNone, 4, NoItinerary,
3042 "strexb", "\t$Rd, $Rt, $addr", "", []>;
3043 def t2STREXH : T2I_strex<0b01, (outs rGPR:$Rd),
3044 (ins rGPR:$Rt, addr_offset_none:$addr),
3045 AddrModeNone, 4, NoItinerary,
3046 "strexh", "\t$Rd, $Rt, $addr", "", []>;
3047 def t2STREX : Thumb2I<(outs rGPR:$Rd), (ins rGPR:$Rt,
3048 t2addrmode_imm0_1020s4:$addr),
3049 AddrModeNone, 4, NoItinerary,
3050 "strex", "\t$Rd, $Rt, $addr", "",
3055 let Inst{31-27} = 0b11101;
3056 let Inst{26-20} = 0b0000100;
3057 let Inst{19-16} = addr{11-8};
3058 let Inst{15-12} = Rt;
3059 let Inst{11-8} = Rd;
3060 let Inst{7-0} = addr{7-0};
3064 let hasExtraSrcRegAllocReq = 1, Constraints = "@earlyclobber $Rd" in
3065 def t2STREXD : T2I_strex<0b11, (outs rGPR:$Rd),
3066 (ins rGPR:$Rt, rGPR:$Rt2, addr_offset_none:$addr),
3067 AddrModeNone, 4, NoItinerary,
3068 "strexd", "\t$Rd, $Rt, $Rt2, $addr", "", [],
3071 let Inst{11-8} = Rt2;
3074 def t2CLREX : T2I<(outs), (ins), NoItinerary, "clrex", "", []>,
3075 Requires<[IsThumb2, HasV7]> {
3076 let Inst{31-16} = 0xf3bf;
3077 let Inst{15-14} = 0b10;
3080 let Inst{11-8} = 0b1111;
3081 let Inst{7-4} = 0b0010;
3082 let Inst{3-0} = 0b1111;
3085 //===----------------------------------------------------------------------===//
3086 // SJLJ Exception handling intrinsics
3087 // eh_sjlj_setjmp() is an instruction sequence to store the return
3088 // address and save #0 in R0 for the non-longjmp case.
3089 // Since by its nature we may be coming from some other function to get
3090 // here, and we're using the stack frame for the containing function to
3091 // save/restore registers, we can't keep anything live in regs across
3092 // the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
3093 // when we get here from a longjmp(). We force everything out of registers
3094 // except for our own input by listing the relevant registers in Defs. By
3095 // doing so, we also cause the prologue/epilogue code to actively preserve
3096 // all of the callee-saved resgisters, which is exactly what we want.
3097 // $val is a scratch register for our use.
3099 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR,
3100 Q0, Q1, Q2, Q3, Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15],
3101 hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1,
3102 usesCustomInserter = 1 in {
3103 def t2Int_eh_sjlj_setjmp : Thumb2XI<(outs), (ins tGPR:$src, tGPR:$val),
3104 AddrModeNone, 0, NoItinerary, "", "",
3105 [(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>,
3106 Requires<[IsThumb2, HasVFP2]>;
3110 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR ],
3111 hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1,
3112 usesCustomInserter = 1 in {
3113 def t2Int_eh_sjlj_setjmp_nofp : Thumb2XI<(outs), (ins tGPR:$src, tGPR:$val),
3114 AddrModeNone, 0, NoItinerary, "", "",
3115 [(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>,
3116 Requires<[IsThumb2, NoVFP]>;
3120 //===----------------------------------------------------------------------===//
3121 // Control-Flow Instructions
3124 // FIXME: remove when we have a way to marking a MI with these properties.
3125 // FIXME: Should pc be an implicit operand like PICADD, etc?
3126 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
3127 hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in
3128 def t2LDMIA_RET: t2PseudoExpand<(outs GPR:$wb), (ins GPR:$Rn, pred:$p,
3129 reglist:$regs, variable_ops),
3130 4, IIC_iLoad_mBr, [],
3131 (t2LDMIA_UPD GPR:$wb, GPR:$Rn, pred:$p, reglist:$regs)>,
3132 RegConstraint<"$Rn = $wb">;
3134 let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
3135 let isPredicable = 1 in
3136 def t2B : T2I<(outs), (ins uncondbrtarget:$target), IIC_Br,
3138 [(br bb:$target)]> {
3139 let Inst{31-27} = 0b11110;
3140 let Inst{15-14} = 0b10;
3144 let Inst{26} = target{19};
3145 let Inst{11} = target{18};
3146 let Inst{13} = target{17};
3147 let Inst{21-16} = target{16-11};
3148 let Inst{10-0} = target{10-0};
3151 let isNotDuplicable = 1, isIndirectBranch = 1 in {
3152 def t2BR_JT : t2PseudoInst<(outs),
3153 (ins GPR:$target, GPR:$index, i32imm:$jt, i32imm:$id),
3155 [(ARMbr2jt GPR:$target, GPR:$index, tjumptable:$jt, imm:$id)]>;
3157 // FIXME: Add a non-pc based case that can be predicated.
3158 def t2TBB_JT : t2PseudoInst<(outs),
3159 (ins GPR:$index, i32imm:$jt, i32imm:$id), 0, IIC_Br, []>;
3161 def t2TBH_JT : t2PseudoInst<(outs),
3162 (ins GPR:$index, i32imm:$jt, i32imm:$id), 0, IIC_Br, []>;
3164 def t2TBB : T2I<(outs), (ins addrmode_tbb:$addr), IIC_Br,
3165 "tbb", "\t$addr", []> {
3168 let Inst{31-20} = 0b111010001101;
3169 let Inst{19-16} = Rn;
3170 let Inst{15-5} = 0b11110000000;
3171 let Inst{4} = 0; // B form
3174 let DecoderMethod = "DecodeThumbTableBranch";
3177 def t2TBH : T2I<(outs), (ins addrmode_tbh:$addr), IIC_Br,
3178 "tbh", "\t$addr", []> {
3181 let Inst{31-20} = 0b111010001101;
3182 let Inst{19-16} = Rn;
3183 let Inst{15-5} = 0b11110000000;
3184 let Inst{4} = 1; // H form
3187 let DecoderMethod = "DecodeThumbTableBranch";
3189 } // isNotDuplicable, isIndirectBranch
3191 } // isBranch, isTerminator, isBarrier
3193 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
3194 // a two-value operand where a dag node expects ", "two operands. :(
3195 let isBranch = 1, isTerminator = 1 in
3196 def t2Bcc : T2I<(outs), (ins brtarget:$target), IIC_Br,
3198 [/*(ARMbrcond bb:$target, imm:$cc)*/]> {
3199 let Inst{31-27} = 0b11110;
3200 let Inst{15-14} = 0b10;
3204 let Inst{25-22} = p;
3207 let Inst{26} = target{20};
3208 let Inst{11} = target{19};
3209 let Inst{13} = target{18};
3210 let Inst{21-16} = target{17-12};
3211 let Inst{10-0} = target{11-1};
3213 let DecoderMethod = "DecodeThumb2BCCInstruction";
3216 // Tail calls. The IOS version of thumb tail calls uses a t2 branch, so
3218 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in {
3220 let Defs = [R0, R1, R2, R3, R9, R12, PC,
3221 Q0, Q1, Q2, Q3, Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15],
3223 def tTAILJMPd: tPseudoExpand<(outs),
3224 (ins uncondbrtarget:$dst, pred:$p, variable_ops),
3226 (t2B uncondbrtarget:$dst, pred:$p)>,
3227 Requires<[IsThumb2, IsIOS]>;
3231 let Defs = [ITSTATE] in
3232 def t2IT : Thumb2XI<(outs), (ins it_pred:$cc, it_mask:$mask),
3233 AddrModeNone, 2, IIC_iALUx,
3234 "it$mask\t$cc", "", []> {
3235 // 16-bit instruction.
3236 let Inst{31-16} = 0x0000;
3237 let Inst{15-8} = 0b10111111;
3242 let Inst{3-0} = mask;
3244 let DecoderMethod = "DecodeIT";
3247 // Branch and Exchange Jazelle -- for disassembly only
3249 def t2BXJ : T2I<(outs), (ins rGPR:$func), NoItinerary, "bxj", "\t$func", []> {
3251 let Inst{31-27} = 0b11110;
3253 let Inst{25-20} = 0b111100;
3254 let Inst{19-16} = func;
3255 let Inst{15-0} = 0b1000111100000000;
3258 // Compare and branch on zero / non-zero
3259 let isBranch = 1, isTerminator = 1 in {
3260 def tCBZ : T1I<(outs), (ins tGPR:$Rn, t_cbtarget:$target), IIC_Br,
3261 "cbz\t$Rn, $target", []>,
3262 T1Misc<{0,0,?,1,?,?,?}>,
3263 Requires<[IsThumb2]> {
3267 let Inst{9} = target{5};
3268 let Inst{7-3} = target{4-0};
3272 def tCBNZ : T1I<(outs), (ins tGPR:$Rn, t_cbtarget:$target), IIC_Br,
3273 "cbnz\t$Rn, $target", []>,
3274 T1Misc<{1,0,?,1,?,?,?}>,
3275 Requires<[IsThumb2]> {
3279 let Inst{9} = target{5};
3280 let Inst{7-3} = target{4-0};
3286 // Change Processor State is a system instruction.
3287 // FIXME: Since the asm parser has currently no clean way to handle optional
3288 // operands, create 3 versions of the same instruction. Once there's a clean
3289 // framework to represent optional operands, change this behavior.
3290 class t2CPS<dag iops, string asm_op> : T2XI<(outs), iops, NoItinerary,
3291 !strconcat("cps", asm_op), []> {
3297 let Inst{31-27} = 0b11110;
3299 let Inst{25-20} = 0b111010;
3300 let Inst{19-16} = 0b1111;
3301 let Inst{15-14} = 0b10;
3303 let Inst{10-9} = imod;
3305 let Inst{7-5} = iflags;
3306 let Inst{4-0} = mode;
3307 let DecoderMethod = "DecodeT2CPSInstruction";
3311 def t2CPS3p : t2CPS<(ins imod_op:$imod, iflags_op:$iflags, i32imm:$mode),
3312 "$imod.w\t$iflags, $mode">;
3313 let mode = 0, M = 0 in
3314 def t2CPS2p : t2CPS<(ins imod_op:$imod, iflags_op:$iflags),
3315 "$imod.w\t$iflags">;
3316 let imod = 0, iflags = 0, M = 1 in
3317 def t2CPS1p : t2CPS<(ins imm0_31:$mode), "\t$mode">;
3319 // A6.3.4 Branches and miscellaneous control
3320 // Table A6-14 Change Processor State, and hint instructions
3321 class T2I_hint<bits<8> op7_0, string opc, string asm>
3322 : T2I<(outs), (ins), NoItinerary, opc, asm, []> {
3323 let Inst{31-20} = 0xf3a;
3324 let Inst{19-16} = 0b1111;
3325 let Inst{15-14} = 0b10;
3327 let Inst{10-8} = 0b000;
3328 let Inst{7-0} = op7_0;
3331 def t2NOP : T2I_hint<0b00000000, "nop", ".w">;
3332 def t2YIELD : T2I_hint<0b00000001, "yield", ".w">;
3333 def t2WFE : T2I_hint<0b00000010, "wfe", ".w">;
3334 def t2WFI : T2I_hint<0b00000011, "wfi", ".w">;
3335 def t2SEV : T2I_hint<0b00000100, "sev", ".w">;
3337 def t2DBG : T2I<(outs), (ins imm0_15:$opt), NoItinerary, "dbg", "\t$opt", []> {
3339 let Inst{31-20} = 0b111100111010;
3340 let Inst{19-16} = 0b1111;
3341 let Inst{15-8} = 0b10000000;
3342 let Inst{7-4} = 0b1111;
3343 let Inst{3-0} = opt;
3346 // Secure Monitor Call is a system instruction.
3347 // Option = Inst{19-16}
3348 def t2SMC : T2I<(outs), (ins imm0_15:$opt), NoItinerary, "smc", "\t$opt", []> {
3349 let Inst{31-27} = 0b11110;
3350 let Inst{26-20} = 0b1111111;
3351 let Inst{15-12} = 0b1000;
3354 let Inst{19-16} = opt;
3357 class T2SRS<bits<2> Op, bit W, dag oops, dag iops, InstrItinClass itin,
3358 string opc, string asm, list<dag> pattern>
3359 : T2I<oops, iops, itin, opc, asm, pattern> {
3361 let Inst{31-25} = 0b1110100;
3362 let Inst{24-23} = Op;
3365 let Inst{20-16} = 0b01101;
3366 let Inst{15-5} = 0b11000000000;
3367 let Inst{4-0} = mode{4-0};
3370 // Store Return State is a system instruction.
3371 def t2SRSDB_UPD : T2SRS<0b00, 1, (outs), (ins imm0_31:$mode), NoItinerary,
3372 "srsdb", "\tsp!, $mode", []>;
3373 def t2SRSDB : T2SRS<0b00, 0, (outs), (ins imm0_31:$mode), NoItinerary,
3374 "srsdb","\tsp, $mode", []>;
3375 def t2SRSIA_UPD : T2SRS<0b11, 1, (outs), (ins imm0_31:$mode), NoItinerary,
3376 "srsia","\tsp!, $mode", []>;
3377 def t2SRSIA : T2SRS<0b11, 0, (outs), (ins imm0_31:$mode), NoItinerary,
3378 "srsia","\tsp, $mode", []>;
3380 // Return From Exception is a system instruction.
3381 class T2RFE<bits<12> op31_20, dag oops, dag iops, InstrItinClass itin,
3382 string opc, string asm, list<dag> pattern>
3383 : T2I<oops, iops, itin, opc, asm, pattern> {
3384 let Inst{31-20} = op31_20{11-0};
3387 let Inst{19-16} = Rn;
3388 let Inst{15-0} = 0xc000;
3391 def t2RFEDBW : T2RFE<0b111010000011,
3392 (outs), (ins GPR:$Rn), NoItinerary, "rfedb", "\t$Rn!",
3393 [/* For disassembly only; pattern left blank */]>;
3394 def t2RFEDB : T2RFE<0b111010000001,
3395 (outs), (ins GPR:$Rn), NoItinerary, "rfedb", "\t$Rn",
3396 [/* For disassembly only; pattern left blank */]>;
3397 def t2RFEIAW : T2RFE<0b111010011011,
3398 (outs), (ins GPR:$Rn), NoItinerary, "rfeia", "\t$Rn!",
3399 [/* For disassembly only; pattern left blank */]>;
3400 def t2RFEIA : T2RFE<0b111010011001,
3401 (outs), (ins GPR:$Rn), NoItinerary, "rfeia", "\t$Rn",
3402 [/* For disassembly only; pattern left blank */]>;
3404 //===----------------------------------------------------------------------===//
3405 // Non-Instruction Patterns
3408 // 32-bit immediate using movw + movt.
3409 // This is a single pseudo instruction to make it re-materializable.
3410 // FIXME: Remove this when we can do generalized remat.
3411 let isReMaterializable = 1, isMoveImm = 1 in
3412 def t2MOVi32imm : PseudoInst<(outs rGPR:$dst), (ins i32imm:$src), IIC_iMOVix2,
3413 [(set rGPR:$dst, (i32 imm:$src))]>,
3414 Requires<[IsThumb, HasV6T2]>;
3416 // Pseudo instruction that combines movw + movt + add pc (if pic).
3417 // It also makes it possible to rematerialize the instructions.
3418 // FIXME: Remove this when we can do generalized remat and when machine licm
3419 // can properly the instructions.
3420 let isReMaterializable = 1 in {
3421 def t2MOV_ga_pcrel : PseudoInst<(outs rGPR:$dst), (ins i32imm:$addr),
3423 [(set rGPR:$dst, (ARMWrapperPIC tglobaladdr:$addr))]>,
3424 Requires<[IsThumb2, UseMovt]>;
3426 def t2MOV_ga_dyn : PseudoInst<(outs rGPR:$dst), (ins i32imm:$addr),
3428 [(set rGPR:$dst, (ARMWrapperDYN tglobaladdr:$addr))]>,
3429 Requires<[IsThumb2, UseMovt]>;
3432 // ConstantPool, GlobalAddress, and JumpTable
3433 def : T2Pat<(ARMWrapper tglobaladdr :$dst), (t2LEApcrel tglobaladdr :$dst)>,
3434 Requires<[IsThumb2, DontUseMovt]>;
3435 def : T2Pat<(ARMWrapper tconstpool :$dst), (t2LEApcrel tconstpool :$dst)>;
3436 def : T2Pat<(ARMWrapper tglobaladdr :$dst), (t2MOVi32imm tglobaladdr :$dst)>,
3437 Requires<[IsThumb2, UseMovt]>;
3439 def : T2Pat<(ARMWrapperJT tjumptable:$dst, imm:$id),
3440 (t2LEApcrelJT tjumptable:$dst, imm:$id)>;
3442 // Pseudo instruction that combines ldr from constpool and add pc. This should
3443 // be expanded into two instructions late to allow if-conversion and
3445 let canFoldAsLoad = 1, isReMaterializable = 1 in
3446 def t2LDRpci_pic : PseudoInst<(outs rGPR:$dst), (ins i32imm:$addr, pclabel:$cp),
3448 [(set rGPR:$dst, (ARMpic_add (load (ARMWrapper tconstpool:$addr)),
3450 Requires<[IsThumb2]>;
3452 // Pseudo isntruction that combines movs + predicated rsbmi
3453 // to implement integer ABS
3454 let usesCustomInserter = 1, Defs = [CPSR] in {
3455 def t2ABS : PseudoInst<(outs rGPR:$dst), (ins rGPR:$src),
3456 NoItinerary, []>, Requires<[IsThumb2]>;
3459 //===----------------------------------------------------------------------===//
3460 // Coprocessor load/store -- for disassembly only
3462 class T2CI<bits<4> op31_28, dag oops, dag iops, string opc, string asm>
3463 : T2I<oops, iops, NoItinerary, opc, asm, []> {
3464 let Inst{31-28} = op31_28;
3465 let Inst{27-25} = 0b110;
3468 multiclass t2LdStCop<bits<4> op31_28, bit load, bit Dbit, string asm> {
3469 def _OFFSET : T2CI<op31_28,
3470 (outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr),
3471 asm, "\t$cop, $CRd, $addr"> {
3475 let Inst{24} = 1; // P = 1
3476 let Inst{23} = addr{8};
3477 let Inst{22} = Dbit;
3478 let Inst{21} = 0; // W = 0
3479 let Inst{20} = load;
3480 let Inst{19-16} = addr{12-9};
3481 let Inst{15-12} = CRd;
3482 let Inst{11-8} = cop;
3483 let Inst{7-0} = addr{7-0};
3484 let DecoderMethod = "DecodeCopMemInstruction";
3486 def _PRE : T2CI<op31_28,
3487 (outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr),
3488 asm, "\t$cop, $CRd, $addr!"> {
3492 let Inst{24} = 1; // P = 1
3493 let Inst{23} = addr{8};
3494 let Inst{22} = Dbit;
3495 let Inst{21} = 1; // W = 1
3496 let Inst{20} = load;
3497 let Inst{19-16} = addr{12-9};
3498 let Inst{15-12} = CRd;
3499 let Inst{11-8} = cop;
3500 let Inst{7-0} = addr{7-0};
3501 let DecoderMethod = "DecodeCopMemInstruction";
3503 def _POST: T2CI<op31_28,
3504 (outs), (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
3505 postidx_imm8s4:$offset),
3506 asm, "\t$cop, $CRd, $addr, $offset"> {
3511 let Inst{24} = 0; // P = 0
3512 let Inst{23} = offset{8};
3513 let Inst{22} = Dbit;
3514 let Inst{21} = 1; // W = 1
3515 let Inst{20} = load;
3516 let Inst{19-16} = addr;
3517 let Inst{15-12} = CRd;
3518 let Inst{11-8} = cop;
3519 let Inst{7-0} = offset{7-0};
3520 let DecoderMethod = "DecodeCopMemInstruction";
3522 def _OPTION : T2CI<op31_28, (outs),
3523 (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
3524 coproc_option_imm:$option),
3525 asm, "\t$cop, $CRd, $addr, $option"> {
3530 let Inst{24} = 0; // P = 0
3531 let Inst{23} = 1; // U = 1
3532 let Inst{22} = Dbit;
3533 let Inst{21} = 0; // W = 0
3534 let Inst{20} = load;
3535 let Inst{19-16} = addr;
3536 let Inst{15-12} = CRd;
3537 let Inst{11-8} = cop;
3538 let Inst{7-0} = option;
3539 let DecoderMethod = "DecodeCopMemInstruction";
3543 defm t2LDC : t2LdStCop<0b1110, 1, 0, "ldc">;
3544 defm t2LDCL : t2LdStCop<0b1110, 1, 1, "ldcl">;
3545 defm t2STC : t2LdStCop<0b1110, 0, 0, "stc">;
3546 defm t2STCL : t2LdStCop<0b1110, 0, 1, "stcl">;
3547 defm t2LDC2 : t2LdStCop<0b1111, 1, 0, "ldc2">;
3548 defm t2LDC2L : t2LdStCop<0b1111, 1, 1, "ldc2l">;
3549 defm t2STC2 : t2LdStCop<0b1111, 0, 0, "stc2">;
3550 defm t2STC2L : t2LdStCop<0b1111, 0, 1, "stc2l">;
3553 //===----------------------------------------------------------------------===//
3554 // Move between special register and ARM core register -- for disassembly only
3556 // Move to ARM core register from Special Register
3560 // A/R class can only move from CPSR or SPSR.
3561 def t2MRS_AR : T2I<(outs GPR:$Rd), (ins), NoItinerary, "mrs", "\t$Rd, apsr", []>,
3562 Requires<[IsThumb2,IsARClass]> {
3564 let Inst{31-12} = 0b11110011111011111000;
3565 let Inst{11-8} = Rd;
3566 let Inst{7-0} = 0b0000;
3569 def : t2InstAlias<"mrs${p} $Rd, cpsr", (t2MRS_AR GPR:$Rd, pred:$p)>;
3571 def t2MRSsys_AR: T2I<(outs GPR:$Rd), (ins), NoItinerary, "mrs", "\t$Rd, spsr", []>,
3572 Requires<[IsThumb2,IsARClass]> {
3574 let Inst{31-12} = 0b11110011111111111000;
3575 let Inst{11-8} = Rd;
3576 let Inst{7-0} = 0b0000;
3581 // This MRS has a mask field in bits 7-0 and can take more values than
3582 // the A/R class (a full msr_mask).
3583 def t2MRS_M : T2I<(outs rGPR:$Rd), (ins msr_mask:$mask), NoItinerary,
3584 "mrs", "\t$Rd, $mask", []>,
3585 Requires<[IsThumb2,IsMClass]> {
3588 let Inst{31-12} = 0b11110011111011111000;
3589 let Inst{11-8} = Rd;
3590 let Inst{19-16} = 0b1111;
3591 let Inst{7-0} = mask;
3595 // Move from ARM core register to Special Register
3599 // No need to have both system and application versions, the encodings are the
3600 // same and the assembly parser has no way to distinguish between them. The mask
3601 // operand contains the special register (R Bit) in bit 4 and bits 3-0 contains
3602 // the mask with the fields to be accessed in the special register.
3603 def t2MSR_AR : T2I<(outs), (ins msr_mask:$mask, rGPR:$Rn),
3604 NoItinerary, "msr", "\t$mask, $Rn", []>,
3605 Requires<[IsThumb2,IsARClass]> {
3608 let Inst{31-21} = 0b11110011100;
3609 let Inst{20} = mask{4}; // R Bit
3610 let Inst{19-16} = Rn;
3611 let Inst{15-12} = 0b1000;
3612 let Inst{11-8} = mask{3-0};
3618 // Move from ARM core register to Special Register
3619 def t2MSR_M : T2I<(outs), (ins msr_mask:$SYSm, rGPR:$Rn),
3620 NoItinerary, "msr", "\t$SYSm, $Rn", []>,
3621 Requires<[IsThumb2,IsMClass]> {
3624 let Inst{31-21} = 0b11110011100;
3626 let Inst{19-16} = Rn;
3627 let Inst{15-12} = 0b1000;
3628 let Inst{7-0} = SYSm;
3632 //===----------------------------------------------------------------------===//
3633 // Move between coprocessor and ARM core register
3636 class t2MovRCopro<bits<4> Op, string opc, bit direction, dag oops, dag iops,
3638 : T2Cop<Op, oops, iops,
3639 !strconcat(opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2"),
3641 let Inst{27-24} = 0b1110;
3642 let Inst{20} = direction;
3652 let Inst{15-12} = Rt;
3653 let Inst{11-8} = cop;
3654 let Inst{23-21} = opc1;
3655 let Inst{7-5} = opc2;
3656 let Inst{3-0} = CRm;
3657 let Inst{19-16} = CRn;
3660 class t2MovRRCopro<bits<4> Op, string opc, bit direction,
3661 list<dag> pattern = []>
3663 (ins p_imm:$cop, imm0_15:$opc1, GPR:$Rt, GPR:$Rt2, c_imm:$CRm),
3664 !strconcat(opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm"), pattern> {
3665 let Inst{27-24} = 0b1100;
3666 let Inst{23-21} = 0b010;
3667 let Inst{20} = direction;
3675 let Inst{15-12} = Rt;
3676 let Inst{19-16} = Rt2;
3677 let Inst{11-8} = cop;
3678 let Inst{7-4} = opc1;
3679 let Inst{3-0} = CRm;
3682 /* from ARM core register to coprocessor */
3683 def t2MCR : t2MovRCopro<0b1110, "mcr", 0,
3685 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
3686 c_imm:$CRm, imm0_7:$opc2),
3687 [(int_arm_mcr imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
3688 imm:$CRm, imm:$opc2)]>;
3689 def t2MCR2 : t2MovRCopro<0b1111, "mcr2", 0,
3690 (outs), (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
3691 c_imm:$CRm, imm0_7:$opc2),
3692 [(int_arm_mcr2 imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
3693 imm:$CRm, imm:$opc2)]>;
3695 /* from coprocessor to ARM core register */
3696 def t2MRC : t2MovRCopro<0b1110, "mrc", 1,
3697 (outs GPR:$Rt), (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
3698 c_imm:$CRm, imm0_7:$opc2), []>;
3700 def t2MRC2 : t2MovRCopro<0b1111, "mrc2", 1,
3701 (outs GPR:$Rt), (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
3702 c_imm:$CRm, imm0_7:$opc2), []>;
3704 def : T2v6Pat<(int_arm_mrc imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2),
3705 (t2MRC imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
3707 def : T2v6Pat<(int_arm_mrc2 imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2),
3708 (t2MRC2 imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
3711 /* from ARM core register to coprocessor */
3712 def t2MCRR : t2MovRRCopro<0b1110, "mcrr", 0,
3713 [(int_arm_mcrr imm:$cop, imm:$opc1, GPR:$Rt, GPR:$Rt2,
3715 def t2MCRR2 : t2MovRRCopro<0b1111, "mcrr2", 0,
3716 [(int_arm_mcrr2 imm:$cop, imm:$opc1, GPR:$Rt,
3717 GPR:$Rt2, imm:$CRm)]>;
3718 /* from coprocessor to ARM core register */
3719 def t2MRRC : t2MovRRCopro<0b1110, "mrrc", 1>;
3721 def t2MRRC2 : t2MovRRCopro<0b1111, "mrrc2", 1>;
3723 //===----------------------------------------------------------------------===//
3724 // Other Coprocessor Instructions.
3727 def tCDP : T2Cop<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1,
3728 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
3729 "cdp\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
3730 [(int_arm_cdp imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
3731 imm:$CRm, imm:$opc2)]> {
3732 let Inst{27-24} = 0b1110;
3741 let Inst{3-0} = CRm;
3743 let Inst{7-5} = opc2;
3744 let Inst{11-8} = cop;
3745 let Inst{15-12} = CRd;
3746 let Inst{19-16} = CRn;
3747 let Inst{23-20} = opc1;
3750 def t2CDP2 : T2Cop<0b1111, (outs), (ins p_imm:$cop, imm0_15:$opc1,
3751 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
3752 "cdp2\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
3753 [(int_arm_cdp2 imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
3754 imm:$CRm, imm:$opc2)]> {
3755 let Inst{27-24} = 0b1110;
3764 let Inst{3-0} = CRm;
3766 let Inst{7-5} = opc2;
3767 let Inst{11-8} = cop;
3768 let Inst{15-12} = CRd;
3769 let Inst{19-16} = CRn;
3770 let Inst{23-20} = opc1;
3775 //===----------------------------------------------------------------------===//
3776 // Non-Instruction Patterns
3779 // SXT/UXT with no rotate
3780 let AddedComplexity = 16 in {
3781 def : T2Pat<(and rGPR:$Rm, 0x000000FF), (t2UXTB rGPR:$Rm, 0)>,
3782 Requires<[IsThumb2]>;
3783 def : T2Pat<(and rGPR:$Rm, 0x0000FFFF), (t2UXTH rGPR:$Rm, 0)>,
3784 Requires<[IsThumb2]>;
3785 def : T2Pat<(and rGPR:$Rm, 0x00FF00FF), (t2UXTB16 rGPR:$Rm, 0)>,
3786 Requires<[HasT2ExtractPack, IsThumb2]>;
3787 def : T2Pat<(add rGPR:$Rn, (and rGPR:$Rm, 0x00FF)),
3788 (t2UXTAB rGPR:$Rn, rGPR:$Rm, 0)>,
3789 Requires<[HasT2ExtractPack, IsThumb2]>;
3790 def : T2Pat<(add rGPR:$Rn, (and rGPR:$Rm, 0xFFFF)),
3791 (t2UXTAH rGPR:$Rn, rGPR:$Rm, 0)>,
3792 Requires<[HasT2ExtractPack, IsThumb2]>;
3795 def : T2Pat<(sext_inreg rGPR:$Src, i8), (t2SXTB rGPR:$Src, 0)>,
3796 Requires<[IsThumb2]>;
3797 def : T2Pat<(sext_inreg rGPR:$Src, i16), (t2SXTH rGPR:$Src, 0)>,
3798 Requires<[IsThumb2]>;
3799 def : T2Pat<(add rGPR:$Rn, (sext_inreg rGPR:$Rm, i8)),
3800 (t2SXTAB rGPR:$Rn, rGPR:$Rm, 0)>,
3801 Requires<[HasT2ExtractPack, IsThumb2]>;
3802 def : T2Pat<(add rGPR:$Rn, (sext_inreg rGPR:$Rm, i16)),
3803 (t2SXTAH rGPR:$Rn, rGPR:$Rm, 0)>,
3804 Requires<[HasT2ExtractPack, IsThumb2]>;
3806 // Atomic load/store patterns
3807 def : T2Pat<(atomic_load_8 t2addrmode_imm12:$addr),
3808 (t2LDRBi12 t2addrmode_imm12:$addr)>;
3809 def : T2Pat<(atomic_load_8 t2addrmode_negimm8:$addr),
3810 (t2LDRBi8 t2addrmode_negimm8:$addr)>;
3811 def : T2Pat<(atomic_load_8 t2addrmode_so_reg:$addr),
3812 (t2LDRBs t2addrmode_so_reg:$addr)>;
3813 def : T2Pat<(atomic_load_16 t2addrmode_imm12:$addr),
3814 (t2LDRHi12 t2addrmode_imm12:$addr)>;
3815 def : T2Pat<(atomic_load_16 t2addrmode_negimm8:$addr),
3816 (t2LDRHi8 t2addrmode_negimm8:$addr)>;
3817 def : T2Pat<(atomic_load_16 t2addrmode_so_reg:$addr),
3818 (t2LDRHs t2addrmode_so_reg:$addr)>;
3819 def : T2Pat<(atomic_load_32 t2addrmode_imm12:$addr),
3820 (t2LDRi12 t2addrmode_imm12:$addr)>;
3821 def : T2Pat<(atomic_load_32 t2addrmode_negimm8:$addr),
3822 (t2LDRi8 t2addrmode_negimm8:$addr)>;
3823 def : T2Pat<(atomic_load_32 t2addrmode_so_reg:$addr),
3824 (t2LDRs t2addrmode_so_reg:$addr)>;
3825 def : T2Pat<(atomic_store_8 t2addrmode_imm12:$addr, GPR:$val),
3826 (t2STRBi12 GPR:$val, t2addrmode_imm12:$addr)>;
3827 def : T2Pat<(atomic_store_8 t2addrmode_negimm8:$addr, GPR:$val),
3828 (t2STRBi8 GPR:$val, t2addrmode_negimm8:$addr)>;
3829 def : T2Pat<(atomic_store_8 t2addrmode_so_reg:$addr, GPR:$val),
3830 (t2STRBs GPR:$val, t2addrmode_so_reg:$addr)>;
3831 def : T2Pat<(atomic_store_16 t2addrmode_imm12:$addr, GPR:$val),
3832 (t2STRHi12 GPR:$val, t2addrmode_imm12:$addr)>;
3833 def : T2Pat<(atomic_store_16 t2addrmode_negimm8:$addr, GPR:$val),
3834 (t2STRHi8 GPR:$val, t2addrmode_negimm8:$addr)>;
3835 def : T2Pat<(atomic_store_16 t2addrmode_so_reg:$addr, GPR:$val),
3836 (t2STRHs GPR:$val, t2addrmode_so_reg:$addr)>;
3837 def : T2Pat<(atomic_store_32 t2addrmode_imm12:$addr, GPR:$val),
3838 (t2STRi12 GPR:$val, t2addrmode_imm12:$addr)>;
3839 def : T2Pat<(atomic_store_32 t2addrmode_negimm8:$addr, GPR:$val),
3840 (t2STRi8 GPR:$val, t2addrmode_negimm8:$addr)>;
3841 def : T2Pat<(atomic_store_32 t2addrmode_so_reg:$addr, GPR:$val),
3842 (t2STRs GPR:$val, t2addrmode_so_reg:$addr)>;
3845 //===----------------------------------------------------------------------===//
3846 // Assembler aliases
3849 // Aliases for ADC without the ".w" optional width specifier.
3850 def : t2InstAlias<"adc${s}${p} $Rd, $Rn, $Rm",
3851 (t2ADCrr rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, pred:$p, cc_out:$s)>;
3852 def : t2InstAlias<"adc${s}${p} $Rd, $Rn, $ShiftedRm",
3853 (t2ADCrs rGPR:$Rd, rGPR:$Rn, t2_so_reg:$ShiftedRm,
3854 pred:$p, cc_out:$s)>;
3856 // Aliases for SBC without the ".w" optional width specifier.
3857 def : t2InstAlias<"sbc${s}${p} $Rd, $Rn, $Rm",
3858 (t2SBCrr rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, pred:$p, cc_out:$s)>;
3859 def : t2InstAlias<"sbc${s}${p} $Rd, $Rn, $ShiftedRm",
3860 (t2SBCrs rGPR:$Rd, rGPR:$Rn, t2_so_reg:$ShiftedRm,
3861 pred:$p, cc_out:$s)>;
3863 // Aliases for ADD without the ".w" optional width specifier.
3864 def : t2InstAlias<"add${s}${p} $Rd, $Rn, $imm",
3865 (t2ADDri GPRnopc:$Rd, GPRnopc:$Rn, t2_so_imm:$imm, pred:$p, cc_out:$s)>;
3866 def : t2InstAlias<"add${p} $Rd, $Rn, $imm",
3867 (t2ADDri12 GPRnopc:$Rd, GPR:$Rn, imm0_4095:$imm, pred:$p)>;
3868 def : t2InstAlias<"add${s}${p} $Rd, $Rn, $Rm",
3869 (t2ADDrr GPRnopc:$Rd, GPRnopc:$Rn, rGPR:$Rm, pred:$p, cc_out:$s)>;
3870 def : t2InstAlias<"add${s}${p} $Rd, $Rn, $ShiftedRm",
3871 (t2ADDrs GPRnopc:$Rd, GPRnopc:$Rn, t2_so_reg:$ShiftedRm,
3872 pred:$p, cc_out:$s)>;
3873 // ... and with the destination and source register combined.
3874 def : t2InstAlias<"add${s}${p} $Rdn, $imm",
3875 (t2ADDri GPRnopc:$Rdn, GPRnopc:$Rdn, t2_so_imm:$imm, pred:$p, cc_out:$s)>;
3876 def : t2InstAlias<"add${p} $Rdn, $imm",
3877 (t2ADDri12 GPRnopc:$Rdn, GPRnopc:$Rdn, imm0_4095:$imm, pred:$p)>;
3878 def : t2InstAlias<"add${s}${p} $Rdn, $Rm",
3879 (t2ADDrr GPRnopc:$Rdn, GPRnopc:$Rdn, rGPR:$Rm, pred:$p, cc_out:$s)>;
3880 def : t2InstAlias<"add${s}${p} $Rdn, $ShiftedRm",
3881 (t2ADDrs GPRnopc:$Rdn, GPRnopc:$Rdn, t2_so_reg:$ShiftedRm,
3882 pred:$p, cc_out:$s)>;
3884 // Aliases for SUB without the ".w" optional width specifier.
3885 def : t2InstAlias<"sub${s}${p} $Rd, $Rn, $imm",
3886 (t2SUBri GPRnopc:$Rd, GPRnopc:$Rn, t2_so_imm:$imm, pred:$p, cc_out:$s)>;
3887 def : t2InstAlias<"sub${p} $Rd, $Rn, $imm",
3888 (t2SUBri12 GPRnopc:$Rd, GPR:$Rn, imm0_4095:$imm, pred:$p)>;
3889 def : t2InstAlias<"sub${s}${p} $Rd, $Rn, $Rm",
3890 (t2SUBrr GPRnopc:$Rd, GPRnopc:$Rn, rGPR:$Rm, pred:$p, cc_out:$s)>;
3891 def : t2InstAlias<"sub${s}${p} $Rd, $Rn, $ShiftedRm",
3892 (t2SUBrs GPRnopc:$Rd, GPRnopc:$Rn, t2_so_reg:$ShiftedRm,
3893 pred:$p, cc_out:$s)>;
3894 // ... and with the destination and source register combined.
3895 def : t2InstAlias<"sub${s}${p} $Rdn, $imm",
3896 (t2SUBri GPRnopc:$Rdn, GPRnopc:$Rdn, t2_so_imm:$imm, pred:$p, cc_out:$s)>;
3897 def : t2InstAlias<"sub${p} $Rdn, $imm",
3898 (t2SUBri12 GPRnopc:$Rdn, GPRnopc:$Rdn, imm0_4095:$imm, pred:$p)>;
3899 def : t2InstAlias<"sub${s}${p} $Rdn, $Rm",
3900 (t2SUBrr GPRnopc:$Rdn, GPRnopc:$Rdn, rGPR:$Rm, pred:$p, cc_out:$s)>;
3901 def : t2InstAlias<"sub${s}${p} $Rdn, $ShiftedRm",
3902 (t2SUBrs GPRnopc:$Rdn, GPRnopc:$Rdn, t2_so_reg:$ShiftedRm,
3903 pred:$p, cc_out:$s)>;
3906 // Alias for compares without the ".w" optional width specifier.
3907 def : t2InstAlias<"cmn${p} $Rn, $Rm",
3908 (t2CMNzrr GPRnopc:$Rn, rGPR:$Rm, pred:$p)>;
3909 def : t2InstAlias<"teq${p} $Rn, $Rm",
3910 (t2TEQrr GPRnopc:$Rn, rGPR:$Rm, pred:$p)>;
3911 def : t2InstAlias<"tst${p} $Rn, $Rm",
3912 (t2TSTrr GPRnopc:$Rn, rGPR:$Rm, pred:$p)>;
3915 def : InstAlias<"dmb", (t2DMB 0xf)>, Requires<[IsThumb2, HasDB]>;
3916 def : InstAlias<"dsb", (t2DSB 0xf)>, Requires<[IsThumb2, HasDB]>;
3917 def : InstAlias<"isb", (t2ISB 0xf)>, Requires<[IsThumb2, HasDB]>;
3919 // Alias for LDR, LDRB, LDRH, LDRSB, and LDRSH without the ".w" optional
3921 def : t2InstAlias<"ldr${p} $Rt, $addr",
3922 (t2LDRi12 GPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
3923 def : t2InstAlias<"ldrb${p} $Rt, $addr",
3924 (t2LDRBi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
3925 def : t2InstAlias<"ldrh${p} $Rt, $addr",
3926 (t2LDRHi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
3927 def : t2InstAlias<"ldrsb${p} $Rt, $addr",
3928 (t2LDRSBi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
3929 def : t2InstAlias<"ldrsh${p} $Rt, $addr",
3930 (t2LDRSHi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
3932 def : t2InstAlias<"ldr${p} $Rt, $addr",
3933 (t2LDRs GPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
3934 def : t2InstAlias<"ldrb${p} $Rt, $addr",
3935 (t2LDRBs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
3936 def : t2InstAlias<"ldrh${p} $Rt, $addr",
3937 (t2LDRHs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
3938 def : t2InstAlias<"ldrsb${p} $Rt, $addr",
3939 (t2LDRSBs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
3940 def : t2InstAlias<"ldrsh${p} $Rt, $addr",
3941 (t2LDRSHs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
3943 def : t2InstAlias<"ldr${p} $Rt, $addr",
3944 (t2LDRpci GPR:$Rt, t2ldrlabel:$addr, pred:$p)>;
3945 def : t2InstAlias<"ldrb${p} $Rt, $addr",
3946 (t2LDRBpci rGPR:$Rt, t2ldrlabel:$addr, pred:$p)>;
3947 def : t2InstAlias<"ldrh${p} $Rt, $addr",
3948 (t2LDRHpci rGPR:$Rt, t2ldrlabel:$addr, pred:$p)>;
3949 def : t2InstAlias<"ldrsb${p} $Rt, $addr",
3950 (t2LDRSBpci rGPR:$Rt, t2ldrlabel:$addr, pred:$p)>;
3951 def : t2InstAlias<"ldrsh${p} $Rt, $addr",
3952 (t2LDRSHpci rGPR:$Rt, t2ldrlabel:$addr, pred:$p)>;
3954 // Alias for MVN with(out) the ".w" optional width specifier.
3955 def : t2InstAlias<"mvn${s}${p}.w $Rd, $imm",
3956 (t2MVNi rGPR:$Rd, t2_so_imm:$imm, pred:$p, cc_out:$s)>;
3957 def : t2InstAlias<"mvn${s}${p} $Rd, $Rm",
3958 (t2MVNr rGPR:$Rd, rGPR:$Rm, pred:$p, cc_out:$s)>;
3959 def : t2InstAlias<"mvn${s}${p} $Rd, $ShiftedRm",
3960 (t2MVNs rGPR:$Rd, t2_so_reg:$ShiftedRm, pred:$p, cc_out:$s)>;
3962 // PKHBT/PKHTB with default shift amount. PKHTB is equivalent to PKHBT when the
3963 // shift amount is zero (i.e., unspecified).
3964 def : InstAlias<"pkhbt${p} $Rd, $Rn, $Rm",
3965 (t2PKHBT rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>,
3966 Requires<[HasT2ExtractPack, IsThumb2]>;
3967 def : InstAlias<"pkhtb${p} $Rd, $Rn, $Rm",
3968 (t2PKHBT rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>,
3969 Requires<[HasT2ExtractPack, IsThumb2]>;
3971 // PUSH/POP aliases for STM/LDM
3972 def : t2InstAlias<"push${p}.w $regs", (t2STMDB_UPD SP, pred:$p, reglist:$regs)>;
3973 def : t2InstAlias<"push${p} $regs", (t2STMDB_UPD SP, pred:$p, reglist:$regs)>;
3974 def : t2InstAlias<"pop${p}.w $regs", (t2LDMIA_UPD SP, pred:$p, reglist:$regs)>;
3975 def : t2InstAlias<"pop${p} $regs", (t2LDMIA_UPD SP, pred:$p, reglist:$regs)>;
3977 // STMIA/STMIA_UPD aliases w/o the optional .w suffix
3978 def : t2InstAlias<"stm${p} $Rn, $regs",
3979 (t2STMIA GPR:$Rn, pred:$p, reglist:$regs)>;
3980 def : t2InstAlias<"stm${p} $Rn!, $regs",
3981 (t2STMIA_UPD GPR:$Rn, pred:$p, reglist:$regs)>;
3983 // LDMIA/LDMIA_UPD aliases w/o the optional .w suffix
3984 def : t2InstAlias<"ldm${p} $Rn, $regs",
3985 (t2LDMIA GPR:$Rn, pred:$p, reglist:$regs)>;
3986 def : t2InstAlias<"ldm${p} $Rn!, $regs",
3987 (t2LDMIA_UPD GPR:$Rn, pred:$p, reglist:$regs)>;
3989 // STMDB/STMDB_UPD aliases w/ the optional .w suffix
3990 def : t2InstAlias<"stmdb${p}.w $Rn, $regs",
3991 (t2STMDB GPR:$Rn, pred:$p, reglist:$regs)>;
3992 def : t2InstAlias<"stmdb${p}.w $Rn!, $regs",
3993 (t2STMDB_UPD GPR:$Rn, pred:$p, reglist:$regs)>;
3995 // LDMDB/LDMDB_UPD aliases w/ the optional .w suffix
3996 def : t2InstAlias<"ldmdb${p}.w $Rn, $regs",
3997 (t2LDMDB GPR:$Rn, pred:$p, reglist:$regs)>;
3998 def : t2InstAlias<"ldmdb${p}.w $Rn!, $regs",
3999 (t2LDMDB_UPD GPR:$Rn, pred:$p, reglist:$regs)>;
4001 // Alias for REV/REV16/REVSH without the ".w" optional width specifier.
4002 def : t2InstAlias<"rev${p} $Rd, $Rm", (t2REV rGPR:$Rd, rGPR:$Rm, pred:$p)>;
4003 def : t2InstAlias<"rev16${p} $Rd, $Rm", (t2REV16 rGPR:$Rd, rGPR:$Rm, pred:$p)>;
4004 def : t2InstAlias<"revsh${p} $Rd, $Rm", (t2REVSH rGPR:$Rd, rGPR:$Rm, pred:$p)>;
4007 // Alias for RSB without the ".w" optional width specifier, and with optional
4008 // implied destination register.
4009 def : t2InstAlias<"rsb${s}${p} $Rd, $Rn, $imm",
4010 (t2RSBri rGPR:$Rd, rGPR:$Rn, t2_so_imm:$imm, pred:$p, cc_out:$s)>;
4011 def : t2InstAlias<"rsb${s}${p} $Rdn, $imm",
4012 (t2RSBri rGPR:$Rdn, rGPR:$Rdn, t2_so_imm:$imm, pred:$p, cc_out:$s)>;
4013 def : t2InstAlias<"rsb${s}${p} $Rdn, $Rm",
4014 (t2RSBrr rGPR:$Rdn, rGPR:$Rdn, rGPR:$Rm, pred:$p, cc_out:$s)>;
4015 def : t2InstAlias<"rsb${s}${p} $Rdn, $ShiftedRm",
4016 (t2RSBrs rGPR:$Rdn, rGPR:$Rdn, t2_so_reg:$ShiftedRm, pred:$p,
4019 // SSAT/USAT optional shift operand.
4020 def : t2InstAlias<"ssat${p} $Rd, $sat_imm, $Rn",
4021 (t2SSAT rGPR:$Rd, imm1_32:$sat_imm, rGPR:$Rn, 0, pred:$p)>;
4022 def : t2InstAlias<"usat${p} $Rd, $sat_imm, $Rn",
4023 (t2USAT rGPR:$Rd, imm0_31:$sat_imm, rGPR:$Rn, 0, pred:$p)>;
4025 // STM w/o the .w suffix.
4026 def : t2InstAlias<"stm${p} $Rn, $regs",
4027 (t2STMIA GPR:$Rn, pred:$p, reglist:$regs)>;
4029 // Alias for STR, STRB, and STRH without the ".w" optional
4031 def : t2InstAlias<"str${p} $Rt, $addr",
4032 (t2STRi12 GPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
4033 def : t2InstAlias<"strb${p} $Rt, $addr",
4034 (t2STRBi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
4035 def : t2InstAlias<"strh${p} $Rt, $addr",
4036 (t2STRHi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
4038 def : t2InstAlias<"str${p} $Rt, $addr",
4039 (t2STRs GPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
4040 def : t2InstAlias<"strb${p} $Rt, $addr",
4041 (t2STRBs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
4042 def : t2InstAlias<"strh${p} $Rt, $addr",
4043 (t2STRHs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
4045 // Extend instruction optional rotate operand.
4046 def : t2InstAlias<"sxtab${p} $Rd, $Rn, $Rm",
4047 (t2SXTAB rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>;
4048 def : t2InstAlias<"sxtah${p} $Rd, $Rn, $Rm",
4049 (t2SXTAH rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>;
4050 def : t2InstAlias<"sxtab16${p} $Rd, $Rn, $Rm",
4051 (t2SXTAB16 rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>;
4053 def : t2InstAlias<"sxtb${p} $Rd, $Rm",
4054 (t2SXTB rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
4055 def : t2InstAlias<"sxtb16${p} $Rd, $Rm",
4056 (t2SXTB16 rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
4057 def : t2InstAlias<"sxth${p} $Rd, $Rm",
4058 (t2SXTH rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
4059 def : t2InstAlias<"sxtb${p}.w $Rd, $Rm",
4060 (t2SXTB rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
4061 def : t2InstAlias<"sxth${p}.w $Rd, $Rm",
4062 (t2SXTH rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
4064 def : t2InstAlias<"uxtab${p} $Rd, $Rn, $Rm",
4065 (t2UXTAB rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>;
4066 def : t2InstAlias<"uxtah${p} $Rd, $Rn, $Rm",
4067 (t2UXTAH rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>;
4068 def : t2InstAlias<"uxtab16${p} $Rd, $Rn, $Rm",
4069 (t2UXTAB16 rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>;
4070 def : t2InstAlias<"uxtb${p} $Rd, $Rm",
4071 (t2UXTB rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
4072 def : t2InstAlias<"uxtb16${p} $Rd, $Rm",
4073 (t2UXTB16 rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
4074 def : t2InstAlias<"uxth${p} $Rd, $Rm",
4075 (t2UXTH rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
4077 def : t2InstAlias<"uxtb${p}.w $Rd, $Rm",
4078 (t2UXTB rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
4079 def : t2InstAlias<"uxth${p}.w $Rd, $Rm",
4080 (t2UXTH rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
4082 // Extend instruction w/o the ".w" optional width specifier.
4083 def : t2InstAlias<"uxtb${p} $Rd, $Rm$rot",
4084 (t2UXTB rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>;
4085 def : t2InstAlias<"uxtb16${p} $Rd, $Rm$rot",
4086 (t2UXTB16 rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>;
4087 def : t2InstAlias<"uxth${p} $Rd, $Rm$rot",
4088 (t2UXTH rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>;
4090 def : t2InstAlias<"sxtb${p} $Rd, $Rm$rot",
4091 (t2SXTB rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>;
4092 def : t2InstAlias<"sxtb16${p} $Rd, $Rm$rot",
4093 (t2SXTB16 rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>;
4094 def : t2InstAlias<"sxth${p} $Rd, $Rm$rot",
4095 (t2SXTH rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>;
4098 // "mov Rd, t2_so_imm_not" can be handled via "mvn" in assembly, just like
4100 def : t2InstAlias<"mov${p} $Rd, $imm",
4101 (t2MVNi rGPR:$Rd, t2_so_imm_not:$imm, pred:$p, zero_reg)>;
4102 def : t2InstAlias<"mvn${p} $Rd, $imm",
4103 (t2MOVi rGPR:$Rd, t2_so_imm_not:$imm, pred:$p, zero_reg)>;
4104 // Same for AND <--> BIC
4105 def : t2InstAlias<"bic${s}${p} $Rd, $Rn, $imm",
4106 (t2ANDri rGPR:$Rd, rGPR:$Rn, so_imm_not:$imm,
4107 pred:$p, cc_out:$s)>;
4108 def : t2InstAlias<"bic${s}${p} $Rdn, $imm",
4109 (t2ANDri rGPR:$Rdn, rGPR:$Rdn, so_imm_not:$imm,
4110 pred:$p, cc_out:$s)>;
4111 def : t2InstAlias<"and${s}${p} $Rd, $Rn, $imm",
4112 (t2BICri rGPR:$Rd, rGPR:$Rn, so_imm_not:$imm,
4113 pred:$p, cc_out:$s)>;
4114 def : t2InstAlias<"and${s}${p} $Rdn, $imm",
4115 (t2BICri rGPR:$Rdn, rGPR:$Rdn, so_imm_not:$imm,
4116 pred:$p, cc_out:$s)>;
4117 // Likewise, "add Rd, t2_so_imm_neg" -> sub
4118 def : t2InstAlias<"add${s}${p} $Rd, $Rn, $imm",
4119 (t2SUBri GPRnopc:$Rd, GPRnopc:$Rn, t2_so_imm_neg:$imm,
4120 pred:$p, cc_out:$s)>;
4121 def : t2InstAlias<"add${s}${p} $Rd, $imm",
4122 (t2SUBri GPRnopc:$Rd, GPRnopc:$Rd, t2_so_imm_neg:$imm,
4123 pred:$p, cc_out:$s)>;
4124 // Same for CMP <--> CMN via t2_so_imm_neg
4125 def : t2InstAlias<"cmp${p} $Rd, $imm",
4126 (t2CMNzri rGPR:$Rd, t2_so_imm_neg:$imm, pred:$p)>;
4127 def : t2InstAlias<"cmn${p} $Rd, $imm",
4128 (t2CMPri rGPR:$Rd, t2_so_imm_neg:$imm, pred:$p)>;
4131 // Wide 'mul' encoding can be specified with only two operands.
4132 def : t2InstAlias<"mul${p} $Rn, $Rm",
4133 (t2MUL rGPR:$Rn, rGPR:$Rm, rGPR:$Rn, pred:$p)>;
4135 // "neg" is and alias for "rsb rd, rn, #0"
4136 def : t2InstAlias<"neg${s}${p} $Rd, $Rm",
4137 (t2RSBri rGPR:$Rd, rGPR:$Rm, 0, pred:$p, cc_out:$s)>;
4139 // MOV so_reg assembler pseudos. InstAlias isn't expressive enough for
4140 // these, unfortunately.
4141 def t2MOVsi: t2AsmPseudo<"mov${p} $Rd, $shift",
4142 (ins rGPR:$Rd, t2_so_reg:$shift, pred:$p)>;
4143 def t2MOVSsi: t2AsmPseudo<"movs${p} $Rd, $shift",
4144 (ins rGPR:$Rd, t2_so_reg:$shift, pred:$p)>;
4146 def t2MOVsr: t2AsmPseudo<"mov${p} $Rd, $shift",
4147 (ins rGPR:$Rd, so_reg_reg:$shift, pred:$p)>;
4148 def t2MOVSsr: t2AsmPseudo<"movs${p} $Rd, $shift",
4149 (ins rGPR:$Rd, so_reg_reg:$shift, pred:$p)>;
4151 // ADR w/o the .w suffix
4152 def : t2InstAlias<"adr${p} $Rd, $addr",
4153 (t2ADR rGPR:$Rd, t2adrlabel:$addr, pred:$p)>;