1 //===-- ARMInstrThumb2.td - Thumb2 support for ARM ---------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Thumb2 instruction set.
12 //===----------------------------------------------------------------------===//
14 // IT block predicate field
15 def it_pred_asmoperand : AsmOperandClass {
16 let Name = "ITCondCode";
17 let ParserMethod = "parseITCondCode";
19 def it_pred : Operand<i32> {
20 let PrintMethod = "printMandatoryPredicateOperand";
21 let ParserMatchClass = it_pred_asmoperand;
24 // IT block condition mask
25 def it_mask_asmoperand : AsmOperandClass { let Name = "ITMask"; }
26 def it_mask : Operand<i32> {
27 let PrintMethod = "printThumbITMask";
28 let ParserMatchClass = it_mask_asmoperand;
31 // t2_shift_imm: An integer that encodes a shift amount and the type of shift
32 // (asr or lsl). The 6-bit immediate encodes as:
35 // {4-0} imm5 shift amount.
36 // asr #32 not allowed
37 def t2_shift_imm : Operand<i32> {
38 let PrintMethod = "printShiftImmOperand";
39 let ParserMatchClass = ShifterImmAsmOperand;
40 let DecoderMethod = "DecodeT2ShifterImmOperand";
43 // Shifted operands. No register controlled shifts for Thumb2.
44 // Note: We do not support rrx shifted operands yet.
45 def t2_so_reg : Operand<i32>, // reg imm
46 ComplexPattern<i32, 2, "SelectT2ShifterOperandReg",
48 let EncoderMethod = "getT2SORegOpValue";
49 let PrintMethod = "printT2SOOperand";
50 let DecoderMethod = "DecodeSORegImmOperand";
51 let ParserMatchClass = ShiftedImmAsmOperand;
52 let MIOperandInfo = (ops rGPR, i32imm);
55 // t2_so_imm_not_XFORM - Return the complement of a t2_so_imm value
56 def t2_so_imm_not_XFORM : SDNodeXForm<imm, [{
57 return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), MVT::i32);
60 // t2_so_imm_neg_XFORM - Return the negation of a t2_so_imm value
61 def t2_so_imm_neg_XFORM : SDNodeXForm<imm, [{
62 return CurDAG->getTargetConstant(-((int)N->getZExtValue()), MVT::i32);
65 // so_imm_notSext_XFORM - Return a so_imm value packed into the format
66 // described for so_imm_notSext def below, with sign extension from 16
68 def t2_so_imm_notSext16_XFORM : SDNodeXForm<imm, [{
69 APInt apIntN = N->getAPIntValue();
70 unsigned N16bitSignExt = apIntN.trunc(16).sext(32).getZExtValue();
71 return CurDAG->getTargetConstant(~N16bitSignExt, MVT::i32);
74 // t2_so_imm - Match a 32-bit immediate operand, which is an
75 // 8-bit immediate rotated by an arbitrary number of bits, or an 8-bit
76 // immediate splatted into multiple bytes of the word.
77 def t2_so_imm_asmoperand : ImmAsmOperand { let Name = "T2SOImm"; }
78 def t2_so_imm : Operand<i32>, ImmLeaf<i32, [{
79 return ARM_AM::getT2SOImmVal(Imm) != -1;
81 let ParserMatchClass = t2_so_imm_asmoperand;
82 let EncoderMethod = "getT2SOImmOpValue";
83 let DecoderMethod = "DecodeT2SOImm";
86 // t2_so_imm_not - Match an immediate that is a complement
88 // Note: this pattern doesn't require an encoder method and such, as it's
89 // only used on aliases (Pat<> and InstAlias<>). The actual encoding
90 // is handled by the destination instructions, which use t2_so_imm.
91 def t2_so_imm_not_asmoperand : AsmOperandClass { let Name = "T2SOImmNot"; }
92 def t2_so_imm_not : Operand<i32>, PatLeaf<(imm), [{
93 return ARM_AM::getT2SOImmVal(~((uint32_t)N->getZExtValue())) != -1;
94 }], t2_so_imm_not_XFORM> {
95 let ParserMatchClass = t2_so_imm_not_asmoperand;
98 // t2_so_imm_notSext - match an immediate that is a complement of a t2_so_imm
99 // if the upper 16 bits are zero.
100 def t2_so_imm_notSext : Operand<i32>, PatLeaf<(imm), [{
101 APInt apIntN = N->getAPIntValue();
102 if (!apIntN.isIntN(16)) return false;
103 unsigned N16bitSignExt = apIntN.trunc(16).sext(32).getZExtValue();
104 return ARM_AM::getT2SOImmVal(~N16bitSignExt) != -1;
105 }], t2_so_imm_notSext16_XFORM> {
106 let ParserMatchClass = t2_so_imm_not_asmoperand;
109 // t2_so_imm_neg - Match an immediate that is a negation of a t2_so_imm.
110 def t2_so_imm_neg_asmoperand : AsmOperandClass { let Name = "T2SOImmNeg"; }
111 def t2_so_imm_neg : Operand<i32>, PatLeaf<(imm), [{
112 int64_t Value = -(int)N->getZExtValue();
113 return Value && ARM_AM::getT2SOImmVal(Value) != -1;
114 }], t2_so_imm_neg_XFORM> {
115 let ParserMatchClass = t2_so_imm_neg_asmoperand;
118 /// imm0_4095 predicate - True if the 32-bit immediate is in the range [0.4095].
119 def imm0_4095_asmoperand: ImmAsmOperand { let Name = "Imm0_4095"; }
120 def imm0_4095 : Operand<i32>, ImmLeaf<i32, [{
121 return Imm >= 0 && Imm < 4096;
123 let ParserMatchClass = imm0_4095_asmoperand;
126 def imm0_4095_neg_asmoperand: AsmOperandClass { let Name = "Imm0_4095Neg"; }
127 def imm0_4095_neg : Operand<i32>, PatLeaf<(i32 imm), [{
128 return (uint32_t)(-N->getZExtValue()) < 4096;
130 let ParserMatchClass = imm0_4095_neg_asmoperand;
133 def imm1_255_neg : PatLeaf<(i32 imm), [{
134 uint32_t Val = -N->getZExtValue();
135 return (Val > 0 && Val < 255);
138 def imm0_255_not : PatLeaf<(i32 imm), [{
139 return (uint32_t)(~N->getZExtValue()) < 255;
142 def lo5AllOne : PatLeaf<(i32 imm), [{
143 // Returns true if all low 5-bits are 1.
144 return (((uint32_t)N->getZExtValue()) & 0x1FUL) == 0x1FUL;
147 // Define Thumb2 specific addressing modes.
149 // t2addrmode_imm12 := reg + imm12
150 def t2addrmode_imm12_asmoperand : AsmOperandClass {let Name="MemUImm12Offset";}
151 def t2addrmode_imm12 : Operand<i32>,
152 ComplexPattern<i32, 2, "SelectT2AddrModeImm12", []> {
153 let PrintMethod = "printAddrModeImm12Operand<false>";
154 let EncoderMethod = "getAddrModeImm12OpValue";
155 let DecoderMethod = "DecodeT2AddrModeImm12";
156 let ParserMatchClass = t2addrmode_imm12_asmoperand;
157 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
160 // t2ldrlabel := imm12
161 def t2ldrlabel : Operand<i32> {
162 let EncoderMethod = "getAddrModeImm12OpValue";
163 let PrintMethod = "printThumbLdrLabelOperand";
166 def t2ldr_pcrel_imm12_asmoperand : AsmOperandClass {let Name = "MemPCRelImm12";}
167 def t2ldr_pcrel_imm12 : Operand<i32> {
168 let ParserMatchClass = t2ldr_pcrel_imm12_asmoperand;
169 // used for assembler pseudo instruction and maps to t2ldrlabel, so
170 // doesn't need encoder or print methods of its own.
173 // ADR instruction labels.
174 def t2adrlabel : Operand<i32> {
175 let EncoderMethod = "getT2AdrLabelOpValue";
176 let PrintMethod = "printAdrLabelOperand";
180 // t2addrmode_posimm8 := reg + imm8
181 def MemPosImm8OffsetAsmOperand : AsmOperandClass {let Name="MemPosImm8Offset";}
182 def t2addrmode_posimm8 : Operand<i32> {
183 let PrintMethod = "printT2AddrModeImm8Operand";
184 let EncoderMethod = "getT2AddrModeImm8OpValue";
185 let DecoderMethod = "DecodeT2AddrModeImm8";
186 let ParserMatchClass = MemPosImm8OffsetAsmOperand;
187 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
190 // t2addrmode_negimm8 := reg - imm8
191 def MemNegImm8OffsetAsmOperand : AsmOperandClass {let Name="MemNegImm8Offset";}
192 def t2addrmode_negimm8 : Operand<i32>,
193 ComplexPattern<i32, 2, "SelectT2AddrModeImm8", []> {
194 let PrintMethod = "printT2AddrModeImm8Operand";
195 let EncoderMethod = "getT2AddrModeImm8OpValue";
196 let DecoderMethod = "DecodeT2AddrModeImm8";
197 let ParserMatchClass = MemNegImm8OffsetAsmOperand;
198 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
201 // t2addrmode_imm8 := reg +/- imm8
202 def MemImm8OffsetAsmOperand : AsmOperandClass { let Name = "MemImm8Offset"; }
203 def t2addrmode_imm8 : Operand<i32>,
204 ComplexPattern<i32, 2, "SelectT2AddrModeImm8", []> {
205 let PrintMethod = "printT2AddrModeImm8Operand";
206 let EncoderMethod = "getT2AddrModeImm8OpValue";
207 let DecoderMethod = "DecodeT2AddrModeImm8";
208 let ParserMatchClass = MemImm8OffsetAsmOperand;
209 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
212 def t2am_imm8_offset : Operand<i32>,
213 ComplexPattern<i32, 1, "SelectT2AddrModeImm8Offset",
214 [], [SDNPWantRoot]> {
215 let PrintMethod = "printT2AddrModeImm8OffsetOperand";
216 let EncoderMethod = "getT2AddrModeImm8OffsetOpValue";
217 let DecoderMethod = "DecodeT2Imm8";
220 // t2addrmode_imm8s4 := reg +/- (imm8 << 2)
221 def MemImm8s4OffsetAsmOperand : AsmOperandClass {let Name = "MemImm8s4Offset";}
222 def t2addrmode_imm8s4 : Operand<i32> {
223 let PrintMethod = "printT2AddrModeImm8s4Operand";
224 let EncoderMethod = "getT2AddrModeImm8s4OpValue";
225 let DecoderMethod = "DecodeT2AddrModeImm8s4";
226 let ParserMatchClass = MemImm8s4OffsetAsmOperand;
227 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
230 def t2am_imm8s4_offset_asmoperand : AsmOperandClass { let Name = "Imm8s4"; }
231 def t2am_imm8s4_offset : Operand<i32> {
232 let PrintMethod = "printT2AddrModeImm8s4OffsetOperand";
233 let EncoderMethod = "getT2Imm8s4OpValue";
234 let DecoderMethod = "DecodeT2Imm8S4";
237 // t2addrmode_imm0_1020s4 := reg + (imm8 << 2)
238 def MemImm0_1020s4OffsetAsmOperand : AsmOperandClass {
239 let Name = "MemImm0_1020s4Offset";
241 def t2addrmode_imm0_1020s4 : Operand<i32> {
242 let PrintMethod = "printT2AddrModeImm0_1020s4Operand";
243 let EncoderMethod = "getT2AddrModeImm0_1020s4OpValue";
244 let DecoderMethod = "DecodeT2AddrModeImm0_1020s4";
245 let ParserMatchClass = MemImm0_1020s4OffsetAsmOperand;
246 let MIOperandInfo = (ops GPRnopc:$base, i32imm:$offsimm);
249 // t2addrmode_so_reg := reg + (reg << imm2)
250 def t2addrmode_so_reg_asmoperand : AsmOperandClass {let Name="T2MemRegOffset";}
251 def t2addrmode_so_reg : Operand<i32>,
252 ComplexPattern<i32, 3, "SelectT2AddrModeSoReg", []> {
253 let PrintMethod = "printT2AddrModeSoRegOperand";
254 let EncoderMethod = "getT2AddrModeSORegOpValue";
255 let DecoderMethod = "DecodeT2AddrModeSOReg";
256 let ParserMatchClass = t2addrmode_so_reg_asmoperand;
257 let MIOperandInfo = (ops GPR:$base, rGPR:$offsreg, i32imm:$offsimm);
260 // Addresses for the TBB/TBH instructions.
261 def addrmode_tbb_asmoperand : AsmOperandClass { let Name = "MemTBB"; }
262 def addrmode_tbb : Operand<i32> {
263 let PrintMethod = "printAddrModeTBB";
264 let ParserMatchClass = addrmode_tbb_asmoperand;
265 let MIOperandInfo = (ops GPR:$Rn, rGPR:$Rm);
267 def addrmode_tbh_asmoperand : AsmOperandClass { let Name = "MemTBH"; }
268 def addrmode_tbh : Operand<i32> {
269 let PrintMethod = "printAddrModeTBH";
270 let ParserMatchClass = addrmode_tbh_asmoperand;
271 let MIOperandInfo = (ops GPR:$Rn, rGPR:$Rm);
274 //===----------------------------------------------------------------------===//
275 // Multiclass helpers...
279 class T2OneRegImm<dag oops, dag iops, InstrItinClass itin,
280 string opc, string asm, list<dag> pattern>
281 : T2I<oops, iops, itin, opc, asm, pattern> {
286 let Inst{26} = imm{11};
287 let Inst{14-12} = imm{10-8};
288 let Inst{7-0} = imm{7-0};
292 class T2sOneRegImm<dag oops, dag iops, InstrItinClass itin,
293 string opc, string asm, list<dag> pattern>
294 : T2sI<oops, iops, itin, opc, asm, pattern> {
300 let Inst{26} = imm{11};
301 let Inst{14-12} = imm{10-8};
302 let Inst{7-0} = imm{7-0};
305 class T2OneRegCmpImm<dag oops, dag iops, InstrItinClass itin,
306 string opc, string asm, list<dag> pattern>
307 : T2I<oops, iops, itin, opc, asm, pattern> {
311 let Inst{19-16} = Rn;
312 let Inst{26} = imm{11};
313 let Inst{14-12} = imm{10-8};
314 let Inst{7-0} = imm{7-0};
318 class T2OneRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
319 string opc, string asm, list<dag> pattern>
320 : T2I<oops, iops, itin, opc, asm, pattern> {
325 let Inst{3-0} = ShiftedRm{3-0};
326 let Inst{5-4} = ShiftedRm{6-5};
327 let Inst{14-12} = ShiftedRm{11-9};
328 let Inst{7-6} = ShiftedRm{8-7};
331 class T2sOneRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
332 string opc, string asm, list<dag> pattern>
333 : T2sI<oops, iops, itin, opc, asm, pattern> {
338 let Inst{3-0} = ShiftedRm{3-0};
339 let Inst{5-4} = ShiftedRm{6-5};
340 let Inst{14-12} = ShiftedRm{11-9};
341 let Inst{7-6} = ShiftedRm{8-7};
344 class T2OneRegCmpShiftedReg<dag oops, dag iops, InstrItinClass itin,
345 string opc, string asm, list<dag> pattern>
346 : T2I<oops, iops, itin, opc, asm, pattern> {
350 let Inst{19-16} = Rn;
351 let Inst{3-0} = ShiftedRm{3-0};
352 let Inst{5-4} = ShiftedRm{6-5};
353 let Inst{14-12} = ShiftedRm{11-9};
354 let Inst{7-6} = ShiftedRm{8-7};
357 class T2TwoReg<dag oops, dag iops, InstrItinClass itin,
358 string opc, string asm, list<dag> pattern>
359 : T2I<oops, iops, itin, opc, asm, pattern> {
367 class T2sTwoReg<dag oops, dag iops, InstrItinClass itin,
368 string opc, string asm, list<dag> pattern>
369 : T2sI<oops, iops, itin, opc, asm, pattern> {
377 class T2TwoRegCmp<dag oops, dag iops, InstrItinClass itin,
378 string opc, string asm, list<dag> pattern>
379 : T2I<oops, iops, itin, opc, asm, pattern> {
383 let Inst{19-16} = Rn;
388 class T2TwoRegImm<dag oops, dag iops, InstrItinClass itin,
389 string opc, string asm, list<dag> pattern>
390 : T2I<oops, iops, itin, opc, asm, pattern> {
396 let Inst{19-16} = Rn;
397 let Inst{26} = imm{11};
398 let Inst{14-12} = imm{10-8};
399 let Inst{7-0} = imm{7-0};
402 class T2sTwoRegImm<dag oops, dag iops, InstrItinClass itin,
403 string opc, string asm, list<dag> pattern>
404 : T2sI<oops, iops, itin, opc, asm, pattern> {
410 let Inst{19-16} = Rn;
411 let Inst{26} = imm{11};
412 let Inst{14-12} = imm{10-8};
413 let Inst{7-0} = imm{7-0};
416 class T2TwoRegShiftImm<dag oops, dag iops, InstrItinClass itin,
417 string opc, string asm, list<dag> pattern>
418 : T2I<oops, iops, itin, opc, asm, pattern> {
425 let Inst{14-12} = imm{4-2};
426 let Inst{7-6} = imm{1-0};
429 class T2sTwoRegShiftImm<dag oops, dag iops, InstrItinClass itin,
430 string opc, string asm, list<dag> pattern>
431 : T2sI<oops, iops, itin, opc, asm, pattern> {
438 let Inst{14-12} = imm{4-2};
439 let Inst{7-6} = imm{1-0};
442 class T2ThreeReg<dag oops, dag iops, InstrItinClass itin,
443 string opc, string asm, list<dag> pattern>
444 : T2I<oops, iops, itin, opc, asm, pattern> {
450 let Inst{19-16} = Rn;
454 class T2sThreeReg<dag oops, dag iops, InstrItinClass itin,
455 string opc, string asm, list<dag> pattern>
456 : T2sI<oops, iops, itin, opc, asm, pattern> {
462 let Inst{19-16} = Rn;
466 class T2TwoRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
467 string opc, string asm, list<dag> pattern>
468 : T2I<oops, iops, itin, opc, asm, pattern> {
474 let Inst{19-16} = Rn;
475 let Inst{3-0} = ShiftedRm{3-0};
476 let Inst{5-4} = ShiftedRm{6-5};
477 let Inst{14-12} = ShiftedRm{11-9};
478 let Inst{7-6} = ShiftedRm{8-7};
481 class T2sTwoRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
482 string opc, string asm, list<dag> pattern>
483 : T2sI<oops, iops, itin, opc, asm, pattern> {
489 let Inst{19-16} = Rn;
490 let Inst{3-0} = ShiftedRm{3-0};
491 let Inst{5-4} = ShiftedRm{6-5};
492 let Inst{14-12} = ShiftedRm{11-9};
493 let Inst{7-6} = ShiftedRm{8-7};
496 class T2FourReg<dag oops, dag iops, InstrItinClass itin,
497 string opc, string asm, list<dag> pattern>
498 : T2I<oops, iops, itin, opc, asm, pattern> {
504 let Inst{19-16} = Rn;
505 let Inst{15-12} = Ra;
510 class T2MulLong<bits<3> opc22_20, bits<4> opc7_4,
511 dag oops, dag iops, InstrItinClass itin,
512 string opc, string asm, list<dag> pattern>
513 : T2I<oops, iops, itin, opc, asm, pattern> {
519 let Inst{31-23} = 0b111110111;
520 let Inst{22-20} = opc22_20;
521 let Inst{19-16} = Rn;
522 let Inst{15-12} = RdLo;
523 let Inst{11-8} = RdHi;
524 let Inst{7-4} = opc7_4;
527 class T2MlaLong<bits<3> opc22_20, bits<4> opc7_4,
528 dag oops, dag iops, InstrItinClass itin,
529 string opc, string asm, list<dag> pattern>
530 : T2I<oops, iops, itin, opc, asm, pattern> {
536 let Inst{31-23} = 0b111110111;
537 let Inst{22-20} = opc22_20;
538 let Inst{19-16} = Rn;
539 let Inst{15-12} = RdLo;
540 let Inst{11-8} = RdHi;
541 let Inst{7-4} = opc7_4;
546 /// T2I_bin_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a
547 /// binary operation that produces a value. These are predicable and can be
548 /// changed to modify CPSR.
549 multiclass T2I_bin_irs<bits<4> opcod, string opc,
550 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
551 PatFrag opnode, bit Commutable = 0,
554 def ri : T2sTwoRegImm<
555 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm), iii,
556 opc, "\t$Rd, $Rn, $imm",
557 [(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_imm:$imm))]>,
558 Sched<[WriteALU, ReadALU]> {
559 let Inst{31-27} = 0b11110;
561 let Inst{24-21} = opcod;
565 def rr : T2sThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), iir,
566 opc, !strconcat(wide, "\t$Rd, $Rn, $Rm"),
567 [(set rGPR:$Rd, (opnode rGPR:$Rn, rGPR:$Rm))]>,
568 Sched<[WriteALU, ReadALU, ReadALU]> {
569 let isCommutable = Commutable;
570 let Inst{31-27} = 0b11101;
571 let Inst{26-25} = 0b01;
572 let Inst{24-21} = opcod;
573 let Inst{14-12} = 0b000; // imm3
574 let Inst{7-6} = 0b00; // imm2
575 let Inst{5-4} = 0b00; // type
578 def rs : T2sTwoRegShiftedReg<
579 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm), iis,
580 opc, !strconcat(wide, "\t$Rd, $Rn, $ShiftedRm"),
581 [(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_reg:$ShiftedRm))]>,
582 Sched<[WriteALUsi, ReadALU]> {
583 let Inst{31-27} = 0b11101;
584 let Inst{26-25} = 0b01;
585 let Inst{24-21} = opcod;
587 // Assembly aliases for optional destination operand when it's the same
588 // as the source operand.
589 def : t2InstAlias<!strconcat(opc, "${s}${p} $Rdn, $imm"),
590 (!cast<Instruction>(NAME#"ri") rGPR:$Rdn, rGPR:$Rdn,
591 t2_so_imm:$imm, pred:$p,
593 def : t2InstAlias<!strconcat(opc, "${s}${p}", wide, " $Rdn, $Rm"),
594 (!cast<Instruction>(NAME#"rr") rGPR:$Rdn, rGPR:$Rdn,
597 def : t2InstAlias<!strconcat(opc, "${s}${p}", wide, " $Rdn, $shift"),
598 (!cast<Instruction>(NAME#"rs") rGPR:$Rdn, rGPR:$Rdn,
599 t2_so_reg:$shift, pred:$p,
603 /// T2I_bin_w_irs - Same as T2I_bin_irs except these operations need
604 // the ".w" suffix to indicate that they are wide.
605 multiclass T2I_bin_w_irs<bits<4> opcod, string opc,
606 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
607 PatFrag opnode, bit Commutable = 0> :
608 T2I_bin_irs<opcod, opc, iii, iir, iis, opnode, Commutable, ".w"> {
609 // Assembler aliases w/ the ".w" suffix.
610 def : t2InstAlias<!strconcat(opc, "${s}${p}.w", " $Rd, $Rn, $imm"),
611 (!cast<Instruction>(NAME#"ri") rGPR:$Rd, rGPR:$Rn, t2_so_imm:$imm, pred:$p,
613 // Assembler aliases w/o the ".w" suffix.
614 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rd, $Rn, $Rm"),
615 (!cast<Instruction>(NAME#"rr") rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, pred:$p,
617 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rd, $Rn, $shift"),
618 (!cast<Instruction>(NAME#"rs") rGPR:$Rd, rGPR:$Rn, t2_so_reg:$shift,
619 pred:$p, cc_out:$s)>;
621 // and with the optional destination operand, too.
622 def : t2InstAlias<!strconcat(opc, "${s}${p}.w", " $Rdn, $imm"),
623 (!cast<Instruction>(NAME#"ri") rGPR:$Rdn, rGPR:$Rdn, t2_so_imm:$imm,
624 pred:$p, cc_out:$s)>;
625 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rdn, $Rm"),
626 (!cast<Instruction>(NAME#"rr") rGPR:$Rdn, rGPR:$Rdn, rGPR:$Rm, pred:$p,
628 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rdn, $shift"),
629 (!cast<Instruction>(NAME#"rs") rGPR:$Rdn, rGPR:$Rdn, t2_so_reg:$shift,
630 pred:$p, cc_out:$s)>;
633 /// T2I_rbin_is - Same as T2I_bin_irs except the order of operands are
634 /// reversed. The 'rr' form is only defined for the disassembler; for codegen
635 /// it is equivalent to the T2I_bin_irs counterpart.
636 multiclass T2I_rbin_irs<bits<4> opcod, string opc, PatFrag opnode> {
638 def ri : T2sTwoRegImm<
639 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm), IIC_iALUi,
640 opc, ".w\t$Rd, $Rn, $imm",
641 [(set rGPR:$Rd, (opnode t2_so_imm:$imm, rGPR:$Rn))]>,
642 Sched<[WriteALU, ReadALU]> {
643 let Inst{31-27} = 0b11110;
645 let Inst{24-21} = opcod;
649 def rr : T2sThreeReg<
650 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUr,
651 opc, "\t$Rd, $Rn, $Rm",
652 [/* For disassembly only; pattern left blank */]>,
653 Sched<[WriteALU, ReadALU, ReadALU]> {
654 let Inst{31-27} = 0b11101;
655 let Inst{26-25} = 0b01;
656 let Inst{24-21} = opcod;
657 let Inst{14-12} = 0b000; // imm3
658 let Inst{7-6} = 0b00; // imm2
659 let Inst{5-4} = 0b00; // type
662 def rs : T2sTwoRegShiftedReg<
663 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm),
664 IIC_iALUsir, opc, "\t$Rd, $Rn, $ShiftedRm",
665 [(set rGPR:$Rd, (opnode t2_so_reg:$ShiftedRm, rGPR:$Rn))]>,
666 Sched<[WriteALUsi, ReadALU]> {
667 let Inst{31-27} = 0b11101;
668 let Inst{26-25} = 0b01;
669 let Inst{24-21} = opcod;
673 /// T2I_bin_s_irs - Similar to T2I_bin_irs except it sets the 's' bit so the
674 /// instruction modifies the CPSR register.
676 /// These opcodes will be converted to the real non-S opcodes by
677 /// AdjustInstrPostInstrSelection after giving then an optional CPSR operand.
678 let hasPostISelHook = 1, Defs = [CPSR] in {
679 multiclass T2I_bin_s_irs<InstrItinClass iii, InstrItinClass iir,
680 InstrItinClass iis, PatFrag opnode,
681 bit Commutable = 0> {
683 def ri : t2PseudoInst<(outs rGPR:$Rd),
684 (ins GPRnopc:$Rn, t2_so_imm:$imm, pred:$p),
686 [(set rGPR:$Rd, CPSR, (opnode GPRnopc:$Rn,
688 Sched<[WriteALU, ReadALU]>;
690 def rr : t2PseudoInst<(outs rGPR:$Rd), (ins GPRnopc:$Rn, rGPR:$Rm, pred:$p),
692 [(set rGPR:$Rd, CPSR, (opnode GPRnopc:$Rn,
694 Sched<[WriteALU, ReadALU, ReadALU]> {
695 let isCommutable = Commutable;
698 def rs : t2PseudoInst<(outs rGPR:$Rd),
699 (ins GPRnopc:$Rn, t2_so_reg:$ShiftedRm, pred:$p),
701 [(set rGPR:$Rd, CPSR, (opnode GPRnopc:$Rn,
702 t2_so_reg:$ShiftedRm))]>,
703 Sched<[WriteALUsi, ReadALUsr]>;
707 /// T2I_rbin_s_is - Same as T2I_bin_s_irs, except selection DAG
708 /// operands are reversed.
709 let hasPostISelHook = 1, Defs = [CPSR] in {
710 multiclass T2I_rbin_s_is<PatFrag opnode> {
712 def ri : t2PseudoInst<(outs rGPR:$Rd),
713 (ins rGPR:$Rn, t2_so_imm:$imm, pred:$p),
715 [(set rGPR:$Rd, CPSR, (opnode t2_so_imm:$imm,
717 Sched<[WriteALU, ReadALU]>;
719 def rs : t2PseudoInst<(outs rGPR:$Rd),
720 (ins rGPR:$Rn, t2_so_reg:$ShiftedRm, pred:$p),
722 [(set rGPR:$Rd, CPSR, (opnode t2_so_reg:$ShiftedRm,
724 Sched<[WriteALUsi, ReadALU]>;
728 /// T2I_bin_ii12rs - Defines a set of (op reg, {so_imm|imm0_4095|r|so_reg})
729 /// patterns for a binary operation that produces a value.
730 multiclass T2I_bin_ii12rs<bits<3> op23_21, string opc, PatFrag opnode,
731 bit Commutable = 0> {
733 // The register-immediate version is re-materializable. This is useful
734 // in particular for taking the address of a local.
735 let isReMaterializable = 1 in {
736 def ri : T2sTwoRegImm<
737 (outs GPRnopc:$Rd), (ins GPRnopc:$Rn, t2_so_imm:$imm), IIC_iALUi,
738 opc, ".w\t$Rd, $Rn, $imm",
739 [(set GPRnopc:$Rd, (opnode GPRnopc:$Rn, t2_so_imm:$imm))]>,
740 Sched<[WriteALU, ReadALU]> {
741 let Inst{31-27} = 0b11110;
744 let Inst{23-21} = op23_21;
750 (outs GPRnopc:$Rd), (ins GPR:$Rn, imm0_4095:$imm), IIC_iALUi,
751 !strconcat(opc, "w"), "\t$Rd, $Rn, $imm",
752 [(set GPRnopc:$Rd, (opnode GPR:$Rn, imm0_4095:$imm))]>,
753 Sched<[WriteALU, ReadALU]> {
757 let Inst{31-27} = 0b11110;
758 let Inst{26} = imm{11};
759 let Inst{25-24} = 0b10;
760 let Inst{23-21} = op23_21;
761 let Inst{20} = 0; // The S bit.
762 let Inst{19-16} = Rn;
764 let Inst{14-12} = imm{10-8};
766 let Inst{7-0} = imm{7-0};
769 def rr : T2sThreeReg<(outs GPRnopc:$Rd), (ins GPRnopc:$Rn, rGPR:$Rm),
770 IIC_iALUr, opc, ".w\t$Rd, $Rn, $Rm",
771 [(set GPRnopc:$Rd, (opnode GPRnopc:$Rn, rGPR:$Rm))]>,
772 Sched<[WriteALU, ReadALU, ReadALU]> {
773 let isCommutable = Commutable;
774 let Inst{31-27} = 0b11101;
775 let Inst{26-25} = 0b01;
777 let Inst{23-21} = op23_21;
778 let Inst{14-12} = 0b000; // imm3
779 let Inst{7-6} = 0b00; // imm2
780 let Inst{5-4} = 0b00; // type
783 def rs : T2sTwoRegShiftedReg<
784 (outs GPRnopc:$Rd), (ins GPRnopc:$Rn, t2_so_reg:$ShiftedRm),
785 IIC_iALUsi, opc, ".w\t$Rd, $Rn, $ShiftedRm",
786 [(set GPRnopc:$Rd, (opnode GPRnopc:$Rn, t2_so_reg:$ShiftedRm))]>,
787 Sched<[WriteALUsi, ReadALU]> {
788 let Inst{31-27} = 0b11101;
789 let Inst{26-25} = 0b01;
791 let Inst{23-21} = op23_21;
795 /// T2I_adde_sube_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns
796 /// for a binary operation that produces a value and use the carry
797 /// bit. It's not predicable.
798 let Defs = [CPSR], Uses = [CPSR] in {
799 multiclass T2I_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
800 bit Commutable = 0> {
802 def ri : T2sTwoRegImm<(outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm),
803 IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
804 [(set rGPR:$Rd, CPSR, (opnode rGPR:$Rn, t2_so_imm:$imm, CPSR))]>,
805 Requires<[IsThumb2]>, Sched<[WriteALU, ReadALU]> {
806 let Inst{31-27} = 0b11110;
808 let Inst{24-21} = opcod;
812 def rr : T2sThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUr,
813 opc, ".w\t$Rd, $Rn, $Rm",
814 [(set rGPR:$Rd, CPSR, (opnode rGPR:$Rn, rGPR:$Rm, CPSR))]>,
815 Requires<[IsThumb2]>, Sched<[WriteALU, ReadALU, ReadALU]> {
816 let isCommutable = Commutable;
817 let Inst{31-27} = 0b11101;
818 let Inst{26-25} = 0b01;
819 let Inst{24-21} = opcod;
820 let Inst{14-12} = 0b000; // imm3
821 let Inst{7-6} = 0b00; // imm2
822 let Inst{5-4} = 0b00; // type
825 def rs : T2sTwoRegShiftedReg<
826 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm),
827 IIC_iALUsi, opc, ".w\t$Rd, $Rn, $ShiftedRm",
828 [(set rGPR:$Rd, CPSR, (opnode rGPR:$Rn, t2_so_reg:$ShiftedRm, CPSR))]>,
829 Requires<[IsThumb2]>, Sched<[WriteALUsi, ReadALU]> {
830 let Inst{31-27} = 0b11101;
831 let Inst{26-25} = 0b01;
832 let Inst{24-21} = opcod;
837 /// T2I_sh_ir - Defines a set of (op reg, {so_imm|r}) patterns for a shift /
838 // rotate operation that produces a value.
839 multiclass T2I_sh_ir<bits<2> opcod, string opc, Operand ty, PatFrag opnode> {
841 def ri : T2sTwoRegShiftImm<
842 (outs rGPR:$Rd), (ins rGPR:$Rm, ty:$imm), IIC_iMOVsi,
843 opc, ".w\t$Rd, $Rm, $imm",
844 [(set rGPR:$Rd, (opnode rGPR:$Rm, (i32 ty:$imm)))]>,
846 let Inst{31-27} = 0b11101;
847 let Inst{26-21} = 0b010010;
848 let Inst{19-16} = 0b1111; // Rn
849 let Inst{5-4} = opcod;
852 def rr : T2sThreeReg<
853 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMOVsr,
854 opc, ".w\t$Rd, $Rn, $Rm",
855 [(set rGPR:$Rd, (opnode rGPR:$Rn, rGPR:$Rm))]>,
857 let Inst{31-27} = 0b11111;
858 let Inst{26-23} = 0b0100;
859 let Inst{22-21} = opcod;
860 let Inst{15-12} = 0b1111;
861 let Inst{7-4} = 0b0000;
864 // Optional destination register
865 def : t2InstAlias<!strconcat(opc, "${s}${p}", ".w $Rdn, $imm"),
866 (!cast<Instruction>(NAME#"ri") rGPR:$Rdn, rGPR:$Rdn, ty:$imm, pred:$p,
868 def : t2InstAlias<!strconcat(opc, "${s}${p}", ".w $Rdn, $Rm"),
869 (!cast<Instruction>(NAME#"rr") rGPR:$Rdn, rGPR:$Rdn, rGPR:$Rm, pred:$p,
872 // Assembler aliases w/o the ".w" suffix.
873 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rd, $Rn, $imm"),
874 (!cast<Instruction>(NAME#"ri") rGPR:$Rd, rGPR:$Rn, ty:$imm, pred:$p,
876 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rd, $Rn, $Rm"),
877 (!cast<Instruction>(NAME#"rr") rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, pred:$p,
880 // and with the optional destination operand, too.
881 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rdn, $imm"),
882 (!cast<Instruction>(NAME#"ri") rGPR:$Rdn, rGPR:$Rdn, ty:$imm, pred:$p,
884 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rdn, $Rm"),
885 (!cast<Instruction>(NAME#"rr") rGPR:$Rdn, rGPR:$Rdn, rGPR:$Rm, pred:$p,
889 /// T2I_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
890 /// patterns. Similar to T2I_bin_irs except the instruction does not produce
891 /// a explicit result, only implicitly set CPSR.
892 multiclass T2I_cmp_irs<bits<4> opcod, string opc,
893 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
895 let isCompare = 1, Defs = [CPSR] in {
897 def ri : T2OneRegCmpImm<
898 (outs), (ins GPRnopc:$Rn, t2_so_imm:$imm), iii,
899 opc, ".w\t$Rn, $imm",
900 [(opnode GPRnopc:$Rn, t2_so_imm:$imm)]>, Sched<[WriteCMP]> {
901 let Inst{31-27} = 0b11110;
903 let Inst{24-21} = opcod;
904 let Inst{20} = 1; // The S bit.
906 let Inst{11-8} = 0b1111; // Rd
909 def rr : T2TwoRegCmp<
910 (outs), (ins GPRnopc:$Rn, rGPR:$Rm), iir,
912 [(opnode GPRnopc:$Rn, rGPR:$Rm)]>, Sched<[WriteCMP]> {
913 let Inst{31-27} = 0b11101;
914 let Inst{26-25} = 0b01;
915 let Inst{24-21} = opcod;
916 let Inst{20} = 1; // The S bit.
917 let Inst{14-12} = 0b000; // imm3
918 let Inst{11-8} = 0b1111; // Rd
919 let Inst{7-6} = 0b00; // imm2
920 let Inst{5-4} = 0b00; // type
923 def rs : T2OneRegCmpShiftedReg<
924 (outs), (ins GPRnopc:$Rn, t2_so_reg:$ShiftedRm), iis,
925 opc, ".w\t$Rn, $ShiftedRm",
926 [(opnode GPRnopc:$Rn, t2_so_reg:$ShiftedRm)]>,
927 Sched<[WriteCMPsi]> {
928 let Inst{31-27} = 0b11101;
929 let Inst{26-25} = 0b01;
930 let Inst{24-21} = opcod;
931 let Inst{20} = 1; // The S bit.
932 let Inst{11-8} = 0b1111; // Rd
936 // Assembler aliases w/o the ".w" suffix.
937 // No alias here for 'rr' version as not all instantiations of this
938 // multiclass want one (CMP in particular, does not).
939 def : t2InstAlias<!strconcat(opc, "${p}", " $Rn, $imm"),
940 (!cast<Instruction>(NAME#"ri") GPRnopc:$Rn, t2_so_imm:$imm, pred:$p)>;
941 def : t2InstAlias<!strconcat(opc, "${p}", " $Rn, $shift"),
942 (!cast<Instruction>(NAME#"rs") GPRnopc:$Rn, t2_so_reg:$shift, pred:$p)>;
945 /// T2I_ld - Defines a set of (op r, {imm12|imm8|so_reg}) load patterns.
946 multiclass T2I_ld<bit signed, bits<2> opcod, string opc,
947 InstrItinClass iii, InstrItinClass iis, RegisterClass target,
949 def i12 : T2Ii12<(outs target:$Rt), (ins t2addrmode_imm12:$addr), iii,
950 opc, ".w\t$Rt, $addr",
951 [(set target:$Rt, (opnode t2addrmode_imm12:$addr))]> {
954 let Inst{31-25} = 0b1111100;
955 let Inst{24} = signed;
957 let Inst{22-21} = opcod;
958 let Inst{20} = 1; // load
959 let Inst{19-16} = addr{16-13}; // Rn
960 let Inst{15-12} = Rt;
961 let Inst{11-0} = addr{11-0}; // imm
963 def i8 : T2Ii8 <(outs target:$Rt), (ins t2addrmode_negimm8:$addr), iii,
965 [(set target:$Rt, (opnode t2addrmode_negimm8:$addr))]> {
968 let Inst{31-27} = 0b11111;
969 let Inst{26-25} = 0b00;
970 let Inst{24} = signed;
972 let Inst{22-21} = opcod;
973 let Inst{20} = 1; // load
974 let Inst{19-16} = addr{12-9}; // Rn
975 let Inst{15-12} = Rt;
977 // Offset: index==TRUE, wback==FALSE
978 let Inst{10} = 1; // The P bit.
979 let Inst{9} = addr{8}; // U
980 let Inst{8} = 0; // The W bit.
981 let Inst{7-0} = addr{7-0}; // imm
983 def s : T2Iso <(outs target:$Rt), (ins t2addrmode_so_reg:$addr), iis,
984 opc, ".w\t$Rt, $addr",
985 [(set target:$Rt, (opnode t2addrmode_so_reg:$addr))]> {
986 let Inst{31-27} = 0b11111;
987 let Inst{26-25} = 0b00;
988 let Inst{24} = signed;
990 let Inst{22-21} = opcod;
991 let Inst{20} = 1; // load
992 let Inst{11-6} = 0b000000;
995 let Inst{15-12} = Rt;
998 let Inst{19-16} = addr{9-6}; // Rn
999 let Inst{3-0} = addr{5-2}; // Rm
1000 let Inst{5-4} = addr{1-0}; // imm
1002 let DecoderMethod = "DecodeT2LoadShift";
1005 // pci variant is very similar to i12, but supports negative offsets
1007 def pci : T2Ipc <(outs target:$Rt), (ins t2ldrlabel:$addr), iii,
1008 opc, ".w\t$Rt, $addr",
1009 [(set target:$Rt, (opnode (ARMWrapper tconstpool:$addr)))]> {
1010 let isReMaterializable = 1;
1011 let Inst{31-27} = 0b11111;
1012 let Inst{26-25} = 0b00;
1013 let Inst{24} = signed;
1014 let Inst{23} = ?; // add = (U == '1')
1015 let Inst{22-21} = opcod;
1016 let Inst{20} = 1; // load
1017 let Inst{19-16} = 0b1111; // Rn
1020 let Inst{15-12} = Rt{3-0};
1021 let Inst{11-0} = addr{11-0};
1025 /// T2I_st - Defines a set of (op r, {imm12|imm8|so_reg}) store patterns.
1026 multiclass T2I_st<bits<2> opcod, string opc,
1027 InstrItinClass iii, InstrItinClass iis, RegisterClass target,
1029 def i12 : T2Ii12<(outs), (ins target:$Rt, t2addrmode_imm12:$addr), iii,
1030 opc, ".w\t$Rt, $addr",
1031 [(opnode target:$Rt, t2addrmode_imm12:$addr)]> {
1032 let Inst{31-27} = 0b11111;
1033 let Inst{26-23} = 0b0001;
1034 let Inst{22-21} = opcod;
1035 let Inst{20} = 0; // !load
1038 let Inst{15-12} = Rt;
1041 let addr{12} = 1; // add = TRUE
1042 let Inst{19-16} = addr{16-13}; // Rn
1043 let Inst{23} = addr{12}; // U
1044 let Inst{11-0} = addr{11-0}; // imm
1046 def i8 : T2Ii8 <(outs), (ins target:$Rt, t2addrmode_negimm8:$addr), iii,
1047 opc, "\t$Rt, $addr",
1048 [(opnode target:$Rt, t2addrmode_negimm8:$addr)]> {
1049 let Inst{31-27} = 0b11111;
1050 let Inst{26-23} = 0b0000;
1051 let Inst{22-21} = opcod;
1052 let Inst{20} = 0; // !load
1054 // Offset: index==TRUE, wback==FALSE
1055 let Inst{10} = 1; // The P bit.
1056 let Inst{8} = 0; // The W bit.
1059 let Inst{15-12} = Rt;
1062 let Inst{19-16} = addr{12-9}; // Rn
1063 let Inst{9} = addr{8}; // U
1064 let Inst{7-0} = addr{7-0}; // imm
1066 def s : T2Iso <(outs), (ins target:$Rt, t2addrmode_so_reg:$addr), iis,
1067 opc, ".w\t$Rt, $addr",
1068 [(opnode target:$Rt, t2addrmode_so_reg:$addr)]> {
1069 let Inst{31-27} = 0b11111;
1070 let Inst{26-23} = 0b0000;
1071 let Inst{22-21} = opcod;
1072 let Inst{20} = 0; // !load
1073 let Inst{11-6} = 0b000000;
1076 let Inst{15-12} = Rt;
1079 let Inst{19-16} = addr{9-6}; // Rn
1080 let Inst{3-0} = addr{5-2}; // Rm
1081 let Inst{5-4} = addr{1-0}; // imm
1085 /// T2I_ext_rrot - A unary operation with two forms: one whose operand is a
1086 /// register and one whose operand is a register rotated by 8/16/24.
1087 class T2I_ext_rrot<bits<3> opcod, string opc, PatFrag opnode>
1088 : T2TwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm, rot_imm:$rot), IIC_iEXTr,
1089 opc, ".w\t$Rd, $Rm$rot",
1090 [(set rGPR:$Rd, (opnode (rotr rGPR:$Rm, rot_imm:$rot)))]>,
1091 Requires<[IsThumb2]> {
1092 let Inst{31-27} = 0b11111;
1093 let Inst{26-23} = 0b0100;
1094 let Inst{22-20} = opcod;
1095 let Inst{19-16} = 0b1111; // Rn
1096 let Inst{15-12} = 0b1111;
1100 let Inst{5-4} = rot{1-0}; // rotate
1103 // UXTB16 - Requres T2ExtractPack, does not need the .w qualifier.
1104 class T2I_ext_rrot_uxtb16<bits<3> opcod, string opc, PatFrag opnode>
1105 : T2TwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm, rot_imm:$rot),
1106 IIC_iEXTr, opc, "\t$Rd, $Rm$rot",
1107 [(set rGPR:$Rd, (opnode (rotr rGPR:$Rm, rot_imm:$rot)))]>,
1108 Requires<[HasT2ExtractPack, IsThumb2]> {
1110 let Inst{31-27} = 0b11111;
1111 let Inst{26-23} = 0b0100;
1112 let Inst{22-20} = opcod;
1113 let Inst{19-16} = 0b1111; // Rn
1114 let Inst{15-12} = 0b1111;
1116 let Inst{5-4} = rot;
1119 // SXTB16 - Requres T2ExtractPack, does not need the .w qualifier, no pattern
1121 class T2I_ext_rrot_sxtb16<bits<3> opcod, string opc>
1122 : T2TwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm, rot_imm:$rot), IIC_iEXTr,
1123 opc, "\t$Rd, $Rm$rot", []>,
1124 Requires<[IsThumb2, HasT2ExtractPack]> {
1126 let Inst{31-27} = 0b11111;
1127 let Inst{26-23} = 0b0100;
1128 let Inst{22-20} = opcod;
1129 let Inst{19-16} = 0b1111; // Rn
1130 let Inst{15-12} = 0b1111;
1132 let Inst{5-4} = rot;
1135 /// T2I_exta_rrot - A binary operation with two forms: one whose operand is a
1136 /// register and one whose operand is a register rotated by 8/16/24.
1137 class T2I_exta_rrot<bits<3> opcod, string opc, PatFrag opnode>
1138 : T2ThreeReg<(outs rGPR:$Rd),
1139 (ins rGPR:$Rn, rGPR:$Rm, rot_imm:$rot),
1140 IIC_iEXTAsr, opc, "\t$Rd, $Rn, $Rm$rot",
1141 [(set rGPR:$Rd, (opnode rGPR:$Rn, (rotr rGPR:$Rm,rot_imm:$rot)))]>,
1142 Requires<[HasT2ExtractPack, IsThumb2]> {
1144 let Inst{31-27} = 0b11111;
1145 let Inst{26-23} = 0b0100;
1146 let Inst{22-20} = opcod;
1147 let Inst{15-12} = 0b1111;
1149 let Inst{5-4} = rot;
1152 class T2I_exta_rrot_np<bits<3> opcod, string opc>
1153 : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm,rot_imm:$rot),
1154 IIC_iEXTAsr, opc, "\t$Rd, $Rn, $Rm$rot", []> {
1156 let Inst{31-27} = 0b11111;
1157 let Inst{26-23} = 0b0100;
1158 let Inst{22-20} = opcod;
1159 let Inst{15-12} = 0b1111;
1161 let Inst{5-4} = rot;
1164 //===----------------------------------------------------------------------===//
1166 //===----------------------------------------------------------------------===//
1168 //===----------------------------------------------------------------------===//
1169 // Miscellaneous Instructions.
1172 class T2PCOneRegImm<dag oops, dag iops, InstrItinClass itin,
1173 string asm, list<dag> pattern>
1174 : T2XI<oops, iops, itin, asm, pattern> {
1178 let Inst{11-8} = Rd;
1179 let Inst{26} = label{11};
1180 let Inst{14-12} = label{10-8};
1181 let Inst{7-0} = label{7-0};
1184 // LEApcrel - Load a pc-relative address into a register without offending the
1186 def t2ADR : T2PCOneRegImm<(outs rGPR:$Rd),
1187 (ins t2adrlabel:$addr, pred:$p),
1188 IIC_iALUi, "adr{$p}.w\t$Rd, $addr", []>,
1189 Sched<[WriteALU, ReadALU]> {
1190 let Inst{31-27} = 0b11110;
1191 let Inst{25-24} = 0b10;
1192 // Inst{23:21} = '11' (add = FALSE) or '00' (add = TRUE)
1195 let Inst{19-16} = 0b1111; // Rn
1200 let Inst{11-8} = Rd;
1201 let Inst{23} = addr{12};
1202 let Inst{21} = addr{12};
1203 let Inst{26} = addr{11};
1204 let Inst{14-12} = addr{10-8};
1205 let Inst{7-0} = addr{7-0};
1207 let DecoderMethod = "DecodeT2Adr";
1210 let neverHasSideEffects = 1, isReMaterializable = 1 in
1211 def t2LEApcrel : t2PseudoInst<(outs rGPR:$Rd), (ins i32imm:$label, pred:$p),
1212 4, IIC_iALUi, []>, Sched<[WriteALU, ReadALU]>;
1213 let hasSideEffects = 1 in
1214 def t2LEApcrelJT : t2PseudoInst<(outs rGPR:$Rd),
1215 (ins i32imm:$label, nohash_imm:$id, pred:$p),
1217 []>, Sched<[WriteALU, ReadALU]>;
1220 //===----------------------------------------------------------------------===//
1221 // Load / store Instructions.
1225 let canFoldAsLoad = 1, isReMaterializable = 1 in
1226 defm t2LDR : T2I_ld<0, 0b10, "ldr", IIC_iLoad_i, IIC_iLoad_si, GPR,
1227 UnOpFrag<(load node:$Src)>>;
1229 // Loads with zero extension
1230 defm t2LDRH : T2I_ld<0, 0b01, "ldrh", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
1231 rGPR, UnOpFrag<(zextloadi16 node:$Src)>>;
1232 defm t2LDRB : T2I_ld<0, 0b00, "ldrb", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
1233 rGPR, UnOpFrag<(zextloadi8 node:$Src)>>;
1235 // Loads with sign extension
1236 defm t2LDRSH : T2I_ld<1, 0b01, "ldrsh", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
1237 rGPR, UnOpFrag<(sextloadi16 node:$Src)>>;
1238 defm t2LDRSB : T2I_ld<1, 0b00, "ldrsb", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
1239 rGPR, UnOpFrag<(sextloadi8 node:$Src)>>;
1241 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
1243 def t2LDRDi8 : T2Ii8s4<1, 0, 1, (outs rGPR:$Rt, rGPR:$Rt2),
1244 (ins t2addrmode_imm8s4:$addr),
1245 IIC_iLoad_d_i, "ldrd", "\t$Rt, $Rt2, $addr", "", []>;
1246 } // mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1
1248 // zextload i1 -> zextload i8
1249 def : T2Pat<(zextloadi1 t2addrmode_imm12:$addr),
1250 (t2LDRBi12 t2addrmode_imm12:$addr)>;
1251 def : T2Pat<(zextloadi1 t2addrmode_negimm8:$addr),
1252 (t2LDRBi8 t2addrmode_negimm8:$addr)>;
1253 def : T2Pat<(zextloadi1 t2addrmode_so_reg:$addr),
1254 (t2LDRBs t2addrmode_so_reg:$addr)>;
1255 def : T2Pat<(zextloadi1 (ARMWrapper tconstpool:$addr)),
1256 (t2LDRBpci tconstpool:$addr)>;
1258 // extload -> zextload
1259 // FIXME: Reduce the number of patterns by legalizing extload to zextload
1261 def : T2Pat<(extloadi1 t2addrmode_imm12:$addr),
1262 (t2LDRBi12 t2addrmode_imm12:$addr)>;
1263 def : T2Pat<(extloadi1 t2addrmode_negimm8:$addr),
1264 (t2LDRBi8 t2addrmode_negimm8:$addr)>;
1265 def : T2Pat<(extloadi1 t2addrmode_so_reg:$addr),
1266 (t2LDRBs t2addrmode_so_reg:$addr)>;
1267 def : T2Pat<(extloadi1 (ARMWrapper tconstpool:$addr)),
1268 (t2LDRBpci tconstpool:$addr)>;
1270 def : T2Pat<(extloadi8 t2addrmode_imm12:$addr),
1271 (t2LDRBi12 t2addrmode_imm12:$addr)>;
1272 def : T2Pat<(extloadi8 t2addrmode_negimm8:$addr),
1273 (t2LDRBi8 t2addrmode_negimm8:$addr)>;
1274 def : T2Pat<(extloadi8 t2addrmode_so_reg:$addr),
1275 (t2LDRBs t2addrmode_so_reg:$addr)>;
1276 def : T2Pat<(extloadi8 (ARMWrapper tconstpool:$addr)),
1277 (t2LDRBpci tconstpool:$addr)>;
1279 def : T2Pat<(extloadi16 t2addrmode_imm12:$addr),
1280 (t2LDRHi12 t2addrmode_imm12:$addr)>;
1281 def : T2Pat<(extloadi16 t2addrmode_negimm8:$addr),
1282 (t2LDRHi8 t2addrmode_negimm8:$addr)>;
1283 def : T2Pat<(extloadi16 t2addrmode_so_reg:$addr),
1284 (t2LDRHs t2addrmode_so_reg:$addr)>;
1285 def : T2Pat<(extloadi16 (ARMWrapper tconstpool:$addr)),
1286 (t2LDRHpci tconstpool:$addr)>;
1288 // FIXME: The destination register of the loads and stores can't be PC, but
1289 // can be SP. We need another regclass (similar to rGPR) to represent
1290 // that. Not a pressing issue since these are selected manually,
1295 let mayLoad = 1, neverHasSideEffects = 1 in {
1296 def t2LDR_PRE : T2Ipreldst<0, 0b10, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1297 (ins t2addrmode_imm8:$addr),
1298 AddrModeT2_i8, IndexModePre, IIC_iLoad_iu,
1299 "ldr", "\t$Rt, $addr!", "$addr.base = $Rn_wb",
1301 let AsmMatchConverter = "cvtLdWriteBackRegT2AddrModeImm8";
1304 def t2LDR_POST : T2Ipostldst<0, 0b10, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1305 (ins addr_offset_none:$Rn, t2am_imm8_offset:$offset),
1306 AddrModeT2_i8, IndexModePost, IIC_iLoad_iu,
1307 "ldr", "\t$Rt, $Rn$offset", "$Rn = $Rn_wb", []>;
1309 def t2LDRB_PRE : T2Ipreldst<0, 0b00, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1310 (ins t2addrmode_imm8:$addr),
1311 AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
1312 "ldrb", "\t$Rt, $addr!", "$addr.base = $Rn_wb",
1314 let AsmMatchConverter = "cvtLdWriteBackRegT2AddrModeImm8";
1316 def t2LDRB_POST : T2Ipostldst<0, 0b00, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1317 (ins addr_offset_none:$Rn, t2am_imm8_offset:$offset),
1318 AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
1319 "ldrb", "\t$Rt, $Rn$offset", "$Rn = $Rn_wb", []>;
1321 def t2LDRH_PRE : T2Ipreldst<0, 0b01, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1322 (ins t2addrmode_imm8:$addr),
1323 AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
1324 "ldrh", "\t$Rt, $addr!", "$addr.base = $Rn_wb",
1326 let AsmMatchConverter = "cvtLdWriteBackRegT2AddrModeImm8";
1328 def t2LDRH_POST : T2Ipostldst<0, 0b01, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1329 (ins addr_offset_none:$Rn, t2am_imm8_offset:$offset),
1330 AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
1331 "ldrh", "\t$Rt, $Rn$offset", "$Rn = $Rn_wb", []>;
1333 def t2LDRSB_PRE : T2Ipreldst<1, 0b00, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1334 (ins t2addrmode_imm8:$addr),
1335 AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
1336 "ldrsb", "\t$Rt, $addr!", "$addr.base = $Rn_wb",
1338 let AsmMatchConverter = "cvtLdWriteBackRegT2AddrModeImm8";
1340 def t2LDRSB_POST : T2Ipostldst<1, 0b00, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1341 (ins addr_offset_none:$Rn, t2am_imm8_offset:$offset),
1342 AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
1343 "ldrsb", "\t$Rt, $Rn$offset", "$Rn = $Rn_wb", []>;
1345 def t2LDRSH_PRE : T2Ipreldst<1, 0b01, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1346 (ins t2addrmode_imm8:$addr),
1347 AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
1348 "ldrsh", "\t$Rt, $addr!", "$addr.base = $Rn_wb",
1350 let AsmMatchConverter = "cvtLdWriteBackRegT2AddrModeImm8";
1352 def t2LDRSH_POST : T2Ipostldst<1, 0b01, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1353 (ins addr_offset_none:$Rn, t2am_imm8_offset:$offset),
1354 AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
1355 "ldrsh", "\t$Rt, $Rn$offset", "$Rn = $Rn_wb", []>;
1356 } // mayLoad = 1, neverHasSideEffects = 1
1358 // LDRT, LDRBT, LDRHT, LDRSBT, LDRSHT all have offset mode (PUW=0b110).
1359 // Ref: A8.6.57 LDR (immediate, Thumb) Encoding T4
1360 class T2IldT<bit signed, bits<2> type, string opc, InstrItinClass ii>
1361 : T2Ii8<(outs rGPR:$Rt), (ins t2addrmode_posimm8:$addr), ii, opc,
1362 "\t$Rt, $addr", []> {
1365 let Inst{31-27} = 0b11111;
1366 let Inst{26-25} = 0b00;
1367 let Inst{24} = signed;
1369 let Inst{22-21} = type;
1370 let Inst{20} = 1; // load
1371 let Inst{19-16} = addr{12-9};
1372 let Inst{15-12} = Rt;
1374 let Inst{10-8} = 0b110; // PUW.
1375 let Inst{7-0} = addr{7-0};
1378 def t2LDRT : T2IldT<0, 0b10, "ldrt", IIC_iLoad_i>;
1379 def t2LDRBT : T2IldT<0, 0b00, "ldrbt", IIC_iLoad_bh_i>;
1380 def t2LDRHT : T2IldT<0, 0b01, "ldrht", IIC_iLoad_bh_i>;
1381 def t2LDRSBT : T2IldT<1, 0b00, "ldrsbt", IIC_iLoad_bh_i>;
1382 def t2LDRSHT : T2IldT<1, 0b01, "ldrsht", IIC_iLoad_bh_i>;
1385 defm t2STR :T2I_st<0b10,"str", IIC_iStore_i, IIC_iStore_si, GPR,
1386 BinOpFrag<(store node:$LHS, node:$RHS)>>;
1387 defm t2STRB:T2I_st<0b00,"strb", IIC_iStore_bh_i, IIC_iStore_bh_si,
1388 rGPR, BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
1389 defm t2STRH:T2I_st<0b01,"strh", IIC_iStore_bh_i, IIC_iStore_bh_si,
1390 rGPR, BinOpFrag<(truncstorei16 node:$LHS, node:$RHS)>>;
1393 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in
1394 def t2STRDi8 : T2Ii8s4<1, 0, 0, (outs),
1395 (ins GPR:$Rt, GPR:$Rt2, t2addrmode_imm8s4:$addr),
1396 IIC_iStore_d_r, "strd", "\t$Rt, $Rt2, $addr", "", []>;
1400 let mayStore = 1, neverHasSideEffects = 1 in {
1401 def t2STR_PRE : T2Ipreldst<0, 0b10, 0, 1, (outs GPRnopc:$Rn_wb),
1402 (ins GPRnopc:$Rt, t2addrmode_imm8:$addr),
1403 AddrModeT2_i8, IndexModePre, IIC_iStore_iu,
1404 "str", "\t$Rt, $addr!",
1405 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> {
1406 let AsmMatchConverter = "cvtStWriteBackRegT2AddrModeImm8";
1408 def t2STRH_PRE : T2Ipreldst<0, 0b01, 0, 1, (outs GPRnopc:$Rn_wb),
1409 (ins rGPR:$Rt, t2addrmode_imm8:$addr),
1410 AddrModeT2_i8, IndexModePre, IIC_iStore_iu,
1411 "strh", "\t$Rt, $addr!",
1412 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> {
1413 let AsmMatchConverter = "cvtStWriteBackRegT2AddrModeImm8";
1416 def t2STRB_PRE : T2Ipreldst<0, 0b00, 0, 1, (outs GPRnopc:$Rn_wb),
1417 (ins rGPR:$Rt, t2addrmode_imm8:$addr),
1418 AddrModeT2_i8, IndexModePre, IIC_iStore_bh_iu,
1419 "strb", "\t$Rt, $addr!",
1420 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> {
1421 let AsmMatchConverter = "cvtStWriteBackRegT2AddrModeImm8";
1423 } // mayStore = 1, neverHasSideEffects = 1
1425 def t2STR_POST : T2Ipostldst<0, 0b10, 0, 0, (outs GPRnopc:$Rn_wb),
1426 (ins GPRnopc:$Rt, addr_offset_none:$Rn,
1427 t2am_imm8_offset:$offset),
1428 AddrModeT2_i8, IndexModePost, IIC_iStore_iu,
1429 "str", "\t$Rt, $Rn$offset",
1430 "$Rn = $Rn_wb,@earlyclobber $Rn_wb",
1431 [(set GPRnopc:$Rn_wb,
1432 (post_store GPRnopc:$Rt, addr_offset_none:$Rn,
1433 t2am_imm8_offset:$offset))]>;
1435 def t2STRH_POST : T2Ipostldst<0, 0b01, 0, 0, (outs GPRnopc:$Rn_wb),
1436 (ins rGPR:$Rt, addr_offset_none:$Rn,
1437 t2am_imm8_offset:$offset),
1438 AddrModeT2_i8, IndexModePost, IIC_iStore_bh_iu,
1439 "strh", "\t$Rt, $Rn$offset",
1440 "$Rn = $Rn_wb,@earlyclobber $Rn_wb",
1441 [(set GPRnopc:$Rn_wb,
1442 (post_truncsti16 rGPR:$Rt, addr_offset_none:$Rn,
1443 t2am_imm8_offset:$offset))]>;
1445 def t2STRB_POST : T2Ipostldst<0, 0b00, 0, 0, (outs GPRnopc:$Rn_wb),
1446 (ins rGPR:$Rt, addr_offset_none:$Rn,
1447 t2am_imm8_offset:$offset),
1448 AddrModeT2_i8, IndexModePost, IIC_iStore_bh_iu,
1449 "strb", "\t$Rt, $Rn$offset",
1450 "$Rn = $Rn_wb,@earlyclobber $Rn_wb",
1451 [(set GPRnopc:$Rn_wb,
1452 (post_truncsti8 rGPR:$Rt, addr_offset_none:$Rn,
1453 t2am_imm8_offset:$offset))]>;
1455 // Pseudo-instructions for pattern matching the pre-indexed stores. We can't
1456 // put the patterns on the instruction definitions directly as ISel wants
1457 // the address base and offset to be separate operands, not a single
1458 // complex operand like we represent the instructions themselves. The
1459 // pseudos map between the two.
1460 let usesCustomInserter = 1,
1461 Constraints = "$Rn = $Rn_wb,@earlyclobber $Rn_wb" in {
1462 def t2STR_preidx: t2PseudoInst<(outs GPRnopc:$Rn_wb),
1463 (ins rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$offset, pred:$p),
1465 [(set GPRnopc:$Rn_wb,
1466 (pre_store rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$offset))]>;
1467 def t2STRB_preidx: t2PseudoInst<(outs GPRnopc:$Rn_wb),
1468 (ins rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$offset, pred:$p),
1470 [(set GPRnopc:$Rn_wb,
1471 (pre_truncsti8 rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$offset))]>;
1472 def t2STRH_preidx: t2PseudoInst<(outs GPRnopc:$Rn_wb),
1473 (ins rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$offset, pred:$p),
1475 [(set GPRnopc:$Rn_wb,
1476 (pre_truncsti16 rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$offset))]>;
1479 // STRT, STRBT, STRHT all have offset mode (PUW=0b110) and are for disassembly
1481 // Ref: A8.6.193 STR (immediate, Thumb) Encoding T4
1482 class T2IstT<bits<2> type, string opc, InstrItinClass ii>
1483 : T2Ii8<(outs rGPR:$Rt), (ins t2addrmode_imm8:$addr), ii, opc,
1484 "\t$Rt, $addr", []> {
1485 let Inst{31-27} = 0b11111;
1486 let Inst{26-25} = 0b00;
1487 let Inst{24} = 0; // not signed
1489 let Inst{22-21} = type;
1490 let Inst{20} = 0; // store
1492 let Inst{10-8} = 0b110; // PUW
1496 let Inst{15-12} = Rt;
1497 let Inst{19-16} = addr{12-9};
1498 let Inst{7-0} = addr{7-0};
1501 def t2STRT : T2IstT<0b10, "strt", IIC_iStore_i>;
1502 def t2STRBT : T2IstT<0b00, "strbt", IIC_iStore_bh_i>;
1503 def t2STRHT : T2IstT<0b01, "strht", IIC_iStore_bh_i>;
1505 // ldrd / strd pre / post variants
1506 // For disassembly only.
1508 def t2LDRD_PRE : T2Ii8s4<1, 1, 1, (outs rGPR:$Rt, rGPR:$Rt2, GPR:$wb),
1509 (ins t2addrmode_imm8s4:$addr), IIC_iLoad_d_ru,
1510 "ldrd", "\t$Rt, $Rt2, $addr!", "$addr.base = $wb", []> {
1511 let AsmMatchConverter = "cvtT2LdrdPre";
1512 let DecoderMethod = "DecodeT2LDRDPreInstruction";
1515 def t2LDRD_POST : T2Ii8s4post<0, 1, 1, (outs rGPR:$Rt, rGPR:$Rt2, GPR:$wb),
1516 (ins addr_offset_none:$addr, t2am_imm8s4_offset:$imm),
1517 IIC_iLoad_d_ru, "ldrd", "\t$Rt, $Rt2, $addr$imm",
1518 "$addr.base = $wb", []>;
1520 def t2STRD_PRE : T2Ii8s4<1, 1, 0, (outs GPR:$wb),
1521 (ins rGPR:$Rt, rGPR:$Rt2, t2addrmode_imm8s4:$addr),
1522 IIC_iStore_d_ru, "strd", "\t$Rt, $Rt2, $addr!",
1523 "$addr.base = $wb", []> {
1524 let AsmMatchConverter = "cvtT2StrdPre";
1525 let DecoderMethod = "DecodeT2STRDPreInstruction";
1528 def t2STRD_POST : T2Ii8s4post<0, 1, 0, (outs GPR:$wb),
1529 (ins rGPR:$Rt, rGPR:$Rt2, addr_offset_none:$addr,
1530 t2am_imm8s4_offset:$imm),
1531 IIC_iStore_d_ru, "strd", "\t$Rt, $Rt2, $addr$imm",
1532 "$addr.base = $wb", []>;
1534 // T2Ipl (Preload Data/Instruction) signals the memory system of possible future
1535 // data/instruction access.
1536 // instr_write is inverted for Thumb mode: (prefetch 3) -> (preload 0),
1537 // (prefetch 1) -> (preload 2), (prefetch 2) -> (preload 1).
1538 multiclass T2Ipl<bits<1> write, bits<1> instr, string opc> {
1540 def i12 : T2Ii12<(outs), (ins t2addrmode_imm12:$addr), IIC_Preload, opc,
1542 [(ARMPreload t2addrmode_imm12:$addr, (i32 write), (i32 instr))]>,
1543 Sched<[WritePreLd]> {
1544 let Inst{31-25} = 0b1111100;
1545 let Inst{24} = instr;
1547 let Inst{21} = write;
1549 let Inst{15-12} = 0b1111;
1552 let addr{12} = 1; // add = TRUE
1553 let Inst{19-16} = addr{16-13}; // Rn
1554 let Inst{23} = addr{12}; // U
1555 let Inst{11-0} = addr{11-0}; // imm12
1558 def i8 : T2Ii8<(outs), (ins t2addrmode_negimm8:$addr), IIC_Preload, opc,
1560 [(ARMPreload t2addrmode_negimm8:$addr, (i32 write), (i32 instr))]>,
1561 Sched<[WritePreLd]> {
1562 let Inst{31-25} = 0b1111100;
1563 let Inst{24} = instr;
1564 let Inst{23} = 0; // U = 0
1566 let Inst{21} = write;
1568 let Inst{15-12} = 0b1111;
1569 let Inst{11-8} = 0b1100;
1572 let Inst{19-16} = addr{12-9}; // Rn
1573 let Inst{7-0} = addr{7-0}; // imm8
1576 def s : T2Iso<(outs), (ins t2addrmode_so_reg:$addr), IIC_Preload, opc,
1578 [(ARMPreload t2addrmode_so_reg:$addr, (i32 write), (i32 instr))]>,
1579 Sched<[WritePreLd]> {
1580 let Inst{31-25} = 0b1111100;
1581 let Inst{24} = instr;
1582 let Inst{23} = 0; // add = TRUE for T1
1584 let Inst{21} = write;
1586 let Inst{15-12} = 0b1111;
1587 let Inst{11-6} = 0000000;
1590 let Inst{19-16} = addr{9-6}; // Rn
1591 let Inst{3-0} = addr{5-2}; // Rm
1592 let Inst{5-4} = addr{1-0}; // imm2
1594 let DecoderMethod = "DecodeT2LoadShift";
1596 // FIXME: We should have a separate 'pci' variant here. As-is we represent
1597 // it via the i12 variant, which it's related to, but that means we can
1598 // represent negative immediates, which aren't legal for anything except
1599 // the 'pci' case (Rn == 15).
1602 defm t2PLD : T2Ipl<0, 0, "pld">, Requires<[IsThumb2]>;
1603 defm t2PLDW : T2Ipl<1, 0, "pldw">, Requires<[IsThumb2,HasV7,HasMP]>;
1604 defm t2PLI : T2Ipl<0, 1, "pli">, Requires<[IsThumb2,HasV7]>;
1606 //===----------------------------------------------------------------------===//
1607 // Load / store multiple Instructions.
1610 multiclass thumb2_ld_mult<string asm, InstrItinClass itin,
1611 InstrItinClass itin_upd, bit L_bit> {
1613 T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1614 itin, !strconcat(asm, "${p}.w\t$Rn, $regs"), []> {
1618 let Inst{31-27} = 0b11101;
1619 let Inst{26-25} = 0b00;
1620 let Inst{24-23} = 0b01; // Increment After
1622 let Inst{21} = 0; // No writeback
1623 let Inst{20} = L_bit;
1624 let Inst{19-16} = Rn;
1625 let Inst{15-0} = regs;
1628 T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1629 itin_upd, !strconcat(asm, "${p}.w\t$Rn!, $regs"), "$Rn = $wb", []> {
1633 let Inst{31-27} = 0b11101;
1634 let Inst{26-25} = 0b00;
1635 let Inst{24-23} = 0b01; // Increment After
1637 let Inst{21} = 1; // Writeback
1638 let Inst{20} = L_bit;
1639 let Inst{19-16} = Rn;
1640 let Inst{15-0} = regs;
1643 T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1644 itin, !strconcat(asm, "db${p}\t$Rn, $regs"), []> {
1648 let Inst{31-27} = 0b11101;
1649 let Inst{26-25} = 0b00;
1650 let Inst{24-23} = 0b10; // Decrement Before
1652 let Inst{21} = 0; // No writeback
1653 let Inst{20} = L_bit;
1654 let Inst{19-16} = Rn;
1655 let Inst{15-0} = regs;
1658 T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1659 itin_upd, !strconcat(asm, "db${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
1663 let Inst{31-27} = 0b11101;
1664 let Inst{26-25} = 0b00;
1665 let Inst{24-23} = 0b10; // Decrement Before
1667 let Inst{21} = 1; // Writeback
1668 let Inst{20} = L_bit;
1669 let Inst{19-16} = Rn;
1670 let Inst{15-0} = regs;
1674 let neverHasSideEffects = 1 in {
1676 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
1677 defm t2LDM : thumb2_ld_mult<"ldm", IIC_iLoad_m, IIC_iLoad_mu, 1>;
1679 multiclass thumb2_st_mult<string asm, InstrItinClass itin,
1680 InstrItinClass itin_upd, bit L_bit> {
1682 T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1683 itin, !strconcat(asm, "${p}.w\t$Rn, $regs"), []> {
1687 let Inst{31-27} = 0b11101;
1688 let Inst{26-25} = 0b00;
1689 let Inst{24-23} = 0b01; // Increment After
1691 let Inst{21} = 0; // No writeback
1692 let Inst{20} = L_bit;
1693 let Inst{19-16} = Rn;
1695 let Inst{14} = regs{14};
1697 let Inst{12-0} = regs{12-0};
1700 T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1701 itin_upd, !strconcat(asm, "${p}.w\t$Rn!, $regs"), "$Rn = $wb", []> {
1705 let Inst{31-27} = 0b11101;
1706 let Inst{26-25} = 0b00;
1707 let Inst{24-23} = 0b01; // Increment After
1709 let Inst{21} = 1; // Writeback
1710 let Inst{20} = L_bit;
1711 let Inst{19-16} = Rn;
1713 let Inst{14} = regs{14};
1715 let Inst{12-0} = regs{12-0};
1718 T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1719 itin, !strconcat(asm, "db${p}\t$Rn, $regs"), []> {
1723 let Inst{31-27} = 0b11101;
1724 let Inst{26-25} = 0b00;
1725 let Inst{24-23} = 0b10; // Decrement Before
1727 let Inst{21} = 0; // No writeback
1728 let Inst{20} = L_bit;
1729 let Inst{19-16} = Rn;
1731 let Inst{14} = regs{14};
1733 let Inst{12-0} = regs{12-0};
1736 T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1737 itin_upd, !strconcat(asm, "db${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
1741 let Inst{31-27} = 0b11101;
1742 let Inst{26-25} = 0b00;
1743 let Inst{24-23} = 0b10; // Decrement Before
1745 let Inst{21} = 1; // Writeback
1746 let Inst{20} = L_bit;
1747 let Inst{19-16} = Rn;
1749 let Inst{14} = regs{14};
1751 let Inst{12-0} = regs{12-0};
1756 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
1757 defm t2STM : thumb2_st_mult<"stm", IIC_iStore_m, IIC_iStore_mu, 0>;
1759 } // neverHasSideEffects
1762 //===----------------------------------------------------------------------===//
1763 // Move Instructions.
1766 let neverHasSideEffects = 1 in
1767 def t2MOVr : T2sTwoReg<(outs GPRnopc:$Rd), (ins GPR:$Rm), IIC_iMOVr,
1768 "mov", ".w\t$Rd, $Rm", []>, Sched<[WriteALU]> {
1769 let Inst{31-27} = 0b11101;
1770 let Inst{26-25} = 0b01;
1771 let Inst{24-21} = 0b0010;
1772 let Inst{19-16} = 0b1111; // Rn
1773 let Inst{14-12} = 0b000;
1774 let Inst{7-4} = 0b0000;
1776 def : t2InstAlias<"mov${p}.w $Rd, $Rm", (t2MOVr GPRnopc:$Rd, GPR:$Rm,
1777 pred:$p, zero_reg)>;
1778 def : t2InstAlias<"movs${p}.w $Rd, $Rm", (t2MOVr GPRnopc:$Rd, GPR:$Rm,
1780 def : t2InstAlias<"movs${p} $Rd, $Rm", (t2MOVr GPRnopc:$Rd, GPR:$Rm,
1783 // AddedComplexity to ensure isel tries t2MOVi before t2MOVi16.
1784 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1,
1785 AddedComplexity = 1 in
1786 def t2MOVi : T2sOneRegImm<(outs rGPR:$Rd), (ins t2_so_imm:$imm), IIC_iMOVi,
1787 "mov", ".w\t$Rd, $imm",
1788 [(set rGPR:$Rd, t2_so_imm:$imm)]>, Sched<[WriteALU]> {
1789 let Inst{31-27} = 0b11110;
1791 let Inst{24-21} = 0b0010;
1792 let Inst{19-16} = 0b1111; // Rn
1796 // cc_out is handled as part of the explicit mnemonic in the parser for 'mov'.
1797 // Use aliases to get that to play nice here.
1798 def : t2InstAlias<"movs${p}.w $Rd, $imm", (t2MOVi rGPR:$Rd, t2_so_imm:$imm,
1800 def : t2InstAlias<"movs${p} $Rd, $imm", (t2MOVi rGPR:$Rd, t2_so_imm:$imm,
1803 def : t2InstAlias<"mov${p}.w $Rd, $imm", (t2MOVi rGPR:$Rd, t2_so_imm:$imm,
1804 pred:$p, zero_reg)>;
1805 def : t2InstAlias<"mov${p} $Rd, $imm", (t2MOVi rGPR:$Rd, t2_so_imm:$imm,
1806 pred:$p, zero_reg)>;
1808 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
1809 def t2MOVi16 : T2I<(outs rGPR:$Rd), (ins imm0_65535_expr:$imm), IIC_iMOVi,
1810 "movw", "\t$Rd, $imm",
1811 [(set rGPR:$Rd, imm0_65535:$imm)]>, Sched<[WriteALU]> {
1812 let Inst{31-27} = 0b11110;
1814 let Inst{24-21} = 0b0010;
1815 let Inst{20} = 0; // The S bit.
1821 let Inst{11-8} = Rd;
1822 let Inst{19-16} = imm{15-12};
1823 let Inst{26} = imm{11};
1824 let Inst{14-12} = imm{10-8};
1825 let Inst{7-0} = imm{7-0};
1826 let DecoderMethod = "DecodeT2MOVTWInstruction";
1829 def t2MOVi16_ga_pcrel : PseudoInst<(outs rGPR:$Rd),
1830 (ins i32imm:$addr, pclabel:$id), IIC_iMOVi, []>;
1832 let Constraints = "$src = $Rd" in {
1833 def t2MOVTi16 : T2I<(outs rGPR:$Rd),
1834 (ins rGPR:$src, imm0_65535_expr:$imm), IIC_iMOVi,
1835 "movt", "\t$Rd, $imm",
1837 (or (and rGPR:$src, 0xffff), lo16AllZero:$imm))]>,
1839 let Inst{31-27} = 0b11110;
1841 let Inst{24-21} = 0b0110;
1842 let Inst{20} = 0; // The S bit.
1848 let Inst{11-8} = Rd;
1849 let Inst{19-16} = imm{15-12};
1850 let Inst{26} = imm{11};
1851 let Inst{14-12} = imm{10-8};
1852 let Inst{7-0} = imm{7-0};
1853 let DecoderMethod = "DecodeT2MOVTWInstruction";
1856 def t2MOVTi16_ga_pcrel : PseudoInst<(outs rGPR:$Rd),
1857 (ins rGPR:$src, i32imm:$addr, pclabel:$id), IIC_iMOVi, []>,
1861 def : T2Pat<(or rGPR:$src, 0xffff0000), (t2MOVTi16 rGPR:$src, 0xffff)>;
1863 //===----------------------------------------------------------------------===//
1864 // Extend Instructions.
1869 def t2SXTB : T2I_ext_rrot<0b100, "sxtb",
1870 UnOpFrag<(sext_inreg node:$Src, i8)>>;
1871 def t2SXTH : T2I_ext_rrot<0b000, "sxth",
1872 UnOpFrag<(sext_inreg node:$Src, i16)>>;
1873 def t2SXTB16 : T2I_ext_rrot_sxtb16<0b010, "sxtb16">;
1875 def t2SXTAB : T2I_exta_rrot<0b100, "sxtab",
1876 BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
1877 def t2SXTAH : T2I_exta_rrot<0b000, "sxtah",
1878 BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
1879 def t2SXTAB16 : T2I_exta_rrot_np<0b010, "sxtab16">;
1883 let AddedComplexity = 16 in {
1884 def t2UXTB : T2I_ext_rrot<0b101, "uxtb",
1885 UnOpFrag<(and node:$Src, 0x000000FF)>>;
1886 def t2UXTH : T2I_ext_rrot<0b001, "uxth",
1887 UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
1888 def t2UXTB16 : T2I_ext_rrot_uxtb16<0b011, "uxtb16",
1889 UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
1891 // FIXME: This pattern incorrectly assumes the shl operator is a rotate.
1892 // The transformation should probably be done as a combiner action
1893 // instead so we can include a check for masking back in the upper
1894 // eight bits of the source into the lower eight bits of the result.
1895 //def : T2Pat<(and (shl rGPR:$Src, (i32 8)), 0xFF00FF),
1896 // (t2UXTB16 rGPR:$Src, 3)>,
1897 // Requires<[HasT2ExtractPack, IsThumb2]>;
1898 def : T2Pat<(and (srl rGPR:$Src, (i32 8)), 0xFF00FF),
1899 (t2UXTB16 rGPR:$Src, 1)>,
1900 Requires<[HasT2ExtractPack, IsThumb2]>;
1902 def t2UXTAB : T2I_exta_rrot<0b101, "uxtab",
1903 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
1904 def t2UXTAH : T2I_exta_rrot<0b001, "uxtah",
1905 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
1906 def t2UXTAB16 : T2I_exta_rrot_np<0b011, "uxtab16">;
1909 //===----------------------------------------------------------------------===//
1910 // Arithmetic Instructions.
1913 defm t2ADD : T2I_bin_ii12rs<0b000, "add",
1914 BinOpFrag<(add node:$LHS, node:$RHS)>, 1>;
1915 defm t2SUB : T2I_bin_ii12rs<0b101, "sub",
1916 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
1918 // ADD and SUB with 's' bit set. No 12-bit immediate (T4) variants.
1920 // Currently, t2ADDS/t2SUBS are pseudo opcodes that exist only in the
1921 // selection DAG. They are "lowered" to real t2ADD/t2SUB opcodes by
1922 // AdjustInstrPostInstrSelection where we determine whether or not to
1923 // set the "s" bit based on CPSR liveness.
1925 // FIXME: Eliminate t2ADDS/t2SUBS pseudo opcodes after adding tablegen
1926 // support for an optional CPSR definition that corresponds to the DAG
1927 // node's second value. We can then eliminate the implicit def of CPSR.
1928 defm t2ADDS : T2I_bin_s_irs <IIC_iALUi, IIC_iALUr, IIC_iALUsi,
1929 BinOpFrag<(ARMaddc node:$LHS, node:$RHS)>, 1>;
1930 defm t2SUBS : T2I_bin_s_irs <IIC_iALUi, IIC_iALUr, IIC_iALUsi,
1931 BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>;
1933 let hasPostISelHook = 1 in {
1934 defm t2ADC : T2I_adde_sube_irs<0b1010, "adc",
1935 BinOpWithFlagFrag<(ARMadde node:$LHS, node:$RHS, node:$FLAG)>, 1>;
1936 defm t2SBC : T2I_adde_sube_irs<0b1011, "sbc",
1937 BinOpWithFlagFrag<(ARMsube node:$LHS, node:$RHS, node:$FLAG)>>;
1941 defm t2RSB : T2I_rbin_irs <0b1110, "rsb",
1942 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
1944 // FIXME: Eliminate them if we can write def : Pat patterns which defines
1945 // CPSR and the implicit def of CPSR is not needed.
1946 defm t2RSBS : T2I_rbin_s_is <BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>;
1948 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
1949 // The assume-no-carry-in form uses the negation of the input since add/sub
1950 // assume opposite meanings of the carry flag (i.e., carry == !borrow).
1951 // See the definition of AddWithCarry() in the ARM ARM A2.2.1 for the gory
1953 // The AddedComplexity preferences the first variant over the others since
1954 // it can be shrunk to a 16-bit wide encoding, while the others cannot.
1955 let AddedComplexity = 1 in
1956 def : T2Pat<(add GPR:$src, imm1_255_neg:$imm),
1957 (t2SUBri GPR:$src, imm1_255_neg:$imm)>;
1958 def : T2Pat<(add GPR:$src, t2_so_imm_neg:$imm),
1959 (t2SUBri GPR:$src, t2_so_imm_neg:$imm)>;
1960 def : T2Pat<(add GPR:$src, imm0_4095_neg:$imm),
1961 (t2SUBri12 GPR:$src, imm0_4095_neg:$imm)>;
1962 def : T2Pat<(add GPR:$src, imm0_65535_neg:$imm),
1963 (t2SUBrr GPR:$src, (t2MOVi16 (imm_neg_XFORM imm:$imm)))>;
1965 let AddedComplexity = 1 in
1966 def : T2Pat<(ARMaddc rGPR:$src, imm1_255_neg:$imm),
1967 (t2SUBSri rGPR:$src, imm1_255_neg:$imm)>;
1968 def : T2Pat<(ARMaddc rGPR:$src, t2_so_imm_neg:$imm),
1969 (t2SUBSri rGPR:$src, t2_so_imm_neg:$imm)>;
1970 def : T2Pat<(ARMaddc rGPR:$src, imm0_65535_neg:$imm),
1971 (t2SUBSrr rGPR:$src, (t2MOVi16 (imm_neg_XFORM imm:$imm)))>;
1972 // The with-carry-in form matches bitwise not instead of the negation.
1973 // Effectively, the inverse interpretation of the carry flag already accounts
1974 // for part of the negation.
1975 let AddedComplexity = 1 in
1976 def : T2Pat<(ARMadde rGPR:$src, imm0_255_not:$imm, CPSR),
1977 (t2SBCri rGPR:$src, imm0_255_not:$imm)>;
1978 def : T2Pat<(ARMadde rGPR:$src, t2_so_imm_not:$imm, CPSR),
1979 (t2SBCri rGPR:$src, t2_so_imm_not:$imm)>;
1980 def : T2Pat<(ARMadde rGPR:$src, imm0_65535_neg:$imm, CPSR),
1981 (t2SBCrr rGPR:$src, (t2MOVi16 (imm_not_XFORM imm:$imm)))>;
1983 // Select Bytes -- for disassembly only
1985 def t2SEL : T2ThreeReg<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
1986 NoItinerary, "sel", "\t$Rd, $Rn, $Rm", []>,
1987 Requires<[IsThumb2, HasThumb2DSP]> {
1988 let Inst{31-27} = 0b11111;
1989 let Inst{26-24} = 0b010;
1991 let Inst{22-20} = 0b010;
1992 let Inst{15-12} = 0b1111;
1994 let Inst{6-4} = 0b000;
1997 // A6.3.13, A6.3.14, A6.3.15 Parallel addition and subtraction (signed/unsigned)
1998 // And Miscellaneous operations -- for disassembly only
1999 class T2I_pam<bits<3> op22_20, bits<4> op7_4, string opc,
2000 list<dag> pat = [/* For disassembly only; pattern left blank */],
2001 dag iops = (ins rGPR:$Rn, rGPR:$Rm),
2002 string asm = "\t$Rd, $Rn, $Rm">
2003 : T2I<(outs rGPR:$Rd), iops, NoItinerary, opc, asm, pat>,
2004 Requires<[IsThumb2, HasThumb2DSP]> {
2005 let Inst{31-27} = 0b11111;
2006 let Inst{26-23} = 0b0101;
2007 let Inst{22-20} = op22_20;
2008 let Inst{15-12} = 0b1111;
2009 let Inst{7-4} = op7_4;
2015 let Inst{11-8} = Rd;
2016 let Inst{19-16} = Rn;
2020 // Saturating add/subtract -- for disassembly only
2022 def t2QADD : T2I_pam<0b000, 0b1000, "qadd",
2023 [(set rGPR:$Rd, (int_arm_qadd rGPR:$Rn, rGPR:$Rm))],
2024 (ins rGPR:$Rm, rGPR:$Rn), "\t$Rd, $Rm, $Rn">;
2025 def t2QADD16 : T2I_pam<0b001, 0b0001, "qadd16">;
2026 def t2QADD8 : T2I_pam<0b000, 0b0001, "qadd8">;
2027 def t2QASX : T2I_pam<0b010, 0b0001, "qasx">;
2028 def t2QDADD : T2I_pam<0b000, 0b1001, "qdadd", [],
2029 (ins rGPR:$Rm, rGPR:$Rn), "\t$Rd, $Rm, $Rn">;
2030 def t2QDSUB : T2I_pam<0b000, 0b1011, "qdsub", [],
2031 (ins rGPR:$Rm, rGPR:$Rn), "\t$Rd, $Rm, $Rn">;
2032 def t2QSAX : T2I_pam<0b110, 0b0001, "qsax">;
2033 def t2QSUB : T2I_pam<0b000, 0b1010, "qsub",
2034 [(set rGPR:$Rd, (int_arm_qsub rGPR:$Rn, rGPR:$Rm))],
2035 (ins rGPR:$Rm, rGPR:$Rn), "\t$Rd, $Rm, $Rn">;
2036 def t2QSUB16 : T2I_pam<0b101, 0b0001, "qsub16">;
2037 def t2QSUB8 : T2I_pam<0b100, 0b0001, "qsub8">;
2038 def t2UQADD16 : T2I_pam<0b001, 0b0101, "uqadd16">;
2039 def t2UQADD8 : T2I_pam<0b000, 0b0101, "uqadd8">;
2040 def t2UQASX : T2I_pam<0b010, 0b0101, "uqasx">;
2041 def t2UQSAX : T2I_pam<0b110, 0b0101, "uqsax">;
2042 def t2UQSUB16 : T2I_pam<0b101, 0b0101, "uqsub16">;
2043 def t2UQSUB8 : T2I_pam<0b100, 0b0101, "uqsub8">;
2045 // Signed/Unsigned add/subtract -- for disassembly only
2047 def t2SASX : T2I_pam<0b010, 0b0000, "sasx">;
2048 def t2SADD16 : T2I_pam<0b001, 0b0000, "sadd16">;
2049 def t2SADD8 : T2I_pam<0b000, 0b0000, "sadd8">;
2050 def t2SSAX : T2I_pam<0b110, 0b0000, "ssax">;
2051 def t2SSUB16 : T2I_pam<0b101, 0b0000, "ssub16">;
2052 def t2SSUB8 : T2I_pam<0b100, 0b0000, "ssub8">;
2053 def t2UASX : T2I_pam<0b010, 0b0100, "uasx">;
2054 def t2UADD16 : T2I_pam<0b001, 0b0100, "uadd16">;
2055 def t2UADD8 : T2I_pam<0b000, 0b0100, "uadd8">;
2056 def t2USAX : T2I_pam<0b110, 0b0100, "usax">;
2057 def t2USUB16 : T2I_pam<0b101, 0b0100, "usub16">;
2058 def t2USUB8 : T2I_pam<0b100, 0b0100, "usub8">;
2060 // Signed/Unsigned halving add/subtract -- for disassembly only
2062 def t2SHASX : T2I_pam<0b010, 0b0010, "shasx">;
2063 def t2SHADD16 : T2I_pam<0b001, 0b0010, "shadd16">;
2064 def t2SHADD8 : T2I_pam<0b000, 0b0010, "shadd8">;
2065 def t2SHSAX : T2I_pam<0b110, 0b0010, "shsax">;
2066 def t2SHSUB16 : T2I_pam<0b101, 0b0010, "shsub16">;
2067 def t2SHSUB8 : T2I_pam<0b100, 0b0010, "shsub8">;
2068 def t2UHASX : T2I_pam<0b010, 0b0110, "uhasx">;
2069 def t2UHADD16 : T2I_pam<0b001, 0b0110, "uhadd16">;
2070 def t2UHADD8 : T2I_pam<0b000, 0b0110, "uhadd8">;
2071 def t2UHSAX : T2I_pam<0b110, 0b0110, "uhsax">;
2072 def t2UHSUB16 : T2I_pam<0b101, 0b0110, "uhsub16">;
2073 def t2UHSUB8 : T2I_pam<0b100, 0b0110, "uhsub8">;
2075 // Helper class for disassembly only
2076 // A6.3.16 & A6.3.17
2077 // T2Imac - Thumb2 multiply [accumulate, and absolute difference] instructions.
2078 class T2ThreeReg_mac<bit long, bits<3> op22_20, bits<4> op7_4, dag oops,
2079 dag iops, InstrItinClass itin, string opc, string asm, list<dag> pattern>
2080 : T2ThreeReg<oops, iops, itin, opc, asm, pattern> {
2081 let Inst{31-27} = 0b11111;
2082 let Inst{26-24} = 0b011;
2083 let Inst{23} = long;
2084 let Inst{22-20} = op22_20;
2085 let Inst{7-4} = op7_4;
2088 class T2FourReg_mac<bit long, bits<3> op22_20, bits<4> op7_4, dag oops,
2089 dag iops, InstrItinClass itin, string opc, string asm, list<dag> pattern>
2090 : T2FourReg<oops, iops, itin, opc, asm, pattern> {
2091 let Inst{31-27} = 0b11111;
2092 let Inst{26-24} = 0b011;
2093 let Inst{23} = long;
2094 let Inst{22-20} = op22_20;
2095 let Inst{7-4} = op7_4;
2098 // Unsigned Sum of Absolute Differences [and Accumulate].
2099 def t2USAD8 : T2ThreeReg_mac<0, 0b111, 0b0000, (outs rGPR:$Rd),
2100 (ins rGPR:$Rn, rGPR:$Rm),
2101 NoItinerary, "usad8", "\t$Rd, $Rn, $Rm", []>,
2102 Requires<[IsThumb2, HasThumb2DSP]> {
2103 let Inst{15-12} = 0b1111;
2105 def t2USADA8 : T2FourReg_mac<0, 0b111, 0b0000, (outs rGPR:$Rd),
2106 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), NoItinerary,
2107 "usada8", "\t$Rd, $Rn, $Rm, $Ra", []>,
2108 Requires<[IsThumb2, HasThumb2DSP]>;
2110 // Signed/Unsigned saturate.
2111 class T2SatI<dag oops, dag iops, InstrItinClass itin,
2112 string opc, string asm, list<dag> pattern>
2113 : T2I<oops, iops, itin, opc, asm, pattern> {
2119 let Inst{11-8} = Rd;
2120 let Inst{19-16} = Rn;
2121 let Inst{4-0} = sat_imm;
2122 let Inst{21} = sh{5};
2123 let Inst{14-12} = sh{4-2};
2124 let Inst{7-6} = sh{1-0};
2129 (ins imm1_32:$sat_imm, rGPR:$Rn, t2_shift_imm:$sh),
2130 NoItinerary, "ssat", "\t$Rd, $sat_imm, $Rn$sh", []> {
2131 let Inst{31-27} = 0b11110;
2132 let Inst{25-22} = 0b1100;
2138 def t2SSAT16: T2SatI<
2139 (outs rGPR:$Rd), (ins imm1_16:$sat_imm, rGPR:$Rn), NoItinerary,
2140 "ssat16", "\t$Rd, $sat_imm, $Rn", []>,
2141 Requires<[IsThumb2, HasThumb2DSP]> {
2142 let Inst{31-27} = 0b11110;
2143 let Inst{25-22} = 0b1100;
2146 let Inst{21} = 1; // sh = '1'
2147 let Inst{14-12} = 0b000; // imm3 = '000'
2148 let Inst{7-6} = 0b00; // imm2 = '00'
2149 let Inst{5-4} = 0b00;
2154 (ins imm0_31:$sat_imm, rGPR:$Rn, t2_shift_imm:$sh),
2155 NoItinerary, "usat", "\t$Rd, $sat_imm, $Rn$sh", []> {
2156 let Inst{31-27} = 0b11110;
2157 let Inst{25-22} = 0b1110;
2162 def t2USAT16: T2SatI<(outs rGPR:$Rd), (ins imm0_15:$sat_imm, rGPR:$Rn),
2164 "usat16", "\t$Rd, $sat_imm, $Rn", []>,
2165 Requires<[IsThumb2, HasThumb2DSP]> {
2166 let Inst{31-22} = 0b1111001110;
2169 let Inst{21} = 1; // sh = '1'
2170 let Inst{14-12} = 0b000; // imm3 = '000'
2171 let Inst{7-6} = 0b00; // imm2 = '00'
2172 let Inst{5-4} = 0b00;
2175 def : T2Pat<(int_arm_ssat GPR:$a, imm:$pos), (t2SSAT imm:$pos, GPR:$a, 0)>;
2176 def : T2Pat<(int_arm_usat GPR:$a, imm:$pos), (t2USAT imm:$pos, GPR:$a, 0)>;
2178 //===----------------------------------------------------------------------===//
2179 // Shift and rotate Instructions.
2182 defm t2LSL : T2I_sh_ir<0b00, "lsl", imm0_31,
2183 BinOpFrag<(shl node:$LHS, node:$RHS)>>;
2184 defm t2LSR : T2I_sh_ir<0b01, "lsr", imm_sr,
2185 BinOpFrag<(srl node:$LHS, node:$RHS)>>;
2186 defm t2ASR : T2I_sh_ir<0b10, "asr", imm_sr,
2187 BinOpFrag<(sra node:$LHS, node:$RHS)>>;
2188 defm t2ROR : T2I_sh_ir<0b11, "ror", imm0_31,
2189 BinOpFrag<(rotr node:$LHS, node:$RHS)>>;
2191 // (rotr x, (and y, 0x...1f)) ==> (ROR x, y)
2192 def : T2Pat<(rotr rGPR:$lhs, (and rGPR:$rhs, lo5AllOne)),
2193 (t2RORrr rGPR:$lhs, rGPR:$rhs)>;
2195 let Uses = [CPSR] in {
2196 def t2RRX : T2sTwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iMOVsi,
2197 "rrx", "\t$Rd, $Rm",
2198 [(set rGPR:$Rd, (ARMrrx rGPR:$Rm))]>, Sched<[WriteALU]> {
2199 let Inst{31-27} = 0b11101;
2200 let Inst{26-25} = 0b01;
2201 let Inst{24-21} = 0b0010;
2202 let Inst{19-16} = 0b1111; // Rn
2203 let Inst{14-12} = 0b000;
2204 let Inst{7-4} = 0b0011;
2208 let isCodeGenOnly = 1, Defs = [CPSR] in {
2209 def t2MOVsrl_flag : T2TwoRegShiftImm<
2210 (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iMOVsi,
2211 "lsrs", ".w\t$Rd, $Rm, #1",
2212 [(set rGPR:$Rd, (ARMsrl_flag rGPR:$Rm))]>,
2214 let Inst{31-27} = 0b11101;
2215 let Inst{26-25} = 0b01;
2216 let Inst{24-21} = 0b0010;
2217 let Inst{20} = 1; // The S bit.
2218 let Inst{19-16} = 0b1111; // Rn
2219 let Inst{5-4} = 0b01; // Shift type.
2220 // Shift amount = Inst{14-12:7-6} = 1.
2221 let Inst{14-12} = 0b000;
2222 let Inst{7-6} = 0b01;
2224 def t2MOVsra_flag : T2TwoRegShiftImm<
2225 (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iMOVsi,
2226 "asrs", ".w\t$Rd, $Rm, #1",
2227 [(set rGPR:$Rd, (ARMsra_flag rGPR:$Rm))]>,
2229 let Inst{31-27} = 0b11101;
2230 let Inst{26-25} = 0b01;
2231 let Inst{24-21} = 0b0010;
2232 let Inst{20} = 1; // The S bit.
2233 let Inst{19-16} = 0b1111; // Rn
2234 let Inst{5-4} = 0b10; // Shift type.
2235 // Shift amount = Inst{14-12:7-6} = 1.
2236 let Inst{14-12} = 0b000;
2237 let Inst{7-6} = 0b01;
2241 //===----------------------------------------------------------------------===//
2242 // Bitwise Instructions.
2245 defm t2AND : T2I_bin_w_irs<0b0000, "and",
2246 IIC_iBITi, IIC_iBITr, IIC_iBITsi,
2247 BinOpFrag<(and node:$LHS, node:$RHS)>, 1>;
2248 defm t2ORR : T2I_bin_w_irs<0b0010, "orr",
2249 IIC_iBITi, IIC_iBITr, IIC_iBITsi,
2250 BinOpFrag<(or node:$LHS, node:$RHS)>, 1>;
2251 defm t2EOR : T2I_bin_w_irs<0b0100, "eor",
2252 IIC_iBITi, IIC_iBITr, IIC_iBITsi,
2253 BinOpFrag<(xor node:$LHS, node:$RHS)>, 1>;
2255 defm t2BIC : T2I_bin_w_irs<0b0001, "bic",
2256 IIC_iBITi, IIC_iBITr, IIC_iBITsi,
2257 BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
2259 class T2BitFI<dag oops, dag iops, InstrItinClass itin,
2260 string opc, string asm, list<dag> pattern>
2261 : T2I<oops, iops, itin, opc, asm, pattern> {
2266 let Inst{11-8} = Rd;
2267 let Inst{4-0} = msb{4-0};
2268 let Inst{14-12} = lsb{4-2};
2269 let Inst{7-6} = lsb{1-0};
2272 class T2TwoRegBitFI<dag oops, dag iops, InstrItinClass itin,
2273 string opc, string asm, list<dag> pattern>
2274 : T2BitFI<oops, iops, itin, opc, asm, pattern> {
2277 let Inst{19-16} = Rn;
2280 let Constraints = "$src = $Rd" in
2281 def t2BFC : T2BitFI<(outs rGPR:$Rd), (ins rGPR:$src, bf_inv_mask_imm:$imm),
2282 IIC_iUNAsi, "bfc", "\t$Rd, $imm",
2283 [(set rGPR:$Rd, (and rGPR:$src, bf_inv_mask_imm:$imm))]> {
2284 let Inst{31-27} = 0b11110;
2285 let Inst{26} = 0; // should be 0.
2287 let Inst{24-20} = 0b10110;
2288 let Inst{19-16} = 0b1111; // Rn
2290 let Inst{5} = 0; // should be 0.
2293 let msb{4-0} = imm{9-5};
2294 let lsb{4-0} = imm{4-0};
2297 def t2SBFX: T2TwoRegBitFI<
2298 (outs rGPR:$Rd), (ins rGPR:$Rn, imm0_31:$lsb, imm1_32:$msb),
2299 IIC_iUNAsi, "sbfx", "\t$Rd, $Rn, $lsb, $msb", []> {
2300 let Inst{31-27} = 0b11110;
2302 let Inst{24-20} = 0b10100;
2306 def t2UBFX: T2TwoRegBitFI<
2307 (outs rGPR:$Rd), (ins rGPR:$Rn, imm0_31:$lsb, imm1_32:$msb),
2308 IIC_iUNAsi, "ubfx", "\t$Rd, $Rn, $lsb, $msb", []> {
2309 let Inst{31-27} = 0b11110;
2311 let Inst{24-20} = 0b11100;
2315 // A8.6.18 BFI - Bitfield insert (Encoding T1)
2316 let Constraints = "$src = $Rd" in {
2317 def t2BFI : T2TwoRegBitFI<(outs rGPR:$Rd),
2318 (ins rGPR:$src, rGPR:$Rn, bf_inv_mask_imm:$imm),
2319 IIC_iBITi, "bfi", "\t$Rd, $Rn, $imm",
2320 [(set rGPR:$Rd, (ARMbfi rGPR:$src, rGPR:$Rn,
2321 bf_inv_mask_imm:$imm))]> {
2322 let Inst{31-27} = 0b11110;
2323 let Inst{26} = 0; // should be 0.
2325 let Inst{24-20} = 0b10110;
2327 let Inst{5} = 0; // should be 0.
2330 let msb{4-0} = imm{9-5};
2331 let lsb{4-0} = imm{4-0};
2335 defm t2ORN : T2I_bin_irs<0b0011, "orn",
2336 IIC_iBITi, IIC_iBITr, IIC_iBITsi,
2337 BinOpFrag<(or node:$LHS, (not node:$RHS))>, 0, "">;
2339 /// T2I_un_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a
2340 /// unary operation that produces a value. These are predicable and can be
2341 /// changed to modify CPSR.
2342 multiclass T2I_un_irs<bits<4> opcod, string opc,
2343 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
2345 bit Cheap = 0, bit ReMat = 0, bit MoveImm = 0> {
2347 def i : T2sOneRegImm<(outs rGPR:$Rd), (ins t2_so_imm:$imm), iii,
2349 [(set rGPR:$Rd, (opnode t2_so_imm:$imm))]>, Sched<[WriteALU]> {
2350 let isAsCheapAsAMove = Cheap;
2351 let isReMaterializable = ReMat;
2352 let isMoveImm = MoveImm;
2353 let Inst{31-27} = 0b11110;
2355 let Inst{24-21} = opcod;
2356 let Inst{19-16} = 0b1111; // Rn
2360 def r : T2sTwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm), iir,
2361 opc, ".w\t$Rd, $Rm",
2362 [(set rGPR:$Rd, (opnode rGPR:$Rm))]>, Sched<[WriteALU]> {
2363 let Inst{31-27} = 0b11101;
2364 let Inst{26-25} = 0b01;
2365 let Inst{24-21} = opcod;
2366 let Inst{19-16} = 0b1111; // Rn
2367 let Inst{14-12} = 0b000; // imm3
2368 let Inst{7-6} = 0b00; // imm2
2369 let Inst{5-4} = 0b00; // type
2372 def s : T2sOneRegShiftedReg<(outs rGPR:$Rd), (ins t2_so_reg:$ShiftedRm), iis,
2373 opc, ".w\t$Rd, $ShiftedRm",
2374 [(set rGPR:$Rd, (opnode t2_so_reg:$ShiftedRm))]>,
2376 let Inst{31-27} = 0b11101;
2377 let Inst{26-25} = 0b01;
2378 let Inst{24-21} = opcod;
2379 let Inst{19-16} = 0b1111; // Rn
2383 // Prefer over of t2EORri ra, rb, -1 because mvn has 16-bit version
2384 let AddedComplexity = 1 in
2385 defm t2MVN : T2I_un_irs <0b0011, "mvn",
2386 IIC_iMVNi, IIC_iMVNr, IIC_iMVNsi,
2387 UnOpFrag<(not node:$Src)>, 1, 1, 1>;
2389 let AddedComplexity = 1 in
2390 def : T2Pat<(and rGPR:$src, t2_so_imm_not:$imm),
2391 (t2BICri rGPR:$src, t2_so_imm_not:$imm)>;
2393 // top16Zero - answer true if the upper 16 bits of $src are 0, false otherwise
2394 def top16Zero: PatLeaf<(i32 rGPR:$src), [{
2395 return CurDAG->MaskedValueIsZero(SDValue(N,0), APInt::getHighBitsSet(32, 16));
2398 // so_imm_notSext is needed instead of so_imm_not, as the value of imm
2399 // will match the extended, not the original bitWidth for $src.
2400 def : T2Pat<(and top16Zero:$src, t2_so_imm_notSext:$imm),
2401 (t2BICri rGPR:$src, t2_so_imm_notSext:$imm)>;
2404 // FIXME: Disable this pattern on Darwin to workaround an assembler bug.
2405 def : T2Pat<(or rGPR:$src, t2_so_imm_not:$imm),
2406 (t2ORNri rGPR:$src, t2_so_imm_not:$imm)>,
2407 Requires<[IsThumb2]>;
2409 def : T2Pat<(t2_so_imm_not:$src),
2410 (t2MVNi t2_so_imm_not:$src)>;
2412 //===----------------------------------------------------------------------===//
2413 // Multiply Instructions.
2415 let isCommutable = 1 in
2416 def t2MUL: T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL32,
2417 "mul", "\t$Rd, $Rn, $Rm",
2418 [(set rGPR:$Rd, (mul rGPR:$Rn, rGPR:$Rm))]> {
2419 let Inst{31-27} = 0b11111;
2420 let Inst{26-23} = 0b0110;
2421 let Inst{22-20} = 0b000;
2422 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2423 let Inst{7-4} = 0b0000; // Multiply
2426 def t2MLA: T2FourReg<
2427 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2428 "mla", "\t$Rd, $Rn, $Rm, $Ra",
2429 [(set rGPR:$Rd, (add (mul rGPR:$Rn, rGPR:$Rm), rGPR:$Ra))]>,
2430 Requires<[IsThumb2, UseMulOps]> {
2431 let Inst{31-27} = 0b11111;
2432 let Inst{26-23} = 0b0110;
2433 let Inst{22-20} = 0b000;
2434 let Inst{7-4} = 0b0000; // Multiply
2437 def t2MLS: T2FourReg<
2438 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2439 "mls", "\t$Rd, $Rn, $Rm, $Ra",
2440 [(set rGPR:$Rd, (sub rGPR:$Ra, (mul rGPR:$Rn, rGPR:$Rm)))]>,
2441 Requires<[IsThumb2, UseMulOps]> {
2442 let Inst{31-27} = 0b11111;
2443 let Inst{26-23} = 0b0110;
2444 let Inst{22-20} = 0b000;
2445 let Inst{7-4} = 0b0001; // Multiply and Subtract
2448 // Extra precision multiplies with low / high results
2449 let neverHasSideEffects = 1 in {
2450 let isCommutable = 1 in {
2451 def t2SMULL : T2MulLong<0b000, 0b0000,
2452 (outs rGPR:$RdLo, rGPR:$RdHi),
2453 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL64,
2454 "smull", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2456 def t2UMULL : T2MulLong<0b010, 0b0000,
2457 (outs rGPR:$RdLo, rGPR:$RdHi),
2458 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL64,
2459 "umull", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2462 // Multiply + accumulate
2463 def t2SMLAL : T2MlaLong<0b100, 0b0000,
2464 (outs rGPR:$RdLo, rGPR:$RdHi),
2465 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$RLo, rGPR:$RHi), IIC_iMAC64,
2466 "smlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
2467 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">;
2469 def t2UMLAL : T2MlaLong<0b110, 0b0000,
2470 (outs rGPR:$RdLo, rGPR:$RdHi),
2471 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$RLo, rGPR:$RHi), IIC_iMAC64,
2472 "umlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
2473 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">;
2475 def t2UMAAL : T2MulLong<0b110, 0b0110,
2476 (outs rGPR:$RdLo, rGPR:$RdHi),
2477 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMAC64,
2478 "umaal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
2479 Requires<[IsThumb2, HasThumb2DSP]>;
2480 } // neverHasSideEffects
2482 // Rounding variants of the below included for disassembly only
2484 // Most significant word multiply
2485 def t2SMMUL : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL32,
2486 "smmul", "\t$Rd, $Rn, $Rm",
2487 [(set rGPR:$Rd, (mulhs rGPR:$Rn, rGPR:$Rm))]>,
2488 Requires<[IsThumb2, HasThumb2DSP]> {
2489 let Inst{31-27} = 0b11111;
2490 let Inst{26-23} = 0b0110;
2491 let Inst{22-20} = 0b101;
2492 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2493 let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
2496 def t2SMMULR : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL32,
2497 "smmulr", "\t$Rd, $Rn, $Rm", []>,
2498 Requires<[IsThumb2, HasThumb2DSP]> {
2499 let Inst{31-27} = 0b11111;
2500 let Inst{26-23} = 0b0110;
2501 let Inst{22-20} = 0b101;
2502 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2503 let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1)
2506 def t2SMMLA : T2FourReg<
2507 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2508 "smmla", "\t$Rd, $Rn, $Rm, $Ra",
2509 [(set rGPR:$Rd, (add (mulhs rGPR:$Rm, rGPR:$Rn), rGPR:$Ra))]>,
2510 Requires<[IsThumb2, HasThumb2DSP, UseMulOps]> {
2511 let Inst{31-27} = 0b11111;
2512 let Inst{26-23} = 0b0110;
2513 let Inst{22-20} = 0b101;
2514 let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
2517 def t2SMMLAR: T2FourReg<
2518 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2519 "smmlar", "\t$Rd, $Rn, $Rm, $Ra", []>,
2520 Requires<[IsThumb2, HasThumb2DSP]> {
2521 let Inst{31-27} = 0b11111;
2522 let Inst{26-23} = 0b0110;
2523 let Inst{22-20} = 0b101;
2524 let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1)
2527 def t2SMMLS: T2FourReg<
2528 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2529 "smmls", "\t$Rd, $Rn, $Rm, $Ra",
2530 [(set rGPR:$Rd, (sub rGPR:$Ra, (mulhs rGPR:$Rn, rGPR:$Rm)))]>,
2531 Requires<[IsThumb2, HasThumb2DSP, UseMulOps]> {
2532 let Inst{31-27} = 0b11111;
2533 let Inst{26-23} = 0b0110;
2534 let Inst{22-20} = 0b110;
2535 let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
2538 def t2SMMLSR:T2FourReg<
2539 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2540 "smmlsr", "\t$Rd, $Rn, $Rm, $Ra", []>,
2541 Requires<[IsThumb2, HasThumb2DSP]> {
2542 let Inst{31-27} = 0b11111;
2543 let Inst{26-23} = 0b0110;
2544 let Inst{22-20} = 0b110;
2545 let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1)
2548 multiclass T2I_smul<string opc, PatFrag opnode> {
2549 def BB : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2550 !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm",
2551 [(set rGPR:$Rd, (opnode (sext_inreg rGPR:$Rn, i16),
2552 (sext_inreg rGPR:$Rm, i16)))]>,
2553 Requires<[IsThumb2, HasThumb2DSP]> {
2554 let Inst{31-27} = 0b11111;
2555 let Inst{26-23} = 0b0110;
2556 let Inst{22-20} = 0b001;
2557 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2558 let Inst{7-6} = 0b00;
2559 let Inst{5-4} = 0b00;
2562 def BT : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2563 !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm",
2564 [(set rGPR:$Rd, (opnode (sext_inreg rGPR:$Rn, i16),
2565 (sra rGPR:$Rm, (i32 16))))]>,
2566 Requires<[IsThumb2, HasThumb2DSP]> {
2567 let Inst{31-27} = 0b11111;
2568 let Inst{26-23} = 0b0110;
2569 let Inst{22-20} = 0b001;
2570 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2571 let Inst{7-6} = 0b00;
2572 let Inst{5-4} = 0b01;
2575 def TB : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2576 !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm",
2577 [(set rGPR:$Rd, (opnode (sra rGPR:$Rn, (i32 16)),
2578 (sext_inreg rGPR:$Rm, i16)))]>,
2579 Requires<[IsThumb2, HasThumb2DSP]> {
2580 let Inst{31-27} = 0b11111;
2581 let Inst{26-23} = 0b0110;
2582 let Inst{22-20} = 0b001;
2583 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2584 let Inst{7-6} = 0b00;
2585 let Inst{5-4} = 0b10;
2588 def TT : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2589 !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm",
2590 [(set rGPR:$Rd, (opnode (sra rGPR:$Rn, (i32 16)),
2591 (sra rGPR:$Rm, (i32 16))))]>,
2592 Requires<[IsThumb2, HasThumb2DSP]> {
2593 let Inst{31-27} = 0b11111;
2594 let Inst{26-23} = 0b0110;
2595 let Inst{22-20} = 0b001;
2596 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2597 let Inst{7-6} = 0b00;
2598 let Inst{5-4} = 0b11;
2601 def WB : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2602 !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm",
2603 [(set rGPR:$Rd, (sra (opnode rGPR:$Rn,
2604 (sext_inreg rGPR:$Rm, i16)), (i32 16)))]>,
2605 Requires<[IsThumb2, HasThumb2DSP]> {
2606 let Inst{31-27} = 0b11111;
2607 let Inst{26-23} = 0b0110;
2608 let Inst{22-20} = 0b011;
2609 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2610 let Inst{7-6} = 0b00;
2611 let Inst{5-4} = 0b00;
2614 def WT : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2615 !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm",
2616 [(set rGPR:$Rd, (sra (opnode rGPR:$Rn,
2617 (sra rGPR:$Rm, (i32 16))), (i32 16)))]>,
2618 Requires<[IsThumb2, HasThumb2DSP]> {
2619 let Inst{31-27} = 0b11111;
2620 let Inst{26-23} = 0b0110;
2621 let Inst{22-20} = 0b011;
2622 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2623 let Inst{7-6} = 0b00;
2624 let Inst{5-4} = 0b01;
2629 multiclass T2I_smla<string opc, PatFrag opnode> {
2631 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2632 !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm, $Ra",
2633 [(set rGPR:$Rd, (add rGPR:$Ra,
2634 (opnode (sext_inreg rGPR:$Rn, i16),
2635 (sext_inreg rGPR:$Rm, i16))))]>,
2636 Requires<[IsThumb2, HasThumb2DSP, UseMulOps]> {
2637 let Inst{31-27} = 0b11111;
2638 let Inst{26-23} = 0b0110;
2639 let Inst{22-20} = 0b001;
2640 let Inst{7-6} = 0b00;
2641 let Inst{5-4} = 0b00;
2645 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2646 !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm, $Ra",
2647 [(set rGPR:$Rd, (add rGPR:$Ra, (opnode (sext_inreg rGPR:$Rn, i16),
2648 (sra rGPR:$Rm, (i32 16)))))]>,
2649 Requires<[IsThumb2, HasThumb2DSP, UseMulOps]> {
2650 let Inst{31-27} = 0b11111;
2651 let Inst{26-23} = 0b0110;
2652 let Inst{22-20} = 0b001;
2653 let Inst{7-6} = 0b00;
2654 let Inst{5-4} = 0b01;
2658 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2659 !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm, $Ra",
2660 [(set rGPR:$Rd, (add rGPR:$Ra, (opnode (sra rGPR:$Rn, (i32 16)),
2661 (sext_inreg rGPR:$Rm, i16))))]>,
2662 Requires<[IsThumb2, HasThumb2DSP, UseMulOps]> {
2663 let Inst{31-27} = 0b11111;
2664 let Inst{26-23} = 0b0110;
2665 let Inst{22-20} = 0b001;
2666 let Inst{7-6} = 0b00;
2667 let Inst{5-4} = 0b10;
2671 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2672 !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm, $Ra",
2673 [(set rGPR:$Rd, (add rGPR:$Ra, (opnode (sra rGPR:$Rn, (i32 16)),
2674 (sra rGPR:$Rm, (i32 16)))))]>,
2675 Requires<[IsThumb2, HasThumb2DSP, UseMulOps]> {
2676 let Inst{31-27} = 0b11111;
2677 let Inst{26-23} = 0b0110;
2678 let Inst{22-20} = 0b001;
2679 let Inst{7-6} = 0b00;
2680 let Inst{5-4} = 0b11;
2684 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2685 !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm, $Ra",
2686 [(set rGPR:$Rd, (add rGPR:$Ra, (sra (opnode rGPR:$Rn,
2687 (sext_inreg rGPR:$Rm, i16)), (i32 16))))]>,
2688 Requires<[IsThumb2, HasThumb2DSP, UseMulOps]> {
2689 let Inst{31-27} = 0b11111;
2690 let Inst{26-23} = 0b0110;
2691 let Inst{22-20} = 0b011;
2692 let Inst{7-6} = 0b00;
2693 let Inst{5-4} = 0b00;
2697 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2698 !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm, $Ra",
2699 [(set rGPR:$Rd, (add rGPR:$Ra, (sra (opnode rGPR:$Rn,
2700 (sra rGPR:$Rm, (i32 16))), (i32 16))))]>,
2701 Requires<[IsThumb2, HasThumb2DSP, UseMulOps]> {
2702 let Inst{31-27} = 0b11111;
2703 let Inst{26-23} = 0b0110;
2704 let Inst{22-20} = 0b011;
2705 let Inst{7-6} = 0b00;
2706 let Inst{5-4} = 0b01;
2710 defm t2SMUL : T2I_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
2711 defm t2SMLA : T2I_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
2713 // Halfword multiple accumulate long: SMLAL<x><y>
2714 def t2SMLALBB : T2FourReg_mac<1, 0b100, 0b1000, (outs rGPR:$Ra,rGPR:$Rd),
2715 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlalbb", "\t$Ra, $Rd, $Rn, $Rm",
2716 [/* For disassembly only; pattern left blank */]>,
2717 Requires<[IsThumb2, HasThumb2DSP]>;
2718 def t2SMLALBT : T2FourReg_mac<1, 0b100, 0b1001, (outs rGPR:$Ra,rGPR:$Rd),
2719 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlalbt", "\t$Ra, $Rd, $Rn, $Rm",
2720 [/* For disassembly only; pattern left blank */]>,
2721 Requires<[IsThumb2, HasThumb2DSP]>;
2722 def t2SMLALTB : T2FourReg_mac<1, 0b100, 0b1010, (outs rGPR:$Ra,rGPR:$Rd),
2723 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlaltb", "\t$Ra, $Rd, $Rn, $Rm",
2724 [/* For disassembly only; pattern left blank */]>,
2725 Requires<[IsThumb2, HasThumb2DSP]>;
2726 def t2SMLALTT : T2FourReg_mac<1, 0b100, 0b1011, (outs rGPR:$Ra,rGPR:$Rd),
2727 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlaltt", "\t$Ra, $Rd, $Rn, $Rm",
2728 [/* For disassembly only; pattern left blank */]>,
2729 Requires<[IsThumb2, HasThumb2DSP]>;
2731 // Dual halfword multiple: SMUAD, SMUSD, SMLAD, SMLSD, SMLALD, SMLSLD
2732 def t2SMUAD: T2ThreeReg_mac<
2733 0, 0b010, 0b0000, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
2734 IIC_iMAC32, "smuad", "\t$Rd, $Rn, $Rm", []>,
2735 Requires<[IsThumb2, HasThumb2DSP]> {
2736 let Inst{15-12} = 0b1111;
2738 def t2SMUADX:T2ThreeReg_mac<
2739 0, 0b010, 0b0001, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
2740 IIC_iMAC32, "smuadx", "\t$Rd, $Rn, $Rm", []>,
2741 Requires<[IsThumb2, HasThumb2DSP]> {
2742 let Inst{15-12} = 0b1111;
2744 def t2SMUSD: T2ThreeReg_mac<
2745 0, 0b100, 0b0000, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
2746 IIC_iMAC32, "smusd", "\t$Rd, $Rn, $Rm", []>,
2747 Requires<[IsThumb2, HasThumb2DSP]> {
2748 let Inst{15-12} = 0b1111;
2750 def t2SMUSDX:T2ThreeReg_mac<
2751 0, 0b100, 0b0001, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
2752 IIC_iMAC32, "smusdx", "\t$Rd, $Rn, $Rm", []>,
2753 Requires<[IsThumb2, HasThumb2DSP]> {
2754 let Inst{15-12} = 0b1111;
2756 def t2SMLAD : T2FourReg_mac<
2757 0, 0b010, 0b0000, (outs rGPR:$Rd),
2758 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smlad",
2759 "\t$Rd, $Rn, $Rm, $Ra", []>,
2760 Requires<[IsThumb2, HasThumb2DSP]>;
2761 def t2SMLADX : T2FourReg_mac<
2762 0, 0b010, 0b0001, (outs rGPR:$Rd),
2763 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smladx",
2764 "\t$Rd, $Rn, $Rm, $Ra", []>,
2765 Requires<[IsThumb2, HasThumb2DSP]>;
2766 def t2SMLSD : T2FourReg_mac<0, 0b100, 0b0000, (outs rGPR:$Rd),
2767 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smlsd",
2768 "\t$Rd, $Rn, $Rm, $Ra", []>,
2769 Requires<[IsThumb2, HasThumb2DSP]>;
2770 def t2SMLSDX : T2FourReg_mac<0, 0b100, 0b0001, (outs rGPR:$Rd),
2771 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smlsdx",
2772 "\t$Rd, $Rn, $Rm, $Ra", []>,
2773 Requires<[IsThumb2, HasThumb2DSP]>;
2774 def t2SMLALD : T2FourReg_mac<1, 0b100, 0b1100, (outs rGPR:$Ra,rGPR:$Rd),
2775 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMAC64, "smlald",
2776 "\t$Ra, $Rd, $Rn, $Rm", []>,
2777 Requires<[IsThumb2, HasThumb2DSP]>;
2778 def t2SMLALDX : T2FourReg_mac<1, 0b100, 0b1101, (outs rGPR:$Ra,rGPR:$Rd),
2779 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlaldx",
2780 "\t$Ra, $Rd, $Rn, $Rm", []>,
2781 Requires<[IsThumb2, HasThumb2DSP]>;
2782 def t2SMLSLD : T2FourReg_mac<1, 0b101, 0b1100, (outs rGPR:$Ra,rGPR:$Rd),
2783 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlsld",
2784 "\t$Ra, $Rd, $Rn, $Rm", []>,
2785 Requires<[IsThumb2, HasThumb2DSP]>;
2786 def t2SMLSLDX : T2FourReg_mac<1, 0b101, 0b1101, (outs rGPR:$Ra,rGPR:$Rd),
2787 (ins rGPR:$Rm,rGPR:$Rn), IIC_iMAC64, "smlsldx",
2788 "\t$Ra, $Rd, $Rn, $Rm", []>,
2789 Requires<[IsThumb2, HasThumb2DSP]>;
2791 //===----------------------------------------------------------------------===//
2792 // Division Instructions.
2793 // Signed and unsigned division on v7-M
2795 def t2SDIV : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iDIV,
2796 "sdiv", "\t$Rd, $Rn, $Rm",
2797 [(set rGPR:$Rd, (sdiv rGPR:$Rn, rGPR:$Rm))]>,
2798 Requires<[HasDivide, IsThumb2]> {
2799 let Inst{31-27} = 0b11111;
2800 let Inst{26-21} = 0b011100;
2802 let Inst{15-12} = 0b1111;
2803 let Inst{7-4} = 0b1111;
2806 def t2UDIV : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iDIV,
2807 "udiv", "\t$Rd, $Rn, $Rm",
2808 [(set rGPR:$Rd, (udiv rGPR:$Rn, rGPR:$Rm))]>,
2809 Requires<[HasDivide, IsThumb2]> {
2810 let Inst{31-27} = 0b11111;
2811 let Inst{26-21} = 0b011101;
2813 let Inst{15-12} = 0b1111;
2814 let Inst{7-4} = 0b1111;
2817 //===----------------------------------------------------------------------===//
2818 // Misc. Arithmetic Instructions.
2821 class T2I_misc<bits<2> op1, bits<2> op2, dag oops, dag iops,
2822 InstrItinClass itin, string opc, string asm, list<dag> pattern>
2823 : T2ThreeReg<oops, iops, itin, opc, asm, pattern> {
2824 let Inst{31-27} = 0b11111;
2825 let Inst{26-22} = 0b01010;
2826 let Inst{21-20} = op1;
2827 let Inst{15-12} = 0b1111;
2828 let Inst{7-6} = 0b10;
2829 let Inst{5-4} = op2;
2833 def t2CLZ : T2I_misc<0b11, 0b00, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2834 "clz", "\t$Rd, $Rm", [(set rGPR:$Rd, (ctlz rGPR:$Rm))]>,
2837 def t2RBIT : T2I_misc<0b01, 0b10, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2838 "rbit", "\t$Rd, $Rm",
2839 [(set rGPR:$Rd, (ARMrbit rGPR:$Rm))]>,
2842 def t2REV : T2I_misc<0b01, 0b00, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2843 "rev", ".w\t$Rd, $Rm", [(set rGPR:$Rd, (bswap rGPR:$Rm))]>,
2846 def t2REV16 : T2I_misc<0b01, 0b01, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2847 "rev16", ".w\t$Rd, $Rm",
2848 [(set rGPR:$Rd, (rotr (bswap rGPR:$Rm), (i32 16)))]>,
2851 def t2REVSH : T2I_misc<0b01, 0b11, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2852 "revsh", ".w\t$Rd, $Rm",
2853 [(set rGPR:$Rd, (sra (bswap rGPR:$Rm), (i32 16)))]>,
2856 def : T2Pat<(or (sra (shl rGPR:$Rm, (i32 24)), (i32 16)),
2857 (and (srl rGPR:$Rm, (i32 8)), 0xFF)),
2858 (t2REVSH rGPR:$Rm)>;
2860 def t2PKHBT : T2ThreeReg<
2861 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, pkh_lsl_amt:$sh),
2862 IIC_iBITsi, "pkhbt", "\t$Rd, $Rn, $Rm$sh",
2863 [(set rGPR:$Rd, (or (and rGPR:$Rn, 0xFFFF),
2864 (and (shl rGPR:$Rm, pkh_lsl_amt:$sh),
2866 Requires<[HasT2ExtractPack, IsThumb2]>,
2867 Sched<[WriteALUsi, ReadALU]> {
2868 let Inst{31-27} = 0b11101;
2869 let Inst{26-25} = 0b01;
2870 let Inst{24-20} = 0b01100;
2871 let Inst{5} = 0; // BT form
2875 let Inst{14-12} = sh{4-2};
2876 let Inst{7-6} = sh{1-0};
2879 // Alternate cases for PKHBT where identities eliminate some nodes.
2880 def : T2Pat<(or (and rGPR:$src1, 0xFFFF), (and rGPR:$src2, 0xFFFF0000)),
2881 (t2PKHBT rGPR:$src1, rGPR:$src2, 0)>,
2882 Requires<[HasT2ExtractPack, IsThumb2]>;
2883 def : T2Pat<(or (and rGPR:$src1, 0xFFFF), (shl rGPR:$src2, imm16_31:$sh)),
2884 (t2PKHBT rGPR:$src1, rGPR:$src2, imm16_31:$sh)>,
2885 Requires<[HasT2ExtractPack, IsThumb2]>;
2887 // Note: Shifts of 1-15 bits will be transformed to srl instead of sra and
2888 // will match the pattern below.
2889 def t2PKHTB : T2ThreeReg<
2890 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, pkh_asr_amt:$sh),
2891 IIC_iBITsi, "pkhtb", "\t$Rd, $Rn, $Rm$sh",
2892 [(set rGPR:$Rd, (or (and rGPR:$Rn, 0xFFFF0000),
2893 (and (sra rGPR:$Rm, pkh_asr_amt:$sh),
2895 Requires<[HasT2ExtractPack, IsThumb2]>,
2896 Sched<[WriteALUsi, ReadALU]> {
2897 let Inst{31-27} = 0b11101;
2898 let Inst{26-25} = 0b01;
2899 let Inst{24-20} = 0b01100;
2900 let Inst{5} = 1; // TB form
2904 let Inst{14-12} = sh{4-2};
2905 let Inst{7-6} = sh{1-0};
2908 // Alternate cases for PKHTB where identities eliminate some nodes. Note that
2909 // a shift amount of 0 is *not legal* here, it is PKHBT instead.
2910 def : T2Pat<(or (and rGPR:$src1, 0xFFFF0000), (srl rGPR:$src2, imm16_31:$sh)),
2911 (t2PKHTB rGPR:$src1, rGPR:$src2, imm16_31:$sh)>,
2912 Requires<[HasT2ExtractPack, IsThumb2]>;
2913 def : T2Pat<(or (and rGPR:$src1, 0xFFFF0000),
2914 (and (srl rGPR:$src2, imm1_15:$sh), 0xFFFF)),
2915 (t2PKHTB rGPR:$src1, rGPR:$src2, imm1_15:$sh)>,
2916 Requires<[HasT2ExtractPack, IsThumb2]>;
2918 //===----------------------------------------------------------------------===//
2919 // Comparison Instructions...
2921 defm t2CMP : T2I_cmp_irs<0b1101, "cmp",
2922 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsi,
2923 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
2925 def : T2Pat<(ARMcmpZ GPRnopc:$lhs, t2_so_imm:$imm),
2926 (t2CMPri GPRnopc:$lhs, t2_so_imm:$imm)>;
2927 def : T2Pat<(ARMcmpZ GPRnopc:$lhs, rGPR:$rhs),
2928 (t2CMPrr GPRnopc:$lhs, rGPR:$rhs)>;
2929 def : T2Pat<(ARMcmpZ GPRnopc:$lhs, t2_so_reg:$rhs),
2930 (t2CMPrs GPRnopc:$lhs, t2_so_reg:$rhs)>;
2932 let isCompare = 1, Defs = [CPSR] in {
2934 def t2CMNri : T2OneRegCmpImm<
2935 (outs), (ins GPRnopc:$Rn, t2_so_imm:$imm), IIC_iCMPi,
2936 "cmn", ".w\t$Rn, $imm",
2937 [(ARMcmn GPRnopc:$Rn, (ineg t2_so_imm:$imm))]>,
2938 Sched<[WriteCMP, ReadALU]> {
2939 let Inst{31-27} = 0b11110;
2941 let Inst{24-21} = 0b1000;
2942 let Inst{20} = 1; // The S bit.
2944 let Inst{11-8} = 0b1111; // Rd
2947 def t2CMNzrr : T2TwoRegCmp<
2948 (outs), (ins GPRnopc:$Rn, rGPR:$Rm), IIC_iCMPr,
2949 "cmn", ".w\t$Rn, $Rm",
2950 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>
2951 GPRnopc:$Rn, rGPR:$Rm)]>, Sched<[WriteCMP, ReadALU, ReadALU]> {
2952 let Inst{31-27} = 0b11101;
2953 let Inst{26-25} = 0b01;
2954 let Inst{24-21} = 0b1000;
2955 let Inst{20} = 1; // The S bit.
2956 let Inst{14-12} = 0b000; // imm3
2957 let Inst{11-8} = 0b1111; // Rd
2958 let Inst{7-6} = 0b00; // imm2
2959 let Inst{5-4} = 0b00; // type
2962 def t2CMNzrs : T2OneRegCmpShiftedReg<
2963 (outs), (ins GPRnopc:$Rn, t2_so_reg:$ShiftedRm), IIC_iCMPsi,
2964 "cmn", ".w\t$Rn, $ShiftedRm",
2965 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>
2966 GPRnopc:$Rn, t2_so_reg:$ShiftedRm)]>,
2967 Sched<[WriteCMPsi, ReadALU, ReadALU]> {
2968 let Inst{31-27} = 0b11101;
2969 let Inst{26-25} = 0b01;
2970 let Inst{24-21} = 0b1000;
2971 let Inst{20} = 1; // The S bit.
2972 let Inst{11-8} = 0b1111; // Rd
2976 // Assembler aliases w/o the ".w" suffix.
2977 // No alias here for 'rr' version as not all instantiations of this multiclass
2978 // want one (CMP in particular, does not).
2979 def : t2InstAlias<"cmn${p} $Rn, $imm",
2980 (t2CMNri GPRnopc:$Rn, t2_so_imm:$imm, pred:$p)>;
2981 def : t2InstAlias<"cmn${p} $Rn, $shift",
2982 (t2CMNzrs GPRnopc:$Rn, t2_so_reg:$shift, pred:$p)>;
2984 def : T2Pat<(ARMcmp GPR:$src, t2_so_imm_neg:$imm),
2985 (t2CMNri GPR:$src, t2_so_imm_neg:$imm)>;
2987 def : T2Pat<(ARMcmpZ GPRnopc:$src, t2_so_imm_neg:$imm),
2988 (t2CMNri GPRnopc:$src, t2_so_imm_neg:$imm)>;
2990 defm t2TST : T2I_cmp_irs<0b0000, "tst",
2991 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsi,
2992 BinOpFrag<(ARMcmpZ (and_su node:$LHS, node:$RHS), 0)>>;
2993 defm t2TEQ : T2I_cmp_irs<0b0100, "teq",
2994 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsi,
2995 BinOpFrag<(ARMcmpZ (xor_su node:$LHS, node:$RHS), 0)>>;
2997 // Conditional moves
2998 // FIXME: should be able to write a pattern for ARMcmov, but can't use
2999 // a two-value operand where a dag node expects two operands. :(
3000 let neverHasSideEffects = 1 in {
3002 let isCommutable = 1, isSelect = 1 in
3003 def t2MOVCCr : t2PseudoInst<(outs rGPR:$Rd),
3004 (ins rGPR:$false, rGPR:$Rm, pred:$p),
3006 [/*(set rGPR:$Rd, (ARMcmov rGPR:$false, rGPR:$Rm, imm:$cc, CCR:$ccr))*/]>,
3007 RegConstraint<"$false = $Rd">,
3010 let isMoveImm = 1 in
3011 def t2MOVCCi : t2PseudoInst<(outs rGPR:$Rd),
3012 (ins rGPR:$false, t2_so_imm:$imm, pred:$p),
3014 [/*(set rGPR:$Rd,(ARMcmov rGPR:$false,t2_so_imm:$imm, imm:$cc, CCR:$ccr))*/]>,
3015 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
3017 // FIXME: Pseudo-ize these. For now, just mark codegen only.
3018 let isCodeGenOnly = 1 in {
3019 let isMoveImm = 1 in
3020 def t2MOVCCi16 : T2I<(outs rGPR:$Rd), (ins rGPR:$false, imm0_65535_expr:$imm),
3022 "movw", "\t$Rd, $imm", []>,
3023 RegConstraint<"$false = $Rd">, Sched<[WriteALU]> {
3024 let Inst{31-27} = 0b11110;
3026 let Inst{24-21} = 0b0010;
3027 let Inst{20} = 0; // The S bit.
3033 let Inst{11-8} = Rd;
3034 let Inst{19-16} = imm{15-12};
3035 let Inst{26} = imm{11};
3036 let Inst{14-12} = imm{10-8};
3037 let Inst{7-0} = imm{7-0};
3040 let isMoveImm = 1 in
3041 def t2MOVCCi32imm : PseudoInst<(outs rGPR:$dst),
3042 (ins rGPR:$false, i32imm:$src, pred:$p),
3043 IIC_iCMOVix2, []>, RegConstraint<"$false = $dst">;
3045 let isMoveImm = 1 in
3046 def t2MVNCCi : T2OneRegImm<(outs rGPR:$Rd), (ins rGPR:$false, t2_so_imm:$imm),
3047 IIC_iCMOVi, "mvn", "\t$Rd, $imm",
3048 [/*(set rGPR:$Rd,(ARMcmov rGPR:$false,t2_so_imm_not:$imm,
3049 imm:$cc, CCR:$ccr))*/]>,
3050 RegConstraint<"$false = $Rd">, Sched<[WriteALU]> {
3051 let Inst{31-27} = 0b11110;
3053 let Inst{24-21} = 0b0011;
3054 let Inst{20} = 0; // The S bit.
3055 let Inst{19-16} = 0b1111; // Rn
3059 class T2I_movcc_sh<bits<2> opcod, dag oops, dag iops, InstrItinClass itin,
3060 string opc, string asm, list<dag> pattern>
3061 : T2TwoRegShiftImm<oops, iops, itin, opc, asm, pattern>, Sched<[WriteALU]> {
3062 let Inst{31-27} = 0b11101;
3063 let Inst{26-25} = 0b01;
3064 let Inst{24-21} = 0b0010;
3065 let Inst{20} = 0; // The S bit.
3066 let Inst{19-16} = 0b1111; // Rn
3067 let Inst{5-4} = opcod; // Shift type.
3069 def t2MOVCClsl : T2I_movcc_sh<0b00, (outs rGPR:$Rd),
3070 (ins rGPR:$false, rGPR:$Rm, i32imm:$imm),
3071 IIC_iCMOVsi, "lsl", ".w\t$Rd, $Rm, $imm", []>,
3072 RegConstraint<"$false = $Rd">;
3073 def t2MOVCClsr : T2I_movcc_sh<0b01, (outs rGPR:$Rd),
3074 (ins rGPR:$false, rGPR:$Rm, i32imm:$imm),
3075 IIC_iCMOVsi, "lsr", ".w\t$Rd, $Rm, $imm", []>,
3076 RegConstraint<"$false = $Rd">;
3077 def t2MOVCCasr : T2I_movcc_sh<0b10, (outs rGPR:$Rd),
3078 (ins rGPR:$false, rGPR:$Rm, i32imm:$imm),
3079 IIC_iCMOVsi, "asr", ".w\t$Rd, $Rm, $imm", []>,
3080 RegConstraint<"$false = $Rd">;
3081 def t2MOVCCror : T2I_movcc_sh<0b11, (outs rGPR:$Rd),
3082 (ins rGPR:$false, rGPR:$Rm, i32imm:$imm),
3083 IIC_iCMOVsi, "ror", ".w\t$Rd, $Rm, $imm", []>,
3084 RegConstraint<"$false = $Rd">;
3085 } // isCodeGenOnly = 1
3087 } // neverHasSideEffects
3089 //===----------------------------------------------------------------------===//
3090 // Atomic operations intrinsics
3093 // memory barriers protect the atomic sequences
3094 let hasSideEffects = 1 in {
3095 def t2DMB : AInoP<(outs), (ins memb_opt:$opt), ThumbFrm, NoItinerary,
3096 "dmb", "\t$opt", [(ARMMemBarrier (i32 imm:$opt))]>,
3097 Requires<[IsThumb, HasDB]> {
3099 let Inst{31-4} = 0xf3bf8f5;
3100 let Inst{3-0} = opt;
3104 def t2DSB : AInoP<(outs), (ins memb_opt:$opt), ThumbFrm, NoItinerary,
3105 "dsb", "\t$opt", []>,
3106 Requires<[IsThumb, HasDB]> {
3108 let Inst{31-4} = 0xf3bf8f4;
3109 let Inst{3-0} = opt;
3112 def t2ISB : AInoP<(outs), (ins instsyncb_opt:$opt), ThumbFrm, NoItinerary,
3114 []>, Requires<[IsThumb, HasDB]> {
3116 let Inst{31-4} = 0xf3bf8f6;
3117 let Inst{3-0} = opt;
3120 class T2I_ldrex<bits<2> opcod, dag oops, dag iops, AddrMode am, int sz,
3121 InstrItinClass itin, string opc, string asm, string cstr,
3122 list<dag> pattern, bits<4> rt2 = 0b1111>
3123 : Thumb2I<oops, iops, am, sz, itin, opc, asm, cstr, pattern> {
3124 let Inst{31-27} = 0b11101;
3125 let Inst{26-20} = 0b0001101;
3126 let Inst{11-8} = rt2;
3127 let Inst{7-6} = 0b01;
3128 let Inst{5-4} = opcod;
3129 let Inst{3-0} = 0b1111;
3133 let Inst{19-16} = addr;
3134 let Inst{15-12} = Rt;
3136 class T2I_strex<bits<2> opcod, dag oops, dag iops, AddrMode am, int sz,
3137 InstrItinClass itin, string opc, string asm, string cstr,
3138 list<dag> pattern, bits<4> rt2 = 0b1111>
3139 : Thumb2I<oops, iops, am, sz, itin, opc, asm, cstr, pattern> {
3140 let Inst{31-27} = 0b11101;
3141 let Inst{26-20} = 0b0001100;
3142 let Inst{11-8} = rt2;
3143 let Inst{7-6} = 0b01;
3144 let Inst{5-4} = opcod;
3150 let Inst{19-16} = addr;
3151 let Inst{15-12} = Rt;
3154 let mayLoad = 1 in {
3155 def t2LDREXB : T2I_ldrex<0b00, (outs rGPR:$Rt), (ins addr_offset_none:$addr),
3156 AddrModeNone, 4, NoItinerary,
3157 "ldrexb", "\t$Rt, $addr", "", []>;
3158 def t2LDREXH : T2I_ldrex<0b01, (outs rGPR:$Rt), (ins addr_offset_none:$addr),
3159 AddrModeNone, 4, NoItinerary,
3160 "ldrexh", "\t$Rt, $addr", "", []>;
3161 def t2LDREX : Thumb2I<(outs rGPR:$Rt), (ins t2addrmode_imm0_1020s4:$addr),
3162 AddrModeNone, 4, NoItinerary,
3163 "ldrex", "\t$Rt, $addr", "", []> {
3166 let Inst{31-27} = 0b11101;
3167 let Inst{26-20} = 0b0000101;
3168 let Inst{19-16} = addr{11-8};
3169 let Inst{15-12} = Rt;
3170 let Inst{11-8} = 0b1111;
3171 let Inst{7-0} = addr{7-0};
3173 let hasExtraDefRegAllocReq = 1 in
3174 def t2LDREXD : T2I_ldrex<0b11, (outs rGPR:$Rt, rGPR:$Rt2),
3175 (ins addr_offset_none:$addr),
3176 AddrModeNone, 4, NoItinerary,
3177 "ldrexd", "\t$Rt, $Rt2, $addr", "",
3180 let Inst{11-8} = Rt2;
3184 let mayStore = 1, Constraints = "@earlyclobber $Rd" in {
3185 def t2STREXB : T2I_strex<0b00, (outs rGPR:$Rd),
3186 (ins rGPR:$Rt, addr_offset_none:$addr),
3187 AddrModeNone, 4, NoItinerary,
3188 "strexb", "\t$Rd, $Rt, $addr", "", []>;
3189 def t2STREXH : T2I_strex<0b01, (outs rGPR:$Rd),
3190 (ins rGPR:$Rt, addr_offset_none:$addr),
3191 AddrModeNone, 4, NoItinerary,
3192 "strexh", "\t$Rd, $Rt, $addr", "", []>;
3193 def t2STREX : Thumb2I<(outs rGPR:$Rd), (ins rGPR:$Rt,
3194 t2addrmode_imm0_1020s4:$addr),
3195 AddrModeNone, 4, NoItinerary,
3196 "strex", "\t$Rd, $Rt, $addr", "",
3201 let Inst{31-27} = 0b11101;
3202 let Inst{26-20} = 0b0000100;
3203 let Inst{19-16} = addr{11-8};
3204 let Inst{15-12} = Rt;
3205 let Inst{11-8} = Rd;
3206 let Inst{7-0} = addr{7-0};
3208 let hasExtraSrcRegAllocReq = 1 in
3209 def t2STREXD : T2I_strex<0b11, (outs rGPR:$Rd),
3210 (ins rGPR:$Rt, rGPR:$Rt2, addr_offset_none:$addr),
3211 AddrModeNone, 4, NoItinerary,
3212 "strexd", "\t$Rd, $Rt, $Rt2, $addr", "", [],
3215 let Inst{11-8} = Rt2;
3219 def t2CLREX : T2I<(outs), (ins), NoItinerary, "clrex", "", []>,
3220 Requires<[IsThumb2, HasV7]> {
3221 let Inst{31-16} = 0xf3bf;
3222 let Inst{15-14} = 0b10;
3225 let Inst{11-8} = 0b1111;
3226 let Inst{7-4} = 0b0010;
3227 let Inst{3-0} = 0b1111;
3230 //===----------------------------------------------------------------------===//
3231 // SJLJ Exception handling intrinsics
3232 // eh_sjlj_setjmp() is an instruction sequence to store the return
3233 // address and save #0 in R0 for the non-longjmp case.
3234 // Since by its nature we may be coming from some other function to get
3235 // here, and we're using the stack frame for the containing function to
3236 // save/restore registers, we can't keep anything live in regs across
3237 // the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
3238 // when we get here from a longjmp(). We force everything out of registers
3239 // except for our own input by listing the relevant registers in Defs. By
3240 // doing so, we also cause the prologue/epilogue code to actively preserve
3241 // all of the callee-saved resgisters, which is exactly what we want.
3242 // $val is a scratch register for our use.
3244 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR,
3245 Q0, Q1, Q2, Q3, Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15],
3246 hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1,
3247 usesCustomInserter = 1 in {
3248 def t2Int_eh_sjlj_setjmp : Thumb2XI<(outs), (ins tGPR:$src, tGPR:$val),
3249 AddrModeNone, 0, NoItinerary, "", "",
3250 [(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>,
3251 Requires<[IsThumb2, HasVFP2]>;
3255 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR ],
3256 hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1,
3257 usesCustomInserter = 1 in {
3258 def t2Int_eh_sjlj_setjmp_nofp : Thumb2XI<(outs), (ins tGPR:$src, tGPR:$val),
3259 AddrModeNone, 0, NoItinerary, "", "",
3260 [(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>,
3261 Requires<[IsThumb2, NoVFP]>;
3265 //===----------------------------------------------------------------------===//
3266 // Control-Flow Instructions
3269 // FIXME: remove when we have a way to marking a MI with these properties.
3270 // FIXME: Should pc be an implicit operand like PICADD, etc?
3271 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
3272 hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in
3273 def t2LDMIA_RET: t2PseudoExpand<(outs GPR:$wb), (ins GPR:$Rn, pred:$p,
3274 reglist:$regs, variable_ops),
3275 4, IIC_iLoad_mBr, [],
3276 (t2LDMIA_UPD GPR:$wb, GPR:$Rn, pred:$p, reglist:$regs)>,
3277 RegConstraint<"$Rn = $wb">;
3279 let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
3280 let isPredicable = 1 in
3281 def t2B : T2I<(outs), (ins uncondbrtarget:$target), IIC_Br,
3283 [(br bb:$target)]>, Sched<[WriteBr]> {
3284 let Inst{31-27} = 0b11110;
3285 let Inst{15-14} = 0b10;
3289 let Inst{26} = target{19};
3290 let Inst{11} = target{18};
3291 let Inst{13} = target{17};
3292 let Inst{25-16} = target{20-11};
3293 let Inst{10-0} = target{10-0};
3294 let DecoderMethod = "DecodeT2BInstruction";
3297 let isNotDuplicable = 1, isIndirectBranch = 1 in {
3298 def t2BR_JT : t2PseudoInst<(outs),
3299 (ins GPR:$target, GPR:$index, i32imm:$jt, i32imm:$id),
3301 [(ARMbr2jt GPR:$target, GPR:$index, tjumptable:$jt, imm:$id)]>,
3304 // FIXME: Add a non-pc based case that can be predicated.
3305 def t2TBB_JT : t2PseudoInst<(outs),
3306 (ins GPR:$index, i32imm:$jt, i32imm:$id), 0, IIC_Br, []>,
3309 def t2TBH_JT : t2PseudoInst<(outs),
3310 (ins GPR:$index, i32imm:$jt, i32imm:$id), 0, IIC_Br, []>,
3313 def t2TBB : T2I<(outs), (ins addrmode_tbb:$addr), IIC_Br,
3314 "tbb", "\t$addr", []>, Sched<[WriteBrTbl]> {
3317 let Inst{31-20} = 0b111010001101;
3318 let Inst{19-16} = Rn;
3319 let Inst{15-5} = 0b11110000000;
3320 let Inst{4} = 0; // B form
3323 let DecoderMethod = "DecodeThumbTableBranch";
3326 def t2TBH : T2I<(outs), (ins addrmode_tbh:$addr), IIC_Br,
3327 "tbh", "\t$addr", []>, Sched<[WriteBrTbl]> {
3330 let Inst{31-20} = 0b111010001101;
3331 let Inst{19-16} = Rn;
3332 let Inst{15-5} = 0b11110000000;
3333 let Inst{4} = 1; // H form
3336 let DecoderMethod = "DecodeThumbTableBranch";
3338 } // isNotDuplicable, isIndirectBranch
3340 } // isBranch, isTerminator, isBarrier
3342 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
3343 // a two-value operand where a dag node expects ", "two operands. :(
3344 let isBranch = 1, isTerminator = 1 in
3345 def t2Bcc : T2I<(outs), (ins brtarget:$target), IIC_Br,
3347 [/*(ARMbrcond bb:$target, imm:$cc)*/]>, Sched<[WriteBr]> {
3348 let Inst{31-27} = 0b11110;
3349 let Inst{15-14} = 0b10;
3353 let Inst{25-22} = p;
3356 let Inst{26} = target{20};
3357 let Inst{11} = target{19};
3358 let Inst{13} = target{18};
3359 let Inst{21-16} = target{17-12};
3360 let Inst{10-0} = target{11-1};
3362 let DecoderMethod = "DecodeThumb2BCCInstruction";
3365 // Tail calls. The IOS version of thumb tail calls uses a t2 branch, so
3367 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in {
3370 def tTAILJMPd: tPseudoExpand<(outs),
3371 (ins uncondbrtarget:$dst, pred:$p),
3373 (t2B uncondbrtarget:$dst, pred:$p)>,
3374 Requires<[IsThumb2, IsIOS]>, Sched<[WriteBr]>;
3378 let Defs = [ITSTATE] in
3379 def t2IT : Thumb2XI<(outs), (ins it_pred:$cc, it_mask:$mask),
3380 AddrModeNone, 2, IIC_iALUx,
3381 "it$mask\t$cc", "", []> {
3382 // 16-bit instruction.
3383 let Inst{31-16} = 0x0000;
3384 let Inst{15-8} = 0b10111111;
3389 let Inst{3-0} = mask;
3391 let DecoderMethod = "DecodeIT";
3394 // Branch and Exchange Jazelle -- for disassembly only
3396 def t2BXJ : T2I<(outs), (ins rGPR:$func), NoItinerary, "bxj", "\t$func", []>,
3399 let Inst{31-27} = 0b11110;
3401 let Inst{25-20} = 0b111100;
3402 let Inst{19-16} = func;
3403 let Inst{15-0} = 0b1000111100000000;
3406 // Compare and branch on zero / non-zero
3407 let isBranch = 1, isTerminator = 1 in {
3408 def tCBZ : T1I<(outs), (ins tGPR:$Rn, t_cbtarget:$target), IIC_Br,
3409 "cbz\t$Rn, $target", []>,
3410 T1Misc<{0,0,?,1,?,?,?}>,
3411 Requires<[IsThumb2]>, Sched<[WriteBr]> {
3415 let Inst{9} = target{5};
3416 let Inst{7-3} = target{4-0};
3420 def tCBNZ : T1I<(outs), (ins tGPR:$Rn, t_cbtarget:$target), IIC_Br,
3421 "cbnz\t$Rn, $target", []>,
3422 T1Misc<{1,0,?,1,?,?,?}>,
3423 Requires<[IsThumb2]>, Sched<[WriteBr]> {
3427 let Inst{9} = target{5};
3428 let Inst{7-3} = target{4-0};
3434 // Change Processor State is a system instruction.
3435 // FIXME: Since the asm parser has currently no clean way to handle optional
3436 // operands, create 3 versions of the same instruction. Once there's a clean
3437 // framework to represent optional operands, change this behavior.
3438 class t2CPS<dag iops, string asm_op> : T2XI<(outs), iops, NoItinerary,
3439 !strconcat("cps", asm_op), []> {
3445 let Inst{31-11} = 0b111100111010111110000;
3446 let Inst{10-9} = imod;
3448 let Inst{7-5} = iflags;
3449 let Inst{4-0} = mode;
3450 let DecoderMethod = "DecodeT2CPSInstruction";
3454 def t2CPS3p : t2CPS<(ins imod_op:$imod, iflags_op:$iflags, i32imm:$mode),
3455 "$imod.w\t$iflags, $mode">;
3456 let mode = 0, M = 0 in
3457 def t2CPS2p : t2CPS<(ins imod_op:$imod, iflags_op:$iflags),
3458 "$imod.w\t$iflags">;
3459 let imod = 0, iflags = 0, M = 1 in
3460 def t2CPS1p : t2CPS<(ins imm0_31:$mode), "\t$mode">;
3462 // A6.3.4 Branches and miscellaneous control
3463 // Table A6-14 Change Processor State, and hint instructions
3464 def t2HINT : T2I<(outs), (ins imm0_4:$imm), NoItinerary, "hint", "\t$imm",[]> {
3466 let Inst{31-3} = 0b11110011101011111000000000000;
3467 let Inst{2-0} = imm;
3470 def : t2InstAlias<"hint$p.w $imm", (t2HINT imm0_4:$imm, pred:$p)>;
3471 def : t2InstAlias<"nop$p.w", (t2HINT 0, pred:$p)>;
3472 def : t2InstAlias<"yield$p.w", (t2HINT 1, pred:$p)>;
3473 def : t2InstAlias<"wfe$p.w", (t2HINT 2, pred:$p)>;
3474 def : t2InstAlias<"wfi$p.w", (t2HINT 3, pred:$p)>;
3475 def : t2InstAlias<"sev$p.w", (t2HINT 4, pred:$p)>;
3477 def t2DBG : T2I<(outs), (ins imm0_15:$opt), NoItinerary, "dbg", "\t$opt", []> {
3479 let Inst{31-20} = 0b111100111010;
3480 let Inst{19-16} = 0b1111;
3481 let Inst{15-8} = 0b10000000;
3482 let Inst{7-4} = 0b1111;
3483 let Inst{3-0} = opt;
3486 // Secure Monitor Call is a system instruction.
3487 // Option = Inst{19-16}
3488 def t2SMC : T2I<(outs), (ins imm0_15:$opt), NoItinerary, "smc", "\t$opt",
3489 []>, Requires<[IsThumb2, HasTrustZone]> {
3490 let Inst{31-27} = 0b11110;
3491 let Inst{26-20} = 0b1111111;
3492 let Inst{15-12} = 0b1000;
3495 let Inst{19-16} = opt;
3498 class T2SRS<bits<2> Op, bit W, dag oops, dag iops, InstrItinClass itin,
3499 string opc, string asm, list<dag> pattern>
3500 : T2I<oops, iops, itin, opc, asm, pattern> {
3502 let Inst{31-25} = 0b1110100;
3503 let Inst{24-23} = Op;
3506 let Inst{20-16} = 0b01101;
3507 let Inst{15-5} = 0b11000000000;
3508 let Inst{4-0} = mode{4-0};
3511 // Store Return State is a system instruction.
3512 def t2SRSDB_UPD : T2SRS<0b00, 1, (outs), (ins imm0_31:$mode), NoItinerary,
3513 "srsdb", "\tsp!, $mode", []>;
3514 def t2SRSDB : T2SRS<0b00, 0, (outs), (ins imm0_31:$mode), NoItinerary,
3515 "srsdb","\tsp, $mode", []>;
3516 def t2SRSIA_UPD : T2SRS<0b11, 1, (outs), (ins imm0_31:$mode), NoItinerary,
3517 "srsia","\tsp!, $mode", []>;
3518 def t2SRSIA : T2SRS<0b11, 0, (outs), (ins imm0_31:$mode), NoItinerary,
3519 "srsia","\tsp, $mode", []>;
3522 def : t2InstAlias<"srsdb${p} $mode", (t2SRSDB imm0_31:$mode, pred:$p)>;
3523 def : t2InstAlias<"srsdb${p} $mode!", (t2SRSDB_UPD imm0_31:$mode, pred:$p)>;
3525 def : t2InstAlias<"srsia${p} $mode", (t2SRSIA imm0_31:$mode, pred:$p)>;
3526 def : t2InstAlias<"srsia${p} $mode!", (t2SRSIA_UPD imm0_31:$mode, pred:$p)>;
3528 // Return From Exception is a system instruction.
3529 class T2RFE<bits<12> op31_20, dag oops, dag iops, InstrItinClass itin,
3530 string opc, string asm, list<dag> pattern>
3531 : T2I<oops, iops, itin, opc, asm, pattern> {
3532 let Inst{31-20} = op31_20{11-0};
3535 let Inst{19-16} = Rn;
3536 let Inst{15-0} = 0xc000;
3539 def t2RFEDBW : T2RFE<0b111010000011,
3540 (outs), (ins GPR:$Rn), NoItinerary, "rfedb", "\t$Rn!",
3541 [/* For disassembly only; pattern left blank */]>;
3542 def t2RFEDB : T2RFE<0b111010000001,
3543 (outs), (ins GPR:$Rn), NoItinerary, "rfedb", "\t$Rn",
3544 [/* For disassembly only; pattern left blank */]>;
3545 def t2RFEIAW : T2RFE<0b111010011011,
3546 (outs), (ins GPR:$Rn), NoItinerary, "rfeia", "\t$Rn!",
3547 [/* For disassembly only; pattern left blank */]>;
3548 def t2RFEIA : T2RFE<0b111010011001,
3549 (outs), (ins GPR:$Rn), NoItinerary, "rfeia", "\t$Rn",
3550 [/* For disassembly only; pattern left blank */]>;
3552 //===----------------------------------------------------------------------===//
3553 // Non-Instruction Patterns
3556 // 32-bit immediate using movw + movt.
3557 // This is a single pseudo instruction to make it re-materializable.
3558 // FIXME: Remove this when we can do generalized remat.
3559 let isReMaterializable = 1, isMoveImm = 1 in
3560 def t2MOVi32imm : PseudoInst<(outs rGPR:$dst), (ins i32imm:$src), IIC_iMOVix2,
3561 [(set rGPR:$dst, (i32 imm:$src))]>,
3562 Requires<[IsThumb, HasV6T2]>;
3564 // Pseudo instruction that combines movw + movt + add pc (if pic).
3565 // It also makes it possible to rematerialize the instructions.
3566 // FIXME: Remove this when we can do generalized remat and when machine licm
3567 // can properly the instructions.
3568 let isReMaterializable = 1 in {
3569 def t2MOV_ga_pcrel : PseudoInst<(outs rGPR:$dst), (ins i32imm:$addr),
3571 [(set rGPR:$dst, (ARMWrapperPIC tglobaladdr:$addr))]>,
3572 Requires<[IsThumb2, UseMovt]>;
3574 def t2MOV_ga_dyn : PseudoInst<(outs rGPR:$dst), (ins i32imm:$addr),
3576 [(set rGPR:$dst, (ARMWrapperDYN tglobaladdr:$addr))]>,
3577 Requires<[IsThumb2, UseMovt]>;
3580 // ConstantPool, GlobalAddress, and JumpTable
3581 def : T2Pat<(ARMWrapper tglobaladdr :$dst), (t2LEApcrel tglobaladdr :$dst)>,
3582 Requires<[IsThumb2, DontUseMovt]>;
3583 def : T2Pat<(ARMWrapper tconstpool :$dst), (t2LEApcrel tconstpool :$dst)>;
3584 def : T2Pat<(ARMWrapper tglobaladdr :$dst), (t2MOVi32imm tglobaladdr :$dst)>,
3585 Requires<[IsThumb2, UseMovt]>;
3587 def : T2Pat<(ARMWrapperJT tjumptable:$dst, imm:$id),
3588 (t2LEApcrelJT tjumptable:$dst, imm:$id)>;
3590 // Pseudo instruction that combines ldr from constpool and add pc. This should
3591 // be expanded into two instructions late to allow if-conversion and
3593 let canFoldAsLoad = 1, isReMaterializable = 1 in
3594 def t2LDRpci_pic : PseudoInst<(outs rGPR:$dst), (ins i32imm:$addr, pclabel:$cp),
3596 [(set rGPR:$dst, (ARMpic_add (load (ARMWrapper tconstpool:$addr)),
3598 Requires<[IsThumb2]>;
3600 // Pseudo isntruction that combines movs + predicated rsbmi
3601 // to implement integer ABS
3602 let usesCustomInserter = 1, Defs = [CPSR] in {
3603 def t2ABS : PseudoInst<(outs rGPR:$dst), (ins rGPR:$src),
3604 NoItinerary, []>, Requires<[IsThumb2]>;
3607 //===----------------------------------------------------------------------===//
3608 // Coprocessor load/store -- for disassembly only
3610 class T2CI<bits<4> op31_28, dag oops, dag iops, string opc, string asm>
3611 : T2I<oops, iops, NoItinerary, opc, asm, []> {
3612 let Inst{31-28} = op31_28;
3613 let Inst{27-25} = 0b110;
3616 multiclass t2LdStCop<bits<4> op31_28, bit load, bit Dbit, string asm> {
3617 def _OFFSET : T2CI<op31_28,
3618 (outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr),
3619 asm, "\t$cop, $CRd, $addr"> {
3623 let Inst{24} = 1; // P = 1
3624 let Inst{23} = addr{8};
3625 let Inst{22} = Dbit;
3626 let Inst{21} = 0; // W = 0
3627 let Inst{20} = load;
3628 let Inst{19-16} = addr{12-9};
3629 let Inst{15-12} = CRd;
3630 let Inst{11-8} = cop;
3631 let Inst{7-0} = addr{7-0};
3632 let DecoderMethod = "DecodeCopMemInstruction";
3634 def _PRE : T2CI<op31_28,
3635 (outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5_pre:$addr),
3636 asm, "\t$cop, $CRd, $addr!"> {
3640 let Inst{24} = 1; // P = 1
3641 let Inst{23} = addr{8};
3642 let Inst{22} = Dbit;
3643 let Inst{21} = 1; // W = 1
3644 let Inst{20} = load;
3645 let Inst{19-16} = addr{12-9};
3646 let Inst{15-12} = CRd;
3647 let Inst{11-8} = cop;
3648 let Inst{7-0} = addr{7-0};
3649 let DecoderMethod = "DecodeCopMemInstruction";
3651 def _POST: T2CI<op31_28,
3652 (outs), (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
3653 postidx_imm8s4:$offset),
3654 asm, "\t$cop, $CRd, $addr, $offset"> {
3659 let Inst{24} = 0; // P = 0
3660 let Inst{23} = offset{8};
3661 let Inst{22} = Dbit;
3662 let Inst{21} = 1; // W = 1
3663 let Inst{20} = load;
3664 let Inst{19-16} = addr;
3665 let Inst{15-12} = CRd;
3666 let Inst{11-8} = cop;
3667 let Inst{7-0} = offset{7-0};
3668 let DecoderMethod = "DecodeCopMemInstruction";
3670 def _OPTION : T2CI<op31_28, (outs),
3671 (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
3672 coproc_option_imm:$option),
3673 asm, "\t$cop, $CRd, $addr, $option"> {
3678 let Inst{24} = 0; // P = 0
3679 let Inst{23} = 1; // U = 1
3680 let Inst{22} = Dbit;
3681 let Inst{21} = 0; // W = 0
3682 let Inst{20} = load;
3683 let Inst{19-16} = addr;
3684 let Inst{15-12} = CRd;
3685 let Inst{11-8} = cop;
3686 let Inst{7-0} = option;
3687 let DecoderMethod = "DecodeCopMemInstruction";
3691 defm t2LDC : t2LdStCop<0b1110, 1, 0, "ldc">;
3692 defm t2LDCL : t2LdStCop<0b1110, 1, 1, "ldcl">;
3693 defm t2STC : t2LdStCop<0b1110, 0, 0, "stc">;
3694 defm t2STCL : t2LdStCop<0b1110, 0, 1, "stcl">;
3695 defm t2LDC2 : t2LdStCop<0b1111, 1, 0, "ldc2">;
3696 defm t2LDC2L : t2LdStCop<0b1111, 1, 1, "ldc2l">;
3697 defm t2STC2 : t2LdStCop<0b1111, 0, 0, "stc2">;
3698 defm t2STC2L : t2LdStCop<0b1111, 0, 1, "stc2l">;
3701 //===----------------------------------------------------------------------===//
3702 // Move between special register and ARM core register -- for disassembly only
3704 // Move to ARM core register from Special Register
3708 // A/R class can only move from CPSR or SPSR.
3709 def t2MRS_AR : T2I<(outs GPR:$Rd), (ins), NoItinerary, "mrs", "\t$Rd, apsr",
3710 []>, Requires<[IsThumb2,IsARClass]> {
3712 let Inst{31-12} = 0b11110011111011111000;
3713 let Inst{11-8} = Rd;
3714 let Inst{7-0} = 0b0000;
3717 def : t2InstAlias<"mrs${p} $Rd, cpsr", (t2MRS_AR GPR:$Rd, pred:$p)>;
3719 def t2MRSsys_AR: T2I<(outs GPR:$Rd), (ins), NoItinerary, "mrs", "\t$Rd, spsr",
3720 []>, Requires<[IsThumb2,IsARClass]> {
3722 let Inst{31-12} = 0b11110011111111111000;
3723 let Inst{11-8} = Rd;
3724 let Inst{7-0} = 0b0000;
3729 // This MRS has a mask field in bits 7-0 and can take more values than
3730 // the A/R class (a full msr_mask).
3731 def t2MRS_M : T2I<(outs rGPR:$Rd), (ins msr_mask:$mask), NoItinerary,
3732 "mrs", "\t$Rd, $mask", []>,
3733 Requires<[IsThumb,IsMClass]> {
3736 let Inst{31-12} = 0b11110011111011111000;
3737 let Inst{11-8} = Rd;
3738 let Inst{19-16} = 0b1111;
3739 let Inst{7-0} = mask;
3743 // Move from ARM core register to Special Register
3747 // No need to have both system and application versions, the encodings are the
3748 // same and the assembly parser has no way to distinguish between them. The mask
3749 // operand contains the special register (R Bit) in bit 4 and bits 3-0 contains
3750 // the mask with the fields to be accessed in the special register.
3751 def t2MSR_AR : T2I<(outs), (ins msr_mask:$mask, rGPR:$Rn),
3752 NoItinerary, "msr", "\t$mask, $Rn", []>,
3753 Requires<[IsThumb2,IsARClass]> {
3756 let Inst{31-21} = 0b11110011100;
3757 let Inst{20} = mask{4}; // R Bit
3758 let Inst{19-16} = Rn;
3759 let Inst{15-12} = 0b1000;
3760 let Inst{11-8} = mask{3-0};
3766 // Move from ARM core register to Special Register
3767 def t2MSR_M : T2I<(outs), (ins msr_mask:$SYSm, rGPR:$Rn),
3768 NoItinerary, "msr", "\t$SYSm, $Rn", []>,
3769 Requires<[IsThumb,IsMClass]> {
3772 let Inst{31-21} = 0b11110011100;
3774 let Inst{19-16} = Rn;
3775 let Inst{15-12} = 0b1000;
3776 let Inst{11-0} = SYSm;
3780 //===----------------------------------------------------------------------===//
3781 // Move between coprocessor and ARM core register
3784 class t2MovRCopro<bits<4> Op, string opc, bit direction, dag oops, dag iops,
3786 : T2Cop<Op, oops, iops,
3787 !strconcat(opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2"),
3789 let Inst{27-24} = 0b1110;
3790 let Inst{20} = direction;
3800 let Inst{15-12} = Rt;
3801 let Inst{11-8} = cop;
3802 let Inst{23-21} = opc1;
3803 let Inst{7-5} = opc2;
3804 let Inst{3-0} = CRm;
3805 let Inst{19-16} = CRn;
3808 class t2MovRRCopro<bits<4> Op, string opc, bit direction,
3809 list<dag> pattern = []>
3811 (ins p_imm:$cop, imm0_15:$opc1, GPR:$Rt, GPR:$Rt2, c_imm:$CRm),
3812 !strconcat(opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm"), pattern> {
3813 let Inst{27-24} = 0b1100;
3814 let Inst{23-21} = 0b010;
3815 let Inst{20} = direction;
3823 let Inst{15-12} = Rt;
3824 let Inst{19-16} = Rt2;
3825 let Inst{11-8} = cop;
3826 let Inst{7-4} = opc1;
3827 let Inst{3-0} = CRm;
3830 /* from ARM core register to coprocessor */
3831 def t2MCR : t2MovRCopro<0b1110, "mcr", 0,
3833 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
3834 c_imm:$CRm, imm0_7:$opc2),
3835 [(int_arm_mcr imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
3836 imm:$CRm, imm:$opc2)]>;
3837 def : t2InstAlias<"mcr $cop, $opc1, $Rt, $CRn, $CRm",
3838 (t2MCR p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
3840 def t2MCR2 : t2MovRCopro<0b1111, "mcr2", 0,
3841 (outs), (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
3842 c_imm:$CRm, imm0_7:$opc2),
3843 [(int_arm_mcr2 imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
3844 imm:$CRm, imm:$opc2)]>;
3845 def : t2InstAlias<"mcr2 $cop, $opc1, $Rt, $CRn, $CRm",
3846 (t2MCR2 p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
3849 /* from coprocessor to ARM core register */
3850 def t2MRC : t2MovRCopro<0b1110, "mrc", 1,
3851 (outs GPR:$Rt), (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
3852 c_imm:$CRm, imm0_7:$opc2), []>;
3853 def : t2InstAlias<"mrc $cop, $opc1, $Rt, $CRn, $CRm",
3854 (t2MRC GPR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
3857 def t2MRC2 : t2MovRCopro<0b1111, "mrc2", 1,
3858 (outs GPR:$Rt), (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
3859 c_imm:$CRm, imm0_7:$opc2), []>;
3860 def : t2InstAlias<"mrc2 $cop, $opc1, $Rt, $CRn, $CRm",
3861 (t2MRC2 GPR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
3864 def : T2v6Pat<(int_arm_mrc imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2),
3865 (t2MRC imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
3867 def : T2v6Pat<(int_arm_mrc2 imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2),
3868 (t2MRC2 imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
3871 /* from ARM core register to coprocessor */
3872 def t2MCRR : t2MovRRCopro<0b1110, "mcrr", 0,
3873 [(int_arm_mcrr imm:$cop, imm:$opc1, GPR:$Rt, GPR:$Rt2,
3875 def t2MCRR2 : t2MovRRCopro<0b1111, "mcrr2", 0,
3876 [(int_arm_mcrr2 imm:$cop, imm:$opc1, GPR:$Rt,
3877 GPR:$Rt2, imm:$CRm)]>;
3878 /* from coprocessor to ARM core register */
3879 def t2MRRC : t2MovRRCopro<0b1110, "mrrc", 1>;
3881 def t2MRRC2 : t2MovRRCopro<0b1111, "mrrc2", 1>;
3883 //===----------------------------------------------------------------------===//
3884 // Other Coprocessor Instructions.
3887 def tCDP : T2Cop<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1,
3888 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
3889 "cdp\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
3890 [(int_arm_cdp imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
3891 imm:$CRm, imm:$opc2)]> {
3892 let Inst{27-24} = 0b1110;
3901 let Inst{3-0} = CRm;
3903 let Inst{7-5} = opc2;
3904 let Inst{11-8} = cop;
3905 let Inst{15-12} = CRd;
3906 let Inst{19-16} = CRn;
3907 let Inst{23-20} = opc1;
3910 def t2CDP2 : T2Cop<0b1111, (outs), (ins p_imm:$cop, imm0_15:$opc1,
3911 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
3912 "cdp2\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
3913 [(int_arm_cdp2 imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
3914 imm:$CRm, imm:$opc2)]> {
3915 let Inst{27-24} = 0b1110;
3924 let Inst{3-0} = CRm;
3926 let Inst{7-5} = opc2;
3927 let Inst{11-8} = cop;
3928 let Inst{15-12} = CRd;
3929 let Inst{19-16} = CRn;
3930 let Inst{23-20} = opc1;
3935 //===----------------------------------------------------------------------===//
3936 // Non-Instruction Patterns
3939 // SXT/UXT with no rotate
3940 let AddedComplexity = 16 in {
3941 def : T2Pat<(and rGPR:$Rm, 0x000000FF), (t2UXTB rGPR:$Rm, 0)>,
3942 Requires<[IsThumb2]>;
3943 def : T2Pat<(and rGPR:$Rm, 0x0000FFFF), (t2UXTH rGPR:$Rm, 0)>,
3944 Requires<[IsThumb2]>;
3945 def : T2Pat<(and rGPR:$Rm, 0x00FF00FF), (t2UXTB16 rGPR:$Rm, 0)>,
3946 Requires<[HasT2ExtractPack, IsThumb2]>;
3947 def : T2Pat<(add rGPR:$Rn, (and rGPR:$Rm, 0x00FF)),
3948 (t2UXTAB rGPR:$Rn, rGPR:$Rm, 0)>,
3949 Requires<[HasT2ExtractPack, IsThumb2]>;
3950 def : T2Pat<(add rGPR:$Rn, (and rGPR:$Rm, 0xFFFF)),
3951 (t2UXTAH rGPR:$Rn, rGPR:$Rm, 0)>,
3952 Requires<[HasT2ExtractPack, IsThumb2]>;
3955 def : T2Pat<(sext_inreg rGPR:$Src, i8), (t2SXTB rGPR:$Src, 0)>,
3956 Requires<[IsThumb2]>;
3957 def : T2Pat<(sext_inreg rGPR:$Src, i16), (t2SXTH rGPR:$Src, 0)>,
3958 Requires<[IsThumb2]>;
3959 def : T2Pat<(add rGPR:$Rn, (sext_inreg rGPR:$Rm, i8)),
3960 (t2SXTAB rGPR:$Rn, rGPR:$Rm, 0)>,
3961 Requires<[HasT2ExtractPack, IsThumb2]>;
3962 def : T2Pat<(add rGPR:$Rn, (sext_inreg rGPR:$Rm, i16)),
3963 (t2SXTAH rGPR:$Rn, rGPR:$Rm, 0)>,
3964 Requires<[HasT2ExtractPack, IsThumb2]>;
3966 // Atomic load/store patterns
3967 def : T2Pat<(atomic_load_8 t2addrmode_imm12:$addr),
3968 (t2LDRBi12 t2addrmode_imm12:$addr)>;
3969 def : T2Pat<(atomic_load_8 t2addrmode_negimm8:$addr),
3970 (t2LDRBi8 t2addrmode_negimm8:$addr)>;
3971 def : T2Pat<(atomic_load_8 t2addrmode_so_reg:$addr),
3972 (t2LDRBs t2addrmode_so_reg:$addr)>;
3973 def : T2Pat<(atomic_load_16 t2addrmode_imm12:$addr),
3974 (t2LDRHi12 t2addrmode_imm12:$addr)>;
3975 def : T2Pat<(atomic_load_16 t2addrmode_negimm8:$addr),
3976 (t2LDRHi8 t2addrmode_negimm8:$addr)>;
3977 def : T2Pat<(atomic_load_16 t2addrmode_so_reg:$addr),
3978 (t2LDRHs t2addrmode_so_reg:$addr)>;
3979 def : T2Pat<(atomic_load_32 t2addrmode_imm12:$addr),
3980 (t2LDRi12 t2addrmode_imm12:$addr)>;
3981 def : T2Pat<(atomic_load_32 t2addrmode_negimm8:$addr),
3982 (t2LDRi8 t2addrmode_negimm8:$addr)>;
3983 def : T2Pat<(atomic_load_32 t2addrmode_so_reg:$addr),
3984 (t2LDRs t2addrmode_so_reg:$addr)>;
3985 def : T2Pat<(atomic_store_8 t2addrmode_imm12:$addr, GPR:$val),
3986 (t2STRBi12 GPR:$val, t2addrmode_imm12:$addr)>;
3987 def : T2Pat<(atomic_store_8 t2addrmode_negimm8:$addr, GPR:$val),
3988 (t2STRBi8 GPR:$val, t2addrmode_negimm8:$addr)>;
3989 def : T2Pat<(atomic_store_8 t2addrmode_so_reg:$addr, GPR:$val),
3990 (t2STRBs GPR:$val, t2addrmode_so_reg:$addr)>;
3991 def : T2Pat<(atomic_store_16 t2addrmode_imm12:$addr, GPR:$val),
3992 (t2STRHi12 GPR:$val, t2addrmode_imm12:$addr)>;
3993 def : T2Pat<(atomic_store_16 t2addrmode_negimm8:$addr, GPR:$val),
3994 (t2STRHi8 GPR:$val, t2addrmode_negimm8:$addr)>;
3995 def : T2Pat<(atomic_store_16 t2addrmode_so_reg:$addr, GPR:$val),
3996 (t2STRHs GPR:$val, t2addrmode_so_reg:$addr)>;
3997 def : T2Pat<(atomic_store_32 t2addrmode_imm12:$addr, GPR:$val),
3998 (t2STRi12 GPR:$val, t2addrmode_imm12:$addr)>;
3999 def : T2Pat<(atomic_store_32 t2addrmode_negimm8:$addr, GPR:$val),
4000 (t2STRi8 GPR:$val, t2addrmode_negimm8:$addr)>;
4001 def : T2Pat<(atomic_store_32 t2addrmode_so_reg:$addr, GPR:$val),
4002 (t2STRs GPR:$val, t2addrmode_so_reg:$addr)>;
4005 //===----------------------------------------------------------------------===//
4006 // Assembler aliases
4009 // Aliases for ADC without the ".w" optional width specifier.
4010 def : t2InstAlias<"adc${s}${p} $Rd, $Rn, $Rm",
4011 (t2ADCrr rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, pred:$p, cc_out:$s)>;
4012 def : t2InstAlias<"adc${s}${p} $Rd, $Rn, $ShiftedRm",
4013 (t2ADCrs rGPR:$Rd, rGPR:$Rn, t2_so_reg:$ShiftedRm,
4014 pred:$p, cc_out:$s)>;
4016 // Aliases for SBC without the ".w" optional width specifier.
4017 def : t2InstAlias<"sbc${s}${p} $Rd, $Rn, $Rm",
4018 (t2SBCrr rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, pred:$p, cc_out:$s)>;
4019 def : t2InstAlias<"sbc${s}${p} $Rd, $Rn, $ShiftedRm",
4020 (t2SBCrs rGPR:$Rd, rGPR:$Rn, t2_so_reg:$ShiftedRm,
4021 pred:$p, cc_out:$s)>;
4023 // Aliases for ADD without the ".w" optional width specifier.
4024 def : t2InstAlias<"add${s}${p} $Rd, $Rn, $imm",
4025 (t2ADDri rGPR:$Rd, GPRnopc:$Rn, t2_so_imm:$imm, pred:$p, cc_out:$s)>;
4026 def : t2InstAlias<"add${p} $Rd, $Rn, $imm",
4027 (t2ADDri12 GPRnopc:$Rd, GPR:$Rn, imm0_4095:$imm, pred:$p)>;
4028 def : t2InstAlias<"add${s}${p} $Rd, $Rn, $Rm",
4029 (t2ADDrr GPRnopc:$Rd, GPRnopc:$Rn, rGPR:$Rm, pred:$p, cc_out:$s)>;
4030 def : t2InstAlias<"add${s}${p} $Rd, $Rn, $ShiftedRm",
4031 (t2ADDrs GPRnopc:$Rd, GPRnopc:$Rn, t2_so_reg:$ShiftedRm,
4032 pred:$p, cc_out:$s)>;
4033 // ... and with the destination and source register combined.
4034 def : t2InstAlias<"add${s}${p} $Rdn, $imm",
4035 (t2ADDri GPRnopc:$Rdn, GPRnopc:$Rdn, t2_so_imm:$imm, pred:$p, cc_out:$s)>;
4036 def : t2InstAlias<"add${p} $Rdn, $imm",
4037 (t2ADDri12 GPRnopc:$Rdn, GPRnopc:$Rdn, imm0_4095:$imm, pred:$p)>;
4038 def : t2InstAlias<"add${s}${p} $Rdn, $Rm",
4039 (t2ADDrr GPRnopc:$Rdn, GPRnopc:$Rdn, rGPR:$Rm, pred:$p, cc_out:$s)>;
4040 def : t2InstAlias<"add${s}${p} $Rdn, $ShiftedRm",
4041 (t2ADDrs GPRnopc:$Rdn, GPRnopc:$Rdn, t2_so_reg:$ShiftedRm,
4042 pred:$p, cc_out:$s)>;
4044 // add w/ negative immediates is just a sub.
4045 def : t2InstAlias<"add${s}${p} $Rd, $Rn, $imm",
4046 (t2SUBri GPRnopc:$Rd, GPRnopc:$Rn, t2_so_imm_neg:$imm, pred:$p,
4048 def : t2InstAlias<"add${p} $Rd, $Rn, $imm",
4049 (t2SUBri12 GPRnopc:$Rd, GPR:$Rn, imm0_4095_neg:$imm, pred:$p)>;
4050 def : t2InstAlias<"add${s}${p} $Rdn, $imm",
4051 (t2SUBri GPRnopc:$Rdn, GPRnopc:$Rdn, t2_so_imm_neg:$imm, pred:$p,
4053 def : t2InstAlias<"add${p} $Rdn, $imm",
4054 (t2SUBri12 GPRnopc:$Rdn, GPRnopc:$Rdn, imm0_4095_neg:$imm, pred:$p)>;
4056 def : t2InstAlias<"add${s}${p}.w $Rd, $Rn, $imm",
4057 (t2SUBri GPRnopc:$Rd, GPRnopc:$Rn, t2_so_imm_neg:$imm, pred:$p,
4059 def : t2InstAlias<"addw${p} $Rd, $Rn, $imm",
4060 (t2SUBri12 GPRnopc:$Rd, GPR:$Rn, imm0_4095_neg:$imm, pred:$p)>;
4061 def : t2InstAlias<"add${s}${p}.w $Rdn, $imm",
4062 (t2SUBri GPRnopc:$Rdn, GPRnopc:$Rdn, t2_so_imm_neg:$imm, pred:$p,
4064 def : t2InstAlias<"addw${p} $Rdn, $imm",
4065 (t2SUBri12 GPRnopc:$Rdn, GPRnopc:$Rdn, imm0_4095_neg:$imm, pred:$p)>;
4068 // Aliases for SUB without the ".w" optional width specifier.
4069 def : t2InstAlias<"sub${s}${p} $Rd, $Rn, $imm",
4070 (t2SUBri GPRnopc:$Rd, GPRnopc:$Rn, t2_so_imm:$imm, pred:$p, cc_out:$s)>;
4071 def : t2InstAlias<"sub${p} $Rd, $Rn, $imm",
4072 (t2SUBri12 GPRnopc:$Rd, GPR:$Rn, imm0_4095:$imm, pred:$p)>;
4073 def : t2InstAlias<"sub${s}${p} $Rd, $Rn, $Rm",
4074 (t2SUBrr GPRnopc:$Rd, GPRnopc:$Rn, rGPR:$Rm, pred:$p, cc_out:$s)>;
4075 def : t2InstAlias<"sub${s}${p} $Rd, $Rn, $ShiftedRm",
4076 (t2SUBrs GPRnopc:$Rd, GPRnopc:$Rn, t2_so_reg:$ShiftedRm,
4077 pred:$p, cc_out:$s)>;
4078 // ... and with the destination and source register combined.
4079 def : t2InstAlias<"sub${s}${p} $Rdn, $imm",
4080 (t2SUBri GPRnopc:$Rdn, GPRnopc:$Rdn, t2_so_imm:$imm, pred:$p, cc_out:$s)>;
4081 def : t2InstAlias<"sub${p} $Rdn, $imm",
4082 (t2SUBri12 GPRnopc:$Rdn, GPRnopc:$Rdn, imm0_4095:$imm, pred:$p)>;
4083 def : t2InstAlias<"sub${s}${p}.w $Rdn, $Rm",
4084 (t2SUBrr GPRnopc:$Rdn, GPRnopc:$Rdn, rGPR:$Rm, pred:$p, cc_out:$s)>;
4085 def : t2InstAlias<"sub${s}${p} $Rdn, $Rm",
4086 (t2SUBrr GPRnopc:$Rdn, GPRnopc:$Rdn, rGPR:$Rm, pred:$p, cc_out:$s)>;
4087 def : t2InstAlias<"sub${s}${p} $Rdn, $ShiftedRm",
4088 (t2SUBrs GPRnopc:$Rdn, GPRnopc:$Rdn, t2_so_reg:$ShiftedRm,
4089 pred:$p, cc_out:$s)>;
4091 // Alias for compares without the ".w" optional width specifier.
4092 def : t2InstAlias<"cmn${p} $Rn, $Rm",
4093 (t2CMNzrr GPRnopc:$Rn, rGPR:$Rm, pred:$p)>;
4094 def : t2InstAlias<"teq${p} $Rn, $Rm",
4095 (t2TEQrr GPRnopc:$Rn, rGPR:$Rm, pred:$p)>;
4096 def : t2InstAlias<"tst${p} $Rn, $Rm",
4097 (t2TSTrr GPRnopc:$Rn, rGPR:$Rm, pred:$p)>;
4100 def : InstAlias<"dmb", (t2DMB 0xf)>, Requires<[IsThumb, HasDB]>;
4101 def : InstAlias<"dsb", (t2DSB 0xf)>, Requires<[IsThumb, HasDB]>;
4102 def : InstAlias<"isb", (t2ISB 0xf)>, Requires<[IsThumb, HasDB]>;
4104 // Alias for LDR, LDRB, LDRH, LDRSB, and LDRSH without the ".w" optional
4106 def : t2InstAlias<"ldr${p} $Rt, $addr",
4107 (t2LDRi12 GPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
4108 def : t2InstAlias<"ldrb${p} $Rt, $addr",
4109 (t2LDRBi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
4110 def : t2InstAlias<"ldrh${p} $Rt, $addr",
4111 (t2LDRHi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
4112 def : t2InstAlias<"ldrsb${p} $Rt, $addr",
4113 (t2LDRSBi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
4114 def : t2InstAlias<"ldrsh${p} $Rt, $addr",
4115 (t2LDRSHi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
4117 def : t2InstAlias<"ldr${p} $Rt, $addr",
4118 (t2LDRs GPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
4119 def : t2InstAlias<"ldrb${p} $Rt, $addr",
4120 (t2LDRBs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
4121 def : t2InstAlias<"ldrh${p} $Rt, $addr",
4122 (t2LDRHs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
4123 def : t2InstAlias<"ldrsb${p} $Rt, $addr",
4124 (t2LDRSBs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
4125 def : t2InstAlias<"ldrsh${p} $Rt, $addr",
4126 (t2LDRSHs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
4128 def : t2InstAlias<"ldr${p} $Rt, $addr",
4129 (t2LDRpci GPR:$Rt, t2ldrlabel:$addr, pred:$p)>;
4130 def : t2InstAlias<"ldrb${p} $Rt, $addr",
4131 (t2LDRBpci rGPR:$Rt, t2ldrlabel:$addr, pred:$p)>;
4132 def : t2InstAlias<"ldrh${p} $Rt, $addr",
4133 (t2LDRHpci rGPR:$Rt, t2ldrlabel:$addr, pred:$p)>;
4134 def : t2InstAlias<"ldrsb${p} $Rt, $addr",
4135 (t2LDRSBpci rGPR:$Rt, t2ldrlabel:$addr, pred:$p)>;
4136 def : t2InstAlias<"ldrsh${p} $Rt, $addr",
4137 (t2LDRSHpci rGPR:$Rt, t2ldrlabel:$addr, pred:$p)>;
4139 // Alias for MVN with(out) the ".w" optional width specifier.
4140 def : t2InstAlias<"mvn${s}${p}.w $Rd, $imm",
4141 (t2MVNi rGPR:$Rd, t2_so_imm:$imm, pred:$p, cc_out:$s)>;
4142 def : t2InstAlias<"mvn${s}${p} $Rd, $Rm",
4143 (t2MVNr rGPR:$Rd, rGPR:$Rm, pred:$p, cc_out:$s)>;
4144 def : t2InstAlias<"mvn${s}${p} $Rd, $ShiftedRm",
4145 (t2MVNs rGPR:$Rd, t2_so_reg:$ShiftedRm, pred:$p, cc_out:$s)>;
4147 // PKHBT/PKHTB with default shift amount. PKHTB is equivalent to PKHBT when the
4148 // shift amount is zero (i.e., unspecified).
4149 def : InstAlias<"pkhbt${p} $Rd, $Rn, $Rm",
4150 (t2PKHBT rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>,
4151 Requires<[HasT2ExtractPack, IsThumb2]>;
4152 def : InstAlias<"pkhtb${p} $Rd, $Rn, $Rm",
4153 (t2PKHBT rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>,
4154 Requires<[HasT2ExtractPack, IsThumb2]>;
4156 // PUSH/POP aliases for STM/LDM
4157 def : t2InstAlias<"push${p}.w $regs", (t2STMDB_UPD SP, pred:$p, reglist:$regs)>;
4158 def : t2InstAlias<"push${p} $regs", (t2STMDB_UPD SP, pred:$p, reglist:$regs)>;
4159 def : t2InstAlias<"pop${p}.w $regs", (t2LDMIA_UPD SP, pred:$p, reglist:$regs)>;
4160 def : t2InstAlias<"pop${p} $regs", (t2LDMIA_UPD SP, pred:$p, reglist:$regs)>;
4162 // STMIA/STMIA_UPD aliases w/o the optional .w suffix
4163 def : t2InstAlias<"stm${p} $Rn, $regs",
4164 (t2STMIA GPR:$Rn, pred:$p, reglist:$regs)>;
4165 def : t2InstAlias<"stm${p} $Rn!, $regs",
4166 (t2STMIA_UPD GPR:$Rn, pred:$p, reglist:$regs)>;
4168 // LDMIA/LDMIA_UPD aliases w/o the optional .w suffix
4169 def : t2InstAlias<"ldm${p} $Rn, $regs",
4170 (t2LDMIA GPR:$Rn, pred:$p, reglist:$regs)>;
4171 def : t2InstAlias<"ldm${p} $Rn!, $regs",
4172 (t2LDMIA_UPD GPR:$Rn, pred:$p, reglist:$regs)>;
4174 // STMDB/STMDB_UPD aliases w/ the optional .w suffix
4175 def : t2InstAlias<"stmdb${p}.w $Rn, $regs",
4176 (t2STMDB GPR:$Rn, pred:$p, reglist:$regs)>;
4177 def : t2InstAlias<"stmdb${p}.w $Rn!, $regs",
4178 (t2STMDB_UPD GPR:$Rn, pred:$p, reglist:$regs)>;
4180 // LDMDB/LDMDB_UPD aliases w/ the optional .w suffix
4181 def : t2InstAlias<"ldmdb${p}.w $Rn, $regs",
4182 (t2LDMDB GPR:$Rn, pred:$p, reglist:$regs)>;
4183 def : t2InstAlias<"ldmdb${p}.w $Rn!, $regs",
4184 (t2LDMDB_UPD GPR:$Rn, pred:$p, reglist:$regs)>;
4186 // Alias for REV/REV16/REVSH without the ".w" optional width specifier.
4187 def : t2InstAlias<"rev${p} $Rd, $Rm", (t2REV rGPR:$Rd, rGPR:$Rm, pred:$p)>;
4188 def : t2InstAlias<"rev16${p} $Rd, $Rm", (t2REV16 rGPR:$Rd, rGPR:$Rm, pred:$p)>;
4189 def : t2InstAlias<"revsh${p} $Rd, $Rm", (t2REVSH rGPR:$Rd, rGPR:$Rm, pred:$p)>;
4192 // Alias for RSB without the ".w" optional width specifier, and with optional
4193 // implied destination register.
4194 def : t2InstAlias<"rsb${s}${p} $Rd, $Rn, $imm",
4195 (t2RSBri rGPR:$Rd, rGPR:$Rn, t2_so_imm:$imm, pred:$p, cc_out:$s)>;
4196 def : t2InstAlias<"rsb${s}${p} $Rdn, $imm",
4197 (t2RSBri rGPR:$Rdn, rGPR:$Rdn, t2_so_imm:$imm, pred:$p, cc_out:$s)>;
4198 def : t2InstAlias<"rsb${s}${p} $Rdn, $Rm",
4199 (t2RSBrr rGPR:$Rdn, rGPR:$Rdn, rGPR:$Rm, pred:$p, cc_out:$s)>;
4200 def : t2InstAlias<"rsb${s}${p} $Rdn, $ShiftedRm",
4201 (t2RSBrs rGPR:$Rdn, rGPR:$Rdn, t2_so_reg:$ShiftedRm, pred:$p,
4204 // SSAT/USAT optional shift operand.
4205 def : t2InstAlias<"ssat${p} $Rd, $sat_imm, $Rn",
4206 (t2SSAT rGPR:$Rd, imm1_32:$sat_imm, rGPR:$Rn, 0, pred:$p)>;
4207 def : t2InstAlias<"usat${p} $Rd, $sat_imm, $Rn",
4208 (t2USAT rGPR:$Rd, imm0_31:$sat_imm, rGPR:$Rn, 0, pred:$p)>;
4210 // STM w/o the .w suffix.
4211 def : t2InstAlias<"stm${p} $Rn, $regs",
4212 (t2STMIA GPR:$Rn, pred:$p, reglist:$regs)>;
4214 // Alias for STR, STRB, and STRH without the ".w" optional
4216 def : t2InstAlias<"str${p} $Rt, $addr",
4217 (t2STRi12 GPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
4218 def : t2InstAlias<"strb${p} $Rt, $addr",
4219 (t2STRBi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
4220 def : t2InstAlias<"strh${p} $Rt, $addr",
4221 (t2STRHi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
4223 def : t2InstAlias<"str${p} $Rt, $addr",
4224 (t2STRs GPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
4225 def : t2InstAlias<"strb${p} $Rt, $addr",
4226 (t2STRBs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
4227 def : t2InstAlias<"strh${p} $Rt, $addr",
4228 (t2STRHs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
4230 // Extend instruction optional rotate operand.
4231 def : t2InstAlias<"sxtab${p} $Rd, $Rn, $Rm",
4232 (t2SXTAB rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>;
4233 def : t2InstAlias<"sxtah${p} $Rd, $Rn, $Rm",
4234 (t2SXTAH rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>;
4235 def : t2InstAlias<"sxtab16${p} $Rd, $Rn, $Rm",
4236 (t2SXTAB16 rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>;
4238 def : t2InstAlias<"sxtb${p} $Rd, $Rm",
4239 (t2SXTB rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
4240 def : t2InstAlias<"sxtb16${p} $Rd, $Rm",
4241 (t2SXTB16 rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
4242 def : t2InstAlias<"sxth${p} $Rd, $Rm",
4243 (t2SXTH rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
4244 def : t2InstAlias<"sxtb${p}.w $Rd, $Rm",
4245 (t2SXTB rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
4246 def : t2InstAlias<"sxth${p}.w $Rd, $Rm",
4247 (t2SXTH rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
4249 def : t2InstAlias<"uxtab${p} $Rd, $Rn, $Rm",
4250 (t2UXTAB rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>;
4251 def : t2InstAlias<"uxtah${p} $Rd, $Rn, $Rm",
4252 (t2UXTAH rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>;
4253 def : t2InstAlias<"uxtab16${p} $Rd, $Rn, $Rm",
4254 (t2UXTAB16 rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>;
4255 def : t2InstAlias<"uxtb${p} $Rd, $Rm",
4256 (t2UXTB rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
4257 def : t2InstAlias<"uxtb16${p} $Rd, $Rm",
4258 (t2UXTB16 rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
4259 def : t2InstAlias<"uxth${p} $Rd, $Rm",
4260 (t2UXTH rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
4262 def : t2InstAlias<"uxtb${p}.w $Rd, $Rm",
4263 (t2UXTB rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
4264 def : t2InstAlias<"uxth${p}.w $Rd, $Rm",
4265 (t2UXTH rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
4267 // Extend instruction w/o the ".w" optional width specifier.
4268 def : t2InstAlias<"uxtb${p} $Rd, $Rm$rot",
4269 (t2UXTB rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>;
4270 def : t2InstAlias<"uxtb16${p} $Rd, $Rm$rot",
4271 (t2UXTB16 rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>;
4272 def : t2InstAlias<"uxth${p} $Rd, $Rm$rot",
4273 (t2UXTH rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>;
4275 def : t2InstAlias<"sxtb${p} $Rd, $Rm$rot",
4276 (t2SXTB rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>;
4277 def : t2InstAlias<"sxtb16${p} $Rd, $Rm$rot",
4278 (t2SXTB16 rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>;
4279 def : t2InstAlias<"sxth${p} $Rd, $Rm$rot",
4280 (t2SXTH rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>;
4283 // "mov Rd, t2_so_imm_not" can be handled via "mvn" in assembly, just like
4285 def : t2InstAlias<"mov${p} $Rd, $imm",
4286 (t2MVNi rGPR:$Rd, t2_so_imm_not:$imm, pred:$p, zero_reg)>;
4287 def : t2InstAlias<"mvn${p} $Rd, $imm",
4288 (t2MOVi rGPR:$Rd, t2_so_imm_not:$imm, pred:$p, zero_reg)>;
4289 // Same for AND <--> BIC
4290 def : t2InstAlias<"bic${s}${p} $Rd, $Rn, $imm",
4291 (t2ANDri rGPR:$Rd, rGPR:$Rn, so_imm_not:$imm,
4292 pred:$p, cc_out:$s)>;
4293 def : t2InstAlias<"bic${s}${p} $Rdn, $imm",
4294 (t2ANDri rGPR:$Rdn, rGPR:$Rdn, so_imm_not:$imm,
4295 pred:$p, cc_out:$s)>;
4296 def : t2InstAlias<"and${s}${p} $Rd, $Rn, $imm",
4297 (t2BICri rGPR:$Rd, rGPR:$Rn, so_imm_not:$imm,
4298 pred:$p, cc_out:$s)>;
4299 def : t2InstAlias<"and${s}${p} $Rdn, $imm",
4300 (t2BICri rGPR:$Rdn, rGPR:$Rdn, so_imm_not:$imm,
4301 pred:$p, cc_out:$s)>;
4302 // Likewise, "add Rd, t2_so_imm_neg" -> sub
4303 def : t2InstAlias<"add${s}${p} $Rd, $Rn, $imm",
4304 (t2SUBri GPRnopc:$Rd, GPRnopc:$Rn, t2_so_imm_neg:$imm,
4305 pred:$p, cc_out:$s)>;
4306 def : t2InstAlias<"add${s}${p} $Rd, $imm",
4307 (t2SUBri GPRnopc:$Rd, GPRnopc:$Rd, t2_so_imm_neg:$imm,
4308 pred:$p, cc_out:$s)>;
4309 // Same for CMP <--> CMN via t2_so_imm_neg
4310 def : t2InstAlias<"cmp${p} $Rd, $imm",
4311 (t2CMNri rGPR:$Rd, t2_so_imm_neg:$imm, pred:$p)>;
4312 def : t2InstAlias<"cmn${p} $Rd, $imm",
4313 (t2CMPri rGPR:$Rd, t2_so_imm_neg:$imm, pred:$p)>;
4316 // Wide 'mul' encoding can be specified with only two operands.
4317 def : t2InstAlias<"mul${p} $Rn, $Rm",
4318 (t2MUL rGPR:$Rn, rGPR:$Rm, rGPR:$Rn, pred:$p)>;
4320 // "neg" is and alias for "rsb rd, rn, #0"
4321 def : t2InstAlias<"neg${s}${p} $Rd, $Rm",
4322 (t2RSBri rGPR:$Rd, rGPR:$Rm, 0, pred:$p, cc_out:$s)>;
4324 // MOV so_reg assembler pseudos. InstAlias isn't expressive enough for
4325 // these, unfortunately.
4326 def t2MOVsi: t2AsmPseudo<"mov${p} $Rd, $shift",
4327 (ins rGPR:$Rd, t2_so_reg:$shift, pred:$p)>;
4328 def t2MOVSsi: t2AsmPseudo<"movs${p} $Rd, $shift",
4329 (ins rGPR:$Rd, t2_so_reg:$shift, pred:$p)>;
4331 def t2MOVsr: t2AsmPseudo<"mov${p} $Rd, $shift",
4332 (ins rGPR:$Rd, so_reg_reg:$shift, pred:$p)>;
4333 def t2MOVSsr: t2AsmPseudo<"movs${p} $Rd, $shift",
4334 (ins rGPR:$Rd, so_reg_reg:$shift, pred:$p)>;
4336 // ADR w/o the .w suffix
4337 def : t2InstAlias<"adr${p} $Rd, $addr",
4338 (t2ADR rGPR:$Rd, t2adrlabel:$addr, pred:$p)>;
4340 // LDR(literal) w/ alternate [pc, #imm] syntax.
4341 def t2LDRpcrel : t2AsmPseudo<"ldr${p} $Rt, $addr",
4342 (ins GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>;
4343 def t2LDRBpcrel : t2AsmPseudo<"ldrb${p} $Rt, $addr",
4344 (ins GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>;
4345 def t2LDRHpcrel : t2AsmPseudo<"ldrh${p} $Rt, $addr",
4346 (ins GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>;
4347 def t2LDRSBpcrel : t2AsmPseudo<"ldrsb${p} $Rt, $addr",
4348 (ins GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>;
4349 def t2LDRSHpcrel : t2AsmPseudo<"ldrsh${p} $Rt, $addr",
4350 (ins GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>;
4351 // Version w/ the .w suffix.
4352 def : t2InstAlias<"ldr${p}.w $Rt, $addr",
4353 (t2LDRpcrel GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>;
4354 def : t2InstAlias<"ldrb${p}.w $Rt, $addr",
4355 (t2LDRBpcrel GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>;
4356 def : t2InstAlias<"ldrh${p}.w $Rt, $addr",
4357 (t2LDRHpcrel GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>;
4358 def : t2InstAlias<"ldrsb${p}.w $Rt, $addr",
4359 (t2LDRSBpcrel GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>;
4360 def : t2InstAlias<"ldrsh${p}.w $Rt, $addr",
4361 (t2LDRSHpcrel GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>;
4363 def : t2InstAlias<"add${p} $Rd, pc, $imm",
4364 (t2ADR rGPR:$Rd, imm0_4095:$imm, pred:$p)>;