1 //===- ARMInstrThumb2.td - Thumb2 support for ARM -------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Thumb2 instruction set.
12 //===----------------------------------------------------------------------===//
14 // IT block predicate field
15 def it_pred_asmoperand : AsmOperandClass {
16 let Name = "ITCondCode";
17 let ParserMethod = "parseITCondCode";
19 def it_pred : Operand<i32> {
20 let PrintMethod = "printMandatoryPredicateOperand";
21 let ParserMatchClass = it_pred_asmoperand;
24 // IT block condition mask
25 def it_mask_asmoperand : AsmOperandClass { let Name = "ITMask"; }
26 def it_mask : Operand<i32> {
27 let PrintMethod = "printThumbITMask";
28 let ParserMatchClass = it_mask_asmoperand;
31 // Shifted operands. No register controlled shifts for Thumb2.
32 // Note: We do not support rrx shifted operands yet.
33 def t2_so_reg : Operand<i32>, // reg imm
34 ComplexPattern<i32, 2, "SelectT2ShifterOperandReg",
36 let EncoderMethod = "getT2SORegOpValue";
37 let PrintMethod = "printT2SOOperand";
38 let DecoderMethod = "DecodeSORegImmOperand";
39 let ParserMatchClass = ShiftedImmAsmOperand;
40 let MIOperandInfo = (ops rGPR, i32imm);
43 // t2_so_imm_not_XFORM - Return the complement of a t2_so_imm value
44 def t2_so_imm_not_XFORM : SDNodeXForm<imm, [{
45 return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), MVT::i32);
48 // t2_so_imm_neg_XFORM - Return the negation of a t2_so_imm value
49 def t2_so_imm_neg_XFORM : SDNodeXForm<imm, [{
50 return CurDAG->getTargetConstant(-((int)N->getZExtValue()), MVT::i32);
53 // t2_so_imm - Match a 32-bit immediate operand, which is an
54 // 8-bit immediate rotated by an arbitrary number of bits, or an 8-bit
55 // immediate splatted into multiple bytes of the word.
56 def t2_so_imm_asmoperand : AsmOperandClass { let Name = "T2SOImm"; }
57 def t2_so_imm : Operand<i32>, ImmLeaf<i32, [{
58 return ARM_AM::getT2SOImmVal(Imm) != -1;
60 let ParserMatchClass = t2_so_imm_asmoperand;
61 let EncoderMethod = "getT2SOImmOpValue";
62 let DecoderMethod = "DecodeT2SOImm";
65 // t2_so_imm_not - Match an immediate that is a complement
67 def t2_so_imm_not : Operand<i32>,
69 return ARM_AM::getT2SOImmVal(~((uint32_t)N->getZExtValue())) != -1;
70 }], t2_so_imm_not_XFORM>;
72 // t2_so_imm_neg - Match an immediate that is a negation of a t2_so_imm.
73 def t2_so_imm_neg : Operand<i32>,
75 return ARM_AM::getT2SOImmVal(-((uint32_t)N->getZExtValue())) != -1;
76 }], t2_so_imm_neg_XFORM>;
78 /// imm0_4095 predicate - True if the 32-bit immediate is in the range [0.4095].
79 def imm0_4095 : Operand<i32>,
81 return Imm >= 0 && Imm < 4096;
84 def imm0_4095_neg : PatLeaf<(i32 imm), [{
85 return (uint32_t)(-N->getZExtValue()) < 4096;
88 def imm0_255_neg : PatLeaf<(i32 imm), [{
89 return (uint32_t)(-N->getZExtValue()) < 255;
92 def imm0_255_not : PatLeaf<(i32 imm), [{
93 return (uint32_t)(~N->getZExtValue()) < 255;
96 def lo5AllOne : PatLeaf<(i32 imm), [{
97 // Returns true if all low 5-bits are 1.
98 return (((uint32_t)N->getZExtValue()) & 0x1FUL) == 0x1FUL;
101 // Define Thumb2 specific addressing modes.
103 // t2addrmode_imm12 := reg + imm12
104 def t2addrmode_imm12_asmoperand : AsmOperandClass {let Name="MemUImm12Offset";}
105 def t2addrmode_imm12 : Operand<i32>,
106 ComplexPattern<i32, 2, "SelectT2AddrModeImm12", []> {
107 let PrintMethod = "printAddrModeImm12Operand";
108 let EncoderMethod = "getAddrModeImm12OpValue";
109 let DecoderMethod = "DecodeT2AddrModeImm12";
110 let ParserMatchClass = t2addrmode_imm12_asmoperand;
111 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
114 // t2ldrlabel := imm12
115 def t2ldrlabel : Operand<i32> {
116 let EncoderMethod = "getAddrModeImm12OpValue";
117 let PrintMethod = "printT2LdrLabelOperand";
121 // ADR instruction labels.
122 def t2adrlabel : Operand<i32> {
123 let EncoderMethod = "getT2AdrLabelOpValue";
124 let PrintMethod = "printT2AdrLabelOperand";
128 // t2addrmode_posimm8 := reg + imm8
129 def MemPosImm8OffsetAsmOperand : AsmOperandClass {let Name="MemPosImm8Offset";}
130 def t2addrmode_posimm8 : Operand<i32> {
131 let PrintMethod = "printT2AddrModeImm8Operand";
132 let EncoderMethod = "getT2AddrModeImm8OpValue";
133 let DecoderMethod = "DecodeT2AddrModeImm8";
134 let ParserMatchClass = MemPosImm8OffsetAsmOperand;
135 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
138 // t2addrmode_negimm8 := reg - imm8
139 def MemNegImm8OffsetAsmOperand : AsmOperandClass {let Name="MemNegImm8Offset";}
140 def t2addrmode_negimm8 : Operand<i32>,
141 ComplexPattern<i32, 2, "SelectT2AddrModeImm8", []> {
142 let PrintMethod = "printT2AddrModeImm8Operand";
143 let EncoderMethod = "getT2AddrModeImm8OpValue";
144 let DecoderMethod = "DecodeT2AddrModeImm8";
145 let ParserMatchClass = MemNegImm8OffsetAsmOperand;
146 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
149 // t2addrmode_imm8 := reg +/- imm8
150 def MemImm8OffsetAsmOperand : AsmOperandClass { let Name = "MemImm8Offset"; }
151 def t2addrmode_imm8 : Operand<i32>,
152 ComplexPattern<i32, 2, "SelectT2AddrModeImm8", []> {
153 let PrintMethod = "printT2AddrModeImm8Operand";
154 let EncoderMethod = "getT2AddrModeImm8OpValue";
155 let DecoderMethod = "DecodeT2AddrModeImm8";
156 let ParserMatchClass = MemImm8OffsetAsmOperand;
157 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
160 def t2am_imm8_offset : Operand<i32>,
161 ComplexPattern<i32, 1, "SelectT2AddrModeImm8Offset",
162 [], [SDNPWantRoot]> {
163 let PrintMethod = "printT2AddrModeImm8OffsetOperand";
164 let EncoderMethod = "getT2AddrModeImm8OffsetOpValue";
165 let DecoderMethod = "DecodeT2Imm8";
168 // t2addrmode_imm8s4 := reg +/- (imm8 << 2)
169 def MemImm8s4OffsetAsmOperand : AsmOperandClass {let Name = "MemImm8s4Offset";}
170 def t2addrmode_imm8s4 : Operand<i32> {
171 let PrintMethod = "printT2AddrModeImm8s4Operand";
172 let EncoderMethod = "getT2AddrModeImm8s4OpValue";
173 let DecoderMethod = "DecodeT2AddrModeImm8s4";
174 let ParserMatchClass = MemImm8s4OffsetAsmOperand;
175 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
178 def t2am_imm8s4_offset_asmoperand : AsmOperandClass { let Name = "Imm8s4"; }
179 def t2am_imm8s4_offset : Operand<i32> {
180 let PrintMethod = "printT2AddrModeImm8s4OffsetOperand";
181 let EncoderMethod = "getT2Imm8s4OpValue";
182 let DecoderMethod = "DecodeT2Imm8S4";
185 // t2addrmode_imm0_1020s4 := reg + (imm8 << 2)
186 def MemImm0_1020s4OffsetAsmOperand : AsmOperandClass {
187 let Name = "MemImm0_1020s4Offset";
189 def t2addrmode_imm0_1020s4 : Operand<i32> {
190 let PrintMethod = "printT2AddrModeImm0_1020s4Operand";
191 let EncoderMethod = "getT2AddrModeImm0_1020s4OpValue";
192 let DecoderMethod = "DecodeT2AddrModeImm0_1020s4";
193 let ParserMatchClass = MemImm0_1020s4OffsetAsmOperand;
194 let MIOperandInfo = (ops GPRnopc:$base, i32imm:$offsimm);
197 // t2addrmode_so_reg := reg + (reg << imm2)
198 def t2addrmode_so_reg_asmoperand : AsmOperandClass {let Name="T2MemRegOffset";}
199 def t2addrmode_so_reg : Operand<i32>,
200 ComplexPattern<i32, 3, "SelectT2AddrModeSoReg", []> {
201 let PrintMethod = "printT2AddrModeSoRegOperand";
202 let EncoderMethod = "getT2AddrModeSORegOpValue";
203 let DecoderMethod = "DecodeT2AddrModeSOReg";
204 let ParserMatchClass = t2addrmode_so_reg_asmoperand;
205 let MIOperandInfo = (ops GPR:$base, rGPR:$offsreg, i32imm:$offsimm);
208 // Addresses for the TBB/TBH instructions.
209 def addrmode_tbb_asmoperand : AsmOperandClass { let Name = "MemTBB"; }
210 def addrmode_tbb : Operand<i32> {
211 let PrintMethod = "printAddrModeTBB";
212 let ParserMatchClass = addrmode_tbb_asmoperand;
213 let MIOperandInfo = (ops GPR:$Rn, rGPR:$Rm);
215 def addrmode_tbh_asmoperand : AsmOperandClass { let Name = "MemTBH"; }
216 def addrmode_tbh : Operand<i32> {
217 let PrintMethod = "printAddrModeTBH";
218 let ParserMatchClass = addrmode_tbh_asmoperand;
219 let MIOperandInfo = (ops GPR:$Rn, rGPR:$Rm);
222 //===----------------------------------------------------------------------===//
223 // Multiclass helpers...
227 class T2OneRegImm<dag oops, dag iops, InstrItinClass itin,
228 string opc, string asm, list<dag> pattern>
229 : T2I<oops, iops, itin, opc, asm, pattern> {
234 let Inst{26} = imm{11};
235 let Inst{14-12} = imm{10-8};
236 let Inst{7-0} = imm{7-0};
240 class T2sOneRegImm<dag oops, dag iops, InstrItinClass itin,
241 string opc, string asm, list<dag> pattern>
242 : T2sI<oops, iops, itin, opc, asm, pattern> {
248 let Inst{26} = imm{11};
249 let Inst{14-12} = imm{10-8};
250 let Inst{7-0} = imm{7-0};
253 class T2OneRegCmpImm<dag oops, dag iops, InstrItinClass itin,
254 string opc, string asm, list<dag> pattern>
255 : T2I<oops, iops, itin, opc, asm, pattern> {
259 let Inst{19-16} = Rn;
260 let Inst{26} = imm{11};
261 let Inst{14-12} = imm{10-8};
262 let Inst{7-0} = imm{7-0};
266 class T2OneRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
267 string opc, string asm, list<dag> pattern>
268 : T2I<oops, iops, itin, opc, asm, pattern> {
273 let Inst{3-0} = ShiftedRm{3-0};
274 let Inst{5-4} = ShiftedRm{6-5};
275 let Inst{14-12} = ShiftedRm{11-9};
276 let Inst{7-6} = ShiftedRm{8-7};
279 class T2sOneRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
280 string opc, string asm, list<dag> pattern>
281 : T2sI<oops, iops, itin, opc, asm, pattern> {
286 let Inst{3-0} = ShiftedRm{3-0};
287 let Inst{5-4} = ShiftedRm{6-5};
288 let Inst{14-12} = ShiftedRm{11-9};
289 let Inst{7-6} = ShiftedRm{8-7};
292 class T2OneRegCmpShiftedReg<dag oops, dag iops, InstrItinClass itin,
293 string opc, string asm, list<dag> pattern>
294 : T2I<oops, iops, itin, opc, asm, pattern> {
298 let Inst{19-16} = Rn;
299 let Inst{3-0} = ShiftedRm{3-0};
300 let Inst{5-4} = ShiftedRm{6-5};
301 let Inst{14-12} = ShiftedRm{11-9};
302 let Inst{7-6} = ShiftedRm{8-7};
305 class T2TwoReg<dag oops, dag iops, InstrItinClass itin,
306 string opc, string asm, list<dag> pattern>
307 : T2I<oops, iops, itin, opc, asm, pattern> {
315 class T2sTwoReg<dag oops, dag iops, InstrItinClass itin,
316 string opc, string asm, list<dag> pattern>
317 : T2sI<oops, iops, itin, opc, asm, pattern> {
325 class T2TwoRegCmp<dag oops, dag iops, InstrItinClass itin,
326 string opc, string asm, list<dag> pattern>
327 : T2I<oops, iops, itin, opc, asm, pattern> {
331 let Inst{19-16} = Rn;
336 class T2TwoRegImm<dag oops, dag iops, InstrItinClass itin,
337 string opc, string asm, list<dag> pattern>
338 : T2I<oops, iops, itin, opc, asm, pattern> {
344 let Inst{19-16} = Rn;
345 let Inst{26} = imm{11};
346 let Inst{14-12} = imm{10-8};
347 let Inst{7-0} = imm{7-0};
350 class T2sTwoRegImm<dag oops, dag iops, InstrItinClass itin,
351 string opc, string asm, list<dag> pattern>
352 : T2sI<oops, iops, itin, opc, asm, pattern> {
358 let Inst{19-16} = Rn;
359 let Inst{26} = imm{11};
360 let Inst{14-12} = imm{10-8};
361 let Inst{7-0} = imm{7-0};
364 class T2TwoRegShiftImm<dag oops, dag iops, InstrItinClass itin,
365 string opc, string asm, list<dag> pattern>
366 : T2I<oops, iops, itin, opc, asm, pattern> {
373 let Inst{14-12} = imm{4-2};
374 let Inst{7-6} = imm{1-0};
377 class T2sTwoRegShiftImm<dag oops, dag iops, InstrItinClass itin,
378 string opc, string asm, list<dag> pattern>
379 : T2sI<oops, iops, itin, opc, asm, pattern> {
386 let Inst{14-12} = imm{4-2};
387 let Inst{7-6} = imm{1-0};
390 class T2ThreeReg<dag oops, dag iops, InstrItinClass itin,
391 string opc, string asm, list<dag> pattern>
392 : T2I<oops, iops, itin, opc, asm, pattern> {
398 let Inst{19-16} = Rn;
402 class T2sThreeReg<dag oops, dag iops, InstrItinClass itin,
403 string opc, string asm, list<dag> pattern>
404 : T2sI<oops, iops, itin, opc, asm, pattern> {
410 let Inst{19-16} = Rn;
414 class T2TwoRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
415 string opc, string asm, list<dag> pattern>
416 : T2I<oops, iops, itin, opc, asm, pattern> {
422 let Inst{19-16} = Rn;
423 let Inst{3-0} = ShiftedRm{3-0};
424 let Inst{5-4} = ShiftedRm{6-5};
425 let Inst{14-12} = ShiftedRm{11-9};
426 let Inst{7-6} = ShiftedRm{8-7};
429 class T2sTwoRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
430 string opc, string asm, list<dag> pattern>
431 : T2sI<oops, iops, itin, opc, asm, pattern> {
437 let Inst{19-16} = Rn;
438 let Inst{3-0} = ShiftedRm{3-0};
439 let Inst{5-4} = ShiftedRm{6-5};
440 let Inst{14-12} = ShiftedRm{11-9};
441 let Inst{7-6} = ShiftedRm{8-7};
444 class T2FourReg<dag oops, dag iops, InstrItinClass itin,
445 string opc, string asm, list<dag> pattern>
446 : T2I<oops, iops, itin, opc, asm, pattern> {
452 let Inst{19-16} = Rn;
453 let Inst{15-12} = Ra;
458 class T2MulLong<bits<3> opc22_20, bits<4> opc7_4,
459 dag oops, dag iops, InstrItinClass itin,
460 string opc, string asm, list<dag> pattern>
461 : T2I<oops, iops, itin, opc, asm, pattern> {
467 let Inst{31-23} = 0b111110111;
468 let Inst{22-20} = opc22_20;
469 let Inst{19-16} = Rn;
470 let Inst{15-12} = RdLo;
471 let Inst{11-8} = RdHi;
472 let Inst{7-4} = opc7_4;
477 /// T2I_bin_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a
478 /// binary operation that produces a value. These are predicable and can be
479 /// changed to modify CPSR.
480 multiclass T2I_bin_irs<bits<4> opcod, string opc,
481 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
482 PatFrag opnode, string baseOpc, bit Commutable = 0,
485 def ri : T2sTwoRegImm<
486 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm), iii,
487 opc, "\t$Rd, $Rn, $imm",
488 [(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_imm:$imm))]> {
489 let Inst{31-27} = 0b11110;
491 let Inst{24-21} = opcod;
495 def rr : T2sThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), iir,
496 opc, !strconcat(wide, "\t$Rd, $Rn, $Rm"),
497 [(set rGPR:$Rd, (opnode rGPR:$Rn, rGPR:$Rm))]> {
498 let isCommutable = Commutable;
499 let Inst{31-27} = 0b11101;
500 let Inst{26-25} = 0b01;
501 let Inst{24-21} = opcod;
502 let Inst{14-12} = 0b000; // imm3
503 let Inst{7-6} = 0b00; // imm2
504 let Inst{5-4} = 0b00; // type
507 def rs : T2sTwoRegShiftedReg<
508 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm), iis,
509 opc, !strconcat(wide, "\t$Rd, $Rn, $ShiftedRm"),
510 [(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_reg:$ShiftedRm))]> {
511 let Inst{31-27} = 0b11101;
512 let Inst{26-25} = 0b01;
513 let Inst{24-21} = opcod;
515 // Assembly aliases for optional destination operand when it's the same
516 // as the source operand.
517 def : t2InstAlias<!strconcat(opc, "${s}${p} $Rdn, $imm"),
518 (!cast<Instruction>(!strconcat(baseOpc, "ri")) rGPR:$Rdn, rGPR:$Rdn,
519 t2_so_imm:$imm, pred:$p,
521 def : t2InstAlias<!strconcat(opc, "${s}${p}", wide, " $Rdn, $Rm"),
522 (!cast<Instruction>(!strconcat(baseOpc, "rr")) rGPR:$Rdn, rGPR:$Rdn,
525 def : t2InstAlias<!strconcat(opc, "${s}${p}", wide, " $Rdn, $shift"),
526 (!cast<Instruction>(!strconcat(baseOpc, "rs")) rGPR:$Rdn, rGPR:$Rdn,
527 t2_so_reg:$shift, pred:$p,
531 /// T2I_bin_w_irs - Same as T2I_bin_irs except these operations need
532 // the ".w" suffix to indicate that they are wide.
533 multiclass T2I_bin_w_irs<bits<4> opcod, string opc,
534 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
535 PatFrag opnode, string baseOpc, bit Commutable = 0> :
536 T2I_bin_irs<opcod, opc, iii, iir, iis, opnode, baseOpc, Commutable, ".w"> {
537 // Assembler aliases w/o the ".w" suffix.
538 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rd, $Rn, $Rm"),
539 (!cast<Instruction>(!strconcat(baseOpc, "rr")) rGPR:$Rd, rGPR:$Rn,
542 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rd, $Rn, $shift"),
543 (!cast<Instruction>(!strconcat(baseOpc, "rs")) rGPR:$Rd, rGPR:$Rn,
544 t2_so_reg:$shift, pred:$p,
547 // and with the optional destination operand, too.
548 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rdn, $Rm"),
549 (!cast<Instruction>(!strconcat(baseOpc, "rr")) rGPR:$Rdn, rGPR:$Rdn,
552 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rdn, $shift"),
553 (!cast<Instruction>(!strconcat(baseOpc, "rs")) rGPR:$Rdn, rGPR:$Rdn,
554 t2_so_reg:$shift, pred:$p,
558 /// T2I_rbin_is - Same as T2I_bin_irs except the order of operands are
559 /// reversed. The 'rr' form is only defined for the disassembler; for codegen
560 /// it is equivalent to the T2I_bin_irs counterpart.
561 multiclass T2I_rbin_irs<bits<4> opcod, string opc, PatFrag opnode> {
563 def ri : T2sTwoRegImm<
564 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm), IIC_iALUi,
565 opc, ".w\t$Rd, $Rn, $imm",
566 [(set rGPR:$Rd, (opnode t2_so_imm:$imm, rGPR:$Rn))]> {
567 let Inst{31-27} = 0b11110;
569 let Inst{24-21} = opcod;
573 def rr : T2sThreeReg<
574 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUr,
575 opc, "\t$Rd, $Rn, $Rm",
576 [/* For disassembly only; pattern left blank */]> {
577 let Inst{31-27} = 0b11101;
578 let Inst{26-25} = 0b01;
579 let Inst{24-21} = opcod;
580 let Inst{14-12} = 0b000; // imm3
581 let Inst{7-6} = 0b00; // imm2
582 let Inst{5-4} = 0b00; // type
585 def rs : T2sTwoRegShiftedReg<
586 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm),
587 IIC_iALUsir, opc, "\t$Rd, $Rn, $ShiftedRm",
588 [(set rGPR:$Rd, (opnode t2_so_reg:$ShiftedRm, rGPR:$Rn))]> {
589 let Inst{31-27} = 0b11101;
590 let Inst{26-25} = 0b01;
591 let Inst{24-21} = opcod;
595 /// T2I_bin_s_irs - Similar to T2I_bin_irs except it sets the 's' bit so the
596 /// instruction modifies the CPSR register.
598 /// These opcodes will be converted to the real non-S opcodes by
599 /// AdjustInstrPostInstrSelection after giving then an optional CPSR operand.
600 let hasPostISelHook = 1, isCodeGenOnly = 1, isPseudo = 1, Defs = [CPSR] in {
601 multiclass T2I_bin_s_irs<bits<4> opcod, string opc,
602 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
603 PatFrag opnode, bit Commutable = 0> {
605 def ri : T2sTwoRegImm<
606 (outs rGPR:$Rd), (ins GPR:$Rn, t2_so_imm:$imm), iii,
607 opc, ".w\t$Rd, $Rn, $imm",
608 [(set rGPR:$Rd, CPSR, (opnode GPR:$Rn, t2_so_imm:$imm))]>;
610 def rr : T2sThreeReg<
611 (outs rGPR:$Rd), (ins GPR:$Rn, rGPR:$Rm), iir,
612 opc, ".w\t$Rd, $Rn, $Rm",
613 [(set rGPR:$Rd, CPSR, (opnode GPR:$Rn, rGPR:$Rm))]>;
615 def rs : T2sTwoRegShiftedReg<
616 (outs rGPR:$Rd), (ins GPR:$Rn, t2_so_reg:$ShiftedRm), iis,
617 opc, ".w\t$Rd, $Rn, $ShiftedRm",
618 [(set rGPR:$Rd, CPSR, (opnode GPR:$Rn, t2_so_reg:$ShiftedRm))]>;
622 /// T2I_bin_ii12rs - Defines a set of (op reg, {so_imm|imm0_4095|r|so_reg})
623 /// patterns for a binary operation that produces a value.
624 multiclass T2I_bin_ii12rs<bits<3> op23_21, string opc, PatFrag opnode,
625 bit Commutable = 0> {
627 // The register-immediate version is re-materializable. This is useful
628 // in particular for taking the address of a local.
629 let isReMaterializable = 1 in {
630 def ri : T2sTwoRegImm<
631 (outs rGPR:$Rd), (ins GPRnopc:$Rn, t2_so_imm:$imm), IIC_iALUi,
632 opc, ".w\t$Rd, $Rn, $imm",
633 [(set rGPR:$Rd, (opnode GPRnopc:$Rn, t2_so_imm:$imm))]> {
634 let Inst{31-27} = 0b11110;
637 let Inst{23-21} = op23_21;
643 (outs rGPR:$Rd), (ins GPR:$Rn, imm0_4095:$imm), IIC_iALUi,
644 !strconcat(opc, "w"), "\t$Rd, $Rn, $imm",
645 [(set rGPR:$Rd, (opnode GPR:$Rn, imm0_4095:$imm))]> {
649 let Inst{31-27} = 0b11110;
650 let Inst{26} = imm{11};
651 let Inst{25-24} = 0b10;
652 let Inst{23-21} = op23_21;
653 let Inst{20} = 0; // The S bit.
654 let Inst{19-16} = Rn;
656 let Inst{14-12} = imm{10-8};
658 let Inst{7-0} = imm{7-0};
661 def rr : T2sThreeReg<(outs rGPR:$Rd), (ins GPRnopc:$Rn, rGPR:$Rm), IIC_iALUr,
662 opc, ".w\t$Rd, $Rn, $Rm",
663 [(set rGPR:$Rd, (opnode GPRnopc:$Rn, rGPR:$Rm))]> {
664 let isCommutable = Commutable;
665 let Inst{31-27} = 0b11101;
666 let Inst{26-25} = 0b01;
668 let Inst{23-21} = op23_21;
669 let Inst{14-12} = 0b000; // imm3
670 let Inst{7-6} = 0b00; // imm2
671 let Inst{5-4} = 0b00; // type
674 def rs : T2sTwoRegShiftedReg<
675 (outs rGPR:$Rd), (ins GPRnopc:$Rn, t2_so_reg:$ShiftedRm),
676 IIC_iALUsi, opc, ".w\t$Rd, $Rn, $ShiftedRm",
677 [(set rGPR:$Rd, (opnode GPRnopc:$Rn, t2_so_reg:$ShiftedRm))]> {
678 let Inst{31-27} = 0b11101;
679 let Inst{26-25} = 0b01;
681 let Inst{23-21} = op23_21;
685 /// T2I_adde_sube_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns
686 /// for a binary operation that produces a value and use the carry
687 /// bit. It's not predicable.
688 let Defs = [CPSR], Uses = [CPSR] in {
689 multiclass T2I_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
690 bit Commutable = 0> {
692 def ri : T2sTwoRegImm<(outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm),
693 IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
694 [(set rGPR:$Rd, CPSR, (opnode rGPR:$Rn, t2_so_imm:$imm, CPSR))]>,
695 Requires<[IsThumb2]> {
696 let Inst{31-27} = 0b11110;
698 let Inst{24-21} = opcod;
702 def rr : T2sThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUr,
703 opc, ".w\t$Rd, $Rn, $Rm",
704 [(set rGPR:$Rd, CPSR, (opnode rGPR:$Rn, rGPR:$Rm, CPSR))]>,
705 Requires<[IsThumb2]> {
706 let isCommutable = Commutable;
707 let Inst{31-27} = 0b11101;
708 let Inst{26-25} = 0b01;
709 let Inst{24-21} = opcod;
710 let Inst{14-12} = 0b000; // imm3
711 let Inst{7-6} = 0b00; // imm2
712 let Inst{5-4} = 0b00; // type
715 def rs : T2sTwoRegShiftedReg<
716 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm),
717 IIC_iALUsi, opc, ".w\t$Rd, $Rn, $ShiftedRm",
718 [(set rGPR:$Rd, CPSR, (opnode rGPR:$Rn, t2_so_reg:$ShiftedRm, CPSR))]>,
719 Requires<[IsThumb2]> {
720 let Inst{31-27} = 0b11101;
721 let Inst{26-25} = 0b01;
722 let Inst{24-21} = opcod;
727 /// T2I_rbin_s_is - Same as T2I_rbin_irs except sets 's' bit and the register
728 /// version is not needed since this is only for codegen.
730 /// These opcodes will be converted to the real non-S opcodes by
731 /// AdjustInstrPostInstrSelection after giving then an optional CPSR operand.
732 let hasPostISelHook = 1, isCodeGenOnly = 1, isPseudo = 1, Defs = [CPSR] in {
733 multiclass T2I_rbin_s_is<bits<4> opcod, string opc, PatFrag opnode> {
735 def ri : T2sTwoRegImm<
736 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm), IIC_iALUi,
737 opc, ".w\t$Rd, $Rn, $imm",
738 [(set rGPR:$Rd, CPSR, (opnode t2_so_imm:$imm, rGPR:$Rn))]>;
740 def rs : T2sTwoRegShiftedReg<
741 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm),
742 IIC_iALUsi, opc, "\t$Rd, $Rn, $ShiftedRm",
743 [(set rGPR:$Rd, CPSR, (opnode t2_so_reg:$ShiftedRm, rGPR:$Rn))]>;
747 /// T2I_sh_ir - Defines a set of (op reg, {so_imm|r}) patterns for a shift /
748 // rotate operation that produces a value.
749 multiclass T2I_sh_ir<bits<2> opcod, string opc, Operand ty, PatFrag opnode,
752 def ri : T2sTwoRegShiftImm<
753 (outs rGPR:$Rd), (ins rGPR:$Rm, ty:$imm), IIC_iMOVsi,
754 opc, ".w\t$Rd, $Rm, $imm",
755 [(set rGPR:$Rd, (opnode rGPR:$Rm, (i32 ty:$imm)))]> {
756 let Inst{31-27} = 0b11101;
757 let Inst{26-21} = 0b010010;
758 let Inst{19-16} = 0b1111; // Rn
759 let Inst{5-4} = opcod;
762 def rr : T2sThreeReg<
763 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMOVsr,
764 opc, ".w\t$Rd, $Rn, $Rm",
765 [(set rGPR:$Rd, (opnode rGPR:$Rn, rGPR:$Rm))]> {
766 let Inst{31-27} = 0b11111;
767 let Inst{26-23} = 0b0100;
768 let Inst{22-21} = opcod;
769 let Inst{15-12} = 0b1111;
770 let Inst{7-4} = 0b0000;
773 // Optional destination register
774 def : t2InstAlias<!strconcat(opc, "${s}${p}", ".w $Rdn, $imm"),
775 (!cast<Instruction>(!strconcat(baseOpc, "ri")) rGPR:$Rdn, rGPR:$Rdn,
778 def : t2InstAlias<!strconcat(opc, "${s}${p}", ".w $Rdn, $Rm"),
779 (!cast<Instruction>(!strconcat(baseOpc, "rr")) rGPR:$Rdn, rGPR:$Rdn,
783 // Assembler aliases w/o the ".w" suffix.
784 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rd, $Rn, $imm"),
785 (!cast<Instruction>(!strconcat(baseOpc, "ri")) rGPR:$Rd, rGPR:$Rn,
788 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rd, $Rn, $Rm"),
789 (!cast<Instruction>(!strconcat(baseOpc, "rr")) rGPR:$Rd, rGPR:$Rn,
793 // and with the optional destination operand, too.
794 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rdn, $imm"),
795 (!cast<Instruction>(!strconcat(baseOpc, "ri")) rGPR:$Rdn, rGPR:$Rdn,
798 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rdn, $Rm"),
799 (!cast<Instruction>(!strconcat(baseOpc, "rr")) rGPR:$Rdn, rGPR:$Rdn,
804 /// T2I_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
805 /// patterns. Similar to T2I_bin_irs except the instruction does not produce
806 /// a explicit result, only implicitly set CPSR.
807 multiclass T2I_cmp_irs<bits<4> opcod, string opc,
808 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
809 PatFrag opnode, string baseOpc> {
810 let isCompare = 1, Defs = [CPSR] in {
812 def ri : T2OneRegCmpImm<
813 (outs), (ins GPRnopc:$Rn, t2_so_imm:$imm), iii,
814 opc, ".w\t$Rn, $imm",
815 [(opnode GPRnopc:$Rn, t2_so_imm:$imm)]> {
816 let Inst{31-27} = 0b11110;
818 let Inst{24-21} = opcod;
819 let Inst{20} = 1; // The S bit.
821 let Inst{11-8} = 0b1111; // Rd
824 def rr : T2TwoRegCmp<
825 (outs), (ins GPRnopc:$Rn, rGPR:$Rm), iir,
827 [(opnode GPRnopc:$Rn, rGPR:$Rm)]> {
828 let Inst{31-27} = 0b11101;
829 let Inst{26-25} = 0b01;
830 let Inst{24-21} = opcod;
831 let Inst{20} = 1; // The S bit.
832 let Inst{14-12} = 0b000; // imm3
833 let Inst{11-8} = 0b1111; // Rd
834 let Inst{7-6} = 0b00; // imm2
835 let Inst{5-4} = 0b00; // type
838 def rs : T2OneRegCmpShiftedReg<
839 (outs), (ins GPRnopc:$Rn, t2_so_reg:$ShiftedRm), iis,
840 opc, ".w\t$Rn, $ShiftedRm",
841 [(opnode GPRnopc:$Rn, t2_so_reg:$ShiftedRm)]> {
842 let Inst{31-27} = 0b11101;
843 let Inst{26-25} = 0b01;
844 let Inst{24-21} = opcod;
845 let Inst{20} = 1; // The S bit.
846 let Inst{11-8} = 0b1111; // Rd
850 // Assembler aliases w/o the ".w" suffix.
851 // No alias here for 'rr' version as not all instantiations of this
852 // multiclass want one (CMP in particular, does not).
853 def : t2InstAlias<!strconcat(opc, "${p}", " $Rn, $imm"),
854 (!cast<Instruction>(!strconcat(baseOpc, "ri")) GPRnopc:$Rn,
855 t2_so_imm:$imm, pred:$p)>;
856 def : t2InstAlias<!strconcat(opc, "${p}", " $Rn, $shift"),
857 (!cast<Instruction>(!strconcat(baseOpc, "rs")) GPRnopc:$Rn,
862 /// T2I_ld - Defines a set of (op r, {imm12|imm8|so_reg}) load patterns.
863 multiclass T2I_ld<bit signed, bits<2> opcod, string opc,
864 InstrItinClass iii, InstrItinClass iis, RegisterClass target,
866 def i12 : T2Ii12<(outs target:$Rt), (ins t2addrmode_imm12:$addr), iii,
867 opc, ".w\t$Rt, $addr",
868 [(set target:$Rt, (opnode t2addrmode_imm12:$addr))]> {
871 let Inst{31-25} = 0b1111100;
872 let Inst{24} = signed;
874 let Inst{22-21} = opcod;
875 let Inst{20} = 1; // load
876 let Inst{19-16} = addr{16-13}; // Rn
877 let Inst{15-12} = Rt;
878 let Inst{11-0} = addr{11-0}; // imm
880 def i8 : T2Ii8 <(outs target:$Rt), (ins t2addrmode_negimm8:$addr), iii,
882 [(set target:$Rt, (opnode t2addrmode_negimm8:$addr))]> {
885 let Inst{31-27} = 0b11111;
886 let Inst{26-25} = 0b00;
887 let Inst{24} = signed;
889 let Inst{22-21} = opcod;
890 let Inst{20} = 1; // load
891 let Inst{19-16} = addr{12-9}; // Rn
892 let Inst{15-12} = Rt;
894 // Offset: index==TRUE, wback==FALSE
895 let Inst{10} = 1; // The P bit.
896 let Inst{9} = addr{8}; // U
897 let Inst{8} = 0; // The W bit.
898 let Inst{7-0} = addr{7-0}; // imm
900 def s : T2Iso <(outs target:$Rt), (ins t2addrmode_so_reg:$addr), iis,
901 opc, ".w\t$Rt, $addr",
902 [(set target:$Rt, (opnode t2addrmode_so_reg:$addr))]> {
903 let Inst{31-27} = 0b11111;
904 let Inst{26-25} = 0b00;
905 let Inst{24} = signed;
907 let Inst{22-21} = opcod;
908 let Inst{20} = 1; // load
909 let Inst{11-6} = 0b000000;
912 let Inst{15-12} = Rt;
915 let Inst{19-16} = addr{9-6}; // Rn
916 let Inst{3-0} = addr{5-2}; // Rm
917 let Inst{5-4} = addr{1-0}; // imm
919 let DecoderMethod = "DecodeT2LoadShift";
922 // FIXME: Is the pci variant actually needed?
923 def pci : T2Ipc <(outs target:$Rt), (ins t2ldrlabel:$addr), iii,
924 opc, ".w\t$Rt, $addr",
925 [(set target:$Rt, (opnode (ARMWrapper tconstpool:$addr)))]> {
926 let isReMaterializable = 1;
927 let Inst{31-27} = 0b11111;
928 let Inst{26-25} = 0b00;
929 let Inst{24} = signed;
930 let Inst{23} = ?; // add = (U == '1')
931 let Inst{22-21} = opcod;
932 let Inst{20} = 1; // load
933 let Inst{19-16} = 0b1111; // Rn
936 let Inst{15-12} = Rt{3-0};
937 let Inst{11-0} = addr{11-0};
941 /// T2I_st - Defines a set of (op r, {imm12|imm8|so_reg}) store patterns.
942 multiclass T2I_st<bits<2> opcod, string opc,
943 InstrItinClass iii, InstrItinClass iis, RegisterClass target,
945 def i12 : T2Ii12<(outs), (ins target:$Rt, t2addrmode_imm12:$addr), iii,
946 opc, ".w\t$Rt, $addr",
947 [(opnode target:$Rt, t2addrmode_imm12:$addr)]> {
948 let Inst{31-27} = 0b11111;
949 let Inst{26-23} = 0b0001;
950 let Inst{22-21} = opcod;
951 let Inst{20} = 0; // !load
954 let Inst{15-12} = Rt;
957 let addr{12} = 1; // add = TRUE
958 let Inst{19-16} = addr{16-13}; // Rn
959 let Inst{23} = addr{12}; // U
960 let Inst{11-0} = addr{11-0}; // imm
962 def i8 : T2Ii8 <(outs), (ins target:$Rt, t2addrmode_negimm8:$addr), iii,
964 [(opnode target:$Rt, t2addrmode_negimm8:$addr)]> {
965 let Inst{31-27} = 0b11111;
966 let Inst{26-23} = 0b0000;
967 let Inst{22-21} = opcod;
968 let Inst{20} = 0; // !load
970 // Offset: index==TRUE, wback==FALSE
971 let Inst{10} = 1; // The P bit.
972 let Inst{8} = 0; // The W bit.
975 let Inst{15-12} = Rt;
978 let Inst{19-16} = addr{12-9}; // Rn
979 let Inst{9} = addr{8}; // U
980 let Inst{7-0} = addr{7-0}; // imm
982 def s : T2Iso <(outs), (ins target:$Rt, t2addrmode_so_reg:$addr), iis,
983 opc, ".w\t$Rt, $addr",
984 [(opnode target:$Rt, t2addrmode_so_reg:$addr)]> {
985 let Inst{31-27} = 0b11111;
986 let Inst{26-23} = 0b0000;
987 let Inst{22-21} = opcod;
988 let Inst{20} = 0; // !load
989 let Inst{11-6} = 0b000000;
992 let Inst{15-12} = Rt;
995 let Inst{19-16} = addr{9-6}; // Rn
996 let Inst{3-0} = addr{5-2}; // Rm
997 let Inst{5-4} = addr{1-0}; // imm
1001 /// T2I_ext_rrot - A unary operation with two forms: one whose operand is a
1002 /// register and one whose operand is a register rotated by 8/16/24.
1003 class T2I_ext_rrot<bits<3> opcod, string opc, PatFrag opnode>
1004 : T2TwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm, rot_imm:$rot), IIC_iEXTr,
1005 opc, ".w\t$Rd, $Rm$rot",
1006 [(set rGPR:$Rd, (opnode (rotr rGPR:$Rm, rot_imm:$rot)))]>,
1007 Requires<[IsThumb2]> {
1008 let Inst{31-27} = 0b11111;
1009 let Inst{26-23} = 0b0100;
1010 let Inst{22-20} = opcod;
1011 let Inst{19-16} = 0b1111; // Rn
1012 let Inst{15-12} = 0b1111;
1016 let Inst{5-4} = rot{1-0}; // rotate
1019 // UXTB16 - Requres T2ExtractPack, does not need the .w qualifier.
1020 class T2I_ext_rrot_uxtb16<bits<3> opcod, string opc, PatFrag opnode>
1021 : T2TwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm, rot_imm:$rot),
1022 IIC_iEXTr, opc, "\t$Rd, $Rm$rot",
1023 [(set rGPR:$Rd, (opnode (rotr rGPR:$Rm, rot_imm:$rot)))]>,
1024 Requires<[HasT2ExtractPack, IsThumb2]> {
1026 let Inst{31-27} = 0b11111;
1027 let Inst{26-23} = 0b0100;
1028 let Inst{22-20} = opcod;
1029 let Inst{19-16} = 0b1111; // Rn
1030 let Inst{15-12} = 0b1111;
1032 let Inst{5-4} = rot;
1035 // SXTB16 - Requres T2ExtractPack, does not need the .w qualifier, no pattern
1037 class T2I_ext_rrot_sxtb16<bits<3> opcod, string opc>
1038 : T2TwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm, rot_imm:$rot), IIC_iEXTr,
1039 opc, "\t$Rd, $Rm$rot", []>,
1040 Requires<[IsThumb2, HasT2ExtractPack]> {
1042 let Inst{31-27} = 0b11111;
1043 let Inst{26-23} = 0b0100;
1044 let Inst{22-20} = opcod;
1045 let Inst{19-16} = 0b1111; // Rn
1046 let Inst{15-12} = 0b1111;
1048 let Inst{5-4} = rot;
1051 /// T2I_exta_rrot - A binary operation with two forms: one whose operand is a
1052 /// register and one whose operand is a register rotated by 8/16/24.
1053 class T2I_exta_rrot<bits<3> opcod, string opc, PatFrag opnode>
1054 : T2ThreeReg<(outs rGPR:$Rd),
1055 (ins rGPR:$Rn, rGPR:$Rm, rot_imm:$rot),
1056 IIC_iEXTAsr, opc, "\t$Rd, $Rn, $Rm$rot",
1057 [(set rGPR:$Rd, (opnode rGPR:$Rn, (rotr rGPR:$Rm,rot_imm:$rot)))]>,
1058 Requires<[HasT2ExtractPack, IsThumb2]> {
1060 let Inst{31-27} = 0b11111;
1061 let Inst{26-23} = 0b0100;
1062 let Inst{22-20} = opcod;
1063 let Inst{15-12} = 0b1111;
1065 let Inst{5-4} = rot;
1068 class T2I_exta_rrot_np<bits<3> opcod, string opc>
1069 : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm,rot_imm:$rot),
1070 IIC_iEXTAsr, opc, "\t$Rd, $Rn, $Rm$rot", []> {
1072 let Inst{31-27} = 0b11111;
1073 let Inst{26-23} = 0b0100;
1074 let Inst{22-20} = opcod;
1075 let Inst{15-12} = 0b1111;
1077 let Inst{5-4} = rot;
1080 //===----------------------------------------------------------------------===//
1082 //===----------------------------------------------------------------------===//
1084 //===----------------------------------------------------------------------===//
1085 // Miscellaneous Instructions.
1088 class T2PCOneRegImm<dag oops, dag iops, InstrItinClass itin,
1089 string asm, list<dag> pattern>
1090 : T2XI<oops, iops, itin, asm, pattern> {
1094 let Inst{11-8} = Rd;
1095 let Inst{26} = label{11};
1096 let Inst{14-12} = label{10-8};
1097 let Inst{7-0} = label{7-0};
1100 // LEApcrel - Load a pc-relative address into a register without offending the
1102 def t2ADR : T2PCOneRegImm<(outs rGPR:$Rd),
1103 (ins t2adrlabel:$addr, pred:$p),
1104 IIC_iALUi, "adr{$p}.w\t$Rd, $addr", []> {
1105 let Inst{31-27} = 0b11110;
1106 let Inst{25-24} = 0b10;
1107 // Inst{23:21} = '11' (add = FALSE) or '00' (add = TRUE)
1110 let Inst{19-16} = 0b1111; // Rn
1115 let Inst{11-8} = Rd;
1116 let Inst{23} = addr{12};
1117 let Inst{21} = addr{12};
1118 let Inst{26} = addr{11};
1119 let Inst{14-12} = addr{10-8};
1120 let Inst{7-0} = addr{7-0};
1122 let DecoderMethod = "DecodeT2Adr";
1125 let neverHasSideEffects = 1, isReMaterializable = 1 in
1126 def t2LEApcrel : t2PseudoInst<(outs rGPR:$Rd), (ins i32imm:$label, pred:$p),
1128 def t2LEApcrelJT : t2PseudoInst<(outs rGPR:$Rd),
1129 (ins i32imm:$label, nohash_imm:$id, pred:$p),
1134 //===----------------------------------------------------------------------===//
1135 // Load / store Instructions.
1139 let canFoldAsLoad = 1, isReMaterializable = 1 in
1140 defm t2LDR : T2I_ld<0, 0b10, "ldr", IIC_iLoad_i, IIC_iLoad_si, GPR,
1141 UnOpFrag<(load node:$Src)>>;
1143 // Loads with zero extension
1144 defm t2LDRH : T2I_ld<0, 0b01, "ldrh", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
1145 rGPR, UnOpFrag<(zextloadi16 node:$Src)>>;
1146 defm t2LDRB : T2I_ld<0, 0b00, "ldrb", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
1147 rGPR, UnOpFrag<(zextloadi8 node:$Src)>>;
1149 // Loads with sign extension
1150 defm t2LDRSH : T2I_ld<1, 0b01, "ldrsh", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
1151 rGPR, UnOpFrag<(sextloadi16 node:$Src)>>;
1152 defm t2LDRSB : T2I_ld<1, 0b00, "ldrsb", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
1153 rGPR, UnOpFrag<(sextloadi8 node:$Src)>>;
1155 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
1157 def t2LDRDi8 : T2Ii8s4<1, 0, 1, (outs rGPR:$Rt, rGPR:$Rt2),
1158 (ins t2addrmode_imm8s4:$addr),
1159 IIC_iLoad_d_i, "ldrd", "\t$Rt, $Rt2, $addr", "", []>;
1160 } // mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1
1162 // zextload i1 -> zextload i8
1163 def : T2Pat<(zextloadi1 t2addrmode_imm12:$addr),
1164 (t2LDRBi12 t2addrmode_imm12:$addr)>;
1165 def : T2Pat<(zextloadi1 t2addrmode_negimm8:$addr),
1166 (t2LDRBi8 t2addrmode_negimm8:$addr)>;
1167 def : T2Pat<(zextloadi1 t2addrmode_so_reg:$addr),
1168 (t2LDRBs t2addrmode_so_reg:$addr)>;
1169 def : T2Pat<(zextloadi1 (ARMWrapper tconstpool:$addr)),
1170 (t2LDRBpci tconstpool:$addr)>;
1172 // extload -> zextload
1173 // FIXME: Reduce the number of patterns by legalizing extload to zextload
1175 def : T2Pat<(extloadi1 t2addrmode_imm12:$addr),
1176 (t2LDRBi12 t2addrmode_imm12:$addr)>;
1177 def : T2Pat<(extloadi1 t2addrmode_negimm8:$addr),
1178 (t2LDRBi8 t2addrmode_negimm8:$addr)>;
1179 def : T2Pat<(extloadi1 t2addrmode_so_reg:$addr),
1180 (t2LDRBs t2addrmode_so_reg:$addr)>;
1181 def : T2Pat<(extloadi1 (ARMWrapper tconstpool:$addr)),
1182 (t2LDRBpci tconstpool:$addr)>;
1184 def : T2Pat<(extloadi8 t2addrmode_imm12:$addr),
1185 (t2LDRBi12 t2addrmode_imm12:$addr)>;
1186 def : T2Pat<(extloadi8 t2addrmode_negimm8:$addr),
1187 (t2LDRBi8 t2addrmode_negimm8:$addr)>;
1188 def : T2Pat<(extloadi8 t2addrmode_so_reg:$addr),
1189 (t2LDRBs t2addrmode_so_reg:$addr)>;
1190 def : T2Pat<(extloadi8 (ARMWrapper tconstpool:$addr)),
1191 (t2LDRBpci tconstpool:$addr)>;
1193 def : T2Pat<(extloadi16 t2addrmode_imm12:$addr),
1194 (t2LDRHi12 t2addrmode_imm12:$addr)>;
1195 def : T2Pat<(extloadi16 t2addrmode_negimm8:$addr),
1196 (t2LDRHi8 t2addrmode_negimm8:$addr)>;
1197 def : T2Pat<(extloadi16 t2addrmode_so_reg:$addr),
1198 (t2LDRHs t2addrmode_so_reg:$addr)>;
1199 def : T2Pat<(extloadi16 (ARMWrapper tconstpool:$addr)),
1200 (t2LDRHpci tconstpool:$addr)>;
1202 // FIXME: The destination register of the loads and stores can't be PC, but
1203 // can be SP. We need another regclass (similar to rGPR) to represent
1204 // that. Not a pressing issue since these are selected manually,
1209 let mayLoad = 1, neverHasSideEffects = 1 in {
1210 def t2LDR_PRE : T2Ipreldst<0, 0b10, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1211 (ins t2addrmode_imm8:$addr),
1212 AddrModeT2_i8, IndexModePre, IIC_iLoad_iu,
1213 "ldr", "\t$Rt, $addr!", "$addr.base = $Rn_wb",
1215 let AsmMatchConverter = "cvtLdWriteBackRegT2AddrModeImm8";
1218 def t2LDR_POST : T2Ipostldst<0, 0b10, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1219 (ins addr_offset_none:$Rn, t2am_imm8_offset:$offset),
1220 AddrModeT2_i8, IndexModePost, IIC_iLoad_iu,
1221 "ldr", "\t$Rt, $Rn, $offset", "$Rn = $Rn_wb", []>;
1223 def t2LDRB_PRE : T2Ipreldst<0, 0b00, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1224 (ins t2addrmode_imm8:$addr),
1225 AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
1226 "ldrb", "\t$Rt, $addr!", "$addr.base = $Rn_wb",
1228 let AsmMatchConverter = "cvtLdWriteBackRegT2AddrModeImm8";
1230 def t2LDRB_POST : T2Ipostldst<0, 0b00, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1231 (ins addr_offset_none:$Rn, t2am_imm8_offset:$offset),
1232 AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
1233 "ldrb", "\t$Rt, $Rn, $offset", "$Rn = $Rn_wb", []>;
1235 def t2LDRH_PRE : T2Ipreldst<0, 0b01, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1236 (ins t2addrmode_imm8:$addr),
1237 AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
1238 "ldrh", "\t$Rt, $addr!", "$addr.base = $Rn_wb",
1240 let AsmMatchConverter = "cvtLdWriteBackRegT2AddrModeImm8";
1242 def t2LDRH_POST : T2Ipostldst<0, 0b01, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1243 (ins addr_offset_none:$Rn, t2am_imm8_offset:$offset),
1244 AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
1245 "ldrh", "\t$Rt, $Rn, $offset", "$Rn = $Rn_wb", []>;
1247 def t2LDRSB_PRE : T2Ipreldst<1, 0b00, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1248 (ins t2addrmode_imm8:$addr),
1249 AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
1250 "ldrsb", "\t$Rt, $addr!", "$addr.base = $Rn_wb",
1252 let AsmMatchConverter = "cvtLdWriteBackRegT2AddrModeImm8";
1254 def t2LDRSB_POST : T2Ipostldst<1, 0b00, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1255 (ins addr_offset_none:$Rn, t2am_imm8_offset:$offset),
1256 AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
1257 "ldrsb", "\t$Rt, $Rn, $offset", "$Rn = $Rn_wb", []>;
1259 def t2LDRSH_PRE : T2Ipreldst<1, 0b01, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1260 (ins t2addrmode_imm8:$addr),
1261 AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
1262 "ldrsh", "\t$Rt, $addr!", "$addr.base = $Rn_wb",
1264 let AsmMatchConverter = "cvtLdWriteBackRegT2AddrModeImm8";
1266 def t2LDRSH_POST : T2Ipostldst<1, 0b01, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1267 (ins addr_offset_none:$Rn, t2am_imm8_offset:$offset),
1268 AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
1269 "ldrsh", "\t$Rt, $Rn, $offset", "$Rn = $Rn_wb", []>;
1270 } // mayLoad = 1, neverHasSideEffects = 1
1272 // LDRT, LDRBT, LDRHT, LDRSBT, LDRSHT all have offset mode (PUW=0b110).
1273 // Ref: A8.6.57 LDR (immediate, Thumb) Encoding T4
1274 class T2IldT<bit signed, bits<2> type, string opc, InstrItinClass ii>
1275 : T2Ii8<(outs rGPR:$Rt), (ins t2addrmode_posimm8:$addr), ii, opc,
1276 "\t$Rt, $addr", []> {
1279 let Inst{31-27} = 0b11111;
1280 let Inst{26-25} = 0b00;
1281 let Inst{24} = signed;
1283 let Inst{22-21} = type;
1284 let Inst{20} = 1; // load
1285 let Inst{19-16} = addr{12-9};
1286 let Inst{15-12} = Rt;
1288 let Inst{10-8} = 0b110; // PUW.
1289 let Inst{7-0} = addr{7-0};
1292 def t2LDRT : T2IldT<0, 0b10, "ldrt", IIC_iLoad_i>;
1293 def t2LDRBT : T2IldT<0, 0b00, "ldrbt", IIC_iLoad_bh_i>;
1294 def t2LDRHT : T2IldT<0, 0b01, "ldrht", IIC_iLoad_bh_i>;
1295 def t2LDRSBT : T2IldT<1, 0b00, "ldrsbt", IIC_iLoad_bh_i>;
1296 def t2LDRSHT : T2IldT<1, 0b01, "ldrsht", IIC_iLoad_bh_i>;
1299 defm t2STR :T2I_st<0b10,"str", IIC_iStore_i, IIC_iStore_si, GPR,
1300 BinOpFrag<(store node:$LHS, node:$RHS)>>;
1301 defm t2STRB:T2I_st<0b00,"strb", IIC_iStore_bh_i, IIC_iStore_bh_si,
1302 rGPR, BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
1303 defm t2STRH:T2I_st<0b01,"strh", IIC_iStore_bh_i, IIC_iStore_bh_si,
1304 rGPR, BinOpFrag<(truncstorei16 node:$LHS, node:$RHS)>>;
1307 let mayLoad = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in
1308 def t2STRDi8 : T2Ii8s4<1, 0, 0, (outs),
1309 (ins GPR:$Rt, GPR:$Rt2, t2addrmode_imm8s4:$addr),
1310 IIC_iStore_d_r, "strd", "\t$Rt, $Rt2, $addr", "", []>;
1313 def t2STR_PRE : T2Ipreldst<0, 0b10, 0, 1, (outs GPRnopc:$Rn_wb),
1314 (ins rGPR:$Rt, t2addrmode_imm8:$addr),
1315 AddrModeT2_i8, IndexModePre, IIC_iStore_iu,
1316 "str", "\t$Rt, $addr!",
1317 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> {
1318 let AsmMatchConverter = "cvtStWriteBackRegT2AddrModeImm8";
1320 def t2STRH_PRE : T2Ipreldst<0, 0b01, 0, 1, (outs GPRnopc:$Rn_wb),
1321 (ins rGPR:$Rt, t2addrmode_imm8:$addr),
1322 AddrModeT2_i8, IndexModePre, IIC_iStore_iu,
1323 "strh", "\t$Rt, $addr!",
1324 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> {
1325 let AsmMatchConverter = "cvtStWriteBackRegT2AddrModeImm8";
1328 def t2STRB_PRE : T2Ipreldst<0, 0b00, 0, 1, (outs GPRnopc:$Rn_wb),
1329 (ins rGPR:$Rt, t2addrmode_imm8:$addr),
1330 AddrModeT2_i8, IndexModePre, IIC_iStore_bh_iu,
1331 "strb", "\t$Rt, $addr!",
1332 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> {
1333 let AsmMatchConverter = "cvtStWriteBackRegT2AddrModeImm8";
1336 def t2STR_POST : T2Ipostldst<0, 0b10, 0, 0, (outs GPRnopc:$Rn_wb),
1337 (ins rGPR:$Rt, addr_offset_none:$Rn,
1338 t2am_imm8_offset:$offset),
1339 AddrModeT2_i8, IndexModePost, IIC_iStore_iu,
1340 "str", "\t$Rt, $Rn, $offset",
1341 "$Rn = $Rn_wb,@earlyclobber $Rn_wb",
1342 [(set GPRnopc:$Rn_wb,
1343 (post_store rGPR:$Rt, addr_offset_none:$Rn,
1344 t2am_imm8_offset:$offset))]>;
1346 def t2STRH_POST : T2Ipostldst<0, 0b01, 0, 0, (outs GPRnopc:$Rn_wb),
1347 (ins rGPR:$Rt, addr_offset_none:$Rn,
1348 t2am_imm8_offset:$offset),
1349 AddrModeT2_i8, IndexModePost, IIC_iStore_bh_iu,
1350 "strh", "\t$Rt, $Rn, $offset",
1351 "$Rn = $Rn_wb,@earlyclobber $Rn_wb",
1352 [(set GPRnopc:$Rn_wb,
1353 (post_truncsti16 rGPR:$Rt, addr_offset_none:$Rn,
1354 t2am_imm8_offset:$offset))]>;
1356 def t2STRB_POST : T2Ipostldst<0, 0b00, 0, 0, (outs GPRnopc:$Rn_wb),
1357 (ins rGPR:$Rt, addr_offset_none:$Rn,
1358 t2am_imm8_offset:$offset),
1359 AddrModeT2_i8, IndexModePost, IIC_iStore_bh_iu,
1360 "strb", "\t$Rt, $Rn, $offset",
1361 "$Rn = $Rn_wb,@earlyclobber $Rn_wb",
1362 [(set GPRnopc:$Rn_wb,
1363 (post_truncsti8 rGPR:$Rt, addr_offset_none:$Rn,
1364 t2am_imm8_offset:$offset))]>;
1366 // Pseudo-instructions for pattern matching the pre-indexed stores. We can't
1367 // put the patterns on the instruction definitions directly as ISel wants
1368 // the address base and offset to be separate operands, not a single
1369 // complex operand like we represent the instructions themselves. The
1370 // pseudos map between the two.
1371 let usesCustomInserter = 1,
1372 Constraints = "$Rn = $Rn_wb,@earlyclobber $Rn_wb" in {
1373 def t2STR_preidx: t2PseudoInst<(outs GPRnopc:$Rn_wb),
1374 (ins rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$offset, pred:$p),
1376 [(set GPRnopc:$Rn_wb,
1377 (pre_store rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$offset))]>;
1378 def t2STRB_preidx: t2PseudoInst<(outs GPRnopc:$Rn_wb),
1379 (ins rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$offset, pred:$p),
1381 [(set GPRnopc:$Rn_wb,
1382 (pre_truncsti8 rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$offset))]>;
1383 def t2STRH_preidx: t2PseudoInst<(outs GPRnopc:$Rn_wb),
1384 (ins rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$offset, pred:$p),
1386 [(set GPRnopc:$Rn_wb,
1387 (pre_truncsti16 rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$offset))]>;
1391 // STRT, STRBT, STRHT all have offset mode (PUW=0b110) and are for disassembly
1393 // Ref: A8.6.193 STR (immediate, Thumb) Encoding T4
1394 class T2IstT<bits<2> type, string opc, InstrItinClass ii>
1395 : T2Ii8<(outs rGPR:$Rt), (ins t2addrmode_imm8:$addr), ii, opc,
1396 "\t$Rt, $addr", []> {
1397 let Inst{31-27} = 0b11111;
1398 let Inst{26-25} = 0b00;
1399 let Inst{24} = 0; // not signed
1401 let Inst{22-21} = type;
1402 let Inst{20} = 0; // store
1404 let Inst{10-8} = 0b110; // PUW
1408 let Inst{15-12} = Rt;
1409 let Inst{19-16} = addr{12-9};
1410 let Inst{7-0} = addr{7-0};
1413 def t2STRT : T2IstT<0b10, "strt", IIC_iStore_i>;
1414 def t2STRBT : T2IstT<0b00, "strbt", IIC_iStore_bh_i>;
1415 def t2STRHT : T2IstT<0b01, "strht", IIC_iStore_bh_i>;
1417 // ldrd / strd pre / post variants
1418 // For disassembly only.
1420 def t2LDRD_PRE : T2Ii8s4<1, 1, 1, (outs rGPR:$Rt, rGPR:$Rt2, GPR:$wb),
1421 (ins t2addrmode_imm8s4:$addr), IIC_iLoad_d_ru,
1422 "ldrd", "\t$Rt, $Rt2, $addr!", "$addr.base = $wb", []> {
1423 let AsmMatchConverter = "cvtT2LdrdPre";
1424 let DecoderMethod = "DecodeT2LDRDPreInstruction";
1427 def t2LDRD_POST : T2Ii8s4post<0, 1, 1, (outs rGPR:$Rt, rGPR:$Rt2, GPR:$wb),
1428 (ins addr_offset_none:$addr, t2am_imm8s4_offset:$imm),
1429 IIC_iLoad_d_ru, "ldrd", "\t$Rt, $Rt2, $addr$imm",
1430 "$addr.base = $wb", []>;
1432 def t2STRD_PRE : T2Ii8s4<1, 1, 0, (outs GPR:$wb),
1433 (ins rGPR:$Rt, rGPR:$Rt2, t2addrmode_imm8s4:$addr),
1434 IIC_iStore_d_ru, "strd", "\t$Rt, $Rt2, $addr!",
1435 "$addr.base = $wb", []> {
1436 let AsmMatchConverter = "cvtT2StrdPre";
1437 let DecoderMethod = "DecodeT2STRDPreInstruction";
1440 def t2STRD_POST : T2Ii8s4post<0, 1, 0, (outs GPR:$wb),
1441 (ins rGPR:$Rt, rGPR:$Rt2, addr_offset_none:$addr,
1442 t2am_imm8s4_offset:$imm),
1443 IIC_iStore_d_ru, "strd", "\t$Rt, $Rt2, $addr$imm",
1444 "$addr.base = $wb", []>;
1446 // T2Ipl (Preload Data/Instruction) signals the memory system of possible future
1447 // data/instruction access. These are for disassembly only.
1448 // instr_write is inverted for Thumb mode: (prefetch 3) -> (preload 0),
1449 // (prefetch 1) -> (preload 2), (prefetch 2) -> (preload 1).
1450 multiclass T2Ipl<bits<1> write, bits<1> instr, string opc> {
1452 def i12 : T2Ii12<(outs), (ins t2addrmode_imm12:$addr), IIC_Preload, opc,
1454 [(ARMPreload t2addrmode_imm12:$addr, (i32 write), (i32 instr))]> {
1455 let Inst{31-25} = 0b1111100;
1456 let Inst{24} = instr;
1458 let Inst{21} = write;
1460 let Inst{15-12} = 0b1111;
1463 let addr{12} = 1; // add = TRUE
1464 let Inst{19-16} = addr{16-13}; // Rn
1465 let Inst{23} = addr{12}; // U
1466 let Inst{11-0} = addr{11-0}; // imm12
1469 def i8 : T2Ii8<(outs), (ins t2addrmode_negimm8:$addr), IIC_Preload, opc,
1471 [(ARMPreload t2addrmode_negimm8:$addr, (i32 write), (i32 instr))]> {
1472 let Inst{31-25} = 0b1111100;
1473 let Inst{24} = instr;
1474 let Inst{23} = 0; // U = 0
1476 let Inst{21} = write;
1478 let Inst{15-12} = 0b1111;
1479 let Inst{11-8} = 0b1100;
1482 let Inst{19-16} = addr{12-9}; // Rn
1483 let Inst{7-0} = addr{7-0}; // imm8
1486 def s : T2Iso<(outs), (ins t2addrmode_so_reg:$addr), IIC_Preload, opc,
1488 [(ARMPreload t2addrmode_so_reg:$addr, (i32 write), (i32 instr))]> {
1489 let Inst{31-25} = 0b1111100;
1490 let Inst{24} = instr;
1491 let Inst{23} = 0; // add = TRUE for T1
1493 let Inst{21} = write;
1495 let Inst{15-12} = 0b1111;
1496 let Inst{11-6} = 0000000;
1499 let Inst{19-16} = addr{9-6}; // Rn
1500 let Inst{3-0} = addr{5-2}; // Rm
1501 let Inst{5-4} = addr{1-0}; // imm2
1503 let DecoderMethod = "DecodeT2LoadShift";
1507 defm t2PLD : T2Ipl<0, 0, "pld">, Requires<[IsThumb2]>;
1508 defm t2PLDW : T2Ipl<1, 0, "pldw">, Requires<[IsThumb2,HasV7,HasMP]>;
1509 defm t2PLI : T2Ipl<0, 1, "pli">, Requires<[IsThumb2,HasV7]>;
1511 //===----------------------------------------------------------------------===//
1512 // Load / store multiple Instructions.
1515 multiclass thumb2_ld_mult<string asm, InstrItinClass itin,
1516 InstrItinClass itin_upd, bit L_bit> {
1518 T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1519 itin, !strconcat(asm, "${p}.w\t$Rn, $regs"), []> {
1523 let Inst{31-27} = 0b11101;
1524 let Inst{26-25} = 0b00;
1525 let Inst{24-23} = 0b01; // Increment After
1527 let Inst{21} = 0; // No writeback
1528 let Inst{20} = L_bit;
1529 let Inst{19-16} = Rn;
1531 let Inst{14-0} = regs{14-0};
1534 T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1535 itin_upd, !strconcat(asm, "${p}.w\t$Rn!, $regs"), "$Rn = $wb", []> {
1539 let Inst{31-27} = 0b11101;
1540 let Inst{26-25} = 0b00;
1541 let Inst{24-23} = 0b01; // Increment After
1543 let Inst{21} = 1; // Writeback
1544 let Inst{20} = L_bit;
1545 let Inst{19-16} = Rn;
1547 let Inst{14-0} = regs{14-0};
1550 T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1551 itin, !strconcat(asm, "db${p}\t$Rn, $regs"), []> {
1555 let Inst{31-27} = 0b11101;
1556 let Inst{26-25} = 0b00;
1557 let Inst{24-23} = 0b10; // Decrement Before
1559 let Inst{21} = 0; // No writeback
1560 let Inst{20} = L_bit;
1561 let Inst{19-16} = Rn;
1563 let Inst{14-0} = regs{14-0};
1566 T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1567 itin_upd, !strconcat(asm, "db${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
1571 let Inst{31-27} = 0b11101;
1572 let Inst{26-25} = 0b00;
1573 let Inst{24-23} = 0b10; // Decrement Before
1575 let Inst{21} = 1; // Writeback
1576 let Inst{20} = L_bit;
1577 let Inst{19-16} = Rn;
1579 let Inst{14-0} = regs{14-0};
1583 let neverHasSideEffects = 1 in {
1585 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
1586 defm t2LDM : thumb2_ld_mult<"ldm", IIC_iLoad_m, IIC_iLoad_mu, 1>;
1588 multiclass thumb2_st_mult<string asm, InstrItinClass itin,
1589 InstrItinClass itin_upd, bit L_bit> {
1591 T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1592 itin, !strconcat(asm, "${p}.w\t$Rn, $regs"), []> {
1596 let Inst{31-27} = 0b11101;
1597 let Inst{26-25} = 0b00;
1598 let Inst{24-23} = 0b01; // Increment After
1600 let Inst{21} = 0; // No writeback
1601 let Inst{20} = L_bit;
1602 let Inst{19-16} = Rn;
1604 let Inst{14} = regs{14};
1606 let Inst{12-0} = regs{12-0};
1609 T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1610 itin_upd, !strconcat(asm, "${p}.w\t$Rn!, $regs"), "$Rn = $wb", []> {
1614 let Inst{31-27} = 0b11101;
1615 let Inst{26-25} = 0b00;
1616 let Inst{24-23} = 0b01; // Increment After
1618 let Inst{21} = 1; // Writeback
1619 let Inst{20} = L_bit;
1620 let Inst{19-16} = Rn;
1622 let Inst{14} = regs{14};
1624 let Inst{12-0} = regs{12-0};
1627 T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1628 itin, !strconcat(asm, "db${p}\t$Rn, $regs"), []> {
1632 let Inst{31-27} = 0b11101;
1633 let Inst{26-25} = 0b00;
1634 let Inst{24-23} = 0b10; // Decrement Before
1636 let Inst{21} = 0; // No writeback
1637 let Inst{20} = L_bit;
1638 let Inst{19-16} = Rn;
1640 let Inst{14} = regs{14};
1642 let Inst{12-0} = regs{12-0};
1645 T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1646 itin_upd, !strconcat(asm, "db${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
1650 let Inst{31-27} = 0b11101;
1651 let Inst{26-25} = 0b00;
1652 let Inst{24-23} = 0b10; // Decrement Before
1654 let Inst{21} = 1; // Writeback
1655 let Inst{20} = L_bit;
1656 let Inst{19-16} = Rn;
1658 let Inst{14} = regs{14};
1660 let Inst{12-0} = regs{12-0};
1665 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
1666 defm t2STM : thumb2_st_mult<"stm", IIC_iStore_m, IIC_iStore_mu, 0>;
1668 } // neverHasSideEffects
1671 //===----------------------------------------------------------------------===//
1672 // Move Instructions.
1675 let neverHasSideEffects = 1 in
1676 def t2MOVr : T2sTwoReg<(outs GPRnopc:$Rd), (ins GPR:$Rm), IIC_iMOVr,
1677 "mov", ".w\t$Rd, $Rm", []> {
1678 let Inst{31-27} = 0b11101;
1679 let Inst{26-25} = 0b01;
1680 let Inst{24-21} = 0b0010;
1681 let Inst{19-16} = 0b1111; // Rn
1682 let Inst{14-12} = 0b000;
1683 let Inst{7-4} = 0b0000;
1685 def : t2InstAlias<"movs${p}.w $Rd, $Rm", (t2MOVr GPRnopc:$Rd, GPR:$Rm,
1687 def : t2InstAlias<"movs${p} $Rd, $Rm", (t2MOVr GPRnopc:$Rd, GPR:$Rm,
1690 // AddedComplexity to ensure isel tries t2MOVi before t2MOVi16.
1691 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1,
1692 AddedComplexity = 1 in
1693 def t2MOVi : T2sOneRegImm<(outs rGPR:$Rd), (ins t2_so_imm:$imm), IIC_iMOVi,
1694 "mov", ".w\t$Rd, $imm",
1695 [(set rGPR:$Rd, t2_so_imm:$imm)]> {
1696 let Inst{31-27} = 0b11110;
1698 let Inst{24-21} = 0b0010;
1699 let Inst{19-16} = 0b1111; // Rn
1703 // cc_out is handled as part of the explicit mnemonic in the parser for 'mov'.
1704 // Use aliases to get that to play nice here.
1705 def : t2InstAlias<"movs${p}.w $Rd, $imm", (t2MOVi rGPR:$Rd, t2_so_imm:$imm,
1707 def : t2InstAlias<"movs${p} $Rd, $imm", (t2MOVi rGPR:$Rd, t2_so_imm:$imm,
1710 def : t2InstAlias<"mov${p}.w $Rd, $imm", (t2MOVi rGPR:$Rd, t2_so_imm:$imm,
1711 pred:$p, zero_reg)>;
1712 def : t2InstAlias<"mov${p} $Rd, $imm", (t2MOVi rGPR:$Rd, t2_so_imm:$imm,
1713 pred:$p, zero_reg)>;
1715 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
1716 def t2MOVi16 : T2I<(outs rGPR:$Rd), (ins imm0_65535_expr:$imm), IIC_iMOVi,
1717 "movw", "\t$Rd, $imm",
1718 [(set rGPR:$Rd, imm0_65535:$imm)]> {
1719 let Inst{31-27} = 0b11110;
1721 let Inst{24-21} = 0b0010;
1722 let Inst{20} = 0; // The S bit.
1728 let Inst{11-8} = Rd;
1729 let Inst{19-16} = imm{15-12};
1730 let Inst{26} = imm{11};
1731 let Inst{14-12} = imm{10-8};
1732 let Inst{7-0} = imm{7-0};
1735 def t2MOVi16_ga_pcrel : PseudoInst<(outs rGPR:$Rd),
1736 (ins i32imm:$addr, pclabel:$id), IIC_iMOVi, []>;
1738 let Constraints = "$src = $Rd" in {
1739 def t2MOVTi16 : T2I<(outs rGPR:$Rd),
1740 (ins rGPR:$src, imm0_65535_expr:$imm), IIC_iMOVi,
1741 "movt", "\t$Rd, $imm",
1743 (or (and rGPR:$src, 0xffff), lo16AllZero:$imm))]> {
1744 let Inst{31-27} = 0b11110;
1746 let Inst{24-21} = 0b0110;
1747 let Inst{20} = 0; // The S bit.
1753 let Inst{11-8} = Rd;
1754 let Inst{19-16} = imm{15-12};
1755 let Inst{26} = imm{11};
1756 let Inst{14-12} = imm{10-8};
1757 let Inst{7-0} = imm{7-0};
1760 def t2MOVTi16_ga_pcrel : PseudoInst<(outs rGPR:$Rd),
1761 (ins rGPR:$src, i32imm:$addr, pclabel:$id), IIC_iMOVi, []>;
1764 def : T2Pat<(or rGPR:$src, 0xffff0000), (t2MOVTi16 rGPR:$src, 0xffff)>;
1766 //===----------------------------------------------------------------------===//
1767 // Extend Instructions.
1772 def t2SXTB : T2I_ext_rrot<0b100, "sxtb",
1773 UnOpFrag<(sext_inreg node:$Src, i8)>>;
1774 def t2SXTH : T2I_ext_rrot<0b000, "sxth",
1775 UnOpFrag<(sext_inreg node:$Src, i16)>>;
1776 def t2SXTB16 : T2I_ext_rrot_sxtb16<0b010, "sxtb16">;
1778 def t2SXTAB : T2I_exta_rrot<0b100, "sxtab",
1779 BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
1780 def t2SXTAH : T2I_exta_rrot<0b000, "sxtah",
1781 BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
1782 def t2SXTAB16 : T2I_exta_rrot_np<0b010, "sxtab16">;
1786 let AddedComplexity = 16 in {
1787 def t2UXTB : T2I_ext_rrot<0b101, "uxtb",
1788 UnOpFrag<(and node:$Src, 0x000000FF)>>;
1789 def t2UXTH : T2I_ext_rrot<0b001, "uxth",
1790 UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
1791 def t2UXTB16 : T2I_ext_rrot_uxtb16<0b011, "uxtb16",
1792 UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
1794 // FIXME: This pattern incorrectly assumes the shl operator is a rotate.
1795 // The transformation should probably be done as a combiner action
1796 // instead so we can include a check for masking back in the upper
1797 // eight bits of the source into the lower eight bits of the result.
1798 //def : T2Pat<(and (shl rGPR:$Src, (i32 8)), 0xFF00FF),
1799 // (t2UXTB16 rGPR:$Src, 3)>,
1800 // Requires<[HasT2ExtractPack, IsThumb2]>;
1801 def : T2Pat<(and (srl rGPR:$Src, (i32 8)), 0xFF00FF),
1802 (t2UXTB16 rGPR:$Src, 1)>,
1803 Requires<[HasT2ExtractPack, IsThumb2]>;
1805 def t2UXTAB : T2I_exta_rrot<0b101, "uxtab",
1806 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
1807 def t2UXTAH : T2I_exta_rrot<0b001, "uxtah",
1808 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
1809 def t2UXTAB16 : T2I_exta_rrot_np<0b011, "uxtab16">;
1812 //===----------------------------------------------------------------------===//
1813 // Arithmetic Instructions.
1816 defm t2ADD : T2I_bin_ii12rs<0b000, "add",
1817 BinOpFrag<(add node:$LHS, node:$RHS)>, 1>;
1818 defm t2SUB : T2I_bin_ii12rs<0b101, "sub",
1819 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
1821 // ADD and SUB with 's' bit set. No 12-bit immediate (T4) variants.
1823 // Currently, t2ADDS/t2SUBS are pseudo opcodes that exist only in the
1824 // selection DAG. They are "lowered" to real t2ADD/t2SUB opcodes by
1825 // AdjustInstrPostInstrSelection where we determine whether or not to
1826 // set the "s" bit based on CPSR liveness.
1828 // FIXME: Eliminate t2ADDS/t2SUBS pseudo opcodes after adding tablegen
1829 // support for an optional CPSR definition that corresponds to the DAG
1830 // node's second value. We can then eliminate the implicit def of CPSR.
1831 defm t2ADDS : T2I_bin_s_irs <0b1000, "add",
1832 IIC_iALUi, IIC_iALUr, IIC_iALUsi,
1833 BinOpFrag<(ARMaddc node:$LHS, node:$RHS)>, 1>;
1834 defm t2SUBS : T2I_bin_s_irs <0b1101, "sub",
1835 IIC_iALUi, IIC_iALUr, IIC_iALUsi,
1836 BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>;
1838 let hasPostISelHook = 1 in {
1839 defm t2ADC : T2I_adde_sube_irs<0b1010, "adc",
1840 BinOpWithFlagFrag<(ARMadde node:$LHS, node:$RHS, node:$FLAG)>, 1>;
1841 defm t2SBC : T2I_adde_sube_irs<0b1011, "sbc",
1842 BinOpWithFlagFrag<(ARMsube node:$LHS, node:$RHS, node:$FLAG)>>;
1846 defm t2RSB : T2I_rbin_irs <0b1110, "rsb",
1847 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
1849 // FIXME: Eliminate them if we can write def : Pat patterns which defines
1850 // CPSR and the implicit def of CPSR is not needed.
1851 defm t2RSBS : T2I_rbin_s_is <0b1110, "rsb",
1852 BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>;
1854 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
1855 // The assume-no-carry-in form uses the negation of the input since add/sub
1856 // assume opposite meanings of the carry flag (i.e., carry == !borrow).
1857 // See the definition of AddWithCarry() in the ARM ARM A2.2.1 for the gory
1859 // The AddedComplexity preferences the first variant over the others since
1860 // it can be shrunk to a 16-bit wide encoding, while the others cannot.
1861 let AddedComplexity = 1 in
1862 def : T2Pat<(add GPR:$src, imm0_255_neg:$imm),
1863 (t2SUBri GPR:$src, imm0_255_neg:$imm)>;
1864 def : T2Pat<(add GPR:$src, t2_so_imm_neg:$imm),
1865 (t2SUBri GPR:$src, t2_so_imm_neg:$imm)>;
1866 def : T2Pat<(add GPR:$src, imm0_4095_neg:$imm),
1867 (t2SUBri12 GPR:$src, imm0_4095_neg:$imm)>;
1868 let AddedComplexity = 1 in
1869 def : T2Pat<(ARMaddc rGPR:$src, imm0_255_neg:$imm),
1870 (t2SUBSri rGPR:$src, imm0_255_neg:$imm)>;
1871 def : T2Pat<(ARMaddc rGPR:$src, t2_so_imm_neg:$imm),
1872 (t2SUBSri rGPR:$src, t2_so_imm_neg:$imm)>;
1873 // The with-carry-in form matches bitwise not instead of the negation.
1874 // Effectively, the inverse interpretation of the carry flag already accounts
1875 // for part of the negation.
1876 let AddedComplexity = 1 in
1877 def : T2Pat<(ARMadde rGPR:$src, imm0_255_not:$imm, CPSR),
1878 (t2SBCri rGPR:$src, imm0_255_not:$imm)>;
1879 def : T2Pat<(ARMadde rGPR:$src, t2_so_imm_not:$imm, CPSR),
1880 (t2SBCri rGPR:$src, t2_so_imm_not:$imm)>;
1882 // Select Bytes -- for disassembly only
1884 def t2SEL : T2ThreeReg<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
1885 NoItinerary, "sel", "\t$Rd, $Rn, $Rm", []>,
1886 Requires<[IsThumb2, HasThumb2DSP]> {
1887 let Inst{31-27} = 0b11111;
1888 let Inst{26-24} = 0b010;
1890 let Inst{22-20} = 0b010;
1891 let Inst{15-12} = 0b1111;
1893 let Inst{6-4} = 0b000;
1896 // A6.3.13, A6.3.14, A6.3.15 Parallel addition and subtraction (signed/unsigned)
1897 // And Miscellaneous operations -- for disassembly only
1898 class T2I_pam<bits<3> op22_20, bits<4> op7_4, string opc,
1899 list<dag> pat = [/* For disassembly only; pattern left blank */],
1900 dag iops = (ins rGPR:$Rn, rGPR:$Rm),
1901 string asm = "\t$Rd, $Rn, $Rm">
1902 : T2I<(outs rGPR:$Rd), iops, NoItinerary, opc, asm, pat>,
1903 Requires<[IsThumb2, HasThumb2DSP]> {
1904 let Inst{31-27} = 0b11111;
1905 let Inst{26-23} = 0b0101;
1906 let Inst{22-20} = op22_20;
1907 let Inst{15-12} = 0b1111;
1908 let Inst{7-4} = op7_4;
1914 let Inst{11-8} = Rd;
1915 let Inst{19-16} = Rn;
1919 // Saturating add/subtract -- for disassembly only
1921 def t2QADD : T2I_pam<0b000, 0b1000, "qadd",
1922 [(set rGPR:$Rd, (int_arm_qadd rGPR:$Rn, rGPR:$Rm))],
1923 (ins rGPR:$Rm, rGPR:$Rn), "\t$Rd, $Rm, $Rn">;
1924 def t2QADD16 : T2I_pam<0b001, 0b0001, "qadd16">;
1925 def t2QADD8 : T2I_pam<0b000, 0b0001, "qadd8">;
1926 def t2QASX : T2I_pam<0b010, 0b0001, "qasx">;
1927 def t2QDADD : T2I_pam<0b000, 0b1001, "qdadd", [],
1928 (ins rGPR:$Rm, rGPR:$Rn), "\t$Rd, $Rm, $Rn">;
1929 def t2QDSUB : T2I_pam<0b000, 0b1011, "qdsub", [],
1930 (ins rGPR:$Rm, rGPR:$Rn), "\t$Rd, $Rm, $Rn">;
1931 def t2QSAX : T2I_pam<0b110, 0b0001, "qsax">;
1932 def t2QSUB : T2I_pam<0b000, 0b1010, "qsub",
1933 [(set rGPR:$Rd, (int_arm_qsub rGPR:$Rn, rGPR:$Rm))],
1934 (ins rGPR:$Rm, rGPR:$Rn), "\t$Rd, $Rm, $Rn">;
1935 def t2QSUB16 : T2I_pam<0b101, 0b0001, "qsub16">;
1936 def t2QSUB8 : T2I_pam<0b100, 0b0001, "qsub8">;
1937 def t2UQADD16 : T2I_pam<0b001, 0b0101, "uqadd16">;
1938 def t2UQADD8 : T2I_pam<0b000, 0b0101, "uqadd8">;
1939 def t2UQASX : T2I_pam<0b010, 0b0101, "uqasx">;
1940 def t2UQSAX : T2I_pam<0b110, 0b0101, "uqsax">;
1941 def t2UQSUB16 : T2I_pam<0b101, 0b0101, "uqsub16">;
1942 def t2UQSUB8 : T2I_pam<0b100, 0b0101, "uqsub8">;
1944 // Signed/Unsigned add/subtract -- for disassembly only
1946 def t2SASX : T2I_pam<0b010, 0b0000, "sasx">;
1947 def t2SADD16 : T2I_pam<0b001, 0b0000, "sadd16">;
1948 def t2SADD8 : T2I_pam<0b000, 0b0000, "sadd8">;
1949 def t2SSAX : T2I_pam<0b110, 0b0000, "ssax">;
1950 def t2SSUB16 : T2I_pam<0b101, 0b0000, "ssub16">;
1951 def t2SSUB8 : T2I_pam<0b100, 0b0000, "ssub8">;
1952 def t2UASX : T2I_pam<0b010, 0b0100, "uasx">;
1953 def t2UADD16 : T2I_pam<0b001, 0b0100, "uadd16">;
1954 def t2UADD8 : T2I_pam<0b000, 0b0100, "uadd8">;
1955 def t2USAX : T2I_pam<0b110, 0b0100, "usax">;
1956 def t2USUB16 : T2I_pam<0b101, 0b0100, "usub16">;
1957 def t2USUB8 : T2I_pam<0b100, 0b0100, "usub8">;
1959 // Signed/Unsigned halving add/subtract -- for disassembly only
1961 def t2SHASX : T2I_pam<0b010, 0b0010, "shasx">;
1962 def t2SHADD16 : T2I_pam<0b001, 0b0010, "shadd16">;
1963 def t2SHADD8 : T2I_pam<0b000, 0b0010, "shadd8">;
1964 def t2SHSAX : T2I_pam<0b110, 0b0010, "shsax">;
1965 def t2SHSUB16 : T2I_pam<0b101, 0b0010, "shsub16">;
1966 def t2SHSUB8 : T2I_pam<0b100, 0b0010, "shsub8">;
1967 def t2UHASX : T2I_pam<0b010, 0b0110, "uhasx">;
1968 def t2UHADD16 : T2I_pam<0b001, 0b0110, "uhadd16">;
1969 def t2UHADD8 : T2I_pam<0b000, 0b0110, "uhadd8">;
1970 def t2UHSAX : T2I_pam<0b110, 0b0110, "uhsax">;
1971 def t2UHSUB16 : T2I_pam<0b101, 0b0110, "uhsub16">;
1972 def t2UHSUB8 : T2I_pam<0b100, 0b0110, "uhsub8">;
1974 // Helper class for disassembly only
1975 // A6.3.16 & A6.3.17
1976 // T2Imac - Thumb2 multiply [accumulate, and absolute difference] instructions.
1977 class T2ThreeReg_mac<bit long, bits<3> op22_20, bits<4> op7_4, dag oops,
1978 dag iops, InstrItinClass itin, string opc, string asm, list<dag> pattern>
1979 : T2ThreeReg<oops, iops, itin, opc, asm, pattern> {
1980 let Inst{31-27} = 0b11111;
1981 let Inst{26-24} = 0b011;
1982 let Inst{23} = long;
1983 let Inst{22-20} = op22_20;
1984 let Inst{7-4} = op7_4;
1987 class T2FourReg_mac<bit long, bits<3> op22_20, bits<4> op7_4, dag oops,
1988 dag iops, InstrItinClass itin, string opc, string asm, list<dag> pattern>
1989 : T2FourReg<oops, iops, itin, opc, asm, pattern> {
1990 let Inst{31-27} = 0b11111;
1991 let Inst{26-24} = 0b011;
1992 let Inst{23} = long;
1993 let Inst{22-20} = op22_20;
1994 let Inst{7-4} = op7_4;
1997 // Unsigned Sum of Absolute Differences [and Accumulate].
1998 def t2USAD8 : T2ThreeReg_mac<0, 0b111, 0b0000, (outs rGPR:$Rd),
1999 (ins rGPR:$Rn, rGPR:$Rm),
2000 NoItinerary, "usad8", "\t$Rd, $Rn, $Rm", []>,
2001 Requires<[IsThumb2, HasThumb2DSP]> {
2002 let Inst{15-12} = 0b1111;
2004 def t2USADA8 : T2FourReg_mac<0, 0b111, 0b0000, (outs rGPR:$Rd),
2005 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), NoItinerary,
2006 "usada8", "\t$Rd, $Rn, $Rm, $Ra", []>,
2007 Requires<[IsThumb2, HasThumb2DSP]>;
2009 // Signed/Unsigned saturate.
2010 class T2SatI<dag oops, dag iops, InstrItinClass itin,
2011 string opc, string asm, list<dag> pattern>
2012 : T2I<oops, iops, itin, opc, asm, pattern> {
2018 let Inst{11-8} = Rd;
2019 let Inst{19-16} = Rn;
2020 let Inst{4-0} = sat_imm;
2021 let Inst{21} = sh{5};
2022 let Inst{14-12} = sh{4-2};
2023 let Inst{7-6} = sh{1-0};
2027 (outs rGPR:$Rd), (ins imm1_32:$sat_imm, rGPR:$Rn, shift_imm:$sh),
2028 NoItinerary, "ssat", "\t$Rd, $sat_imm, $Rn$sh", []> {
2029 let Inst{31-27} = 0b11110;
2030 let Inst{25-22} = 0b1100;
2036 def t2SSAT16: T2SatI<
2037 (outs rGPR:$Rd), (ins imm1_16:$sat_imm, rGPR:$Rn), NoItinerary,
2038 "ssat16", "\t$Rd, $sat_imm, $Rn", []>,
2039 Requires<[IsThumb2, HasThumb2DSP]> {
2040 let Inst{31-27} = 0b11110;
2041 let Inst{25-22} = 0b1100;
2044 let Inst{21} = 1; // sh = '1'
2045 let Inst{14-12} = 0b000; // imm3 = '000'
2046 let Inst{7-6} = 0b00; // imm2 = '00'
2047 let Inst{5-4} = 0b00;
2051 (outs rGPR:$Rd), (ins imm0_31:$sat_imm, rGPR:$Rn, shift_imm:$sh),
2052 NoItinerary, "usat", "\t$Rd, $sat_imm, $Rn$sh", []> {
2053 let Inst{31-27} = 0b11110;
2054 let Inst{25-22} = 0b1110;
2059 def t2USAT16: T2SatI<(outs rGPR:$Rd), (ins imm0_15:$sat_imm, rGPR:$Rn),
2061 "usat16", "\t$Rd, $sat_imm, $Rn", []>,
2062 Requires<[IsThumb2, HasThumb2DSP]> {
2063 let Inst{31-27} = 0b11110;
2064 let Inst{25-22} = 0b1110;
2067 let Inst{21} = 1; // sh = '1'
2068 let Inst{14-12} = 0b000; // imm3 = '000'
2069 let Inst{7-6} = 0b00; // imm2 = '00'
2072 def : T2Pat<(int_arm_ssat GPR:$a, imm:$pos), (t2SSAT imm:$pos, GPR:$a, 0)>;
2073 def : T2Pat<(int_arm_usat GPR:$a, imm:$pos), (t2USAT imm:$pos, GPR:$a, 0)>;
2075 //===----------------------------------------------------------------------===//
2076 // Shift and rotate Instructions.
2079 defm t2LSL : T2I_sh_ir<0b00, "lsl", imm0_31,
2080 BinOpFrag<(shl node:$LHS, node:$RHS)>, "t2LSL">;
2081 defm t2LSR : T2I_sh_ir<0b01, "lsr", imm_sr,
2082 BinOpFrag<(srl node:$LHS, node:$RHS)>, "t2LSR">;
2083 defm t2ASR : T2I_sh_ir<0b10, "asr", imm_sr,
2084 BinOpFrag<(sra node:$LHS, node:$RHS)>, "t2ASR">;
2085 defm t2ROR : T2I_sh_ir<0b11, "ror", imm0_31,
2086 BinOpFrag<(rotr node:$LHS, node:$RHS)>, "t2ROR">;
2088 // (rotr x, (and y, 0x...1f)) ==> (ROR x, y)
2089 def : Pat<(rotr rGPR:$lhs, (and rGPR:$rhs, lo5AllOne)),
2090 (t2RORrr rGPR:$lhs, rGPR:$rhs)>;
2092 let Uses = [CPSR] in {
2093 def t2RRX : T2sTwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iMOVsi,
2094 "rrx", "\t$Rd, $Rm",
2095 [(set rGPR:$Rd, (ARMrrx rGPR:$Rm))]> {
2096 let Inst{31-27} = 0b11101;
2097 let Inst{26-25} = 0b01;
2098 let Inst{24-21} = 0b0010;
2099 let Inst{19-16} = 0b1111; // Rn
2100 let Inst{14-12} = 0b000;
2101 let Inst{7-4} = 0b0011;
2105 let isCodeGenOnly = 1, Defs = [CPSR] in {
2106 def t2MOVsrl_flag : T2TwoRegShiftImm<
2107 (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iMOVsi,
2108 "lsrs", ".w\t$Rd, $Rm, #1",
2109 [(set rGPR:$Rd, (ARMsrl_flag rGPR:$Rm))]> {
2110 let Inst{31-27} = 0b11101;
2111 let Inst{26-25} = 0b01;
2112 let Inst{24-21} = 0b0010;
2113 let Inst{20} = 1; // The S bit.
2114 let Inst{19-16} = 0b1111; // Rn
2115 let Inst{5-4} = 0b01; // Shift type.
2116 // Shift amount = Inst{14-12:7-6} = 1.
2117 let Inst{14-12} = 0b000;
2118 let Inst{7-6} = 0b01;
2120 def t2MOVsra_flag : T2TwoRegShiftImm<
2121 (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iMOVsi,
2122 "asrs", ".w\t$Rd, $Rm, #1",
2123 [(set rGPR:$Rd, (ARMsra_flag rGPR:$Rm))]> {
2124 let Inst{31-27} = 0b11101;
2125 let Inst{26-25} = 0b01;
2126 let Inst{24-21} = 0b0010;
2127 let Inst{20} = 1; // The S bit.
2128 let Inst{19-16} = 0b1111; // Rn
2129 let Inst{5-4} = 0b10; // Shift type.
2130 // Shift amount = Inst{14-12:7-6} = 1.
2131 let Inst{14-12} = 0b000;
2132 let Inst{7-6} = 0b01;
2136 //===----------------------------------------------------------------------===//
2137 // Bitwise Instructions.
2140 defm t2AND : T2I_bin_w_irs<0b0000, "and",
2141 IIC_iBITi, IIC_iBITr, IIC_iBITsi,
2142 BinOpFrag<(and node:$LHS, node:$RHS)>, "t2AND", 1>;
2143 defm t2ORR : T2I_bin_w_irs<0b0010, "orr",
2144 IIC_iBITi, IIC_iBITr, IIC_iBITsi,
2145 BinOpFrag<(or node:$LHS, node:$RHS)>, "t2ORR", 1>;
2146 defm t2EOR : T2I_bin_w_irs<0b0100, "eor",
2147 IIC_iBITi, IIC_iBITr, IIC_iBITsi,
2148 BinOpFrag<(xor node:$LHS, node:$RHS)>, "t2EOR", 1>;
2150 defm t2BIC : T2I_bin_w_irs<0b0001, "bic",
2151 IIC_iBITi, IIC_iBITr, IIC_iBITsi,
2152 BinOpFrag<(and node:$LHS, (not node:$RHS))>,
2155 class T2BitFI<dag oops, dag iops, InstrItinClass itin,
2156 string opc, string asm, list<dag> pattern>
2157 : T2I<oops, iops, itin, opc, asm, pattern> {
2162 let Inst{11-8} = Rd;
2163 let Inst{4-0} = msb{4-0};
2164 let Inst{14-12} = lsb{4-2};
2165 let Inst{7-6} = lsb{1-0};
2168 class T2TwoRegBitFI<dag oops, dag iops, InstrItinClass itin,
2169 string opc, string asm, list<dag> pattern>
2170 : T2BitFI<oops, iops, itin, opc, asm, pattern> {
2173 let Inst{19-16} = Rn;
2176 let Constraints = "$src = $Rd" in
2177 def t2BFC : T2BitFI<(outs rGPR:$Rd), (ins rGPR:$src, bf_inv_mask_imm:$imm),
2178 IIC_iUNAsi, "bfc", "\t$Rd, $imm",
2179 [(set rGPR:$Rd, (and rGPR:$src, bf_inv_mask_imm:$imm))]> {
2180 let Inst{31-27} = 0b11110;
2181 let Inst{26} = 0; // should be 0.
2183 let Inst{24-20} = 0b10110;
2184 let Inst{19-16} = 0b1111; // Rn
2186 let Inst{5} = 0; // should be 0.
2189 let msb{4-0} = imm{9-5};
2190 let lsb{4-0} = imm{4-0};
2193 def t2SBFX: T2TwoRegBitFI<
2194 (outs rGPR:$Rd), (ins rGPR:$Rn, imm0_31:$lsb, imm1_32:$msb),
2195 IIC_iUNAsi, "sbfx", "\t$Rd, $Rn, $lsb, $msb", []> {
2196 let Inst{31-27} = 0b11110;
2198 let Inst{24-20} = 0b10100;
2202 def t2UBFX: T2TwoRegBitFI<
2203 (outs rGPR:$Rd), (ins rGPR:$Rn, imm0_31:$lsb, imm1_32:$msb),
2204 IIC_iUNAsi, "ubfx", "\t$Rd, $Rn, $lsb, $msb", []> {
2205 let Inst{31-27} = 0b11110;
2207 let Inst{24-20} = 0b11100;
2211 // A8.6.18 BFI - Bitfield insert (Encoding T1)
2212 let Constraints = "$src = $Rd" in {
2213 def t2BFI : T2TwoRegBitFI<(outs rGPR:$Rd),
2214 (ins rGPR:$src, rGPR:$Rn, bf_inv_mask_imm:$imm),
2215 IIC_iBITi, "bfi", "\t$Rd, $Rn, $imm",
2216 [(set rGPR:$Rd, (ARMbfi rGPR:$src, rGPR:$Rn,
2217 bf_inv_mask_imm:$imm))]> {
2218 let Inst{31-27} = 0b11110;
2219 let Inst{26} = 0; // should be 0.
2221 let Inst{24-20} = 0b10110;
2223 let Inst{5} = 0; // should be 0.
2226 let msb{4-0} = imm{9-5};
2227 let lsb{4-0} = imm{4-0};
2231 defm t2ORN : T2I_bin_irs<0b0011, "orn",
2232 IIC_iBITi, IIC_iBITr, IIC_iBITsi,
2233 BinOpFrag<(or node:$LHS, (not node:$RHS))>,
2236 /// T2I_un_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a
2237 /// unary operation that produces a value. These are predicable and can be
2238 /// changed to modify CPSR.
2239 multiclass T2I_un_irs<bits<4> opcod, string opc,
2240 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
2241 PatFrag opnode, bit Cheap = 0, bit ReMat = 0> {
2243 def i : T2sOneRegImm<(outs rGPR:$Rd), (ins t2_so_imm:$imm), iii,
2245 [(set rGPR:$Rd, (opnode t2_so_imm:$imm))]> {
2246 let isAsCheapAsAMove = Cheap;
2247 let isReMaterializable = ReMat;
2248 let Inst{31-27} = 0b11110;
2250 let Inst{24-21} = opcod;
2251 let Inst{19-16} = 0b1111; // Rn
2255 def r : T2sTwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm), iir,
2256 opc, ".w\t$Rd, $Rm",
2257 [(set rGPR:$Rd, (opnode rGPR:$Rm))]> {
2258 let Inst{31-27} = 0b11101;
2259 let Inst{26-25} = 0b01;
2260 let Inst{24-21} = opcod;
2261 let Inst{19-16} = 0b1111; // Rn
2262 let Inst{14-12} = 0b000; // imm3
2263 let Inst{7-6} = 0b00; // imm2
2264 let Inst{5-4} = 0b00; // type
2267 def s : T2sOneRegShiftedReg<(outs rGPR:$Rd), (ins t2_so_reg:$ShiftedRm), iis,
2268 opc, ".w\t$Rd, $ShiftedRm",
2269 [(set rGPR:$Rd, (opnode t2_so_reg:$ShiftedRm))]> {
2270 let Inst{31-27} = 0b11101;
2271 let Inst{26-25} = 0b01;
2272 let Inst{24-21} = opcod;
2273 let Inst{19-16} = 0b1111; // Rn
2277 // Prefer over of t2EORri ra, rb, -1 because mvn has 16-bit version
2278 let AddedComplexity = 1 in
2279 defm t2MVN : T2I_un_irs <0b0011, "mvn",
2280 IIC_iMVNi, IIC_iMVNr, IIC_iMVNsi,
2281 UnOpFrag<(not node:$Src)>, 1, 1>;
2283 let AddedComplexity = 1 in
2284 def : T2Pat<(and rGPR:$src, t2_so_imm_not:$imm),
2285 (t2BICri rGPR:$src, t2_so_imm_not:$imm)>;
2287 // FIXME: Disable this pattern on Darwin to workaround an assembler bug.
2288 def : T2Pat<(or rGPR:$src, t2_so_imm_not:$imm),
2289 (t2ORNri rGPR:$src, t2_so_imm_not:$imm)>,
2290 Requires<[IsThumb2]>;
2292 def : T2Pat<(t2_so_imm_not:$src),
2293 (t2MVNi t2_so_imm_not:$src)>;
2295 //===----------------------------------------------------------------------===//
2296 // Multiply Instructions.
2298 let isCommutable = 1 in
2299 def t2MUL: T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL32,
2300 "mul", "\t$Rd, $Rn, $Rm",
2301 [(set rGPR:$Rd, (mul rGPR:$Rn, rGPR:$Rm))]> {
2302 let Inst{31-27} = 0b11111;
2303 let Inst{26-23} = 0b0110;
2304 let Inst{22-20} = 0b000;
2305 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2306 let Inst{7-4} = 0b0000; // Multiply
2309 def t2MLA: T2FourReg<
2310 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2311 "mla", "\t$Rd, $Rn, $Rm, $Ra",
2312 [(set rGPR:$Rd, (add (mul rGPR:$Rn, rGPR:$Rm), rGPR:$Ra))]> {
2313 let Inst{31-27} = 0b11111;
2314 let Inst{26-23} = 0b0110;
2315 let Inst{22-20} = 0b000;
2316 let Inst{7-4} = 0b0000; // Multiply
2319 def t2MLS: T2FourReg<
2320 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2321 "mls", "\t$Rd, $Rn, $Rm, $Ra",
2322 [(set rGPR:$Rd, (sub rGPR:$Ra, (mul rGPR:$Rn, rGPR:$Rm)))]> {
2323 let Inst{31-27} = 0b11111;
2324 let Inst{26-23} = 0b0110;
2325 let Inst{22-20} = 0b000;
2326 let Inst{7-4} = 0b0001; // Multiply and Subtract
2329 // Extra precision multiplies with low / high results
2330 let neverHasSideEffects = 1 in {
2331 let isCommutable = 1 in {
2332 def t2SMULL : T2MulLong<0b000, 0b0000,
2333 (outs rGPR:$RdLo, rGPR:$RdHi),
2334 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL64,
2335 "smull", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2337 def t2UMULL : T2MulLong<0b010, 0b0000,
2338 (outs rGPR:$RdLo, rGPR:$RdHi),
2339 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL64,
2340 "umull", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2343 // Multiply + accumulate
2344 def t2SMLAL : T2MulLong<0b100, 0b0000,
2345 (outs rGPR:$RdLo, rGPR:$RdHi),
2346 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMAC64,
2347 "smlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2349 def t2UMLAL : T2MulLong<0b110, 0b0000,
2350 (outs rGPR:$RdLo, rGPR:$RdHi),
2351 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMAC64,
2352 "umlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2354 def t2UMAAL : T2MulLong<0b110, 0b0110,
2355 (outs rGPR:$RdLo, rGPR:$RdHi),
2356 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMAC64,
2357 "umaal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
2358 Requires<[IsThumb2, HasThumb2DSP]>;
2359 } // neverHasSideEffects
2361 // Rounding variants of the below included for disassembly only
2363 // Most significant word multiply
2364 def t2SMMUL : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL32,
2365 "smmul", "\t$Rd, $Rn, $Rm",
2366 [(set rGPR:$Rd, (mulhs rGPR:$Rn, rGPR:$Rm))]>,
2367 Requires<[IsThumb2, HasThumb2DSP]> {
2368 let Inst{31-27} = 0b11111;
2369 let Inst{26-23} = 0b0110;
2370 let Inst{22-20} = 0b101;
2371 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2372 let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
2375 def t2SMMULR : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL32,
2376 "smmulr", "\t$Rd, $Rn, $Rm", []>,
2377 Requires<[IsThumb2, HasThumb2DSP]> {
2378 let Inst{31-27} = 0b11111;
2379 let Inst{26-23} = 0b0110;
2380 let Inst{22-20} = 0b101;
2381 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2382 let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1)
2385 def t2SMMLA : T2FourReg<
2386 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2387 "smmla", "\t$Rd, $Rn, $Rm, $Ra",
2388 [(set rGPR:$Rd, (add (mulhs rGPR:$Rm, rGPR:$Rn), rGPR:$Ra))]>,
2389 Requires<[IsThumb2, HasThumb2DSP]> {
2390 let Inst{31-27} = 0b11111;
2391 let Inst{26-23} = 0b0110;
2392 let Inst{22-20} = 0b101;
2393 let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
2396 def t2SMMLAR: T2FourReg<
2397 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2398 "smmlar", "\t$Rd, $Rn, $Rm, $Ra", []>,
2399 Requires<[IsThumb2, HasThumb2DSP]> {
2400 let Inst{31-27} = 0b11111;
2401 let Inst{26-23} = 0b0110;
2402 let Inst{22-20} = 0b101;
2403 let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1)
2406 def t2SMMLS: T2FourReg<
2407 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2408 "smmls", "\t$Rd, $Rn, $Rm, $Ra",
2409 [(set rGPR:$Rd, (sub rGPR:$Ra, (mulhs rGPR:$Rn, rGPR:$Rm)))]>,
2410 Requires<[IsThumb2, HasThumb2DSP]> {
2411 let Inst{31-27} = 0b11111;
2412 let Inst{26-23} = 0b0110;
2413 let Inst{22-20} = 0b110;
2414 let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
2417 def t2SMMLSR:T2FourReg<
2418 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2419 "smmlsr", "\t$Rd, $Rn, $Rm, $Ra", []>,
2420 Requires<[IsThumb2, HasThumb2DSP]> {
2421 let Inst{31-27} = 0b11111;
2422 let Inst{26-23} = 0b0110;
2423 let Inst{22-20} = 0b110;
2424 let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1)
2427 multiclass T2I_smul<string opc, PatFrag opnode> {
2428 def BB : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2429 !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm",
2430 [(set rGPR:$Rd, (opnode (sext_inreg rGPR:$Rn, i16),
2431 (sext_inreg rGPR:$Rm, i16)))]>,
2432 Requires<[IsThumb2, HasThumb2DSP]> {
2433 let Inst{31-27} = 0b11111;
2434 let Inst{26-23} = 0b0110;
2435 let Inst{22-20} = 0b001;
2436 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2437 let Inst{7-6} = 0b00;
2438 let Inst{5-4} = 0b00;
2441 def BT : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2442 !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm",
2443 [(set rGPR:$Rd, (opnode (sext_inreg rGPR:$Rn, i16),
2444 (sra rGPR:$Rm, (i32 16))))]>,
2445 Requires<[IsThumb2, HasThumb2DSP]> {
2446 let Inst{31-27} = 0b11111;
2447 let Inst{26-23} = 0b0110;
2448 let Inst{22-20} = 0b001;
2449 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2450 let Inst{7-6} = 0b00;
2451 let Inst{5-4} = 0b01;
2454 def TB : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2455 !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm",
2456 [(set rGPR:$Rd, (opnode (sra rGPR:$Rn, (i32 16)),
2457 (sext_inreg rGPR:$Rm, i16)))]>,
2458 Requires<[IsThumb2, HasThumb2DSP]> {
2459 let Inst{31-27} = 0b11111;
2460 let Inst{26-23} = 0b0110;
2461 let Inst{22-20} = 0b001;
2462 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2463 let Inst{7-6} = 0b00;
2464 let Inst{5-4} = 0b10;
2467 def TT : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2468 !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm",
2469 [(set rGPR:$Rd, (opnode (sra rGPR:$Rn, (i32 16)),
2470 (sra rGPR:$Rm, (i32 16))))]>,
2471 Requires<[IsThumb2, HasThumb2DSP]> {
2472 let Inst{31-27} = 0b11111;
2473 let Inst{26-23} = 0b0110;
2474 let Inst{22-20} = 0b001;
2475 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2476 let Inst{7-6} = 0b00;
2477 let Inst{5-4} = 0b11;
2480 def WB : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2481 !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm",
2482 [(set rGPR:$Rd, (sra (opnode rGPR:$Rn,
2483 (sext_inreg rGPR:$Rm, i16)), (i32 16)))]>,
2484 Requires<[IsThumb2, HasThumb2DSP]> {
2485 let Inst{31-27} = 0b11111;
2486 let Inst{26-23} = 0b0110;
2487 let Inst{22-20} = 0b011;
2488 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2489 let Inst{7-6} = 0b00;
2490 let Inst{5-4} = 0b00;
2493 def WT : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2494 !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm",
2495 [(set rGPR:$Rd, (sra (opnode rGPR:$Rn,
2496 (sra rGPR:$Rm, (i32 16))), (i32 16)))]>,
2497 Requires<[IsThumb2, HasThumb2DSP]> {
2498 let Inst{31-27} = 0b11111;
2499 let Inst{26-23} = 0b0110;
2500 let Inst{22-20} = 0b011;
2501 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2502 let Inst{7-6} = 0b00;
2503 let Inst{5-4} = 0b01;
2508 multiclass T2I_smla<string opc, PatFrag opnode> {
2510 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2511 !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm, $Ra",
2512 [(set rGPR:$Rd, (add rGPR:$Ra,
2513 (opnode (sext_inreg rGPR:$Rn, i16),
2514 (sext_inreg rGPR:$Rm, i16))))]>,
2515 Requires<[IsThumb2, HasThumb2DSP]> {
2516 let Inst{31-27} = 0b11111;
2517 let Inst{26-23} = 0b0110;
2518 let Inst{22-20} = 0b001;
2519 let Inst{7-6} = 0b00;
2520 let Inst{5-4} = 0b00;
2524 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2525 !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm, $Ra",
2526 [(set rGPR:$Rd, (add rGPR:$Ra, (opnode (sext_inreg rGPR:$Rn, i16),
2527 (sra rGPR:$Rm, (i32 16)))))]>,
2528 Requires<[IsThumb2, HasThumb2DSP]> {
2529 let Inst{31-27} = 0b11111;
2530 let Inst{26-23} = 0b0110;
2531 let Inst{22-20} = 0b001;
2532 let Inst{7-6} = 0b00;
2533 let Inst{5-4} = 0b01;
2537 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2538 !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm, $Ra",
2539 [(set rGPR:$Rd, (add rGPR:$Ra, (opnode (sra rGPR:$Rn, (i32 16)),
2540 (sext_inreg rGPR:$Rm, i16))))]>,
2541 Requires<[IsThumb2, HasThumb2DSP]> {
2542 let Inst{31-27} = 0b11111;
2543 let Inst{26-23} = 0b0110;
2544 let Inst{22-20} = 0b001;
2545 let Inst{7-6} = 0b00;
2546 let Inst{5-4} = 0b10;
2550 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2551 !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm, $Ra",
2552 [(set rGPR:$Rd, (add rGPR:$Ra, (opnode (sra rGPR:$Rn, (i32 16)),
2553 (sra rGPR:$Rm, (i32 16)))))]>,
2554 Requires<[IsThumb2, HasThumb2DSP]> {
2555 let Inst{31-27} = 0b11111;
2556 let Inst{26-23} = 0b0110;
2557 let Inst{22-20} = 0b001;
2558 let Inst{7-6} = 0b00;
2559 let Inst{5-4} = 0b11;
2563 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2564 !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm, $Ra",
2565 [(set rGPR:$Rd, (add rGPR:$Ra, (sra (opnode rGPR:$Rn,
2566 (sext_inreg rGPR:$Rm, i16)), (i32 16))))]>,
2567 Requires<[IsThumb2, HasThumb2DSP]> {
2568 let Inst{31-27} = 0b11111;
2569 let Inst{26-23} = 0b0110;
2570 let Inst{22-20} = 0b011;
2571 let Inst{7-6} = 0b00;
2572 let Inst{5-4} = 0b00;
2576 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2577 !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm, $Ra",
2578 [(set rGPR:$Rd, (add rGPR:$Ra, (sra (opnode rGPR:$Rn,
2579 (sra rGPR:$Rm, (i32 16))), (i32 16))))]>,
2580 Requires<[IsThumb2, HasThumb2DSP]> {
2581 let Inst{31-27} = 0b11111;
2582 let Inst{26-23} = 0b0110;
2583 let Inst{22-20} = 0b011;
2584 let Inst{7-6} = 0b00;
2585 let Inst{5-4} = 0b01;
2589 defm t2SMUL : T2I_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
2590 defm t2SMLA : T2I_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
2592 // Halfword multiple accumulate long: SMLAL<x><y>
2593 def t2SMLALBB : T2FourReg_mac<1, 0b100, 0b1000, (outs rGPR:$Ra,rGPR:$Rd),
2594 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlalbb", "\t$Ra, $Rd, $Rn, $Rm",
2595 [/* For disassembly only; pattern left blank */]>,
2596 Requires<[IsThumb2, HasThumb2DSP]>;
2597 def t2SMLALBT : T2FourReg_mac<1, 0b100, 0b1001, (outs rGPR:$Ra,rGPR:$Rd),
2598 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlalbt", "\t$Ra, $Rd, $Rn, $Rm",
2599 [/* For disassembly only; pattern left blank */]>,
2600 Requires<[IsThumb2, HasThumb2DSP]>;
2601 def t2SMLALTB : T2FourReg_mac<1, 0b100, 0b1010, (outs rGPR:$Ra,rGPR:$Rd),
2602 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlaltb", "\t$Ra, $Rd, $Rn, $Rm",
2603 [/* For disassembly only; pattern left blank */]>,
2604 Requires<[IsThumb2, HasThumb2DSP]>;
2605 def t2SMLALTT : T2FourReg_mac<1, 0b100, 0b1011, (outs rGPR:$Ra,rGPR:$Rd),
2606 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlaltt", "\t$Ra, $Rd, $Rn, $Rm",
2607 [/* For disassembly only; pattern left blank */]>,
2608 Requires<[IsThumb2, HasThumb2DSP]>;
2610 // Dual halfword multiple: SMUAD, SMUSD, SMLAD, SMLSD, SMLALD, SMLSLD
2611 def t2SMUAD: T2ThreeReg_mac<
2612 0, 0b010, 0b0000, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
2613 IIC_iMAC32, "smuad", "\t$Rd, $Rn, $Rm", []>,
2614 Requires<[IsThumb2, HasThumb2DSP]> {
2615 let Inst{15-12} = 0b1111;
2617 def t2SMUADX:T2ThreeReg_mac<
2618 0, 0b010, 0b0001, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
2619 IIC_iMAC32, "smuadx", "\t$Rd, $Rn, $Rm", []>,
2620 Requires<[IsThumb2, HasThumb2DSP]> {
2621 let Inst{15-12} = 0b1111;
2623 def t2SMUSD: T2ThreeReg_mac<
2624 0, 0b100, 0b0000, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
2625 IIC_iMAC32, "smusd", "\t$Rd, $Rn, $Rm", []>,
2626 Requires<[IsThumb2, HasThumb2DSP]> {
2627 let Inst{15-12} = 0b1111;
2629 def t2SMUSDX:T2ThreeReg_mac<
2630 0, 0b100, 0b0001, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
2631 IIC_iMAC32, "smusdx", "\t$Rd, $Rn, $Rm", []>,
2632 Requires<[IsThumb2, HasThumb2DSP]> {
2633 let Inst{15-12} = 0b1111;
2635 def t2SMLAD : T2FourReg_mac<
2636 0, 0b010, 0b0000, (outs rGPR:$Rd),
2637 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smlad",
2638 "\t$Rd, $Rn, $Rm, $Ra", []>,
2639 Requires<[IsThumb2, HasThumb2DSP]>;
2640 def t2SMLADX : T2FourReg_mac<
2641 0, 0b010, 0b0001, (outs rGPR:$Rd),
2642 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smladx",
2643 "\t$Rd, $Rn, $Rm, $Ra", []>,
2644 Requires<[IsThumb2, HasThumb2DSP]>;
2645 def t2SMLSD : T2FourReg_mac<0, 0b100, 0b0000, (outs rGPR:$Rd),
2646 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smlsd",
2647 "\t$Rd, $Rn, $Rm, $Ra", []>,
2648 Requires<[IsThumb2, HasThumb2DSP]>;
2649 def t2SMLSDX : T2FourReg_mac<0, 0b100, 0b0001, (outs rGPR:$Rd),
2650 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smlsdx",
2651 "\t$Rd, $Rn, $Rm, $Ra", []>,
2652 Requires<[IsThumb2, HasThumb2DSP]>;
2653 def t2SMLALD : T2FourReg_mac<1, 0b100, 0b1100, (outs rGPR:$Ra,rGPR:$Rd),
2654 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMAC64, "smlald",
2655 "\t$Ra, $Rd, $Rn, $Rm", []>,
2656 Requires<[IsThumb2, HasThumb2DSP]>;
2657 def t2SMLALDX : T2FourReg_mac<1, 0b100, 0b1101, (outs rGPR:$Ra,rGPR:$Rd),
2658 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlaldx",
2659 "\t$Ra, $Rd, $Rn, $Rm", []>,
2660 Requires<[IsThumb2, HasThumb2DSP]>;
2661 def t2SMLSLD : T2FourReg_mac<1, 0b101, 0b1100, (outs rGPR:$Ra,rGPR:$Rd),
2662 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlsld",
2663 "\t$Ra, $Rd, $Rn, $Rm", []>,
2664 Requires<[IsThumb2, HasThumb2DSP]>;
2665 def t2SMLSLDX : T2FourReg_mac<1, 0b101, 0b1101, (outs rGPR:$Ra,rGPR:$Rd),
2666 (ins rGPR:$Rm,rGPR:$Rn), IIC_iMAC64, "smlsldx",
2667 "\t$Ra, $Rd, $Rn, $Rm", []>,
2668 Requires<[IsThumb2, HasThumb2DSP]>;
2670 //===----------------------------------------------------------------------===//
2671 // Division Instructions.
2672 // Signed and unsigned division on v7-M
2674 def t2SDIV : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUi,
2675 "sdiv", "\t$Rd, $Rn, $Rm",
2676 [(set rGPR:$Rd, (sdiv rGPR:$Rn, rGPR:$Rm))]>,
2677 Requires<[HasDivide, IsThumb2]> {
2678 let Inst{31-27} = 0b11111;
2679 let Inst{26-21} = 0b011100;
2681 let Inst{15-12} = 0b1111;
2682 let Inst{7-4} = 0b1111;
2685 def t2UDIV : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUi,
2686 "udiv", "\t$Rd, $Rn, $Rm",
2687 [(set rGPR:$Rd, (udiv rGPR:$Rn, rGPR:$Rm))]>,
2688 Requires<[HasDivide, IsThumb2]> {
2689 let Inst{31-27} = 0b11111;
2690 let Inst{26-21} = 0b011101;
2692 let Inst{15-12} = 0b1111;
2693 let Inst{7-4} = 0b1111;
2696 //===----------------------------------------------------------------------===//
2697 // Misc. Arithmetic Instructions.
2700 class T2I_misc<bits<2> op1, bits<2> op2, dag oops, dag iops,
2701 InstrItinClass itin, string opc, string asm, list<dag> pattern>
2702 : T2ThreeReg<oops, iops, itin, opc, asm, pattern> {
2703 let Inst{31-27} = 0b11111;
2704 let Inst{26-22} = 0b01010;
2705 let Inst{21-20} = op1;
2706 let Inst{15-12} = 0b1111;
2707 let Inst{7-6} = 0b10;
2708 let Inst{5-4} = op2;
2712 def t2CLZ : T2I_misc<0b11, 0b00, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2713 "clz", "\t$Rd, $Rm", [(set rGPR:$Rd, (ctlz rGPR:$Rm))]>;
2715 def t2RBIT : T2I_misc<0b01, 0b10, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2716 "rbit", "\t$Rd, $Rm",
2717 [(set rGPR:$Rd, (ARMrbit rGPR:$Rm))]>;
2719 def t2REV : T2I_misc<0b01, 0b00, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2720 "rev", ".w\t$Rd, $Rm", [(set rGPR:$Rd, (bswap rGPR:$Rm))]>;
2722 def t2REV16 : T2I_misc<0b01, 0b01, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2723 "rev16", ".w\t$Rd, $Rm",
2724 [(set rGPR:$Rd, (rotr (bswap rGPR:$Rm), (i32 16)))]>;
2726 def t2REVSH : T2I_misc<0b01, 0b11, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2727 "revsh", ".w\t$Rd, $Rm",
2728 [(set rGPR:$Rd, (sra (bswap rGPR:$Rm), (i32 16)))]>;
2730 def : T2Pat<(or (sra (shl rGPR:$Rm, (i32 24)), (i32 16)),
2731 (and (srl rGPR:$Rm, (i32 8)), 0xFF)),
2732 (t2REVSH rGPR:$Rm)>;
2734 def t2PKHBT : T2ThreeReg<
2735 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, pkh_lsl_amt:$sh),
2736 IIC_iBITsi, "pkhbt", "\t$Rd, $Rn, $Rm$sh",
2737 [(set rGPR:$Rd, (or (and rGPR:$Rn, 0xFFFF),
2738 (and (shl rGPR:$Rm, pkh_lsl_amt:$sh),
2740 Requires<[HasT2ExtractPack, IsThumb2]> {
2741 let Inst{31-27} = 0b11101;
2742 let Inst{26-25} = 0b01;
2743 let Inst{24-20} = 0b01100;
2744 let Inst{5} = 0; // BT form
2748 let Inst{14-12} = sh{4-2};
2749 let Inst{7-6} = sh{1-0};
2752 // Alternate cases for PKHBT where identities eliminate some nodes.
2753 def : T2Pat<(or (and rGPR:$src1, 0xFFFF), (and rGPR:$src2, 0xFFFF0000)),
2754 (t2PKHBT rGPR:$src1, rGPR:$src2, 0)>,
2755 Requires<[HasT2ExtractPack, IsThumb2]>;
2756 def : T2Pat<(or (and rGPR:$src1, 0xFFFF), (shl rGPR:$src2, imm16_31:$sh)),
2757 (t2PKHBT rGPR:$src1, rGPR:$src2, imm16_31:$sh)>,
2758 Requires<[HasT2ExtractPack, IsThumb2]>;
2760 // Note: Shifts of 1-15 bits will be transformed to srl instead of sra and
2761 // will match the pattern below.
2762 def t2PKHTB : T2ThreeReg<
2763 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, pkh_asr_amt:$sh),
2764 IIC_iBITsi, "pkhtb", "\t$Rd, $Rn, $Rm$sh",
2765 [(set rGPR:$Rd, (or (and rGPR:$Rn, 0xFFFF0000),
2766 (and (sra rGPR:$Rm, pkh_asr_amt:$sh),
2768 Requires<[HasT2ExtractPack, IsThumb2]> {
2769 let Inst{31-27} = 0b11101;
2770 let Inst{26-25} = 0b01;
2771 let Inst{24-20} = 0b01100;
2772 let Inst{5} = 1; // TB form
2776 let Inst{14-12} = sh{4-2};
2777 let Inst{7-6} = sh{1-0};
2780 // Alternate cases for PKHTB where identities eliminate some nodes. Note that
2781 // a shift amount of 0 is *not legal* here, it is PKHBT instead.
2782 def : T2Pat<(or (and rGPR:$src1, 0xFFFF0000), (srl rGPR:$src2, imm16_31:$sh)),
2783 (t2PKHTB rGPR:$src1, rGPR:$src2, imm16_31:$sh)>,
2784 Requires<[HasT2ExtractPack, IsThumb2]>;
2785 def : T2Pat<(or (and rGPR:$src1, 0xFFFF0000),
2786 (and (srl rGPR:$src2, imm1_15:$sh), 0xFFFF)),
2787 (t2PKHTB rGPR:$src1, rGPR:$src2, imm1_15:$sh)>,
2788 Requires<[HasT2ExtractPack, IsThumb2]>;
2790 //===----------------------------------------------------------------------===//
2791 // Comparison Instructions...
2793 defm t2CMP : T2I_cmp_irs<0b1101, "cmp",
2794 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsi,
2795 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>, "t2CMP">;
2797 def : T2Pat<(ARMcmpZ GPRnopc:$lhs, t2_so_imm:$imm),
2798 (t2CMPri GPRnopc:$lhs, t2_so_imm:$imm)>;
2799 def : T2Pat<(ARMcmpZ GPRnopc:$lhs, rGPR:$rhs),
2800 (t2CMPrr GPRnopc:$lhs, rGPR:$rhs)>;
2801 def : T2Pat<(ARMcmpZ GPRnopc:$lhs, t2_so_reg:$rhs),
2802 (t2CMPrs GPRnopc:$lhs, t2_so_reg:$rhs)>;
2804 //FIXME: Disable CMN, as CCodes are backwards from compare expectations
2805 // Compare-to-zero still works out, just not the relationals
2806 //defm t2CMN : T2I_cmp_irs<0b1000, "cmn",
2807 // BinOpFrag<(ARMcmp node:$LHS,(ineg node:$RHS))>>;
2808 defm t2CMNz : T2I_cmp_irs<0b1000, "cmn",
2809 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsi,
2810 BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>,
2813 //def : T2Pat<(ARMcmp GPR:$src, t2_so_imm_neg:$imm),
2814 // (t2CMNri GPR:$src, t2_so_imm_neg:$imm)>;
2816 def : T2Pat<(ARMcmpZ GPRnopc:$src, t2_so_imm_neg:$imm),
2817 (t2CMNzri GPRnopc:$src, t2_so_imm_neg:$imm)>;
2819 defm t2TST : T2I_cmp_irs<0b0000, "tst",
2820 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsi,
2821 BinOpFrag<(ARMcmpZ (and_su node:$LHS, node:$RHS), 0)>,
2823 defm t2TEQ : T2I_cmp_irs<0b0100, "teq",
2824 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsi,
2825 BinOpFrag<(ARMcmpZ (xor_su node:$LHS, node:$RHS), 0)>,
2828 // Conditional moves
2829 // FIXME: should be able to write a pattern for ARMcmov, but can't use
2830 // a two-value operand where a dag node expects two operands. :(
2831 let neverHasSideEffects = 1 in {
2832 def t2MOVCCr : t2PseudoInst<(outs rGPR:$Rd),
2833 (ins rGPR:$false, rGPR:$Rm, pred:$p),
2835 [/*(set rGPR:$Rd, (ARMcmov rGPR:$false, rGPR:$Rm, imm:$cc, CCR:$ccr))*/]>,
2836 RegConstraint<"$false = $Rd">;
2838 let isMoveImm = 1 in
2839 def t2MOVCCi : t2PseudoInst<(outs rGPR:$Rd),
2840 (ins rGPR:$false, t2_so_imm:$imm, pred:$p),
2842 [/*(set rGPR:$Rd,(ARMcmov rGPR:$false,t2_so_imm:$imm, imm:$cc, CCR:$ccr))*/]>,
2843 RegConstraint<"$false = $Rd">;
2845 // FIXME: Pseudo-ize these. For now, just mark codegen only.
2846 let isCodeGenOnly = 1 in {
2847 let isMoveImm = 1 in
2848 def t2MOVCCi16 : T2I<(outs rGPR:$Rd), (ins rGPR:$false, imm0_65535_expr:$imm),
2850 "movw", "\t$Rd, $imm", []>,
2851 RegConstraint<"$false = $Rd"> {
2852 let Inst{31-27} = 0b11110;
2854 let Inst{24-21} = 0b0010;
2855 let Inst{20} = 0; // The S bit.
2861 let Inst{11-8} = Rd;
2862 let Inst{19-16} = imm{15-12};
2863 let Inst{26} = imm{11};
2864 let Inst{14-12} = imm{10-8};
2865 let Inst{7-0} = imm{7-0};
2868 let isMoveImm = 1 in
2869 def t2MOVCCi32imm : PseudoInst<(outs rGPR:$dst),
2870 (ins rGPR:$false, i32imm:$src, pred:$p),
2871 IIC_iCMOVix2, []>, RegConstraint<"$false = $dst">;
2873 let isMoveImm = 1 in
2874 def t2MVNCCi : T2OneRegImm<(outs rGPR:$Rd), (ins rGPR:$false, t2_so_imm:$imm),
2875 IIC_iCMOVi, "mvn", ".w\t$Rd, $imm",
2876 [/*(set rGPR:$Rd,(ARMcmov rGPR:$false,t2_so_imm_not:$imm,
2877 imm:$cc, CCR:$ccr))*/]>,
2878 RegConstraint<"$false = $Rd"> {
2879 let Inst{31-27} = 0b11110;
2881 let Inst{24-21} = 0b0011;
2882 let Inst{20} = 0; // The S bit.
2883 let Inst{19-16} = 0b1111; // Rn
2887 class T2I_movcc_sh<bits<2> opcod, dag oops, dag iops, InstrItinClass itin,
2888 string opc, string asm, list<dag> pattern>
2889 : T2TwoRegShiftImm<oops, iops, itin, opc, asm, pattern> {
2890 let Inst{31-27} = 0b11101;
2891 let Inst{26-25} = 0b01;
2892 let Inst{24-21} = 0b0010;
2893 let Inst{20} = 0; // The S bit.
2894 let Inst{19-16} = 0b1111; // Rn
2895 let Inst{5-4} = opcod; // Shift type.
2897 def t2MOVCClsl : T2I_movcc_sh<0b00, (outs rGPR:$Rd),
2898 (ins rGPR:$false, rGPR:$Rm, i32imm:$imm),
2899 IIC_iCMOVsi, "lsl", ".w\t$Rd, $Rm, $imm", []>,
2900 RegConstraint<"$false = $Rd">;
2901 def t2MOVCClsr : T2I_movcc_sh<0b01, (outs rGPR:$Rd),
2902 (ins rGPR:$false, rGPR:$Rm, i32imm:$imm),
2903 IIC_iCMOVsi, "lsr", ".w\t$Rd, $Rm, $imm", []>,
2904 RegConstraint<"$false = $Rd">;
2905 def t2MOVCCasr : T2I_movcc_sh<0b10, (outs rGPR:$Rd),
2906 (ins rGPR:$false, rGPR:$Rm, i32imm:$imm),
2907 IIC_iCMOVsi, "asr", ".w\t$Rd, $Rm, $imm", []>,
2908 RegConstraint<"$false = $Rd">;
2909 def t2MOVCCror : T2I_movcc_sh<0b11, (outs rGPR:$Rd),
2910 (ins rGPR:$false, rGPR:$Rm, i32imm:$imm),
2911 IIC_iCMOVsi, "ror", ".w\t$Rd, $Rm, $imm", []>,
2912 RegConstraint<"$false = $Rd">;
2913 } // isCodeGenOnly = 1
2914 } // neverHasSideEffects
2916 //===----------------------------------------------------------------------===//
2917 // Atomic operations intrinsics
2920 // memory barriers protect the atomic sequences
2921 let hasSideEffects = 1 in {
2922 def t2DMB : AInoP<(outs), (ins memb_opt:$opt), ThumbFrm, NoItinerary,
2923 "dmb", "\t$opt", [(ARMMemBarrier (i32 imm:$opt))]>,
2924 Requires<[IsThumb, HasDB]> {
2926 let Inst{31-4} = 0xf3bf8f5;
2927 let Inst{3-0} = opt;
2931 def t2DSB : AInoP<(outs), (ins memb_opt:$opt), ThumbFrm, NoItinerary,
2932 "dsb", "\t$opt", []>,
2933 Requires<[IsThumb, HasDB]> {
2935 let Inst{31-4} = 0xf3bf8f4;
2936 let Inst{3-0} = opt;
2939 def t2ISB : AInoP<(outs), (ins memb_opt:$opt), ThumbFrm, NoItinerary,
2941 []>, Requires<[IsThumb2, HasDB]> {
2943 let Inst{31-4} = 0xf3bf8f6;
2944 let Inst{3-0} = opt;
2947 class T2I_ldrex<bits<2> opcod, dag oops, dag iops, AddrMode am, int sz,
2948 InstrItinClass itin, string opc, string asm, string cstr,
2949 list<dag> pattern, bits<4> rt2 = 0b1111>
2950 : Thumb2I<oops, iops, am, sz, itin, opc, asm, cstr, pattern> {
2951 let Inst{31-27} = 0b11101;
2952 let Inst{26-20} = 0b0001101;
2953 let Inst{11-8} = rt2;
2954 let Inst{7-6} = 0b01;
2955 let Inst{5-4} = opcod;
2956 let Inst{3-0} = 0b1111;
2960 let Inst{19-16} = addr;
2961 let Inst{15-12} = Rt;
2963 class T2I_strex<bits<2> opcod, dag oops, dag iops, AddrMode am, int sz,
2964 InstrItinClass itin, string opc, string asm, string cstr,
2965 list<dag> pattern, bits<4> rt2 = 0b1111>
2966 : Thumb2I<oops, iops, am, sz, itin, opc, asm, cstr, pattern> {
2967 let Inst{31-27} = 0b11101;
2968 let Inst{26-20} = 0b0001100;
2969 let Inst{11-8} = rt2;
2970 let Inst{7-6} = 0b01;
2971 let Inst{5-4} = opcod;
2977 let Inst{19-16} = addr;
2978 let Inst{15-12} = Rt;
2981 let mayLoad = 1 in {
2982 def t2LDREXB : T2I_ldrex<0b00, (outs rGPR:$Rt), (ins addr_offset_none:$addr),
2983 AddrModeNone, 4, NoItinerary,
2984 "ldrexb", "\t$Rt, $addr", "", []>;
2985 def t2LDREXH : T2I_ldrex<0b01, (outs rGPR:$Rt), (ins addr_offset_none:$addr),
2986 AddrModeNone, 4, NoItinerary,
2987 "ldrexh", "\t$Rt, $addr", "", []>;
2988 def t2LDREX : Thumb2I<(outs rGPR:$Rt), (ins t2addrmode_imm0_1020s4:$addr),
2989 AddrModeNone, 4, NoItinerary,
2990 "ldrex", "\t$Rt, $addr", "", []> {
2993 let Inst{31-27} = 0b11101;
2994 let Inst{26-20} = 0b0000101;
2995 let Inst{19-16} = addr{11-8};
2996 let Inst{15-12} = Rt;
2997 let Inst{11-8} = 0b1111;
2998 let Inst{7-0} = addr{7-0};
3000 let hasExtraDefRegAllocReq = 1 in
3001 def t2LDREXD : T2I_ldrex<0b11, (outs rGPR:$Rt, rGPR:$Rt2),
3002 (ins addr_offset_none:$addr),
3003 AddrModeNone, 4, NoItinerary,
3004 "ldrexd", "\t$Rt, $Rt2, $addr", "",
3007 let Inst{11-8} = Rt2;
3011 let mayStore = 1, Constraints = "@earlyclobber $Rd" in {
3012 def t2STREXB : T2I_strex<0b00, (outs rGPR:$Rd),
3013 (ins rGPR:$Rt, addr_offset_none:$addr),
3014 AddrModeNone, 4, NoItinerary,
3015 "strexb", "\t$Rd, $Rt, $addr", "", []>;
3016 def t2STREXH : T2I_strex<0b01, (outs rGPR:$Rd),
3017 (ins rGPR:$Rt, addr_offset_none:$addr),
3018 AddrModeNone, 4, NoItinerary,
3019 "strexh", "\t$Rd, $Rt, $addr", "", []>;
3020 def t2STREX : Thumb2I<(outs rGPR:$Rd), (ins rGPR:$Rt,
3021 t2addrmode_imm0_1020s4:$addr),
3022 AddrModeNone, 4, NoItinerary,
3023 "strex", "\t$Rd, $Rt, $addr", "",
3028 let Inst{31-27} = 0b11101;
3029 let Inst{26-20} = 0b0000100;
3030 let Inst{19-16} = addr{11-8};
3031 let Inst{15-12} = Rt;
3032 let Inst{11-8} = Rd;
3033 let Inst{7-0} = addr{7-0};
3037 let hasExtraSrcRegAllocReq = 1, Constraints = "@earlyclobber $Rd" in
3038 def t2STREXD : T2I_strex<0b11, (outs rGPR:$Rd),
3039 (ins rGPR:$Rt, rGPR:$Rt2, addr_offset_none:$addr),
3040 AddrModeNone, 4, NoItinerary,
3041 "strexd", "\t$Rd, $Rt, $Rt2, $addr", "", [],
3044 let Inst{11-8} = Rt2;
3047 def t2CLREX : T2I<(outs), (ins), NoItinerary, "clrex", "", []>,
3048 Requires<[IsThumb2, HasV7]> {
3049 let Inst{31-16} = 0xf3bf;
3050 let Inst{15-14} = 0b10;
3053 let Inst{11-8} = 0b1111;
3054 let Inst{7-4} = 0b0010;
3055 let Inst{3-0} = 0b1111;
3058 //===----------------------------------------------------------------------===//
3059 // SJLJ Exception handling intrinsics
3060 // eh_sjlj_setjmp() is an instruction sequence to store the return
3061 // address and save #0 in R0 for the non-longjmp case.
3062 // Since by its nature we may be coming from some other function to get
3063 // here, and we're using the stack frame for the containing function to
3064 // save/restore registers, we can't keep anything live in regs across
3065 // the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
3066 // when we get here from a longjmp(). We force everything out of registers
3067 // except for our own input by listing the relevant registers in Defs. By
3068 // doing so, we also cause the prologue/epilogue code to actively preserve
3069 // all of the callee-saved resgisters, which is exactly what we want.
3070 // $val is a scratch register for our use.
3072 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR,
3073 QQQQ0, QQQQ1, QQQQ2, QQQQ3 ],
3074 hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1 in {
3075 def t2Int_eh_sjlj_setjmp : Thumb2XI<(outs), (ins tGPR:$src, tGPR:$val),
3076 AddrModeNone, 0, NoItinerary, "", "",
3077 [(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>,
3078 Requires<[IsThumb2, HasVFP2]>;
3082 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR ],
3083 hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1 in {
3084 def t2Int_eh_sjlj_setjmp_nofp : Thumb2XI<(outs), (ins tGPR:$src, tGPR:$val),
3085 AddrModeNone, 0, NoItinerary, "", "",
3086 [(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>,
3087 Requires<[IsThumb2, NoVFP]>;
3091 //===----------------------------------------------------------------------===//
3092 // Control-Flow Instructions
3095 // FIXME: remove when we have a way to marking a MI with these properties.
3096 // FIXME: Should pc be an implicit operand like PICADD, etc?
3097 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
3098 hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in
3099 def t2LDMIA_RET: t2PseudoExpand<(outs GPR:$wb), (ins GPR:$Rn, pred:$p,
3100 reglist:$regs, variable_ops),
3101 4, IIC_iLoad_mBr, [],
3102 (t2LDMIA_UPD GPR:$wb, GPR:$Rn, pred:$p, reglist:$regs)>,
3103 RegConstraint<"$Rn = $wb">;
3105 let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
3106 let isPredicable = 1 in
3107 def t2B : T2I<(outs), (ins uncondbrtarget:$target), IIC_Br,
3109 [(br bb:$target)]> {
3110 let Inst{31-27} = 0b11110;
3111 let Inst{15-14} = 0b10;
3115 let Inst{26} = target{19};
3116 let Inst{11} = target{18};
3117 let Inst{13} = target{17};
3118 let Inst{21-16} = target{16-11};
3119 let Inst{10-0} = target{10-0};
3122 let isNotDuplicable = 1, isIndirectBranch = 1 in {
3123 def t2BR_JT : t2PseudoInst<(outs),
3124 (ins GPR:$target, GPR:$index, i32imm:$jt, i32imm:$id),
3126 [(ARMbr2jt GPR:$target, GPR:$index, tjumptable:$jt, imm:$id)]>;
3128 // FIXME: Add a non-pc based case that can be predicated.
3129 def t2TBB_JT : t2PseudoInst<(outs),
3130 (ins GPR:$index, i32imm:$jt, i32imm:$id), 0, IIC_Br, []>;
3132 def t2TBH_JT : t2PseudoInst<(outs),
3133 (ins GPR:$index, i32imm:$jt, i32imm:$id), 0, IIC_Br, []>;
3135 def t2TBB : T2I<(outs), (ins addrmode_tbb:$addr), IIC_Br,
3136 "tbb", "\t$addr", []> {
3139 let Inst{31-20} = 0b111010001101;
3140 let Inst{19-16} = Rn;
3141 let Inst{15-5} = 0b11110000000;
3142 let Inst{4} = 0; // B form
3145 let DecoderMethod = "DecodeThumbTableBranch";
3148 def t2TBH : T2I<(outs), (ins addrmode_tbh:$addr), IIC_Br,
3149 "tbh", "\t$addr", []> {
3152 let Inst{31-20} = 0b111010001101;
3153 let Inst{19-16} = Rn;
3154 let Inst{15-5} = 0b11110000000;
3155 let Inst{4} = 1; // H form
3158 let DecoderMethod = "DecodeThumbTableBranch";
3160 } // isNotDuplicable, isIndirectBranch
3162 } // isBranch, isTerminator, isBarrier
3164 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
3165 // a two-value operand where a dag node expects ", "two operands. :(
3166 let isBranch = 1, isTerminator = 1 in
3167 def t2Bcc : T2I<(outs), (ins brtarget:$target), IIC_Br,
3169 [/*(ARMbrcond bb:$target, imm:$cc)*/]> {
3170 let Inst{31-27} = 0b11110;
3171 let Inst{15-14} = 0b10;
3175 let Inst{25-22} = p;
3178 let Inst{26} = target{20};
3179 let Inst{11} = target{19};
3180 let Inst{13} = target{18};
3181 let Inst{21-16} = target{17-12};
3182 let Inst{10-0} = target{11-1};
3184 let DecoderMethod = "DecodeThumb2BCCInstruction";
3187 // Tail calls. The Darwin version of thumb tail calls uses a t2 branch, so
3189 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in {
3191 let Defs = [R0, R1, R2, R3, R9, R12, QQQQ0, QQQQ2, QQQQ3, PC],
3193 def tTAILJMPd: tPseudoExpand<(outs),
3194 (ins uncondbrtarget:$dst, pred:$p, variable_ops),
3196 (t2B uncondbrtarget:$dst, pred:$p)>,
3197 Requires<[IsThumb2, IsDarwin]>;
3201 let Defs = [ITSTATE] in
3202 def t2IT : Thumb2XI<(outs), (ins it_pred:$cc, it_mask:$mask),
3203 AddrModeNone, 2, IIC_iALUx,
3204 "it$mask\t$cc", "", []> {
3205 // 16-bit instruction.
3206 let Inst{31-16} = 0x0000;
3207 let Inst{15-8} = 0b10111111;
3212 let Inst{3-0} = mask;
3214 let DecoderMethod = "DecodeIT";
3217 // Branch and Exchange Jazelle -- for disassembly only
3219 def t2BXJ : T2I<(outs), (ins rGPR:$func), NoItinerary, "bxj", "\t$func", []> {
3221 let Inst{31-27} = 0b11110;
3223 let Inst{25-20} = 0b111100;
3224 let Inst{19-16} = func;
3225 let Inst{15-0} = 0b1000111100000000;
3228 // Compare and branch on zero / non-zero
3229 let isBranch = 1, isTerminator = 1 in {
3230 def tCBZ : T1I<(outs), (ins tGPR:$Rn, t_cbtarget:$target), IIC_Br,
3231 "cbz\t$Rn, $target", []>,
3232 T1Misc<{0,0,?,1,?,?,?}>,
3233 Requires<[IsThumb2]> {
3237 let Inst{9} = target{5};
3238 let Inst{7-3} = target{4-0};
3242 def tCBNZ : T1I<(outs), (ins tGPR:$Rn, t_cbtarget:$target), IIC_Br,
3243 "cbnz\t$Rn, $target", []>,
3244 T1Misc<{1,0,?,1,?,?,?}>,
3245 Requires<[IsThumb2]> {
3249 let Inst{9} = target{5};
3250 let Inst{7-3} = target{4-0};
3256 // Change Processor State is a system instruction.
3257 // FIXME: Since the asm parser has currently no clean way to handle optional
3258 // operands, create 3 versions of the same instruction. Once there's a clean
3259 // framework to represent optional operands, change this behavior.
3260 class t2CPS<dag iops, string asm_op> : T2XI<(outs), iops, NoItinerary,
3261 !strconcat("cps", asm_op), []> {
3267 let Inst{31-27} = 0b11110;
3269 let Inst{25-20} = 0b111010;
3270 let Inst{19-16} = 0b1111;
3271 let Inst{15-14} = 0b10;
3273 let Inst{10-9} = imod;
3275 let Inst{7-5} = iflags;
3276 let Inst{4-0} = mode;
3277 let DecoderMethod = "DecodeT2CPSInstruction";
3281 def t2CPS3p : t2CPS<(ins imod_op:$imod, iflags_op:$iflags, i32imm:$mode),
3282 "$imod.w\t$iflags, $mode">;
3283 let mode = 0, M = 0 in
3284 def t2CPS2p : t2CPS<(ins imod_op:$imod, iflags_op:$iflags),
3285 "$imod.w\t$iflags">;
3286 let imod = 0, iflags = 0, M = 1 in
3287 def t2CPS1p : t2CPS<(ins imm0_31:$mode), "\t$mode">;
3289 // A6.3.4 Branches and miscellaneous control
3290 // Table A6-14 Change Processor State, and hint instructions
3291 class T2I_hint<bits<8> op7_0, string opc, string asm>
3292 : T2I<(outs), (ins), NoItinerary, opc, asm, []> {
3293 let Inst{31-20} = 0xf3a;
3294 let Inst{19-16} = 0b1111;
3295 let Inst{15-14} = 0b10;
3297 let Inst{10-8} = 0b000;
3298 let Inst{7-0} = op7_0;
3301 def t2NOP : T2I_hint<0b00000000, "nop", ".w">;
3302 def t2YIELD : T2I_hint<0b00000001, "yield", ".w">;
3303 def t2WFE : T2I_hint<0b00000010, "wfe", ".w">;
3304 def t2WFI : T2I_hint<0b00000011, "wfi", ".w">;
3305 def t2SEV : T2I_hint<0b00000100, "sev", ".w">;
3307 def t2DBG : T2I<(outs), (ins imm0_15:$opt), NoItinerary, "dbg", "\t$opt", []> {
3309 let Inst{31-20} = 0b111100111010;
3310 let Inst{19-16} = 0b1111;
3311 let Inst{15-8} = 0b10000000;
3312 let Inst{7-4} = 0b1111;
3313 let Inst{3-0} = opt;
3316 // Secure Monitor Call is a system instruction.
3317 // Option = Inst{19-16}
3318 def t2SMC : T2I<(outs), (ins imm0_15:$opt), NoItinerary, "smc", "\t$opt", []> {
3319 let Inst{31-27} = 0b11110;
3320 let Inst{26-20} = 0b1111111;
3321 let Inst{15-12} = 0b1000;
3324 let Inst{19-16} = opt;
3327 class T2SRS<bits<2> Op, bit W, dag oops, dag iops, InstrItinClass itin,
3328 string opc, string asm, list<dag> pattern>
3329 : T2I<oops, iops, itin, opc, asm, pattern> {
3331 let Inst{31-25} = 0b1110100;
3332 let Inst{24-23} = Op;
3335 let Inst{20-16} = 0b01101;
3336 let Inst{15-5} = 0b11000000000;
3337 let Inst{4-0} = mode{4-0};
3340 // Store Return State is a system instruction.
3341 def t2SRSDB_UPD : T2SRS<0b00, 1, (outs), (ins imm0_31:$mode), NoItinerary,
3342 "srsdb", "\tsp!, $mode", []>;
3343 def t2SRSDB : T2SRS<0b00, 0, (outs), (ins imm0_31:$mode), NoItinerary,
3344 "srsdb","\tsp, $mode", []>;
3345 def t2SRSIA_UPD : T2SRS<0b11, 1, (outs), (ins imm0_31:$mode), NoItinerary,
3346 "srsia","\tsp!, $mode", []>;
3347 def t2SRSIA : T2SRS<0b11, 0, (outs), (ins imm0_31:$mode), NoItinerary,
3348 "srsia","\tsp, $mode", []>;
3350 // Return From Exception is a system instruction.
3351 class T2RFE<bits<12> op31_20, dag oops, dag iops, InstrItinClass itin,
3352 string opc, string asm, list<dag> pattern>
3353 : T2I<oops, iops, itin, opc, asm, pattern> {
3354 let Inst{31-20} = op31_20{11-0};
3357 let Inst{19-16} = Rn;
3358 let Inst{15-0} = 0xc000;
3361 def t2RFEDBW : T2RFE<0b111010000011,
3362 (outs), (ins GPR:$Rn), NoItinerary, "rfedb", "\t$Rn!",
3363 [/* For disassembly only; pattern left blank */]>;
3364 def t2RFEDB : T2RFE<0b111010000001,
3365 (outs), (ins GPR:$Rn), NoItinerary, "rfedb", "\t$Rn",
3366 [/* For disassembly only; pattern left blank */]>;
3367 def t2RFEIAW : T2RFE<0b111010011011,
3368 (outs), (ins GPR:$Rn), NoItinerary, "rfeia", "\t$Rn!",
3369 [/* For disassembly only; pattern left blank */]>;
3370 def t2RFEIA : T2RFE<0b111010011001,
3371 (outs), (ins GPR:$Rn), NoItinerary, "rfeia", "\t$Rn",
3372 [/* For disassembly only; pattern left blank */]>;
3374 //===----------------------------------------------------------------------===//
3375 // Non-Instruction Patterns
3378 // 32-bit immediate using movw + movt.
3379 // This is a single pseudo instruction to make it re-materializable.
3380 // FIXME: Remove this when we can do generalized remat.
3381 let isReMaterializable = 1, isMoveImm = 1 in
3382 def t2MOVi32imm : PseudoInst<(outs rGPR:$dst), (ins i32imm:$src), IIC_iMOVix2,
3383 [(set rGPR:$dst, (i32 imm:$src))]>,
3384 Requires<[IsThumb, HasV6T2]>;
3386 // Pseudo instruction that combines movw + movt + add pc (if pic).
3387 // It also makes it possible to rematerialize the instructions.
3388 // FIXME: Remove this when we can do generalized remat and when machine licm
3389 // can properly the instructions.
3390 let isReMaterializable = 1 in {
3391 def t2MOV_ga_pcrel : PseudoInst<(outs rGPR:$dst), (ins i32imm:$addr),
3393 [(set rGPR:$dst, (ARMWrapperPIC tglobaladdr:$addr))]>,
3394 Requires<[IsThumb2, UseMovt]>;
3396 def t2MOV_ga_dyn : PseudoInst<(outs rGPR:$dst), (ins i32imm:$addr),
3398 [(set rGPR:$dst, (ARMWrapperDYN tglobaladdr:$addr))]>,
3399 Requires<[IsThumb2, UseMovt]>;
3402 // ConstantPool, GlobalAddress, and JumpTable
3403 def : T2Pat<(ARMWrapper tglobaladdr :$dst), (t2LEApcrel tglobaladdr :$dst)>,
3404 Requires<[IsThumb2, DontUseMovt]>;
3405 def : T2Pat<(ARMWrapper tconstpool :$dst), (t2LEApcrel tconstpool :$dst)>;
3406 def : T2Pat<(ARMWrapper tglobaladdr :$dst), (t2MOVi32imm tglobaladdr :$dst)>,
3407 Requires<[IsThumb2, UseMovt]>;
3409 def : T2Pat<(ARMWrapperJT tjumptable:$dst, imm:$id),
3410 (t2LEApcrelJT tjumptable:$dst, imm:$id)>;
3412 // Pseudo instruction that combines ldr from constpool and add pc. This should
3413 // be expanded into two instructions late to allow if-conversion and
3415 let canFoldAsLoad = 1, isReMaterializable = 1 in
3416 def t2LDRpci_pic : PseudoInst<(outs rGPR:$dst), (ins i32imm:$addr, pclabel:$cp),
3418 [(set rGPR:$dst, (ARMpic_add (load (ARMWrapper tconstpool:$addr)),
3420 Requires<[IsThumb2]>;
3421 //===----------------------------------------------------------------------===//
3422 // Coprocessor load/store -- for disassembly only
3424 class T2CI<dag oops, dag iops, string opc, string asm>
3425 : T2I<oops, iops, NoItinerary, opc, asm, []> {
3426 let Inst{27-25} = 0b110;
3429 multiclass T2LdStCop<bits<4> op31_28, bit load, string opc> {
3430 def _OFFSET : T2CI<(outs),
3431 (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr),
3432 opc, "\tp$cop, cr$CRd, $addr"> {
3433 let Inst{31-28} = op31_28;
3434 let Inst{24} = 1; // P = 1
3435 let Inst{21} = 0; // W = 0
3436 let Inst{22} = 0; // D = 0
3437 let Inst{20} = load;
3438 let DecoderMethod = "DecodeCopMemInstruction";
3441 def _PRE : T2CI<(outs),
3442 (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr),
3443 opc, "\tp$cop, cr$CRd, $addr!"> {
3444 let Inst{31-28} = op31_28;
3445 let Inst{24} = 1; // P = 1
3446 let Inst{21} = 1; // W = 1
3447 let Inst{22} = 0; // D = 0
3448 let Inst{20} = load;
3449 let DecoderMethod = "DecodeCopMemInstruction";
3452 def _POST : T2CI<(outs),
3453 (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr),
3454 opc, "\tp$cop, cr$CRd, $addr"> {
3455 let Inst{31-28} = op31_28;
3456 let Inst{24} = 0; // P = 0
3457 let Inst{21} = 1; // W = 1
3458 let Inst{22} = 0; // D = 0
3459 let Inst{20} = load;
3460 let DecoderMethod = "DecodeCopMemInstruction";
3463 def _OPTION : T2CI<(outs),
3464 (ins nohash_imm:$cop,nohash_imm:$CRd,GPR:$base, nohash_imm:$option),
3465 opc, "\tp$cop, cr$CRd, [$base], \\{$option\\}"> {
3466 let Inst{31-28} = op31_28;
3467 let Inst{24} = 0; // P = 0
3468 let Inst{23} = 1; // U = 1
3469 let Inst{21} = 0; // W = 0
3470 let Inst{22} = 0; // D = 0
3471 let Inst{20} = load;
3472 let DecoderMethod = "DecodeCopMemInstruction";
3475 def L_OFFSET : T2CI<(outs),
3476 (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr),
3477 !strconcat(opc, "l"), "\tp$cop, cr$CRd, $addr"> {
3478 let Inst{31-28} = op31_28;
3479 let Inst{24} = 1; // P = 1
3480 let Inst{21} = 0; // W = 0
3481 let Inst{22} = 1; // D = 1
3482 let Inst{20} = load;
3483 let DecoderMethod = "DecodeCopMemInstruction";
3486 def L_PRE : T2CI<(outs),
3487 (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr),
3488 !strconcat(opc, "l"), "\tp$cop, cr$CRd, $addr!"> {
3489 let Inst{31-28} = op31_28;
3490 let Inst{24} = 1; // P = 1
3491 let Inst{21} = 1; // W = 1
3492 let Inst{22} = 1; // D = 1
3493 let Inst{20} = load;
3494 let DecoderMethod = "DecodeCopMemInstruction";
3497 def L_POST : T2CI<(outs),
3498 (ins nohash_imm:$cop, nohash_imm:$CRd, addr_offset_none:$addr,
3499 postidx_imm8s4:$offset),
3500 !strconcat(opc, "l"), "\tp$cop, cr$CRd, $addr, $offset"> {
3501 let Inst{31-28} = op31_28;
3502 let Inst{24} = 0; // P = 0
3503 let Inst{21} = 1; // W = 1
3504 let Inst{22} = 1; // D = 1
3505 let Inst{20} = load;
3506 let DecoderMethod = "DecodeCopMemInstruction";
3509 def L_OPTION : T2CI<(outs),
3510 (ins nohash_imm:$cop, nohash_imm:$CRd,GPR:$base,nohash_imm:$option),
3511 !strconcat(opc, "l"), "\tp$cop, cr$CRd, [$base], \\{$option\\}"> {
3512 let Inst{31-28} = op31_28;
3513 let Inst{24} = 0; // P = 0
3514 let Inst{23} = 1; // U = 1
3515 let Inst{21} = 0; // W = 0
3516 let Inst{22} = 1; // D = 1
3517 let Inst{20} = load;
3518 let DecoderMethod = "DecodeCopMemInstruction";
3522 defm t2LDC : T2LdStCop<0b1111, 1, "ldc">;
3523 defm t2STC : T2LdStCop<0b1111, 0, "stc">;
3526 //===----------------------------------------------------------------------===//
3527 // Move between special register and ARM core register -- for disassembly only
3529 // Move to ARM core register from Special Register
3530 def t2MRS : T2I<(outs GPR:$Rd), (ins), NoItinerary, "mrs", "\t$Rd, apsr", []> {
3532 let Inst{31-12} = 0b11110011111011111000;
3533 let Inst{11-8} = Rd;
3534 let Inst{7-0} = 0b0000;
3537 def : t2InstAlias<"mrs${p} $Rd, cpsr", (t2MRS GPR:$Rd, pred:$p)>;
3539 def t2MRSsys:T2I<(outs GPR:$Rd), (ins), NoItinerary, "mrs", "\t$Rd, spsr", []> {
3541 let Inst{31-12} = 0b11110011111111111000;
3542 let Inst{11-8} = Rd;
3543 let Inst{7-0} = 0b0000;
3546 // Move from ARM core register to Special Register
3548 // No need to have both system and application versions, the encodings are the
3549 // same and the assembly parser has no way to distinguish between them. The mask
3550 // operand contains the special register (R Bit) in bit 4 and bits 3-0 contains
3551 // the mask with the fields to be accessed in the special register.
3552 def t2MSR : T2I<(outs), (ins msr_mask:$mask, rGPR:$Rn),
3553 NoItinerary, "msr", "\t$mask, $Rn", []> {
3556 let Inst{31-21} = 0b11110011100;
3557 let Inst{20} = mask{4}; // R Bit
3558 let Inst{19-16} = Rn;
3559 let Inst{15-12} = 0b1000;
3560 let Inst{11-8} = mask{3-0};
3564 //===----------------------------------------------------------------------===//
3565 // Move between coprocessor and ARM core register
3568 class t2MovRCopro<bits<4> Op, string opc, bit direction, dag oops, dag iops,
3570 : T2Cop<Op, oops, iops,
3571 !strconcat(opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2"),
3573 let Inst{27-24} = 0b1110;
3574 let Inst{20} = direction;
3584 let Inst{15-12} = Rt;
3585 let Inst{11-8} = cop;
3586 let Inst{23-21} = opc1;
3587 let Inst{7-5} = opc2;
3588 let Inst{3-0} = CRm;
3589 let Inst{19-16} = CRn;
3592 class t2MovRRCopro<bits<4> Op, string opc, bit direction,
3593 list<dag> pattern = []>
3595 (ins p_imm:$cop, imm0_15:$opc1, GPR:$Rt, GPR:$Rt2, c_imm:$CRm),
3596 !strconcat(opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm"), pattern> {
3597 let Inst{27-24} = 0b1100;
3598 let Inst{23-21} = 0b010;
3599 let Inst{20} = direction;
3607 let Inst{15-12} = Rt;
3608 let Inst{19-16} = Rt2;
3609 let Inst{11-8} = cop;
3610 let Inst{7-4} = opc1;
3611 let Inst{3-0} = CRm;
3614 /* from ARM core register to coprocessor */
3615 def t2MCR : t2MovRCopro<0b1110, "mcr", 0,
3617 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
3618 c_imm:$CRm, imm0_7:$opc2),
3619 [(int_arm_mcr imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
3620 imm:$CRm, imm:$opc2)]>;
3621 def t2MCR2 : t2MovRCopro<0b1111, "mcr2", 0,
3622 (outs), (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
3623 c_imm:$CRm, imm0_7:$opc2),
3624 [(int_arm_mcr2 imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
3625 imm:$CRm, imm:$opc2)]>;
3627 /* from coprocessor to ARM core register */
3628 def t2MRC : t2MovRCopro<0b1110, "mrc", 1,
3629 (outs GPR:$Rt), (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
3630 c_imm:$CRm, imm0_7:$opc2), []>;
3632 def t2MRC2 : t2MovRCopro<0b1111, "mrc2", 1,
3633 (outs GPR:$Rt), (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
3634 c_imm:$CRm, imm0_7:$opc2), []>;
3636 def : T2v6Pat<(int_arm_mrc imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2),
3637 (t2MRC imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
3639 def : T2v6Pat<(int_arm_mrc2 imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2),
3640 (t2MRC2 imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
3643 /* from ARM core register to coprocessor */
3644 def t2MCRR : t2MovRRCopro<0b1110, "mcrr", 0,
3645 [(int_arm_mcrr imm:$cop, imm:$opc1, GPR:$Rt, GPR:$Rt2,
3647 def t2MCRR2 : t2MovRRCopro<0b1111, "mcrr2", 0,
3648 [(int_arm_mcrr2 imm:$cop, imm:$opc1, GPR:$Rt,
3649 GPR:$Rt2, imm:$CRm)]>;
3650 /* from coprocessor to ARM core register */
3651 def t2MRRC : t2MovRRCopro<0b1110, "mrrc", 1>;
3653 def t2MRRC2 : t2MovRRCopro<0b1111, "mrrc2", 1>;
3655 //===----------------------------------------------------------------------===//
3656 // Other Coprocessor Instructions.
3659 def tCDP : T2Cop<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1,
3660 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
3661 "cdp\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
3662 [(int_arm_cdp imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
3663 imm:$CRm, imm:$opc2)]> {
3664 let Inst{27-24} = 0b1110;
3673 let Inst{3-0} = CRm;
3675 let Inst{7-5} = opc2;
3676 let Inst{11-8} = cop;
3677 let Inst{15-12} = CRd;
3678 let Inst{19-16} = CRn;
3679 let Inst{23-20} = opc1;
3682 def t2CDP2 : T2Cop<0b1111, (outs), (ins p_imm:$cop, imm0_15:$opc1,
3683 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
3684 "cdp2\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
3685 [(int_arm_cdp2 imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
3686 imm:$CRm, imm:$opc2)]> {
3687 let Inst{27-24} = 0b1110;
3696 let Inst{3-0} = CRm;
3698 let Inst{7-5} = opc2;
3699 let Inst{11-8} = cop;
3700 let Inst{15-12} = CRd;
3701 let Inst{19-16} = CRn;
3702 let Inst{23-20} = opc1;
3707 //===----------------------------------------------------------------------===//
3708 // Non-Instruction Patterns
3711 // SXT/UXT with no rotate
3712 let AddedComplexity = 16 in {
3713 def : T2Pat<(and rGPR:$Rm, 0x000000FF), (t2UXTB rGPR:$Rm, 0)>,
3714 Requires<[IsThumb2]>;
3715 def : T2Pat<(and rGPR:$Rm, 0x0000FFFF), (t2UXTH rGPR:$Rm, 0)>,
3716 Requires<[IsThumb2]>;
3717 def : T2Pat<(and rGPR:$Rm, 0x00FF00FF), (t2UXTB16 rGPR:$Rm, 0)>,
3718 Requires<[HasT2ExtractPack, IsThumb2]>;
3719 def : T2Pat<(add rGPR:$Rn, (and rGPR:$Rm, 0x00FF)),
3720 (t2UXTAB rGPR:$Rn, rGPR:$Rm, 0)>,
3721 Requires<[HasT2ExtractPack, IsThumb2]>;
3722 def : T2Pat<(add rGPR:$Rn, (and rGPR:$Rm, 0xFFFF)),
3723 (t2UXTAH rGPR:$Rn, rGPR:$Rm, 0)>,
3724 Requires<[HasT2ExtractPack, IsThumb2]>;
3727 def : T2Pat<(sext_inreg rGPR:$Src, i8), (t2SXTB rGPR:$Src, 0)>,
3728 Requires<[IsThumb2]>;
3729 def : T2Pat<(sext_inreg rGPR:$Src, i16), (t2SXTH rGPR:$Src, 0)>,
3730 Requires<[IsThumb2]>;
3731 def : T2Pat<(add rGPR:$Rn, (sext_inreg rGPR:$Rm, i8)),
3732 (t2SXTAB rGPR:$Rn, rGPR:$Rm, 0)>,
3733 Requires<[HasT2ExtractPack, IsThumb2]>;
3734 def : T2Pat<(add rGPR:$Rn, (sext_inreg rGPR:$Rm, i16)),
3735 (t2SXTAH rGPR:$Rn, rGPR:$Rm, 0)>,
3736 Requires<[HasT2ExtractPack, IsThumb2]>;
3738 // Atomic load/store patterns
3739 def : T2Pat<(atomic_load_8 t2addrmode_imm12:$addr),
3740 (t2LDRBi12 t2addrmode_imm12:$addr)>;
3741 def : T2Pat<(atomic_load_8 t2addrmode_negimm8:$addr),
3742 (t2LDRBi8 t2addrmode_negimm8:$addr)>;
3743 def : T2Pat<(atomic_load_8 t2addrmode_so_reg:$addr),
3744 (t2LDRBs t2addrmode_so_reg:$addr)>;
3745 def : T2Pat<(atomic_load_16 t2addrmode_imm12:$addr),
3746 (t2LDRHi12 t2addrmode_imm12:$addr)>;
3747 def : T2Pat<(atomic_load_16 t2addrmode_negimm8:$addr),
3748 (t2LDRHi8 t2addrmode_negimm8:$addr)>;
3749 def : T2Pat<(atomic_load_16 t2addrmode_so_reg:$addr),
3750 (t2LDRHs t2addrmode_so_reg:$addr)>;
3751 def : T2Pat<(atomic_load_32 t2addrmode_imm12:$addr),
3752 (t2LDRi12 t2addrmode_imm12:$addr)>;
3753 def : T2Pat<(atomic_load_32 t2addrmode_negimm8:$addr),
3754 (t2LDRi8 t2addrmode_negimm8:$addr)>;
3755 def : T2Pat<(atomic_load_32 t2addrmode_so_reg:$addr),
3756 (t2LDRs t2addrmode_so_reg:$addr)>;
3757 def : T2Pat<(atomic_store_8 t2addrmode_imm12:$addr, GPR:$val),
3758 (t2STRBi12 GPR:$val, t2addrmode_imm12:$addr)>;
3759 def : T2Pat<(atomic_store_8 t2addrmode_negimm8:$addr, GPR:$val),
3760 (t2STRBi8 GPR:$val, t2addrmode_negimm8:$addr)>;
3761 def : T2Pat<(atomic_store_8 t2addrmode_so_reg:$addr, GPR:$val),
3762 (t2STRBs GPR:$val, t2addrmode_so_reg:$addr)>;
3763 def : T2Pat<(atomic_store_16 t2addrmode_imm12:$addr, GPR:$val),
3764 (t2STRHi12 GPR:$val, t2addrmode_imm12:$addr)>;
3765 def : T2Pat<(atomic_store_16 t2addrmode_negimm8:$addr, GPR:$val),
3766 (t2STRHi8 GPR:$val, t2addrmode_negimm8:$addr)>;
3767 def : T2Pat<(atomic_store_16 t2addrmode_so_reg:$addr, GPR:$val),
3768 (t2STRHs GPR:$val, t2addrmode_so_reg:$addr)>;
3769 def : T2Pat<(atomic_store_32 t2addrmode_imm12:$addr, GPR:$val),
3770 (t2STRi12 GPR:$val, t2addrmode_imm12:$addr)>;
3771 def : T2Pat<(atomic_store_32 t2addrmode_negimm8:$addr, GPR:$val),
3772 (t2STRi8 GPR:$val, t2addrmode_negimm8:$addr)>;
3773 def : T2Pat<(atomic_store_32 t2addrmode_so_reg:$addr, GPR:$val),
3774 (t2STRs GPR:$val, t2addrmode_so_reg:$addr)>;
3777 //===----------------------------------------------------------------------===//
3778 // Assembler aliases
3781 // Aliases for ADC without the ".w" optional width specifier.
3782 def : t2InstAlias<"adc${s}${p} $Rd, $Rn, $Rm",
3783 (t2ADCrr rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, pred:$p, cc_out:$s)>;
3784 def : t2InstAlias<"adc${s}${p} $Rd, $Rn, $ShiftedRm",
3785 (t2ADCrs rGPR:$Rd, rGPR:$Rn, t2_so_reg:$ShiftedRm,
3786 pred:$p, cc_out:$s)>;
3788 // Aliases for SBC without the ".w" optional width specifier.
3789 def : t2InstAlias<"sbc${s}${p} $Rd, $Rn, $Rm",
3790 (t2SBCrr rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, pred:$p, cc_out:$s)>;
3791 def : t2InstAlias<"sbc${s}${p} $Rd, $Rn, $ShiftedRm",
3792 (t2SBCrs rGPR:$Rd, rGPR:$Rn, t2_so_reg:$ShiftedRm,
3793 pred:$p, cc_out:$s)>;
3795 // Aliases for ADD without the ".w" optional width specifier.
3796 def : t2InstAlias<"add${s}${p} $Rd, $Rn, $imm",
3797 (t2ADDri rGPR:$Rd, GPRnopc:$Rn, t2_so_imm:$imm, pred:$p, cc_out:$s)>;
3798 def : t2InstAlias<"add${p} $Rd, $Rn, $imm",
3799 (t2ADDri12 rGPR:$Rd, GPR:$Rn, imm0_4095:$imm, pred:$p)>;
3800 def : t2InstAlias<"add${s}${p} $Rd, $Rn, $Rm",
3801 (t2ADDrr rGPR:$Rd, GPRnopc:$Rn, rGPR:$Rm, pred:$p, cc_out:$s)>;
3802 def : t2InstAlias<"add${s}${p} $Rd, $Rn, $ShiftedRm",
3803 (t2ADDrs rGPR:$Rd, GPRnopc:$Rn, t2_so_reg:$ShiftedRm,
3804 pred:$p, cc_out:$s)>;
3806 // Aliases for SUB without the ".w" optional width specifier.
3807 def : t2InstAlias<"sub${s}${p} $Rd, $Rn, $imm",
3808 (t2SUBri rGPR:$Rd, GPRnopc:$Rn, t2_so_imm:$imm, pred:$p, cc_out:$s)>;
3809 def : t2InstAlias<"sub${p} $Rd, $Rn, $imm",
3810 (t2SUBri12 rGPR:$Rd, GPR:$Rn, imm0_4095:$imm, pred:$p)>;
3811 def : t2InstAlias<"sub${s}${p} $Rd, $Rn, $Rm",
3812 (t2SUBrr rGPR:$Rd, GPRnopc:$Rn, rGPR:$Rm, pred:$p, cc_out:$s)>;
3813 def : t2InstAlias<"sub${s}${p} $Rd, $Rn, $ShiftedRm",
3814 (t2SUBrs rGPR:$Rd, GPRnopc:$Rn, t2_so_reg:$ShiftedRm,
3815 pred:$p, cc_out:$s)>;
3817 // Alias for compares without the ".w" optional width specifier.
3818 def : t2InstAlias<"cmn${p} $Rn, $Rm",
3819 (t2CMNzrr GPRnopc:$Rn, rGPR:$Rm, pred:$p)>;
3820 def : t2InstAlias<"teq${p} $Rn, $Rm",
3821 (t2TEQrr GPRnopc:$Rn, rGPR:$Rm, pred:$p)>;
3822 def : t2InstAlias<"tst${p} $Rn, $Rm",
3823 (t2TSTrr GPRnopc:$Rn, rGPR:$Rm, pred:$p)>;
3826 def : InstAlias<"dmb", (t2DMB 0xf)>, Requires<[IsThumb2, HasDB]>;
3827 def : InstAlias<"dsb", (t2DSB 0xf)>, Requires<[IsThumb2, HasDB]>;
3828 def : InstAlias<"isb", (t2ISB 0xf)>, Requires<[IsThumb2, HasDB]>;
3830 // Alias for LDR, LDRB, LDRH, LDRSB, and LDRSH without the ".w" optional
3832 def : t2InstAlias<"ldr${p} $Rt, $addr",
3833 (t2LDRi12 GPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
3834 def : t2InstAlias<"ldrb${p} $Rt, $addr",
3835 (t2LDRBi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
3836 def : t2InstAlias<"ldrh${p} $Rt, $addr",
3837 (t2LDRHi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
3838 def : t2InstAlias<"ldrsb${p} $Rt, $addr",
3839 (t2LDRSBi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
3840 def : t2InstAlias<"ldrsh${p} $Rt, $addr",
3841 (t2LDRSHi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
3843 def : t2InstAlias<"ldr${p} $Rt, $addr",
3844 (t2LDRs GPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
3845 def : t2InstAlias<"ldrb${p} $Rt, $addr",
3846 (t2LDRBs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
3847 def : t2InstAlias<"ldrh${p} $Rt, $addr",
3848 (t2LDRHs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
3849 def : t2InstAlias<"ldrsb${p} $Rt, $addr",
3850 (t2LDRSBs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
3851 def : t2InstAlias<"ldrsh${p} $Rt, $addr",
3852 (t2LDRSHs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
3854 // Alias for MVN without the ".w" optional width specifier.
3855 def : t2InstAlias<"mvn${s}${p} $Rd, $Rm",
3856 (t2MVNr rGPR:$Rd, rGPR:$Rm, pred:$p, cc_out:$s)>;
3857 def : t2InstAlias<"mvn${s}${p} $Rd, $ShiftedRm",
3858 (t2MVNs rGPR:$Rd, t2_so_reg:$ShiftedRm, pred:$p, cc_out:$s)>;
3860 // PKHBT/PKHTB with default shift amount. PKHTB is equivalent to PKHBT when the
3861 // shift amount is zero (i.e., unspecified).
3862 def : InstAlias<"pkhbt${p} $Rd, $Rn, $Rm",
3863 (t2PKHBT rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>,
3864 Requires<[HasT2ExtractPack, IsThumb2]>;
3865 def : InstAlias<"pkhtb${p} $Rd, $Rn, $Rm",
3866 (t2PKHBT rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>,
3867 Requires<[HasT2ExtractPack, IsThumb2]>;
3869 // PUSH/POP aliases for STM/LDM
3870 def : t2InstAlias<"push${p}.w $regs", (t2STMDB_UPD SP, pred:$p, reglist:$regs)>;
3871 def : t2InstAlias<"push${p} $regs", (t2STMDB_UPD SP, pred:$p, reglist:$regs)>;
3872 def : t2InstAlias<"pop${p}.w $regs", (t2LDMIA_UPD SP, pred:$p, reglist:$regs)>;
3873 def : t2InstAlias<"pop${p} $regs", (t2LDMIA_UPD SP, pred:$p, reglist:$regs)>;
3875 // Alias for REV/REV16/REVSH without the ".w" optional width specifier.
3876 def : t2InstAlias<"rev${p} $Rd, $Rm", (t2REV rGPR:$Rd, rGPR:$Rm, pred:$p)>;
3877 def : t2InstAlias<"rev16${p} $Rd, $Rm", (t2REV16 rGPR:$Rd, rGPR:$Rm, pred:$p)>;
3878 def : t2InstAlias<"revsh${p} $Rd, $Rm", (t2REVSH rGPR:$Rd, rGPR:$Rm, pred:$p)>;
3881 // Alias for RSB without the ".w" optional width specifier, and with optional
3882 // implied destination register.
3883 def : t2InstAlias<"rsb${s}${p} $Rd, $Rn, $imm",
3884 (t2RSBri rGPR:$Rd, rGPR:$Rn, t2_so_imm:$imm, pred:$p, cc_out:$s)>;
3885 def : t2InstAlias<"rsb${s}${p} $Rdn, $imm",
3886 (t2RSBri rGPR:$Rdn, rGPR:$Rdn, t2_so_imm:$imm, pred:$p, cc_out:$s)>;
3887 def : t2InstAlias<"rsb${s}${p} $Rdn, $Rm",
3888 (t2RSBrr rGPR:$Rdn, rGPR:$Rdn, rGPR:$Rm, pred:$p, cc_out:$s)>;
3889 def : t2InstAlias<"rsb${s}${p} $Rdn, $ShiftedRm",
3890 (t2RSBrs rGPR:$Rdn, rGPR:$Rdn, t2_so_reg:$ShiftedRm, pred:$p,
3893 // SSAT/USAT optional shift operand.
3894 def : t2InstAlias<"ssat${p} $Rd, $sat_imm, $Rn",
3895 (t2SSAT rGPR:$Rd, imm1_32:$sat_imm, rGPR:$Rn, 0, pred:$p)>;
3896 def : t2InstAlias<"usat${p} $Rd, $sat_imm, $Rn",
3897 (t2USAT rGPR:$Rd, imm0_31:$sat_imm, rGPR:$Rn, 0, pred:$p)>;
3899 // STM w/o the .w suffix.
3900 def : t2InstAlias<"stm${p} $Rn, $regs",
3901 (t2STMIA GPR:$Rn, pred:$p, reglist:$regs)>;
3903 // Alias for STR, STRB, and STRH without the ".w" optional
3905 def : t2InstAlias<"str${p} $Rt, $addr",
3906 (t2STRi12 GPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
3907 def : t2InstAlias<"strb${p} $Rt, $addr",
3908 (t2STRBi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
3909 def : t2InstAlias<"strh${p} $Rt, $addr",
3910 (t2STRHi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>;
3912 def : t2InstAlias<"str${p} $Rt, $addr",
3913 (t2STRs GPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
3914 def : t2InstAlias<"strb${p} $Rt, $addr",
3915 (t2STRBs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
3916 def : t2InstAlias<"strh${p} $Rt, $addr",
3917 (t2STRHs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>;
3919 // Extend instruction optional rotate operand.
3920 def : t2InstAlias<"sxtab${p} $Rd, $Rn, $Rm",
3921 (t2SXTAB rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>;
3922 def : t2InstAlias<"sxtah${p} $Rd, $Rn, $Rm",
3923 (t2SXTAH rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>;
3924 def : t2InstAlias<"sxtab16${p} $Rd, $Rn, $Rm",
3925 (t2SXTAB16 rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>;
3926 def : t2InstAlias<"sxtb${p} $Rd, $Rm",
3927 (t2SXTB rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
3928 def : t2InstAlias<"sxtb16${p} $Rd, $Rm",
3929 (t2SXTB16 rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
3930 def : t2InstAlias<"sxth${p} $Rd, $Rm",
3931 (t2SXTH rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
3933 def : t2InstAlias<"uxtab${p} $Rd, $Rn, $Rm",
3934 (t2UXTAB rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>;
3935 def : t2InstAlias<"uxtah${p} $Rd, $Rn, $Rm",
3936 (t2UXTAH rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>;
3937 def : t2InstAlias<"uxtab16${p} $Rd, $Rn, $Rm",
3938 (t2UXTAB16 rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>;
3939 def : t2InstAlias<"uxtb${p} $Rd, $Rm",
3940 (t2UXTB rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
3941 def : t2InstAlias<"uxtb16${p} $Rd, $Rm",
3942 (t2UXTB16 rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
3943 def : t2InstAlias<"uxth${p} $Rd, $Rm",
3944 (t2UXTH rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
3946 // Extend instruction w/o the ".w" optional width specifier.
3947 def : t2InstAlias<"uxtb${p} $Rd, $Rm$rot",
3948 (t2UXTB rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>;
3949 def : t2InstAlias<"uxtb16${p} $Rd, $Rm$rot",
3950 (t2UXTB16 rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>;
3951 def : t2InstAlias<"uxth${p} $Rd, $Rm$rot",
3952 (t2UXTH rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>;
3954 def : t2InstAlias<"sxtb${p} $Rd, $Rm$rot",
3955 (t2SXTB rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>;
3956 def : t2InstAlias<"sxtb16${p} $Rd, $Rm$rot",
3957 (t2SXTB16 rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>;
3958 def : t2InstAlias<"sxth${p} $Rd, $Rm$rot",
3959 (t2SXTH rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>;