1 //===- ARMInstrThumb2.td - Thumb2 support for ARM -------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Thumb2 instruction set.
12 //===----------------------------------------------------------------------===//
14 // Shifted operands. No register controlled shifts for Thumb2.
15 // Note: We do not support rrx shifted operands yet.
16 def t2_so_reg : Operand<i32>, // reg imm
17 ComplexPattern<i32, 2, "SelectThumb2ShifterOperandReg",
19 let PrintMethod = "printSOOperand";
20 let MIOperandInfo = (ops GPR, i32imm);
23 // t2_so_imm_XFORM - Return a t2_so_imm value packed into the format
24 // described for t2_so_imm def below.
25 def t2_so_imm_XFORM : SDNodeXForm<imm, [{
26 return CurDAG->getTargetConstant(
27 ARM_AM::getT2SOImmVal(N->getZExtValue()), MVT::i32);
30 // t2_so_imm_not_XFORM - Return the complement of a t2_so_imm value
31 def t2_so_imm_not_XFORM : SDNodeXForm<imm, [{
32 return CurDAG->getTargetConstant(
33 ARM_AM::getT2SOImmVal(~((uint32_t)N->getZExtValue())), MVT::i32);
36 // t2_so_imm_neg_XFORM - Return the negation of a t2_so_imm value
37 def t2_so_imm_neg_XFORM : SDNodeXForm<imm, [{
38 return CurDAG->getTargetConstant(
39 ARM_AM::getT2SOImmVal(-((int)N->getZExtValue())), MVT::i32);
42 // t2_so_imm - Match a 32-bit immediate operand, which is an
43 // 8-bit immediate rotated by an arbitrary number of bits, or an 8-bit
44 // immediate splatted into multiple bytes of the word. t2_so_imm values are
45 // represented in the imm field in the same 12-bit form that they are encoded
46 // into t2_so_imm instructions: the 8-bit immediate is the least significant bits
47 // [bits 0-7], the 4-bit shift/splat amount is the next 4 bits [bits 8-11].
48 def t2_so_imm : Operand<i32>,
50 return ARM_AM::getT2SOImmVal((uint32_t)N->getZExtValue()) != -1;
51 }], t2_so_imm_XFORM> {
52 let PrintMethod = "printT2SOImmOperand";
55 // t2_so_imm_not - Match an immediate that is a complement
57 def t2_so_imm_not : Operand<i32>,
59 return ARM_AM::getT2SOImmVal(~((uint32_t)N->getZExtValue())) != -1;
60 }], t2_so_imm_not_XFORM> {
61 let PrintMethod = "printT2SOImmOperand";
64 // t2_so_imm_neg - Match an immediate that is a negation of a t2_so_imm.
65 def t2_so_imm_neg : Operand<i32>,
67 return ARM_AM::getT2SOImmVal(-((int)N->getZExtValue())) != -1;
68 }], t2_so_imm_neg_XFORM> {
69 let PrintMethod = "printT2SOImmOperand";
72 /// imm1_31 predicate - True if the 32-bit immediate is in the range [1,31].
73 def imm1_31 : PatLeaf<(i32 imm), [{
74 return (int32_t)N->getZExtValue() >= 1 && (int32_t)N->getZExtValue() < 32;
77 /// imm0_4095 predicate - True if the 32-bit immediate is in the range [0.4095].
78 def imm0_4095 : PatLeaf<(i32 imm), [{
79 return (uint32_t)N->getZExtValue() < 4096;
82 def imm0_4095_neg : PatLeaf<(i32 imm), [{
83 return (uint32_t)(-N->getZExtValue()) < 4096;
86 /// imm0_65535 predicate - True if the 32-bit immediate is in the range
88 def imm0_65535 : PatLeaf<(i32 imm), [{
89 return (uint32_t)N->getZExtValue() < 65536;
93 /// bf_inv_mask_imm predicate - An AND mask to clear an arbitrary width bitfield
95 def bf_inv_mask_imm : Operand<i32>,
97 uint32_t v = (uint32_t)N->getZExtValue();
100 // naive checker. should do better, but simple is best for now since it's
101 // more likely to be correct.
102 while (v & 1) v >>= 1; // shift off the leading 1's
105 while (!(v & 1)) v >>=1; // shift off the mask
106 while (v & 1) v >>= 1; // shift off the trailing 1's
108 // if this is a mask for clearing a bitfield, what's left should be zero.
111 let PrintMethod = "printBitfieldInvMaskImmOperand";
114 /// Split a 32-bit immediate into two 16 bit parts.
115 def t2_lo16 : SDNodeXForm<imm, [{
116 return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() & 0xffff,
120 def t2_hi16 : SDNodeXForm<imm, [{
121 return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() >> 16, MVT::i32);
124 def t2_lo16AllZero : PatLeaf<(i32 imm), [{
125 // Returns true if all low 16-bits are 0.
126 return (((uint32_t)N->getZExtValue()) & 0xFFFFUL) == 0;
129 //===----------------------------------------------------------------------===//
130 // Thumb2 to cover the functionality of the ARM instruction set.
133 /// T2I_un_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a
134 /// unary operation that produces a value. These are predicable and can be
135 /// changed to modify CPSR.
136 multiclass T2I_un_irs<string opc, PatFrag opnode, bit Cheap = 0, bit ReMat = 0>{
138 def i : T2sI<(outs GPR:$dst), (ins t2_so_imm:$src),
140 [(set GPR:$dst, (opnode t2_so_imm:$src))]> {
141 let isAsCheapAsAMove = Cheap;
142 let isReMaterializable = ReMat;
145 def r : T2I<(outs GPR:$dst), (ins GPR:$src),
147 [(set GPR:$dst, (opnode GPR:$src))]>;
149 def s : T2I<(outs GPR:$dst), (ins t2_so_reg:$src),
151 [(set GPR:$dst, (opnode t2_so_reg:$src))]>;
154 /// T2I_bin_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a
155 // binary operation that produces a value. These are predicable and can be
156 /// changed to modify CPSR.
157 multiclass T2I_bin_irs<string opc, PatFrag opnode> {
159 def ri : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs),
160 opc, " $dst, $lhs, $rhs",
161 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>;
163 def rr : T2sI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
164 opc, " $dst, $lhs, $rhs",
165 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]>;
167 def rs : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs),
168 opc, " $dst, $lhs, $rhs",
169 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>;
172 /// T2I_rbin_irs - Same as T2I_bin_irs except the order of operands are reversed.
173 multiclass T2I_rbin_irs<string opc, PatFrag opnode> {
175 def ri : T2I<(outs GPR:$dst), (ins GPR:$rhs, t2_so_imm:$lhs),
176 opc, " $dst, $rhs, $lhs",
177 [(set GPR:$dst, (opnode t2_so_imm:$lhs, GPR:$rhs))]>;
179 def rr : T2I<(outs GPR:$dst), (ins GPR:$rhs, GPR:$lhs),
180 opc, " $dst, $rhs, $lhs",
181 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]>;
183 def rs : T2I<(outs GPR:$dst), (ins GPR:$rhs, t2_so_reg:$lhs),
184 opc, " $dst, $rhs, $lhs",
185 [(set GPR:$dst, (opnode t2_so_reg:$lhs, GPR:$rhs))]>;
188 /// T2I_bin_s_irs - Similar to T2I_bin_irs except it sets the 's' bit so the
189 /// instruction modifies the CPSR register.
190 let Defs = [CPSR] in {
191 multiclass T2I_bin_s_irs<string opc, PatFrag opnode> {
193 def ri : T2I<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs),
194 !strconcat(opc, "s"), " $dst, $lhs, $rhs",
195 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>;
197 def rr : T2I<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
198 !strconcat(opc, "s"), " $dst, $lhs, $rhs",
199 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]>;
201 def rs : T2I<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs),
202 !strconcat(opc, "s"), " $dst, $lhs, $rhs",
203 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>;
207 /// T2I_rbin_s_irs - Same as T2I_bin_s_irs except the order of operands are
209 let Defs = [CPSR] in {
210 multiclass T2I_rbin_s_irs<string opc, PatFrag opnode> {
212 def ri : T2I<(outs GPR:$dst), (ins GPR:$rhs, t2_so_imm:$lhs),
213 !strconcat(opc, "s"), " $dst, $rhs, $lhs",
214 [(set GPR:$dst, (opnode t2_so_imm:$lhs, GPR:$rhs))]>;
216 def rr : T2I<(outs GPR:$dst), (ins GPR:$rhs, GPR:$lhs),
217 !strconcat(opc, "s"), " $dst, $rhs, $lhs",
218 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]>;
220 def rs : T2I<(outs GPR:$dst), (ins GPR:$rhs, t2_so_reg:$lhs),
221 !strconcat(opc, "s"), " $dst, $rhs, $lhs",
222 [(set GPR:$dst, (opnode t2_so_reg:$lhs, GPR:$rhs))]>;
226 /// T2I_bin_ii12rs - Defines a set of (op reg, {so_imm|imm0_4095|r|so_reg})
227 /// patterns for a binary operation that produces a value.
228 multiclass T2I_bin_ii12rs<string opc, PatFrag opnode> {
230 def ri : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs),
231 opc, " $dst, $lhs, $rhs",
232 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>;
234 def ri12 : T2sI<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs),
235 !strconcat(opc, "w"), " $dst, $lhs, $rhs",
236 [(set GPR:$dst, (opnode GPR:$lhs, imm0_4095:$rhs))]>;
238 def rr : T2sI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
239 opc, " $dst, $lhs, $rhs",
240 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]>;
242 def rs : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs),
243 opc, " $dst, $lhs, $rhs",
244 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>;
247 /// T2I_bin_c_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a
248 // binary operation that produces a value and set the carry bit. It can also
249 /// optionally set CPSR.
250 let Uses = [CPSR] in {
251 multiclass T2I_bin_c_irs<string opc, PatFrag opnode> {
253 def ri : T2XI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs, cc_out:$s),
254 !strconcat(opc, "${s} $dst, $lhs, $rhs"),
255 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>;
257 def rr : T2XI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs, cc_out:$s),
258 !strconcat(opc, "${s} $dst, $lhs, $rhs"),
259 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]>;
261 def rs : T2XI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs, cc_out:$s),
262 !strconcat(opc, "${s} $dst, $lhs, $rhs"),
263 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>;
267 /// T2I_rbin_c_irs - Same as T2I_bin_c_irs except the order of operands are
269 let Uses = [CPSR] in {
270 multiclass T2I_rbin_c_irs<string opc, PatFrag opnode> {
272 def ri : T2XI<(outs GPR:$dst), (ins GPR:$rhs, t2_so_imm:$lhs, cc_out:$s),
273 !strconcat(opc, "${s} $dst, $rhs, $lhs"),
274 [(set GPR:$dst, (opnode t2_so_imm:$lhs, GPR:$rhs))]>;
276 def rr : T2XI<(outs GPR:$dst), (ins GPR:$rhs, GPR:$lhs, cc_out:$s),
277 !strconcat(opc, "${s} $dst, $rhs, $lhs"),
278 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]>;
280 def rs : T2XI<(outs GPR:$dst), (ins GPR:$rhs, t2_so_reg:$lhs, cc_out:$s),
281 !strconcat(opc, "${s} $dst, $rhs, $lhs"),
282 [(set GPR:$dst, (opnode t2_so_reg:$lhs, GPR:$rhs))]>;
286 /// T2I_sh_ir - Defines a set of (op reg, {so_imm|r}) patterns for a shift /
287 // rotate operation that produces a value.
288 multiclass T2I_sh_ir<string opc, PatFrag opnode> {
290 def ri : T2sI<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs),
291 opc, " $dst, $lhs, $rhs",
292 [(set GPR:$dst, (opnode GPR:$lhs, imm1_31:$rhs))]>;
294 def rr : T2sI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
295 opc, " $dst, $lhs, $rhs",
296 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]>;
299 /// T21_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
300 /// patterns. Similar to T2I_bin_irs except the instruction does not produce
301 /// a explicit result, only implicitly set CPSR.
302 let Uses = [CPSR] in {
303 multiclass T2I_cmp_is<string opc, PatFrag opnode> {
305 def ri : T2I<(outs), (ins GPR:$lhs, t2_so_imm:$rhs),
307 [(opnode GPR:$lhs, t2_so_imm:$rhs)]>;
309 def rr : T2I<(outs), (ins GPR:$lhs, GPR:$rhs),
311 [(opnode GPR:$lhs, GPR:$rhs)]>;
313 def rs : T2I<(outs), (ins GPR:$lhs, t2_so_reg:$rhs),
315 [(opnode GPR:$lhs, t2_so_reg:$rhs)]>;
319 //===----------------------------------------------------------------------===//
320 // Miscellaneous Instructions.
323 let isNotDuplicable = 1 in
324 def t2PICADD : T2XI<(outs tGPR:$dst), (ins tGPR:$lhs, pclabel:$cp),
325 "$cp:\n\tadd $dst, pc",
326 [(set tGPR:$dst, (ARMpic_add tGPR:$lhs, imm:$cp))]>;
329 // LEApcrel - Load a pc-relative address into a register without offending the
331 def t2LEApcrel : T2XI<(outs GPR:$dst), (ins i32imm:$label, pred:$p),
332 !strconcat(!strconcat(".set PCRELV${:uid}, ($label-(",
333 "${:private}PCRELL${:uid}+8))\n"),
334 !strconcat("${:private}PCRELL${:uid}:\n\t",
335 "add$p $dst, pc, #PCRELV${:uid}")),
338 def t2LEApcrelJT : T2XI<(outs GPR:$dst),
339 (ins i32imm:$label, i32imm:$id, pred:$p),
340 !strconcat(!strconcat(".set PCRELV${:uid}, (${label}_${id:no_hash}-(",
341 "${:private}PCRELL${:uid}+8))\n"),
342 !strconcat("${:private}PCRELL${:uid}:\n\t",
343 "add$p $dst, pc, #PCRELV${:uid}")),
346 // ADD rd, sp, #so_imm
347 def t2ADDrSPi : T2XI<(outs GPR:$dst), (ins GPR:$sp, t2_so_imm:$imm),
348 "add $dst, $sp, $imm",
351 // ADD rd, sp, #imm12
352 def t2ADDrSPi12 : T2XI<(outs GPR:$dst), (ins GPR:$sp, i32imm:$imm),
353 "addw $dst, $sp, $imm",
356 def t2ADDrSPs : T2XI<(outs GPR:$dst), (ins GPR:$sp, t2_so_reg:$rhs),
357 "addw $dst, $sp, $rhs",
361 //===----------------------------------------------------------------------===//
362 // Move Instructions.
365 let neverHasSideEffects = 1 in
366 def t2MOVr : T2sI<(outs GPR:$dst), (ins GPR:$src),
367 "mov", " $dst, $src", []>;
369 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
370 def t2MOVi16 : T2sI<(outs GPR:$dst), (ins i32imm:$src),
371 "movw", " $dst, $src",
372 [(set GPR:$dst, imm0_65535:$src)]>;
374 // FIXME: Also available in ARM mode.
375 let Constraints = "$src = $dst" in
376 def t2MOVTi16 : T2sI<(outs GPR:$dst), (ins GPR:$src, i32imm:$imm),
377 "movt", " $dst, $imm",
379 (or (and GPR:$src, 0xffff), t2_lo16AllZero:$imm))]>;
381 //===----------------------------------------------------------------------===//
382 // Arithmetic Instructions.
385 defm t2ADD : T2I_bin_ii12rs<"add", BinOpFrag<(add node:$LHS, node:$RHS)>>;
386 defm t2SUB : T2I_bin_ii12rs<"sub", BinOpFrag<(sub node:$LHS, node:$RHS)>>;
388 // ADD and SUB with 's' bit set. No 12-bit immediate (T4) variants.
389 defm t2ADDS : T2I_bin_s_irs<"add", BinOpFrag<(addc node:$LHS, node:$RHS)>>;
390 defm t2SUBS : T2I_bin_s_irs<"sub", BinOpFrag<(subc node:$LHS, node:$RHS)>>;
392 // FIXME: predication support
393 defm t2ADC : T2I_bin_c_irs<"adc", BinOpFrag<(adde node:$LHS, node:$RHS)>>;
394 defm t2SBC : T2I_bin_c_irs<"sbc", BinOpFrag<(sube node:$LHS, node:$RHS)>>;
397 defm t2RSB : T2I_rbin_irs <"rsb", BinOpFrag<(sub node:$LHS, node:$RHS)>>;
398 defm t2RSBS : T2I_rbin_c_irs<"rsb", BinOpFrag<(subc node:$LHS, node:$RHS)>>;
399 defm t2RSC : T2I_rbin_s_irs<"rsc", BinOpFrag<(sube node:$LHS, node:$RHS)>>;
401 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
402 def : Thumb2Pat<(add GPR:$src, t2_so_imm_neg:$imm),
403 (t2SUBri GPR:$src, t2_so_imm_neg:$imm)>;
404 def : Thumb2Pat<(add GPR:$src, imm0_4095_neg:$imm),
405 (t2SUBri12 GPR:$src, imm0_4095_neg:$imm)>;
408 //===----------------------------------------------------------------------===//
409 // Shift and rotate Instructions.
412 defm t2LSL : T2I_sh_ir<"lsl", BinOpFrag<(shl node:$LHS, node:$RHS)>>;
413 defm t2LSR : T2I_sh_ir<"lsr", BinOpFrag<(srl node:$LHS, node:$RHS)>>;
414 defm t2ASR : T2I_sh_ir<"asr", BinOpFrag<(sra node:$LHS, node:$RHS)>>;
415 defm t2ROR : T2I_sh_ir<"ror", BinOpFrag<(rotr node:$LHS, node:$RHS)>>;
417 def t2MOVrx : T2sI<(outs GPR:$dst), (ins GPR:$src),
418 "mov", " $dst, $src, rrx",
419 [(set GPR:$dst, (ARMrrx GPR:$src))]>;
421 //===----------------------------------------------------------------------===//
422 // Bitwise Instructions.
425 defm t2AND : T2I_bin_irs<"and", BinOpFrag<(and node:$LHS, node:$RHS)>>;
426 defm t2ORR : T2I_bin_irs<"orr", BinOpFrag<(or node:$LHS, node:$RHS)>>;
427 defm t2EOR : T2I_bin_irs<"eor", BinOpFrag<(xor node:$LHS, node:$RHS)>>;
429 defm t2BIC : T2I_bin_irs<"bic", BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
431 def : Thumb2Pat<(and GPR:$src, t2_so_imm_not:$imm),
432 (t2BICri GPR:$src, t2_so_imm_not:$imm)>;
434 defm t2ORN : T2I_bin_irs<"orn", BinOpFrag<(or node:$LHS, (not node:$RHS))>>;
436 def : Thumb2Pat<(or GPR:$src, t2_so_imm_not:$imm),
437 (t2ORNri GPR:$src, t2_so_imm_not:$imm)>;
439 defm t2MVN : T2I_un_irs <"mvn", UnOpFrag<(not node:$Src)>, 1, 1>;
441 // A8.6.17 BFC - Bitfield clear
442 // FIXME: Also available in ARM mode.
443 let Constraints = "$src = $dst" in
444 def t2BFC : T2I<(outs GPR:$dst), (ins GPR:$src, bf_inv_mask_imm:$imm),
445 "bfc", " $dst, $imm",
446 [(set GPR:$dst, (and GPR:$src, bf_inv_mask_imm:$imm))]>;
448 // FIXME: A8.6.18 BFI - Bitfield insert (Encoding T1)
450 //===----------------------------------------------------------------------===//
451 // Multiply Instructions.
453 def t2MUL: T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b),
454 "mul", " $dst, $a, $b",
455 [(set GPR:$dst, (mul GPR:$a, GPR:$b))]>;
457 def t2MLA: T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
458 "mla", " $dst, $a, $b, $c",
459 [(set GPR:$dst, (add (mul GPR:$a, GPR:$b), GPR:$c))]>;
461 def t2MLS: T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
462 "mls", " $dst, $a, $b, $c",
463 [(set GPR:$dst, (sub GPR:$c, (mul GPR:$a, GPR:$b)))]>;
465 // FIXME: SMULL, etc.
467 //===----------------------------------------------------------------------===//
468 // Misc. Arithmetic Instructions.
474 // FIXME not firing? but ARM version does...
475 def t2CLZ : T2I<(outs GPR:$dst), (ins GPR:$src),
476 "clz", " $dst, $src",
477 [(set GPR:$dst, (ctlz GPR:$src))]>;
479 def t2REV : T2I<(outs GPR:$dst), (ins GPR:$src),
480 "rev", " $dst, $src",
481 [(set GPR:$dst, (bswap GPR:$src))]>;
483 def t2REV16 : T2I<(outs GPR:$dst), (ins GPR:$src),
484 "rev16", " $dst, $src",
486 (or (and (srl GPR:$src, (i32 8)), 0xFF),
487 (or (and (shl GPR:$src, (i32 8)), 0xFF00),
488 (or (and (srl GPR:$src, (i32 8)), 0xFF0000),
489 (and (shl GPR:$src, (i32 8)), 0xFF000000)))))]>;
494 def t2REVSH : T2I<(outs GPR:$dst), (ins GPR:$src),
495 "revsh", " $dst, $src",
498 (or (srl (and GPR:$src, 0xFFFF), (i32 8)),
499 (shl GPR:$src, (i32 8))), i16))]>;
503 //===----------------------------------------------------------------------===//
504 // Comparison Instructions...
507 defm t2CMP : T2I_cmp_is<"cmp",
508 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
509 defm t2CMPnz : T2I_cmp_is<"cmp",
510 BinOpFrag<(ARMcmpNZ node:$LHS, node:$RHS)>>;
512 defm t2CMN : T2I_cmp_is<"cmn",
513 BinOpFrag<(ARMcmp node:$LHS,(ineg node:$RHS))>>;
514 defm t2CMNnz : T2I_cmp_is<"cmn",
515 BinOpFrag<(ARMcmpNZ node:$LHS,(ineg node:$RHS))>>;
517 def : Thumb2Pat<(ARMcmp GPR:$src, t2_so_imm_neg:$imm),
518 (t2CMNri GPR:$src, t2_so_imm_neg:$imm)>;
520 def : Thumb2Pat<(ARMcmpNZ GPR:$src, t2_so_imm_neg:$imm),
521 (t2CMNri GPR:$src, t2_so_imm_neg:$imm)>;
523 // FIXME: TST, TEQ, etc.
525 // A8.6.27 CBNZ, CBZ - Compare and branch on (non)zero.
526 // Short range conditional branch. Looks awesome for loops. Need to figure
527 // out how to use this one.
529 // FIXME: Conditional moves
532 //===----------------------------------------------------------------------===//
533 // Non-Instruction Patterns
536 // ConstantPool, GlobalAddress, and JumpTable
537 def : Thumb2Pat<(ARMWrapper tglobaladdr :$dst), (t2LEApcrel tglobaladdr :$dst)>;
538 def : Thumb2Pat<(ARMWrapper tconstpool :$dst), (t2LEApcrel tconstpool :$dst)>;
539 def : Thumb2Pat<(ARMWrapperJT tjumptable:$dst, imm:$id),
540 (t2LEApcrelJT tjumptable:$dst, imm:$id)>;
542 // Large immediate handling.
544 def : Thumb2Pat<(i32 imm:$src),
545 (t2MOVTi16 (t2MOVi16 (t2_lo16 imm:$src)),
546 (t2_hi16 imm:$src))>;